├── proj ├── lattice │ ├── include │ │ └── scripts │ │ │ ├── IspXCF.dtd │ │ │ ├── diamond_path.mk │ │ │ ├── ft231x.ocd │ │ │ ├── ft232r.ocd │ │ │ ├── ecp5-ocd.sh │ │ │ ├── ft2232.ocd │ │ │ ├── ft231x2.ocd │ │ │ ├── ft4232.ocd │ │ │ ├── trellis_path.mk │ │ │ ├── project.ldf │ │ │ ├── ulx3s_sram.xcf │ │ │ ├── xcf.xsl │ │ │ ├── ulx3s_flash_is25lp032d.xcf │ │ │ ├── ulx3s_flash_s25fl164k.xcf │ │ │ └── ulx3s_flash_is25lp128f.xcf │ ├── ulx3s │ │ ├── universal_make_usbjoy │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── makefile.diamond │ │ │ └── files.mk │ │ └── universal_make_ps2kbd │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ └── files.mk │ ├── fleafpga-ohm-ps2kbd │ │ ├── fleafpga-ohm-kbd-flash.svf │ │ ├── fleafpga-ohm-kbd-flash.vme │ │ ├── fleafpga-ohm-kbd-sram.svf │ │ ├── fleafpga-ohm-kbd-sram.vme │ │ ├── fleafpga_ohm_sram.xcf │ │ ├── fleafpga_ohm_flash.xcf │ │ ├── clocks │ │ │ └── clk_25M_150Mp_150Mn.vhd │ │ └── Makefile │ ├── fleafpga-ohm-usbjoy │ │ ├── fleafpga-ohm-joy-flash.svf │ │ ├── fleafpga-ohm-joy-flash.vme │ │ ├── fleafpga-ohm-joy-sram.svf │ │ ├── fleafpga-ohm-joy-sram.vme │ │ ├── fleafpga_ohm_sram.xcf │ │ ├── fleafpga_ohm_flash.xcf │ │ ├── clocks │ │ │ └── clk_25M_150Mp_150Mn.vhd │ │ └── Makefile │ ├── programmer │ │ ├── openocd │ │ │ ├── ulx3s │ │ │ │ ├── fix_flash_is25lp128f.sed │ │ │ │ ├── ft2232-fpu1.ocd │ │ │ │ ├── ft231x.ocd │ │ │ │ ├── ecp5-25f.ocd │ │ │ │ ├── ecp5-45f.ocd │ │ │ │ ├── ecp5-85f.ocd │ │ │ │ └── ecp5-12f.ocd │ │ │ ├── kondor_ax │ │ │ │ ├── remote.ocd │ │ │ │ ├── ft2232-fpu1.ocd │ │ │ │ ├── ft2232-kondor-ax.ocd │ │ │ │ └── ecp5.ocd │ │ │ ├── sparrowhawk │ │ │ │ ├── remote.ocd │ │ │ │ ├── ft2232-fpu1.ocd │ │ │ │ ├── ecp3.ocd │ │ │ │ ├── pinout.txt │ │ │ │ ├── svf_patch.diff │ │ │ │ └── README.md │ │ │ ├── fleafpga_uno │ │ │ │ ├── machxo2.ocd │ │ │ │ └── ft230x.ocd │ │ │ └── ulx2s │ │ │ │ ├── fx2.ocd │ │ │ │ └── ft232r.ocd │ │ └── ispvm │ │ │ ├── ulx3s_12f_sram.xcf │ │ │ ├── ulx3s_25f_sram.xcf │ │ │ ├── ulx3s_45f_sram.xcf │ │ │ ├── ulx3s_85f_sram.xcf │ │ │ ├── ulx3s_12f_flash_is25lp032d.xcf │ │ │ ├── ulx3s_12f_flash_s25fl164k.xcf │ │ │ ├── ulx3s_25f_flash_is25lp032d.xcf │ │ │ ├── ulx3s_25f_flash_s25fl164k.xcf │ │ │ ├── ulx3s_45f_flash_is25lp032d.xcf │ │ │ ├── ulx3s_45f_flash_s25fl164k.xcf │ │ │ ├── ulx3s_85f_flash_is25lp032d.xcf │ │ │ ├── ulx3s_85f_flash_s25fl164k.xcf │ │ │ ├── ulx3s_12f_flash_is25lp128f.xcf │ │ │ ├── ulx3s_25f_flash_is25lp128f.xcf │ │ │ ├── ulx3s_45f_flash_is25lp128f.xcf │ │ │ └── ulx3s_85f_flash_is25lp128f.xcf │ └── ffm-lfe5-lcdif │ │ └── universal_make_ps2kbd │ │ ├── README.md │ │ ├── makefile │ │ └── files.mk ├── xilinx │ ├── ffm-a7100-lcdif-vivado │ │ ├── amiga_ffm_a7100_lcdif.bit │ │ ├── devlist.txt │ │ ├── cablelist.txt │ │ ├── run_vivado.tcl │ │ └── makefile │ ├── ffm-a7100-lcse-vivado │ │ ├── amiga_ffm_a7100_lcse.bit │ │ ├── devlist.txt │ │ ├── cablelist.txt │ │ ├── run_vivado.tcl │ │ └── makefile │ ├── ffm-a7100-lcdif-ise │ │ ├── devlist.txt │ │ ├── cablelist.txt │ │ ├── README.md │ │ ├── programmer │ │ │ ├── bit2svf.ut │ │ │ ├── bit2xsvf.ut │ │ │ ├── bscan_xc6s_ftg256_blink.bit.xz │ │ │ ├── ft2232-generic.ocd │ │ │ └── miniSpartan6-plus.ocd │ │ ├── xilinx.opt │ │ └── Makefile │ ├── scarab-25k │ │ ├── programmer │ │ │ ├── bit2svf.ut │ │ │ ├── bit2xsvf.ut │ │ │ ├── bscan_xc6s_ftg256_blink.bit.xz │ │ │ ├── ft2232-generic.ocd │ │ │ └── miniSpartan6-plus.ocd │ │ ├── xilinx.opt │ │ ├── scarab.gise │ │ └── Makefile │ └── include │ │ └── vivado.mk └── altera │ ├── ffm-c5a4-sd-lcdif │ ├── altera-usb-blaster.ocd │ ├── ft4232.ocd │ ├── ffm-fpga-c5a4.ocd │ └── Makefile │ ├── ffm-c5a4-sd-lcse │ ├── altera-usb-blaster.ocd │ ├── ft4232.ocd │ ├── ffm-fpga-c5a4.ocd │ └── Makefile │ └── include │ └── quartus_env.sh ├── OSD_CA01.sys ├── Minimig_setup_README.pdf ├── rtl_emard ├── sdram │ └── sdram.vhd ├── tools │ ├── hex2vhdl.sh │ └── jbboot_bin2vhdl.py ├── usb │ ├── usbhost │ │ ├── todo.txt │ │ ├── usbh_crc5.v │ │ └── usbh_crc16.v │ └── usbhid │ │ └── report_decoded_pack_generic.vhd ├── vga │ ├── lattice │ │ ├── ecp5u │ │ │ └── ddr_out_emard.vhd │ │ └── xo2 │ │ │ └── ddr_out.vhd │ ├── generic │ │ └── ddr_out_emard.vhd │ ├── xilinx │ │ ├── xc6 │ │ │ ├── ddr_out.vhd │ │ │ └── hdmi_out_xc6.vhd │ │ └── xc7 │ │ │ ├── ddr_out.vhd │ │ │ └── hdmi_out_xc7.vhd │ ├── hdmi-audio │ │ ├── hdmidelay.vhd │ │ └── serializer_generic.vhd │ ├── hdmi │ │ └── ddr_dvid_out_se.vhd │ └── hdmi_out.vhd ├── lattice │ └── ulx3s │ │ └── clocks │ │ ├── clk_sys_vhdl.vhd │ │ ├── clk_usb_vhdl.vhd │ │ ├── clk_minimig_vhdl.vhd │ │ ├── clk_ramusb_vhdl.vhd │ │ └── DVI_PLL.vhd ├── generic │ └── bram_true2p_1clk.vhd └── osd │ └── osd.vhd ├── Minimig_ECS_Flash_Era_Prgm.vme ├── Minimig_ECS_Diamond_Project.zip ├── source_emard ├── README.md └── poweronreset.vhd ├── .gitattributes ├── unzip_clean_generic.sh ├── .gitignore └── README.md /proj/lattice/include/scripts/IspXCF.dtd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /proj/lattice/ulx3s/universal_make_usbjoy/Makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /OSD_CA01.sys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/Minimig_ECS/HEAD/OSD_CA01.sys -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-ps2kbd/fleafpga-ohm-kbd-flash.svf: -------------------------------------------------------------------------------- 1 | project/project_project_flash.svf -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-ps2kbd/fleafpga-ohm-kbd-flash.vme: -------------------------------------------------------------------------------- 1 | project/project_project_flash.vme -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-ps2kbd/fleafpga-ohm-kbd-sram.svf: -------------------------------------------------------------------------------- 1 | project/project_project_sram.svf -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-ps2kbd/fleafpga-ohm-kbd-sram.vme: -------------------------------------------------------------------------------- 1 | project/project_project_sram.vme -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-usbjoy/fleafpga-ohm-joy-flash.svf: -------------------------------------------------------------------------------- 1 | project/project_project_flash.svf -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-usbjoy/fleafpga-ohm-joy-flash.vme: -------------------------------------------------------------------------------- 1 | project/project_project_flash.vme -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-usbjoy/fleafpga-ohm-joy-sram.svf: -------------------------------------------------------------------------------- 1 | project/project_project_sram.svf -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-usbjoy/fleafpga-ohm-joy-sram.vme: -------------------------------------------------------------------------------- 1 | project/project_project_sram.vme -------------------------------------------------------------------------------- /Minimig_setup_README.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/Minimig_ECS/HEAD/Minimig_setup_README.pdf -------------------------------------------------------------------------------- /rtl_emard/sdram/sdram.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/Minimig_ECS/HEAD/rtl_emard/sdram/sdram.vhd -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-vivado/amiga_ffm_a7100_lcdif.bit: -------------------------------------------------------------------------------- 1 | amiga_ffm_a7100.runs/impl_1/amiga_ffm_a7100.bit -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcse-vivado/amiga_ffm_a7100_lcse.bit: -------------------------------------------------------------------------------- 1 | amiga_ffm_a7100.runs/impl_1/amiga_ffm_a7100.bit -------------------------------------------------------------------------------- /Minimig_ECS_Flash_Era_Prgm.vme: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/Minimig_ECS/HEAD/Minimig_ECS_Flash_Era_Prgm.vme -------------------------------------------------------------------------------- /Minimig_ECS_Diamond_Project.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/Minimig_ECS/HEAD/Minimig_ECS_Diamond_Project.zip -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx3s/fix_flash_is25lp128f.sed: -------------------------------------------------------------------------------- 1 | s/RUNTEST DRPAUSE 2.50E+00 SEC/RUNTEST DRPAUSE 2.50E-01 SEC/g 2 | -------------------------------------------------------------------------------- /source_emard/README.md: -------------------------------------------------------------------------------- 1 | # adaptation 2 | 3 | Keyboard without driving LEDs 4 | 5 | Modules minimally modified to instantiate generic RAM/ROM 6 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/devlist.txt: -------------------------------------------------------------------------------- 1 | # IDCODE IR_len ID_Cmd Text 2 | 03631093 6 0x0009 XA7A100T 3 | 3f0f0f0f 4 0x0000 AT91SAM7SX 4 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-vivado/devlist.txt: -------------------------------------------------------------------------------- 1 | # IDCODE IR_len ID_Cmd Text 2 | 03631093 6 0x0009 XA7A100T 3 | 3f0f0f0f 4 0x0000 AT91SAM7SX 4 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcse-vivado/devlist.txt: -------------------------------------------------------------------------------- 1 | # IDCODE IR_len ID_Cmd Text 2 | 03631093 6 0x0009 XA7A100T 3 | 3f0f0f0f 4 0x0000 AT91SAM7SX 4 | -------------------------------------------------------------------------------- /proj/altera/ffm-c5a4-sd-lcdif/altera-usb-blaster.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Altera USB-Blaster II 3 | # 4 | 5 | interface usb_blaster 6 | usb_blaster_lowlevel_driver ftdi 7 | -------------------------------------------------------------------------------- /proj/altera/ffm-c5a4-sd-lcse/altera-usb-blaster.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Altera USB-Blaster II 3 | # 4 | 5 | interface usb_blaster 6 | usb_blaster_lowlevel_driver ftdi 7 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/cablelist.txt: -------------------------------------------------------------------------------- 1 | ft4232h ftdi 1500000 0x0403:0x6011: 2 | ft4232h_fast ftdi 30000000 0x0403:0x6011: 3 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-vivado/cablelist.txt: -------------------------------------------------------------------------------- 1 | ft4232h ftdi 1500000 0x0403:0x6011: 2 | ft4232h_fast ftdi 30000000 0x0403:0x6011: 3 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcse-vivado/cablelist.txt: -------------------------------------------------------------------------------- 1 | ft4232h ftdi 1500000 0x0403:0x6011: 2 | ft4232h_fast ftdi 30000000 0x0403:0x6011: 3 | -------------------------------------------------------------------------------- /proj/xilinx/scarab-25k/programmer/bit2svf.ut: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port svf -file "default.svf" 3 | addDevice -p 1 -file "default.bit" 4 | Program -p 1 5 | exit 6 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/README.md: -------------------------------------------------------------------------------- 1 | # Snake for Artix-7 compiled with ISE 2 | 3 | Video works but reset_n must be tied to '1' otherwise 4 | snake is unroutable. 5 | -------------------------------------------------------------------------------- /proj/xilinx/scarab-25k/programmer/bit2xsvf.ut: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port xsvf -file "default.xsvf" 3 | addDevice -p 1 -file "default.bit" 4 | Program -p 1 5 | exit 6 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/programmer/bit2svf.ut: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port svf -file "default.svf" 3 | addDevice -p 1 -file "default.bit" 4 | Program -p 1 5 | exit 6 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/programmer/bit2xsvf.ut: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port xsvf -file "default.xsvf" 3 | addDevice -p 1 -file "default.bit" 4 | Program -p 1 5 | exit 6 | -------------------------------------------------------------------------------- /proj/xilinx/scarab-25k/programmer/bscan_xc6s_ftg256_blink.bit.xz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/Minimig_ECS/HEAD/proj/xilinx/scarab-25k/programmer/bscan_xc6s_ftg256_blink.bit.xz -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/programmer/bscan_xc6s_ftg256_blink.bit.xz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/Minimig_ECS/HEAD/proj/xilinx/ffm-a7100-lcdif-ise/programmer/bscan_xc6s_ftg256_blink.bit.xz -------------------------------------------------------------------------------- /proj/altera/ffm-c5a4-sd-lcse/ft4232.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Onboard JTAG Programmer 3 | # 4 | 5 | interface ftdi 6 | ftdi_device_desc "Quad RS232-HS" 7 | ftdi_vid_pid 0x0403 0x6011 8 | ftdi_layout_init 0x3088 0x1f8b 9 | -------------------------------------------------------------------------------- /proj/altera/ffm-c5a4-sd-lcdif/ft4232.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Onboard JTAG Programmer 3 | # 4 | 5 | interface ftdi 6 | ftdi_device_desc "Quad RS232-HS" 7 | ftdi_vid_pid 0x0403 0x6011 8 | ftdi_layout_init 0x3088 0x1f8b 9 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/kondor_ax/remote.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Remote bitbang programmer 3 | # 4 | 5 | interface remote_bitbang 6 | remote_bitbang_host jtag.lan 7 | remote_bitbang_port 3335 8 | adapter_khz 1000 9 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/sparrowhawk/remote.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Remote bitbang programmer 3 | # 4 | 5 | interface remote_bitbang 6 | remote_bitbang_host jtag.lan 7 | remote_bitbang_port 3335 8 | adapter_khz 1000 9 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/diamond_path.mk: -------------------------------------------------------------------------------- 1 | # the path of your diamond installation 2 | DIAMOND_BASE ?= /usr/local/diamond 3 | 4 | # it is a directory that looks like this: 5 | # ls /usr/local/diamond 6 | # 3.7_x64 7 | -------------------------------------------------------------------------------- /proj/xilinx/scarab-25k/programmer/ft2232-generic.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # PLDkit FPU1 JTAG Programmer 3 | # 4 | 5 | interface ftdi 6 | ftdi_device_desc "Dual RS232-HS" 7 | ftdi_vid_pid 0x0403 0x6010 8 | ftdi_layout_init 0x3088 0x1f8b 9 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/programmer/ft2232-generic.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # PLDkit FPU1 JTAG Programmer 3 | # 4 | 5 | interface ftdi 6 | ftdi_device_desc "Dual RS232-HS" 7 | ftdi_vid_pid 0x0403 0x6010 8 | ftdi_layout_init 0x3088 0x1f8b 9 | -------------------------------------------------------------------------------- /proj/altera/include/quartus_env.sh: -------------------------------------------------------------------------------- 1 | ALTERAPATH=/opt/altera/quartus2/13.0sp1 2 | 3 | if [ -d ${ALTERAPATH}/quartus/bin/ ] ; then 4 | export PATH=${ALTERAPATH}/quartus/bin/:"${PATH}" 5 | export QSYS_ROOTDIR="${ALTERAPATH}/quartus/sopc_builder/bin" 6 | fi 7 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx3s/ft2232-fpu1.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # PLDkit FPU1 JTAG Programmer 3 | # 4 | 5 | interface ftdi 6 | ftdi_device_desc "FPU1 JTAG Programmer" 7 | ftdi_vid_pid 0x0403 0x6010 8 | ftdi_layout_init 0x3088 0x1f8b 9 | adapter_khz 25000 10 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/kondor_ax/ft2232-fpu1.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # PLDkit FPU1 JTAG Programmer 3 | # 4 | 5 | interface ftdi 6 | ftdi_device_desc "FPU1 JTAG Programmer" 7 | ftdi_vid_pid 0x0403 0x6010 8 | ftdi_layout_init 0x3088 0x1f8b 9 | adapter_khz 25000 10 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/sparrowhawk/ft2232-fpu1.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # PLDkit FPU1 JTAG Programmer 3 | # 4 | 5 | interface ftdi 6 | ftdi_device_desc "FPU1 JTAG Programmer" 7 | ftdi_vid_pid 0x0403 0x6010 8 | ftdi_layout_init 0x3088 0x1f8b 9 | adapter_khz 25000 10 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/kondor_ax/ft2232-kondor-ax.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Kondor-AX USB-JTAG Onboard Programmer 3 | # 4 | 5 | interface ftdi 6 | ftdi_device_desc "Dual RS232-HS" 7 | ftdi_vid_pid 0x0403 0x6010 8 | ftdi_layout_init 0x3088 0x1f8b 9 | adapter_khz 25000 10 | -------------------------------------------------------------------------------- /rtl_emard/tools/hex2vhdl.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | objcopy -I ihex $1 -O binary /tmp/hex2vhdl.bin 3 | cat rom_c1541_head.vhd 4 | dd bs=512 if=/tmp/hex2vhdl.bin conv=sync \ 5 | | hexdump -v -e '8/1 "x_%02X_, ""\n"' \ 6 | | sed -e 's/_/"/g' 7 | rm /tmp/hex2vhdl.bin 8 | cat rom_c1541_tail.vhd 9 | -------------------------------------------------------------------------------- /proj/altera/ffm-c5a4-sd-lcdif/ffm-fpga-c5a4.ocd: -------------------------------------------------------------------------------- 1 | # de10lite.ocd 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | adapter_khz 8000 8 | 9 | # JTAG TAPs 10 | jtag newtap ffmc5a4 tap -expected-id 0x02b050dd -irlen 10 11 | 12 | init 13 | scan_chain 14 | svf -tap ffmc5a4.tap project.svf 15 | shutdown 16 | -------------------------------------------------------------------------------- /proj/altera/ffm-c5a4-sd-lcse/ffm-fpga-c5a4.ocd: -------------------------------------------------------------------------------- 1 | # de10lite.ocd 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | adapter_khz 8000 8 | 9 | # JTAG TAPs 10 | jtag newtap ffmc5a4 tap -expected-id 0x02b050dd -irlen 10 11 | 12 | init 13 | scan_chain 14 | svf -tap ffmc5a4.tap project.svf 15 | shutdown 16 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/kondor_ax/ecp5.ocd: -------------------------------------------------------------------------------- 1 | # ecp3.cfg 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | # JTAG TAPs 8 | jtag newtap ecp5 tap -expected-id 0x01113043 -irlen 8 -irmask 0xFF -ircapture 0x5 9 | 10 | init 11 | scan_chain 12 | svf -tap ecp5.tap project/project_project_sram.svf 13 | shutdown 14 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/sparrowhawk/ecp3.ocd: -------------------------------------------------------------------------------- 1 | # ecp3.cfg 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | # JTAG TAPs 8 | jtag newtap ecp3 tap -expected-id 0x01015043 -irlen 8 -irmask 0xFF -ircapture 0x19 9 | 10 | init 11 | scan_chain 12 | svf -tap ecp3.tap project/project_project_sram.svf 13 | shutdown 14 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/fleafpga_uno/machxo2.ocd: -------------------------------------------------------------------------------- 1 | # ecp3.cfg 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | # JTAG TAPs 8 | jtag newtap machxo2 tap -expected-id 0x012bd043 -irlen 8 -irmask 0xFF -ircapture 0x5 9 | 10 | init 11 | scan_chain 12 | svf -tap machxo2.tap project/project_project_sram.svf 13 | shutdown 14 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx2s/fx2.ocd: -------------------------------------------------------------------------------- 1 | # ecp3.cfg 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | # JTAG TAPs 8 | jtag newtap fx2 tap -expected-id 0x0129a043 -irlen 8 -irmask 0xFF -ircapture 0x1d 9 | 10 | init 11 | scan_chain 12 | svf -tap fx2.tap -quiet -progress project/project_project_sram.svf 13 | shutdown 14 | -------------------------------------------------------------------------------- /rtl_emard/usb/usbhost/todo.txt: -------------------------------------------------------------------------------- 1 | [x] device-specific report decoder as separate module 2 | [x] get report with addressed write instead of shifting 3 | [x] test will CRC reject bad data 4 | [x] retry setup packets until ACK is received 5 | [x] limit number of setup retries and detach 6 | [x] send keepalive signals if interval >1 ms (>12 bit) 7 | [x] let SIE handle BUS_RESET 8 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ft231x.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag nums and buffer_size 3 | # 4 | 5 | interface ft232r 6 | ft232r_vid_pid 0x0403 0x6015 7 | # ft232r_serial_desc 123456 8 | ft232r_tck_num DSR 9 | ft232r_tms_num DCD 10 | ft232r_tdi_num RI 11 | ft232r_tdo_num CTS 12 | ft232r_trst_num RTS 13 | ft232r_srst_num DTR 14 | ft232r_restore_serial 0x15 15 | adapter_khz 1000 16 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ft232r.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag nums and buffer_size 3 | # low-cost FT232R board from ebay 4 | 5 | interface ft232r 6 | # ft232r_vid_pid 0x0403 0x6015 7 | # ft232r_serial_desc 250001 8 | ft232r_tck_num DTR 9 | ft232r_tms_num CTS 10 | ft232r_tdi_num TXD 11 | ft232r_tdo_num RXD 12 | ft232r_trst_num DCD 13 | ft232r_srst_num RI 14 | adapter_khz 1000 15 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ecp5-ocd.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # ecp5-ocd.sh 3 | 4 | CHIP_ID=$1 5 | FILE_SVF=$2 6 | 7 | cat << EOF 8 | # OpenOCD commands 9 | 10 | telnet_port 4444 11 | gdb_port 3333 12 | 13 | # JTAG TAPs 14 | jtag newtap lfe5 tap -expected-id ${CHIP_ID} -irlen 8 -irmask 0xFF -ircapture 0x5 15 | 16 | init 17 | scan_chain 18 | svf -tap lfe5.tap -quiet -progress ${FILE_SVF} 19 | shutdown 20 | EOF 21 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx2s/ft232r.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag_gpio and buffer_size 3 | # 4 | 5 | interface ft232r 6 | # ft232r_vid_pid 0x0403 0x6001 7 | ft232r_tms_num RI 8 | ft232r_tdo_num DCD 9 | ft232r_tdi_num CTS 10 | ft232r_tck_num DSR 11 | ft232r_trst_num RTS 12 | ft232r_srst_num DTR 13 | # ft232r_buffer_size 16384 14 | # ft232r_restore_serial 0x0015 15 | adapter_khz 1000 16 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/fleafpga_uno/ft230x.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag_gpio and buffer_size 3 | # 4 | 5 | interface ft232r 6 | ft232r_vid_pid 0x0403 0x6015 7 | ft232r_tms_num 0 8 | # problem: TDO uses CBUS (not bitbang gpio) 9 | ft232r_tdo_num 6 10 | ft232r_tdi_num 2 11 | ft232r_tck_num 3 12 | ft232r_trst_num 4 13 | ft232r_srst_num 5 14 | ft232r_buffer_size 16384 15 | adapter_khz 1000 16 | -------------------------------------------------------------------------------- /proj/xilinx/scarab-25k/programmer/miniSpartan6-plus.ocd: -------------------------------------------------------------------------------- 1 | # xc6slx9.ocd 2 | # OpenOCD commands 3 | 4 | # impact->boundary scan->right click in right window->add xilinx device glue.bit->one step svf 5 | 6 | telnet_port 4444 7 | gdb_port 3333 8 | 9 | adapter_khz 1000 10 | 11 | # JTAG TAPs 12 | jtag newtap xc6slx25 tap -expected-id 0x24004093 -irlen 6 13 | 14 | init 15 | scan_chain 16 | svf -tap xc6slx25.tap miniSpartan6-plus.svf 17 | shutdown 18 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/programmer/miniSpartan6-plus.ocd: -------------------------------------------------------------------------------- 1 | # xc6slx9.ocd 2 | # OpenOCD commands 3 | 4 | # impact->boundary scan->right click in right window->add xilinx device glue.bit->one step svf 5 | 6 | telnet_port 4444 7 | gdb_port 3333 8 | 9 | adapter_khz 1000 10 | 11 | # JTAG TAPs 12 | jtag newtap xc6slx25 tap -expected-id 0x24004093 -irlen 6 13 | 14 | init 15 | scan_chain 16 | svf -tap xc6slx25.tap miniSpartan6-plus.svf 17 | shutdown 18 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | 7 | # Standard to msysgit 8 | *.doc diff=astextplain 9 | *.DOC diff=astextplain 10 | *.docx diff=astextplain 11 | *.DOCX diff=astextplain 12 | *.dot diff=astextplain 13 | *.DOT diff=astextplain 14 | *.pdf diff=astextplain 15 | *.PDF diff=astextplain 16 | *.rtf diff=astextplain 17 | *.RTF diff=astextplain 18 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ft2232.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Generic FT2232H JTAG Programmer 3 | # 4 | 5 | 6 | interface ftdi 7 | # ftdi_device_desc "Dual RS232-HS" 8 | ftdi_vid_pid 0x0403 0x6010 9 | ftdi_layout_init 0x3088 0x1f8b 10 | 11 | # default is port A if unspecified 12 | # pinout ADBUS 0-TCK 1-TDI 2-TDO 3-TMS 13 | #ftdi_channel 0 14 | 15 | # uncomment this to use port B 16 | # pinout BDBUS 0-TCK 1-TDI 2-TDO 3-TMS 17 | #ftdi_channel 1 18 | 19 | adapter_khz 25000 20 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ft231x2.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag nums and buffer_size 3 | # pinout for ulx3s jtag-thru: 4 | 5 | # GP14 TMS 6 | # GN14 TDO 7 | # GP15 TDI 8 | # GN15 TCK 9 | 10 | interface ft232r 11 | ft232r_vid_pid 0x0403 0x6015 12 | # ft232r_serial_desc 250001 13 | ft232r_tck_num DTR 14 | ft232r_tms_num RTS 15 | ft232r_tdi_num TXD 16 | ft232r_tdo_num RXD 17 | ft232r_trst_num DCD 18 | ft232r_srst_num RI 19 | adapter_khz 1000 20 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ft4232.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Generic FT4232 JTAG Programmer 3 | # 4 | 5 | 6 | interface ftdi 7 | # ftdi_device_desc "Quad RS232-HS" 8 | ftdi_vid_pid 0x0403 0x6011 9 | ftdi_layout_init 0x3088 0x1f8b 10 | 11 | # default is port A if unspecified 12 | # pinout ADBUS 0-TCK 1-TDI 2-TDO 3-TMS 13 | #ftdi_channel 0 14 | 15 | # uncomment this to use port B 16 | # pinout BDBUS 0-TCK 1-TDI 2-TDO 3-TMS 17 | #ftdi_channel 1 18 | 19 | adapter_khz 25000 20 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/trellis_path.mk: -------------------------------------------------------------------------------- 1 | # ******* tools installation paths ******* 2 | # https://github.com/ldoolitt/vhd2vl 3 | VHDL2VL ?= /mt/scratch/tmp/openfpga/vhd2vl/src/vhd2vl 4 | # https://github.com/YosysHQ/yosys 5 | YOSYS ?= /mt/scratch/tmp/openfpga/yosys/yosys 6 | # https://github.com/YosysHQ/nextpnr 7 | NEXTPNR-ECP5 ?= /mt/scratch/tmp/openfpga/nextpnr/nextpnr-ecp5 8 | # https://github.com/SymbiFlow/prjtrellis 9 | TRELLIS ?= /mt/scratch/tmp/openfpga/prjtrellis 10 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx3s/ft231x.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag nums and buffer_size 3 | # 4 | 5 | interface ft232r 6 | ft232r_vid_pid 0x0403 0x6015 7 | # ft232r_serial_desc 123456 8 | # ft232r_jtag_nums DSR DCD RI CTS 9 | ft232r_tck_num DSR 10 | ft232r_tms_num DCD 11 | ft232r_tdi_num RI 12 | ft232r_tdo_num CTS 13 | ft232r_trst_num RTS 14 | ft232r_srst_num DTR 15 | # ft232r_buffer_size 16384 16 | # ft232r_restore_serial 0x0015 17 | adapter_khz 1000 18 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx3s/ecp5-25f.ocd: -------------------------------------------------------------------------------- 1 | # ecp3.cfg 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | # JTAG TAPs 8 | jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5 9 | #jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5 10 | #jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 11 | 12 | init 13 | scan_chain 14 | svf -tap lfe5u25.tap -quiet -progress project/project_project_sram.svf 15 | shutdown 16 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx3s/ecp5-45f.ocd: -------------------------------------------------------------------------------- 1 | # ecp3.cfg 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | # JTAG TAPs 8 | #jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5 9 | jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5 10 | #jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 11 | 12 | init 13 | scan_chain 14 | svf -tap lfe5u45.tap -quiet -progress project/project_project_sram.svf 15 | shutdown 16 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx3s/ecp5-85f.ocd: -------------------------------------------------------------------------------- 1 | # ecp3.cfg 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | # JTAG TAPs 8 | #jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5 9 | #jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5 10 | jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 11 | 12 | init 13 | scan_chain 14 | svf -tap lfe5u85.tap -quiet -progress project/project_project_sram.svf 15 | shutdown 16 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/ulx3s/ecp5-12f.ocd: -------------------------------------------------------------------------------- 1 | # ecp3.cfg 2 | # OpenOCD commands 3 | 4 | telnet_port 4444 5 | gdb_port 3333 6 | 7 | # JTAG TAPs 8 | jtag newtap lfe5u12 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5 9 | #jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5 10 | #jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5 11 | #jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 12 | 13 | init 14 | scan_chain 15 | svf -tap lfe5u12.tap -quiet -progress project/project_project_sram.svf 16 | shutdown 17 | -------------------------------------------------------------------------------- /proj/lattice/ulx3s/universal_make_ps2kbd/README.md: -------------------------------------------------------------------------------- 1 | # Universal make 2 | 3 | This makefile is recommended as template for all builds from linux. 4 | It uses the same source base for building all bitstream formats for all 5 | boards, all FPGA sizes, all SOCs etc., just by editing simple makefile 6 | which does the magic. 7 | 8 | All project files should be listed in "files.mk" and this file should 9 | be maintained on one place, other derived makefiles should include 10 | "files.mk" from here. 11 | 12 | This makes build workflow significantly faster than maintaining 13 | numerous similar but different projects using diamond GUI alone. 14 | -------------------------------------------------------------------------------- /proj/lattice/ulx3s/universal_make_usbjoy/README.md: -------------------------------------------------------------------------------- 1 | # Universal make 2 | 3 | This makefile is recommended as template for all builds from linux. 4 | It uses the same source base for building all bitstream formats for all 5 | boards, all FPGA sizes, all SOCs etc., just by editing simple makefile 6 | which does the magic. 7 | 8 | All project files should be listed in "files.mk" and this file should 9 | be maintained on one place, other derived makefiles should include 10 | "files.mk" from here. 11 | 12 | This makes build workflow significantly faster than maintaining 13 | numerous similar but different projects using diamond GUI alone. 14 | -------------------------------------------------------------------------------- /proj/lattice/ffm-lfe5-lcdif/universal_make_ps2kbd/README.md: -------------------------------------------------------------------------------- 1 | # Universal make 2 | 3 | This makefile is recommended as template for all builds from linux. 4 | It uses the same source base for building all bitstream formats for all 5 | boards, all FPGA sizes, all SOCs etc., just by editing simple makefile 6 | which does the magic. 7 | 8 | All project files should be listed in "files.mk" and this file should 9 | be maintained on one place, other derived makefiles should include 10 | "files.mk" from here. 11 | 12 | This makes build workflow significantly faster than maintaining 13 | numerous similar but different projects using diamond GUI alone. 14 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/project.ldf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /unzip_clean_generic.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | rm -rf Minimig_ECS 3 | unzip -o Minimig_ECS_Diamond_Project.zip 4 | rm -f Minimig_ECS_Flash_Era_Prgm.vme 5 | cd Minimig_ECS 6 | rm -rf sin_table hdmi_upscale_buffer Cache_BlockRAM JBBoot OSDBootstrap Cache_DataRAM ddr_out flash_config.xcf Minimig_tcl.html Minimig_tcr.dir promote.xml reportview.xml sram_config-SPI_Flash_Era_Prgm.vme test.tpf ttt.txt Untitled.tpf 7 | cd impl1 8 | rm -rf ._Real_._Math_.vhd .build_status backup coreip dm hdla_gen_hierarchy.html Minimig_impl1.bit Minimig_impl1.dir Minimig_impl1_summary.html synlog syntmp synwork 9 | rm -rf source/TG68_old 10 | cd ../.. 11 | rtl_emard/tools/jbboot_bin2vhdl.py Minimig_ECS/BOOTROM1/amigaboot.bin jbboot.vhd 12 | rtl_emard/tools/osdbootstrap_bin2vhdl.py Minimig_ECS/BOOTROM1/osdload.bin osd_bootstrap.vhd 13 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Windows image file caches 2 | Thumbs.db 3 | ehthumbs.db 4 | 5 | # Folder config file 6 | Desktop.ini 7 | 8 | # Recycle Bin used on file shares 9 | $RECYCLE.BIN/ 10 | 11 | # Windows Installer files 12 | *.cab 13 | *.msi 14 | *.msm 15 | *.msp 16 | 17 | # Windows shortcuts 18 | *.lnk 19 | 20 | # ========================= 21 | # Operating System Files 22 | # ========================= 23 | 24 | # OSX 25 | # ========================= 26 | 27 | .DS_Store 28 | .AppleDouble 29 | .LSOverride 30 | 31 | # Thumbnails 32 | ._* 33 | 34 | # Files that might appear in the root of a volume 35 | .DocumentRevisions-V100 36 | .fseventsd 37 | .Spotlight-V100 38 | .TemporaryItems 39 | .Trashes 40 | .VolumeIcon.icns 41 | 42 | # Directories potentially created on remote AFP share 43 | .AppleDB 44 | .AppleDesktop 45 | Network Trash Folder 46 | Temporary Items 47 | .apdisk 48 | -------------------------------------------------------------------------------- /rtl_emard/vga/lattice/ecp5u/ddr_out_emard.vhd: -------------------------------------------------------------------------------- 1 | -- Emard 2 | -- LICENSE=BSD 3 | 4 | library IEEE; 5 | use IEEE.std_logic_1164.all; 6 | library ecp5u; 7 | use ecp5u.components.all; 8 | 9 | entity ddr_out_emard is 10 | port 11 | ( 12 | iclkp: in std_logic; 13 | iclkn: in std_logic; 14 | ireset: in std_logic; 15 | idata: in std_logic_vector(1 downto 0); 16 | odata: out std_logic 17 | ); 18 | end ddr_out_emard; 19 | 20 | architecture Structure of ddr_out_emard is 21 | -- local component declarations 22 | component ODDRX1F 23 | port (D0: in std_logic; D1: in std_logic; SCLK: in std_logic; 24 | RST: in std_logic; Q: out std_logic); 25 | end component; 26 | begin 27 | ddr_module: ODDRX1F 28 | port map (D0=>idata(0), D1=>idata(1), SCLK=>iclkp, RST=>ireset, 29 | Q=>odata); 30 | end Structure; 31 | -------------------------------------------------------------------------------- /rtl_emard/lattice/ulx3s/clocks/clk_sys_vhdl.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- AUTHOR=EMARD 3 | -- LICENSE=BSD 4 | -- 5 | 6 | -- VHDL Wrapper 7 | 8 | LIBRARY ieee; 9 | USE ieee.std_logic_1164.all; 10 | use ieee.std_logic_unsigned.all; 11 | use ieee.std_logic_arith.all; 12 | 13 | entity clk_sys_vhdl is 14 | port 15 | ( 16 | clkin : in std_logic; 17 | clk_25 : out std_logic; 18 | locked : out std_logic 19 | ); 20 | end; 21 | 22 | architecture syn of clk_sys_vhdl is 23 | component clk_sys -- verilog name and its parameters 24 | port 25 | ( 26 | clkin : in std_logic; 27 | clk_25 : out std_logic; 28 | locked : out std_logic 29 | ); 30 | end component; 31 | 32 | begin 33 | clk_sys_v_inst: clk_sys 34 | port map 35 | ( 36 | clkin => clkin, 37 | clk_25 => clk_25, 38 | locked => locked 39 | ); 40 | end syn; 41 | -------------------------------------------------------------------------------- /rtl_emard/vga/generic/ddr_out_emard.vhd: -------------------------------------------------------------------------------- 1 | -- AUTHOR=EMARD 2 | -- LICENSE=BSD 3 | 4 | -- untested attempt to make generic DDR output driver 5 | -- 2 bits parallel are taken as input at rising edge of the clock 6 | -- output serialized bit(0) first, then bit(1) 7 | 8 | library IEEE; 9 | use IEEE.std_logic_1164.all; 10 | 11 | entity ddr_out_emard is 12 | port ( 13 | iclkp: in std_logic; 14 | iclkn: in std_logic; -- not used 15 | ireset: in std_logic; -- not used 16 | idata: in std_logic_vector(1 downto 0); 17 | odata: out std_logic := '0' 18 | ); 19 | end ddr_out_emard; 20 | 21 | architecture Structure of ddr_out_emard is 22 | signal R_idata: std_logic_vector(1 downto 0); 23 | begin 24 | process(iclkp) 25 | begin 26 | if rising_edge(iclkp) then 27 | R_idata <= idata; 28 | end if; 29 | end process; 30 | odata <= R_idata(0) when iclkp='1' else R_idata(1); 31 | end Structure; 32 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/sparrowhawk/pinout.txt: -------------------------------------------------------------------------------- 1 | J15: JTAG Header pinout 2 | 3 | Pin # Description wire ESP-12 WIFI_JTAG 4 | Pin 1 VCC 3.3V red VCC 5 | Pin 2 TDO green GPIO12 6 | Pin 3 TDI blue GPIO13 7 | Pin 4 PROGRAMN 8 | Pin 5 NC 9 | Pin 6 TMS violet GPIO16 10 | Pin 7 GND black GND 11 | Pin 8 TCK yellow GPIO14 12 | Pin 9 DONE 13 | Pin 10 INITN 14 | 15 | WIFI_JTAG connector ESP12 16 | looking at wifi chip metal shield, antenna up 17 | (on RADIONA ESP8266 board: 18 | pin 1 is on opposite side from 6-pin programming female connector) 19 | 20 | essid: jtag 21 | password: 12345678 22 | ip: 192.168.4.1 (jtag.lan) 23 | 24 | 1 RST 25 | 2 ADC 26 | 3 CH_PD 27 | 4 GPIO16 violet TMS 28 | 5 GPIO14 yellow TCK 29 | 6 GPIO12 green TDO 30 | 7 GPIO13 blue TDI 31 | 8 VCC red VCC 32 | 9 GND black GND 33 | 10 GPIO15 34 | 11 GPIO2 35 | 12 GPIO0 36 | 13 GPIO5 37 | 14 GPIO4 38 | 15 RXD 39 | 16 TXD 40 | -------------------------------------------------------------------------------- /source_emard/poweronreset.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_unsigned.all; 4 | use IEEE.numeric_std.ALL; 5 | 6 | entity poweronreset is 7 | port( 8 | clk : in std_logic; 9 | reset_button : in std_logic; 10 | reset_out : out std_logic 11 | ); 12 | end entity; 13 | 14 | architecture rtl of poweronreset is 15 | signal counter : unsigned(16 downto 0):=(others => '0'); 16 | signal resetbutton_debounced : std_logic; 17 | signal powerbutton_debounced : std_logic; 18 | signal power_cut : std_logic; 19 | 20 | begin 21 | mydb : entity work.debounce 22 | port map( 23 | clk=>clk, 24 | signal_in=>reset_button, 25 | signal_out=>resetbutton_debounced 26 | ); 27 | reset_out <= counter(counter'high); 28 | process(clk) 29 | begin 30 | if(rising_edge(clk)) then 31 | if resetbutton_debounced='0' then 32 | counter<=(others => '0'); 33 | elsif counter(counter'high)='1' then 34 | else 35 | counter <= counter+1; 36 | end if; 37 | end if; 38 | end process; 39 | 40 | end architecture; 41 | -------------------------------------------------------------------------------- /proj/lattice/ulx3s/universal_make_usbjoy/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = minimig_usbjoy 3 | BOARD = ulx3s 4 | # 25 45 85 5 | FPGA_SIZE = 25 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* design files ******* 13 | # current boards v3.0.3 v2.1.2 14 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 15 | # first ULX3S prototypes v1.7 boards with patched ESP32 connection 16 | #CONSTRAINTS = ../../constraints/ulx3s_v17p.lpf 17 | 18 | TOP_MODULE_FILE = ../../../../rtl_emard/lattice/ulx3s/top/amiga_ulx3s_usbjoy.vhd 19 | # usually all toplevels have the same top module name 20 | TOP_MODULE = amiga_ulx3s 21 | 22 | include files.mk 23 | 24 | #STRATEGY = ../../../../Minimig_ECS/Area2.sty 25 | STRATEGY = ../../../../Minimig_ECS/Minimig1.sty 26 | 27 | SCRIPTS = ../../include/scripts 28 | include $(SCRIPTS)/trellis_path.mk 29 | include $(SCRIPTS)/diamond_path.mk 30 | include $(SCRIPTS)/diamond_main.mk 31 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/xilinx.opt: -------------------------------------------------------------------------------- 1 | -ifmt mixed 2 | -ofmt NGC 3 | -opt_mode speed 4 | -opt_level 1 5 | -iuc NO 6 | -keep_hierarchy no 7 | -netlist_hierarchy as_optimized 8 | -rtlview no 9 | -glob_opt AllClockNets 10 | -read_cores yes 11 | -write_timing_constraints NO 12 | -cross_clock_analysis NO 13 | -hierarchy_separator / 14 | -bus_delimiter <> 15 | -case maintain 16 | -slice_utilization_ratio 100 17 | -bram_utilization_ratio 100 18 | #-dsp_utilization_ratio 100 19 | -safe_implementation No 20 | -fsm_extract YES 21 | -fsm_encoding Auto 22 | -fsm_style lut 23 | -ram_extract Yes 24 | -ram_style Auto 25 | -rom_extract Yes 26 | -rom_style Auto 27 | -shreg_extract YES 28 | -auto_bram_packing NO 29 | -resource_sharing YES 30 | -async_to_sync NO 31 | #-use_dsp48 auto 32 | -iobuf YES 33 | -max_fanout 500 34 | -register_duplication YES 35 | -register_balancing No 36 | -optimize_primitives NO 37 | -use_clock_enable Auto 38 | -use_sync_set Auto 39 | -use_sync_reset Auto 40 | -iob auto 41 | -equivalent_register_removal YES 42 | -slice_utilization_ratio_maxmargin 5 43 | -use_new_parser yes -------------------------------------------------------------------------------- /rtl_emard/usb/usbhid/report_decoded_pack_generic.vhd: -------------------------------------------------------------------------------- 1 | -- (c) EMARD 2 | -- License=BSD 3 | 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | 7 | package report_decoded_pack is 8 | type T_report_decoded is 9 | record 10 | lstick_x, lstick_y, rstick_x, rstick_y: std_logic_vector(7 downto 0); -- up/left=0 idle=128 down/right=255 11 | lmouseq_x, lmouseq_y, rmouseq_x, rmouseq_y: std_logic_vector(1 downto 0); -- stick to quadrature encoder output 12 | analog_ltrigger, analog_rtrigger: std_logic_vector(7 downto 0); 13 | hat_up, hat_down, hat_left, hat_right: std_logic; 14 | lstick_up, lstick_down, lstick_left, lstick_right: std_logic; 15 | rstick_up, rstick_down, rstick_left, rstick_right: std_logic; 16 | btn_a, btn_b, btn_x, btn_y: std_logic; 17 | btn_lbumper, btn_rbumper: std_logic; 18 | btn_ltrigger, btn_rtrigger: std_logic; 19 | btn_back, btn_start: std_logic; 20 | btn_lstick, btn_rstick: std_logic; 21 | btn_fps, btn_fps_toggle: std_logic; 22 | btn_lmouse_left, btn_lmouse_right: std_logic; 23 | btn_rmouse_left, btn_rmouse_right: std_logic; 24 | end record; 25 | end; 26 | -------------------------------------------------------------------------------- /proj/xilinx/scarab-25k/xilinx.opt: -------------------------------------------------------------------------------- 1 | -ifmt mixed 2 | -ofmt NGC 3 | -opt_mode speed 4 | -opt_level 2 5 | -iuc NO 6 | -keep_hierarchy no 7 | #-netlist_hierarchy as_optimized 8 | -netlist_hierarchy rebuilt 9 | -rtlview no 10 | -glob_opt AllClockNets 11 | -read_cores yes 12 | -write_timing_constraints YES 13 | -cross_clock_analysis NO 14 | -hierarchy_separator / 15 | -bus_delimiter <> 16 | -case maintain 17 | -slice_utilization_ratio 100 18 | -bram_utilization_ratio 100 19 | #-dsp_utilization_ratio 100 20 | -safe_implementation YES 21 | -fsm_extract YES 22 | -fsm_encoding Auto 23 | -fsm_style lut 24 | -ram_extract Yes 25 | -ram_style Auto 26 | -rom_extract Yes 27 | -rom_style Auto 28 | -shreg_extract YES 29 | -auto_bram_packing YES 30 | -resource_sharing YES 31 | -async_to_sync NO 32 | #-use_dsp48 auto 33 | -iobuf YES 34 | -max_fanout 500 35 | -register_duplication YES 36 | -register_balancing YES 37 | -optimize_primitives YES 38 | -use_clock_enable Auto 39 | -use_sync_set Auto 40 | -use_sync_reset Auto 41 | -iob auto 42 | -equivalent_register_removal YES 43 | -slice_utilization_ratio_maxmargin 5 44 | -use_new_parser yes 45 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/sparrowhawk/svf_patch.diff: -------------------------------------------------------------------------------- 1 | --- project/project_project_sram.svf.orig 2016-09-04 11:18:41.791444800 +0200 2 | +++ project/project_project_sram.svf 2016-09-04 11:16:43.418560514 +0200 3 | @@ -46,7 +46,7 @@ STATE IDLE; 4 | 5 | ! Shift in IDCODE(0x16) instruction 6 | SIR 8 TDI (16); 7 | -SDR 32 TDI (FFFFFFFF) 8 | +SDR 32 TDI (01015043) 9 | TDO (01015043) 10 | MASK (FFFFFFFF); 11 | 12 | @@ -95457,6 +95457,13 @@ SIR 8 TDI (17); 13 | SDR 32 TDI (FFFFFFFF) 14 | TDO (00000000); 15 | 16 | +! Verify Status Register 17 | + 18 | +! Shift in LSCC READ STATUS(0x53) instruction 19 | +SIR 8 TDI (53); 20 | +SDR 32 TDI (FFFFFFFF) 21 | + TDO (00020000) 22 | + MASK (00060007); 23 | 24 | ! Exit the programming mode 25 | 26 | @@ -95466,12 +95473,3 @@ RUNTEST IDLE 5 TCK 2,00E-01 SEC; 27 | ! Shift in BYPASS(0xFF) instruction 28 | SIR 8 TDI (FF); 29 | RUNTEST IDLE 100 TCK 1,00E-03 SEC; 30 | - 31 | - 32 | -! Verify Status Register 33 | - 34 | -! Shift in LSCC READ STATUS(0x53) instruction 35 | -SIR 8 TDI (53); 36 | -SDR 32 TDI (FFFFFFFF) 37 | - TDO (00020000) 38 | - MASK (00060007); 39 | -------------------------------------------------------------------------------- /proj/xilinx/include/vivado.mk: -------------------------------------------------------------------------------- 1 | # linux version 2 | vivado ?= /opt/Xilinx/Vivado/2018.1/bin/vivado 3 | # windows version 4 | # vivado ?= /cygdrive/c/Xilinx/Vivado/2015.4/bin/vivado 5 | # basename of the file some_project.xpr 6 | project ?= project 7 | # xc3sprog interface name 8 | xc3sprog_interface ?= ftdi 9 | xc3sprog_device ?= 0 10 | # name of the resulting bitstream file (*.bit) 11 | bitfile?=$(project).runs/impl_1/glue.bit 12 | junk?=junk.log 13 | 14 | build: $(bitfile) 15 | 16 | $(bitfile): clean 17 | # $(vivado) -mode tcl -source run_vivado.tcl -tclargs build 18 | $(vivado) -mode tcl -source run_vivado.tcl -tclargs build -tclargs $(project).xpr 19 | 20 | clean: 21 | # slow and it doesn't clean it all 22 | # $(vivado) -mode tcl -source run_vivado.tcl -tclargs clean 23 | # faster to remove project files 24 | rm -rf *~ vivado.jou vivado.log webtalk* vivado_*.backup.??? 25 | rm -rf $(project).cache $(project).hw $(project).runs 26 | # rm -rf $(project).sim $(project).srcs 27 | rm -rf $(junk) 28 | 29 | program: xc3sprog 30 | 31 | xc3sprog: 32 | xc3sprog -c $(xc3sprog_interface) -p $(xc3sprog_device) $(bitfile) 33 | -------------------------------------------------------------------------------- /rtl_emard/lattice/ulx3s/clocks/clk_usb_vhdl.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- AUTHOR=EMARD 3 | -- LICENSE=BSD 4 | -- 5 | 6 | -- VHDL Wrapper 7 | 8 | LIBRARY ieee; 9 | USE ieee.std_logic_1164.all; 10 | use ieee.std_logic_unsigned.all; 11 | use ieee.std_logic_arith.all; 12 | 13 | entity clk_usb_vhdl is 14 | port 15 | ( 16 | clkin : in std_logic; 17 | clk_240 : out std_logic; 18 | clk_48 : out std_logic; 19 | clk_6 : out std_logic; 20 | locked : out std_logic 21 | ); 22 | end; 23 | 24 | architecture syn of clk_usb_vhdl is 25 | component clk_usb -- verilog name and its parameters 26 | port 27 | ( 28 | clkin : in std_logic; 29 | clk_240 : out std_logic; 30 | clk_48 : out std_logic; 31 | clk_6 : out std_logic; 32 | locked : out std_logic 33 | ); 34 | end component; 35 | 36 | begin 37 | clk_usb_v_inst: clk_usb 38 | port map 39 | ( 40 | clkin => clkin, 41 | clk_240 => clk_240, 42 | clk_48 => clk_48, 43 | clk_6 => clk_6, 44 | locked => locked 45 | ); 46 | end syn; 47 | -------------------------------------------------------------------------------- /rtl_emard/lattice/ulx3s/clocks/clk_minimig_vhdl.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- AUTHOR=EMARD 3 | -- LICENSE=BSD 4 | -- 5 | 6 | -- VHDL Wrapper 7 | 8 | LIBRARY ieee; 9 | USE ieee.std_logic_1164.all; 10 | use ieee.std_logic_unsigned.all; 11 | use ieee.std_logic_arith.all; 12 | 13 | entity clk_minimig_vhdl is 14 | port 15 | ( 16 | clkin : in std_logic; 17 | clk_140 : out std_logic; 18 | clk_112 : out std_logic; 19 | clk_28 : out std_logic; 20 | clk_7 : out std_logic; 21 | locked : out std_logic 22 | ); 23 | end; 24 | 25 | architecture syn of clk_minimig_vhdl is 26 | component clk_minimig -- verilog name and its parameters 27 | port 28 | ( 29 | clkin: in std_logic; 30 | clk_140: out std_logic; 31 | clk_112: out std_logic; 32 | clk_28 : out std_logic; 33 | clk_7 : out std_logic; 34 | locked: out std_logic 35 | ); 36 | end component; 37 | 38 | begin 39 | clk_minimig_cpu_v_inst: clk_minimig 40 | port map 41 | ( 42 | clkin => clkin, 43 | clk_140 => clk_140, 44 | clk_112 => clk_112, 45 | clk_28 => clk_28, 46 | clk_7 => clk_7, 47 | locked => locked 48 | ); 49 | end syn; 50 | -------------------------------------------------------------------------------- /rtl_emard/vga/xilinx/xc6/ddr_out.vhd: -------------------------------------------------------------------------------- 1 | -- Emard 2 | -- LICENSE=BSD 3 | 4 | library IEEE; 5 | use IEEE.std_logic_1164.all; 6 | 7 | library unisim; 8 | use unisim.vcomponents.all; 9 | 10 | entity ddr_out_emard is 11 | port 12 | ( 13 | iclkp: in std_logic; -- normal clock 14 | iclkn: in std_logic; -- inverted clock 15 | ireset: in std_logic := '0'; 16 | idata: in std_logic_vector(1 downto 0); 17 | odata: out std_logic 18 | ); 19 | end; 20 | 21 | -- seems to not work? 22 | -- should OSERDES2 be used insted? 23 | architecture Structure of ddr_out_emard is 24 | begin 25 | ODDR_inst: ODDR2 26 | generic map 27 | ( 28 | DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC" 29 | ) 30 | port map 31 | ( 32 | C0 => iclkp, -- 1-bit clock input 33 | C1 => iclkn, -- 1-bit clock input inverted 34 | CE => '1', -- 1-bit clock enable input 35 | D0 => idata(0), -- 1-bit data input (output at positive edge) 36 | D1 => idata(1), -- 1-bit data input (output at negative edge) 37 | R => ireset, -- 1-bit reset input 38 | S => '0', -- 1-bit set input 39 | Q => odata -- 1-bit DDR output 40 | ); 41 | end Structure; 42 | -------------------------------------------------------------------------------- /rtl_emard/lattice/ulx3s/clocks/clk_ramusb_vhdl.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- AUTHOR=EMARD 3 | -- LICENSE=BSD 4 | -- 5 | 6 | -- VHDL Wrapper 7 | 8 | LIBRARY ieee; 9 | USE ieee.std_logic_1164.all; 10 | use ieee.std_logic_unsigned.all; 11 | use ieee.std_logic_arith.all; 12 | 13 | entity clk_ramusb_vhdl is 14 | port 15 | ( 16 | clkin : in std_logic; 17 | clk_112 : out std_logic; 18 | clk_112_120deg : out std_logic; 19 | clk_6 : out std_logic; 20 | locked : out std_logic 21 | ); 22 | end; 23 | 24 | architecture syn of clk_ramusb_vhdl is 25 | component clk_ramusb -- verilog name and its parameters 26 | port 27 | ( 28 | clkin : in std_logic; 29 | clk_112 : out std_logic; 30 | clk_112_120deg : out std_logic; 31 | clk_6 : out std_logic; 32 | locked : out std_logic 33 | ); 34 | end component; 35 | 36 | begin 37 | clk_ramusb_v_inst: clk_ramusb 38 | port map 39 | ( 40 | clkin => clkin, 41 | clk_112 => clk_112, 42 | clk_112_120deg => clk_112_120deg, 43 | clk_6 => clk_6, 44 | locked => locked 45 | ); 46 | end syn; 47 | -------------------------------------------------------------------------------- /proj/xilinx/scarab-25k/scarab.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /rtl_emard/vga/xilinx/xc7/ddr_out.vhd: -------------------------------------------------------------------------------- 1 | -- Emard 2 | -- LICENSE=BSD 3 | 4 | library IEEE; 5 | use IEEE.std_logic_1164.all; 6 | 7 | library unisim; 8 | use unisim.vcomponents.all; 9 | 10 | entity ddr_out_emard is 11 | port 12 | ( 13 | iclkp: in std_logic; -- only this is used 14 | iclkn: in std_logic := '0'; -- not needed for xilinx 15 | ireset: in std_logic := '0'; 16 | idata: in std_logic_vector(1 downto 0); 17 | odata: out std_logic 18 | ); 19 | end ddr_out_emard; 20 | 21 | architecture Structure of ddr_out_emard is 22 | begin 23 | ODDR_inst: ODDR 24 | generic map 25 | ( 26 | DDR_CLK_EDGE => "SAME_EDGE", -- input sampling: "OPPOSITE_EDGE" or "SAME_EDGE" 27 | INIT => '0', -- Initial value for Q port ('1' or '0') 28 | SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") 29 | ) 30 | port map 31 | ( 32 | C => iclkp, -- 1-bit clock input 33 | CE => '1', -- 1-bit clock enable input 34 | D1 => idata(0), -- 1-bit data input (output at positive edge) 35 | D2 => idata(1), -- 1-bit data input (output at negative edge) 36 | R => ireset, -- 1-bit reset input 37 | S => '0', -- 1-bit set input 38 | Q => odata -- 1-bit DDR output 39 | ); 40 | end Structure; 41 | -------------------------------------------------------------------------------- /rtl_emard/vga/hdmi-audio/hdmidelay.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- (c) 2016 Alexey Spirkov 3 | -- I am happy for anyone to use this for non-commercial use. 4 | -- If my verilog/vhdl/c files are used commercially or otherwise sold, 5 | -- please contact me for explicit permission at me _at_ alsp.net. 6 | -- This applies for source and binary form and derived works. 7 | 8 | library ieee; 9 | use ieee.std_logic_1164.all; 10 | 11 | entity hdmi_delay_line is 12 | generic( 13 | G_WIDTH : integer := 40; 14 | G_DEPTH : integer := 11); 15 | port ( 16 | I_CLK : in std_logic; 17 | I_D : in std_logic_vector(G_WIDTH-1 downto 0); 18 | O_Q : out std_logic_vector(G_WIDTH-1 downto 0)); 19 | end hdmi_delay_line; 20 | 21 | architecture rtl of hdmi_delay_line is 22 | type t_q_pipe is array(0 to G_DEPTH-1) of std_logic_vector(G_WIDTH-1 downto 0); 23 | signal q_pipe : t_q_pipe; 24 | begin 25 | process_pipe : process(i_clk) 26 | begin 27 | if(rising_edge(i_clk)) then 28 | 29 | q_pipe <= I_D&q_pipe(0 to q_pipe'length-2); 30 | 31 | end if; 32 | end process process_pipe; 33 | O_Q <= q_pipe(q_pipe'length-1); 34 | end rtl; 35 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Port of Amiga emulator "Minimig" 2 | 3 | Started from Minimig_ECS for Fleasystems "Ohm" board 4 | and making it more portable to work on Altera, Lattice 5 | and Xilinx. Also used to test compatibility of various 6 | vendors and boards when running a complex project. 7 | 8 | Altera Cyclone-V (5CEBA4F23C7) 9 | Lattice ECP5 (LFE5U-25F-6BG381C and LFE5U-45F-6BG381C) 10 | Xilinx Artix-7 (XC7A100T-FGG484-2) 11 | 12 | Keyboard driver modified not to control keyboard LEDs 13 | to avoid compatibility issues with various keyboard. 14 | 15 | VGA to HDMI converter is replaced from "snake" template 16 | because original video output didn't make monitor sync. 17 | New video doesn't have hdmi-audio. 18 | 19 | Except clock PLL generators, most (if not all) vendor specific 20 | RAM/ROMs are converted to generic vhdl with python scripts 21 | and other modules slightly adjusted to use new generic modules. 22 | 23 | There is a script which unzips original archive, removes 24 | unneed files and converts some binaries to generic vhdl. 25 | 26 | # SD browser menu 27 | 28 | Press all 4 cursor buttons together at the same time and 29 | Minimig menu will appear where you can browse SD card to 30 | load *.adf files and change Minimig emulation parameters. 31 | 32 | OSD menu is running on auxililary 68k CPU. It's source is here: 33 | [minimig_tc64](https://github.com/robinsonb5/minimig_tc64) 34 | -------------------------------------------------------------------------------- /proj/lattice/programmer/openocd/sparrowhawk/README.md: -------------------------------------------------------------------------------- 1 | # JTAG programming on linux 2 | 3 | Connect any ft2232 cable to JTAG 4 | run this (it may even work). 5 | 6 | make program_ft2232 7 | 8 | Even if it doesn't work, it will alter some 9 | ft2232 status so from then on, this may work: 10 | 11 | make program 12 | 13 | Or programming from diamond GUI may work: 14 | Tools->Programmer, detect cable, click on icon "program"... 15 | 16 | # JTAG pinout 17 | 18 | Connect JTAG programmer to 1x10-pin male header J15: 19 | 20 | J15: JTAG Header wire ESP-12 WIFI_JTAG 21 | ---------------- ---- ---------------- 22 | Pin 1 VCC 3.3V red VCC 23 | Pin 2 TDO green GPIO12 24 | Pin 3 TDI blue GPIO13 25 | Pin 4 PROGRAMN 26 | Pin 5 NC 27 | Pin 6 TMS violet GPIO16 28 | Pin 7 GND black GND 29 | Pin 8 TCK yellow GPIO14 30 | Pin 9 DONE 31 | Pin 10 INITN 32 | 33 | Note: wifi_jtag doesn't work. It will display chip ID 34 | run upload, and report failure status and bitstream will not work. 35 | Probably it uploads too slow. 36 | 37 | # ft2232 and openocd 38 | 39 | The make command will generate and patch *.svf bitstream file 40 | for programming with external tools like openocd. 41 | 42 | "make program_ft2232" will attempt to upload generated *.svf 43 | file to FPGA with openocd. This upload is temporary (to SRAM of FPGA) 44 | and is active as long as FPGA board power is ON. 45 | 46 | However, openocd will change something to ft2232 cable and/or linux kernel 47 | so from then on (while ft2232 USB cable is plugged in PC), the cable will be 48 | recognized by diamond internal programmer. 49 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ulx3s_sram.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-25F 13 | 0x41111043 14 | All 15 | LFE5U-25F 16 | 17 | 8 18 | 11111111 19 | 1 20 | 0 21 | 22 | project/project_project.bit 23 | Fast Program 24 | 32 | 33 | 34 | 35 | SEQUENTIAL 36 | ENTIRED CHAIN 37 | No Override 38 | TLR 39 | TLR 40 | 41 | 1 42 | 43 | 44 | USB2 45 | FTUSB-0 46 | DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A 47 | 48 | 49 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_12f_sram.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-12F 13 | 0x21111043 14 | All 15 | LFE5U-12F 16 | 17 | 8 18 | 11111111 19 | 1 20 | 0 21 | 22 | project/project_project.bit 23 | Fast Program 24 | 32 | 33 | 34 | 35 | SEQUENTIAL 36 | ENTIRED CHAIN 37 | No Override 38 | TLR 39 | TLR 40 | 41 | 1 42 | 43 | 44 | USB2 45 | FTUSB-0 46 | DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A 47 | 48 | 49 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_25f_sram.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-25F 13 | 0x41111043 14 | All 15 | LFE5U-25F 16 | 17 | 8 18 | 11111111 19 | 1 20 | 0 21 | 22 | project/project_project.bit 23 | Fast Program 24 | 32 | 33 | 34 | 35 | SEQUENTIAL 36 | ENTIRED CHAIN 37 | No Override 38 | TLR 39 | TLR 40 | 41 | 1 42 | 43 | 44 | USB2 45 | FTUSB-0 46 | DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A 47 | 48 | 49 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_45f_sram.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-45F 13 | 0x41112043 14 | All 15 | LFE5U-45F 16 | 17 | 8 18 | 11111111 19 | 1 20 | 0 21 | 22 | project/project_project.bit 23 | Fast Program 24 | 32 | 33 | 34 | 35 | SEQUENTIAL 36 | ENTIRED CHAIN 37 | No Override 38 | TLR 39 | TLR 40 | 41 | 1 42 | 43 | 44 | USB2 45 | FTUSB-0 46 | DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A 47 | 48 | 49 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_85f_sram.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-85F 13 | 0x41113043 14 | All 15 | LFE5U-85F 16 | 17 | 8 18 | 11111111 19 | 1 20 | 0 21 | 22 | project/project_project.bit 23 | Fast Program 24 | 32 | 33 | 34 | 35 | SEQUENTIAL 36 | ENTIRED CHAIN 37 | No Override 38 | TLR 39 | TLR 40 | 41 | 1 42 | 43 | 44 | USB2 45 | FTUSB-0 46 | DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A 47 | 48 | 49 | -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-ps2kbd/fleafpga_ohm_sram.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5UM 12 | LFE5U-25F 13 | 0x41111043 14 | All 15 | LFE5U-25F 16 | 17 | 8 18 | 11111111 19 | 1 20 | 0 21 | 22 | project/project_project.bit 23 | Fast Program 24 | 32 | 33 | 34 | 35 | SEQUENTIAL 36 | ENTIRED CHAIN 37 | No Override 38 | TLR 39 | TLR 40 | 41 | 1 42 | 43 | 44 | USB2 45 | FTUSB-0 46 | DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A 47 | 48 | 49 | -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-usbjoy/fleafpga_ohm_sram.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5UM 12 | LFE5U-25F 13 | 0x41111043 14 | All 15 | LFE5U-25F 16 | 17 | 8 18 | 11111111 19 | 1 20 | 0 21 | 22 | project/project_project.bit 23 | Fast Program 24 | 32 | 33 | 34 | 35 | SEQUENTIAL 36 | ENTIRED CHAIN 37 | No Override 38 | TLR 39 | TLR 40 | 41 | 1 42 | 43 | 44 | USB2 45 | FTUSB-0 46 | DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A 47 | 48 | 49 | -------------------------------------------------------------------------------- /rtl_emard/vga/hdmi/ddr_dvid_out_se.vhd: -------------------------------------------------------------------------------- 1 | -- Emard 2 | -- LICENSE=BSD 3 | -- instantiates vendor specific DDR output buffers 4 | 5 | library IEEE; 6 | use IEEE.STD_LOGIC_1164.ALL; 7 | 8 | entity ddr_dvid_out_se is 9 | Port ( 10 | clk : in STD_LOGIC; -- positive clock 125MHz (phase 0) 11 | clk_n : in STD_LOGIC; -- negative clock 125MHz (phase 180) 12 | -- input hdmi data for DDR out, 2 bits per clock period 13 | in_red : in STD_LOGIC_VECTOR(1 downto 0); 14 | in_green : in STD_LOGIC_VECTOR(1 downto 0); 15 | in_blue : in STD_LOGIC_VECTOR(1 downto 0); 16 | in_clock : in STD_LOGIC_VECTOR(1 downto 0); 17 | -- single-ended DDR out suitable for onboard hardware driver 18 | out_red : out STD_LOGIC; 19 | out_green : out STD_LOGIC; 20 | out_blue : out STD_LOGIC; 21 | out_clock : out STD_LOGIC 22 | ); 23 | end ddr_dvid_out_se; 24 | 25 | architecture Behavioral of ddr_dvid_out_se is 26 | begin 27 | 28 | -- DDR vendor specific primitives 29 | ddr_out_red: entity work.ddr_out_emard 30 | port map 31 | ( 32 | iclkp=>clk, iclkn=>clk_n, ireset=>'0', 33 | idata(1 downto 0)=>in_red(1 downto 0), odata=>out_red 34 | ); 35 | 36 | ddr_out_green: entity work.ddr_out_emard 37 | port map 38 | ( 39 | iclkp=>clk, iclkn=>clk_n, ireset=>'0', 40 | idata(1 downto 0)=>in_green(1 downto 0), odata=>out_green 41 | ); 42 | 43 | ddr_out_blue: entity work.ddr_out_emard 44 | port map 45 | ( 46 | iclkp=>clk, iclkn=>clk_n, ireset=>'0', 47 | idata(1 downto 0)=>in_blue(1 downto 0), odata=>out_blue 48 | ); 49 | 50 | ddr_out_clock: entity work.ddr_out_emard 51 | port map 52 | ( 53 | iclkp=>clk, iclkn=>clk_n, ireset=>'0', 54 | idata(1 downto 0)=>in_clock(1 downto 0), odata=>out_clock 55 | ); 56 | 57 | end Behavioral; 58 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/xcf.xsl: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | -------------------------------------------------------------------------------- /proj/lattice/ulx3s/universal_make_ps2kbd/makefile: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = minimig_ps2kbd 3 | BOARD = ulx3s 4 | # 25 45 85 5 | FPGA_SIZE = 25 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* design files ******* 13 | CLK0_NAME = clk_minimig 14 | CLK0_FILE_NAME = ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK0_NAME).v 15 | CLK0_OPTIONS = \ 16 | --module=$(CLK0_NAME) \ 17 | --clkin=25 \ 18 | --clkout0_name=clk_140 --clkout0=140.625 \ 19 | --clkout1_name=clk_112 --clkout1=112.5 \ 20 | --clkout2_name=clk_28 --clkout2=28.125 \ 21 | --clkout3_name=clk_7 --clkout3=7.03125 22 | 23 | CLK1_NAME = clk_ramusb 24 | CLK1_FILE_NAME = ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK1_NAME).v 25 | CLK1_OPTIONS = \ 26 | --module=$(CLK1_NAME) \ 27 | --clkin=25 \ 28 | --clkout0_name=clk_112 --clkout0=112.5 \ 29 | --clkout1_name=clk_112_120deg --clkout1=112.5 --phase1=120 \ 30 | --clkout2_name=clk_6 --clkout2=6 31 | 32 | CLK2_NAME = clk_usb 33 | CLK2_FILE_NAME = ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK2_NAME).v 34 | CLK2_OPTIONS = \ 35 | --module=$(CLK2_NAME) \ 36 | --clkin=25 \ 37 | --clkout0_name=clk_240 --clkout0=240 \ 38 | --clkout1_name=clk_48 --clkout1=48 \ 39 | --clkout2_name=clk_6 --clkout2=6 40 | 41 | # ******* design files ******* 42 | # current boards v3.0.3 v2.1.2 43 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 44 | # first ULX3S prototypes v1.7 boards with patched ESP32 connection 45 | #CONSTRAINTS = ../../constraints/ulx3s_v17p.lpf 46 | 47 | TOP_MODULE_FILE = ../../../../rtl_emard/lattice/ulx3s/top/amiga_ulx3s_ps2kbd.vhd 48 | # usually all toplevels have the same top module name 49 | TOP_MODULE = amiga_ulx3s 50 | 51 | include files.mk 52 | 53 | #STRATEGY = ../../../../Minimig_ECS/Area2.sty 54 | STRATEGY = ../../../../Minimig_ECS/Minimig1.sty 55 | 56 | SCRIPTS = ../../include/scripts 57 | include $(SCRIPTS)/trellis_path.mk 58 | include $(SCRIPTS)/diamond_path.mk 59 | include $(SCRIPTS)/diamond_main.mk 60 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcse-vivado/run_vivado.tcl: -------------------------------------------------------------------------------- 1 | 2 | #******************************************************************************* 3 | # Simple script to control vivado project via command line 4 | # 5 | # It takes 2 arguments 6 | # arg 1 either. 7 | # clean cleans project files 8 | # build build all output files 9 | # arg 2 project_name.xpr 10 | 11 | # usage 12 | # #!/bin/sh 13 | # vivado=/opt/Xilinx/Vivado/2015.2/bin/vivado 14 | # $vivado -mode tcl -source run_vivado.tcl -tclargs clean 15 | # $vivado -mode tcl -source run_vivado.tcl -tclargs build 16 | 17 | 18 | 19 | 20 | #******************************************************************************* 21 | # Open project 22 | #open_project esa11_7a35i_bram.xpr 23 | open_project [lindex $argv 1] 24 | 25 | 26 | #******************************************************************************* 27 | # Update sources 28 | update_compile_order -fileset sources_1 29 | 30 | 31 | ##******************************************************************************* 32 | ## Clean project 33 | 34 | if {[lindex $argv 0] == "clean"} { 35 | ## clean implementation 36 | reset_run impl_1 37 | 38 | ## clean synthesis 39 | reset_run synth_1 40 | 41 | ## clean PS project configuration 42 | # reset_target all [get_files ./vivado/ps_scripts.srcs/sources_1/bd/system/system.bd] 43 | } 44 | 45 | 46 | ##******************************************************************************* 47 | ## Make output files 48 | 49 | if {[lindex $argv 0] == "build"} { 50 | 51 | ## export PS configuration 52 | # generate_target all [get_files ./vivado/ps_scripts.srcs/sources_1/bd/system/system.bd] 53 | # open_bd_design ./vivado/ps_scripts.srcs/sources_1/bd/system/system.bd 54 | # export_hardware [get_files ./vivado/ps_scripts.srcs/sources_1/bd/system/system.bd] 55 | # close_bd_design system 56 | 57 | ## do synthesis 58 | launch_runs synth_1 59 | wait_on_run synth_1 60 | 61 | ## do implementation 62 | launch_runs impl_1 63 | wait_on_run impl_1 64 | 65 | ## make bit file 66 | launch_runs impl_1 -to_step write_bitstream 67 | wait_on_run impl_1 68 | } 69 | 70 | #******************************************************************************* 71 | # Close opened project 72 | close_project 73 | 74 | exit 75 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-vivado/run_vivado.tcl: -------------------------------------------------------------------------------- 1 | 2 | #******************************************************************************* 3 | # Simple script to control vivado project via command line 4 | # 5 | # It takes 2 arguments 6 | # arg 1 either. 7 | # clean cleans project files 8 | # build build all output files 9 | # arg 2 project_name.xpr 10 | 11 | # usage 12 | # #!/bin/sh 13 | # vivado=/opt/Xilinx/Vivado/2015.2/bin/vivado 14 | # $vivado -mode tcl -source run_vivado.tcl -tclargs clean 15 | # $vivado -mode tcl -source run_vivado.tcl -tclargs build 16 | 17 | 18 | 19 | 20 | #******************************************************************************* 21 | # Open project 22 | #open_project esa11_7a35i_bram.xpr 23 | open_project [lindex $argv 1] 24 | 25 | 26 | #******************************************************************************* 27 | # Update sources 28 | update_compile_order -fileset sources_1 29 | 30 | 31 | ##******************************************************************************* 32 | ## Clean project 33 | 34 | if {[lindex $argv 0] == "clean"} { 35 | ## clean implementation 36 | reset_run impl_1 37 | 38 | ## clean synthesis 39 | reset_run synth_1 40 | 41 | ## clean PS project configuration 42 | # reset_target all [get_files ./vivado/ps_scripts.srcs/sources_1/bd/system/system.bd] 43 | } 44 | 45 | 46 | ##******************************************************************************* 47 | ## Make output files 48 | 49 | if {[lindex $argv 0] == "build"} { 50 | 51 | ## export PS configuration 52 | # generate_target all [get_files ./vivado/ps_scripts.srcs/sources_1/bd/system/system.bd] 53 | # open_bd_design ./vivado/ps_scripts.srcs/sources_1/bd/system/system.bd 54 | # export_hardware [get_files ./vivado/ps_scripts.srcs/sources_1/bd/system/system.bd] 55 | # close_bd_design system 56 | 57 | ## do synthesis 58 | launch_runs synth_1 59 | wait_on_run synth_1 60 | 61 | ## do implementation 62 | launch_runs impl_1 63 | wait_on_run impl_1 64 | 65 | ## make bit file 66 | launch_runs impl_1 -to_step write_bitstream 67 | wait_on_run impl_1 68 | } 69 | 70 | #******************************************************************************* 71 | # Close opened project 72 | close_project 73 | 74 | exit 75 | -------------------------------------------------------------------------------- /proj/lattice/ffm-lfe5-lcdif/universal_make_ps2kbd/makefile: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = minimig_ps2kbd 3 | BOARD = ulx3s 4 | # 25 45 85 5 | FPGA_SIZE = 85 6 | FPGA_PACKAGE = 6bg554c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft4232.ocd 12 | 13 | # ******* design files ******* 14 | CLK0_NAME = clk_minimig 15 | CLK0_FILE_NAME = ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK0_NAME).v 16 | CLK0_OPTIONS = \ 17 | --module=$(CLK0_NAME) \ 18 | --clkin=25 \ 19 | --clkout0_name=clk_140 --clkout0=140.625 \ 20 | --clkout1_name=clk_112 --clkout1=112.5 \ 21 | --clkout2_name=clk_28 --clkout2=28.125 \ 22 | --clkout3_name=clk_7 --clkout3=7.03125 23 | 24 | CLK1_NAME = clk_ramusb 25 | CLK1_FILE_NAME = ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK1_NAME).v 26 | CLK1_OPTIONS = \ 27 | --module=$(CLK1_NAME) \ 28 | --clkin=25 \ 29 | --clkout0_name=clk_112 --clkout0=112.5 \ 30 | --clkout1_name=clk_112_120deg --clkout1=112.5 --phase1=120 \ 31 | --clkout2_name=clk_6 --clkout2=6 32 | 33 | CLK2_NAME = clk_usb 34 | CLK2_FILE_NAME = ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK2_NAME).v 35 | CLK2_OPTIONS = \ 36 | --module=$(CLK2_NAME) \ 37 | --clkin=25 \ 38 | --clkout0_name=clk_240 --clkout0=240 \ 39 | --clkout1_name=clk_48 --clkout1=48 \ 40 | --clkout2_name=clk_6 --clkout2=6 41 | 42 | CLK3_NAME = clk_sys 43 | CLK3_FILE_NAME = ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK3_NAME).v 44 | CLK3_OPTIONS = \ 45 | --module=$(CLK3_NAME) \ 46 | --clkin=100 \ 47 | --clkout0_name=clk_25 --clkout0=25 48 | 49 | # ******* design files ******* 50 | CONSTRAINTS = ../../constraints/FFM-LFE5U-V0r0_mit_FFC-CA7-V2r0.lpf 51 | 52 | TOP_MODULE_FILE = ../../../../rtl_emard/lattice/ffm_lfe5/top/amiga_ffm_lfe5_ps2kbd.vhd 53 | # usually all toplevels have the same top module name 54 | TOP_MODULE = amiga_ffm_lfe5 55 | 56 | include files.mk 57 | 58 | #STRATEGY = ../../../../Minimig_ECS/Area2.sty 59 | STRATEGY = ../../../../Minimig_ECS/Minimig1.sty 60 | 61 | SCRIPTS = ../../include/scripts 62 | include $(SCRIPTS)/trellis_path.mk 63 | include $(SCRIPTS)/diamond_path.mk 64 | include $(SCRIPTS)/diamond_main.mk 65 | -------------------------------------------------------------------------------- /rtl_emard/tools/jbboot_bin2vhdl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import sys 4 | import os.path 5 | 6 | fin = open(sys.argv[1], 'rb') 7 | fout = open(sys.argv[2], 'w') 8 | 9 | # module name 10 | modulename = "jbboot" 11 | # output data size (bytes) 12 | datasize = 2 13 | 14 | data = fin.read() 15 | 16 | array_len = int(len(data)/datasize) 17 | 18 | # calculate addr size 19 | adrsize = 0 20 | fitsize = 1 21 | 22 | while fitsize < array_len: 23 | adrsize += 1 24 | fitsize += fitsize 25 | 26 | fout.write("-- converted by jbboot_bin2vhdl.py\n"); 27 | fout.write("library ieee;\n"); 28 | fout.write("use ieee.std_logic_1164.all;\n"); 29 | fout.write("use ieee.numeric_std.all;\n"); 30 | fout.write("\n"); 31 | fout.write("entity " + modulename + " is\n"); 32 | fout.write(" port\n"); 33 | fout.write(" (\n"); 34 | fout.write(" clk: in std_logic;\n"); 35 | fout.write(" addr: in std_logic_vector(" + str(adrsize - 1) + " downto 0);\n"); 36 | fout.write(" data: out std_logic_vector(" + str(8*datasize - 1) + " downto 0)\n"); 37 | fout.write(" );\n"); 38 | fout.write("end " + modulename + ";\n"); 39 | fout.write("\n") 40 | fout.write("architecture arch of " + modulename + " is\n"); 41 | fout.write(" type rom_type is array (0 to " + str(fitsize-1) + ") of std_logic_vector(" + str(8*datasize - 1) + " downto 0);\n"); 42 | fout.write(" constant rom_data: rom_type := ("); 43 | 44 | last = array_len-1 45 | 46 | if datasize == 1: 47 | for i in range(0, array_len): 48 | if (i % 8) == 0: 49 | fout.write("\n") 50 | fout.write("x\"%02x\"" % (data[i],) ) 51 | if i != fitsize-1: 52 | fout.write(",") 53 | 54 | if datasize == 2: 55 | for i in range(0, array_len): 56 | if (i % 8) == 0: 57 | fout.write("\n") 58 | fout.write("x\"%02x%02x\"" % (data[2*i+0],data[2*i+1],) ) 59 | if i != fitsize-1: 60 | fout.write(",") 61 | 62 | if array_len < fitsize: 63 | fout.write("\nothers => (others => '0')"); 64 | fout.write(");\n"); 65 | fout.write(" signal R_data: std_logic_vector(" + str(8*datasize - 1) + " downto 0);\n"); 66 | fout.write(" signal R_addr: std_logic_vector(" + str(adrsize - 1) + " downto 0);\n"); 67 | fout.write("begin\n"); 68 | fout.write(" process(clk)\n"); 69 | fout.write(" begin\n"); 70 | fout.write(" if rising_edge(clk) then\n"); 71 | fout.write(" R_data <= rom_data(to_integer(unsigned(addr)));\n"); 72 | fout.write(" end if;\n"); 73 | fout.write(" end process;\n"); 74 | fout.write(" data <= R_data;\n"); 75 | fout.write("end arch;\n"); 76 | 77 | fin.close() 78 | fout.close() 79 | 80 | -------------------------------------------------------------------------------- /rtl_emard/vga/hdmi_out.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Copyright (c) 2015 Davor Jadrijevic 3 | -- All rights reserved. 4 | -- 5 | -- Redistribution and use in source and binary forms, with or without 6 | -- modification, are permitted provided that the following conditions 7 | -- are met: 8 | -- 1. Redistributions of source code must retain the above copyright 9 | -- notice, this list of conditions and the following disclaimer. 10 | -- 2. Redistributions in binary form must reproduce the above copyright 11 | -- notice, this list of conditions and the following disclaimer in the 12 | -- documentation and/or other materials provided with the distribution. 13 | -- 14 | -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 | -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 | -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 | -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 | -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 | -- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 | -- SUCH DAMAGE. 25 | -- 26 | -- $Id$ 27 | -- 28 | 29 | -- vendor-independent module for simulating differential HDMI output 30 | -- this module tested on scarab and it works :) 31 | 32 | library IEEE; 33 | use IEEE.STD_LOGIC_1164.ALL; 34 | use IEEE.STD_LOGIC_ARITH.ALL; 35 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 36 | 37 | entity hdmi_out is 38 | port ( 39 | tmds_in_clk: in std_logic; -- 25 MHz pixel clock single ended 40 | tmds_out_clk_p, tmds_out_clk_n: out std_logic; -- output 25 MHz differential 41 | tmds_in_rgb: in std_logic_vector(2 downto 0); -- input (250 MHz single ended) 42 | tmds_out_rgb_p, tmds_out_rgb_n: out std_logic_vector(2 downto 0) -- output 250 MHz differential 43 | ); 44 | end hdmi_out; 45 | 46 | architecture Behavioral of hdmi_out is 47 | begin 48 | -- vendor-independent differential output buffering for HDMI clock and video 49 | tmds_out_clk_p <= tmds_in_clk; 50 | tmds_out_clk_n <= not tmds_in_clk; 51 | 52 | hdmi_video: for i in 0 to 2 generate 53 | tmds_out_rgb_p(i) <= tmds_in_rgb(i); 54 | tmds_out_rgb_n(i) <= not tmds_in_rgb(i); 55 | end generate; 56 | end Behavioral; 57 | -------------------------------------------------------------------------------- /rtl_emard/vga/xilinx/xc6/hdmi_out_xc6.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Copyright (c) 2015 Davor Jadrijevic 3 | -- All rights reserved. 4 | -- 5 | -- Redistribution and use in source and binary forms, with or without 6 | -- modification, are permitted provided that the following conditions 7 | -- are met: 8 | -- 1. Redistributions of source code must retain the above copyright 9 | -- notice, this list of conditions and the following disclaimer. 10 | -- 2. Redistributions in binary form must reproduce the above copyright 11 | -- notice, this list of conditions and the following disclaimer in the 12 | -- documentation and/or other materials provided with the distribution. 13 | -- 14 | -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 | -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 | -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 | -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 | -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 | -- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 | -- SUCH DAMAGE. 25 | -- 26 | -- $Id$ 27 | -- 28 | 29 | -- vendor-specific module for differential HDMI output 30 | -- on Xilinx (Spartan-6) 31 | 32 | library IEEE; 33 | use IEEE.STD_LOGIC_1164.ALL; 34 | use IEEE.STD_LOGIC_ARITH.ALL; 35 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 36 | 37 | library unisim; 38 | use unisim.vcomponents.all; 39 | 40 | entity hdmi_out is 41 | port ( 42 | tmds_in_clk: in std_logic; -- input pixel clock single ended 43 | tmds_out_clk_p, tmds_out_clk_n: out std_logic; -- output pixel clock differential 44 | tmds_in_rgb: in std_logic_vector(2 downto 0); -- input rgb single ended 45 | tmds_out_rgb_p, tmds_out_rgb_n: out std_logic_vector(2 downto 0) -- output rgb differential 46 | ); 47 | end hdmi_out; 48 | 49 | architecture Behavioral of hdmi_out is 50 | begin 51 | -- vendor-specific differential output buffering for HDMI clock and video 52 | hdmi_clock: obufds 53 | --generic map(IOSTANDARD => "DEFAULT") 54 | port map(i => tmds_in_clk, o => tmds_out_clk_p, ob => tmds_out_clk_n); 55 | hdmi_video: for i in 0 to 2 generate 56 | tmds_video: obufds 57 | --generic map(IOSTANDARD => "DEFAULT") 58 | port map(i => tmds_in_rgb(i), o => tmds_out_rgb_p(i), ob => tmds_out_rgb_n(i)); 59 | end generate; 60 | end Behavioral; 61 | -------------------------------------------------------------------------------- /rtl_emard/vga/xilinx/xc7/hdmi_out_xc7.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Copyright (c) 2015 Davor Jadrijevic 3 | -- All rights reserved. 4 | -- 5 | -- Redistribution and use in source and binary forms, with or without 6 | -- modification, are permitted provided that the following conditions 7 | -- are met: 8 | -- 1. Redistributions of source code must retain the above copyright 9 | -- notice, this list of conditions and the following disclaimer. 10 | -- 2. Redistributions in binary form must reproduce the above copyright 11 | -- notice, this list of conditions and the following disclaimer in the 12 | -- documentation and/or other materials provided with the distribution. 13 | -- 14 | -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 | -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 | -- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 | -- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 | -- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 | -- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 | -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 | -- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 | -- SUCH DAMAGE. 25 | -- 26 | -- $Id$ 27 | -- 28 | 29 | -- vendor-specific module for differential HDMI output 30 | -- on Xilinx (Spartan-6) 31 | 32 | library IEEE; 33 | use IEEE.STD_LOGIC_1164.ALL; 34 | use IEEE.STD_LOGIC_ARITH.ALL; 35 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 36 | 37 | library unisim; 38 | use unisim.vcomponents.all; 39 | 40 | entity hdmi_out is 41 | port ( 42 | tmds_in_clk: in std_logic; -- 25 MHz pixel clock single ended 43 | tmds_out_clk_p, tmds_out_clk_n: out std_logic; -- output 25 MHz differential 44 | tmds_in_rgb: in std_logic_vector(2 downto 0); -- input (250 MHz single ended) 45 | tmds_out_rgb_p, tmds_out_rgb_n: out std_logic_vector(2 downto 0) -- output 250 MHz differential 46 | ); 47 | end hdmi_out; 48 | 49 | architecture Behavioral of hdmi_out is 50 | signal obuf_tmds_clock: std_logic; 51 | begin 52 | -- vendor-specific differential output buffering for HDMI clock and video 53 | 54 | hdmi_clock: obufds 55 | --generic map(IOSTANDARD => "DEFAULT") 56 | port map(i => tmds_in_clk, o => tmds_out_clk_p, ob => tmds_out_clk_n); 57 | 58 | hdmi_video: for i in 0 to 2 generate 59 | tmds_video: obufds 60 | --generic map(IOSTANDARD => "DEFAULT") 61 | port map(i => tmds_in_rgb(i), o => tmds_out_rgb_p(i), ob => tmds_out_rgb_n(i)); 62 | end generate; 63 | 64 | end Behavioral; 65 | -------------------------------------------------------------------------------- /rtl_emard/generic/bram_true2p_1clk.vhd: -------------------------------------------------------------------------------- 1 | -- Generated by Quartus II Template 2 | 3 | -- File->New File->VHDL File 4 | -- Edit->Insert Template->VHDL->Full designs->RAMs and ROMs->True dual port RAM (singled clock) 5 | 6 | -- True Dual-Port RAM with single clock 7 | 8 | -- when pass_thru enabled on port 9 | -- then Read-during-write on port should return newly written data 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | use ieee.std_logic_unsigned.all; 14 | 15 | entity bram_true2p_1clk is 16 | generic 17 | ( 18 | dual_port: boolean := True; -- set to False for single port A 19 | pass_thru_a, pass_thru_b: boolean := True; 20 | data_width: natural := 8; 21 | addr_width: natural := 6 22 | ); 23 | port 24 | ( 25 | clk: in std_logic; 26 | addr_a: in std_logic_vector((addr_width-1) downto 0); 27 | addr_b: in std_logic_vector((addr_width-1) downto 0) := (others => '-'); 28 | we_a: in std_logic := '0'; 29 | we_b: in std_logic := '0'; 30 | data_in_a: in std_logic_vector((data_width-1) downto 0); 31 | data_in_b: in std_logic_vector((data_width-1) downto 0) := (others => '-'); 32 | data_out_a: out std_logic_vector((data_width -1) downto 0); 33 | data_out_b: out std_logic_vector((data_width -1) downto 0) 34 | ); 35 | end bram_true2p_1clk; 36 | 37 | architecture rtl of bram_true2p_1clk is 38 | -- Build a 2-D array type for the RAM 39 | subtype word_t is std_logic_vector((data_width-1) downto 0); 40 | type memory_t is array(2**addr_width-1 downto 0) of word_t; 41 | 42 | -- Declare the RAM 43 | shared variable ram: memory_t; 44 | begin 45 | -- Port A 46 | G_port_a_passthru: if pass_thru_a generate 47 | process(clk) 48 | begin 49 | if(rising_edge(clk)) then 50 | if(we_a = '1') then 51 | ram(conv_integer(addr_a)) := data_in_a; 52 | end if; 53 | data_out_a <= ram(conv_integer(addr_a)); 54 | end if; 55 | end process; 56 | end generate; 57 | 58 | G_port_a_not_passthru: if not pass_thru_a generate 59 | process(clk) 60 | begin 61 | if(rising_edge(clk)) then 62 | data_out_a <= ram(conv_integer(addr_a)); 63 | if(we_a = '1') then 64 | ram(conv_integer(addr_a)) := data_in_a; 65 | end if; 66 | end if; 67 | end process; 68 | end generate; 69 | 70 | -- Port B 71 | G_port_b_passthru: if dual_port and pass_thru_b generate 72 | process(clk) 73 | begin 74 | if(rising_edge(clk)) then 75 | if(we_b = '1') then 76 | ram(conv_integer(addr_b)) := data_in_b; 77 | end if; 78 | data_out_b <= ram(conv_integer(addr_b)); 79 | end if; 80 | end process; 81 | end generate; 82 | 83 | G_port_b_not_passthru: if dual_port and not pass_thru_b generate 84 | process(clk) 85 | begin 86 | if(rising_edge(clk)) then 87 | data_out_b <= ram(conv_integer(addr_b)); 88 | if(we_b = '1') then 89 | ram(conv_integer(addr_b)) := data_in_b; 90 | end if; 91 | end if; 92 | end process; 93 | end generate; 94 | end rtl; 95 | -------------------------------------------------------------------------------- /rtl_emard/vga/lattice/xo2/ddr_out.vhd: -------------------------------------------------------------------------------- 1 | -- Emard 2 | -- LICENSE=BSD 3 | -- starting from auto-generated code 4 | -- signals renamed to be more meaningful 5 | -- commented out unused outputs 6 | 7 | library IEEE; 8 | use IEEE.std_logic_1164.all; 9 | -- synopsys translate_off 10 | library MACHXO2; 11 | use MACHXO2.components.all; 12 | -- synopsys translate_on 13 | 14 | entity ddr_out is 15 | port 16 | ( 17 | iclkp: in std_logic; 18 | iclkn: in std_logic; 19 | --clkout: out std_logic; 20 | ireset: in std_logic; 21 | --sclk: out std_logic; 22 | idata: in std_logic_vector(1 downto 0); 23 | odata: out std_logic 24 | ); 25 | end ddr_out; 26 | 27 | architecture Structure of ddr_out is 28 | 29 | -- internal signal declarations 30 | signal db0: std_logic; 31 | signal da0: std_logic; 32 | signal buf_clkout: std_logic; 33 | signal scuba_vlo: std_logic; 34 | signal scuba_vhi: std_logic; 35 | signal buf_douto0: std_logic; 36 | 37 | -- local component declarations 38 | component VHI 39 | port (Z: out std_logic); 40 | end component; 41 | component VLO 42 | port (Z: out std_logic); 43 | end component; 44 | component OB 45 | port (I: in std_logic; O: out std_logic); 46 | end component; 47 | component ODDRXE 48 | port (D0: in std_logic; D1: in std_logic; SCLK: in std_logic; 49 | RST: in std_logic; Q: out std_logic); 50 | end component; 51 | attribute IO_TYPE : string; 52 | --attribute IO_TYPE of Inst4_OB : label is "LVDS25"; 53 | attribute IO_TYPE of Inst1_OB0 : label is "LVDS25"; 54 | attribute syn_keep : boolean; 55 | attribute NGD_DRC_MASK : integer; 56 | attribute NGD_DRC_MASK of Structure : architecture is 1; 57 | 58 | begin 59 | -- component instantiation statements 60 | --Inst4_OB: OB 61 | -- port map (I=>buf_clkout, O=>clkout); 62 | 63 | Inst3_ODDRXE0: ODDRXE 64 | port map (D0=>da0, D1=>db0, SCLK=>iclkp, RST=>ireset, 65 | Q=>buf_douto0); 66 | 67 | scuba_vlo_inst: VLO 68 | port map (Z=>scuba_vlo); 69 | 70 | scuba_vhi_inst: VHI 71 | port map (Z=>scuba_vhi); 72 | 73 | Inst2_ODDRXE: ODDRXE 74 | port map (D0=>scuba_vhi, D1=>scuba_vlo, SCLK=>iclkn, RST=>ireset, 75 | Q=>buf_clkout); 76 | 77 | Inst1_OB0: OB 78 | port map (I=>buf_douto0, O=>odata); 79 | 80 | --sclk <= iclkp; 81 | db0 <= idata(1); 82 | da0 <= idata(0); 83 | end Structure; 84 | 85 | -- synopsys translate_off 86 | library MACHXO2; 87 | configuration Structure_CON of ddr_out is 88 | for Structure 89 | for all:VHI use entity MACHXO2.VHI(V); end for; 90 | for all:VLO use entity MACHXO2.VLO(V); end for; 91 | for all:OB use entity MACHXO2.OB(V); end for; 92 | for all:ODDRXE use entity MACHXO2.ODDRXE(V); end for; 93 | end for; 94 | end Structure_CON; 95 | 96 | -- synopsys translate_on 97 | -------------------------------------------------------------------------------- /rtl_emard/usb/usbhost/usbh_crc5.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------- 2 | // USB Full Speed Host 3 | // V0.5 4 | // Ultra-Embedded.com 5 | // Copyright 2015-2019 6 | // 7 | // Email: admin@ultra-embedded.com 8 | // 9 | // License: GPL 10 | // If you would like a version with a more permissive license for 11 | // use in closed source commercial applications please contact me 12 | // for details. 13 | //----------------------------------------------------------------- 14 | // 15 | // This file is open source HDL; you can redistribute it and/or 16 | // modify it under the terms of the GNU General Public License as 17 | // published by the Free Software Foundation; either version 2 of 18 | // the License, or (at your option) any later version. 19 | // 20 | // This file is distributed in the hope that it will be useful, 21 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 22 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 | // GNU General Public License for more details. 24 | // 25 | // You should have received a copy of the GNU General Public 26 | // License along with this file; if not, write to the Free Software 27 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 28 | // USA 29 | //----------------------------------------------------------------- 30 | 31 | //----------------------------------------------------------------- 32 | // Generated File 33 | //----------------------------------------------------------------- 34 | //----------------------------------------------------------------- 35 | // Module: 5-bit CRC used by USB tokens 36 | //----------------------------------------------------------------- 37 | module usbh_crc5 38 | ( 39 | input [4:0] crc_i, 40 | input [10:0] data_i, 41 | output [4:0] crc_o 42 | ); 43 | 44 | //----------------------------------------------------------------- 45 | // Implementation 46 | //----------------------------------------------------------------- 47 | assign crc_o[0] = data_i[10] ^ data_i[9] ^ data_i[6] ^ data_i[5] ^ data_i[3] ^ data_i[0] ^ 48 | crc_i[0] ^ crc_i[3] ^ crc_i[4]; 49 | 50 | assign crc_o[1] = data_i[10] ^ data_i[7] ^ data_i[6] ^ data_i[4] ^ data_i[1] ^ 51 | crc_i[0] ^ crc_i[1] ^ crc_i[4]; 52 | 53 | assign crc_o[2] = data_i[10] ^ data_i[9] ^ data_i[8] ^ data_i[7] ^ data_i[6] ^ data_i[3] ^ data_i[2] ^ data_i[0] ^ 54 | crc_i[0] ^ crc_i[1] ^ crc_i[2] ^ crc_i[3] ^ crc_i[4]; 55 | 56 | assign crc_o[3] = data_i[10] ^ data_i[9] ^ data_i[8] ^ data_i[7] ^ data_i[4] ^ data_i[3] ^ data_i[1] ^ 57 | crc_i[1] ^ crc_i[2] ^ crc_i[3] ^ crc_i[4]; 58 | 59 | assign crc_o[4] = data_i[10] ^ data_i[9] ^ data_i[8] ^ data_i[5] ^ data_i[4] ^ data_i[2] ^ 60 | crc_i[2] ^ crc_i[3] ^ crc_i[4]; 61 | 62 | endmodule 63 | 64 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-ise/Makefile: -------------------------------------------------------------------------------- 1 | project = FFM-A7100-V3r0_and_FFC-CA7-V2r0 2 | vendor = xilinx 3 | family = artix7 4 | MODEL ?= xc7a100t 5 | part = ${MODEL}-fgg484-2 # last number -3 is speed grade 6 | flashsize = 8192 # KB (kilobytes) - SPI flash device is M25P40 7 | top_module = amiga_ffm_a7100 8 | isedir = /opt/Xilinx/ISE/14.7/ISE_DS 9 | xil_env = . $(isedir)/settings64.sh 10 | SHELL = /bin/bash 11 | # openocd_interface = interface/altera-usb-blaster.cfg 12 | # openocd_interface = ../include/ft2232-fpu1.ocd 13 | openocd_interface = programmer/ft2232-generic.ocd 14 | xc3sprog_interface = ft4232h_fast 15 | 16 | include ../include/xilinx.mk 17 | 18 | vfiles = \ 19 | ../../../Minimig_ECS/impl1/source/Agnus.v \ 20 | ../../../Minimig_ECS/impl1/source/akiko.v \ 21 | ../../../Minimig_ECS/impl1/source/Amber.v \ 22 | ../../../Minimig_ECS/impl1/source/Audio.v \ 23 | ../../../Minimig_ECS/impl1/source/Beamcounter.v \ 24 | ../../../Minimig_ECS/impl1/source/Bitplanes.v \ 25 | ../../../Minimig_ECS/impl1/source/Blitter.v \ 26 | ../../../Minimig_ECS/impl1/source/CIA8520.v \ 27 | ../../../Minimig_ECS/impl1/source/Clock.v \ 28 | ../../../Minimig_ECS/impl1/source/Copper.v \ 29 | ../../../Minimig_ECS/impl1/source/Denise.v \ 30 | ../../../Minimig_ECS/impl1/source/Floppy.v \ 31 | ../../../Minimig_ECS/impl1/source/Gary.v \ 32 | ../../../Minimig_ECS/impl1/source/Gayle.v \ 33 | ../../../source_emard/Minimig1.v \ 34 | ../../../Minimig_ECS/impl1/source/Paula.v \ 35 | ../../../source_emard/PS2Keyboard.v \ 36 | ../../../source_emard/twowaycache.v \ 37 | ../../../Minimig_ECS/impl1/source/Sprites.v \ 38 | ../../../Minimig_ECS/impl1/source/Userio.v \ 39 | 40 | vhdfiles = \ 41 | top/amiga_ffm_a7100_lcdif.vhd \ 42 | ../../../Minimig_ECS/impl1/source/Fampiga.vhd \ 43 | ../../../source_emard/cfide.vhd \ 44 | ../../../Minimig_ECS/impl1/source/Debounce.vhd \ 45 | ../../../Minimig_ECS/RTL/sdram_cache.vhd \ 46 | ../../../Minimig_ECS/impl1/source/TG68K.vhd \ 47 | ../../../Minimig_ECS/impl1/source/TG68K_ALU.vhd \ 48 | ../../../Minimig_ECS/impl1/source/TG68K_Pack.vhd \ 49 | ../../../Minimig_ECS/impl1/source/TG68KdotC_Kernel.vhd \ 50 | ../../../source_emard/poweronreset.vhd \ 51 | ../../../osd_bootstrap.vhd \ 52 | ../../../Minimig_ECS/impl1/source/HDMI/aux_ecc1.vhd \ 53 | ../../../Minimig_ECS/impl1/source/HDMI/aux_ecc2.vhd \ 54 | ../../../Minimig_ECS/impl1/source/HDMI/aux_encoder.vhd \ 55 | ../../../source_emard/HDMI/dvid.vhd \ 56 | ../../../Minimig_ECS/impl1/source/HDMI/dvienc_defs.vhd \ 57 | ../../../Minimig_ECS/impl1/source/HDMI/edvi_ucode.vhd \ 58 | ../../../Minimig_ECS/impl1/source/HDMI/infoframe_rom_800x600_60hz_40M_48k.vhd \ 59 | ../../../Minimig_ECS/impl1/source/HDMI/TMDS_encoder.vhd \ 60 | ../../../jbboot.vhd \ 61 | ../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 62 | ../../../rtl_emard/vga/hdmi/vga2dvid.vhd \ 63 | ../../../rtl_emard/vga/hdmi/tmds_encoder.vhd \ 64 | ../../../rtl_emard/spdif/spdif_tx.vhd \ 65 | ../../../rtl_emard/vga/xilinx/xc6/ddr_out.vhd \ 66 | 67 | # ../../../rtl_emard/vga/vga.vhd \ 68 | # ../../../rtl_emard/osd/osd.vhd \ 69 | # ../../../rtl_emard/osd/char_rom.vhd \ 70 | -------------------------------------------------------------------------------- /proj/xilinx/scarab-25k/Makefile: -------------------------------------------------------------------------------- 1 | project = miniSpartan6-plus 2 | vendor = xilinx 3 | family = spartan6 4 | MODEL ?= xc6slx25 5 | part = ${MODEL}-ftg256-3 # last number -3 is speed grade 6 | flashsize = 8192 # KB (kilobytes) - SPI flash device is M25P40 7 | top_module = amiga_scarab 8 | isedir = /opt/Xilinx/ISE/14.7/ISE_DS 9 | xil_env = . $(isedir)/settings64.sh 10 | SHELL = /bin/bash 11 | # openocd_interface = interface/altera-usb-blaster.cfg 12 | # openocd_interface = ../include/ft2232-fpu1.ocd 13 | openocd_interface = programmer/ft2232-generic.ocd 14 | xc3sprog_interface = ftdi 15 | 16 | include ../include/xilinx.mk 17 | 18 | vfiles = \ 19 | ../../../Minimig_ECS/impl1/source/Agnus.v \ 20 | ../../../Minimig_ECS/impl1/source/akiko.v \ 21 | ../../../Minimig_ECS/impl1/source/Amber.v \ 22 | ../../../Minimig_ECS/impl1/source/Audio.v \ 23 | ../../../Minimig_ECS/impl1/source/Beamcounter.v \ 24 | ../../../Minimig_ECS/impl1/source/Bitplanes.v \ 25 | ../../../Minimig_ECS/impl1/source/Blitter.v \ 26 | ../../../Minimig_ECS/impl1/source/CIA8520.v \ 27 | ../../../Minimig_ECS/impl1/source/Clock.v \ 28 | ../../../Minimig_ECS/impl1/source/Copper.v \ 29 | ../../../Minimig_ECS/impl1/source/Denise.v \ 30 | ../../../Minimig_ECS/impl1/source/Floppy.v \ 31 | ../../../Minimig_ECS/impl1/source/Gary.v \ 32 | ../../../Minimig_ECS/impl1/source/Gayle.v \ 33 | ../../../source_emard/Minimig1.v \ 34 | ../../../Minimig_ECS/impl1/source/Paula.v \ 35 | ../../../source_emard/PS2Keyboard.v \ 36 | ../../../source_emard/twowaycache.v \ 37 | ../../../Minimig_ECS/impl1/source/Sprites.v \ 38 | ../../../Minimig_ECS/impl1/source/Userio.v \ 39 | 40 | vhdfiles = \ 41 | top/amiga_scarab.vhd \ 42 | clocks/clk_50_28_140_7_116.vhd \ 43 | ../../../Minimig_ECS/impl1/source/Fampiga.vhd \ 44 | ../../../source_emard/cfide.vhd \ 45 | ../../../Minimig_ECS/impl1/source/Debounce.vhd \ 46 | ../../../Minimig_ECS/RTL/sdram_cache.vhd \ 47 | ../../../Minimig_ECS/impl1/source/TG68K.vhd \ 48 | ../../../Minimig_ECS/impl1/source/TG68K_ALU.vhd \ 49 | ../../../Minimig_ECS/impl1/source/TG68K_Pack.vhd \ 50 | ../../../Minimig_ECS/impl1/source/TG68KdotC_Kernel.vhd \ 51 | ../../../source_emard/poweronreset.vhd \ 52 | ../../../osd_bootstrap.vhd \ 53 | ../../../Minimig_ECS/impl1/source/HDMI/aux_ecc1.vhd \ 54 | ../../../Minimig_ECS/impl1/source/HDMI/aux_ecc2.vhd \ 55 | ../../../Minimig_ECS/impl1/source/HDMI/aux_encoder.vhd \ 56 | ../../../source_emard/HDMI/dvid.vhd \ 57 | ../../../Minimig_ECS/impl1/source/HDMI/dvienc_defs.vhd \ 58 | ../../../Minimig_ECS/impl1/source/HDMI/edvi_ucode.vhd \ 59 | ../../../Minimig_ECS/impl1/source/HDMI/infoframe_rom_800x600_60hz_40M_48k.vhd \ 60 | ../../../Minimig_ECS/impl1/source/HDMI/TMDS_encoder.vhd \ 61 | ../../../jbboot.vhd \ 62 | ../../../rtl_emard/osd/osd.vhd \ 63 | ../../../rtl_emard/osd/char_rom.vhd \ 64 | ../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 65 | ../../../rtl_emard/vga/vga.vhd \ 66 | ../../../rtl_emard/vga/hdmi/vga2dvid.vhd \ 67 | ../../../rtl_emard/vga/hdmi/tmds_encoder.vhd \ 68 | ../../../rtl_emard/vga/hdmi/ddr_dvid_out_se.vhd \ 69 | ../../../rtl_emard/vga/xilinx/xc6/ddr_out.vhd \ 70 | ../../../rtl_emard/vga/xilinx/xc6/hdmi_out_xc6.vhd \ 71 | ../../../rtl_emard/spdif/spdif_tx.vhd \ 72 | 73 | # ../../../rtl_emard/vga/hdmi_out.vhd \ 74 | -------------------------------------------------------------------------------- /proj/lattice/ulx3s/universal_make_ps2kbd/files.mk: -------------------------------------------------------------------------------- 1 | VHDL_FILES = $(TOP_MODULE_FILE) \ 2 | ../../../../rtl_emard/lattice/ulx3s/clocks/ecp5pll.vhd \ 3 | ../../../../Minimig_ECS/impl1/source/Fampiga.vhd \ 4 | ../../../../source_emard/cfide.vhd \ 5 | ../../../../Minimig_ECS/impl1/source/Debounce.vhd \ 6 | ../../../../Minimig_ECS/impl1/source/TG68K.vhd \ 7 | ../../../../Minimig_ECS/impl1/source/TG68K_ALU.vhd \ 8 | ../../../../Minimig_ECS/impl1/source/TG68K_Pack.vhd \ 9 | ../../../../Minimig_ECS/impl1/source/TG68KdotC_Kernel.vhd \ 10 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_ecc1.vhd \ 11 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_ecc2.vhd \ 12 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_encoder.vhd \ 13 | ../../../../source_emard/HDMI/dvid.vhd \ 14 | ../../../../Minimig_ECS/impl1/source/HDMI/dvienc_defs.vhd \ 15 | ../../../../Minimig_ECS/impl1/source/HDMI/edvi_ucode.vhd \ 16 | ../../../../Minimig_ECS/impl1/source/HDMI/infoframe_rom_800x600_60hz_40M_48k.vhd \ 17 | ../../../../Minimig_ECS/impl1/source/HDMI/TMDS_encoder.vhd \ 18 | ../../../../source_emard/poweronreset.vhd \ 19 | ../../../../osd_bootstrap.vhd \ 20 | ../../../../jbboot.vhd \ 21 | ../../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 22 | ../../../../rtl_emard/vga/vga.vhd \ 23 | ../../../../rtl_emard/vga/hdmi/vga2dvid.vhd \ 24 | ../../../../rtl_emard/vga/hdmi/tmds_encoder.vhd \ 25 | ../../../../rtl_emard/vga/lattice/ecp5u/ddr_out_emard.vhd \ 26 | ../../../../rtl_emard/usb/usbhid/usbhid_report_decoder_saitek_joystick.vhd \ 27 | ../../../../rtl_emard/usb/usbhid/report_decoded_pack_generic.vhd \ 28 | ../../../../rtl_emard/usb/usbhost/usbh_setup_pack.vhd \ 29 | ../../../../rtl_emard/usb/usbhost/usbh_host_hid.vhd \ 30 | ../../../../rtl_emard/usb/usbhost/usbh_sie_vhdl.vhd \ 31 | ../../../../rtl_emard/usb/usb11_phy_vhdl/usb_phy.vhd \ 32 | ../../../../rtl_emard/usb/usb11_phy_vhdl/usb_rx_phy_48MHz.vhd \ 33 | ../../../../rtl_emard/usb/usb11_phy_vhdl/usb_rx_phy_emard.vhd \ 34 | ../../../../rtl_emard/usb/usb11_phy_vhdl/usb_tx_phy.vhd \ 35 | ../../../../rtl_emard/spdif/spdif_tx.vhd \ 36 | ../../../../rtl_emard/osd/char_rom.vhd \ 37 | ../../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 38 | ../../../../Minimig_ECS/RTL/sdram_cache.vhd \ 39 | 40 | # sdram controllers 41 | # ../../../../rtl_emard/sdram/sdram.vhd \ 42 | # ../../../../Minimig_ECS/RTL/sdram_cache.vhd \ 43 | 44 | VERILOG_FILES = \ 45 | ../../../../Minimig_ECS/impl1/source/Agnus.v \ 46 | ../../../../Minimig_ECS/impl1/source/Amber.v \ 47 | ../../../../Minimig_ECS/impl1/source/Audio.v \ 48 | ../../../../Minimig_ECS/impl1/source/Beamcounter.v \ 49 | ../../../../Minimig_ECS/impl1/source/Bitplanes.v \ 50 | ../../../../Minimig_ECS/impl1/source/Blitter.v \ 51 | ../../../../Minimig_ECS/impl1/source/CIA8520.v \ 52 | ../../../../Minimig_ECS/impl1/source/Clock.v \ 53 | ../../../../Minimig_ECS/impl1/source/Copper.v \ 54 | ../../../../Minimig_ECS/impl1/source/Denise.v \ 55 | ../../../../Minimig_ECS/impl1/source/Floppy.v \ 56 | ../../../../Minimig_ECS/impl1/source/Gary.v \ 57 | ../../../../Minimig_ECS/impl1/source/Gayle.v \ 58 | ../../../../source_emard/Minimig1.v \ 59 | ../../../../Minimig_ECS/impl1/source/Paula.v \ 60 | ../../../../source_emard/PS2Keyboard.v \ 61 | ../../../../source_emard/twowaycache.v \ 62 | ../../../../Minimig_ECS/impl1/source/Sprites.v \ 63 | ../../../../source_emard/Userio.v \ 64 | ../../../../rtl_emard/usb/usbhost/usbh_sie.v \ 65 | ../../../../rtl_emard/usb/usbhost/usbh_crc5.v \ 66 | ../../../../rtl_emard/usb/usbhost/usbh_crc16.v \ 67 | -------------------------------------------------------------------------------- /proj/lattice/ulx3s/universal_make_usbjoy/files.mk: -------------------------------------------------------------------------------- 1 | VHDL_FILES = $(TOP_MODULE_FILE) \ 2 | ../../../../rtl_emard/lattice/ulx3s/clocks/ecp5pll.vhd \ 3 | ../../../../Minimig_ECS/impl1/source/Fampiga.vhd \ 4 | ../../../../source_emard/cfide.vhd \ 5 | ../../../../Minimig_ECS/impl1/source/Debounce.vhd \ 6 | ../../../../Minimig_ECS/impl1/source/TG68K.vhd \ 7 | ../../../../Minimig_ECS/impl1/source/TG68K_ALU.vhd \ 8 | ../../../../Minimig_ECS/impl1/source/TG68K_Pack.vhd \ 9 | ../../../../Minimig_ECS/impl1/source/TG68KdotC_Kernel.vhd \ 10 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_ecc1.vhd \ 11 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_ecc2.vhd \ 12 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_encoder.vhd \ 13 | ../../../../source_emard/HDMI/dvid.vhd \ 14 | ../../../../Minimig_ECS/impl1/source/HDMI/dvienc_defs.vhd \ 15 | ../../../../Minimig_ECS/impl1/source/HDMI/edvi_ucode.vhd \ 16 | ../../../../Minimig_ECS/impl1/source/HDMI/infoframe_rom_800x600_60hz_40M_48k.vhd \ 17 | ../../../../Minimig_ECS/impl1/source/HDMI/TMDS_encoder.vhd \ 18 | ../../../../source_emard/poweronreset.vhd \ 19 | ../../../../osd_bootstrap.vhd \ 20 | ../../../../jbboot.vhd \ 21 | ../../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 22 | ../../../../rtl_emard/vga/vga.vhd \ 23 | ../../../../rtl_emard/vga/hdmi/vga2dvid.vhd \ 24 | ../../../../rtl_emard/vga/hdmi/tmds_encoder.vhd \ 25 | ../../../../rtl_emard/vga/lattice/ecp5u/ddr_out_emard.vhd \ 26 | ../../../../rtl_emard/usb/usbhid/usbhid_report_decoder_saitek_joystick.vhd \ 27 | ../../../../rtl_emard/usb/usbhid/report_decoded_pack_generic.vhd \ 28 | ../../../../rtl_emard/usb/usbhost/usbh_setup_pack.vhd \ 29 | ../../../../rtl_emard/usb/usbhost/usbh_host_hid.vhd \ 30 | ../../../../rtl_emard/usb/usbhost/usbh_sie_vhdl.vhd \ 31 | ../../../../rtl_emard/usb/usb11_phy_vhdl/usb_phy.vhd \ 32 | ../../../../rtl_emard/usb/usb11_phy_vhdl/usb_rx_phy_48MHz.vhd \ 33 | ../../../../rtl_emard/usb/usb11_phy_vhdl/usb_rx_phy_emard.vhd \ 34 | ../../../../rtl_emard/usb/usb11_phy_vhdl/usb_tx_phy.vhd \ 35 | ../../../../rtl_emard/spdif/spdif_tx.vhd \ 36 | ../../../../rtl_emard/osd/char_rom.vhd \ 37 | ../../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 38 | ../../../../Minimig_ECS/RTL/sdram_cache.vhd \ 39 | 40 | # sdram controllers 41 | # ../../../../rtl_emard/sdram/sdram.vhd \ 42 | # ../../../../Minimig_ECS/RTL/sdram_cache.vhd \ 43 | 44 | VERILOG_FILES = \ 45 | ../../../../Minimig_ECS/impl1/source/Agnus.v \ 46 | ../../../../Minimig_ECS/impl1/source/Amber.v \ 47 | ../../../../Minimig_ECS/impl1/source/Audio.v \ 48 | ../../../../Minimig_ECS/impl1/source/Beamcounter.v \ 49 | ../../../../Minimig_ECS/impl1/source/Bitplanes.v \ 50 | ../../../../Minimig_ECS/impl1/source/Blitter.v \ 51 | ../../../../Minimig_ECS/impl1/source/CIA8520.v \ 52 | ../../../../Minimig_ECS/impl1/source/Clock.v \ 53 | ../../../../Minimig_ECS/impl1/source/Copper.v \ 54 | ../../../../Minimig_ECS/impl1/source/Denise.v \ 55 | ../../../../Minimig_ECS/impl1/source/Floppy.v \ 56 | ../../../../Minimig_ECS/impl1/source/Gary.v \ 57 | ../../../../Minimig_ECS/impl1/source/Gayle.v \ 58 | ../../../../source_emard/Minimig1.v \ 59 | ../../../../Minimig_ECS/impl1/source/Paula.v \ 60 | ../../../../source_emard/PS2Keyboard.v \ 61 | ../../../../source_emard/twowaycache.v \ 62 | ../../../../Minimig_ECS/impl1/source/Sprites.v \ 63 | ../../../../source_emard/Userio.v \ 64 | ../../../../rtl_emard/usb/usbhost/usbh_sie.v \ 65 | ../../../../rtl_emard/usb/usbhost/usbh_crc5.v \ 66 | ../../../../rtl_emard/usb/usbhost/usbh_crc16.v \ 67 | -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-ps2kbd/fleafpga_ohm_flash.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Micron 11 | ECP5U 12 | LFE5U-25F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program,Verify 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-25F 34 | 0x41111043 35 | All 36 | LFE5U-25F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-25F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | WinBond 58 | SPI Serial Flash 59 | W25Q80 60 | 0x13 61 | 8-pin SOIC 62 | SPI Flash Erase,Program,Verify 63 | project/project_project.mcs 64 | 0x00000000 65 | 0x00020000 66 | 8 67 | 1048576 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-usbjoy/fleafpga_ohm_flash.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Micron 11 | ECP5U 12 | LFE5U-25F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program,Verify 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-25F 34 | 0x41111043 35 | All 36 | LFE5U-25F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-25F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | WinBond 58 | SPI Serial Flash 59 | W25Q80 60 | 0x13 61 | 8-pin SOIC 62 | SPI Flash Erase,Program,Verify 63 | project/project_project.mcs 64 | 0x00000000 65 | 0x00020000 66 | 8 67 | 1048576 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-ps2kbd/clocks/clk_25M_150Mp_150Mn.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 2 | -- Module Version: 5.7 3 | --/mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_25M_150Mp_150Mn -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 150.00 -fclkop_tol 0.0 -fclkos 150.00 -fclkos_tol 0.0 -phases 180 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/fpgarduino/f32c/rtl/proj/lattice/ulx3s/xram_sdram_vector_12f/clk_433M92/clk_25M_150Mp_150Mn/clk_25M_150Mp_150Mn.fdc 4 | 5 | -- Tue Feb 20 00:29:23 2018 6 | 7 | library IEEE; 8 | use IEEE.std_logic_1164.all; 9 | library ECP5U; 10 | use ECP5U.components.all; 11 | 12 | entity clk_25M_150Mp_150Mn is 13 | port ( 14 | CLKI: in std_logic; 15 | CLKOP: out std_logic; 16 | CLKOS: out std_logic); 17 | end clk_25M_150Mp_150Mn; 18 | 19 | architecture Structure of clk_25M_150Mp_150Mn is 20 | 21 | -- internal signal declarations 22 | signal REFCLK: std_logic; 23 | signal LOCK: std_logic; 24 | signal CLKOS_t: std_logic; 25 | signal CLKOP_t: std_logic; 26 | signal scuba_vhi: std_logic; 27 | signal scuba_vlo: std_logic; 28 | 29 | attribute FREQUENCY_PIN_CLKOS : string; 30 | attribute FREQUENCY_PIN_CLKOP : string; 31 | attribute FREQUENCY_PIN_CLKI : string; 32 | attribute ICP_CURRENT : string; 33 | attribute LPF_RESISTOR : string; 34 | attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "150.000000"; 35 | attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "150.000000"; 36 | attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "25.000000"; 37 | attribute ICP_CURRENT of PLLInst_0 : label is "5"; 38 | attribute LPF_RESISTOR of PLLInst_0 : label is "16"; 39 | attribute syn_keep : boolean; 40 | attribute NGD_DRC_MASK : integer; 41 | attribute NGD_DRC_MASK of Structure : architecture is 1; 42 | 43 | begin 44 | -- component instantiation statements 45 | scuba_vhi_inst: VHI 46 | port map (Z=>scuba_vhi); 47 | 48 | scuba_vlo_inst: VLO 49 | port map (Z=>scuba_vlo); 50 | 51 | PLLInst_0: EHXPLLL 52 | generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 53 | STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 54 | CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, 55 | CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 5, 56 | CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0, 57 | CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", 58 | CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", 59 | OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 60 | OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", 61 | OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", 62 | OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, 63 | CLKOS2_DIV=> 1, CLKOS_DIV=> 4, CLKOP_DIV=> 4, CLKFB_DIV=> 6, 64 | CLKI_DIV=> 1, FEEDBK_PATH=> "CLKOP") 65 | port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 66 | PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 67 | PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 68 | STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 69 | ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 70 | ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, 71 | CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 72 | REFCLK=>REFCLK, CLKINTFB=>open); 73 | 74 | CLKOS <= CLKOS_t; 75 | CLKOP <= CLKOP_t; 76 | end Structure; 77 | -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-usbjoy/clocks/clk_25M_150Mp_150Mn.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 2 | -- Module Version: 5.7 3 | --/mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_25M_150Mp_150Mn -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 150.00 -fclkop_tol 0.0 -fclkos 150.00 -fclkos_tol 0.0 -phases 180 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/fpgarduino/f32c/rtl/proj/lattice/ulx3s/xram_sdram_vector_12f/clk_433M92/clk_25M_150Mp_150Mn/clk_25M_150Mp_150Mn.fdc 4 | 5 | -- Tue Feb 20 00:29:23 2018 6 | 7 | library IEEE; 8 | use IEEE.std_logic_1164.all; 9 | library ECP5U; 10 | use ECP5U.components.all; 11 | 12 | entity clk_25M_150Mp_150Mn is 13 | port ( 14 | CLKI: in std_logic; 15 | CLKOP: out std_logic; 16 | CLKOS: out std_logic); 17 | end clk_25M_150Mp_150Mn; 18 | 19 | architecture Structure of clk_25M_150Mp_150Mn is 20 | 21 | -- internal signal declarations 22 | signal REFCLK: std_logic; 23 | signal LOCK: std_logic; 24 | signal CLKOS_t: std_logic; 25 | signal CLKOP_t: std_logic; 26 | signal scuba_vhi: std_logic; 27 | signal scuba_vlo: std_logic; 28 | 29 | attribute FREQUENCY_PIN_CLKOS : string; 30 | attribute FREQUENCY_PIN_CLKOP : string; 31 | attribute FREQUENCY_PIN_CLKI : string; 32 | attribute ICP_CURRENT : string; 33 | attribute LPF_RESISTOR : string; 34 | attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "150.000000"; 35 | attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "150.000000"; 36 | attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "25.000000"; 37 | attribute ICP_CURRENT of PLLInst_0 : label is "5"; 38 | attribute LPF_RESISTOR of PLLInst_0 : label is "16"; 39 | attribute syn_keep : boolean; 40 | attribute NGD_DRC_MASK : integer; 41 | attribute NGD_DRC_MASK of Structure : architecture is 1; 42 | 43 | begin 44 | -- component instantiation statements 45 | scuba_vhi_inst: VHI 46 | port map (Z=>scuba_vhi); 47 | 48 | scuba_vlo_inst: VLO 49 | port map (Z=>scuba_vlo); 50 | 51 | PLLInst_0: EHXPLLL 52 | generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 53 | STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 54 | CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, 55 | CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 5, 56 | CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0, 57 | CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", 58 | CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", 59 | OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 60 | OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", 61 | OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", 62 | OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, 63 | CLKOS2_DIV=> 1, CLKOS_DIV=> 4, CLKOP_DIV=> 4, CLKFB_DIV=> 6, 64 | CLKI_DIV=> 1, FEEDBK_PATH=> "CLKOP") 65 | port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 66 | PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 67 | PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 68 | STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 69 | ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 70 | ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, 71 | CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 72 | REFCLK=>REFCLK, CLKINTFB=>open); 73 | 74 | CLKOS <= CLKOS_t; 75 | CLKOP <= CLKOP_t; 76 | end Structure; 77 | -------------------------------------------------------------------------------- /rtl_emard/osd/osd.vhd: -------------------------------------------------------------------------------- 1 | -- (C)EMARD 2 | -- LICENSE=BSD 3 | 4 | -- display 64-bit binary-to-hex conversion 5 | -- on VGA-synchronous OSD 6 | 7 | library IEEE; 8 | use IEEE.STD_LOGIC_1164.ALL; 9 | use IEEE.STD_LOGIC_ARITH.ALL; 10 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 11 | 12 | entity osd is 13 | generic ( 14 | C_digits: integer := 16; -- number of hex digits to show 15 | C_resolution_x: integer := 640 16 | ); 17 | port ( 18 | clk_pixel: in std_logic := '0'; -- VGA pixel clock 25 MHz 19 | vsync, fetch_next: std_logic; 20 | probe_in: in std_logic_vector(4*C_digits-1 downto 0) := (others => '0'); -- test: x"0123456789ABCDEF" 21 | osd_out: out std_logic 22 | ); 23 | end; 24 | 25 | architecture Behavioral of osd is 26 | --component char_rom is 27 | --Port 28 | --( 29 | -- clock: in STD_LOGIC; 30 | -- addr: in STD_LOGIC_VECTOR(11 downto 0); 31 | -- data: out STD_LOGIC_VECTOR(7 downto 0) 32 | --); 33 | --end component; 34 | 35 | -- OSD 36 | signal R_osd_x, R_osd_y: std_logic_vector(10 downto 0); -- 2048x2048 max 37 | --signal R_osd_counter: std_logic_vector(20 downto 0); -- pixel counter 38 | signal S_char_data: std_logic_vector(7 downto 0); 39 | signal S_char_addr: integer; 40 | signal R_osd_out: std_logic; 41 | signal S_osd_pixel: std_logic; 42 | signal S_ascii: std_logic_vector(7 downto 0) := x"41"; 43 | signal S_nibble: std_logic_vector(3 downto 0); 44 | signal R_xpix: integer range 0 to 5 := 0; 45 | signal R_xcol: integer range 0 to C_digits-1 := 0; 46 | begin 47 | -- S_char_addr <= (others => '0') when R_xpix = 5 else conv_std_logic_vector(5*R_xcol + R_xpix, 12); 48 | S_nibble <= probe_in(4*(C_digits-1-R_xcol)+3 downto 4*(C_digits-1-R_xcol)); 49 | -- S_ascii <= S_nibble + x"30" when S_nibble < 10 else S_nibble + x"41" - x"0A"; 50 | -- ascii*5 -> char ROM address, R_xpix=5 outputs 0 for 1-pixel wide inter-char spacer 51 | -- address 5*0x10 is space (between chars) 52 | -- S_char_addr <= x"50" when R_xpix = 5 else conv_std_logic_vector(5*conv_integer(S_nibble) + R_xpix, 8); 53 | S_char_addr <= 16*5 when R_xpix = 5 else 5*conv_integer(S_nibble) + R_xpix; 54 | inst_charrom: entity work.char_rom 55 | port map 56 | ( 57 | clock => clk_pixel, 58 | addr => S_char_addr, 59 | data(6 downto 0) => S_char_data(6 downto 0) 60 | ); 61 | 62 | S_osd_pixel <= '1' when S_char_data(conv_integer(R_osd_y(3 downto 1)))='1' else '0'; -- doublesize y -> .. downto 1 63 | process(clk_pixel) 64 | begin 65 | if rising_edge(clk_pixel) then 66 | if vsync = '1' then 67 | R_osd_y <= (others => '0'); 68 | R_xpix <= 0; 69 | R_xcol <= 0; 70 | else 71 | if fetch_next='1' then 72 | if R_osd_x = C_resolution_x - 1 then 73 | R_xpix <= 0; 74 | R_xcol <= 0; 75 | R_osd_x <= (others => '0'); 76 | R_osd_y <= R_osd_y+1; 77 | else 78 | if R_osd_x(0) = '0' then -- doublesize x 79 | if R_xpix = 5 then 80 | R_xpix <= 0; 81 | R_xcol <= R_xcol + 1; 82 | else 83 | R_xpix <= R_xpix + 1; 84 | end if; 85 | end if; 86 | R_osd_x <= R_osd_x+1; 87 | end if; 88 | if R_osd_x < C_digits*6*2 and R_osd_y < 16 then 89 | R_osd_out <= S_osd_pixel; 90 | else 91 | R_osd_out <= '0'; 92 | end if; 93 | end if; 94 | end if; 95 | end if; 96 | end process; 97 | osd_out <= R_osd_out; 98 | end Behavioral; 99 | -------------------------------------------------------------------------------- /proj/altera/ffm-c5a4-sd-lcdif/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | # Project Configuration: 3 | # 4 | # Specify the name of the design (project) and the Quartus II 5 | # Settings File (.qsf) 6 | ################################################################### 7 | 8 | PROJECT = project 9 | TOP_LEVEL_ENTITY = amiga_ffm_c5a4_sd 10 | ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf 11 | 12 | ################################################################### 13 | # Part, Family, Boardfile 14 | FAMILY = "Cyclone V" 15 | PART = 5CEBA4F23C7 16 | #BOARDFILE = ffm-c5a4-sd-v2r0-0.board 17 | BOARDFILE = FFM-C5A4-SD-V3r0_mit_FFC-CA7-V2r0.board 18 | CONFIG_DEVICE = EPCS64 # fixme 19 | SERIAL_FLASH_LOADER_DEVICE = EP4CE22 # fixme 20 | OPENOCD_BOARD=ffm-fpga-c5a4.ocd 21 | # OPENOCD_INTERFACE=altera-usb-blaster.ocd 22 | OPENOCD_INTERFACE=ft4232.ocd 23 | # OPENOCD_INTERFACE=remote.ocd 24 | OPENOCD_SVF_CLOCK=33MHz 25 | 26 | ################################################################### 27 | # 28 | # Quartus shell environment vars 29 | # 30 | ################################################################### 31 | 32 | quartus_env ?= . ../include/quartus_env.sh 33 | 34 | # include makefile which does it all 35 | include ../include/altera.mk 36 | 37 | ################################################################### 38 | # Setup your sources here 39 | SRCS = \ 40 | top/amiga_ffm_c5a4_sd.vhd \ 41 | ../../../Minimig_ECS/impl1/source/Fampiga.vhd \ 42 | ../../../source_emard/cfide.vhd \ 43 | ../../../Minimig_ECS/impl1/source/Debounce.vhd \ 44 | ../../../Minimig_ECS/RTL/sdram_cache.vhd \ 45 | ../../../Minimig_ECS/impl1/source/TG68K.vhd \ 46 | ../../../Minimig_ECS/impl1/source/TG68K_ALU.vhd \ 47 | ../../../Minimig_ECS/impl1/source/TG68K_Pack.vhd \ 48 | ../../../Minimig_ECS/impl1/source/TG68KdotC_Kernel.vhd \ 49 | ../../../source_emard/poweronreset.vhd \ 50 | ../../../osd_bootstrap.vhd \ 51 | ../../../jbboot.vhd \ 52 | ../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 53 | ../../../rtl_emard/vga/vga.vhd \ 54 | ../../../rtl_emard/vga/hdmi/vga2dvid.vhd \ 55 | ../../../rtl_emard/vga/hdmi/tmds_encoder.vhd \ 56 | ../../../rtl_emard/vga/altera/cyclone5/dvi_lvds.vhd \ 57 | ../../../rtl_emard/vga/adv/i2c_sender.vhd \ 58 | ../../../rtl_emard/spdif/spdif_tx.vhd \ 59 | ../../../Minimig_ECS/impl1/source/Agnus.v \ 60 | ../../../Minimig_ECS/impl1/source/Amber.v \ 61 | ../../../Minimig_ECS/impl1/source/Audio.v \ 62 | ../../../Minimig_ECS/impl1/source/Beamcounter.v \ 63 | ../../../Minimig_ECS/impl1/source/Bitplanes.v \ 64 | ../../../Minimig_ECS/impl1/source/Blitter.v \ 65 | ../../../Minimig_ECS/impl1/source/CIA8520.v \ 66 | ../../../Minimig_ECS/impl1/source/Clock.v \ 67 | ../../../Minimig_ECS/impl1/source/Copper.v \ 68 | ../../../Minimig_ECS/impl1/source/Denise.v \ 69 | ../../../Minimig_ECS/impl1/source/Floppy.v \ 70 | ../../../Minimig_ECS/impl1/source/Gary.v \ 71 | ../../../Minimig_ECS/impl1/source/Gayle.v \ 72 | ../../../source_emard/Minimig1.v \ 73 | ../../../Minimig_ECS/impl1/source/Paula.v \ 74 | ../../../source_emard/PS2Keyboard.v \ 75 | ../../../source_emard/twowaycache.v \ 76 | ../../../Minimig_ECS/impl1/source/Sprites.v \ 77 | ../../../source_emard/Userio.v \ 78 | 79 | #../../../Minimig_ECS/impl1/source/HDMI/aux_ecc1.vhd \ 80 | #../../../Minimig_ECS/impl1/source/HDMI/aux_ecc2.vhd \ 81 | #../../../Minimig_ECS/impl1/source/HDMI/aux_encoder.vhd \ 82 | #../../../source_emard/HDMI/dvid.vhd \ 83 | #../../../Minimig_ECS/impl1/source/HDMI/dvienc_defs.vhd \ 84 | #../../../Minimig_ECS/impl1/source/HDMI/edvi_ucode.vhd \ 85 | #../../../Minimig_ECS/impl1/source/HDMI/infoframe_rom_800x600_60hz_40M_48k.vhd \ 86 | #../../../Minimig_ECS/impl1/source/HDMI/TMDS_encoder.vhd \ 87 | -------------------------------------------------------------------------------- /proj/altera/ffm-c5a4-sd-lcse/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | # Project Configuration: 3 | # 4 | # Specify the name of the design (project) and the Quartus II 5 | # Settings File (.qsf) 6 | ################################################################### 7 | 8 | PROJECT = project 9 | TOP_LEVEL_ENTITY = amiga_ffm_c5a4_sd 10 | ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf 11 | 12 | ################################################################### 13 | # Part, Family, Boardfile 14 | FAMILY = "Cyclone V" 15 | PART = 5CEBA4F23C7 16 | #BOARDFILE = ffm-c5a4-sd-v2r0-0.board 17 | BOARDFILE = FFM-C5A4-SD-V2r0_mit_FFC-CA7-V2r0.board 18 | CONFIG_DEVICE = EPCS64 # fixme 19 | SERIAL_FLASH_LOADER_DEVICE = EP4CE22 # fixme 20 | OPENOCD_BOARD=ffm-fpga-c5a4.ocd 21 | # OPENOCD_INTERFACE=altera-usb-blaster.ocd 22 | OPENOCD_INTERFACE=ft4232.ocd 23 | # OPENOCD_INTERFACE=remote.ocd 24 | OPENOCD_SVF_CLOCK=33MHz 25 | 26 | ################################################################### 27 | # 28 | # Quartus shell environment vars 29 | # 30 | ################################################################### 31 | 32 | quartus_env ?= . ../include/quartus_env.sh 33 | 34 | # include makefile which does it all 35 | include ../include/altera.mk 36 | 37 | ################################################################### 38 | # Setup your sources here 39 | SRCS = \ 40 | top/amiga_ffm_c5a4_sd.vhd \ 41 | ../../../Minimig_ECS/impl1/source/Fampiga.vhd \ 42 | ../../../source_emard/cfide.vhd \ 43 | ../../../Minimig_ECS/impl1/source/Debounce.vhd \ 44 | ../../../Minimig_ECS/RTL/sdram_cache.vhd \ 45 | ../../../Minimig_ECS/impl1/source/TG68K.vhd \ 46 | ../../../Minimig_ECS/impl1/source/TG68K_ALU.vhd \ 47 | ../../../Minimig_ECS/impl1/source/TG68K_Pack.vhd \ 48 | ../../../Minimig_ECS/impl1/source/TG68KdotC_Kernel.vhd \ 49 | ../../../source_emard/poweronreset.vhd \ 50 | ../../../osd_bootstrap.vhd \ 51 | ../../../jbboot.vhd \ 52 | ../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 53 | ../../../rtl_emard/vga/vga.vhd \ 54 | ../../../rtl_emard/vga/hdmi/vga2dvid.vhd \ 55 | ../../../rtl_emard/vga/hdmi/tmds_encoder.vhd \ 56 | ../../../rtl_emard/vga/altera/cyclone5/dvi_lvds.vhd \ 57 | ../../../rtl_emard/vga/adv/i2c_sender.vhd \ 58 | ../../../rtl_emard/spdif/spdif_tx.vhd \ 59 | ../../../Minimig_ECS/impl1/source/Agnus.v \ 60 | ../../../Minimig_ECS/impl1/source/Amber.v \ 61 | ../../../Minimig_ECS/impl1/source/Audio.v \ 62 | ../../../Minimig_ECS/impl1/source/Beamcounter.v \ 63 | ../../../Minimig_ECS/impl1/source/Bitplanes.v \ 64 | ../../../Minimig_ECS/impl1/source/Blitter.v \ 65 | ../../../Minimig_ECS/impl1/source/CIA8520.v \ 66 | ../../../Minimig_ECS/impl1/source/Clock.v \ 67 | ../../../Minimig_ECS/impl1/source/Copper.v \ 68 | ../../../Minimig_ECS/impl1/source/Denise.v \ 69 | ../../../Minimig_ECS/impl1/source/Floppy.v \ 70 | ../../../Minimig_ECS/impl1/source/Gary.v \ 71 | ../../../Minimig_ECS/impl1/source/Gayle.v \ 72 | ../../../source_emard/Minimig1.v \ 73 | ../../../Minimig_ECS/impl1/source/Paula.v \ 74 | ../../../source_emard/PS2Keyboard.v \ 75 | ../../../source_emard/twowaycache.v \ 76 | ../../../Minimig_ECS/impl1/source/Sprites.v \ 77 | ../../../source_emard/Userio.v \ 78 | 79 | #../../../Minimig_ECS/impl1/source/HDMI/aux_ecc1.vhd \ 80 | #../../../Minimig_ECS/impl1/source/HDMI/aux_ecc2.vhd \ 81 | #../../../Minimig_ECS/impl1/source/HDMI/aux_encoder.vhd \ 82 | #../../../source_emard/HDMI/dvid.vhd \ 83 | #../../../Minimig_ECS/impl1/source/HDMI/dvienc_defs.vhd \ 84 | #../../../Minimig_ECS/impl1/source/HDMI/edvi_ucode.vhd \ 85 | #../../../Minimig_ECS/impl1/source/HDMI/infoframe_rom_800x600_60hz_40M_48k.vhd \ 86 | #../../../Minimig_ECS/impl1/source/HDMI/TMDS_encoder.vhd \ 87 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ulx3s_flash_is25lp032d.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-12F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp032d.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-12F 34 | 0x21111043 35 | All 36 | LFE5U-12F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | Micron 58 | SPI Serial Flash 59 | SPI-M25P32 60 | 0x15 61 | 8-pin VDFPN8 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp032d.mcs 64 | 0x00000000 65 | 0x00400000 66 | 32 67 | 4194304 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp032d.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ulx3s_flash_s25fl164k.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-12F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_s25fl164k.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-12F 34 | 0x21111043 35 | All 36 | LFE5U-12F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL164K 60 | 0x16 61 | 8-lead SOIC 62 | SPI Flash Erase,Program 63 | project/project_project_flash_s25fl164k.mcs 64 | 0x00000000 65 | 0x00800000 66 | 64 67 | 8388608 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_s25fl164k.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/include/scripts/ulx3s_flash_is25lp128f.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-12F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp128f.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-12F 34 | 0x21111043 35 | All 36 | LFE5U-12F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL128S 60 | 8-lead WSON 61 | 0x17 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp128f.mcs 64 | 0x00000000 65 | 0x01000000 66 | 128 67 | 16777216 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp128f.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_12f_flash_is25lp032d.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-12F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp032d.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-12F 34 | 0x21111043 35 | All 36 | LFE5U-12F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | Micron 58 | SPI Serial Flash 59 | SPI-M25P32 60 | 0x15 61 | 8-pin VDFPN8 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp032d.mcs 64 | 0x00000000 65 | 0x00400000 66 | 32 67 | 4194304 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp032d.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_12f_flash_s25fl164k.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-12F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_s25fl164k.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-12F 34 | 0x21111043 35 | All 36 | LFE5U-12F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL164K 60 | 0x16 61 | 8-lead SOIC 62 | SPI Flash Erase,Program 63 | project/project_project_flash_s25fl164k.mcs 64 | 0x00000000 65 | 0x00800000 66 | 64 67 | 8388608 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_s25fl164k.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_25f_flash_is25lp032d.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-25F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp032d.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-25F 34 | 0x41111043 35 | All 36 | LFE5U-25F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | Micron 58 | SPI Serial Flash 59 | SPI-M25P32 60 | 0x15 61 | 8-pin VDFPN8 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp032d.mcs 64 | 0x00000000 65 | 0x00400000 66 | 32 67 | 4194304 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp032d.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_25f_flash_s25fl164k.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-25F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_s25fl164k.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-25F 34 | 0x41111043 35 | All 36 | LFE5U-25F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL164K 60 | 0x16 61 | 8-lead SOIC 62 | SPI Flash Erase,Program 63 | project/project_project_flash_s25fl164k.mcs 64 | 0x00000000 65 | 0x01000000 66 | 128 67 | 16777216 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_s25fl164k.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_45f_flash_is25lp032d.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-45F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp032d.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-45F 34 | 0x41112043 35 | All 36 | LFE5U-45F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | Micron 58 | SPI Serial Flash 59 | SPI-M25P32 60 | 0x15 61 | 8-pin VDFPN8 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp032d.mcs 64 | 0x00000000 65 | 0x00400000 66 | 32 67 | 4194304 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp032d.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_45f_flash_s25fl164k.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-45F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_s25fl164k.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-45F 34 | 0x41112043 35 | All 36 | LFE5U-45F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL164K 60 | 0x16 61 | 8-lead SOIC 62 | SPI Flash Erase,Program 63 | project/project_project_flash_s25fl164k.mcs 64 | 0x00000000 65 | 0x00800000 66 | 64 67 | 8388608 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_s25fl164k.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_85f_flash_is25lp032d.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-85F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp032d.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-85F 34 | 0x41113043 35 | All 36 | LFE5U-85F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-85F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | Micron 58 | SPI Serial Flash 59 | SPI-M25P32 60 | 0x15 61 | 8-pin VDFPN8 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp032d.mcs 64 | 0x00000000 65 | 0x00400000 66 | 32 67 | 4194304 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp032d.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_85f_flash_s25fl164k.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-85F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_s25fl164k.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-85F 34 | 0x41113043 35 | All 36 | LFE5U-85F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-85F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL164K 60 | 0x16 61 | 8-lead SOIC 62 | SPI Flash Erase,Program 63 | project/project_project_flash_s25fl164k.mcs 64 | 0x00000000 65 | 0x01000000 66 | 128 67 | 16777216 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_s25fl164k.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_12f_flash_is25lp128f.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-12F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp128f.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-12F 34 | 0x21111043 35 | All 36 | LFE5U-12F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL128S 60 | 8-lead WSON 61 | 0x17 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp128f.mcs 64 | 0x00000000 65 | 0x01000000 66 | 128 67 | 16777216 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp128f.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_25f_flash_is25lp128f.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-25F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp128f.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-25F 34 | 0x41111043 35 | All 36 | LFE5U-25F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL128S 60 | 8-lead WSON 61 | 0x17 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp128f.mcs 64 | 0x00000000 65 | 0x01000000 66 | 128 67 | 16777216 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp128f.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_45f_flash_is25lp128f.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-45F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp128f.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-45F 34 | 0x41112043 35 | All 36 | LFE5U-45F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL128S 60 | 8-lead WSON 61 | 0x17 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp128f.mcs 64 | 0x00000000 65 | 0x01000000 66 | 128 67 | 16777216 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp128f.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /proj/lattice/programmer/ispvm/ulx3s_85f_flash_is25lp128f.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | ECP5U 12 | LFE5U-85F 13 | All 14 | 15 | 8 16 | 11111111 17 | 1 18 | 0 19 | 20 | project/project_project_flash_is25lp128f.mcs 21 | 12/23/17 00:34:50 22 | SPI Flash Erase,Program 23 | 27 | 28 | 29 | 30 | 1 31 | Lattice 32 | ECP5U 33 | LFE5U-85F 34 | 0x41113043 35 | All 36 | LFE5U-85F 37 | 38 | 8 39 | 11111111 40 | 1 41 | 0 42 | 43 | /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-85F.msk 44 | Bypass 45 | 52 | 53 | 54 | 55 | 56 | 1 57 | SPANSION 58 | SPI Serial Flash 59 | SPI-S25FL128S 60 | 8-lead WSON 61 | 0x17 62 | SPI Flash Erase,Program 63 | project/project_project_flash_is25lp128f.mcs 64 | 0x00000000 65 | 0x01000000 66 | 128 67 | 16777216 68 | 1 69 | 70 | 71 | 72 | 73 | 74 | 1 75 | 76 | project/project_project_flash_is25lp128f.mcs 77 | 78 | 81 | 82 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | SEQUENTIAL 92 | ENTIRED CHAIN 93 | No Override 94 | TLR 95 | TLR 96 | 97 | 1 98 | 99 | 100 | USB2 101 | FTUSB-0 102 | FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A 103 | 104 | 105 | -------------------------------------------------------------------------------- /rtl_emard/vga/hdmi-audio/serializer_generic.vhd: -------------------------------------------------------------------------------- 1 | -- (c) EMARD 2 | -- LICENSE=BSD 3 | 4 | -- generic (vendor-agnostic) serializer 5 | 6 | LIBRARY ieee; 7 | USE ieee.std_logic_1164.all; 8 | 9 | ENTITY serializer_generic IS 10 | GENERIC 11 | ( 12 | C_channel_bits: integer := 10; -- number of bits per channel 13 | C_output_bits: integer := 1; -- output bits per channel 14 | C_channels: integer := 3 -- number of channels to serialize 15 | ); 16 | PORT 17 | ( 18 | tx_in : IN STD_LOGIC_VECTOR(C_channel_bits*C_channels-1 DOWNTO 0); 19 | tx_inclock : IN STD_LOGIC; -- 10x tx_syncclock 20 | tx_syncclock : IN STD_LOGIC; 21 | tx_out : OUT STD_LOGIC_VECTOR((C_channels+1)*C_output_bits-1 DOWNTO 0) -- one more channel for clock 22 | ); 23 | END; 24 | 25 | ARCHITECTURE SYN OF serializer_generic IS 26 | signal R_tx_latch: std_logic_vector(C_channel_bits*C_channels-1 downto 0); 27 | signal S_tx_clock: std_logic_vector(C_channel_bits-1 downto 0); 28 | type T_channel_shift is array(0 to C_channels) of std_logic_vector(C_channel_bits-1 downto 0); -- -- one channel more for clock 29 | signal S_channel_latch, R_channel_shift: T_channel_shift; 30 | signal R_pixel_clock_toggle, R_prev_pixel_clock_toggle: std_logic; 31 | signal R_clock_edge: std_logic; 32 | constant C_shift_pad: std_logic_vector(C_output_bits-1 downto 0) := (others => '0'); 33 | BEGIN 34 | process(tx_syncclock) -- pixel clock 35 | begin 36 | if rising_edge(tx_syncclock) then 37 | R_tx_latch <= tx_in; -- add the clock to be shifted to the channels 38 | end if; 39 | end process; 40 | 41 | -- rename - separate to shifted 4 channels 42 | separate_channels: 43 | for i in 0 to C_channels-1 generate 44 | reverse_bits: 45 | for j in 0 to C_channel_bits-1 generate 46 | S_channel_latch(i)(j) <= R_tx_latch(C_channel_bits*(i+1)-j-1); 47 | end generate; 48 | end generate; 49 | 50 | S_channel_latch(3) <= "1111100000"; -- the clock pattern 51 | 52 | process(tx_syncclock) 53 | begin 54 | if rising_edge(tx_syncclock) then 55 | R_pixel_clock_toggle <= not R_pixel_clock_toggle; 56 | end if; 57 | end process; 58 | 59 | -- shift-synchronous pixel clock edge detection 60 | process(tx_inclock) -- pixel shift clock (250 MHz) 61 | begin 62 | if rising_edge(tx_inclock) then -- pixel clock (25 MHz) 63 | R_prev_pixel_clock_toggle <= R_pixel_clock_toggle; 64 | R_clock_edge <= R_pixel_clock_toggle xor R_prev_pixel_clock_toggle; 65 | end if; 66 | end process; 67 | 68 | -- fixme: initial state issue (clock shifting?) 69 | process(tx_inclock) -- pixel shift clock 70 | begin 71 | if rising_edge(tx_inclock) then 72 | if R_clock_edge='1' then -- rising edge detection 73 | R_channel_shift(0) <= S_channel_latch(0); 74 | R_channel_shift(1) <= S_channel_latch(1); 75 | R_channel_shift(2) <= S_channel_latch(2); 76 | R_channel_shift(3) <= S_channel_latch(3); 77 | else 78 | R_channel_shift(0) <= C_shift_pad & R_channel_shift(0)(C_channel_bits-1 downto C_output_bits); 79 | R_channel_shift(1) <= C_shift_pad & R_channel_shift(1)(C_channel_bits-1 downto C_output_bits); 80 | R_channel_shift(2) <= C_shift_pad & R_channel_shift(2)(C_channel_bits-1 downto C_output_bits); 81 | R_channel_shift(3) <= C_shift_pad & R_channel_shift(3)(C_channel_bits-1 downto C_output_bits); 82 | end if; 83 | end if; 84 | end process; 85 | 86 | tx_out <= R_channel_shift(3)(C_output_bits-1 downto 0) 87 | & R_channel_shift(2)(C_output_bits-1 downto 0) 88 | & R_channel_shift(1)(C_output_bits-1 downto 0) 89 | & R_channel_shift(0)(C_output_bits-1 downto 0); 90 | 91 | END SYN; 92 | -------------------------------------------------------------------------------- /rtl_emard/usb/usbhost/usbh_crc16.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------- 2 | // USB Full Speed Host 3 | // V0.5 4 | // Ultra-Embedded.com 5 | // Copyright 2015-2019 6 | // 7 | // Email: admin@ultra-embedded.com 8 | // 9 | // License: GPL 10 | // If you would like a version with a more permissive license for 11 | // use in closed source commercial applications please contact me 12 | // for details. 13 | //----------------------------------------------------------------- 14 | // 15 | // This file is open source HDL; you can redistribute it and/or 16 | // modify it under the terms of the GNU General Public License as 17 | // published by the Free Software Foundation; either version 2 of 18 | // the License, or (at your option) any later version. 19 | // 20 | // This file is distributed in the hope that it will be useful, 21 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 22 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 | // GNU General Public License for more details. 24 | // 25 | // You should have received a copy of the GNU General Public 26 | // License along with this file; if not, write to the Free Software 27 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 28 | // USA 29 | //----------------------------------------------------------------- 30 | 31 | //----------------------------------------------------------------- 32 | // Generated File 33 | //----------------------------------------------------------------- 34 | //----------------------------------------------------------------- 35 | // Module: 16-bit CRC used by USB data packets 36 | //----------------------------------------------------------------- 37 | module usbh_crc16 38 | ( 39 | input [15:0] crc_i, 40 | input [7:0] data_i, 41 | output [15:0] crc_o 42 | ); 43 | 44 | //----------------------------------------------------------------- 45 | // Implementation 46 | //----------------------------------------------------------------- 47 | assign crc_o[15] = data_i[0] ^ data_i[1] ^ data_i[2] ^ data_i[3] ^ data_i[4] ^ 48 | data_i[5] ^ data_i[6] ^ data_i[7] ^ crc_i[7] ^ crc_i[6] ^ 49 | crc_i[5] ^ crc_i[4] ^ crc_i[3] ^ crc_i[2] ^ 50 | crc_i[1] ^ crc_i[0]; 51 | assign crc_o[14] = data_i[0] ^ data_i[1] ^ data_i[2] ^ data_i[3] ^ data_i[4] ^ data_i[5] ^ 52 | data_i[6] ^ crc_i[6] ^ crc_i[5] ^ crc_i[4] ^ 53 | crc_i[3] ^ crc_i[2] ^ crc_i[1] ^ crc_i[0]; 54 | assign crc_o[13] = data_i[6] ^ data_i[7] ^ crc_i[7] ^ crc_i[6]; 55 | assign crc_o[12] = data_i[5] ^ data_i[6] ^ crc_i[6] ^ crc_i[5]; 56 | assign crc_o[11] = data_i[4] ^ data_i[5] ^ crc_i[5] ^ crc_i[4]; 57 | assign crc_o[10] = data_i[3] ^ data_i[4] ^ crc_i[4] ^ crc_i[3]; 58 | assign crc_o[9] = data_i[2] ^ data_i[3] ^ crc_i[3] ^ crc_i[2]; 59 | assign crc_o[8] = data_i[1] ^ data_i[2] ^ crc_i[2] ^ crc_i[1]; 60 | assign crc_o[7] = data_i[0] ^ data_i[1] ^ crc_i[15] ^ crc_i[1] ^ crc_i[0]; 61 | assign crc_o[6] = data_i[0] ^ crc_i[14] ^ crc_i[0]; 62 | assign crc_o[5] = crc_i[13]; 63 | assign crc_o[4] = crc_i[12]; 64 | assign crc_o[3] = crc_i[11]; 65 | assign crc_o[2] = crc_i[10]; 66 | assign crc_o[1] = crc_i[9]; 67 | assign crc_o[0] = data_i[0] ^ data_i[1] ^ data_i[2] ^ data_i[3] ^ data_i[4] ^ data_i[5] ^ 68 | data_i[6] ^ data_i[7] ^ crc_i[8] ^ crc_i[7] ^ crc_i[6] ^ 69 | crc_i[5] ^ crc_i[4] ^ crc_i[3] ^ crc_i[2] ^ 70 | crc_i[1] ^ crc_i[0]; 71 | 72 | endmodule 73 | 74 | -------------------------------------------------------------------------------- /rtl_emard/lattice/ulx3s/clocks/DVI_PLL.vhd: -------------------------------------------------------------------------------- 1 | -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 2 | -- Module Version: 5.7 3 | --C:\lscc\diamond\3.9_x64\ispfpga\bin\nt64\scuba.exe -w -n DVI_PLL -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25 -fclkop 112.5 -fclkop_tol 5.0 -fclkos 140.625 -fclkos_tol 2.0 -phases 0 -fclkos2 140.625 -fclkos2_tol 2.0 -phases2 90 -phase_cntl STATIC -fb_mode 1 -fdc C:/lscc/diamond/3.3_x64/examples/Flea_zero_Amiga_HDMI/RTL/DVI_PLL/DVI_PLL.fdc 4 | 5 | -- Mon Aug 21 18:35:42 2017 6 | 7 | library IEEE; 8 | use IEEE.std_logic_1164.all; 9 | library ECP5U; 10 | use ECP5U.components.all; 11 | 12 | entity DVI_PLL is 13 | port ( 14 | CLKI: in std_logic; 15 | CLKOP: out std_logic; 16 | CLKOS: out std_logic; 17 | CLKOS2: out std_logic); 18 | end DVI_PLL; 19 | 20 | architecture Structure of DVI_PLL is 21 | 22 | -- internal signal declarations 23 | signal REFCLK: std_logic; 24 | signal LOCK: std_logic; 25 | signal CLKOS2_t: std_logic; 26 | signal CLKOS_t: std_logic; 27 | signal CLKOP_t: std_logic; 28 | signal scuba_vhi: std_logic; 29 | signal scuba_vlo: std_logic; 30 | 31 | attribute FREQUENCY_PIN_CLKOS2 : string; 32 | attribute FREQUENCY_PIN_CLKOS : string; 33 | attribute FREQUENCY_PIN_CLKOP : string; 34 | attribute FREQUENCY_PIN_CLKI : string; 35 | attribute ICP_CURRENT : string; 36 | attribute LPF_RESISTOR : string; 37 | attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "140.625000"; 38 | attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "140.625000"; 39 | attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "112.500000"; 40 | attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "25.000000"; 41 | attribute ICP_CURRENT of PLLInst_0 : label is "5"; 42 | attribute LPF_RESISTOR of PLLInst_0 : label is "16"; 43 | attribute syn_keep : boolean; 44 | attribute NGD_DRC_MASK : integer; 45 | attribute NGD_DRC_MASK of Structure : architecture is 1; 46 | 47 | begin 48 | -- component instantiation statements 49 | scuba_vhi_inst: VHI 50 | port map (Z=>scuba_vhi); 51 | 52 | scuba_vlo_inst: VLO 53 | port map (Z=>scuba_vlo); 54 | 55 | PLLInst_0: EHXPLLL 56 | generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 57 | STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 58 | CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, 59 | CLKOS2_CPHASE=> 4, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 3, 60 | CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 4, PLL_LOCK_MODE=> 0, 61 | CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", 62 | CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", 63 | OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 64 | OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", 65 | OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", 66 | OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, 67 | CLKOS2_DIV=> 4, CLKOS_DIV=> 4, CLKOP_DIV=> 5, CLKFB_DIV=> 9, 68 | CLKI_DIV=> 2, FEEDBK_PATH=> "CLKOP") 69 | port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 70 | PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 71 | PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 72 | STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 73 | ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 74 | ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, 75 | CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 76 | REFCLK=>REFCLK, CLKINTFB=>open); 77 | 78 | CLKOS2 <= CLKOS2_t; 79 | CLKOS <= CLKOS_t; 80 | CLKOP <= CLKOP_t; 81 | end Structure; 82 | -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-ps2kbd/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROJ_FILE := $(shell ls *.ldf | head -1) 3 | PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4) 4 | IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8) 5 | IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4) 6 | 7 | DIAMOND_BASE := /usr/local/diamond 8 | DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1) 9 | DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc) 10 | DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd) 11 | 12 | OPENOCD_BASE := ../../programmer/openocd/ulx3s/ 13 | 14 | # name of the project as defined in project file 15 | PROJECT = project 16 | 17 | JUNK = ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml 18 | JUNK += dummy_sym.sort project_tcl.html promote.xml 19 | JUNK += generate_core.tcl generate_ngd.tcl msg_file.log 20 | JUNK += project_tcr.dir 21 | 22 | all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme 23 | 24 | $(PROJECT)/$(PROJECT)_$(PROJECT).bit: 25 | echo prj_project open ${PROJ_FILE} \; prj_run Export -task Bitgen | ${DIAMONDC} 26 | 27 | $(PROJECT)/$(PROJECT)_$(PROJECT).mcs: 28 | LANG=C ${DDTCMD} -dev LFE5U-25F -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit -oft -int -of $(PROJECT)/$(PROJECT)_$(PROJECT).mcs 29 | 30 | $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).bit 31 | LANG=C ${DDTCMD} -oft -fullvme -if fleafpga_ohm_sram.xcf -nocompress -noheader -of $@ 32 | 33 | $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs 34 | LANG=C ${DDTCMD} -oft -fullvme -if fleafpga_ohm_flash.xcf -noheader -of $@ 35 | 36 | $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).bit 37 | LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if fleafpga_ohm_sram.xcf -of $@ 38 | 39 | $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs 40 | LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if fleafpga_ohm_flash.xcf -of $@ 41 | 42 | program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit 43 | echo pgr_project open fleafpga_ohm_sram.xcf \; pgr_program run | ${DIAMONDC} 44 | 45 | program_wifi: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf 46 | openocd --file=$(OPENOCD_BASE)/remote.ocd --file=$(OPENOCD_BASE)/ecp5-25f.ocd 47 | 48 | program_ft2232: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf 49 | openocd --file=$(OPENOCD_BASE)/ft2232-fpu1.ocd --file=$(OPENOCD_BASE)/ecp5-25f.ocd 50 | 51 | program_flea: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme 52 | FleaFPGA-JTAG $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme 53 | 54 | program_flea_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme 55 | FleaFPGA-JTAG $< 56 | 57 | $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs 58 | LANG=C ${DDTCMD} -oft -fullvme -if fleafpga_ohm_flash.xcf -nocompress -noheader -of $@ 59 | 60 | #$(PROJECT)/$(PROJECT)_$(PROJECT).jed: 61 | # echo prj_project open ${PROJ_FILE} \; prj_run Export -task Jedecgen | ${DIAMONDC} 62 | 63 | #$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).jed 64 | # ${DDTCMD} -oft -fullvme -if sparrowhawk_flash.xcf -nocompress -noheader -of $@ 65 | 66 | #$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).jed 67 | # ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ 68 | 69 | flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme 70 | FleaFPGA-JTAG $< 71 | 72 | # example another project 73 | #%.svf : %.jed 74 | # ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ 75 | # mv -f $@ $@.flash 76 | # ${DDTCMD} -oft -svfsingle -revd -op "SRAM Fast Program" -if $< -of $@ 77 | # mv -f $@ $@.sram 78 | # ./svf_to_urjtag.pl <$@.flash | sed 's/,/./g' > $@ 79 | 80 | clean: 81 | rm -rf $(JUNK) *~ 82 | -------------------------------------------------------------------------------- /proj/lattice/fleafpga-ohm-usbjoy/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROJ_FILE := $(shell ls *.ldf | head -1) 3 | PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4) 4 | IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8) 5 | IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4) 6 | 7 | DIAMOND_BASE := /usr/local/diamond 8 | DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1) 9 | DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc) 10 | DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd) 11 | 12 | OPENOCD_BASE := ../../programmer/openocd/ulx3s/ 13 | 14 | # name of the project as defined in project file 15 | PROJECT = project 16 | 17 | JUNK = ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml 18 | JUNK += dummy_sym.sort project_tcl.html promote.xml 19 | JUNK += generate_core.tcl generate_ngd.tcl msg_file.log 20 | JUNK += project_tcr.dir 21 | 22 | all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme 23 | 24 | $(PROJECT)/$(PROJECT)_$(PROJECT).bit: 25 | echo prj_project open ${PROJ_FILE} \; prj_run Export -task Bitgen | ${DIAMONDC} 26 | 27 | $(PROJECT)/$(PROJECT)_$(PROJECT).mcs: 28 | LANG=C ${DDTCMD} -dev LFE5U-25F -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit -oft -int -of $(PROJECT)/$(PROJECT)_$(PROJECT).mcs 29 | 30 | $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).bit 31 | LANG=C ${DDTCMD} -oft -fullvme -if fleafpga_ohm_sram.xcf -nocompress -noheader -of $@ 32 | 33 | $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs 34 | LANG=C ${DDTCMD} -oft -fullvme -if fleafpga_ohm_flash.xcf -noheader -of $@ 35 | 36 | $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).bit 37 | LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if fleafpga_ohm_sram.xcf -of $@ 38 | 39 | $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs 40 | LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if fleafpga_ohm_flash.xcf -of $@ 41 | 42 | program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit 43 | echo pgr_project open fleafpga_ohm_sram.xcf \; pgr_program run | ${DIAMONDC} 44 | 45 | program_wifi: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf 46 | openocd --file=$(OPENOCD_BASE)/remote.ocd --file=$(OPENOCD_BASE)/ecp5-25f.ocd 47 | 48 | program_ft2232: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf 49 | openocd --file=$(OPENOCD_BASE)/ft2232-fpu1.ocd --file=$(OPENOCD_BASE)/ecp5-25f.ocd 50 | 51 | program_flea: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme 52 | FleaFPGA-JTAG $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme 53 | 54 | program_flea_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme 55 | FleaFPGA-JTAG $< 56 | 57 | $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs 58 | LANG=C ${DDTCMD} -oft -fullvme -if fleafpga_ohm_flash.xcf -nocompress -noheader -of $@ 59 | 60 | #$(PROJECT)/$(PROJECT)_$(PROJECT).jed: 61 | # echo prj_project open ${PROJ_FILE} \; prj_run Export -task Jedecgen | ${DIAMONDC} 62 | 63 | #$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).jed 64 | # ${DDTCMD} -oft -fullvme -if sparrowhawk_flash.xcf -nocompress -noheader -of $@ 65 | 66 | #$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).jed 67 | # ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ 68 | 69 | flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme 70 | FleaFPGA-JTAG $< 71 | 72 | # example another project 73 | #%.svf : %.jed 74 | # ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ 75 | # mv -f $@ $@.flash 76 | # ${DDTCMD} -oft -svfsingle -revd -op "SRAM Fast Program" -if $< -of $@ 77 | # mv -f $@ $@.sram 78 | # ./svf_to_urjtag.pl <$@.flash | sed 's/,/./g' > $@ 79 | 80 | clean: 81 | rm -rf $(JUNK) *~ 82 | -------------------------------------------------------------------------------- /proj/lattice/ffm-lfe5-lcdif/universal_make_ps2kbd/files.mk: -------------------------------------------------------------------------------- 1 | VHDL_FILES = $(TOP_MODULE_FILE) \ 2 | ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK0_NAME)_vhdl.vhd \ 3 | ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK1_NAME)_vhdl.vhd \ 4 | ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK2_NAME)_vhdl.vhd \ 5 | ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK3_NAME)_vhdl.vhd \ 6 | ../../../../Minimig_ECS/impl1/source/Fampiga.vhd \ 7 | ../../../../source_emard/cfide.vhd \ 8 | ../../../../Minimig_ECS/impl1/source/Debounce.vhd \ 9 | ../../../../Minimig_ECS/impl1/source/TG68K.vhd \ 10 | ../../../../Minimig_ECS/impl1/source/TG68K_ALU.vhd \ 11 | ../../../../Minimig_ECS/impl1/source/TG68K_Pack.vhd \ 12 | ../../../../Minimig_ECS/impl1/source/TG68KdotC_Kernel.vhd \ 13 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_ecc1.vhd \ 14 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_ecc2.vhd \ 15 | ../../../../Minimig_ECS/impl1/source/HDMI/aux_encoder.vhd \ 16 | ../../../../source_emard/HDMI/dvid.vhd \ 17 | ../../../../Minimig_ECS/impl1/source/HDMI/dvienc_defs.vhd \ 18 | ../../../../Minimig_ECS/impl1/source/HDMI/edvi_ucode.vhd \ 19 | ../../../../Minimig_ECS/impl1/source/HDMI/infoframe_rom_800x600_60hz_40M_48k.vhd \ 20 | ../../../../Minimig_ECS/impl1/source/HDMI/TMDS_encoder.vhd \ 21 | ../../../../source_emard/poweronreset.vhd \ 22 | ../../../../osd_bootstrap.vhd \ 23 | ../../../../jbboot.vhd \ 24 | ../../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 25 | ../../../../rtl_emard/vga/vga.vhd \ 26 | ../../../../rtl_emard/vga/hdmi/vga2dvid.vhd \ 27 | ../../../../rtl_emard/vga/hdmi/tmds_encoder.vhd \ 28 | ../../../../rtl_emard/vga/lattice/ecp5u/ddr_out_emard.vhd \ 29 | ../../../../rtl_emard/vga/adv/i2c_sender.vhd \ 30 | ../../../../rtl_emard/spdif/spdif_tx.vhd \ 31 | ../../../../rtl_emard/osd/char_rom.vhd \ 32 | ../../../../rtl_emard/generic/bram_true2p_1clk.vhd \ 33 | ../../../../Minimig_ECS/RTL/sdram_cache.vhd \ 34 | 35 | 36 | #../../../../rtl_emard/usb/usbhid/usbhid_report_decoder_saitek_joystick.vhd \ 37 | #../../../../rtl_emard/usb/usbhid/report_decoded_pack_generic.vhd \ 38 | #../../../../rtl_emard/usb/usbhost/usbh_setup_pack.vhd \ 39 | #../../../../rtl_emard/usb/usbhost/usbh_host_hid.vhd \ 40 | #../../../../rtl_emard/usb/usbhost/usbh_sie_vhdl.vhd \ 41 | #../../../../rtl_emard/usb/usb11_phy_vhdl/usb_phy.vhd \ 42 | #../../../../rtl_emard/usb/usb11_phy_vhdl/usb_rx_phy_48MHz.vhd \ 43 | #../../../../rtl_emard/usb/usb11_phy_vhdl/usb_tx_phy.vhd \ 44 | 45 | 46 | # sdram controllers 47 | # ../../../../rtl_emard/sdram/sdram.vhd \ 48 | # ../../../../Minimig_ECS/RTL/sdram_cache.vhd \ 49 | 50 | VERILOG_FILES = \ 51 | ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK0_NAME).v \ 52 | ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK1_NAME).v \ 53 | ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK2_NAME).v \ 54 | ../../../../rtl_emard/lattice/ulx3s/clocks/$(CLK3_NAME).v \ 55 | ../../../../Minimig_ECS/impl1/source/Agnus.v \ 56 | ../../../../Minimig_ECS/impl1/source/Amber.v \ 57 | ../../../../Minimig_ECS/impl1/source/Audio.v \ 58 | ../../../../Minimig_ECS/impl1/source/Beamcounter.v \ 59 | ../../../../Minimig_ECS/impl1/source/Bitplanes.v \ 60 | ../../../../Minimig_ECS/impl1/source/Blitter.v \ 61 | ../../../../Minimig_ECS/impl1/source/CIA8520.v \ 62 | ../../../../Minimig_ECS/impl1/source/Clock.v \ 63 | ../../../../Minimig_ECS/impl1/source/Copper.v \ 64 | ../../../../Minimig_ECS/impl1/source/Denise.v \ 65 | ../../../../Minimig_ECS/impl1/source/Floppy.v \ 66 | ../../../../Minimig_ECS/impl1/source/Gary.v \ 67 | ../../../../Minimig_ECS/impl1/source/Gayle.v \ 68 | ../../../../source_emard/Minimig1.v \ 69 | ../../../../Minimig_ECS/impl1/source/Paula.v \ 70 | ../../../../source_emard/PS2Keyboard.v \ 71 | ../../../../source_emard/twowaycache.v \ 72 | ../../../../Minimig_ECS/impl1/source/Sprites.v \ 73 | ../../../../source_emard/Userio.v \ 74 | ../../../../rtl_emard/usb/usbhost/usbh_sie.v \ 75 | ../../../../rtl_emard/usb/usbhost/usbh_crc5.v \ 76 | ../../../../rtl_emard/usb/usbhost/usbh_crc16.v \ 77 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcse-vivado/makefile: -------------------------------------------------------------------------------- 1 | #vivado=/opt/Xilinx/Vivado/2015.3/bin/vivado 2 | project=amiga_ffm_a7100 3 | xc3sprog_interface = ft4232h_fast 4 | #xc3sprog_interface = ft4232h 5 | # name of resulting bitstream file (*.bit) 6 | bitfile=$(project).runs/impl_1/amiga_ffm_a7100.bit 7 | 8 | junk=*~ 9 | junk+=.Xil vivado.log vivado.jou ip_upgrade.log 10 | junk+=$(project).ip_user_files 11 | junk+=$(project).sim 12 | junk+=$(project).cache 13 | 14 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.upgrade_log 15 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.v 16 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.vh 17 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.vhdl 18 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.dcp 19 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.xml 20 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.xdc 21 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.veo 22 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.vho 23 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.tcl 24 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.ncf 25 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.log 26 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/doc 27 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/sim 28 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/synth 29 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/clk_wiz_v5_3_1 30 | 31 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.upgrade_log 32 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.v 33 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.vh 34 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.vhdl 35 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.dcp 36 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.xml 37 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.xdc 38 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.veo 39 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.vho 40 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.tcl 41 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.ncf 42 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.log 43 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/doc 44 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/sim 45 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/synth 46 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/clk_wiz_v5_3_1 47 | 48 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.upgrade_log 49 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.v 50 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.vh 51 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.vhdl 52 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.dcp 53 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.xml 54 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.xdc 55 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.veo 56 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.vho 57 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.tcl 58 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.ncf 59 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.log 60 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/doc 61 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/sim 62 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/synth 63 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/clk_wiz_v5_3_1 64 | 65 | include ../include/vivado.mk 66 | -------------------------------------------------------------------------------- /proj/xilinx/ffm-a7100-lcdif-vivado/makefile: -------------------------------------------------------------------------------- 1 | #vivado=/opt/Xilinx/Vivado/2015.3/bin/vivado 2 | project=amiga_ffm_a7100 3 | xc3sprog_interface = ft4232h_fast 4 | #xc3sprog_interface = ft4232h 5 | # name of resulting bitstream file (*.bit) 6 | bitfile=$(project).runs/impl_1/amiga_ffm_a7100.bit 7 | 8 | junk=*~ 9 | junk+=.Xil vivado.log vivado.jou ip_upgrade.log 10 | junk+=$(project).ip_user_files 11 | junk+=$(project).sim 12 | junk+=$(project).cache 13 | 14 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.upgrade_log 15 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.v 16 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.vh 17 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.vhdl 18 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.dcp 19 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.xml 20 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.xdc 21 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.veo 22 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.vho 23 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.tcl 24 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.ncf 25 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/*.log 26 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/doc 27 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/sim 28 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/synth 29 | junk+=$(project).srcs/sources_1/ip/clk_d100_112_7_28_140_280MHz/clk_wiz_v5_3_1 30 | 31 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.upgrade_log 32 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.v 33 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.vh 34 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.vhdl 35 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.dcp 36 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.xml 37 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.xdc 38 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.veo 39 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.vho 40 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.tcl 41 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.ncf 42 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/*.log 43 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/doc 44 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/sim 45 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/synth 46 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_120MHz/clk_wiz_v5_3_1 47 | 48 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.upgrade_log 49 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.v 50 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.vh 51 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.vhdl 52 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.dcp 53 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.xml 54 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.xdc 55 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.veo 56 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.vho 57 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.tcl 58 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.ncf 59 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/*.log 60 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/doc 61 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/sim 62 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/synth 63 | junk+=$(project).srcs/sources_1/ip/clk_d100_7_28_140_280_105MHz/clk_wiz_v5_3_1 64 | 65 | include ../include/vivado.mk 66 | --------------------------------------------------------------------------------