├── README.md ├── clocks └── README.md ├── constraints ├── FFM-LFE5U-V0r0_mit_FFC-CA7-V2r0.lpf ├── ulx3s_v20.lpf ├── ulx3s_v20_extgpdi.lpf ├── ulx3s_v20_sd4bit.lpf ├── ulx3s_v20_segpdi.lpf ├── ulx3s_v314.lpf ├── ulx3s_v316.lpf └── ulx4m_v002.lpf ├── examples ├── adc │ ├── adc_lcd_lvds │ │ ├── hdl │ │ │ └── top │ │ │ │ └── top_hex_480x272.v │ │ └── proj │ │ │ └── lattice │ │ │ └── ulx3s │ │ │ ├── Makefile │ │ │ ├── constraints │ │ │ └── ulx3s_v20.lpf │ │ │ ├── hex_font.mem │ │ │ ├── makefile.diamond │ │ │ └── makefile.trellis │ ├── adc_oled │ │ ├── hdl │ │ │ └── top │ │ │ │ └── ulx3s_adc_oled.vhd │ │ └── proj │ │ │ └── lattice │ │ │ └── ulx3s │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ └── makefile.diamond │ └── max1112x │ │ └── hdl │ │ ├── max1112x_init_pack.vhd │ │ ├── max1112x_reader_array.vhd │ │ └── max1112x_reader_shift.vhd ├── adxl355 │ ├── esp32 │ │ ├── adxl355.py │ │ └── pps.py │ ├── pc │ │ └── gps2ulx3s.py │ ├── proj │ │ ├── Makefile │ │ ├── constraints │ │ │ └── ulx3s_v20.lpf │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── top │ │ │ └── top_adxl355.v │ └── projbig │ │ ├── Makefile │ │ ├── README.md │ │ ├── constraints │ │ └── ulx3s_v20.lpf │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── rtl │ │ ├── adxl355_sync.v │ │ └── adxl355rd.v │ │ └── top │ │ └── top_adxl355log.v ├── audio │ ├── Makefile │ ├── README.md │ ├── hdl │ │ ├── dacpwm.v │ │ ├── dacpwm_vhdl.vhd │ │ ├── i2s.vhd │ │ ├── i2s_v.v │ │ ├── sinewave.v │ │ ├── spdif_tx.vhd │ │ ├── squarewave.v │ │ ├── top_audio.v │ │ └── trianglewave.v │ ├── makefile.diamond │ ├── makefile.trellis │ └── testbench │ │ └── sinewave.c ├── bram │ └── hdl │ │ ├── bram_true2p_2clk.v │ │ └── bram_true2p_2clk.vhd ├── btn_debounce │ └── hdl │ │ └── btn_debounce.v ├── collatz │ ├── hdl │ │ ├── collatz_conjecture.v │ │ └── random_counter.v │ └── proj │ │ ├── Makefile │ │ ├── README.md │ │ ├── collatz.py │ │ ├── filesv.mk │ │ ├── hex_font.mem │ │ ├── makefilev.diamond │ │ ├── makefilev.trellis │ │ ├── ssd1331_linit_xflip_16bit.mem │ │ ├── st7789_linit_xflip.mem │ │ └── top │ │ └── verilog │ │ └── ulx3s_collatz_test.v ├── db9joy │ ├── Makefile │ ├── hdl │ │ └── db9joy.v │ ├── makefile.diamond │ ├── makefile.trellis │ └── pinout.txt ├── dvi │ ├── Makefile │ ├── README.md │ ├── hdl │ │ ├── blink.vhd │ │ ├── fake_differential.v │ │ ├── tmds_encoder.vhd │ │ ├── vga.vhd │ │ └── vga2dvid.vhd │ ├── makefile.diamond │ ├── makefile.trellis │ ├── makefilevhdl.diamond │ ├── makefilevhdl.trellis │ └── top │ │ ├── empty.v │ │ ├── top_vgatest.v │ │ └── vhdl │ │ └── top_vgatest.vhd ├── dvi_in │ ├── hdl │ │ ├── deserialiser_1_to_10.vhd │ │ ├── dvi2vga.vhd │ │ ├── edid_rom.vhd │ │ ├── serialiser_10_to_x.vhd │ │ ├── tmds_dekoder.vhd │ │ └── tmds_deserializer.vhd │ └── proj │ │ ├── Makefile │ │ ├── README.md │ │ ├── constraints │ │ ├── ulx3s_v20.lpf │ │ └── ulx3s_v31.lpf │ │ ├── hex_font.mem │ │ ├── st7789_linit_xflip.mem │ │ └── top │ │ ├── top_v20_dvi_in.vhd │ │ └── top_v31_dvi_in.vhd ├── dvi_osd │ ├── Makefile │ ├── esp32 │ │ ├── osd.py │ │ └── spiram.py │ ├── font_bizcat8x16.mem │ ├── hdl │ │ ├── font_bizcat8x16.mem │ │ ├── osd.v │ │ ├── osd_vhd.vhd │ │ ├── spi_osd.vhd │ │ ├── spi_osd_v.v │ │ ├── spi_ram_btn.vhd │ │ └── spi_ram_btn_v.v │ ├── makefile.diamond │ ├── makefile.trellis │ ├── makefilevhdl.trellis │ ├── osd.mem │ ├── osd.txt │ └── top │ │ ├── top_spi_char.v │ │ └── vhdl │ │ └── top_spi_char.vhd ├── ecp5pll │ ├── Makefile │ ├── hdl │ │ ├── sv │ │ │ └── ecp5pll.sv │ │ └── vhd │ │ │ └── ecp5pll.vhd │ ├── makefile.diamond │ ├── makefile.trellis │ ├── makefilesv.diamond │ ├── makefilesv.trellis │ └── top │ │ ├── v │ │ └── top_ecp5pll.v │ │ └── vhd │ │ └── top_ecp5pll.vhd ├── eink │ ├── driver │ │ └── esp32 │ │ │ └── IL382x.py │ ├── eink154 │ │ ├── README.md │ │ ├── esp32 │ │ │ ├── IL382x.py │ │ │ ├── eink.py │ │ │ └── heltec_eink154bw200x200.py │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ └── top │ │ │ └── top_eink.v │ ├── epaper290 │ │ ├── README.md │ │ ├── esp32 │ │ │ ├── IL382x.py │ │ │ ├── epaper.py │ │ │ └── waveshare_epaper290bw296x128.py │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ └── top │ │ │ └── top_eink.v │ └── misc │ │ └── line_bresenham.py ├── esp32_passthru │ └── proj │ │ ├── Makefile │ │ ├── README.md │ │ ├── hdl │ │ └── esp32_passthru.v │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── top │ │ └── top_esp32_passthru.v ├── esp32_rmii │ ├── esp32 │ │ └── lan8720wrover.py │ └── proj │ │ ├── Makefile │ │ ├── README.md │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── top │ │ └── esp32rmii.v ├── eth │ └── rmii │ │ └── proj │ │ ├── Makefile │ │ ├── README.md │ │ ├── arp_reply.mem │ │ ├── ethpack.py │ │ ├── hex_font.mem │ │ ├── icmp_reply.mem │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── st7789_linit_xflip.mem │ │ └── top │ │ └── top_eth_hex_demo.v ├── flash_passthru │ └── proj │ │ ├── Makefile │ │ ├── README.md │ │ ├── constraints │ │ ├── ulx3s_v20_flash.lpf │ │ ├── ulx3s_v314_flash.lpf │ │ └── ulx3s_v316_flash.lpf │ │ ├── flashrom.layout │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── top │ │ └── flash_passthru.v ├── fm │ ├── Makefile │ ├── hdl │ │ ├── bram_rds.vhd │ │ ├── fir.vhd │ │ ├── fm.vhd │ │ ├── fmgen.vhd │ │ ├── lowpass.vhd │ │ ├── message_ps.vhd │ │ ├── message_ps_rt.vhd │ │ ├── rds.vhd │ │ └── test │ │ │ └── fmgen_test.vhd │ ├── makefilevhdl.trellis │ └── top │ │ ├── message_ps.mem │ │ └── top_fm.v ├── gray_counter │ ├── hdl │ │ ├── v │ │ │ └── gray_counter.v │ │ └── vhd │ │ │ └── gray_counter.vhd │ └── proj │ │ ├── Makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── makefilev.trellis │ │ └── top │ │ ├── v │ │ ├── empty.v │ │ └── ulx3s_gray_counter.v │ │ └── vhd │ │ └── ulx3s_gray_counter.vhd ├── hex │ ├── decoder │ │ ├── README.md │ │ ├── hex_decoder.vhd │ │ ├── hex_decoder_v.v │ │ ├── hex_font.mem │ │ └── hex_font_h.mem │ ├── dvi_hex │ │ ├── hdl │ │ │ └── top_hex_640x480.v │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── hex_font.mem │ │ │ ├── makefile.diamond │ │ │ └── makefile.trellis │ ├── lcd_lvds_hex │ │ ├── hdl │ │ │ └── top_hex_480x272.v │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── hex_font.mem │ │ │ ├── makefile-480x272.diamond │ │ │ └── makefile-480x272.trellis │ ├── lcd_st7789_hex │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── hex_font.mem │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ └── st7789_linit_xflip.mem │ ├── oled_ssd1306_hex │ │ └── proj │ │ │ ├── README.md │ │ │ ├── hex_font_h.mem │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── ssd1306_linit_xflip.mem │ │ │ ├── ssd1306_linit_yflip.mem │ │ │ └── ssd1306_oinit_xflip.mem │ ├── oled_ssd1331_hex │ │ └── proj │ │ │ ├── README.md │ │ │ ├── hex_font.mem │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── oled_init_xflip.mem │ │ │ ├── oled_init_xflip_16bit.mem │ │ │ └── ssd1331_linit_xflip_16bit.mem │ └── oled_ssd1351_hex │ │ └── proj │ │ ├── README.md │ │ ├── hex_font.mem │ │ ├── makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── ssd1351_linit_xflip_16bit.mem │ │ └── ssd1351_oinit_xflip_16bit.mem ├── jtag_slave │ ├── doc │ │ └── jtag-slave.pdf │ ├── hdl │ │ ├── jtag_slave.v │ │ ├── jtag_slave_clk.v │ │ ├── tap_defines.v │ │ └── top │ │ │ ├── top_jtag_slave.v │ │ │ ├── top_jtag_slave_passthru.v │ │ │ └── top_jtagg_slave.v │ └── proj │ │ ├── ulx3s_jtag_hex_passthru_v │ │ ├── Arduino │ │ │ ├── jtagwalkesp32 │ │ │ │ ├── jtagwalkesp32.ino │ │ │ │ ├── libxsvf.h │ │ │ │ ├── tap.cpp │ │ │ │ └── tap.h │ │ │ └── spiesp32 │ │ │ │ └── spiesp32.ino │ │ ├── README.md │ │ ├── constraints │ │ │ └── ulx3s_v20_sdio_segpdi.lpf │ │ ├── makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── oled_font.mem │ │ ├── oled_init.mem │ │ ├── oled_init_xflip.mem │ │ └── oled_init_yflip.mem │ │ ├── ulx3s_jtag_hex_v │ │ ├── README.md │ │ ├── jtag-slave-scan.ocd │ │ ├── jtag-slave-test.svf │ │ ├── makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── oled_font.mem │ │ ├── oled_init.mem │ │ ├── oled_init_xflip.mem │ │ └── oled_init_yflip.mem │ │ └── ulx3s_jtagg_hex_v │ │ ├── Makefile │ │ ├── README.md │ │ ├── hex_font.mem │ │ ├── jtagg-slave-scan.ocd │ │ ├── jtagg-slave-test.svf │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── st7789_linit_xflip.mem ├── jtagthru │ ├── hdl │ │ └── jtagthru.v │ └── proj │ │ └── ulx3s_jtagthru │ │ ├── README.md │ │ ├── makefile │ │ ├── makefile.diamond │ │ └── makefile.trellis ├── lcd35 │ ├── README.md │ ├── box │ │ └── lcd35.scad │ ├── proj │ │ └── lattice │ │ │ └── ulx3s │ │ │ ├── makefile.diamond │ │ │ └── makefile.trellis │ └── rtl │ │ ├── lattice │ │ ├── clocks_diamond │ │ │ └── clk_25m_287m5_19m17.v │ │ ├── clocks_trellis │ │ │ └── clk_25m_287m5_19m17.v │ │ └── top │ │ │ ├── top_90deg.v │ │ │ └── top_cable.v │ │ └── video.v ├── lcd_st7789 │ └── micropython │ │ ├── st7789_240x240 │ │ ├── README.md │ │ ├── esp32 │ │ │ ├── st7789py.py │ │ │ ├── test_st7789.py │ │ │ └── vectorfont.py │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ └── top │ │ │ └── top_st7789.v │ │ └── st7789_240x240_polyline │ │ ├── esp32 │ │ ├── polytest314.py │ │ ├── polytest316.py │ │ ├── st7789poly.py │ │ ├── st7789vfont.py │ │ ├── stclock.py │ │ └── test.py │ │ └── proj │ │ ├── Makefile │ │ ├── hdl │ │ ├── draw_line.v │ │ ├── draw_polyline.v │ │ ├── lcd_hvline.v │ │ └── st7789_linit_pixels.mem │ │ ├── hex_font.mem │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── st7789_linit.mem │ │ ├── st7789_linit_pixels.mem │ │ ├── st7789_linit_xflip.mem │ │ └── top │ │ ├── top_st7789_spi_slave.v │ │ ├── top_st7789_spi_slave_polyline.v │ │ ├── top_st7789_spi_slave_polyline_v314.v │ │ └── top_st7789_spi_slave_polyline_v316.v ├── led64x64 │ ├── README.md │ ├── emard │ │ ├── ledscan.vhd │ │ └── top.v │ ├── makefile.diamond │ └── makefile.trellis ├── lvds │ └── hdl │ │ ├── lvds2vga.vhd │ │ ├── vga2lvds.vhd │ │ └── vga2lvds_old.vhd ├── lvds_passthru │ ├── Makefile │ ├── constraints │ │ └── ulx3s_v20.lpf │ ├── hdl │ │ └── top_lvds_passthru.vhd │ ├── makefile.diamond │ └── makefile.trellis ├── multiboot │ ├── Makefile │ ├── README.md │ ├── bitstream0 │ │ ├── Makefile │ │ ├── bitstream0.v │ │ └── makefile.trellis │ ├── bitstream1 │ │ ├── Makefile │ │ ├── bitstream1.v │ │ └── makefile.trellis │ ├── bitstream2 │ │ ├── Makefile │ │ ├── bitstream2.v │ │ └── makefile.trellis │ └── gzip4k.py ├── nmigen │ └── dvi │ │ ├── README.md │ │ ├── blink.py │ │ ├── build.sh │ │ ├── ecp5pll.py │ │ ├── tmds_encoder.py │ │ ├── top_vgatest.py │ │ ├── vga.py │ │ ├── vga2dvid.py │ │ └── vga_timings.py ├── oled │ ├── hdl │ │ ├── ssd1306_video_verilog │ │ │ ├── ssd1306_oinit.mem │ │ │ ├── ssd1306_oinit_xflip.mem │ │ │ ├── ssd1306_oinit_xyflip.mem │ │ │ ├── ssd1306_oinit_yflip.mem │ │ │ └── top │ │ │ │ ├── top_checkered.v │ │ │ │ └── top_hex_demo.v │ │ ├── ssd1331_hex_vhdl │ │ │ ├── oled_font_pack.vhd │ │ │ ├── oled_hex_decoder.vhd │ │ │ └── oled_init_pack.vhd │ │ ├── ssd1331_term_verilog │ │ │ ├── font_rom.v │ │ │ ├── font_vga.mem │ │ │ ├── pll.v │ │ │ ├── top.v │ │ │ └── uart_rx.v │ │ ├── ssd1331_vga_vhdl │ │ │ ├── oled_vga.vhd │ │ │ └── oled_vga_init_pack.vhd │ │ ├── ssd1331_video_verilog │ │ │ ├── hex_decoder.v │ │ │ ├── oled_font.mem │ │ │ ├── oled_init.mem │ │ │ ├── oled_init_16bit.mem │ │ │ ├── oled_init_xflip.mem │ │ │ ├── oled_init_xflip_16bit.mem │ │ │ ├── oled_init_xyflip.mem │ │ │ ├── oled_init_xyflip_16bit.mem │ │ │ ├── oled_init_yflip.mem │ │ │ ├── oled_init_yflip_16bit.mem │ │ │ ├── oled_video.v │ │ │ ├── spi │ │ │ │ └── spi_slave.v │ │ │ └── top │ │ │ │ ├── top_checkered.v │ │ │ │ ├── top_hex_demo.v │ │ │ │ └── top_spi_hex.v │ │ └── ssd1351_video_verilog │ │ │ ├── ssd1351_oinit_xflip_16bit.mem │ │ │ └── top │ │ │ ├── top_checkered.v │ │ │ └── top_hex_demo.v │ ├── micropython │ │ ├── README.md │ │ └── oled.py │ └── proj │ │ ├── ulx3s_checkered_v │ │ ├── README.md │ │ ├── makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── oled_font.mem │ │ ├── oled_init.mem │ │ ├── oled_init_16bit.mem │ │ ├── oled_init_xflip.mem │ │ ├── oled_init_xflip_16bit.mem │ │ ├── oled_init_xyflip.mem │ │ ├── oled_init_xyflip_16bit.mem │ │ ├── oled_init_yflip.mem │ │ └── oled_init_yflip_16bit.mem │ │ ├── ulx3s_hex_vhdl │ │ ├── README.md │ │ ├── clock │ │ │ └── clk_25M_100M_7M5_12M_60M.vhd │ │ ├── makefile │ │ └── top │ │ │ └── ulx3s_oledtest.vhd │ │ ├── ulx3s_oled_vga_vhdl │ │ ├── README.md │ │ ├── makefile │ │ └── top │ │ │ └── ulx3s_oled_vga.vhd │ │ ├── ulx3s_spi_hex_v │ │ ├── README.md │ │ ├── makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── oled_font.mem │ │ ├── oled_init.mem │ │ ├── oled_init_xflip.mem │ │ └── oled_init_yflip.mem │ │ └── ulx3s_terminal │ │ ├── README.md │ │ ├── font_vga.mem │ │ ├── makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── oled_init.mem ├── onchip_osc_blink │ ├── Makefile │ ├── README.md │ ├── makefile.diamond │ ├── makefile.trellis │ └── oscg_blink.v ├── onchip_osc_blink_ffm │ ├── README.md │ ├── makefile │ ├── makefile.diamond │ ├── makefile.trellis │ └── oscg_blink.v ├── ov7670_dvi │ ├── hdl │ │ ├── OV7670_config.v │ │ ├── OV7670_config_rom.v │ │ ├── SCCB_interface.v │ │ ├── camera_configure.v │ │ ├── camera_read.v │ │ ├── hvsync_generator.v │ │ ├── top_OV7640.v │ │ └── vgabuff.v │ └── proj │ │ └── ulx3s_ov7670_dvi │ │ ├── makefile │ │ ├── makefile.diamond │ │ └── makefile.trellis ├── ps2 │ ├── kbd │ │ ├── hdl │ │ │ ├── ps2kbd.v │ │ │ └── top │ │ │ │ └── kbd_top.v │ │ └── proj │ │ │ └── lattice │ │ │ └── ulx3s │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ └── makefile.trellis │ ├── mouse │ │ ├── hdl │ │ │ ├── mousem.vhd │ │ │ ├── mousem_v.v │ │ │ ├── ps2mouse.v │ │ │ └── top │ │ │ │ └── ulx3s_ps2mouse.v │ │ └── proj │ │ │ └── lattice │ │ │ └── ulx3s │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── makefile.vhdl.diamond │ │ │ └── makefile.vhdl.trellis │ ├── mouse_dvi │ │ ├── hdl │ │ │ └── top │ │ │ │ ├── ffm_ps2mouse_dvi.v │ │ │ │ └── ulx3s_ps2mouse_dvi.v │ │ └── proj │ │ │ └── lattice │ │ │ ├── ffmlfe5 │ │ │ ├── README.md │ │ │ ├── clocks │ │ │ │ └── clk_100_250_125_25.v │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ └── makefile.trellis │ │ │ └── ulx3s │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ └── makefile.trellis │ ├── mouse_dvi_gui │ │ ├── hdl │ │ │ └── top │ │ │ │ └── ulx3s_ps2mouse_dvi_gui.v │ │ └── proj │ │ │ └── lattice │ │ │ └── ulx3s │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ └── makefile.trellis │ ├── mouse_oled │ │ ├── hdl │ │ │ └── top │ │ │ │ └── ulx3s_ps2mouse_oled.v │ │ └── proj │ │ │ └── lattice │ │ │ └── ulx3s │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── oled_init.mem │ │ │ └── oled_init_16bit.mem │ └── mouse_oled_dvi │ │ ├── hdl │ │ └── top │ │ │ └── ulx3s_ps2mouse_oled_dvi.v │ │ └── proj │ │ └── lattice │ │ └── ulx3s │ │ ├── README.md │ │ ├── makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── oled_init.mem │ │ └── oled_init_16bit.mem ├── qspi │ ├── bench │ │ └── busmaster.v │ └── hdl │ │ ├── eqspiflash.v │ │ ├── flashconfig.v │ │ ├── lleqspi.v │ │ ├── llqspi.v │ │ └── wbspiflash.v ├── rtc │ ├── i2c_master │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── hdl │ │ │ ├── i2c_master.v │ │ │ ├── i2c_master_8bit.v │ │ │ └── mcp7940n.v │ │ │ ├── hex_font.mem │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── makefile8bit.diamond │ │ │ ├── makefile8bit.trellis │ │ │ ├── st7789_linit_xflip.mem │ │ │ └── top │ │ │ ├── top_mcp7940n_rtc.v │ │ │ └── top_mcp7940n_rtc_8bit.v │ └── micropython-mcp7940n │ │ ├── README.md │ │ ├── esp32 │ │ ├── mcp7940.py │ │ ├── rtceink.py │ │ └── setrtc.py │ │ └── proj │ │ ├── Makefile │ │ ├── README.md │ │ ├── hdl │ │ └── i2c_bridge.v │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── top │ │ ├── top_i2c_bridge.v │ │ └── top_i2c_bridge_eink.v ├── sdcard │ └── micropython │ │ ├── README.md │ │ ├── esp32 │ │ └── sdtest.py │ │ └── proj │ │ ├── Makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── top │ │ └── top_sd_pullup.v ├── sdram │ ├── memtest_mister │ │ ├── hdl │ │ │ ├── btn_ecp5pll_phase.v │ │ │ ├── mem_tester.v │ │ │ ├── rnd_vec_gen.v │ │ │ ├── rnd_vec_gen2.v │ │ │ ├── sdram_control.v │ │ │ ├── top │ │ │ │ ├── top_ffm_memtest.v │ │ │ │ ├── top_memtest.v │ │ │ │ └── top_ulx4m_memtest.v │ │ │ └── vgaout.v │ │ └── proj │ │ │ ├── ffmlfe5_memtest │ │ │ ├── Makefile │ │ │ ├── makefile-720x480.diamond │ │ │ └── makefile-720x480.trellis │ │ │ └── ulx3s_memtest │ │ │ ├── Makefile │ │ │ ├── makefile-720x480.diamond │ │ │ └── makefile-720x480.trellis │ ├── sdram_16bit │ │ ├── hdl │ │ │ ├── sdram_16bit.v │ │ │ └── top │ │ │ │ └── sdram_hex_oled.v │ │ └── proj │ │ │ └── ulx3s_sdram_hex_v │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── oled_font.mem │ │ │ ├── oled_init.mem │ │ │ ├── oled_init_xflip.mem │ │ │ └── oled_init_xflip_16bit.mem │ ├── sdram_ctrl │ │ ├── hdl │ │ │ ├── sdram_ctrl.v │ │ │ └── top │ │ │ │ └── sdram_hex_oled.v │ │ └── proj │ │ │ └── ulx3s_sdram_hex_v │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── oled_font.mem │ │ │ ├── oled_init.mem │ │ │ ├── oled_init_xflip.mem │ │ │ └── oled_init_xflip_16bit.mem │ ├── sdram_fpga │ │ ├── hdl │ │ │ ├── sdram_0bject.vhd │ │ │ └── top │ │ │ │ └── sdram_fpga_hex_oled.vhd │ │ └── proj │ │ │ └── ulx3s_sdram_hex_v │ │ │ ├── README.md │ │ │ ├── makefile │ │ │ └── makefile.diamond │ ├── sdram_mist │ │ └── sdram_mist.v │ ├── sdram_mistery │ │ ├── hdl │ │ │ └── sdram.v │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── esp32 │ │ │ ├── hex_font.mem │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── st7789_linit_xflip.mem │ │ │ └── top │ │ │ └── top_spirw_sdram_hex.v │ ├── sdram_pnru │ │ ├── proj │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── esp32 │ │ │ │ └── spiram.py │ │ │ ├── hex_font.mem │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── st7789_linit_xflip.mem │ │ │ └── top │ │ │ │ └── top_spirw_sdram_hex.v │ │ ├── sdram_pnru.v │ │ └── sdram_pnru2.v │ ├── sdram_pnru_68k │ │ ├── hdl │ │ │ └── sdram.v │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── esp32 │ │ │ ├── hex_font.mem │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── st7789_linit_xflip.mem │ │ │ └── top │ │ │ └── top_spirw_sdram_hex.v │ ├── sdram_pnru_68k_180deg │ │ ├── README.md │ │ ├── hdl │ │ │ └── sdram.v │ │ └── proj │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── esp32 │ │ │ ├── hex_font.mem │ │ │ ├── makefile.diamond │ │ │ ├── makefile.trellis │ │ │ ├── st7789_linit_xflip.mem │ │ │ └── top │ │ │ └── top_spirw_sdram_hex.v │ └── sdram_pnru_99k │ │ └── hdl │ │ └── sdram.v ├── serdes │ ├── Makefile │ ├── README.md │ ├── makefile.trellis │ └── top │ │ └── top_serdes.v ├── serdes_dvi │ ├── Makefile │ ├── README.md │ ├── makefile.trellis │ └── top │ │ └── top_serdes_dvi.v ├── spi_display │ ├── hdl │ │ ├── spi_display_verilog │ │ │ ├── lcd_video.v │ │ │ ├── lcd_video_vhd.vhd │ │ │ ├── ssd1306_linit.mem │ │ │ ├── ssd1306_linit_xflip.mem │ │ │ ├── ssd1306_linit_xyflip.mem │ │ │ ├── ssd1306_linit_yflip.mem │ │ │ ├── ssd1331_linit_xflip_16bit.mem │ │ │ ├── ssd1351_linit_16bit.mem │ │ │ ├── ssd1351_linit_xflip_16bit.mem │ │ │ ├── st7789_init.mem │ │ │ ├── st7789_linit.mem │ │ │ ├── st7789_linit_long.mem │ │ │ ├── st7789_linit_xflip.mem │ │ │ ├── st7789_linit_xyflip.mem │ │ │ ├── st7789_linit_yflip.mem │ │ │ └── top │ │ │ │ ├── top_checkered.v │ │ │ │ ├── top_hex_demo.v │ │ │ │ └── top_hex_mul.v │ │ └── spi_display_vhdl │ │ │ ├── spi_display.vhd │ │ │ ├── spi_display_init_pack.vhd │ │ │ ├── ssd1331_init_pack.vhd │ │ │ ├── st7789_init_pack.vhd │ │ │ └── st7789_init_pack_long.vhd │ └── proj │ │ ├── ssd1331_vga_vhdl │ │ ├── Makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── top │ │ │ └── top_vgatest.vhd │ │ ├── st7789_osd_verilog │ │ ├── Makefile │ │ ├── README.md │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── osd.mem │ │ ├── osd.txt │ │ ├── st7789_linit.mem │ │ └── top │ │ │ └── top_st7789_vga.v │ │ ├── st7789_vga_verilog │ │ ├── Makefile │ │ ├── README.md │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ ├── st7789_linit.mem │ │ └── top │ │ │ └── top_st7789_vga.v │ │ └── st7789_vga_vhdl │ │ ├── Makefile │ │ ├── makefile.diamond │ │ ├── makefile.trellis │ │ └── top │ │ └── top_vgatest.vhd ├── spi_ram │ ├── esp32 │ │ ├── spiram.py │ │ └── spiram_test.py │ ├── hdl │ │ ├── bram_true2p_2clk.vhd │ │ ├── spi_ram_slave.vhd │ │ └── top │ │ │ └── ulx3s_spi_ram_oled.vhd │ └── proj │ │ └── ulx3s_spi_ram_oled │ │ ├── README.md │ │ └── makefile ├── spi_slave │ ├── hdl │ │ ├── spirw_slave.vhd │ │ ├── spirw_slave_v.v │ │ ├── spirw_tight_slave.v │ │ ├── todo.txt │ │ └── top │ │ │ └── top_spirw_hex.v │ └── proj │ │ └── ulx3s_spirw_hex_v │ │ ├── Makefile │ │ ├── README.md │ │ ├── makefile.diamond │ │ └── makefile.trellis ├── usb │ ├── README.md │ ├── ch376 │ │ ├── esp32 │ │ │ └── ch376.py │ │ ├── hdl │ │ │ └── ch376pt.v │ │ ├── proj │ │ │ ├── Makefile │ │ │ ├── makefile.diamond │ │ │ └── makefile.trellis │ │ └── python │ │ │ └── ch376.py │ ├── lattice │ │ └── ulx3s │ │ │ ├── clocks │ │ │ ├── clk_200m_60m_48m_12m_7m5.vhd │ │ │ ├── clk_25M_100M_7M5_12M_60M.vhd │ │ │ ├── clk_25_125_25_48_89.vhd │ │ │ ├── clk_25_125_68_6_25.vhd │ │ │ └── clk_25m_200m.vhd │ │ │ └── top │ │ │ ├── ulx3s_usbeth.vhd │ │ │ └── ulx3s_usbserial.vhd │ ├── proj │ │ ├── lattice │ │ │ ├── constraints │ │ │ │ ├── ulx3s_v17patch.lpf │ │ │ │ ├── ulx3s_v20_dif.lpf │ │ │ │ └── ulx3s_v20_se.lpf │ │ │ └── ulx3s │ │ │ │ ├── constraints │ │ │ │ └── ulx3s_v20_segpdi.lpf │ │ │ │ ├── usbethernet │ │ │ │ ├── README.md │ │ │ │ ├── files.mk │ │ │ │ └── makefile │ │ │ │ ├── usbhid_host │ │ │ │ ├── Makefile │ │ │ │ ├── README.md │ │ │ │ ├── constraints │ │ │ │ │ ├── ulx3s_v20.lpf │ │ │ │ │ └── ulx3s_v20_se.lpf │ │ │ │ ├── files.mk │ │ │ │ ├── filesv.mk │ │ │ │ ├── hex_font.mem │ │ │ │ ├── makefile.diamond │ │ │ │ ├── makefile.trellis │ │ │ │ ├── makefilev.diamond │ │ │ │ ├── makefilev.trellis │ │ │ │ ├── ssd1331_linit_xflip_16bit.mem │ │ │ │ ├── st7789_linit_xflip.mem │ │ │ │ ├── top │ │ │ │ │ ├── verilog │ │ │ │ │ │ └── ulx3s_usbhost_test.v │ │ │ │ │ └── vhdl │ │ │ │ │ │ └── ulx3s_usbhost_test.vhd │ │ │ │ └── usbh_setup_rom.mem │ │ │ │ ├── usbkbd │ │ │ │ ├── Makefile │ │ │ │ ├── filesv.mk │ │ │ │ ├── makefilev.trellis │ │ │ │ └── top │ │ │ │ │ └── verilog │ │ │ │ │ └── ulx3s_usbkbd_test.v │ │ │ │ └── usbserial_vhdl │ │ │ │ ├── files.mk │ │ │ │ └── makefile │ │ └── xilinx │ │ │ ├── ffm-a7100 │ │ │ └── ffm-a7100-vivado │ │ │ │ ├── FFM-A7100-V3r0_and_FFC-CA7-V2r0.xdc │ │ │ │ ├── cablelist.txt │ │ │ │ ├── devlist.txt │ │ │ │ ├── makefile │ │ │ │ ├── project.ldf │ │ │ │ ├── run_vivado.tcl │ │ │ │ ├── top │ │ │ │ └── usbserial_ffm_a7100.vhd │ │ │ │ ├── usbserial_ffm_a7100_v3r0_ffc_ca7_v2r0.xpr │ │ │ │ └── xilinx.opt │ │ │ └── include │ │ │ ├── bit2svf.ut │ │ │ ├── bit2xsvf.ut │ │ │ ├── vivado.mk │ │ │ └── xilinx.mk │ ├── ulpi_wrapper │ │ └── ulpi_wrapper.v │ ├── usb11_phy_vhdl │ │ ├── usb_phy.vhd │ │ ├── usb_phy_transciver.vhd │ │ ├── usb_rx_phy.vhd │ │ └── usb_tx_phy.vhd │ ├── usbcdc │ │ ├── README.txt │ │ ├── eth │ │ │ └── usbeth_icmp_echo.vhd │ │ ├── fpgaser.inf │ │ ├── usb_cdc_descriptor_pack.vhd │ │ ├── usb_control.vhd │ │ ├── usb_init.vhd │ │ ├── usb_mii.vhd │ │ ├── usb_packet.vhd │ │ ├── usb_serial.vhd │ │ ├── usb_transact.vhd │ │ └── usbtest.vhd │ ├── usbhid │ │ ├── report_decoded_pack_generic.vhd │ │ ├── usbhid_report_decoder_darfon_joystick.vhd │ │ ├── usbhid_report_decoder_logitech_mouse.vhd │ │ ├── usbhid_report_decoder_saitek_joystick.vhd │ │ └── usbhid_report_decoder_xbox360_joystick.vhd │ └── usbhost │ │ ├── usbh_crc16.v │ │ ├── usbh_crc5.v │ │ ├── usbh_host_hid.v │ │ ├── usbh_host_hid.vhd │ │ ├── usbh_host_hid_convertible.vhd │ │ ├── usbh_setup_pack.vhd │ │ ├── usbh_setup_rom.mem │ │ ├── usbh_sie.v │ │ └── usbh_sie_vhdl.vhd └── vhdlib │ ├── Makefile │ ├── synth.ys │ └── vhd │ ├── blink.vhd │ ├── blinkpkg.vhd │ └── top_blink.vhd ├── multiplatform ├── README.md └── xilinx │ └── vivado │ └── esa11-unimake │ ├── blinky.srcs │ └── sources_1 │ │ └── ip │ │ └── clk_d100_100_200_125_25MHz │ │ └── clk_d100_100_200_125_25MHz.xci │ ├── blinky.xpr │ ├── cablelist.txt │ ├── constraints │ ├── esa11-7a102t-user02.xdc │ └── esa11-7a102t-v1.1-phys.xdc │ ├── devlist.txt │ ├── empty.xpr │ ├── ldf.xsl │ ├── makefile │ ├── modified.xpr │ ├── run.sh │ ├── run_vivado.tcl │ ├── top │ └── phoenix_esa11.vhd │ ├── vivado.mk │ ├── xpr.xsl │ └── xpr.xsl.bak └── scripts ├── IspXCF.dtd ├── diamond_main.mk ├── diamond_path.mk ├── ecp5-ocd.sh ├── ft2232.ocd ├── ft231x.ocd ├── ft231x2.ocd ├── ft232r.ocd ├── ft4232.ocd ├── ldf.xsl ├── project.ldf ├── trellis_main.mk ├── trellis_main_ghdl.mk ├── trellis_main_sv.mk ├── trellis_path.mk ├── ulx3s.sty ├── ulx3s_flash_is25lp032d.xcf ├── ulx3s_flash_is25lp128f.xcf ├── ulx3s_flash_s25fl164k.xcf ├── ulx3s_sram.xcf └── xcf.xsl /README.md: -------------------------------------------------------------------------------- 1 | # ULX3S miscellaneous examples (advanced) 2 | 3 | This is collection of miscellaneous examples for ULX3S. 4 | Most examples are advanced and demonstrate various capabilites 5 | of ULX3S board. Developed and tested on linux using commandline. 6 | 7 | A novel structure of makefiles and scripts is used to ease and 8 | the building and upload of the examples. All examples should 9 | share same build scripts. Build scripts allow building of 10 | the same example with diamond and trellins, to verify that 11 | both produce mostly the same result or for a bug report if different :). 12 | 13 | Opensource tools "prjtrellis", "nextpnr", "yosys" and "vhd2vl" 14 | can be by default extracted to "/mt/scratch/tmp/openfpga/" and compiled. 15 | Makefiles will use above path. This path can be changed at editing 16 | "scripts/trellis_path.mk". 17 | 18 | Installation of opensource tools using "make install" is not required. 19 | -------------------------------------------------------------------------------- /clocks/README.md: -------------------------------------------------------------------------------- 1 | # auto-generated clocks here -------------------------------------------------------------------------------- /examples/adc/adc_lcd_lvds/proj/lattice/ulx3s/Makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/adc/adc_lcd_lvds/proj/lattice/ulx3s/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/adc/adc_oled/proj/lattice/ulx3s/README.md: -------------------------------------------------------------------------------- 1 | # Mouse from Minimig 2 | 3 | Microsoft IntelliMouse Optical USB/PS2 4 | 5 | X/Y movement works. 6 | Left and Right mouse button clicks works. 7 | Other buttons don't work. 8 | 9 | Logitech Wheel Mouse M-BT58 USB/PS2 10 | 11 | X/Y movement works. 12 | Left, Right button clicks and Wheel press (aka middle button) work. 13 | 14 | Wheel rotation is not supported yet. 15 | 16 | The initialization procedure is not very plug-n-play. 17 | Here's a manual procedure that gets it working: 18 | 19 | 0. plug mouse out 20 | 1. upload this bitstream 21 | 2. click btn0 to reset 22 | 3. plug mouse in 23 | 4. click btn0 to reset 24 | 5. click mouse left/right buttons and move mouse, LEDs will show it 25 | -------------------------------------------------------------------------------- /examples/adc/adc_oled/proj/lattice/ulx3s/makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/adxl355/esp32/pps.py: -------------------------------------------------------------------------------- 1 | #from machine import Pin,PWM 2 | #pps=PWM(Pin(5),freq=1,duty=102) 3 | 4 | from machine import Pin,Timer 5 | from time import sleep_ms 6 | pin=Pin(5,Pin.OUT) 7 | @micropython.viper 8 | def tick(x): 9 | pin.on() 10 | sleep_ms(100) 11 | pin.off() 12 | 13 | timer=Timer(3) 14 | timer.init(mode=Timer.PERIODIC, period=1000, callback=tick) 15 | -------------------------------------------------------------------------------- /examples/adxl355/pc/gps2ulx3s.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # PPS proxy 4 | 5 | # reads GPS PPS input from its CDC (cd) line 6 | # sends PPS to ULX3S nRTS (ftdi_nrts) line 7 | 8 | import serial, time 9 | 10 | gps = serial.Serial() 11 | gps.baudrate = 4800 12 | gps.port = '/dev/ttyUSB0' 13 | gps.rtscts = True 14 | gps.dsrdtr = True 15 | gps.open() 16 | gps.setDTR(True) 17 | gps.setRTS(True) 18 | 19 | ulx = serial.Serial() 20 | ulx.baudrate = 115200 21 | ulx.port = '/dev/ttyUSB1' 22 | ulx.open() 23 | 24 | while True: 25 | while(gps.cd): 26 | pass 27 | ulx.setRTS(0) 28 | print(0) 29 | while(not gps.cd): 30 | pass 31 | ulx.setRTS(1) 32 | print(1) 33 | 34 | while False: 35 | ulx.setRTS(int(time.time())&1) 36 | -------------------------------------------------------------------------------- /examples/adxl355/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/adxl355/proj/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = adxl355 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = constraints/ulx3s_v20.lpf 26 | TOP_MODULE = top_adxl355 27 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 28 | 29 | VERILOG_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | 32 | SCRIPTS = ../../../scripts 33 | include $(SCRIPTS)/trellis_path.mk 34 | include $(SCRIPTS)/diamond_path.mk 35 | include $(SCRIPTS)/diamond_main.mk 36 | -------------------------------------------------------------------------------- /examples/adxl355/proj/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = adxl355 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = CABGA381 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | #OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = constraints/ulx3s_v20.lpf 22 | TOP_MODULE = top_adxl355 23 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 24 | 25 | VERILOG_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | 28 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 29 | VHDL_FILES = \ 30 | 31 | # synthesis options 32 | #YOSYS_OPTIONS = -noccu2 33 | NEXTPNR_OPTIONS = --timing-allow-fail 34 | 35 | SCRIPTS = ../../../scripts 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/trellis_path.mk 38 | include $(SCRIPTS)/trellis_main.mk 39 | -------------------------------------------------------------------------------- /examples/adxl355/projbig/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/adxl355/projbig/README.md: -------------------------------------------------------------------------------- 1 | # ADXL355 logger large project 2 | 3 | # TODO 4 | 5 | [x] when reading 2-byte buffer pointer 6 | latch LSB byte when reading LSB for 7 | consistent 16-bit reading 8 | [ ] write to SPI IO for tagging 9 | [ ] write to SPI IO for display 10 | [ ] write to SPI IO for audio message 11 | 12 | 13 | -------------------------------------------------------------------------------- /examples/adxl355/projbig/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = adxl355 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = constraints/ulx3s_v20.lpf 26 | TOP_MODULE = top_adxl355log 27 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 28 | 29 | VERILOG_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | ../../ecp5pll/hdl/sv/ecp5pll.sv \ 32 | rtl/adxl355_clk.v \ 33 | 34 | SCRIPTS = ../../../scripts 35 | include $(SCRIPTS)/trellis_path.mk 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/diamond_main.mk 38 | -------------------------------------------------------------------------------- /examples/adxl355/projbig/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = adxl355 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = CABGA381 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | #OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = constraints/ulx3s_v20.lpf 22 | TOP_MODULE = top_adxl355log 23 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 24 | 25 | VERILOG_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | ../../ecp5pll/hdl/sv/ecp5pll.sv \ 28 | ../../spi_slave/hdl/spirw_slave_v.v \ 29 | rtl/adxl355rd.v \ 30 | rtl/adxl355_sync.v \ 31 | 32 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 33 | VHDL_FILES = \ 34 | 35 | # synthesis options 36 | #YOSYS_OPTIONS = -noccu2 37 | NEXTPNR_OPTIONS = --timing-allow-fail 38 | 39 | SCRIPTS = ../../../scripts 40 | include $(SCRIPTS)/diamond_path.mk 41 | include $(SCRIPTS)/trellis_path.mk 42 | include $(SCRIPTS)/trellis_main.mk 43 | -------------------------------------------------------------------------------- /examples/audio/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/audio/README.md: -------------------------------------------------------------------------------- 1 | # Project Trellis AUDIO 2 | 3 | Simple example generates analog and digital (SPDIF) sound output 4 | to 24-bit SPDIF and 4-bit DAC with resolution enhancement. 5 | 6 | Input is 12-bit unsigned PCM from a simple low frequency 7 | triangle wave generator (something near 50 Hz). 8 | 9 | Because of resolution enhancement with PWM, 4-bit DAC plays smooth 10 | sound wave. 4-bit DAC without such PWM would generate unwanted 11 | high-pitch harmonics due to coarse quantization. 12 | 13 | Analog output goes to 4-bit DAC with resolution enhancement 14 | using 8-bit PWM applied to LSB (least significant bit). 15 | Analog output is sent to TIP and RING1 of 3.5 mm jack. 16 | 17 | Digital output goes to 24-bit signed SPDIF encoder. 18 | 12-bit unsigned wave is mapped to bits [22:11] of 24-bit signed 19 | bus and other bits are zero. 20 | Digital SPDIF output is sent to RING2 of 3.5 mm jack. 21 | 22 | # TODO 23 | 24 | [ ] verilog parametrized widths: 25 | https://github.com/daveshah1/CSI2Rx/blob/master/verilog_cores/phy/word_combiner.v#L33-L48 26 | -------------------------------------------------------------------------------- /examples/audio/hdl/squarewave.v: -------------------------------------------------------------------------------- 1 | // generates triangle wave 2 | 3 | module squarewave 4 | #( 5 | parameter C_delay = 10, // bits for delay part of the counter 6 | parameter C_pcm_bits = 12 // how many bits for PCM output 7 | ) 8 | ( 9 | input clk, // required to run PWM 10 | output signed [C_pcm_bits-1:0] pcm // 12-bit unsigned PCM output 11 | ); 12 | 13 | reg [C_delay+C_pcm_bits-1:0] R_counter; // PWM counter register 14 | reg R_direction; 15 | 16 | always @(posedge clk) 17 | begin 18 | if(R_direction == 1'b1) 19 | R_counter <= R_counter + 1; 20 | else 21 | R_counter <= R_counter - 1; 22 | end 23 | 24 | always @(posedge clk) 25 | begin 26 | if( R_counter[C_delay+C_pcm_bits-1:C_delay] == ~{12'd1770} && R_direction == 1'b0) 27 | R_direction <= 1'b1; // from now on, count forwards 28 | if( R_counter[C_delay+C_pcm_bits-1:C_delay] == 12'd1770 && R_direction == 1'b1) 29 | R_direction <= 1'b0; // from now on, count backwards 30 | end 31 | 32 | assign pcm = {R_direction, 11'b000_0000_0000}; 33 | endmodule 34 | -------------------------------------------------------------------------------- /examples/audio/hdl/trianglewave.v: -------------------------------------------------------------------------------- 1 | // generates triangle wave 2 | 3 | module trianglewave 4 | #( 5 | parameter C_delay = 10, // bits for delay part of the counter 6 | parameter C_pcm_bits = 12 // how many bits for PCM output 7 | ) 8 | ( 9 | input clk, // required to run PWM 10 | output signed [C_pcm_bits-1:0] pcm // 12-bit unsigned PCM output 11 | ); 12 | 13 | reg [C_delay+C_pcm_bits-1:0] R_counter; // PWM counter register 14 | reg R_direction; 15 | 16 | always @(posedge clk) 17 | begin 18 | if(R_direction == 1'b1) 19 | R_counter <= R_counter + 1; 20 | else 21 | R_counter <= R_counter - 1; 22 | end 23 | 24 | always @(posedge clk) 25 | begin 26 | if( R_counter[C_delay+C_pcm_bits-1:C_delay] == ~{12'd1770} && R_direction == 1'b0) 27 | R_direction <= 1'b1; // from now on, count forwards 28 | if( R_counter[C_delay+C_pcm_bits-1:C_delay] == 12'd1770 && R_direction == 1'b1) 29 | R_direction <= 1'b0; // from now on, count backwards 30 | end 31 | 32 | assign pcm = R_counter[C_delay+C_pcm_bits-1:C_delay]; 33 | endmodule 34 | -------------------------------------------------------------------------------- /examples/audio/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = audio 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | FPGA_PACKAGE = 6bg381c 8 | # config flash: 1:SPI (standard), 4:QSPI (quad) 9 | FLASH_SPI = 4 10 | # chip: is25lp032d is25lp128f s25fl164k 11 | FLASH_CHIP = is25lp128f 12 | 13 | # ******* if programming with OpenOCD ******* 14 | # using local latest openocd until in linux distribution 15 | OPENOCD=openocd_ft232r 16 | # default onboard usb-jtag 17 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 18 | # ulx3s-jtag-passthru 19 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 20 | # ulx2s 21 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 22 | # external jtag 23 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 24 | 25 | # ******* design files ******* 26 | CONSTRAINTS = ../../constraints/ulx3s_v20_segpdi.lpf 27 | TOP_MODULE = top_audio 28 | TOP_MODULE_FILE = hdl/$(TOP_MODULE).v 29 | 30 | VERILOG_FILES = \ 31 | $(TOP_MODULE_FILE) \ 32 | hdl/trianglewave.v \ 33 | hdl/sinewave.v \ 34 | hdl/dacpwm.v \ 35 | hdl/i2s_v.v 36 | 37 | VHDL_FILES = \ 38 | hdl/i2s.vhd \ 39 | hdl/spdif_tx.vhd 40 | 41 | SCRIPTS = ../../scripts 42 | include $(SCRIPTS)/trellis_path.mk 43 | include $(SCRIPTS)/diamond_path.mk 44 | include $(SCRIPTS)/diamond_main.mk 45 | -------------------------------------------------------------------------------- /examples/audio/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = audio 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../constraints/ulx3s_v20_segpdi.lpf 21 | TOP_MODULE = top_audio 22 | TOP_MODULE_FILE = hdl/$(TOP_MODULE).v 23 | 24 | VERILOG_FILES = \ 25 | $(TOP_MODULE_FILE) \ 26 | hdl/trianglewave.v \ 27 | hdl/squarewave.v \ 28 | hdl/sinewave.v \ 29 | hdl/dacpwm.v \ 30 | hdl/i2s_v.v 31 | 32 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 33 | VHDL_FILES = \ 34 | hdl/i2s.vhd \ 35 | hdl/spdif_tx.vhd 36 | 37 | # synthesis options 38 | #YOSYS_OPTIONS = -noccu2 39 | 40 | SCRIPTS = ../../scripts 41 | include $(SCRIPTS)/diamond_path.mk 42 | include $(SCRIPTS)/trellis_path.mk 43 | include $(SCRIPTS)/trellis_main.mk 44 | -------------------------------------------------------------------------------- /examples/audio/testbench/sinewave.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | int32_t pos = 0; 5 | int32_t spd = 277; 6 | 7 | int main(int argc, char *argv[]) 8 | { 9 | int32_t i, spd_min = 0, spd_max = 0, pos_min = 9990, pos_max = 0; 10 | int32_t pos_u; 11 | 12 | for(i = 0; i < 10000; i++) 13 | { 14 | pos += spd/8; 15 | spd -= pos/256; 16 | 17 | //pos_u = (pos ^ 0xFFFFF800) & 0xFFF; 18 | pos_u = pos; 19 | //pos_u = (pos ^ 0x7FF) & 0xFFF; 20 | if(pos_u > pos_max) pos_max = pos_u; 21 | if(pos_u < pos_min) pos_min = pos_u; 22 | if(spd > spd_max) spd_max = spd; 23 | if(spd < spd_min) spd_min = spd; 24 | #if 0 25 | printf("pos=%d spd=%d\n", pos_u, spd); 26 | #endif 27 | } 28 | printf("pos=%d..%d spd=%d..%d\n", pos_min, pos_max, spd_min, spd_max); 29 | 30 | } -------------------------------------------------------------------------------- /examples/btn_debounce/hdl/btn_debounce.v: -------------------------------------------------------------------------------- 1 | // BTN debouncer 2 | `default_nettype none 3 | module btn_debounce 4 | #( 5 | parameter bits = 16, 6 | parameter btns = 7 7 | ) 8 | ( 9 | input clk, // 1-100 MHz 10 | input [btns-1:0] btn, 11 | output [btns-1:0] debounce, rising, falling 12 | ); 13 | reg [bits:0] R_debounce; 14 | reg [btns-1:0] R_btn, R_btn_prev; 15 | always @(posedge clk) 16 | begin 17 | if(R_debounce[bits]) 18 | begin 19 | if(R_btn != R_btn_prev) 20 | R_debounce <= 0; 21 | else 22 | R_btn <= btn; 23 | R_btn_prev <= R_btn; 24 | end 25 | else 26 | begin 27 | R_debounce <= R_debounce + 1; 28 | end 29 | end 30 | assign debounce = R_btn; 31 | assign rising = R_btn & ~R_btn_prev; 32 | assign falling = R_btn_prev & ~R_btn; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /examples/collatz/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefilev.trellis -------------------------------------------------------------------------------- /examples/collatz/proj/collatz.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | x = 15 4 | 5 | while x > 1: 6 | print("%08X" % x) 7 | if (x & 1) != 0: 8 | x = (x*3+1)//2 9 | else: 10 | x = x//2 11 | -------------------------------------------------------------------------------- /examples/collatz/proj/filesv.mk: -------------------------------------------------------------------------------- 1 | VERILOG_FILES = \ 2 | $(TOP_MODULE_FILE) \ 3 | ../../ecp5pll/hdl/sv/ecp5pll.sv \ 4 | ../../hex/decoder/hex_decoder_v.v \ 5 | ../../gray_counter/hdl/v/gray_counter.v \ 6 | ../../spi_display/hdl/spi_display_verilog/lcd_video.v \ 7 | ../../btn_debounce/hdl/btn_debounce.v \ 8 | ../hdl/random_counter.v \ 9 | ../hdl/collatz_conjecture.v \ 10 | 11 | # convertible with vhd2vl 12 | VHDL_FILES = \ 13 | ../../dvi/hdl/vga.vhd \ 14 | ../../dvi/hdl/vga2dvid.vhd \ 15 | ../../dvi/hdl/tmds_encoder.vhd \ 16 | -------------------------------------------------------------------------------- /examples/collatz/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/collatz/proj/makefilev.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = collatz 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* design files ******* 13 | CONSTRAINTS = constraints/ulx3s_v20.lpf 14 | 15 | # usually all toplevels have the same top module name 16 | TOP_MODULE = ulx3s_usbhost_test 17 | 18 | # various toplevels for building different soc's 19 | TOP_MODULE_FILE = top/verilog/ulx3s_usbhost_test.v 20 | 21 | include filesv.mk 22 | 23 | #BITSTREAM = \ 24 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit \ 25 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme \ 26 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf \ 27 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme 28 | 29 | SCRIPTS = ../../../../../../scripts 30 | include $(SCRIPTS)/trellis_path.mk 31 | include $(SCRIPTS)/diamond_path.mk 32 | include $(SCRIPTS)/diamond_main.mk 33 | -------------------------------------------------------------------------------- /examples/collatz/proj/makefilev.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = collatz 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | #OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | #CONSTRAINTS = ../../../constraints/ulx3s_v20.lpf 21 | CONSTRAINTS = ../../../constraints/ulx3s_v316.lpf 22 | TOP_MODULE = ulx3s_collatz_test 23 | TOP_MODULE_FILE = top/verilog/$(TOP_MODULE).v 24 | 25 | include filesv.mk 26 | 27 | YOSYS_OPTIONS = -abc9 28 | NEXTPNR_OPTIONS = --timing-allow-fail --ignore-loops 29 | 30 | SCRIPTS = ../../../scripts 31 | include $(SCRIPTS)/diamond_path.mk 32 | include $(SCRIPTS)/trellis_path.mk 33 | include $(SCRIPTS)/trellis_main.mk 34 | -------------------------------------------------------------------------------- /examples/collatz/proj/ssd1331_linit_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../../../spi_display/hdl/spi_display_verilog/ssd1331_linit_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/collatz/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/db9joy/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/db9joy/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = db9joy 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = db9joy 23 | TOP_MODULE_FILE = hdl/$(TOP_MODULE).v 24 | 25 | #VHDL_FILES = \ 26 | #$(TOP_MODULE_FILE) \ 27 | 28 | VERILOG_FILES = \ 29 | $(TOP_MODULE_FILE) \ 30 | 31 | # synthesis options 32 | #YOSYS_OPTIONS = -noccu2 33 | 34 | SCRIPTS = ../../scripts 35 | include $(SCRIPTS)/trellis_path.mk 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/diamond_main.mk 38 | -------------------------------------------------------------------------------- /examples/db9joy/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = db9joy 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = CABGA381 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | #OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = db9joy 23 | TOP_MODULE_FILE = hdl/$(TOP_MODULE).v 24 | 25 | VERILOG_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | 28 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 29 | #VHDL_FILES = \ 30 | 31 | # synthesis options 32 | #YOSYS_OPTIONS = -noccu2 33 | NEXTPNR_OPTIONS = --timing-allow-fail 34 | 35 | SCRIPTS = ../../scripts 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/trellis_path.mk 38 | include $(SCRIPTS)/trellis_main.mk 39 | -------------------------------------------------------------------------------- /examples/dvi/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/dvi/hdl/blink.vhd: -------------------------------------------------------------------------------- 1 | -- (c)EMARD 2 | -- License=BSD 3 | 4 | library IEEE; 5 | use IEEE.STD_LOGIC_1164.ALL; 6 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 7 | 8 | entity blink is 9 | generic 10 | ( 11 | bits: integer := 23 12 | ); 13 | port 14 | ( 15 | clk: in std_logic; -- main clock input from 25MHz clock source 16 | led: out std_logic_vector(7 downto 0) 17 | ); 18 | end; 19 | 20 | architecture Behavioral of blink is 21 | signal R_blink: std_logic_vector(bits-1 downto 0); 22 | begin 23 | process(clk) 24 | begin 25 | if rising_edge(clk) then 26 | R_blink <= R_blink+1; 27 | end if; 28 | end process; 29 | led <= R_blink(R_blink'high downto R_blink'high-7); 30 | end Behavioral; 31 | -------------------------------------------------------------------------------- /examples/dvi/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = dvi 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 26 | TOP_MODULE = top_vgatest 27 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 28 | 29 | VERILOG_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | ../ecp5pll/hdl/sv/ecp5pll.sv \ 32 | 33 | VHDL_FILES = \ 34 | hdl/vga.vhd \ 35 | hdl/vga2dvid.vhd \ 36 | hdl/tmds_encoder.vhd 37 | 38 | SCRIPTS = ../../scripts 39 | include $(SCRIPTS)/trellis_path.mk 40 | include $(SCRIPTS)/diamond_path.mk 41 | include $(SCRIPTS)/diamond_main.mk 42 | -------------------------------------------------------------------------------- /examples/dvi/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = dvi 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = CABGA381 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | #OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = top_vgatest 23 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 24 | 25 | VERILOG_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | ../ecp5pll/hdl/sv/ecp5pll.sv \ 28 | 29 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 30 | VHDL_FILES = \ 31 | hdl/vga.vhd \ 32 | hdl/vga2dvid.vhd \ 33 | hdl/tmds_encoder.vhd 34 | 35 | # synthesis options 36 | #YOSYS_OPTIONS = -noccu2 37 | NEXTPNR_OPTIONS = --timing-allow-fail 38 | 39 | SCRIPTS = ../../scripts 40 | include $(SCRIPTS)/diamond_path.mk 41 | include $(SCRIPTS)/trellis_path.mk 42 | include $(SCRIPTS)/trellis_main.mk 43 | -------------------------------------------------------------------------------- /examples/dvi/makefilevhdl.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = dvi 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 26 | TOP_MODULE = top_vgatest 27 | TOP_MODULE_FILE = top/vhdl/$(TOP_MODULE).vhd 28 | 29 | VERILOG_FILES = \ 30 | top/empty.v \ 31 | 32 | VHDL_FILES = \ 33 | $(TOP_MODULE_FILE) \ 34 | ../ecp5pll/hdl/vhd/ecp5pll.vhd \ 35 | hdl/vga.vhd \ 36 | hdl/vga2dvid.vhd \ 37 | hdl/tmds_encoder.vhd \ 38 | 39 | SCRIPTS = ../../scripts 40 | include $(SCRIPTS)/trellis_path.mk 41 | include $(SCRIPTS)/diamond_path.mk 42 | include $(SCRIPTS)/diamond_main.mk 43 | -------------------------------------------------------------------------------- /examples/dvi/makefilevhdl.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = dvi 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = CABGA381 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | #OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = top_vgatest 23 | TOP_MODULE_FILE = top/vhdl/$(TOP_MODULE).vhd 24 | 25 | VERILOG_FILES = \ 26 | top/empty.v \ 27 | 28 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 29 | VHDL_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | ../ecp5pll/hdl/vhd/ecp5pll.vhd \ 32 | hdl/vga.vhd \ 33 | hdl/vga2dvid.vhd \ 34 | hdl/tmds_encoder.vhd 35 | 36 | # synthesis options 37 | #YOSYS_OPTIONS = -noccu2 38 | NEXTPNR_OPTIONS = --timing-allow-fail 39 | 40 | SCRIPTS = ../../scripts 41 | include $(SCRIPTS)/diamond_path.mk 42 | include $(SCRIPTS)/trellis_path.mk 43 | include $(SCRIPTS)/trellis_main_ghdl.mk 44 | -------------------------------------------------------------------------------- /examples/dvi/top/empty.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/ulx3s-misc/8c07331dd1f9492a8c08bd4bb0b6495ae7630664/examples/dvi/top/empty.v -------------------------------------------------------------------------------- /examples/dvi_in/hdl/dvi2vga.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_unsigned.all; 4 | 5 | entity dvi2vga is 6 | Port 7 | ( 8 | clk: in std_logic; -- pixel clock 9 | dvi_red, dvi_green, dvi_blue: in std_logic_vector(9 downto 0); -- 10-bit TMDS encoded 10 | vga_red, vga_green, vga_blue: out std_logic_vector(7 downto 0); -- 8-bit RGB color decoded 11 | vga_hsync, vga_vsync, vga_blank: out std_logic -- frame control 12 | ); 13 | end; 14 | 15 | architecture Behavioral of dvi2vga is 16 | begin 17 | 18 | red_decoder_inst: 19 | entity work.tmds_dekoder 20 | port map 21 | ( 22 | clk => clk, 23 | din => dvi_red, 24 | dout => vga_red 25 | ); 26 | 27 | green_decoder_inst: 28 | entity work.tmds_dekoder 29 | port map 30 | ( 31 | clk => clk, 32 | din => dvi_green, 33 | dout => vga_green 34 | ); 35 | 36 | blue_decoder_inst: 37 | entity work.tmds_dekoder 38 | port map 39 | ( 40 | clk => clk, 41 | din => dvi_blue, 42 | dout => vga_blue, 43 | c(1) => vga_vsync, 44 | c(0) => vga_hsync, 45 | blank => vga_blank 46 | ); 47 | 48 | end Behavioral; 49 | -------------------------------------------------------------------------------- /examples/dvi_in/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/dvi_in/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/dvi_osd/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/dvi_osd/font_bizcat8x16.mem: -------------------------------------------------------------------------------- 1 | hdl/font_bizcat8x16.mem -------------------------------------------------------------------------------- /examples/ecp5pll/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/ecp5pll/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = ecp5pll 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 26 | TOP_MODULE = top_ecp5pll 27 | TOP_MODULE_FILE = top/vhd/$(TOP_MODULE).vhd 28 | 29 | VERILOG_FILES = 30 | 31 | VHDL_FILES = \ 32 | $(TOP_MODULE_FILE) \ 33 | hdl/vhd/ecp5pll.vhd \ 34 | 35 | SCRIPTS = ../../scripts 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/diamond_path.mk 38 | include $(SCRIPTS)/diamond_main.mk 39 | -------------------------------------------------------------------------------- /examples/ecp5pll/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = ecp5pll 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 21 | TOP_MODULE = top_ecp5pll 22 | TOP_MODULE_FILE = top/vhd/$(TOP_MODULE).vhd 23 | 24 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 25 | VHDL_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | hdl/vhd/ecp5pll.vhd \ 28 | 29 | VERILOG_FILES = \ 30 | ../dvi/top/empty.v 31 | 32 | # synthesis options 33 | NEXTPNR_OPTIONS = --timing-allow-fail 34 | 35 | SCRIPTS = ../../scripts 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/trellis_path.mk 38 | include $(SCRIPTS)/trellis_main_ghdl.mk 39 | -------------------------------------------------------------------------------- /examples/ecp5pll/makefilesv.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = ecp5pll 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 26 | TOP_MODULE = top_ecp5pll 27 | TOP_MODULE_FILE = top/v/$(TOP_MODULE).v 28 | 29 | VERILOG_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | hdl/sv/ecp5pll.sv \ 32 | 33 | VHDL_FILES = 34 | 35 | SCRIPTS = ../../scripts 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/diamond_path.mk 38 | include $(SCRIPTS)/diamond_main.mk 39 | -------------------------------------------------------------------------------- /examples/ecp5pll/makefilesv.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = ecp5pll 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../constraints/ulx3s_v20.lpf 21 | TOP_MODULE = top_ecp5pll 22 | TOP_MODULE_FILE = top/v/$(TOP_MODULE).v 23 | 24 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 25 | VERILOG_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | hdl/sv/ecp5pll.sv \ 28 | 29 | # synthesis options 30 | NEXTPNR_OPTIONS = --timing-allow-fail 31 | 32 | SCRIPTS = ../../scripts 33 | include $(SCRIPTS)/diamond_path.mk 34 | include $(SCRIPTS)/trellis_path.mk 35 | include $(SCRIPTS)/trellis_main.mk 36 | -------------------------------------------------------------------------------- /examples/ecp5pll/top/v/top_ecp5pll.v: -------------------------------------------------------------------------------- 1 | module top_ecp5pll 2 | #( 3 | parameter bits = 26 4 | ) 5 | ( 6 | input clk_25mhz, 7 | input [6:0] btn, 8 | output [7:0] led, 9 | output wifi_gpio0 10 | ); 11 | assign wifi_gpio0 = btn[0]; 12 | SGSR gsr (.CLK(clk_25mhz), .GSR(btn[0])); // global state reset example 13 | 14 | wire [3:0] clocks; 15 | ecp5pll 16 | #( 17 | .in_hz(25000000), 18 | .out0_hz(40000000), .out0_tol_hz(0), 19 | .out1_hz(50000000), .out1_deg( 90), .out1_tol_hz(0), 20 | .out2_hz(60000000), .out2_deg(180), .out2_tol_hz(0), 21 | .out3_hz( 6000000), .out3_deg(300), .out3_tol_hz(0) 22 | ) 23 | ecp5pll_inst 24 | ( 25 | .clk_i(clk_25mhz), 26 | .clk_o(clocks) 27 | ); 28 | 29 | generate 30 | genvar i; 31 | for(i = 0; i < 4; i=i+1) 32 | begin 33 | reg [bits-1:0] R_blink; 34 | always @(posedge clocks[i]) 35 | R_blink <= R_blink+1; 36 | assign led[i*2+1:i*2] = R_blink[bits-1:bits-2]; 37 | end 38 | endgenerate 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /examples/eink/eink154/README.md: -------------------------------------------------------------------------------- 1 | # HELTEC E-INK 1.54" BW 200x200 2 | 3 | Micropython ESP32 driver with FPGA pins bypass core 4 | to external pins GP0-4, display directly pluggable. 5 | 6 | Brand : Heltec 7 | Size : 1.54" 8 | Color : Black & White 9 | Resolution : 200x200 10 | Working Voltage : 3.3V 11 | Viewing Angle : >170° 12 | Controller IC : IL3829 13 | Dimension : Approx.4.7x3.1cm/1.85x1.22inch 14 | PCB Color : White with black silkscreen 15 | 16 | Markings on flat cable: 17 | HINK-E0154A07-A1 18 | Date:2017-02-28 19 | SYX 1942 20 | 21 | ebay: 22 | [1.54 Inch E-Paper Module E-Ink Electronic Display Screen SPI Black White Color](https://www.ebay.com/itm/1-54-Inch-E-Paper-Module-E-Ink-Electronic-Display-Screen-SPI-Black-White-Color/392556403310?hash=item5b662f5a6e:g:BfgAAOSwrcRd3W2f) 23 | 24 | compatible driver: 25 | [e-Paper 1.54" V2](https://github.com/waveshare/e-Paper/blob/master/Arduino/epd1in54_V2/epd1in54_V2.cpp) 26 | -------------------------------------------------------------------------------- /examples/eink/eink154/esp32/IL382x.py: -------------------------------------------------------------------------------- 1 | ../../driver/esp32/IL382x.py -------------------------------------------------------------------------------- /examples/eink/eink154/esp32/heltec_eink154bw200x200.py: -------------------------------------------------------------------------------- 1 | # ESP32 micropython 2 | 3 | # display-specific constants 4 | # for Heltec BW 1.54" 200x200 IL3829 5 | # Markings on flat cable: 6 | # HINK-E0154A07-A1 7 | # Date:2017-02-28 8 | # SYX 1942 9 | 10 | class specific: 11 | def __init__(self): 12 | # display resolution 13 | self.width = 200 14 | self.height = 200 15 | # chip, differs in initialization 16 | self.IL = 3829 17 | # this display doesn't need LUTs for partial refresh 18 | self.lut_full_refresh = None 19 | self.lut_partial_refresh = None 20 | # refresh_frame(parameter) 21 | self.full_refresh = 0xF7 22 | self.partial_refresh = 0xFF 23 | -------------------------------------------------------------------------------- /examples/eink/eink154/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/eink/epaper290/esp32/IL382x.py: -------------------------------------------------------------------------------- 1 | ../../driver/esp32/IL382x.py -------------------------------------------------------------------------------- /examples/eink/epaper290/esp32/waveshare_epaper290bw296x128.py: -------------------------------------------------------------------------------- 1 | # ESP32 micropython 2 | 3 | # display-specific constants 4 | # for Waveshare BW 2.9" 296x128 IL3820 5 | 6 | class specific: 7 | def __init__(self): 8 | # display resolution 9 | self.width = 128 10 | self.height = 296 11 | # chip, differs in initialization 12 | self.IL = 3820 13 | # set_lut(parameter) 14 | self.lut_full_refresh=bytearray([ 15 | 0x02, 0x02, 0x01, 0x11, 0x12, 0x12, 16 | 0x22, 0x22, 0x66, 0x69, 0x69, 0x59, 17 | 0x58, 0x99, 0x99, 0x88, 0x00, 0x00, 18 | 0x00, 0x00, 0xF8, 0xB4, 0x13, 0x51, 19 | 0x35, 0x51, 0x51, 0x19, 0x01, 0x00 20 | ]) 21 | self.lut_partial_refresh=bytearray([ 22 | 0x10, 0x18, 0x18, 0x08, 0x18, 0x18, 23 | 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 24 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 25 | 0x00, 0x00, 0x13, 0x14, 0x44, 0x12, 26 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 27 | ]) 28 | # refresh_frame(parameter) 29 | self.full_refresh = 0xC4 30 | self.partial_refresh = 0xC4 31 | -------------------------------------------------------------------------------- /examples/eink/epaper290/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/esp32_passthru/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/esp32_passthru/proj/README.md: -------------------------------------------------------------------------------- 1 | # Minimal passthru for ESP32 programming 2 | 3 | Flash this to FPGA, it will enable ESP32 serial console 4 | and programming from FT231X usb-serial. 5 | 6 | -------------------------------------------------------------------------------- /examples/esp32_passthru/proj/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = passthru 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | #CONSTRAINTS = ../../../constraints/ulx3s_v20.lpf 26 | #CONSTRAINTS = ../../../constraints/ulx3s_v314.lpf 27 | CONSTRAINTS = ../../../constraints/ulx3s_v316.lpf 28 | TOP_MODULE = top_esp32_passthru 29 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 30 | 31 | VERILOG_FILES = \ 32 | $(TOP_MODULE_FILE) \ 33 | hdl/esp32_passthru.v \ 34 | ../../rtc/micropython-mcp7940n/proj/hdl/i2c_bridge.v \ 35 | 36 | SCRIPTS = ../../../scripts 37 | include $(SCRIPTS)/trellis_path.mk 38 | include $(SCRIPTS)/diamond_path.mk 39 | include $(SCRIPTS)/diamond_main.mk 40 | -------------------------------------------------------------------------------- /examples/esp32_rmii/esp32/lan8720wrover.py: -------------------------------------------------------------------------------- 1 | # LAN8720 MODULE 2 | 3 | #GPIO00 - EMAC_TX_CLK : nINT/REFCLK (50MHz) 4 | #GPIO12 - SMI_MDC : MDC (relocateable) 5 | #GPIO4 - SMI_MDIO : MDIO (relocateable) 6 | #GPIO19 - EMAC_TXD0 : TX0 7 | #GPIO21 - EMAC_TX_EN : TX_EN 8 | #GPIO22 - EMAC_TXD1 : TX1 9 | #GPIO25 - EMAC_RXD0 : RX0 10 | #GPIO26 - EMAC_RXD1 : RX1 11 | #GPIO27 - EMAC_RX_DV : CRS 12 | #GND : GND 13 | #3V3 : VCC 14 | 15 | #GPIO23 JTAG_TDI 16 | #GPIO34 JTAG_TDO (was 19) 17 | #GPIO18 JTAG_TCK 18 | #GPIO5 JTAG_TMS (was 21) 19 | 20 | import network 21 | from machine import Pin 22 | lan = network.LAN(mdc=Pin(12), mdio=Pin(4), power=None, id=None, phy_addr=1, phy_type=network.PHY_LAN8720) 23 | lan.active(True) 24 | lan.ifconfig() 25 | #lan.ifconfig(('192.168.18.190', '255.255.255.0', '192.168.18.254', '192.168.18.254')) 26 | 27 | # disconnect GPIO0 and GPIO12, then press power on ESP32 to boot. 28 | # reconnect GPIO0 and GPIO12 and ctrl-D to python prompt 29 | # LAN should connect and print IP address 30 | # download speed with ftp from ESP32 flash is 300KB/s (3Mbps) 31 | -------------------------------------------------------------------------------- /examples/esp32_rmii/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/esp32_rmii/proj/README.md: -------------------------------------------------------------------------------- 1 | # RMII passthru for ESP32 2 | 3 | Not yet working, TODO: analyze MDIO R/W mode for 3-state operation 4 | -------------------------------------------------------------------------------- /examples/esp32_rmii/proj/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = esp32rmii 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | #CONSTRAINTS = ../../../constraints/ulx3s_v314.lpf 26 | CONSTRAINTS = ../../../constraints/ulx3s_v316.lpf 27 | TOP_MODULE = esp32rmii 28 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 29 | 30 | VERILOG_FILES = \ 31 | $(TOP_MODULE_FILE) \ 32 | 33 | SCRIPTS = ../../../scripts 34 | include $(SCRIPTS)/trellis_path.mk 35 | include $(SCRIPTS)/diamond_path.mk 36 | include $(SCRIPTS)/diamond_main.mk 37 | -------------------------------------------------------------------------------- /examples/eth/rmii/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/eth/rmii/proj/arp_reply.mem: -------------------------------------------------------------------------------- 1 | // eth tx len = 82 (LSB first), crc32 = 0xd9fe2a6d 2 | // 0x0000: 3 | 00 00 00 00 00 00 00 00 55 55 55 55 55 55 55 d5 4 | // 0x0010: 5 | ff ff ff ff ff ff 00 40 00 01 02 03 08 06 00 01 6 | // 0x0020: 7 | 08 00 06 04 00 02 00 40 00 01 02 03 c0 a8 12 80 8 | // 0x0030: 9 | ff ff ff ff ff ff c0 a8 12 80 00 00 00 00 00 00 10 | // 0x0040: 11 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 2a 12 | // 0x0050: 13 | fe d9 14 | -------------------------------------------------------------------------------- /examples/eth/rmii/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/eth/rmii/proj/icmp_reply.mem: -------------------------------------------------------------------------------- 1 | // eth tx len = 118 (LSB first), crc32 = 0x5decf338 2 | // 0x0000: 3 | 00 00 00 00 00 00 00 00 55 55 55 55 55 55 55 d5 4 | // 0x0010: 5 | 00 11 22 33 44 55 00 40 00 01 02 03 08 00 45 00 6 | // 0x0020: 7 | 00 54 00 00 00 00 05 01 3e db c0 a8 12 80 c0 a8 8 | // 0x0030: 9 | 12 fe 00 00 22 fc 33 f6 00 16 5f 61 66 5f 00 00 10 | // 0x0040: 11 | 00 00 23 64 01 00 00 00 00 00 10 11 12 13 14 15 12 | // 0x0050: 13 | 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 14 | // 0x0060: 15 | 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 16 | // 0x0070: 17 | 36 37 38 f3 ec 5d 18 | -------------------------------------------------------------------------------- /examples/eth/rmii/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/flash_passthru/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/flash_passthru/proj/README.md: -------------------------------------------------------------------------------- 1 | # FLASH-GPIO passthru 2 | 3 | This is SPI FLASH passthru to external GPIO pins. 4 | Programmer supported by 5 | [flashrom](https://www.flashrom.org/Flashrom) utility 6 | can be connected, like a generic FT2232 JTAG. 7 | 8 | "flashrom" utility supports a lot of different FLASH chips. 9 | Useful if FLASH chip is write protected or not (yet) 10 | supported by "fujprog", "openFPGALoader" and "esp32ecp5". 11 | 12 | | FLASH | ULX3S | FT2232 | JTAG | 13 | |-------|-------|--------|------| 14 | | CLK | GP0 | DBUS0 | TCK | 15 | | MOSI | GP1 | DBUS1 | TDI | 16 | | MISO | GP2 | DBUS2 | TDO | 17 | | CSn | GP3 | DBUS3 | TMS | 18 | -------------------------------------------------------------------------------- /examples/flash_passthru/proj/flashrom.layout: -------------------------------------------------------------------------------- 1 | 00000000:001FFFFF bootloader_bitstream 2 | 00200000:003FFFFF user_bitstream 3 | -------------------------------------------------------------------------------- /examples/flash_passthru/proj/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = flash_passthru 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = constraints/ulx3s_v20_flash.lpf 26 | #CONSTRAINTS = constraints/ulx3s_v314_flash.lpf 27 | #CONSTRAINTS = ../../../constraints/ulx3s_v316.lpf 28 | TOP_MODULE = flash_passthru 29 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 30 | 31 | VERILOG_FILES = \ 32 | $(TOP_MODULE_FILE) \ 33 | 34 | SCRIPTS = ../../../scripts 35 | include $(SCRIPTS)/trellis_path.mk 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/diamond_main.mk 38 | -------------------------------------------------------------------------------- /examples/fm/Makefile: -------------------------------------------------------------------------------- 1 | makefilevhdl.trellis -------------------------------------------------------------------------------- /examples/fm/hdl/message_ps.vhd: -------------------------------------------------------------------------------- 1 | -- automatically generated with rds_msg 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.std_logic_arith.all; 5 | use ieee.std_logic_unsigned.all; 6 | use ieee.numeric_std.all; 7 | package message is 8 | type rds_msg_type is array(0 to 51) of std_logic_vector(7 downto 0); 9 | -- PI=0xCAFE 10 | -- STEREO=No 11 | -- TA=No 12 | -- AF=107.9 MHz 13 | -- PS="TEST1234" 14 | constant rds_msg_map: rds_msg_type := ( 15 | x"ca",x"fe",x"a0",x"01",x"00",x"2e",x"8e",x"1c",x"c2",x"31",x"51",x"15",x"fb", 16 | x"ca",x"fe",x"a0",x"01",x"00",x"75",x"1c",x"dc",x"da",x"cd",x"4d",x"51",x"e9", 17 | x"ca",x"fe",x"a0",x"01",x"00",x"99",x"ac",x"dc",x"da",x"cc",x"c4",x"cb",x"c6", 18 | x"ca",x"fe",x"a0",x"01",x"00",x"c2",x"3c",x"dc",x"da",x"cc",x"cc",x"d2",x"51", 19 | others => (others => '0') 20 | ); 21 | end message; 22 | -------------------------------------------------------------------------------- /examples/fm/top/message_ps.mem: -------------------------------------------------------------------------------- 1 | // PI=0xCAFE 2 | // STEREO=No 3 | // TA=No 4 | // AF=107.9 MHz 5 | // PS="TEST1234" 6 | ca fe a0 01 00 2e 8e 1c c2 31 51 15 fb 7 | ca fe a0 01 00 75 1c dc da cd 4d 51 e9 8 | ca fe a0 01 00 99 ac dc da cc c4 cb c6 9 | ca fe a0 01 00 c2 3c dc da cc cc d2 51 10 | -------------------------------------------------------------------------------- /examples/gray_counter/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefilev.trellis -------------------------------------------------------------------------------- /examples/gray_counter/proj/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = gray_counter 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = ulx3s_gray_counter 23 | TOP_MODULE_FILE = top/vhd/$(TOP_MODULE).vhd 24 | 25 | VHDL_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | ../hdl/vhd/gray_counter.vhd \ 28 | 29 | VERILOG_FILES = \ 30 | 31 | # synthesis options 32 | #YOSYS_OPTIONS = -noccu2 33 | 34 | SCRIPTS = ../../../scripts 35 | include $(SCRIPTS)/trellis_path.mk 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/diamond_main.mk 38 | -------------------------------------------------------------------------------- /examples/gray_counter/proj/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = gray_counter 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = CABGA381 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | #OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = ulx3s_gray_counter 23 | TOP_MODULE_FILE = top/vhd/$(TOP_MODULE).vhd 24 | 25 | VERILOG_FILES = \ 26 | top/v/empty.v \ 27 | 28 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 29 | VHDL_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | ../hdl/vhd/gray_counter.vhd \ 32 | 33 | # synthesis options 34 | #YOSYS_OPTIONS = -noccu2 35 | NEXTPNR_OPTIONS = --timing-allow-fail 36 | 37 | SCRIPTS = ../../../scripts 38 | include $(SCRIPTS)/diamond_path.mk 39 | include $(SCRIPTS)/trellis_path.mk 40 | include $(SCRIPTS)/trellis_main_ghdl.mk 41 | -------------------------------------------------------------------------------- /examples/gray_counter/proj/makefilev.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = gray_counter 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = CABGA381 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | #OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = ulx3s_gray_counter 23 | TOP_MODULE_FILE = top/v/$(TOP_MODULE).v 24 | 25 | VERILOG_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | ../hdl/v/gray_counter.v \ 28 | 29 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 30 | #VHDL_FILES = \ 31 | 32 | # synthesis options 33 | #YOSYS_OPTIONS = -noccu2 34 | NEXTPNR_OPTIONS = --timing-allow-fail 35 | 36 | SCRIPTS = ../../../scripts 37 | include $(SCRIPTS)/diamond_path.mk 38 | include $(SCRIPTS)/trellis_path.mk 39 | include $(SCRIPTS)/trellis_main.mk 40 | -------------------------------------------------------------------------------- /examples/gray_counter/proj/top/v/empty.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/ulx3s-misc/8c07331dd1f9492a8c08bd4bb0b6495ae7630664/examples/gray_counter/proj/top/v/empty.v -------------------------------------------------------------------------------- /examples/hex/decoder/README.md: -------------------------------------------------------------------------------- 1 | # simplified hex decoder 2 | displays 7x5 font in 8x8 grid 3 | -------------------------------------------------------------------------------- /examples/hex/dvi_hex/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/hex/dvi_hex/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/hex/lcd_lvds_hex/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile-480x272.trellis -------------------------------------------------------------------------------- /examples/hex/lcd_lvds_hex/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/hex/lcd_st7789_hex/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/hex/lcd_st7789_hex/proj/README.md: -------------------------------------------------------------------------------- 1 | # OLED HEX display demo 2 | 3 | IPS 240*240 LED displays with ST7789 4 | 5 | cleanup: 6 | 7 | make -f makefile.trellis clean 8 | 9 | compile: 10 | 11 | make -f makefile.trellis 12 | 13 | program (upload to SRAM, temporary): 14 | 15 | make -f makefile.trellis prog 16 | 17 | or 18 | 19 | make -f makefile.trellis prog_ocd 20 | 21 | -------------------------------------------------------------------------------- /examples/hex/lcd_st7789_hex/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/hex/lcd_st7789_hex/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1306_hex/proj/README.md: -------------------------------------------------------------------------------- 1 | # OLED display demo 2 | 3 | Currently only checkered display is shown on ssd1306. 4 | Picture X-offset is random and varies between resets. 5 | 6 | cleanup: 7 | 8 | make -f makefile.trellis clean 9 | 10 | compile: 11 | 12 | make -f makefile.trellis 13 | 14 | program (upload to SRAM, temporary): 15 | 16 | make -f makefile.trellis program 17 | 18 | or 19 | 20 | make -f makefile.trellis program_ocd 21 | 22 | -------------------------------------------------------------------------------- /examples/hex/oled_ssd1306_hex/proj/hex_font_h.mem: -------------------------------------------------------------------------------- 1 | ../../decoder/hex_font_h.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1306_hex/proj/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/hex/oled_ssd1306_hex/proj/ssd1306_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/ssd1306_linit_xflip.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1306_hex/proj/ssd1306_linit_yflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/ssd1306_linit_yflip.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1306_hex/proj/ssd1306_oinit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1306_video_verilog/ssd1306_oinit_xflip.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1331_hex/proj/README.md: -------------------------------------------------------------------------------- 1 | # OLED HEX display demo 2 | 3 | cleanup: 4 | 5 | make -f makefile.trellis clean 6 | 7 | compile: 8 | 9 | make -f makefile.trellis 10 | 11 | program (upload to SRAM, temporary): 12 | 13 | make -f makefile.trellis program 14 | 15 | or 16 | 17 | make -f makefile.trellis program_ocd 18 | 19 | -------------------------------------------------------------------------------- /examples/hex/oled_ssd1331_hex/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1331_hex/proj/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/hex/oled_ssd1331_hex/proj/oled_init_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_init_xflip.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1331_hex/proj/oled_init_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_init_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1331_hex/proj/ssd1331_linit_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/ssd1331_linit_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1351_hex/proj/README.md: -------------------------------------------------------------------------------- 1 | # OLED HEX display demo 2 | 3 | SSD1351 initializes to random color pixel screen, 4 | picture is slightly dim, probably it's normal for larger OLEDs. 5 | 6 | cleanup: 7 | 8 | make -f makefile.trellis clean 9 | 10 | compile: 11 | 12 | make -f makefile.trellis 13 | 14 | program (upload to SRAM, temporary): 15 | 16 | make -f makefile.trellis program 17 | 18 | or 19 | 20 | make -f makefile.trellis program_ocd 21 | 22 | -------------------------------------------------------------------------------- /examples/hex/oled_ssd1351_hex/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1351_hex/proj/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/hex/oled_ssd1351_hex/proj/ssd1351_linit_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/ssd1351_linit_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/hex/oled_ssd1351_hex/proj/ssd1351_oinit_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1351_video_verilog/ssd1351_oinit_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/jtag_slave/doc/jtag-slave.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/ulx3s-misc/8c07331dd1f9492a8c08bd4bb0b6495ae7630664/examples/jtag_slave/doc/jtag-slave.pdf -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_passthru_v/Arduino/jtagwalkesp32/tap.h: -------------------------------------------------------------------------------- 1 | #ifndef TAP_H 2 | #define TAP_H 3 | 4 | #include "libxsvf.h" 5 | #include 6 | 7 | #define TCK 14 8 | #define TMS 15 9 | #define TDI 13 10 | #define TDO 12 11 | 12 | extern SPIClass *spi_jtag; 13 | 14 | static void tap_transition(struct libxsvf_host *h, int v); 15 | int libxsvf_tap_walk(struct libxsvf_host *h, enum libxsvf_tap_state s); 16 | #endif 17 | -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_passthru_v/README.md: -------------------------------------------------------------------------------- 1 | # JTAG slave terminal 2 | 3 | cleanup: 4 | 5 | make -f makefile.trellis clean 6 | 7 | compile: 8 | 9 | make -f makefile.trellis 10 | 11 | program (upload to SRAM, temporary): 12 | 13 | make -f makefile.trellis program 14 | 15 | or 16 | 17 | make -f makefile.trellis program_ocd 18 | 19 | usage: 20 | 21 | make scan 22 | 23 | On OLED rows have this meaning 24 | 25 | bin TDI 26 | hex TMS 27 | hex TDI 28 | hex TDO 29 | 30 | TDO row should display JTAG ID 149511C3 31 | 32 | -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_passthru_v/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_passthru_v/oled_font.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_font.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_passthru_v/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_passthru_v/oled_init_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_init_xflip.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_passthru_v/oled_init_yflip.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_init_yflip.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_v/README.md: -------------------------------------------------------------------------------- 1 | # JTAG slave terminal 2 | 3 | cleanup: 4 | 5 | make -f makefile.trellis clean 6 | 7 | compile: 8 | 9 | make -f makefile.trellis 10 | 11 | program (upload to SRAM, temporary): 12 | 13 | make -f makefile.trellis program 14 | 15 | or 16 | 17 | make -f makefile.trellis program_ocd 18 | 19 | usage: 20 | 21 | make scan 22 | 23 | On OLED rows have this meaning 24 | 25 | bin TDI 26 | hex TMS 27 | hex TDI 28 | hex TDO 29 | 30 | TDO row should display JTAG ID 149511C3 31 | Trellis always works. Diamond works but unreliable. 32 | -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_v/jtag-slave-scan.ocd: -------------------------------------------------------------------------------- 1 | # OpenOCD commands 2 | 3 | telnet_port 4444 4 | gdb_port 3333 5 | 6 | # JTAG TAPs 7 | jtag newtap jtagslave tap -expected-id 0x149511c3 -irlen 4 -irmask 0xF -ircapture 0x5 8 | 9 | init 10 | scan_chain 11 | svf -tap jtagslave.tap jtag-slave-test.svf 12 | shutdown 13 | -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_v/jtag-slave-test.svf: -------------------------------------------------------------------------------- 1 | HDR 0; 2 | HIR 0; 3 | TDR 0; 4 | TIR 0; 5 | ENDDR DRPAUSE; 6 | ENDIR IRPAUSE; 7 | STATE IDLE; 8 | 9 | SDR 35 TDI (ABCDEF01) 10 | TDO (149511c3) 11 | MASK (FFFFFFFF); 12 | ! after this OLED should display: 13 | ! 3011110101010000 14 | ! 4000000002FEC06F 15 | ! 0ABCDEF010007E00 16 | ! 1149511C3FE1EBFF 17 | 18 | ! examples of some valid tap state walks 19 | !STATE RESET; 20 | !STATE RESET IDLE DRSELECT DRCAPTURE DRSHIFT DREXIT1 DRPAUSE DREXIT2 DRUPDATE IDLE RESET; 21 | !STATE RESET IDLE DRSELECT DRCAPTURE DRSHIFT DREXIT1 DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE DREXIT2 DRUPDATE IDLE; 22 | -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_v/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_v/oled_font.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_font.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_v/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_v/oled_init_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_init_xflip.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtag_hex_v/oled_init_yflip.mem: -------------------------------------------------------------------------------- 1 | ../../../oled/hdl/ssd1331_video_verilog/oled_init_yflip.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtagg_hex_v/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtagg_hex_v/README.md: -------------------------------------------------------------------------------- 1 | # JTAGG vendor specific demo 2 | 3 | JTAGG module allows user bitstream to receive JTAG traffic from 4 | standard JTAG pins. JTAG master (openocd SVF in this example) 5 | needs to send few vendor specific JTAG commands to put vendor-specific 6 | JTAG slave interface into bypass state. 7 | 8 | cleanup: 9 | 10 | make clean 11 | 12 | compile: 13 | 14 | make 15 | 16 | program (upload to SRAM, temporary): 17 | 18 | make prog 19 | 20 | or 21 | 22 | make prog_ocd 23 | make prog_ofl 24 | 25 | usage: 26 | 27 | make scan 28 | 29 | On LCD rows have this meaning 30 | 31 | bin TDI 32 | hex TMS 33 | hex TDI 34 | hex TDO (not used currently) 35 | 36 | TDI row should display 0x600DBABE87654321 37 | 38 | # Links 39 | 40 | [HADBADGE verilog core](https://github.com/Spritetm/hadbadge2019_fpgasoc/blob/4ae8277c45e17e316bb4d46ce625c1507506cd36/soc/top_fpga.v#L312-L322) 41 | 42 | [HADBADGE svf generator](https://github.com/Spritetm/hadbadge2019_fpgasoc/blob/master/soc/jtagload/main.c) 43 | -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtagg_hex_v/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtagg_hex_v/jtagg-slave-scan.ocd: -------------------------------------------------------------------------------- 1 | # OpenOCD commands 2 | 3 | telnet_port 4444 4 | gdb_port 3333 5 | 6 | # JTAG TAPs 7 | jtag newtap jtagslave tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5 8 | 9 | init 10 | scan_chain 11 | svf -tap jtagslave.tap jtagg-slave-test.svf 12 | shutdown 13 | -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtagg_hex_v/jtagg-slave-test.svf: -------------------------------------------------------------------------------- 1 | HDR 0; 2 | HIR 0; 3 | TDR 0; 4 | TIR 0; 5 | ENDDR IDLE; 6 | ENDIR IDLE; 7 | STATE IDLE; 8 | 9 | SIR 8 TDI (38); 10 | SDR 32 TDI (ABCD1234); 11 | SIR 8 TDI (32); 12 | SDR 32 TDI (87654321); 13 | SIR 8 TDI (38); 14 | SDR 32 TDI (AAAA5555); 15 | SIR 8 TDI (32); 16 | SDR 32 TDI (600DBABE); 17 | 18 | ! after this HEX should display: 19 | ! 0011000000000110 20 | ! 0000000000000000 21 | ! 600DBABE87654321 22 | ! 0000000000000000 23 | -------------------------------------------------------------------------------- /examples/jtag_slave/proj/ulx3s_jtagg_hex_v/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/jtagthru/hdl/jtagthru.v: -------------------------------------------------------------------------------- 1 | module jtagthru 2 | ( 3 | input clk_25mhz, 4 | input [6:0] btn, 5 | output [7:0] led, 6 | output ftdi_rxd, 7 | input ftdi_txd, ftdi_nrts, ftdi_ndtr, 8 | inout [27:0] gp, gn, 9 | output wifi_gpio0 10 | ); 11 | assign wifi_gpio0 = btn[0]; 12 | 13 | wire ftdi_rxd, ftdi_txd, ftdi_nrts, ftdi_ndtr; 14 | wire jtag_tdo, jtag_tdi, jtag_tms, jtag_clk; 15 | assign jtag_tdo = gn[14]; 16 | assign gp[15] = jtag_tdi; 17 | assign gp[14] = jtag_tms; 18 | assign gn[15] = jtag_clk; 19 | 20 | localparam ctr_width = 28; 21 | localparam ctr_max = 2**ctr_width - 1; 22 | 23 | reg [ctr_width-1:0] R_blinky = 0; 24 | always @ (posedge clk_25mhz) 25 | begin 26 | R_blinky <= R_blinky+1; 27 | end 28 | 29 | assign led[7:4] = {R_blinky[ctr_width-1:ctr_width-4]}; 30 | 31 | assign led[0] = jtag_tdo; 32 | assign led[1] = ftdi_txd; 33 | assign led[2] = ftdi_nrts; 34 | assign led[3] = ftdi_ndtr; 35 | 36 | assign ftdi_rxd = jtag_tdo; 37 | assign jtag_tdi = ftdi_txd; 38 | assign jtag_tms = ftdi_nrts; 39 | assign jtag_clk = ftdi_ndtr; 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /examples/jtagthru/proj/ulx3s_jtagthru/README.md: -------------------------------------------------------------------------------- 1 | # JTAG thru 2 | 3 | Diamond works, trellis not yet. 4 | 5 | -------------------------------------------------------------------------------- /examples/jtagthru/proj/ulx3s_jtagthru/makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/jtagthru/proj/ulx3s_jtagthru/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = init 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 25 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_segpdi.lpf 26 | TOP_MODULE = jtagthru 27 | TOP_MODULE_FILE = ../../hdl/$(TOP_MODULE).v 28 | 29 | VERILOG_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | 32 | VHDL_FILES = 33 | 34 | SCRIPTS = ../../../../scripts/ 35 | include $(SCRIPTS)/trellis_path.mk 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/diamond_main.mk 38 | -------------------------------------------------------------------------------- /examples/jtagthru/proj/ulx3s_jtagthru/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = jtagthru 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_segpdi.lpf 21 | TOP_MODULE = jtagthru 22 | TOP_MODULE_FILE = ../../hdl/$(TOP_MODULE).v 23 | 24 | VERILOG_FILES = \ 25 | $(TOP_MODULE_FILE) \ 26 | 27 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 28 | VHDL_FILES = 29 | 30 | SCRIPTS = ../../../../scripts/ 31 | include $(SCRIPTS)/diamond_path.mk 32 | include $(SCRIPTS)/trellis_path.mk 33 | include $(SCRIPTS)/trellis_main.mk 34 | -------------------------------------------------------------------------------- /examples/lcd35/README.md: -------------------------------------------------------------------------------- 1 | # simple demo for VGA LCD 2 | 3 | ULX3S with a 3.5" PMOD LCD display with open 4 | source [PCB and schematics](https://github.com/daveshah1/pmods). 5 | 6 | This source is tested on ULX3S, plugged to the right side of ULX3S 7 | 8 | 9 | -------------------------------------------------------------------------------- /examples/lcd35/box/lcd35.scad: -------------------------------------------------------------------------------- 1 | xdisp = 77; 2 | ydisp = 64-2; 3 | zdisp = 3.5; // thickness of LCD itself 4 | ynopcb = 32; // length without PCB 5 | ycoverpcb = 47; // part of y-lcd covered with PCB 6 | zlcdpcb = 6; // thickness of LCD including PCB 7 | 8 | xview = 74; // view opening x 9 | yview = 57; // view opening y 10 | 11 | wthick = 2; // wall thickness 12 | 13 | module dispouter() 14 | { 15 | cube([xdisp+2*wthick, ydisp+2*wthick, zlcdpcb+2*wthick], center=true); 16 | } 17 | 18 | module dispcutter() 19 | { 20 | addcut = 10; 21 | cube([xdisp,addcut + ydisp, zdisp], center=true); 22 | translate([0,-addcut -ydisp/2+ycoverpcb/2,-zdisp/2+0*zlcdpcb/2-0.001]) 23 | cube([xdisp,ycoverpcb,zlcdpcb],center=true); 24 | } 25 | 26 | module dispcover() 27 | { 28 | difference() 29 | { 30 | dispouter(); 31 | // cut inside 32 | translate([0,-5,1.5]) 33 | dispcutter(); 34 | // cut opening 35 | translate([0,-3,6]) 36 | cube([xview,yview+8,10],center=true); 37 | } 38 | } 39 | 40 | 41 | dispcover(); 42 | -------------------------------------------------------------------------------- /examples/lcd35/proj/lattice/ulx3s/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = lcd35 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../../../../constraints/ulx3s_v20_segpdi.lpf 26 | TOP_MODULE = top 27 | TOP_MODULE_FILE = ../../../rtl/lattice/top/top_cable.v 28 | # TOP_MODULE_FILE = ../../../rtl/lattice/top/top_90deg.v 29 | VERILOG_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | ../../../rtl/video.v \ 32 | ../../../rtl/lattice/clocks_diamond/clk_25m_287m5_19m17.v 33 | VHDL_FILES = 34 | 35 | SCRIPTS = ../../../../../scripts 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/diamond_path.mk 38 | include $(SCRIPTS)/diamond_main.mk 39 | -------------------------------------------------------------------------------- /examples/lcd35/proj/lattice/ulx3s/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = lcd35 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../../../../constraints/ulx3s_v20_segpdi.lpf 21 | TOP_MODULE = top 22 | TOP_MODULE_FILE = ../../../rtl/lattice/top/top_cable.v 23 | # TOP_MODULE_FILE = ../../../rtl/lattice/top/top_90deg.v 24 | VERILOG_FILES = \ 25 | $(TOP_MODULE_FILE) \ 26 | ../../../rtl/video.v \ 27 | ../../../rtl/lattice/clocks_trellis/clk_25m_287m5_19m17.v 28 | VHDL_FILES = 29 | 30 | # synthesis options 31 | #YOSYS_OPTIONS = -noccu2 32 | 33 | SCRIPTS = ../../../../../scripts 34 | include $(SCRIPTS)/diamond_path.mk 35 | include $(SCRIPTS)/trellis_path.mk 36 | include $(SCRIPTS)/trellis_main.mk 37 | -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240/README.md: -------------------------------------------------------------------------------- 1 | # LCD ST7789 1.3" Color 240x240 2 | 3 | Micropython ESP32 driver with FPGA pins bypass core 4 | to OLED connector, display directly pluggable. 5 | -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240/proj/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = st7789 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | #OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../../../../constraints/ulx3s_v20.lpf 26 | TOP_MODULE = top_st7789 27 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 28 | 29 | VERILOG_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | 32 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 33 | VHDL_FILES = \ 34 | 35 | SCRIPTS = ../../../../../scripts/ 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/diamond_path.mk 38 | include $(SCRIPTS)/diamond_main.mk 39 | -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240/proj/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = st7789 3 | 4 | BOARD = ulx3s 5 | # 12 25 45 85 6 | FPGA_SIZE = 12 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../../../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = top_st7789 23 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 24 | 25 | VERILOG_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | 28 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 29 | VHDL_FILES = \ 30 | 31 | YOSYS_OPTIONS = -abc9 32 | NEXTPNR_OPTIONS = --timing-allow-fail 33 | 34 | SCRIPTS = ../../../../../scripts/ 35 | include $(SCRIPTS)/diamond_path.mk 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/trellis_main.mk 38 | -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240_polyline/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240_polyline/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240_polyline/proj/st7789_linit.mem: -------------------------------------------------------------------------------- 1 | ../../../../spi_display/hdl/spi_display_verilog/st7789_linit.mem -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240_polyline/proj/st7789_linit_pixels.mem: -------------------------------------------------------------------------------- 1 | hdl/st7789_linit_pixels.mem -------------------------------------------------------------------------------- /examples/lcd_st7789/micropython/st7789_240x240_polyline/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/led64x64/README.md: -------------------------------------------------------------------------------- 1 | # Example for 64x64 LED panel 2 | 3 | It runs 24bpp animated video test picture on 4 | one 64x64 LED panel at 11.8 kHz refresh rate 5 | flickerfree with minumum possible blanking 6 | time providing max intensity. 7 | 8 | It's precisely 25 MHz / (32 * 66) = 11837 FPS :) 9 | -------------------------------------------------------------------------------- /examples/led64x64/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = led64x64 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../constraints/ulx3s_v20_segpdi.lpf 26 | TOP_MODULE = top 27 | TOP_MODULE_FILE = emard/top.v 28 | VERILOG_FILES = \ 29 | $(TOP_MODULE_FILE) 30 | VHDL_FILES = \ 31 | emard/ledscan.vhd 32 | 33 | SCRIPTS = ../../scripts 34 | include $(SCRIPTS)/trellis_path.mk 35 | include $(SCRIPTS)/diamond_path.mk 36 | include $(SCRIPTS)/diamond_main.mk 37 | -------------------------------------------------------------------------------- /examples/led64x64/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = led64x64 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../constraints/ulx3s_v20_segpdi.lpf 21 | TOP_MODULE = top 22 | TOP_MODULE_FILE = emard/top.v 23 | VERILOG_FILES = \ 24 | $(TOP_MODULE_FILE) 25 | VHDL_FILES = \ 26 | emard/ledscan.vhd 27 | 28 | # synthesis options 29 | #YOSYS_OPTIONS = -noccu2 30 | 31 | SCRIPTS = ../../scripts 32 | include $(SCRIPTS)/diamond_path.mk 33 | include $(SCRIPTS)/trellis_path.mk 34 | include $(SCRIPTS)/trellis_main.mk 35 | -------------------------------------------------------------------------------- /examples/lvds_passthru/Makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/lvds_passthru/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = lvds_passthru 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = constraints/ulx3s_v20.lpf 26 | TOP_MODULE = top_lvds_passthru 27 | TOP_MODULE_FILE = hdl/$(TOP_MODULE).vhd 28 | 29 | VERILOG_FILES = 30 | 31 | VHDL_FILES = \ 32 | $(TOP_MODULE_FILE) \ 33 | ../ecp5pll/hdl/vhd/ecp5pll.vhd \ 34 | ../lvds/hdl/lvds2vga.vhd \ 35 | ../lvds/hdl/vga2lvds.vhd \ 36 | ../dvi/hdl/vga2dvid.vhd \ 37 | ../dvi/hdl/tmds_encoder.vhd \ 38 | 39 | 40 | SCRIPTS = ../../scripts 41 | include $(SCRIPTS)/trellis_path.mk 42 | include $(SCRIPTS)/diamond_path.mk 43 | include $(SCRIPTS)/diamond_main.mk 44 | -------------------------------------------------------------------------------- /examples/multiboot/README.md: -------------------------------------------------------------------------------- 1 | # MULTIBOOT 2 | 3 | Flash can contain multiple bitstreams. 4 | Press BTN0 to exit current bitstream and jump to next one. 5 | After the last, it loads the first. 6 | 7 | make flash_ofl 8 | 9 | In this example, each bitstream supports exit because 10 | it reads BTN0 and when pressed long enough (debouncing fuze), 11 | it pulls down USER_PROGRAMN signal which exits currently 12 | running bitstream and loads next one from flash. 13 | 14 | User can solder D28 diode then BTN0 changes function: 15 | BTN0 will hard-pull PROGRAMN and unconditionally exit 16 | any running bitstream and load next one from flash. 17 | With D28 BTN0 can't be used as normal input button 18 | so D28 diode is not soldered as factory default. 19 | 20 | https://github.com/emard/ulx3s/blob/master/doc/MANUAL.md 21 | -------------------------------------------------------------------------------- /examples/multiboot/bitstream0/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/multiboot/bitstream0/bitstream0.v: -------------------------------------------------------------------------------- 1 | // AUTHOR=EMARD 2 | // LICENSE=BSD 3 | 4 | // turn on LED 5 | // exit bitstream on BTN0 with timed fuze 6 | 7 | module bitstream0 8 | ( 9 | input clk_25mhz, 10 | input [6:0] btn, 11 | output [7:0] led, 12 | output user_programn 13 | ); 14 | assign led = 8'b00000001; 15 | // press BTN0 to exit this bitstream 16 | reg [19:0] R_delay_reload = 0; 17 | always @(posedge clk_25mhz) 18 | if(R_delay_reload[19]==0) 19 | R_delay_reload <= R_delay_reload+1; 20 | assign user_programn = btn[0] | ~R_delay_reload[19]; 21 | endmodule 22 | -------------------------------------------------------------------------------- /examples/multiboot/bitstream0/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = bitstream0 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* design files ******* 8 | CONSTRAINTS = ../../../constraints/ulx3s_v20.lpf 9 | TOP_MODULE = ${PROJECT} 10 | TOP_MODULE_FILE = $(TOP_MODULE).v 11 | 12 | VERILOG_FILES = \ 13 | $(TOP_MODULE_FILE) \ 14 | 15 | # synthesis options 16 | #YOSYS_OPTIONS = -noccu2 17 | #NEXTPNR_OPTIONS = --timing-allow-fail 18 | 19 | SCRIPTS = ../../../scripts 20 | include $(SCRIPTS)/diamond_path.mk 21 | include $(SCRIPTS)/trellis_path.mk 22 | include $(SCRIPTS)/trellis_main.mk 23 | -------------------------------------------------------------------------------- /examples/multiboot/bitstream1/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/multiboot/bitstream1/bitstream1.v: -------------------------------------------------------------------------------- 1 | // AUTHOR=EMARD 2 | // LICENSE=BSD 3 | 4 | // turn on LED 5 | // exit bitstream on BTN0 with timed fuze 6 | 7 | module bitstream1 8 | ( 9 | input clk_25mhz, 10 | input [6:0] btn, 11 | output [7:0] led, 12 | output user_programn 13 | ); 14 | assign led = 8'b00000010; 15 | // press BTN0 to exit this bitstream 16 | reg [19:0] R_delay_reload = 0; 17 | always @(posedge clk_25mhz) 18 | if(R_delay_reload[19]==0) 19 | R_delay_reload <= R_delay_reload+1; 20 | assign user_programn = btn[0] | ~R_delay_reload[19]; 21 | endmodule 22 | -------------------------------------------------------------------------------- /examples/multiboot/bitstream1/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = bitstream1 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* design files ******* 8 | CONSTRAINTS = ../../../constraints/ulx3s_v20.lpf 9 | TOP_MODULE = ${PROJECT} 10 | TOP_MODULE_FILE = $(TOP_MODULE).v 11 | 12 | VERILOG_FILES = \ 13 | $(TOP_MODULE_FILE) \ 14 | 15 | # synthesis options 16 | #YOSYS_OPTIONS = -noccu2 17 | #NEXTPNR_OPTIONS = --timing-allow-fail 18 | 19 | SCRIPTS = ../../../scripts 20 | include $(SCRIPTS)/diamond_path.mk 21 | include $(SCRIPTS)/trellis_path.mk 22 | include $(SCRIPTS)/trellis_main.mk 23 | -------------------------------------------------------------------------------- /examples/multiboot/bitstream2/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/multiboot/bitstream2/bitstream2.v: -------------------------------------------------------------------------------- 1 | // AUTHOR=EMARD 2 | // LICENSE=BSD 3 | 4 | // turn on LED 5 | // exit bitstream on BTN0 with timed fuze 6 | 7 | module bitstream2 8 | ( 9 | input clk_25mhz, 10 | input [6:0] btn, 11 | output [7:0] led, 12 | output user_programn 13 | ); 14 | assign led = 8'b00000100; 15 | // press BTN0 to exit this bitstream 16 | reg [19:0] R_delay_reload = 0; 17 | always @(posedge clk_25mhz) 18 | if(R_delay_reload[19]==0) 19 | R_delay_reload <= R_delay_reload+1; 20 | assign user_programn = btn[0] | ~R_delay_reload[19]; 21 | endmodule 22 | -------------------------------------------------------------------------------- /examples/multiboot/bitstream2/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = bitstream2 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* design files ******* 8 | CONSTRAINTS = ../../../constraints/ulx3s_v20.lpf 9 | TOP_MODULE = ${PROJECT} 10 | TOP_MODULE_FILE = $(TOP_MODULE).v 11 | 12 | VERILOG_FILES = \ 13 | $(TOP_MODULE_FILE) \ 14 | 15 | # synthesis options 16 | #YOSYS_OPTIONS = -noccu2 17 | #NEXTPNR_OPTIONS = --timing-allow-fail 18 | 19 | SCRIPTS = ../../../scripts 20 | include $(SCRIPTS)/diamond_path.mk 21 | include $(SCRIPTS)/trellis_path.mk 22 | include $(SCRIPTS)/trellis_main.mk 23 | -------------------------------------------------------------------------------- /examples/multiboot/gzip4k.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # gzip-compress file on PC using small block size 4K, 4 | # suitable for unzipping at devices with small RAM, 5 | # micropython friendly 6 | 7 | import os, sys, zlib 8 | 9 | def gzip4k(fname_src, fname_dst): 10 | stream = open(fname_src, "rb") 11 | comp = zlib.compressobj(level=9, wbits=16 + 12) 12 | with open(fname_dst, "wb") as outf: 13 | while 1: 14 | data = stream.read(1024) 15 | if not data: 16 | break 17 | outf.write(comp.compress(data)) 18 | outf.write(comp.flush()) 19 | 20 | if __name__ == "__main__": 21 | gzip4k(sys.argv[1], sys.argv[2]) 22 | -------------------------------------------------------------------------------- /examples/nmigen/dvi/blink.py: -------------------------------------------------------------------------------- 1 | from nmigen import * 2 | from nmigen.build import Platform 3 | 4 | 5 | class Blink(Elaboratable): 6 | def __init__(self, bits): 7 | self.o_led = Signal(8) 8 | # Configuration 9 | self.bits = bits 10 | 11 | def elaborate(self, platform: Platform) -> Module: 12 | m = Module() 13 | 14 | R_counter = Signal(self.bits) 15 | m.d.pixel += R_counter.eq(R_counter + 1) 16 | m.d.comb += self.o_led.eq(R_counter[(self.bits - 8):]) 17 | 18 | return m -------------------------------------------------------------------------------- /examples/nmigen/dvi/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | export PATH="/mt/scratch/tmp/openfpga/oss-cad-suite/py3bin/:$PATH" 3 | python3 top_vgatest.py 12F 4 | -------------------------------------------------------------------------------- /examples/oled/hdl/ssd1306_video_verilog/ssd1306_oinit.mem: -------------------------------------------------------------------------------- 1 | // SSD1306 init for oled-only driver, UNTESTED 2 | // same sequence is for spi and i2c 3 | // This file must be in the directory from where 4 | // the verilog compiler is running. 5 | // The path to this file is not relative to the 6 | // verilog source that needs to include this file. 7 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 8 | // 31 bytes follow: 9 | // SSD1306_DISPLAYOFF 10 | AE 11 | // SSD1306_SETDISPLAYCLOCKDIV 12 | D5 13 | F0 14 | // SSD1306_SETMULTIPLEX 15 | A8 16 | 3F 17 | // SSD1306_SETDISPLAYOFFSET 18 | D3 19 | 00 20 | // SSD1306_SETSTARTLINE 21 | 40 22 | // SSD1306_CHARGEPUMP 23 | 8D 24 | 14 25 | // SSD1306_MEMORYMODE 26 | 20 27 | 00 28 | // SSD1306_SEGREMAP A0/A1 29 | A1 30 | // SSD1306_COMSCANDEC C0/C8 31 | C8 32 | // SSD1306_SETCOMPINS 33 | DA 34 | 12 35 | // SSD1306_SETCONTRAST 36 | 81 37 | CF 38 | // SSD1306_SETPRECHARGE 39 | D9 40 | F1 41 | // SSD1306_SETVCOMDESELECT 42 | D8 43 | 40 44 | // SSD1306_DISPLAYALLON_RESUME 45 | A4 46 | // SSD1306_NORMALDISPLAY 47 | A6 48 | // SSD1306_DISPLAYON 49 | AF 50 | // set column address 51 | 21 52 | 00 53 | 7F 54 | // set page address 55 | 22 56 | 00 57 | 07 58 | -------------------------------------------------------------------------------- /examples/oled/hdl/ssd1306_video_verilog/ssd1306_oinit_xflip.mem: -------------------------------------------------------------------------------- 1 | // SSD1306 init for oled-only driver, UNTESTED 2 | // same sequence is for spi and i2c 3 | // This file must be in the directory from where 4 | // the verilog compiler is running. 5 | // The path to this file is not relative to the 6 | // verilog source that needs to include this file. 7 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 8 | // 31 bytes follow: 9 | // SSD1306_DISPLAYOFF 10 | AE 11 | // SSD1306_SETDISPLAYCLOCKDIV 12 | D5 13 | F0 14 | // SSD1306_SETMULTIPLEX 15 | A8 16 | 3F 17 | // SSD1306_SETDISPLAYOFFSET 18 | D3 19 | 00 20 | // SSD1306_SETSTARTLINE 21 | 40 22 | // SSD1306_CHARGEPUMP 23 | 8D 24 | 14 25 | // SSD1306_MEMORYMODE 26 | 20 27 | 00 28 | // SSD1306_SEGREMAP A0/A1 29 | A1 30 | // SSD1306_COMSCANDEC C0/C8 31 | C0 32 | // SSD1306_SETCOMPINS 33 | DA 34 | 12 35 | // SSD1306_SETCONTRAST 36 | 81 37 | CF 38 | // SSD1306_SETPRECHARGE 39 | D9 40 | F1 41 | // SSD1306_SETVCOMDESELECT 42 | D8 43 | 40 44 | // SSD1306_DISPLAYALLON_RESUME 45 | A4 46 | // SSD1306_NORMALDISPLAY 47 | A6 48 | // SSD1306_DISPLAYON 49 | AF 50 | // set column address 51 | 21 52 | 00 53 | 7F 54 | // set page address 55 | 22 56 | 00 57 | 07 58 | -------------------------------------------------------------------------------- /examples/oled/hdl/ssd1306_video_verilog/ssd1306_oinit_xyflip.mem: -------------------------------------------------------------------------------- 1 | // SSD1306 init for oled-only driver, UNTESTED 2 | // same sequence is for spi and i2c 3 | // This file must be in the directory from where 4 | // the verilog compiler is running. 5 | // The path to this file is not relative to the 6 | // verilog source that needs to include this file. 7 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 8 | // 31 bytes follow: 9 | // SSD1306_DISPLAYOFF 10 | AE 11 | // SSD1306_SETDISPLAYCLOCKDIV 12 | D5 13 | F0 14 | // SSD1306_SETMULTIPLEX 15 | A8 16 | 3F 17 | // SSD1306_SETDISPLAYOFFSET 18 | D3 19 | 00 20 | // SSD1306_SETSTARTLINE 21 | 40 22 | // SSD1306_CHARGEPUMP 23 | 8D 24 | 14 25 | // SSD1306_MEMORYMODE 26 | 20 27 | 00 28 | // SSD1306_SEGREMAP A0/A1 29 | A0 30 | // SSD1306_COMSCANDEC C0/C8 31 | C0 32 | // SSD1306_SETCOMPINS 33 | DA 34 | 12 35 | // SSD1306_SETCONTRAST 36 | 81 37 | CF 38 | // SSD1306_SETPRECHARGE 39 | D9 40 | F1 41 | // SSD1306_SETVCOMDESELECT 42 | D8 43 | 40 44 | // SSD1306_DISPLAYALLON_RESUME 45 | A4 46 | // SSD1306_NORMALDISPLAY 47 | A6 48 | // SSD1306_DISPLAYON 49 | AF 50 | // set column address 51 | 21 52 | 00 53 | 7F 54 | // set page address 55 | 22 56 | 00 57 | 07 58 | -------------------------------------------------------------------------------- /examples/oled/hdl/ssd1306_video_verilog/ssd1306_oinit_yflip.mem: -------------------------------------------------------------------------------- 1 | // SSD1306 init for oled-only driver, UNTESTED 2 | // same sequence is for spi and i2c 3 | // This file must be in the directory from where 4 | // the verilog compiler is running. 5 | // The path to this file is not relative to the 6 | // verilog source that needs to include this file. 7 | // Use symlink (ln -s orig copy) or copy (cp orig copy). 8 | // 31 bytes follow: 9 | // SSD1306_DISPLAYOFF 10 | AE 11 | // SSD1306_SETDISPLAYCLOCKDIV 12 | D5 13 | F0 14 | // SSD1306_SETMULTIPLEX 15 | A8 16 | 3F 17 | // SSD1306_SETDISPLAYOFFSET 18 | D3 19 | 00 20 | // SSD1306_SETSTARTLINE 21 | 40 22 | // SSD1306_CHARGEPUMP 23 | 8D 24 | 14 25 | // SSD1306_MEMORYMODE 26 | 20 27 | 00 28 | // SSD1306_SEGREMAP A0/A1 29 | A0 30 | // SSD1306_COMSCANDEC C0/C8 31 | C8 32 | // SSD1306_SETCOMPINS 33 | DA 34 | 12 35 | // SSD1306_SETCONTRAST 36 | 81 37 | CF 38 | // SSD1306_SETPRECHARGE 39 | D9 40 | F1 41 | // SSD1306_SETVCOMDESELECT 42 | D8 43 | 40 44 | // SSD1306_DISPLAYALLON_RESUME 45 | A4 46 | // SSD1306_NORMALDISPLAY 47 | A6 48 | // SSD1306_DISPLAYON 49 | AF 50 | // set column address 51 | 21 52 | 00 53 | 7F 54 | // set page address 55 | 22 56 | 00 57 | 07 58 | -------------------------------------------------------------------------------- /examples/oled/hdl/ssd1331_term_verilog/font_rom.v: -------------------------------------------------------------------------------- 1 | module font_rom( 2 | input clk, 3 | input [11:0] addr, 4 | output reg [7:0] data_out 5 | ); 6 | 7 | reg [7:0] store[0:4095]; 8 | 9 | initial 10 | begin 11 | $readmemh("font_vga.mem", store); 12 | end 13 | 14 | always @(posedge clk) 15 | data_out <= store[addr]; 16 | endmodule 17 | -------------------------------------------------------------------------------- /examples/oled/hdl/ssd1331_term_verilog/pll.v: -------------------------------------------------------------------------------- 1 | module pll(input clki, 2 | output locked, 3 | output clko 4 | ); 5 | wire clkfb; 6 | wire clkos; 7 | wire clkop; 8 | (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) 9 | EHXPLLL #( 10 | .PLLRST_ENA("DISABLED"), 11 | .INTFB_WAKE("DISABLED"), 12 | .STDBY_ENABLE("DISABLED"), 13 | .DPHASE_SOURCE("DISABLED"), 14 | .CLKOP_FPHASE(0), 15 | .CLKOP_CPHASE(23), 16 | .OUTDIVIDER_MUXA("DIVA"), 17 | .CLKOP_ENABLE("ENABLED"), 18 | .CLKOP_DIV(48), 19 | .CLKFB_DIV(1), 20 | .CLKI_DIV(2), 21 | .FEEDBK_PATH("INT_OP") 22 | ) pll_i ( 23 | .CLKI(clki), 24 | .CLKFB(clkfb), 25 | .CLKINTFB(clkfb), 26 | .CLKOP(clkop), 27 | .RST(1'b0), 28 | .STDBY(1'b0), 29 | .PHASESEL0(1'b0), 30 | .PHASESEL1(1'b0), 31 | .PHASEDIR(1'b0), 32 | .PHASESTEP(1'b0), 33 | .PLLWAKESYNC(1'b0), 34 | .ENCLKOP(1'b0), 35 | .LOCK(locked) 36 | ); 37 | assign clko = clkop; 38 | endmodule 39 | -------------------------------------------------------------------------------- /examples/oled/micropython/README.md: -------------------------------------------------------------------------------- 1 | # ESP32 micropython -> passthru -> OLED 2 | 3 | This is example of micropython code running 4 | on ESP32 and driving OLED through FPGA using 5 | "passthru" bitstream. 6 | 7 | # TODO 8 | 9 | [ ] buffer for all line commands for 1 char 10 | send 1 long SPI command instead of many short ones 11 | [ ] init sequences for 4 screen orientations 12 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/README.md: -------------------------------------------------------------------------------- 1 | # OLED terminal 2 | 3 | cleanup: 4 | 5 | make -f makefile.trellis clean 6 | 7 | compile: 8 | 9 | make -f makefile.trellis 10 | 11 | program (upload to SRAM, temporary): 12 | 13 | make -f makefile.trellis program 14 | 15 | or 16 | 17 | make -f makefile.trellis program_ocd 18 | 19 | usage: 20 | 21 | screen /dev/ttyUSB0 115200 22 | 23 | type some text... 24 | 25 | to exit: 26 | 27 | ctrl-a \ 28 | 29 | or 30 | 31 | ctrl-a altgr-q 32 | 33 | # trellis-diamond difference 34 | 35 | For bitstream compiled with diamond, 36 | unwanted dot will appear at bottom of 37 | each character. 38 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = init 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 85 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_segpdi.lpf 26 | TOP_MODULE = top_checkered 27 | TOP_MODULE_FILE = ../../hdl/ssd1331_video_verilog/top/$(TOP_MODULE).v 28 | 29 | VERILOG_FILES = \ 30 | $(TOP_MODULE_FILE) \ 31 | ../../hdl/ssd1331_video_verilog/oled_video.v \ 32 | ../../hdl/ssd1331_term_verilog/pll.v 33 | 34 | VHDL_FILES = 35 | 36 | SCRIPTS = ../../../../scripts/ 37 | include $(SCRIPTS)/trellis_path.mk 38 | include $(SCRIPTS)/diamond_path.mk 39 | include $(SCRIPTS)/diamond_main.mk 40 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = init 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_segpdi.lpf 21 | TOP_MODULE = top_checkered 22 | TOP_MODULE_FILE = ../../hdl/ssd1331_video_verilog/top/$(TOP_MODULE).v 23 | 24 | VERILOG_FILES = \ 25 | $(TOP_MODULE_FILE) \ 26 | ../../hdl/ssd1331_video_verilog/oled_video.v \ 27 | ../../hdl/ssd1331_term_verilog/pll.v \ 28 | 29 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 30 | VHDL_FILES = 31 | 32 | SCRIPTS = ../../../../scripts/ 33 | include $(SCRIPTS)/diamond_path.mk 34 | include $(SCRIPTS)/trellis_path.mk 35 | include $(SCRIPTS)/trellis_main.mk 36 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_font.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_font.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_init_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_16bit.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_init_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_xflip.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_init_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_init_xyflip.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_xyflip.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_init_xyflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_xyflip_16bit.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_init_yflip.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_yflip.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_checkered_v/oled_init_yflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_yflip_16bit.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_hex_vhdl/README.md: -------------------------------------------------------------------------------- 1 | # SPI OLED core in VHDL 2 | 3 | This VHDL core displays HEX digits at SSD1331 color OLED display, 4 | showing realtime state of input parallel bus. It's useful 5 | for onboard debugging. 6 | 7 | After a fixed initialization sequence is sent to OLED, 8 | state machine continuoulsy decodes input bus state to HEX 9 | digits and displays it using simple 7x5 font. 10 | 11 | # TODO 12 | 13 | It copies input bus state to a register and with 14 | MUX fetches parts of it to be decoded and diplayed 15 | to OLED's using its feature to sequentially increments 16 | write pointer after each write. 17 | 18 | The MUX is not optimal to have in FPGA. It would be probably 19 | better to only shift bus state, fetching its data sequentially 20 | and from the state machine send commands which will change 21 | OLED's write pointer. 22 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_oled_vga_vhdl/README.md: -------------------------------------------------------------------------------- 1 | # SPI OLED VGA core in VHDL 2 | 3 | This VHDL core takes VGA style input 4 | (pixel clock, RGB pixel data, vsync, hsync, blank) 5 | and display it as video on OLED screen. 6 | 7 | overscan - runs both VGA and OLED at the same clock domain 8 | 9 | VGA generates faster frame rate than SPI can send. 10 | OLED SPI sends pixel by its speed and waits until both 11 | Y counters from input and output match to update next scanline. 12 | OLED timing is achieved with standard format of VGA timings 13 | by setting large horizontal porch timings (around 1900). 14 | 15 | for fast frame updates, VGA generator needs to be slowed down by clk_pixel_ena 16 | otherwise it can work also but screen update will be unacceptably slow (0.5Hz frame rate) 17 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_oled_vga_vhdl/makefile: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = oled_vga 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | FPGA_PACKAGE = 6bg381c 8 | # config flash: 1:SPI (standard), 4:QSPI (quad) 9 | FLASH_SPI = 4 10 | # chip: is25lp032d is25lp128f s25fl164k 11 | FLASH_CHIP = is25lp128f 12 | 13 | # ******* if programming with OpenOCD ******* 14 | # using local latest openocd until in linux distribution 15 | OPENOCD=openocd_ft232r 16 | # default onboard usb-jtag 17 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 18 | # ulx3s-jtag-passthru 19 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 20 | # ulx2s 21 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 22 | # external jtag 23 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 24 | 25 | # ******* design files ******* 26 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_segpdi.lpf 27 | TOP_MODULE = ulx3s_oled_vga 28 | TOP_MODULE_FILE = top/$(TOP_MODULE).vhd 29 | 30 | VERILOG_FILES = 31 | 32 | VHDL_FILES = \ 33 | $(TOP_MODULE_FILE) \ 34 | ../../../dvi/hdl/vga.vhd \ 35 | ../../hdl/ssd1331_vga_vhdl/oled_vga.vhd \ 36 | ../../hdl/ssd1331_vga_vhdl/oled_vga_init_pack.vhd 37 | 38 | SCRIPTS = ../../../../scripts 39 | include $(SCRIPTS)/trellis_path.mk 40 | include $(SCRIPTS)/diamond_path.mk 41 | include $(SCRIPTS)/diamond_main.mk 42 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_spi_hex_v/README.md: -------------------------------------------------------------------------------- 1 | # OLED SPI sniffer HEX display 2 | 3 | cleanup: 4 | 5 | make -f makefile.trellis clean 6 | 7 | compile: 8 | 9 | make -f makefile.trellis 10 | 11 | program (upload to SRAM, temporary): 12 | 13 | make -f makefile.trellis program 14 | 15 | or 16 | 17 | make -f makefile.trellis program_ocd 18 | 19 | usage: 20 | 21 | screen /dev/ttyUSB0 115200 22 | 23 | type some text... 24 | 25 | to exit: 26 | 27 | ctrl-a \ 28 | 29 | or 30 | 31 | ctrl-a altgr-q 32 | 33 | # trellis-diamond difference 34 | 35 | For bitstream compiled with diamond, 36 | unwanted dot will appear at bottom of 37 | each character. 38 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_spi_hex_v/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_spi_hex_v/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = oled_spi_hex 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 85 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_segpdi.lpf 21 | TOP_MODULE = top_spi_hex 22 | TOP_MODULE_FILE = ../../hdl/ssd1331_video_verilog/top/$(TOP_MODULE).v 23 | 24 | VERILOG_FILES = \ 25 | $(TOP_MODULE_FILE) \ 26 | ../../hdl/ssd1331_video_verilog/oled_video.v \ 27 | ../../hdl/ssd1331_video_verilog/hex_decoder.v \ 28 | ../../hdl/ssd1331_video_verilog/spi/spi_slave.v \ 29 | ../../hdl/ssd1331_term_verilog/pll.v \ 30 | 31 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 32 | VHDL_FILES = 33 | 34 | SCRIPTS = ../../../../scripts/ 35 | include $(SCRIPTS)/diamond_path.mk 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/trellis_main.mk 38 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_spi_hex_v/oled_font.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_font.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_spi_hex_v/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_spi_hex_v/oled_init_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_xflip.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_spi_hex_v/oled_init_yflip.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init_yflip.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_terminal/README.md: -------------------------------------------------------------------------------- 1 | # OLED terminal 2 | 3 | cleanup: 4 | 5 | make -f makefile.trellis clean 6 | 7 | compile: 8 | 9 | make -f makefile.trellis 10 | 11 | program (upload to SRAM, temporary): 12 | 13 | make -f makefile.trellis program 14 | 15 | or 16 | 17 | make -f makefile.trellis program_ocd 18 | 19 | usage: 20 | 21 | screen /dev/ttyUSB0 115200 22 | 23 | type some text... 24 | 25 | to exit: 26 | 27 | ctrl-a \ 28 | 29 | or 30 | 31 | ctrl-a altgr-q 32 | 33 | # trellis-diamond difference 34 | 35 | For bitstream compiled with diamond, 36 | unwanted dot will appear at bottom of 37 | each character. 38 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_terminal/font_vga.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_term_verilog/font_vga.mem -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_terminal/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_terminal/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = terminal 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 85 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_segpdi.lpf 21 | TOP_MODULE = top 22 | TOP_MODULE_FILE = ../../hdl/ssd1331_term_verilog/$(TOP_MODULE).v 23 | 24 | VERILOG_FILES = \ 25 | $(TOP_MODULE_FILE) \ 26 | ../../hdl/ssd1331_term_verilog/pll.v \ 27 | ../../hdl/ssd1331_video_verilog/oled_video.v \ 28 | ../../hdl/ssd1331_term_verilog/font_rom.v \ 29 | ../../hdl/ssd1331_term_verilog/uart_rx.v 30 | 31 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 32 | VHDL_FILES = 33 | 34 | SCRIPTS = ../../../../scripts/ 35 | include $(SCRIPTS)/diamond_path.mk 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/trellis_main.mk 38 | -------------------------------------------------------------------------------- /examples/oled/proj/ulx3s_terminal/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/onchip_osc_blink/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/onchip_osc_blink/README.md: -------------------------------------------------------------------------------- 1 | # OSCG on-chip oscillator 2 | 3 | LED blinky using on-chip oscillator module "OSCG". 4 | It doesn't need external clock source. 5 | -------------------------------------------------------------------------------- /examples/onchip_osc_blink/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = oscg_blink 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | FPGA_PACKAGE = 6bg381c 8 | # config flash: 1:SPI (standard), 4:QSPI (quad) 9 | FLASH_SPI = 4 10 | # chip: is25lp032d is25lp128f s25fl164k 11 | FLASH_CHIP = is25lp128f 12 | 13 | # ******* if programming with OpenOCD ******* 14 | # using local latest openocd until in linux distribution 15 | OPENOCD=openocd_ft232r 16 | # default onboard usb-jtag 17 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 18 | # ulx3s-jtag-passthru 19 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 20 | # ulx2s 21 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 22 | # external jtag 23 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 24 | 25 | # ******* design files ******* 26 | CONSTRAINTS = ../../constraints/ulx3s_v20_segpdi.lpf 27 | TOP_MODULE = oscg_blink 28 | TOP_MODULE_FILE = $(TOP_MODULE).v 29 | 30 | VERILOG_FILES = \ 31 | $(TOP_MODULE_FILE) \ 32 | 33 | SCRIPTS = ../../scripts 34 | include $(SCRIPTS)/trellis_path.mk 35 | include $(SCRIPTS)/diamond_path.mk 36 | include $(SCRIPTS)/diamond_main.mk 37 | -------------------------------------------------------------------------------- /examples/onchip_osc_blink/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = oscg_blink 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | OPENOCD=openocd_ft232r 8 | 9 | # ******* design files ******* 10 | CONSTRAINTS = ../../constraints/ulx3s_v20_segpdi.lpf 11 | TOP_MODULE = oscg_blink 12 | TOP_MODULE_FILE = $(TOP_MODULE).v 13 | 14 | VERILOG_FILES = \ 15 | $(TOP_MODULE_FILE) \ 16 | 17 | # synthesis options 18 | #YOSYS_OPTIONS = -noccu2 19 | NEXTPNR_OPTIONS = --timing-allow-fail 20 | 21 | SCRIPTS = ../../scripts 22 | include $(SCRIPTS)/diamond_path.mk 23 | include $(SCRIPTS)/trellis_path.mk 24 | include $(SCRIPTS)/trellis_main.mk 25 | -------------------------------------------------------------------------------- /examples/onchip_osc_blink/oscg_blink.v: -------------------------------------------------------------------------------- 1 | // AUTHOR=EMARD 2 | // LICENSE=BSD 3 | 4 | // blink LED example using on-chip oscillator 5 | 6 | module oscg_blink 7 | ( 8 | output [7:0] led, 9 | input [6:0] btn 10 | //output wifi_gpio0 11 | ); 12 | parameter oscillator_divider = 12; // f=310MHz/divider = 310/12 = 25.8 MHz 13 | parameter counter_bits = 28; 14 | 15 | //assign wifi_gpio0 = btn[0]; 16 | 17 | wire clk; 18 | 19 | // on-chip oscillator 20 | OSCG 21 | #( 22 | .DIV(oscillator_divider) // freq = 310MHz/div, div = 2..128 23 | ) 24 | oscg_instance 25 | ( 26 | .OSC(clk) 27 | ); 28 | 29 | reg [counter_bits-1:0] counter; 30 | always @(posedge clk) 31 | counter <= counter + 1; 32 | 33 | assign led = counter[counter_bits-1:counter_bits-8]; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /examples/onchip_osc_blink_ffm/README.md: -------------------------------------------------------------------------------- 1 | # OSCG on-chip oscillator 2 | 3 | LED blinky using on-chip oscillator module "OSCG". 4 | It doesn't need external clock source. 5 | -------------------------------------------------------------------------------- /examples/onchip_osc_blink_ffm/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/onchip_osc_blink_ffm/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = oscg_blink 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 85 6 | 7 | FPGA_PACKAGE = 6bg554c 8 | # config flash: 1:SPI (standard), 4:QSPI (quad) 9 | FLASH_SPI = 4 10 | # chip: is25lp032d is25lp128f s25fl164k 11 | FLASH_CHIP = is25lp128f 12 | 13 | # ******* if programming with OpenOCD ******* 14 | # using local latest openocd until in linux distribution 15 | OPENOCD=openocd 16 | # default onboard usb-jtag 17 | OPENOCD_INTERFACE=$(SCRIPTS)/ft4232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../constraints/FFM-LFE5U-V0r0_mit_FFC-CA7-V2r0.lpf 21 | TOP_MODULE = oscg_blink 22 | TOP_MODULE_FILE = $(TOP_MODULE).v 23 | 24 | VERILOG_FILES = \ 25 | $(TOP_MODULE_FILE) \ 26 | 27 | SCRIPTS = ../../scripts 28 | include $(SCRIPTS)/trellis_path.mk 29 | include $(SCRIPTS)/diamond_path.mk 30 | include $(SCRIPTS)/diamond_main.mk 31 | -------------------------------------------------------------------------------- /examples/onchip_osc_blink_ffm/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = oscg_blink 3 | BOARD = ffmlfe5 4 | # 12 25 45 85 5 | FPGA_SIZE = 85 6 | FPGA_PACKAGE = CABGA554 7 | 8 | OPENOCD=openocd 9 | # default onboard usb-jtag 10 | OPENOCD_INTERFACE=$(SCRIPTS)/ft4232.ocd 11 | 12 | # ******* design files ******* 13 | CONSTRAINTS = ../../constraints/FFM-LFE5U-V0r0_mit_FFC-CA7-V2r0.lpf 14 | TOP_MODULE = oscg_blink 15 | TOP_MODULE_FILE = $(TOP_MODULE).v 16 | 17 | VERILOG_FILES = \ 18 | $(TOP_MODULE_FILE) \ 19 | 20 | # synthesis options 21 | #YOSYS_OPTIONS = -noccu2 22 | #NEXTPNR_OPTIONS = --timing-allow-fail 23 | 24 | SCRIPTS = ../../scripts 25 | include $(SCRIPTS)/diamond_path.mk 26 | include $(SCRIPTS)/trellis_path.mk 27 | include $(SCRIPTS)/trellis_main.mk 28 | -------------------------------------------------------------------------------- /examples/onchip_osc_blink_ffm/oscg_blink.v: -------------------------------------------------------------------------------- 1 | // AUTHOR=EMARD 2 | // LICENSE=BSD 3 | 4 | // blink LED example using on-chip oscillator 5 | 6 | module oscg_blink 7 | ( 8 | output [3:1] led 9 | ); 10 | parameter oscillator_divider = 12; // f=310MHz/divider = 310/12 = 25.8 MHz 11 | parameter counter_bits = 28; 12 | 13 | wire clk; 14 | 15 | // on-chip oscillator 16 | OSCG 17 | #( 18 | .DIV(oscillator_divider) // freq = 310MHz/div, div = 2..128 19 | ) 20 | oscg_instance 21 | ( 22 | .OSC(clk) 23 | ); 24 | 25 | reg [counter_bits-1:0] counter; 26 | always @(posedge clk) 27 | counter <= counter + 1; 28 | 29 | assign led = counter[counter_bits-1:counter_bits-3]; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /examples/ov7670_dvi/hdl/hvsync_generator.v: -------------------------------------------------------------------------------- 1 | module hvsync_generator( 2 | clk, 3 | vga_h_sync, 4 | vga_v_sync, 5 | inDisplayArea, 6 | CounterX, 7 | CounterY 8 | ); 9 | 10 | input clk; 11 | output vga_h_sync, vga_v_sync; 12 | output inDisplayArea; 13 | output [9:0] CounterX; 14 | output [8:0] CounterY; 15 | 16 | ////////////////////////////////////////////////// 17 | reg [9:0] CounterX; 18 | reg [8:0] CounterY; 19 | wire CounterXmaxed = (CounterX==10'h2FF); 20 | 21 | always @(posedge clk) 22 | if(CounterXmaxed) 23 | CounterX <= 0; 24 | else 25 | CounterX <= CounterX + 1; 26 | 27 | always @(posedge clk) 28 | if(CounterXmaxed) CounterY <= CounterY + 1; 29 | 30 | reg vga_HS, vga_VS; 31 | always @(posedge clk) 32 | begin 33 | vga_HS <= (CounterX[9:4]==6'h2D); // change this value to move the display horizontally 34 | vga_VS <= (CounterY==500); // change this value to move the display vertically 35 | end 36 | 37 | reg inDisplayArea; 38 | always @(posedge clk) 39 | if(inDisplayArea==0) 40 | inDisplayArea <= (CounterXmaxed) && (CounterY<480); 41 | else 42 | inDisplayArea <= !(CounterX==639); 43 | 44 | assign vga_h_sync = ~vga_HS; 45 | assign vga_v_sync = ~vga_VS; 46 | 47 | endmodule 48 | 49 | -------------------------------------------------------------------------------- /examples/ov7670_dvi/hdl/vgabuff.v: -------------------------------------------------------------------------------- 1 | module vgabuff( 2 | input clk, 3 | input [14:0] raddr, 4 | input [14:0] waddr, 5 | input we, 6 | input [15:0] pixout, 7 | output reg [15:0] pixin 8 | ); 9 | 10 | //(16 * 640 * 480) / 96 -- do not know if this is correct 11 | reg [15:0] mem [0:51200]; 12 | 13 | always @(posedge clk) begin 14 | if (we) begin 15 | mem[waddr] <= pixout; 16 | end 17 | pixin <= mem[raddr]; 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /examples/ov7670_dvi/proj/ulx3s_ov7670_dvi/makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/ps2/kbd/hdl/top/kbd_top.v: -------------------------------------------------------------------------------- 1 | // AUTHOR=Paul Ruiz 2 | // LICENSE=BSD 3 | 4 | module kbd_top 5 | ( 6 | input clk_25mhz, 7 | input [6:0] btn, 8 | output [7:0] led, 9 | output wire usb_fpga_pu_dp, usb_fpga_pu_dn, 10 | input wire usb_fpga_bd_dp, usb_fpga_bd_dn, 11 | output wire wifi_gpio0 12 | ); 13 | 14 | wire clk_25mhz; 15 | 16 | assign wifi_gpio0 = btn[0]; 17 | 18 | // enable pull ups on both D+ and D- 19 | assign usb_fpga_pu_dp = 1'b1; 20 | assign usb_fpga_pu_dn = 1'b1; 21 | 22 | wire ps2clk = usb_fpga_bd_dp; 23 | wire ps2data = usb_fpga_bd_dn; 24 | 25 | ps2kbd kbd(clk_25mhz, ps2clk, ps2data, led, , ); 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /examples/ps2/kbd/proj/lattice/ulx3s/README.md: -------------------------------------------------------------------------------- 1 | # PS/2 Keyboard 2 | 3 | Code from Grant Searle converted to verilog and adapted for ULX3S 4 | by Paul Ruiz. 5 | 6 | Logitech UltraX Premium USB+PS/2 keyboard works in PS/2 mode. 7 | -------------------------------------------------------------------------------- /examples/ps2/kbd/proj/lattice/ulx3s/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/ps2/kbd/proj/lattice/ulx3s/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = ps2mouse 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../../../../../constraints/ulx3s_v20_segpdi.lpf 26 | 27 | TOP_MODULE = kbd_top 28 | TOP_MODULE_FILE = ../../../hdl/top/$(TOP_MODULE).v 29 | 30 | VERILOG_FILES = \ 31 | $(TOP_MODULE_FILE) \ 32 | ../../../hdl/ps2kbd.v \ 33 | 34 | SCRIPTS = ../../../../../../scripts 35 | 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/diamond_path.mk 38 | include $(SCRIPTS)/diamond_main.mk 39 | -------------------------------------------------------------------------------- /examples/ps2/kbd/proj/lattice/ulx3s/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = ps2mouse 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = CABGA381 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | 22 | CONSTRAINTS = ../../../../../../constraints/ulx3s_v20_segpdi.lpf 23 | 24 | TOP_MODULE = kbd_top 25 | TOP_MODULE_FILE = ../../../hdl/top/$(TOP_MODULE).v 26 | 27 | VERILOG_FILES = \ 28 | $(TOP_MODULE_FILE) \ 29 | ../../../hdl/ps2kbd.v \ 30 | 31 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 32 | #VHDL_FILES = \ 33 | # ../../../hdl/mousem.vhd \ 34 | # hdl/vga.vhd \ 35 | # hdl/vga2dvid.vhd \ 36 | # hdl/tmds_encoder.vhd 37 | 38 | SCRIPTS = ../../../../../../scripts 39 | 40 | include $(SCRIPTS)/diamond_path.mk 41 | include $(SCRIPTS)/trellis_path.mk 42 | include $(SCRIPTS)/trellis_main.mk 43 | -------------------------------------------------------------------------------- /examples/ps2/mouse/proj/lattice/ulx3s/README.md: -------------------------------------------------------------------------------- 1 | # Mouse from Minimig and Oberon 2 | 3 | Toplevel parameter selects either minimig or oberon mouse core 4 | at compile time. I don't know about compatibilty but oberon 5 | source is shorter, simpler and has slightly more reliable mouse 6 | initialization. 7 | 8 | After mouse re-plug, reset must be pressed for both cores to 9 | get mouse working again. 10 | 11 | Microsoft IntelliMouse Optical USB/PS2 12 | 13 | X/Y movement works. 14 | Left and Right buttons work. 15 | Wheel press (aka middle button) works. 16 | Wheel rotation works with oberon "MouseM". 17 | 2 side buttons don't work. 18 | 19 | Logitech Wheel Mouse M-BT58 USB/PS2 20 | 21 | X/Y movement works. 22 | Left and Right buttons work. 23 | Wheel press (aka middle button) works. 24 | Wheel rotation works with oberon "MouseM". 25 | 26 | The initialization procedure is not very plug-n-play. 27 | Here's a manual procedure that gets it working: 28 | 29 | 0. plug mouse out 30 | 1. upload this bitstream 31 | 2. click btn0 to reset 32 | 3. plug mouse in 33 | 4. click btn0 to reset 34 | 5. click mouse left/right buttons and move mouse, LEDs will show it 35 | -------------------------------------------------------------------------------- /examples/ps2/mouse/proj/lattice/ulx3s/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/ps2/mouse_dvi/proj/lattice/ffmlfe5/README.md: -------------------------------------------------------------------------------- 1 | # Mouse from Minimig 2 | 3 | Mouse doesn't work on FFM board, probably some electrical reason? 4 | 5 | Microsoft IntelliMouse Optical USB/PS2 6 | 7 | X/Y movement works. 8 | Left and Right mouse button clicks works. 9 | Other buttons don't work. 10 | 11 | Logitech Wheel Mouse M-BT58 USB/PS2 12 | 13 | X/Y movement works. 14 | Left, Right button clicks and Wheel press (aka middle button) work. 15 | 16 | Wheel rotation is not supported yet. 17 | 18 | The initialization procedure is not very plug-n-play. 19 | Here's a manual procedure that gets it working: 20 | 21 | 0. plug mouse out 22 | 1. upload this bitstream 23 | 2. click btn0 to reset 24 | 3. plug mouse in 25 | 4. click btn0 to reset 26 | 5. click mouse left/right buttons and move mouse, LEDs will show it 27 | -------------------------------------------------------------------------------- /examples/ps2/mouse_dvi/proj/lattice/ffmlfe5/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/ps2/mouse_dvi/proj/lattice/ulx3s/README.md: -------------------------------------------------------------------------------- 1 | # Mouse from Minimig 2 | 3 | Microsoft IntelliMouse Optical USB/PS2 4 | 5 | X/Y movement works. 6 | Left and Right mouse button clicks works. 7 | Other buttons don't work. 8 | 9 | Logitech Wheel Mouse M-BT58 USB/PS2 10 | 11 | X/Y movement works. 12 | Left, Right button clicks and Wheel press (aka middle button) work. 13 | 14 | Wheel rotation is not supported yet. 15 | 16 | The initialization procedure is not very plug-n-play. 17 | Here's a manual procedure that gets it working: 18 | 19 | 0. plug mouse out 20 | 1. upload this bitstream 21 | 2. click btn0 to reset 22 | 3. plug mouse in 23 | 4. click btn0 to reset 24 | 5. click mouse left/right buttons and move mouse, LEDs will show it 25 | -------------------------------------------------------------------------------- /examples/ps2/mouse_dvi/proj/lattice/ulx3s/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/ps2/mouse_dvi_gui/proj/lattice/ulx3s/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/ps2/mouse_oled/proj/lattice/ulx3s/README.md: -------------------------------------------------------------------------------- 1 | # Mouse from Minimig 2 | 3 | Microsoft IntelliMouse Optical USB/PS2 4 | 5 | X/Y movement works. 6 | Left and Right mouse button clicks works. 7 | Other buttons don't work. 8 | 9 | Logitech Wheel Mouse M-BT58 USB/PS2 10 | 11 | X/Y movement works. 12 | Left, Right button clicks and Wheel press (aka middle button) work. 13 | 14 | Wheel rotation is not supported yet. 15 | 16 | The initialization procedure is not very plug-n-play. 17 | Here's a manual procedure that gets it working: 18 | 19 | 0. plug mouse out 20 | 1. upload this bitstream 21 | 2. click btn0 to reset 22 | 3. plug mouse in 23 | 4. click btn0 to reset 24 | 5. click mouse left/right buttons and move mouse, LEDs will show it 25 | -------------------------------------------------------------------------------- /examples/ps2/mouse_oled/proj/lattice/ulx3s/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/ps2/mouse_oled/proj/lattice/ulx3s/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../../../../oled/hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/ps2/mouse_oled/proj/lattice/ulx3s/oled_init_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../../../oled/hdl/ssd1331_video_verilog/oled_init_16bit.mem -------------------------------------------------------------------------------- /examples/ps2/mouse_oled_dvi/proj/lattice/ulx3s/README.md: -------------------------------------------------------------------------------- 1 | # Mouse from Minimig 2 | 3 | Microsoft IntelliMouse Optical USB/PS2 4 | 5 | X/Y movement works. 6 | Left and Right mouse button clicks works. 7 | Other buttons don't work. 8 | 9 | Logitech Wheel Mouse M-BT58 USB/PS2 10 | 11 | X/Y movement works. 12 | Left, Right button clicks and Wheel press (aka middle button) work. 13 | 14 | Wheel rotation is not supported yet. 15 | 16 | The initialization procedure is not very plug-n-play. 17 | Here's a manual procedure that gets it working: 18 | 19 | 0. plug mouse out 20 | 1. upload this bitstream 21 | 2. click btn0 to reset 22 | 3. plug mouse in 23 | 4. click btn0 to reset 24 | 5. click mouse left/right buttons and move mouse, LEDs will show it 25 | -------------------------------------------------------------------------------- /examples/ps2/mouse_oled_dvi/proj/lattice/ulx3s/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/ps2/mouse_oled_dvi/proj/lattice/ulx3s/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../../../../oled/hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/ps2/mouse_oled_dvi/proj/lattice/ulx3s/oled_init_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../../../oled/hdl/ssd1331_video_verilog/oled_init_16bit.mem -------------------------------------------------------------------------------- /examples/rtc/i2c_master/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/rtc/i2c_master/proj/README.md: -------------------------------------------------------------------------------- 1 | # RTC MCP7940N verilog example 2 | 3 | i2c master example that reads time from onboard real-time-clock 4 | chip MCP7940N. Date and time is provided in BCD format, 5 | suitable to be 6 | displayed on a HEX decoder. 7 | ST7789 LCD HEX decoder core is used. 8 | Additionally seconds in BCD format are also displayed on LEDs. 9 | 10 | If LEDs don't blink each second, RTC is not "ticking". 11 | Clock must be initialized which means writing to its 12 | registers values that enable battery operation, 13 | set clock "speed" adjustment, set current time and start 14 | the clock. After this seconds will be advancing and clock "ticking". 15 | 16 | example "micropython-mcp7940n/esp32/rtcdemo.py" can be used to 17 | initialize the clock 18 | 19 | If lithium battery CR1225 3V is installed, clock will keep 20 | ticking during power off. If there's no battery RTC will keep 21 | settings and ticking only during power is on and forget settings 22 | at power off. 23 | 24 | -------------------------------------------------------------------------------- /examples/rtc/i2c_master/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/rtc/i2c_master/proj/makefile8bit.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = mcp7940n 3 | 4 | BOARD = ulx3s 5 | # 12 25 45 85 6 | FPGA_SIZE = 12 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../../../constraints/ulx3s_v20.lpf 22 | TOP_MODULE = top_mcp7940n_rtc_8bit 23 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 24 | 25 | VERILOG_FILES = \ 26 | $(TOP_MODULE_FILE) \ 27 | hdl/i2c_master.v \ 28 | hdl/i2c_master_8bit.v \ 29 | ../../../spi_display/hdl/spi_display_verilog/lcd_video.v \ 30 | ../../../hex/decoder/hex_decoder_v.v \ 31 | 32 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 33 | VHDL_FILES = \ 34 | 35 | YOSYS_OPTIONS = -abc9 36 | NEXTPNR_OPTIONS = --timing-allow-fail 37 | 38 | SCRIPTS = ../../../../scripts/ 39 | include $(SCRIPTS)/diamond_path.mk 40 | include $(SCRIPTS)/trellis_path.mk 41 | include $(SCRIPTS)/trellis_main.mk 42 | -------------------------------------------------------------------------------- /examples/rtc/i2c_master/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/rtc/micropython-mcp7940n/README.md: -------------------------------------------------------------------------------- 1 | # RTC demo with e-ink display 2 | 3 | This example demonstrates low-power features, shutdown and wake-on-RTC. 4 | 5 | Every minute board will power ON, connect to WiFi, update RTC from NTP 6 | display time on e-ink display and power OFF. 7 | 8 | If NTP is available, "NT" will be displayed. 9 | If NTP is not available, "MC" will be displayed 10 | and clock will keep on working solely from RTC MCP7940N. 11 | 12 | ESP32 micropython code handles i2c, RTC, NTP and e-ink display. 13 | 14 | FPGA bitstream bridges i2c, SPI and shutdown fuze logic. 15 | 16 | # Requirements 17 | 18 | RTC battery CR1225 3V 19 | 20 | e-ink display Heltec 1.54" V2 200x200 Black&White. 21 | 22 | ULX3S has to power OFF and ON each minute. 23 | 24 | Power ULX3S from US2 connector to allow automatic power OFF and ON. 25 | Press BTN0 to start process for the first time. 26 | 27 | When powered from US1, ULX3S will not power OFF by default. 28 | FT231X could be reconfigured to allow power OFF from US1 by 29 | turning OFF green LED D18. 30 | 31 | Bitstream should be compiled with diamond 32 | (trellis bidirectional vector issues) 33 | and written to config FLASH for this example to work 34 | (make flash or ujprog -j flash bitstream.bit) 35 | 36 | # Links 37 | 38 | [RTC](https://github.com/mattytrentini/micropython-mcp7940) 39 | -------------------------------------------------------------------------------- /examples/rtc/micropython-mcp7940n/esp32/setrtc.py: -------------------------------------------------------------------------------- 1 | from machine import Pin, I2C, SDCard, freq 2 | from os import mount 3 | import time, ntptime, mcp7940, ecp5 4 | 5 | 6 | freq(240*1000*1000) 7 | sd=SDCard(slot=3) # 1-bit mode 8 | mount(sd,"/sd") 9 | ecp5.prog("/sd/rtc/ulx3s_12f_i2c_bridge.bit") 10 | 11 | i2c = I2C(sda=Pin(16), scl=Pin(17), freq=400000) 12 | mcp = mcp7940.MCP7940(i2c) 13 | 14 | mcp.control=0 15 | mcp.trim=-29 16 | #mcp.battery=1 17 | #print("battery %s" % ("enabled" if mcp.battery else "disabled")) 18 | print("trim %+d ppm" % mcp.trim) 19 | print("control 0x%02X" % mcp.control) 20 | print("setting time.localtime() to NTP time using ntptime.settime()") 21 | ntptime.settime() 22 | print("after NTP, time.localtime() reads:") 23 | print(time.localtime()) 24 | print("setting mcp.time=time.localtime()") 25 | mcp.stop() 26 | mcp.time=time.localtime() 27 | print("after setting:") 28 | print("battery %s" % ("enabled" if mcp.battery else "disabled")) 29 | print("mcp.time reads:") 30 | # Read time after setting it, repeat to see time incrementing 31 | for i in range(3): 32 | print(mcp.time) 33 | time.sleep_ms(1000) 34 | -------------------------------------------------------------------------------- /examples/rtc/micropython-mcp7940n/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/rtc/micropython-mcp7940n/proj/README.md: -------------------------------------------------------------------------------- 1 | # i2c bridge for RTC example 2 | 3 | Works for diamond and trellis 4 | -------------------------------------------------------------------------------- /examples/rtc/micropython-mcp7940n/proj/hdl/i2c_bridge.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module i2c_bridge 3 | ( 4 | input wire clk, // any 5 | input wire clk_en, // 1-clk pulse, repeats 1.5-6 MHz 6 | input wire [1:0] i, // inputs 7 | output wire [1:0] t // tristate 0->0 1->Z 8 | ); 9 | reg [1:0] state, next_state; 10 | 11 | always @(posedge clk) 12 | case(state) 13 | 2'd0: begin 14 | if(i[0]) 15 | next_state <= 3; 16 | else 17 | next_state <= 0; 18 | end 19 | 20 | 2'd1: begin 21 | if(i[1]) 22 | next_state <= 3; 23 | else 24 | next_state <= 1; 25 | end 26 | 27 | default: begin 28 | if(i[0]==0 && i[1]==1) 29 | next_state <= 0; 30 | else if(i[1]==0 && i[0]==1) 31 | next_state <= 1; 32 | else 33 | next_state <= 3; 34 | end 35 | endcase 36 | 37 | always @(posedge clk) 38 | if(clk_en) 39 | state <= next_state; 40 | 41 | assign t[1] = state == 2'd0 ? 0:1; 42 | assign t[0] = state == 2'd1 ? 0:1; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /examples/rtc/micropython-mcp7940n/proj/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = i2c_bridge 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* if programming with OpenOCD ******* 13 | # using local latest openocd until in linux distribution 14 | #OPENOCD=openocd_ft232r 15 | # default onboard usb-jtag 16 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 17 | # ulx3s-jtag-passthru 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 19 | # ulx2s 20 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 21 | # external jtag 22 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 23 | 24 | # ******* design files ******* 25 | CONSTRAINTS = ../../../../constraints/ulx3s_v20.lpf 26 | #TOP_MODULE = top_i2c_bridge 27 | TOP_MODULE = top_i2c_bridge_eink 28 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 29 | 30 | VERILOG_FILES = \ 31 | $(TOP_MODULE_FILE) \ 32 | hdl/i2c_bridge.v \ 33 | 34 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 35 | VHDL_FILES = \ 36 | 37 | 38 | SCRIPTS = ../../../../scripts/ 39 | include $(SCRIPTS)/trellis_path.mk 40 | include $(SCRIPTS)/diamond_path.mk 41 | include $(SCRIPTS)/diamond_main.mk 42 | -------------------------------------------------------------------------------- /examples/rtc/micropython-mcp7940n/proj/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = i2c_bridge 3 | 4 | BOARD = ulx3s 5 | # 12 25 45 85 6 | FPGA_SIZE = 12 7 | 8 | # ******* if programming with OpenOCD ******* 9 | # using local latest openocd until in linux distribution 10 | OPENOCD=openocd_ft232r 11 | # default onboard usb-jtag 12 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 13 | # ulx3s-jtag-passthru 14 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 15 | # ulx2s 16 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 17 | # external jtag 18 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 19 | 20 | # ******* design files ******* 21 | CONSTRAINTS = ../../../../constraints/ulx3s_v20.lpf 22 | #TOP_MODULE = top_i2c_bridge 23 | TOP_MODULE = top_i2c_bridge_eink 24 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 25 | 26 | VERILOG_FILES = \ 27 | $(TOP_MODULE_FILE) \ 28 | hdl/i2c_bridge.v \ 29 | 30 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 31 | VHDL_FILES = \ 32 | 33 | #YOSYS_OPTIONS = -abc9 34 | #NEXTPNR_OPTIONS = --timing-allow-fail 35 | 36 | SCRIPTS = ../../../../scripts/ 37 | include $(SCRIPTS)/diamond_path.mk 38 | include $(SCRIPTS)/trellis_path.mk 39 | include $(SCRIPTS)/trellis_main.mk 40 | -------------------------------------------------------------------------------- /examples/sdcard/micropython/README.md: -------------------------------------------------------------------------------- 1 | # micropython example SD card in 4-bit mode 2 | 3 | For ESP32 (MicroPython v1.12 on 2019-12-20) 4 | to be able to use SD card in 4-bit mode, 5 | FPGA should pull up all SD card pins. 6 | Compile and write to config flash: 7 | 8 | cd proj 9 | make flash 10 | 11 | then ESP32 should be able to mount SD card in 4-bit mode (MMC mode) 12 | 13 | from machine import SDCard 14 | from os import mount, listdir 15 | mount(SDCard(),"/sd") # 4-bit mode 16 | #mount(SDCard(slot=3),"/sd") # 1-bit mode 17 | print(listdir("/sd")) 18 | 19 | in esp32 directory there is small test bench for reading speed, 20 | create some 1-10 MB "long_file.bin" on root of SD card, test will 21 | read it: 22 | 23 | 1-bit mode SDCard(slot=3): 24 | 25 | >>> import sdtest 26 | ['long_file.bin'] 27 | 1056 KB in 752 ms => 1404 KB/s file read 28 | 4096 KB in 2746 ms => 1491 KB/s raw sector read 29 | 30 | 4-bit mode SDCard(): 31 | 32 | >>> import sdtest 33 | ['long_file.bin'] 34 | 1056 KB in 492 ms => 2146 KB/s file read 35 | 4096 KB in 1777 ms => 2305 KB/s raw sector read 36 | -------------------------------------------------------------------------------- /examples/sdcard/micropython/esp32/sdtest.py: -------------------------------------------------------------------------------- 1 | from machine import SDCard,freq 2 | from os import mount,umount,listdir 3 | from time import ticks_ms 4 | 5 | def run(): 6 | # some SD cards won't work in 4-bit mode unless freq() is explicitely set 7 | freq(240*1000*1000) # 80/160/240 MHz, faster CPU = faster SD card 8 | #sd=SDCard(slot=3) # 1-bit mode 9 | sd=SDCard() # 4-bit mode 10 | mount(sd,"/sd") 11 | print(listdir("/sd")) 12 | f=open("/sd/long_file.bin","rb") # any 1-10 MB long file 13 | b=bytearray(16*1024) 14 | i=0 15 | t1=ticks_ms() 16 | while f.readinto(b): 17 | i+=1 18 | t2=ticks_ms() 19 | print("%d KB in %d ms => %d KB/s file read" % (i*len(b)//1024,t2-t1,1000*i*len(b)//1024//(t2-t1))) 20 | f.close() 21 | umount("/sd") 22 | i=0 23 | t1=ticks_ms() 24 | while i<256: 25 | sd.readblocks(i,b) 26 | i+=1 27 | t2=ticks_ms() 28 | print("%d KB in %d ms => %d KB/s raw sector read" % (i*len(b)//1024,t2-t1,1000*i*len(b)//1024//(t2-t1))) 29 | sd.deinit() 30 | run() 31 | -------------------------------------------------------------------------------- /examples/sdcard/micropython/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/sdcard/micropython/proj/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = sd_pullup 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | FPGA_PACKAGE = 6bg381c 8 | # config flash: 1:SPI (standard), 4:QSPI (quad) 9 | FLASH_SPI = 4 10 | # chip: is25lp032d is25lp128f s25fl164k 11 | FLASH_CHIP = is25lp128f 12 | 13 | # ******* if programming with OpenOCD ******* 14 | # using local latest openocd until in linux distribution 15 | OPENOCD=openocd_ft232r 16 | # default onboard usb-jtag 17 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 18 | # ulx3s-jtag-passthru 19 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 20 | # ulx2s 21 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 22 | # external jtag 23 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 24 | 25 | # ******* design files ******* 26 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_sd4bit.lpf 27 | TOP_MODULE = top_sd_pullup 28 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 29 | 30 | VERILOG_FILES = \ 31 | $(TOP_MODULE_FILE) \ 32 | 33 | #VHDL_FILES = \ 34 | # ../../../lcd_st7789/hdl/st7789_video_verilog/lcd_video_vhd.vhd \ 35 | # ../../../hex/decoder/hex_decoder.vhd \ 36 | 37 | SCRIPTS = ../../../../scripts/ 38 | include $(SCRIPTS)/trellis_path.mk 39 | include $(SCRIPTS)/diamond_path.mk 40 | include $(SCRIPTS)/diamond_main.mk 41 | -------------------------------------------------------------------------------- /examples/sdcard/micropython/proj/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = sd_pullup 3 | BOARD = ulx3s 4 | # leave empty, um-, um5g- 5 | # FPGA_PREFIX = um5g- 6 | # 12 25 45 85 7 | FPGA_SIZE = 12 8 | 9 | # ******* if programming with OpenOCD ******* 10 | # using local latest openocd until in linux distribution 11 | OPENOCD=openocd_ft232r 12 | # default onboard usb-jtag 13 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 14 | # ulx3s-jtag-passthru 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 16 | # ulx2s 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 18 | # external jtag 19 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 20 | 21 | # ******* design files ******* 22 | CONSTRAINTS = ../../../../constraints/ulx3s_v20_sd4bit.lpf 23 | TOP_MODULE = top_sd_pullup 24 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 25 | 26 | VERILOG_FILES = \ 27 | $(TOP_MODULE_FILE) \ 28 | 29 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 30 | # VHDL_FILES = ../../../lcd_st7789/hdl/st7789_video_verilog/lcd_video_vhd.vhd \ 31 | 32 | YOSYS_OPTIONS = -abc9 33 | NEXTPNR_OPTIONS = --timing-allow-fail 34 | 35 | SCRIPTS = ../../../../scripts/ 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/trellis_path.mk 38 | include $(SCRIPTS)/trellis_main.mk 39 | -------------------------------------------------------------------------------- /examples/sdcard/micropython/proj/top/top_sd_pullup.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | // write this to FPGA config flash 3 | // and ESP32 should be able to mount 4 | // SD card in 4-bit mode 5 | module top_sd_pullup 6 | ( 7 | input wire clk_25mhz, 8 | output wire [7:0] led, 9 | input wire [6:0] btn, 10 | input wire wifi_txd, ftdi_txd, 11 | output wire wifi_rxd, ftdi_rxd, 12 | input wire sd_cmd, sd_clk, 13 | input wire [3:0] sd_d 14 | ); 15 | assign wifi_rxd = ftdi_txd; 16 | assign ftdi_rxd = wifi_txd; 17 | assign led = {sd_clk, sd_cmd, sd_d}; // must be used to enable pullups 18 | endmodule 19 | -------------------------------------------------------------------------------- /examples/sdram/memtest_mister/proj/ffmlfe5_memtest/Makefile: -------------------------------------------------------------------------------- 1 | makefile-720x480.trellis -------------------------------------------------------------------------------- /examples/sdram/memtest_mister/proj/ulx3s_memtest/Makefile: -------------------------------------------------------------------------------- 1 | makefile-720x480.trellis -------------------------------------------------------------------------------- /examples/sdram/sdram_16bit/proj/ulx3s_sdram_hex_v/README.md: -------------------------------------------------------------------------------- 1 | # SDRAM from OBERON with OLED HEX demo 2 | 3 | This SDRAM controller works in Oberon 4 | but I don't understand its signaling 5 | so testbench is not fully useful. 6 | 7 | cleanup: 8 | 9 | make -f makefile.trellis clean 10 | 11 | compile: 12 | 13 | make -f makefile.trellis 14 | 15 | program (upload to SRAM, temporary): 16 | 17 | make -f makefile.trellis program 18 | 19 | or 20 | 21 | make -f makefile.trellis program_ocd 22 | 23 | -------------------------------------------------------------------------------- /examples/sdram/sdram_16bit/proj/ulx3s_sdram_hex_v/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/sdram/sdram_16bit/proj/ulx3s_sdram_hex_v/oled_font.mem: -------------------------------------------------------------------------------- 1 | ../../../../oled/hdl/ssd1331_video_verilog/oled_font.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_16bit/proj/ulx3s_sdram_hex_v/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../../../oled/hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_16bit/proj/ulx3s_sdram_hex_v/oled_init_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../../oled/hdl/ssd1331_video_verilog/oled_init_xflip.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_16bit/proj/ulx3s_sdram_hex_v/oled_init_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../../oled/hdl/ssd1331_video_verilog/oled_init_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_ctrl/proj/ulx3s_sdram_hex_v/README.md: -------------------------------------------------------------------------------- 1 | # SDRAM from fpga4fun with OLED HEX demo 2 | 3 | This is 4 | [SDRAM controller from fpga4fun](https://www.fpga4fun.com/SDRAM2.html). 5 | Seems to me like it doesn't work (read address ignored). 6 | Maybe SDRAM is not initialized...? 7 | 8 | cleanup: 9 | 10 | make -f makefile.trellis clean 11 | 12 | compile: 13 | 14 | make -f makefile.trellis 15 | 16 | program (upload to SRAM, temporary): 17 | 18 | make -f makefile.trellis program 19 | 20 | or 21 | 22 | make -f makefile.trellis program_ocd 23 | 24 | -------------------------------------------------------------------------------- /examples/sdram/sdram_ctrl/proj/ulx3s_sdram_hex_v/makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/sdram/sdram_ctrl/proj/ulx3s_sdram_hex_v/oled_font.mem: -------------------------------------------------------------------------------- 1 | ../../../../oled/hdl/ssd1331_video_verilog/oled_font.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_ctrl/proj/ulx3s_sdram_hex_v/oled_init.mem: -------------------------------------------------------------------------------- 1 | ../../../../oled/hdl/ssd1331_video_verilog/oled_init.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_ctrl/proj/ulx3s_sdram_hex_v/oled_init_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../../oled/hdl/ssd1331_video_verilog/oled_init_xflip.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_ctrl/proj/ulx3s_sdram_hex_v/oled_init_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../../oled/hdl/ssd1331_video_verilog/oled_init_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_fpga/proj/ulx3s_sdram_hex_v/README.md: -------------------------------------------------------------------------------- 1 | # SDRAM from nullobject 2 | 3 | This is 4 | [SDRAM controller in VHDL from nullobject](https://github.com/nullobject/sdram-fpga). 5 | It has burst support, configurable application data bus with and 6 | configurable timings. 7 | 8 | cleanup: 9 | 10 | make clean 11 | 12 | compile: 13 | 14 | make 15 | 16 | program (upload to SRAM, temporary): 17 | 18 | make program 19 | 20 | or 21 | 22 | make program_ocd 23 | 24 | # OLED should display: 25 | 26 | left 32-bit should quicky alternate word to be written 27 | "01234567" and "600DCAFE". Hold BTN1 to freeze display 28 | to be able to read. 29 | 30 | right 32-bit should show word that has been read from RAM: 31 | it should be "01234567". Hold BTN2 and it should show "600DCAFE". 32 | -------------------------------------------------------------------------------- /examples/sdram/sdram_fpga/proj/ulx3s_sdram_hex_v/makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/sdram/sdram_mistery/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/sdram/sdram_mistery/proj/README.md: -------------------------------------------------------------------------------- 1 | # SDRAM test 2 | 3 | writing and reading N bytes to/from SPI bus works. 4 | 5 | test it with spiram.py 6 | 7 | >>> import spiram 8 | >>> spiram.poke(0,"abcdABCD12345678") # write 16 bytes from address 0 9 | >>> spiram.peek(0,16) # read 16 bytes from address 0 should be same as above 10 | bytearray(b'abcdABCD12345678') 11 | -------------------------------------------------------------------------------- /examples/sdram/sdram_mistery/proj/esp32: -------------------------------------------------------------------------------- 1 | ../../sdram_pnru/proj/esp32 -------------------------------------------------------------------------------- /examples/sdram/sdram_mistery/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_mistery/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru/proj/README.md: -------------------------------------------------------------------------------- 1 | # SDRAM test 2 | 3 | writing and reading N bytes to/from SPI bus works. 4 | 5 | test it with spiram.py 6 | 7 | >>> import spiram 8 | >>> spiram.poke(0,"abcdABCD12345678") # write 16 bytes from address 0 9 | >>> spiram.peek(0,16) # read 16 bytes from address 0 should be same as above 10 | bytearray(b'abcdABCD12345678') 11 | -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k/proj/README.md: -------------------------------------------------------------------------------- 1 | # SDRAM test 2 | 3 | writing and reading N bytes to/from SPI bus works. 4 | 5 | test it with spiram.py 6 | 7 | >>> import spiram 8 | >>> spiram.poke(0,"abcdABCD12345678") # write 16 bytes from address 0 9 | >>> spiram.peek(0,16) # read 16 bytes from address 0 should be same as above 10 | bytearray(b'abcdABCD12345678') 11 | -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k/proj/esp32: -------------------------------------------------------------------------------- 1 | ../../sdram_pnru/proj/esp32 -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k_180deg/README.md: -------------------------------------------------------------------------------- 1 | This controller should not need to fiddle with SDRAM chip phase shift. 2 | 3 | SDRAM chip phase should always be set to 180 deg 4 | SDRAM driver phase should always be set to 0 deg 5 | -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k_180deg/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k_180deg/proj/README.md: -------------------------------------------------------------------------------- 1 | # SDRAM test 2 | 3 | writing and reading N bytes to/from SPI bus works. 4 | 5 | test it with spiram.py 6 | 7 | >>> import spiram 8 | >>> spiram.poke(0,"abcdABCD12345678") # write 16 bytes from address 0 9 | >>> spiram.peek(0,16) # read 16 bytes from address 0 should be same as above 10 | bytearray(b'abcdABCD12345678') 11 | -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k_180deg/proj/esp32: -------------------------------------------------------------------------------- 1 | ../../sdram_pnru/proj/esp32 -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k_180deg/proj/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/sdram/sdram_pnru_68k_180deg/proj/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/serdes/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/serdes/README.md: -------------------------------------------------------------------------------- 1 | # serdes attempt 2 | 3 | v3.1.4 board only (no serdes on v3.0.x) 4 | 5 | It compiles and applies counter bit output to RX input of serdes. 6 | 7 | With enabled Low Data Rate (LDR) in serdes, signal appear on 8 | output line of serdes module and is used to drive another counter 9 | that blinks LED D0 10 | -------------------------------------------------------------------------------- /examples/serdes/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = serdes 3 | BOARD = ulx3s 4 | # um-25 um-45 um-85 um5g-85 5 | FPGA_SIZE = um-25 6 | # "um-" prefix for serdes: 7 | # FPGA_PREFIX = um- 8 | 9 | # ******* if programming with OpenOCD ******* 10 | # using local latest openocd until in linux distribution 11 | OPENOCD=openocd_ft232r 12 | # default onboard usb-jtag 13 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 14 | # ulx3s-jtag-passthru 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 16 | # ulx2s 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 18 | # external jtag 19 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 20 | 21 | # ******* design files ******* 22 | CONSTRAINTS = ../../constraints/ulx3s_v316.lpf 23 | TOP_MODULE = top_serdes 24 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 25 | 26 | # *.vhd those files will be converted to *.v files with vhdl2vl (warning overwriting/deleting) 27 | VERILOG_FILES = \ 28 | $(TOP_MODULE_FILE) \ 29 | ../ecp5pll/hdl/sv/ecp5pll.sv \ 30 | 31 | # synthesis options 32 | NEXTPNR_OPTIONS = --timing-allow-fail 33 | 34 | SCRIPTS = ../../scripts 35 | include $(SCRIPTS)/diamond_path.mk 36 | include $(SCRIPTS)/trellis_path.mk 37 | include $(SCRIPTS)/trellis_main.mk 38 | -------------------------------------------------------------------------------- /examples/serdes_dvi/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/serdes_dvi/README.md: -------------------------------------------------------------------------------- 1 | # serdes attempt 2 | 3 | v3.1.4 board required (no serdes on v3.0.x boards) 4 | 5 | Generate DVI signal and try to capture stream with serdes RX. 6 | Currently no data appears at RX. 7 | 8 | -------------------------------------------------------------------------------- /examples/spi_display/hdl/spi_display_verilog/st7789_init.mem: -------------------------------------------------------------------------------- 1 | // NOTE this file is obsolete, use "linit" files 2 | // after reset, delay 2^13 us = 8ms before sending commands 3 | 80 4 | 0D 5 | // SWRESET, delay 2^17 us = 131us 6 | 01 7 | 80 8 | 11 9 | // SLPOUT, delay 2^14 us = 16ms 10 | 11 11 | 80 12 | 0E 13 | // COLMOD, 16-bit color, delay 2^14 us = 16ms 14 | 3A 15 | 81 16 | 55 17 | 0E 18 | // MADCTL 19 | 36 20 | 01 21 | 00 22 | // CASET X 23 | 2A 24 | 04 25 | // X start MSB,LSB 26 | 00 27 | 00 28 | // X end MSB,LSB 29 | 00 30 | EF 31 | // RASET Y 32 | 2B 33 | 04 34 | // Y start MSB,LSB 35 | 00 36 | 00 37 | // Y end MSB,LSB 38 | 00 39 | EF 40 | // INVON, delay 2^14 us = 16ms 41 | 21 42 | 80 43 | 0E 44 | // NORON, delay 2^14 us = 16ms 45 | 13 46 | 80 47 | 0E 48 | // DISPON, delay 2^14 us = 16ms 49 | 29 50 | 80 51 | 0E 52 | // RAMWR 2C 00 53 | 2C 54 | 00 55 | -------------------------------------------------------------------------------- /examples/spi_display/hdl/spi_display_verilog/st7789_linit.mem: -------------------------------------------------------------------------------- 1 | // ST7789 init lcd_video (display mounted pins down) 2 | // image normal (no flip) 3 | // 2+3+4+3+2*6+3*3+2 = 35 bytes 4 | // 5 | // Some displays won't initialize for the first time after power up. 6 | // workaround: 0.5s after 1st reset pulse, 2nd reset pulse. 7 | // 8 | // first action is to wait (no command) 9 | // after reset, delay 2^17 us = 131ms before sending commands 10 | 80 11 11 | // send command byte, optional data and optional wait 12 | // SLPOUT, 0-param, delay 2^17 us = 131ms 13 | 11 80 11 14 | // COLMOD, 16-bit color, 1-param, delay 2^14 us = 16ms 15 | 3A 81 55 0E 16 | // MADCTL, 1-param 17 | 36 01 C0 18 | // CASET X, 4-param, start MSB,LSB end MSB,LSB 19 | 2A 04 00 00 00 EF 20 | // RASET Y, 4-param, start MSB,LSB end MSB,LSB 21 | 2B 04 00 50 01 3F 22 | // INVON, 0-param, delay 2^14 us = 16ms 23 | 21 80 0E 24 | // NORON, 0-param, delay 2^14 us = 16ms 25 | 13 80 0E 26 | // DISPON, 0-param, delay 2^14 us = 16ms 27 | 29 80 0E 28 | // RAMWR, 0-param 29 | 2C 00 30 | -------------------------------------------------------------------------------- /examples/spi_display/hdl/spi_display_verilog/st7789_linit_long.mem: -------------------------------------------------------------------------------- 1 | // ST7789 init lcd_video (display mounted pins down) 2 | // image normal (no flip) 3 | // 2+4*3+4+8+3*3+4+3*3+4+2*6+3*3+2 = 75 bytes 4 | // first action is wait, no command 5 | // after reset, delay 2^1 us = 2us before sending commands 6 | 80 11 7 | // send command byte, optional data and optional wait 8 | // SWRESET, 0-param, delay 2^17 us = 131us 9 | 01 80 11 10 | // SLPOUT, 0-param, delay 2^14 us = 16ms 11 | 11 80 0E 12 | // DISPOFF, 0-param, delay 2^14 us = 16ms 13 | 28 80 0E 14 | // MADCTL, 1-param, RGB format 15 | 36 01 C0 16 | // COLMOD, 16-bit color, 1-param, delay 2^14 us = 16ms 17 | 3A 81 55 0E 18 | // PORCH SETTING, (frame rate) 5-param, delay 2^14 us = 16ms 19 | B2 85 0C 0C 00 33 33 0E 20 | // GATE CONTROL, 1-param 21 | B7 01 35 22 | // VCOM SETTING 23 | BB 01 2B 24 | C0 01 2C 25 | C2 02 01 FF 26 | C3 01 11 27 | C4 01 20 28 | C6 01 0F 29 | D0 02 A4 A1 30 | // CASET X, 4-param, start MSB,LSB end MSB,LSB 31 | 2A 04 00 00 00 EF 32 | // RASET Y, 4-param, start MSB,LSB end MSB,LSB 33 | 2B 04 00 50 01 3F 34 | // INVON, 0-param, delay 2^14 us = 16ms 35 | 21 80 0E 36 | // NORON, 0-param, delay 2^14 us = 16ms 37 | 13 80 0E 38 | // DISPON, 0-param, delay 2^14 us = 16ms 39 | 29 80 0E 40 | // RAMWR, 0-param 41 | 2C 00 42 | -------------------------------------------------------------------------------- /examples/spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | // ST7789 init lcd_video (display mounted pins down) 2 | // image x-flip 3 | // 2+3+4+3+2*6+3*3+2 = 35 bytes 4 | // 5 | // Some displays won't initialize for the first time after power up. 6 | // workaround: 0.5s after 1st reset pulse, 2nd reset pulse. 7 | // 8 | // first action is to wait (no command) 9 | // after reset, delay 2^17 us = 131ms before sending commands 10 | 80 11 11 | // send command byte, optional data and optional wait 12 | // SLPOUT, 0-param, delay 2^17 us = 131ms 13 | 11 80 11 14 | // COLMOD, 16-bit color, 1-param, delay 2^14 us = 16ms 15 | 3A 81 55 0E 16 | // MADCTL, 1-param 17 | 36 01 80 18 | // CASET X, 4-param, start MSB,LSB end MSB,LSB 19 | 2A 04 00 00 00 EF 20 | // RASET Y, 4-param, start MSB,LSB end MSB,LSB 21 | 2B 04 00 50 01 3F 22 | // INVON, 0-param, delay 2^14 us = 16ms 23 | 21 80 0E 24 | // NORON, 0-param, delay 2^14 us = 16ms 25 | 13 80 0E 26 | // DISPON, 0-param, delay 2^14 us = 16ms 27 | 29 80 0E 28 | // RAMWR, 0-param 29 | 2C 00 30 | -------------------------------------------------------------------------------- /examples/spi_display/hdl/spi_display_verilog/st7789_linit_xyflip.mem: -------------------------------------------------------------------------------- 1 | // ST7789 init lcd_video (display mounted pins down) 2 | // image xy-flip 3 | // 2+3+4+3+2*6+3*3+2 = 35 bytes 4 | // 5 | // Some displays won't initialize for the first time after power up. 6 | // workaround: 0.5s after 1st reset pulse, 2nd reset pulse. 7 | // 8 | // first action is to wait (no command) 9 | // after reset, delay 2^17 us = 131ms before sending commands 10 | 80 11 11 | // send command byte, optional data and optional wait 12 | // SLPOUT, 0-param, delay 2^17 us = 131ms 13 | 11 80 11 14 | // COLMOD, 16-bit color, 1-param, delay 2^14 us = 16ms 15 | 3A 81 55 0E 16 | // MADCTL, 1-param 17 | 36 01 00 18 | // CASET X, 4-param, start MSB,LSB end MSB,LSB 19 | 2A 04 00 00 00 EF 20 | // RASET Y, 4-param, start MSB,LSB end MSB,LSB 21 | 2B 04 00 00 00 EF 22 | // INVON, 0-param, delay 2^14 us = 16ms 23 | 21 80 0E 24 | // NORON, 0-param, delay 2^14 us = 16ms 25 | 13 80 0E 26 | // DISPON, 0-param, delay 2^14 us = 16ms 27 | 29 80 0E 28 | // RAMWR, 0-param 29 | 2C 00 30 | -------------------------------------------------------------------------------- /examples/spi_display/hdl/spi_display_verilog/st7789_linit_yflip.mem: -------------------------------------------------------------------------------- 1 | // ST7789 init lcd_video (display mounted pins down) 2 | // image y-flip 3 | // 2+3+4+3+2*6+3*3+2 = 35 bytes 4 | // 5 | // Some displays won't initialize for the first time after power up. 6 | // workaround: 0.5s after 1st reset pulse, 2nd reset pulse. 7 | // 8 | // first action is to wait (no command) 9 | // after reset, delay 2^17 us = 131ms before sending commands 10 | 80 11 11 | // send command byte, optional data and optional wait 12 | // SLPOUT, 0-param, delay 2^17 us = 131ms 13 | 11 80 11 14 | // COLMOD, 16-bit color, 1-param, delay 2^14 us = 16ms 15 | 3A 81 55 0E 16 | // MADCTL, 1-param 17 | 36 01 40 18 | // CASET X, 4-param, start MSB,LSB end MSB,LSB 19 | 2A 04 00 00 00 EF 20 | // RASET Y, 4-param, start MSB,LSB end MSB,LSB 21 | 2B 04 00 00 00 EF 22 | // INVON, 0-param, delay 2^14 us = 16ms 23 | 21 80 0E 24 | // NORON, 0-param, delay 2^14 us = 16ms 25 | 13 80 0E 26 | // DISPON, 0-param, delay 2^14 us = 16ms 27 | 29 80 0E 28 | // RAMWR, 0-param 29 | 2C 00 30 | -------------------------------------------------------------------------------- /examples/spi_display/hdl/spi_display_verilog/top/top_checkered.v: -------------------------------------------------------------------------------- 1 | module top_checkered ( 2 | input wire clk_25mhz, 3 | input wire [6:0] btn, 4 | output wire oled_csn, 5 | output wire oled_clk, 6 | output wire oled_mosi, 7 | output wire oled_dc, 8 | output wire oled_resn 9 | ); 10 | wire [7:0] x; 11 | wire [7:0] y; 12 | // checkered red green blue red green blue 13 | wire [15:0] color = x[4] ^ y[4] ? {5'd0, x[7:3], 6'd0} : {y[7:3], 6'd0, 5'd0}; 14 | 15 | lcd_video #( 16 | .c_clk_mhz(25), 17 | .c_init_file("st7789_linit.mem"), 18 | .c_init_size(35), 19 | .c_color_bits(16) 20 | ) lcd_video_inst ( 21 | .clk(clk_25mhz), 22 | .reset(~btn[0]), 23 | .x(x), 24 | .y(y), 25 | .color(color), 26 | .spi_clk(oled_clk), 27 | .spi_mosi(oled_mosi), 28 | .spi_dc(oled_dc), 29 | .spi_resn(oled_resn) 30 | ); 31 | assign oled_csn = 1; // oled_csn is connected to BLK (backlight enable pin) 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /examples/spi_display/hdl/spi_display_vhdl/spi_display_init_pack.vhd: -------------------------------------------------------------------------------- 1 | -- (c) EMARD 2 | -- License=BSD 3 | 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | 7 | package spi_display_init_pack is 8 | type T_spi_display_init_seq is array (natural range <>) of std_logic_vector(7 downto 0); 9 | end; 10 | -------------------------------------------------------------------------------- /examples/spi_display/proj/ssd1331_vga_vhdl/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_osd_verilog/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_osd_verilog/README.md: -------------------------------------------------------------------------------- 1 | # SPI LCD VGA core in VHDL 2 | 3 | This VHDL core takes VGA style input 4 | (pixel clock, RGB pixel data, vsync, hsync, blank) 5 | and display it as video on LCD screen. 6 | 7 | overscan - runs both VGA and LCD at the same clock domain 8 | 9 | VGA generates faster frame rate than SPI can send. 10 | LCD SPI sends pixel by its speed and waits until both 11 | Y counters from input and output match to update next scanline. 12 | LCD timing is achieved with standard format of VGA timings 13 | by setting large horizontal porch timings (around 1900). 14 | 15 | for fast frame updates, VGA generator needs to be slowed down by clk_pixel_ena 16 | otherwise it can work also but screen update will be unacceptably slow (0.5Hz frame rate) 17 | 18 | # TODO 19 | 20 | diamond reports multiple drivers 21 | -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_osd_verilog/osd.txt: -------------------------------------------------------------------------------- 1 | ****************************** 2 | * OSD (on-screen display) * 3 | * video overlay soft core can* 4 | * display ASCII character map* 5 | * over the video display by * 6 | * modifying VGA pixel stream.* 7 | * In rectangular screen area,* 8 | * video content is replaced * 9 | * with pixels coming from * 10 | * ASCII font, forming a * 11 | * "window". This can be * 12 | * combined with a SPI slave * 13 | * receiver and used to * 14 | * provide screen display. * 15 | ****************************** 16 | -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_osd_verilog/st7789_linit.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/spi_display_verilog/st7789_linit.mem -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_vga_verilog/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_vga_verilog/README.md: -------------------------------------------------------------------------------- 1 | # SPI LCD VGA core in VHDL 2 | 3 | This VHDL core takes VGA style input 4 | (pixel clock, RGB pixel data, vsync, hsync, blank) 5 | and display it as video on LCD screen. 6 | 7 | overscan - runs both VGA and LCD at the same clock domain 8 | 9 | VGA generates faster frame rate than SPI can send. 10 | LCD SPI sends pixel by its speed and waits until both 11 | Y counters from input and output match to update next scanline. 12 | LCD timing is achieved with standard format of VGA timings 13 | by setting large horizontal porch timings (around 1900). 14 | 15 | for fast frame updates, VGA generator needs to be slowed down by clk_pixel_ena 16 | otherwise it can work also but screen update will be unacceptably slow (0.5Hz frame rate) 17 | 18 | # TODO 19 | 20 | diamond reports multiple drivers 21 | -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_vga_verilog/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = st7789_vga 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | FPGA_PACKAGE = 6bg381c 8 | # config flash: 1:SPI (standard), 4:QSPI (quad) 9 | FLASH_SPI = 4 10 | # chip: is25lp032d is25lp128f s25fl164k 11 | FLASH_CHIP = is25lp128f 12 | 13 | # ******* if programming with OpenOCD ******* 14 | # using local latest openocd until in linux distribution 15 | OPENOCD=openocd_ft232r 16 | # default onboard usb-jtag 17 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 18 | # ulx3s-jtag-passthru 19 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 20 | # ulx2s 21 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 22 | # external jtag 23 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 24 | 25 | # ******* design files ******* 26 | CONSTRAINTS = ../../../../constraints/ulx3s_v20.lpf 27 | TOP_MODULE = top_st7789_vga 28 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 29 | 30 | VERILOG_FILES = \ 31 | $(TOP_MODULE_FILE) \ 32 | ../../../ecp5pll/hdl/sv/ecp5pll.sv \ 33 | ../../hdl/spi_display_verilog/lcd_video.v 34 | 35 | VHDL_FILES = \ 36 | ../../../dvi/hdl/vga.vhd \ 37 | 38 | SCRIPTS = ../../../../scripts 39 | include $(SCRIPTS)/trellis_path.mk 40 | include $(SCRIPTS)/diamond_path.mk 41 | include $(SCRIPTS)/diamond_main.mk 42 | -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_vga_verilog/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = st7789_vga 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = ../../../../constraints/ulx3s_v20.lpf 21 | TOP_MODULE = top_st7789_vga 22 | TOP_MODULE_FILE = top/$(TOP_MODULE).v 23 | 24 | VERILOG_FILES = \ 25 | $(TOP_MODULE_FILE) \ 26 | ../../../ecp5pll/hdl/sv/ecp5pll.sv \ 27 | ../../hdl/spi_display_verilog/lcd_video.v 28 | 29 | VHDL_FILES = \ 30 | ../../../dvi/hdl/vga.vhd \ 31 | 32 | YOSYS_OPTIONS = -abc9 33 | NEXTPNR_OPTIONS = --timing-allow-fail 34 | 35 | SCRIPTS = ../../../../scripts/ 36 | include $(SCRIPTS)/diamond_path.mk 37 | include $(SCRIPTS)/trellis_path.mk 38 | include $(SCRIPTS)/trellis_main.mk 39 | -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_vga_verilog/st7789_linit.mem: -------------------------------------------------------------------------------- 1 | ../../hdl/spi_display_verilog/st7789_linit.mem -------------------------------------------------------------------------------- /examples/spi_display/proj/st7789_vga_vhdl/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/spi_ram/proj/ulx3s_spi_ram_oled/README.md: -------------------------------------------------------------------------------- 1 | # SPI RAM test with OLED 2 | 3 | Attempt to emulate SPI RAM chip and show debug 4 | data on OLED. -------------------------------------------------------------------------------- /examples/spi_slave/hdl/todo.txt: -------------------------------------------------------------------------------- 1 | [ ] configurable address (16-24-32) and data (8-16-32) 2 | [ ] first byte for chip select as parameter 3 | [ ] output '1' to MISO until first byte matches 4 | [ ] don't have 3-state driver but separate MISO and OE 5 | [ ] input default byte(s) when reading 2nd and 3rd byte 6 | -------------------------------------------------------------------------------- /examples/spi_slave/proj/ulx3s_spirw_hex_v/Makefile: -------------------------------------------------------------------------------- 1 | makefile.trellis -------------------------------------------------------------------------------- /examples/spi_slave/proj/ulx3s_spirw_hex_v/README.md: -------------------------------------------------------------------------------- 1 | # OLED SPI sniffer HEX display 2 | 3 | cleanup: 4 | 5 | make -f makefile.trellis clean 6 | 7 | compile: 8 | 9 | make -f makefile.trellis 10 | 11 | program (upload to SRAM, temporary): 12 | 13 | make -f makefile.trellis program 14 | 15 | or 16 | 17 | make -f makefile.trellis program_ocd 18 | 19 | usage: 20 | 21 | screen /dev/ttyUSB0 115200 22 | 23 | type some text... 24 | 25 | to exit: 26 | 27 | ctrl-a \ 28 | 29 | or 30 | 31 | ctrl-a altgr-q 32 | 33 | # trellis-diamond difference 34 | 35 | For bitstream compiled with diamond, 36 | unwanted dot will appear at bottom of 37 | each character. 38 | -------------------------------------------------------------------------------- /examples/usb/ch376/proj/Makefile: -------------------------------------------------------------------------------- 1 | makefile.diamond -------------------------------------------------------------------------------- /examples/usb/ch376/python/ch376.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import serial 3 | 4 | def test(): 5 | s = serial.Serial("/dev/ttyUSB0", 9600, timeout=1, xonxoff=0, rtscts=0) 6 | 7 | msg = ["FAIL", "OK"] 8 | 9 | for value in bytearray([0x5A, 0xF0, 0xC3]): 10 | s.write([0x57, 0xAB, 0x06, value]) 11 | r = s.read(1) 12 | if len(r): 13 | if (value ^ 0xFF) == r[0]: 14 | msg = "OK" 15 | else: 16 | msg = "FAIL" 17 | print("(0x%02X expected) reply: 0x%02X %s" % (value ^ 0xFF, r[0], msg)) 18 | else: 19 | print("no response") 20 | 21 | test() 22 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbethernet/files.mk: -------------------------------------------------------------------------------- 1 | VHDL_FILES = $(TOP_MODULE_FILE) \ 2 | ../../../../lattice/ulx3s/clocks/clk_25_125_25_48_89.vhd \ 3 | ../../../../usbcdc/eth/usbeth_icmp_echo.vhd \ 4 | ../../../../usbcdc/usb_cdc_descriptor_pack.vhd \ 5 | ../../../../usbcdc/usb_serial.vhd \ 6 | ../../../../usbcdc/usb_transact.vhd \ 7 | ../../../../usbcdc/usb_packet.vhd \ 8 | ../../../../usbcdc/usb_init.vhd \ 9 | ../../../../usbcdc/usb_control.vhd \ 10 | ../../../../usb11_phy_vhdl/usb_phy.vhd \ 11 | ../../../../usb11_phy_vhdl/usb_rx_phy.vhd \ 12 | ../../../../usb11_phy_vhdl/usb_tx_phy.vhd \ 13 | 14 | # ../../../../../oled/hdl/ssd1331_hex_vhdl/oled_hex_decoder.vhd \ 15 | # ../../../../../oled/hdl/ssd1331_hex_vhdl/oled_font_pack.vhd \ 16 | # ../../../../../oled/hdl/ssd1331_hex_vhdl/oled_init_pack.vhd \ 17 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbethernet/makefile: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = ulx3s_usbeth 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* design files ******* 13 | CONSTRAINTS = ../../constraints/ulx3s_v20_dif.lpf 14 | 15 | # usually all toplevels have the same top module name 16 | TOP_MODULE = ulx3s_usbeth 17 | 18 | # various toplevels for building different f32c soc's 19 | TOP_MODULE_FILE = ../../../../lattice/ulx3s/top/ulx3s_usbeth.vhd 20 | 21 | include files.mk 22 | 23 | #BITSTREAM = \ 24 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit \ 25 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme \ 26 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf \ 27 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme 28 | 29 | SCRIPTS = ../../../../../../scripts 30 | include $(SCRIPTS)/trellis_path.mk 31 | include $(SCRIPTS)/diamond_path.mk 32 | include $(SCRIPTS)/diamond_main.mk 33 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/Makefile: -------------------------------------------------------------------------------- 1 | makefilev.trellis -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/README.md: -------------------------------------------------------------------------------- 1 | # USB HID Host Core 2 | 3 | Demo for USB HID devices. Plug mouse, keyboard or joystick, 4 | to US2 over OTG adapter, or to US3, US3 (external PMOD), 5 | press something and watch as OLED HEX display is changing. 6 | 7 | vhdl version works for diamond but not for trellis, 8 | compilation stops with this error: 9 | 10 | ERROR: wire not found for $posedge 11 | 12 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/filesv.mk: -------------------------------------------------------------------------------- 1 | VERILOG_FILES = \ 2 | $(TOP_MODULE_FILE) \ 3 | ../../../../../ecp5pll/hdl/sv/ecp5pll.sv \ 4 | ../../../../../hex/decoder/hex_decoder_v.v \ 5 | ../../../../../spi_display/hdl/spi_display_verilog/lcd_video.v \ 6 | ../../../../usbhost/usbh_sie.v \ 7 | ../../../../usbhost/usbh_crc5.v \ 8 | ../../../../usbhost/usbh_crc16.v \ 9 | ../../../../usbhost/usbh_host_hid.v \ 10 | 11 | # convertible with vhd2vl 12 | VHDL_FILES = \ 13 | ../../../../usb11_phy_vhdl/usb_phy.vhd \ 14 | ../../../../usb11_phy_vhdl/usb_rx_phy.vhd \ 15 | ../../../../usb11_phy_vhdl/usb_tx_phy.vhd \ 16 | ../../../../../dvi/hdl/vga.vhd \ 17 | ../../../../../dvi/hdl/vga2dvid.vhd \ 18 | ../../../../../dvi/hdl/tmds_encoder.vhd \ 19 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/hex_font.mem: -------------------------------------------------------------------------------- 1 | ../../../../../hex/decoder/hex_font.mem -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/makefile.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = usbhost_test 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* design files ******* 13 | CONSTRAINTS = constraints/ulx3s_v20.lpf 14 | 15 | # usually all toplevels have the same top module name 16 | TOP_MODULE = ulx3s_usbhost_test 17 | 18 | # various toplevels for building different f32c soc's 19 | TOP_MODULE_FILE = top/vhdl/$(TOP_MODULE).vhd 20 | 21 | include files.mk 22 | 23 | #BITSTREAM = \ 24 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit \ 25 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme \ 26 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf \ 27 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme 28 | 29 | SCRIPTS = ../../../../../../scripts 30 | include $(SCRIPTS)/trellis_path.mk 31 | include $(SCRIPTS)/diamond_path.mk 32 | include $(SCRIPTS)/diamond_main.mk 33 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/makefile.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = usbhost_test 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | #OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = constraints/ulx3s_v20.lpf 21 | TOP_MODULE = ulx3s_usbhost_test 22 | TOP_MODULE_FILE = top/vhdl/$(TOP_MODULE).vhd 23 | 24 | include files.mk 25 | 26 | #YOSYS_OPTIONS = -abc9 27 | NEXTPNR_OPTIONS = --router router2 28 | #NEXTPNR_OPTIONS = --timing-allow-fail 29 | 30 | SCRIPTS = ../../../../../../scripts 31 | include $(SCRIPTS)/diamond_path.mk 32 | include $(SCRIPTS)/trellis_path.mk 33 | include $(SCRIPTS)/trellis_main_ghdl.mk 34 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/makefilev.diamond: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = usbhost_test 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* design files ******* 13 | CONSTRAINTS = constraints/ulx3s_v20.lpf 14 | 15 | # usually all toplevels have the same top module name 16 | TOP_MODULE = ulx3s_usbhost_test 17 | 18 | # various toplevels for building different soc's 19 | TOP_MODULE_FILE = top/verilog/ulx3s_usbhost_test.v 20 | 21 | include filesv.mk 22 | 23 | #BITSTREAM = \ 24 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit \ 25 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme \ 26 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf \ 27 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme 28 | 29 | SCRIPTS = ../../../../../../scripts 30 | include $(SCRIPTS)/trellis_path.mk 31 | include $(SCRIPTS)/diamond_path.mk 32 | include $(SCRIPTS)/diamond_main.mk 33 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/makefilev.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = usbhost_test 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | #OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = constraints/ulx3s_v20.lpf 21 | TOP_MODULE = ulx3s_usbhost_test 22 | TOP_MODULE_FILE = top/verilog/$(TOP_MODULE).v 23 | 24 | include filesv.mk 25 | 26 | YOSYS_OPTIONS = -abc9 27 | NEXTPNR_OPTIONS = --timing-allow-fail 28 | 29 | SCRIPTS = ../../../../../../scripts 30 | include $(SCRIPTS)/diamond_path.mk 31 | include $(SCRIPTS)/trellis_path.mk 32 | include $(SCRIPTS)/trellis_main.mk 33 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/ssd1331_linit_xflip_16bit.mem: -------------------------------------------------------------------------------- 1 | ../../../../../spi_display/hdl/spi_display_verilog/ssd1331_linit_xflip_16bit.mem -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/st7789_linit_xflip.mem: -------------------------------------------------------------------------------- 1 | ../../../../../spi_display/hdl/spi_display_verilog/st7789_linit_xflip.mem -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbhid_host/usbh_setup_rom.mem: -------------------------------------------------------------------------------- 1 | ../../../../usbhost/usbh_setup_rom.mem -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbkbd/Makefile: -------------------------------------------------------------------------------- 1 | makefilev.trellis -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbkbd/filesv.mk: -------------------------------------------------------------------------------- 1 | VERILOG_FILES = $(TOP_MODULE_FILE) \ 2 | ../../../../../ecp5pll/hdl/sv/ecp5pll.sv \ 3 | ../../../../../hex/decoder/hex_decoder_v.v \ 4 | ../../../../../spi_display/hdl/spi_display_verilog/lcd_video.v \ 5 | ../../../../usbhost/usbh_sie.v \ 6 | ../../../../usbhost/usbh_crc5.v \ 7 | ../../../../usbhost/usbh_crc16.v \ 8 | ../../../../usbhost/usbh_host_hid.v \ 9 | 10 | # convertible with vhd2vl 11 | VHDL_FILES = \ 12 | ../../../../usb11_phy_vhdl/usb_phy.vhd \ 13 | ../../../../usb11_phy_vhdl/usb_rx_phy.vhd \ 14 | ../../../../usb11_phy_vhdl/usb_tx_phy.vhd \ 15 | ../../../../../dvi/hdl/vga.vhd \ 16 | ../../../../../dvi/hdl/vga2dvid.vhd \ 17 | ../../../../../dvi/hdl/tmds_encoder.vhd \ 18 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbkbd/makefilev.trellis: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = usbhost_test 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | 7 | # ******* if programming with OpenOCD ******* 8 | # using local latest openocd until in linux distribution 9 | OPENOCD=openocd_ft232r 10 | # default onboard usb-jtag 11 | OPENOCD_INTERFACE=$(SCRIPTS)/ft231x.ocd 12 | # ulx3s-jtag-passthru 13 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft231x2.ocd 14 | # ulx2s 15 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft232r.ocd 16 | # external jtag 17 | #OPENOCD_INTERFACE=$(SCRIPTS)/ft2232.ocd 18 | 19 | # ******* design files ******* 20 | CONSTRAINTS = constraints/ulx3s_v20.lpf 21 | TOP_MODULE = ulx3s_usbkbd_test 22 | TOP_MODULE_FILE = top/verilog/$(TOP_MODULE).v 23 | 24 | include filesv.mk 25 | 26 | YOSYS_OPTIONS = -abc9 27 | NEXTPNR_OPTIONS = --timing-allow-fail 28 | 29 | SCRIPTS = ../../../../../../scripts 30 | include $(SCRIPTS)/diamond_path.mk 31 | include $(SCRIPTS)/trellis_path.mk 32 | include $(SCRIPTS)/trellis_main.mk 33 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbserial_vhdl/files.mk: -------------------------------------------------------------------------------- 1 | VHDL_FILES = $(TOP_MODULE_FILE) \ 2 | ../../../../lattice/ulx3s/clocks/clk_25M_100M_7M5_12M_60M.vhd \ 3 | ../../../../lattice/ulx3s/clocks/clk_25_125_25_48_89.vhd \ 4 | ../../../../lattice/ulx3s/clocks/clk_25m_200m.vhd \ 5 | ../../../../lattice/ulx3s/clocks/clk_200m_60m_48m_12m_7m5.vhd \ 6 | ../../../../usbcdc/usbtest.vhd \ 7 | ../../../../usbcdc/usb_cdc_descriptor_pack.vhd \ 8 | ../../../../usbcdc/usb_serial.vhd \ 9 | ../../../../usbcdc/usb_transact.vhd \ 10 | ../../../../usbcdc/usb_packet.vhd \ 11 | ../../../../usbcdc/usb_init.vhd \ 12 | ../../../../usbcdc/usb_control.vhd \ 13 | ../../../../usb11_phy_vhdl/usb_phy.vhd \ 14 | ../../../../usb11_phy_vhdl/usb_rx_phy.vhd \ 15 | ../../../../usb11_phy_vhdl/usb_tx_phy.vhd \ 16 | ../../../../../oled/hdl/ssd1331_hex_vhdl/oled_hex_decoder.vhd \ 17 | ../../../../../oled/hdl/ssd1331_hex_vhdl/oled_font_pack.vhd \ 18 | ../../../../../oled/hdl/ssd1331_hex_vhdl/oled_init_pack.vhd \ 19 | 20 | VERILOG_FILES = \ 21 | ../../../../ulpi_wrapper/ulpi_wrapper.v \ 22 | 23 | -------------------------------------------------------------------------------- /examples/usb/proj/lattice/ulx3s/usbserial_vhdl/makefile: -------------------------------------------------------------------------------- 1 | # ******* project, board and chip name ******* 2 | PROJECT = ulx3s_usbtest 3 | BOARD = ulx3s 4 | # 12 25 45 85 5 | FPGA_SIZE = 12 6 | FPGA_PACKAGE = 6bg381c 7 | # config flash: 1:SPI (standard), 4:QSPI (quad) 8 | FLASH_SPI = 4 9 | # chip: is25lp032d is25lp128f s25fl164k 10 | FLASH_CHIP = is25lp128f 11 | 12 | # ******* design files ******* 13 | CONSTRAINTS = ../../constraints/ulx3s_v20_dif.lpf 14 | 15 | # usually all toplevels have the same top module name 16 | TOP_MODULE = ulx3s_usbtest 17 | 18 | # various toplevels for building different f32c soc's 19 | TOP_MODULE_FILE = ../../../../lattice/ulx3s/top/ulx3s_usbserial.vhd 20 | 21 | include files.mk 22 | 23 | #BITSTREAM = \ 24 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).bit \ 25 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).vme \ 26 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT).svf \ 27 | #$(BOARD)_$(FPGA_SIZE)f_$(PROJECT)_flash_$(FLASH_CHIP).vme 28 | 29 | SCRIPTS = ../../../../../../scripts 30 | include $(SCRIPTS)/trellis_path.mk 31 | include $(SCRIPTS)/diamond_path.mk 32 | include $(SCRIPTS)/diamond_main.mk 33 | -------------------------------------------------------------------------------- /examples/usb/proj/xilinx/ffm-a7100/ffm-a7100-vivado/cablelist.txt: -------------------------------------------------------------------------------- 1 | ft4232h ftdi 1500000 0x0403:0x6011: 2 | ft4232h_fast ftdi 30000000 0x0403:0x6011: 3 | -------------------------------------------------------------------------------- /examples/usb/proj/xilinx/ffm-a7100/ffm-a7100-vivado/devlist.txt: -------------------------------------------------------------------------------- 1 | # IDCODE IR_len ID_Cmd Text 2 | 03631093 6 0x0009 XA7A100T 3 | 3f0f0f0f 4 0x0000 AT91SAM7SX 4 | -------------------------------------------------------------------------------- /examples/usb/proj/xilinx/ffm-a7100/ffm-a7100-vivado/xilinx.opt: -------------------------------------------------------------------------------- 1 | -ifmt mixed 2 | -ofmt NGC 3 | -opt_mode speed 4 | -opt_level 2 5 | -iuc NO 6 | -keep_hierarchy no 7 | #-netlist_hierarchy as_optimized 8 | -netlist_hierarchy rebuilt 9 | -rtlview no 10 | -glob_opt AllClockNets 11 | -read_cores yes 12 | -write_timing_constraints YES 13 | -cross_clock_analysis NO 14 | -hierarchy_separator / 15 | -bus_delimiter <> 16 | -case maintain 17 | -slice_utilization_ratio 100 18 | -bram_utilization_ratio 100 19 | #-dsp_utilization_ratio 100 20 | -safe_implementation YES 21 | -fsm_extract YES 22 | -fsm_encoding Auto 23 | -fsm_style lut 24 | -ram_extract Yes 25 | -ram_style Auto 26 | -rom_extract Yes 27 | -rom_style Auto 28 | -shreg_extract YES 29 | -auto_bram_packing YES 30 | -resource_sharing YES 31 | -async_to_sync NO 32 | #-use_dsp48 auto 33 | -iobuf YES 34 | -max_fanout 500 35 | -register_duplication YES 36 | -register_balancing YES 37 | -optimize_primitives YES 38 | -use_clock_enable Auto 39 | -use_sync_set Auto 40 | -use_sync_reset Auto 41 | -iob auto 42 | -equivalent_register_removal YES 43 | -slice_utilization_ratio_maxmargin 5 44 | -use_new_parser yes 45 | -------------------------------------------------------------------------------- /examples/usb/proj/xilinx/include/bit2svf.ut: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port svf -file "default.svf" 3 | addDevice -p 1 -file "default.bit" 4 | Program -p 1 5 | exit 6 | -------------------------------------------------------------------------------- /examples/usb/proj/xilinx/include/bit2xsvf.ut: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port xsvf -file "default.xsvf" 3 | addDevice -p 1 -file "default.bit" 4 | Program -p 1 5 | exit 6 | -------------------------------------------------------------------------------- /examples/usb/proj/xilinx/include/vivado.mk: -------------------------------------------------------------------------------- 1 | # linux version 2 | vivado ?= /opt/Xilinx/Vivado/2018.1/bin/vivado 3 | # windows version 4 | # vivado ?= /cygdrive/c/Xilinx/Vivado/2015.4/bin/vivado 5 | # basename of the file some_project.xpr 6 | project ?= project 7 | # xc3sprog interface name 8 | xc3sprog_interface ?= ftdi 9 | xc3sprog_device ?= 0 10 | # name of the resulting bitstream file (*.bit) 11 | bitfile?=$(project).runs/impl_1/glue.bit 12 | junk?=junk.log 13 | 14 | build: $(bitfile) 15 | 16 | $(bitfile): clean 17 | # $(vivado) -mode tcl -source run_vivado.tcl -tclargs build 18 | $(vivado) -mode tcl -source run_vivado.tcl -tclargs build -tclargs $(project).xpr 19 | 20 | clean: 21 | # slow and it doesn't clean it all 22 | # $(vivado) -mode tcl -source run_vivado.tcl -tclargs clean 23 | # faster to remove project files 24 | rm -rf *~ vivado.jou vivado.log webtalk* vivado_*.backup.??? 25 | rm -rf $(project).cache $(project).hw $(project).runs 26 | # rm -rf $(project).sim $(project).srcs 27 | rm -rf $(junk) 28 | 29 | program: xc3sprog 30 | 31 | xc3sprog: 32 | xc3sprog -c $(xc3sprog_interface) -p $(xc3sprog_device) $(bitfile) 33 | -------------------------------------------------------------------------------- /examples/usb/usbcdc/fpgaser.inf: -------------------------------------------------------------------------------- 1 | [Version] 2 | Signature="$Windows NT$" 3 | Class=Ports 4 | ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} 5 | 6 | Provider=%JORIS% 7 | LayoutFile=layout.inf 8 | DriverVer=10/15/1999,5.0.2153.1 9 | 10 | [Manufacturer] 11 | %JORIS%=JORIS 12 | 13 | [JORIS] 14 | %FPGASER%=Reader, USB\VID_FB9A&PID_FB9A 15 | 16 | [Reader_Install.NTx86] 17 | ;Windows2000 18 | 19 | [DestinationDirs] 20 | DefaultDestDir=12 21 | Reader.NT.Copy=12 22 | 23 | [Reader.NT] 24 | CopyFiles=Reader.NT.Copy 25 | AddReg=Reader.NT.AddReg 26 | 27 | [Reader.NT.Copy] 28 | usbser.sys 29 | 30 | [Reader.NT.AddReg] 31 | HKR,,DevLoader,,*ntkern 32 | HKR,,NTMPDriver,,usbser.sys 33 | HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" 34 | 35 | [Reader.NT.Services] 36 | AddService = usbser, 0x00000002, Service_Inst 37 | 38 | [Service_Inst] 39 | DisplayName = %Serial.SvcDesc% 40 | ServiceType = 1 ; SERVICE_KERNEL_DRIVER 41 | StartType = 3 ; SERVICE_DEMAND_START 42 | ErrorControl = 1 ; SERVICE_ERROR_NORMAL 43 | ServiceBinary = %12%\usbser.sys 44 | LoadOrderGroup = Base 45 | 46 | [Strings] 47 | JORIS = "Joris" 48 | FPGASER = "FPGA Serial" 49 | Serial.SvcDesc = "USB Serial emulation driver" 50 | 51 | -------------------------------------------------------------------------------- /examples/usb/usbhid/report_decoded_pack_generic.vhd: -------------------------------------------------------------------------------- 1 | -- (c) EMARD 2 | -- License=BSD 3 | 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | 7 | package report_decoded_pack is 8 | type T_report_decoded is 9 | record 10 | lstick_x, lstick_y, rstick_x, rstick_y: std_logic_vector(7 downto 0); -- up/left=0 idle=128 down/right=255 11 | lmouseq_x, lmouseq_y, rmouseq_x, rmouseq_y: std_logic_vector(1 downto 0); -- stick to quadrature encoder output 12 | analog_ltrigger, analog_rtrigger: std_logic_vector(7 downto 0); 13 | hat_up, hat_down, hat_left, hat_right: std_logic; 14 | lstick_up, lstick_down, lstick_left, lstick_right: std_logic; 15 | rstick_up, rstick_down, rstick_left, rstick_right: std_logic; 16 | btn_a, btn_b, btn_x, btn_y: std_logic; 17 | btn_lbumper, btn_rbumper: std_logic; 18 | btn_ltrigger, btn_rtrigger: std_logic; 19 | btn_back, btn_start: std_logic; 20 | btn_lstick, btn_rstick: std_logic; 21 | btn_fps, btn_fps_toggle: std_logic; 22 | btn_lmouse_left, btn_lmouse_right: std_logic; 23 | btn_rmouse_left, btn_rmouse_right: std_logic; 24 | end record; 25 | end; 26 | -------------------------------------------------------------------------------- /examples/usb/usbhost/usbh_setup_rom.mem: -------------------------------------------------------------------------------- 1 | // minimal setup sequence is usually the most compatible 2 | // byte length of this sequence should be equal to 3 | // parameter "C_setup_rom_len" in file "usbh_host_hid.v" 4 | 5 | // set_address 1, Microsoft IntelliMouse needs address > 0 to activate reports 6 | 00 05 01 00 00 00 00 00 7 | // set_configuration 1, most devices need configuration = 1 to activate reports 8 | 00 09 01 00 00 00 00 00 9 | 10 | // transmission example 11 | // 00 09 01 00 00 00 00 00 12 | // HOST: < SYNC >EP0 CRC5 13 | // D+ ___-_-_-_---___--_-_-_-_-_-_-_--_-_____ 14 | // D- ---_-_-_-___---__-_-_-_-_-_-_-__-_-__-- 15 | // HOST: < SYNC >< 00 >< 09 >< 01 >< 00 >< 00 >< 00 >< 00 >< 00 >< CRC16 > 16 | // D+ ___-_-_-_----_-_---_-_-_-_--_--_-_--_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-____-__-__--_--_-____ 17 | // D- ---_-_-_-____-_-___-_-_-_-__-__-_-__-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_----_--_--__-__-___-- 18 | // MOUSE: < SYNC >< ACK > 19 | // D+ ___-_-_-_--__-__---_____ 20 | // D- ---_-_-_-__--_--_____--- 21 | -------------------------------------------------------------------------------- /examples/vhdlib/Makefile: -------------------------------------------------------------------------------- 1 | PROJ=blink 2 | all: $(PROJ).bit 3 | 4 | FPGA_SIZE=12 5 | 6 | CONSTRAINTS=../../constraints/ulx3s_v20.lpf 7 | 8 | FILES=vhd/top_blink.vhd vhd/blink.vhd 9 | 10 | $(PROJ).json: $(FILES) synth.ys Makefile 11 | yosys -q synth.ys 12 | 13 | $(PROJ).config: $(PROJ).json 14 | nextpnr-ecp5 --router router2 --json $(PROJ).json \ 15 | --$(FPGA_SIZE)k --speed 6 --package CABGA381 \ 16 | --lpf $(CONSTRAINTS) \ 17 | --timing-allow-fail --no-tmdriv \ 18 | --textcfg $@ 19 | 20 | $(PROJ).bit: $(PROJ).config 21 | ecppack --compress $< $@ 22 | 23 | prog: $(PROJ).bit 24 | fujprog $< 25 | 26 | clean: 27 | rm -f $(PROJ).bit $(PROJ).config $(PROJ).json *~ 28 | -------------------------------------------------------------------------------- /examples/vhdlib/synth.ys: -------------------------------------------------------------------------------- 1 | ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \ 2 | --work=custom_lib \ 3 | vhd/blinkpkg.vhd \ 4 | vhd/blink.vhd \ 5 | -e blink 6 | 7 | ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \ 8 | --work=work \ 9 | vhd/top_blink.vhd \ 10 | -e top_blink 11 | 12 | delete cegen 13 | 14 | synth_ecp5 -top top_blink -nowidelut -run :check 15 | 16 | stat 17 | check -noinit 18 | 19 | write_json blink.json 20 | -------------------------------------------------------------------------------- /examples/vhdlib/vhd/blink.vhd: -------------------------------------------------------------------------------- 1 | -- (c)EMARD 2 | -- License=BSD 3 | 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | use ieee.numeric_std.all; 7 | 8 | library custom_lib; 9 | use custom_lib.blinkpkg.all; 10 | 11 | entity blink is 12 | generic 13 | ( 14 | bits : natural := c_blink_bits 15 | ); 16 | port 17 | ( 18 | clk : in std_logic; 19 | led : out std_logic_vector(7 downto 0) 20 | ); 21 | end; 22 | 23 | architecture mix of blink is 24 | signal R_counter : unsigned(bits-1 downto 0); 25 | begin 26 | process(clk) 27 | begin 28 | if rising_edge(clk) then 29 | R_counter <= R_counter+1; 30 | end if; 31 | end process; 32 | led <= std_logic_vector(R_counter(led'range)); 33 | end mix; 34 | -------------------------------------------------------------------------------- /examples/vhdlib/vhd/blinkpkg.vhd: -------------------------------------------------------------------------------- 1 | package blinkpkg is 2 | constant c_blink_bits : natural := 25; 3 | end; 4 | -------------------------------------------------------------------------------- /examples/vhdlib/vhd/top_blink.vhd: -------------------------------------------------------------------------------- 1 | -- (c)EMARD 2 | -- License=BSD 3 | 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | use ieee.std_logic_unsigned.all; 7 | 8 | library custom_lib; 9 | 10 | entity top_blink is 11 | generic 12 | ( 13 | bits: integer := 25 14 | ); 15 | port 16 | ( 17 | clk_25mhz : in std_logic; -- main clock input from 25MHz clock source 18 | led : out std_logic_vector(7 downto 0) 19 | ); 20 | end; 21 | 22 | architecture mix of top_blink is 23 | begin 24 | 25 | blink_inst: entity custom_lib.blink 26 | generic map 27 | ( 28 | bits => bits 29 | ) 30 | port map 31 | ( 32 | clk => clk_25mhz, 33 | led => led 34 | ); 35 | 36 | end mix; 37 | -------------------------------------------------------------------------------- /multiplatform/README.md: -------------------------------------------------------------------------------- 1 | # Multiplatform 2 | 3 | Things here are for multiplatform compilation. 4 | They are not directly ULX3S related, but can 5 | be useful for compiling the same source for 6 | other platforms and comparing the results. 7 | -------------------------------------------------------------------------------- /multiplatform/xilinx/vivado/esa11-unimake/cablelist.txt: -------------------------------------------------------------------------------- 1 | ft4232h ftdi 1500000 0x0403:0x6011: 2 | ft4232h_fast ftdi 30000000 0x0403:0x6011: 3 | -------------------------------------------------------------------------------- /multiplatform/xilinx/vivado/esa11-unimake/devlist.txt: -------------------------------------------------------------------------------- 1 | # IDCODE IR_len ID_Cmd Text 2 | 03631093 6 0x0009 XA7A100T 3 | 3f0f0f0f 4 0x0000 AT91SAM7SX 4 | -------------------------------------------------------------------------------- /multiplatform/xilinx/vivado/esa11-unimake/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | FPGA_CHIP_UPPERCASE=XC7T100 3 | 4 | CONSTRAINTS="constr1.xdc constr2.xdc" 5 | VHDL_FILES="file1.vhd file2.vhd" 6 | VERILOG_FILES="file3.v file4.v" 7 | # xci files without .xci extensions 8 | XCI_FILES="clock1 clock2" 9 | 10 | xsltproc \ 11 | --stringparam FPGA_DEVICE "xc7a100tfgg484-999" \ 12 | --stringparam CONSTRAINTS_FILES "${CONSTRAINTS}" \ 13 | --stringparam TOP_MODULE "top_module123" \ 14 | --stringparam VHDL_FILES "${VHDL_FILES}" \ 15 | --stringparam VERILOG_FILES "${VERILOG_FILES}" \ 16 | --stringparam XCI_FILES "${XCI_FILES}" \ 17 | xpr.xsl empty.xpr > modified.xpr 18 | 19 | # --stringparam FPGA_DEVICE $(FPGA_CHIP_UPPERCASE)-$(FPGA_PACKAGE_UPPERCASE) \ 20 | # --stringparam STRATEGY_FILE $(STRATEGY) \ 21 | # --stringparam XCF_FILE $(SCRIPTS)/$(BOARD)_sram.xcf \ 22 | # --stringparam TOP_MODULE $(TOP_MODULE) \ 23 | # --stringparam TOP_MODULE_FILE $(TOP_MODULE_FILE) \ 24 | -------------------------------------------------------------------------------- /multiplatform/xilinx/vivado/esa11-unimake/vivado.mk: -------------------------------------------------------------------------------- 1 | # linux version 2 | vivado ?= /opt/Xilinx/Vivado/2017.3/bin/vivado 3 | # windows version 4 | # vivado ?= /cygdrive/c/Xilinx/Vivado/2015.4/bin/vivado 5 | # basename of the file some_project.xpr 6 | project ?= project 7 | # xc3sprog interface name 8 | xc3sprog_interface ?= ftdi 9 | xc3sprog_device ?= 0 10 | # name of the resulting bitstream file (*.bit) 11 | bitfile?=$(project).runs/impl_1/glue.bit 12 | junk?=junk.log 13 | 14 | build: $(bitfile) 15 | 16 | $(bitfile): clean 17 | # $(vivado) -mode tcl -source run_vivado.tcl -tclargs build 18 | $(vivado) -mode tcl -source run_vivado.tcl -tclargs build -tclargs $(project).xpr 19 | 20 | clean: 21 | # slow and it doesn't clean it all 22 | # $(vivado) -mode tcl -source run_vivado.tcl -tclargs clean 23 | # faster to remove project files 24 | rm -rf *~ vivado.jou vivado.log webtalk* vivado_*.backup.??? 25 | rm -rf $(project).cache $(project).hw $(project).runs 26 | # rm -rf $(project).sim $(project).srcs 27 | rm -rf $(junk) 28 | 29 | program: xc3sprog 30 | 31 | xc3sprog: 32 | xc3sprog -c $(xc3sprog_interface) -p $(xc3sprog_device) $(bitfile) 33 | -------------------------------------------------------------------------------- /scripts/IspXCF.dtd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emard/ulx3s-misc/8c07331dd1f9492a8c08bd4bb0b6495ae7630664/scripts/IspXCF.dtd -------------------------------------------------------------------------------- /scripts/diamond_path.mk: -------------------------------------------------------------------------------- 1 | # the path of your diamond installation 2 | DIAMOND_BASE ?= /usr/local/diamond 3 | 4 | # it is a directory that looks like this: 5 | # ls /usr/local/diamond 6 | # 3.7_x64 7 | -------------------------------------------------------------------------------- /scripts/ecp5-ocd.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # ecp5-ocd.sh 3 | 4 | CHIP_ID=$1 5 | FILE_SVF=$2 6 | 7 | cat << EOF 8 | # OpenOCD commands 9 | 10 | telnet_port 4444 11 | gdb_port 3333 12 | 13 | # JTAG TAPs 14 | jtag newtap lfe5 tap -expected-id ${CHIP_ID} -irlen 8 -irmask 0xFF -ircapture 0x5 15 | 16 | init 17 | scan_chain 18 | svf -tap lfe5.tap -quiet -progress ${FILE_SVF} 19 | shutdown 20 | EOF 21 | -------------------------------------------------------------------------------- /scripts/ft2232.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Generic FT2232H JTAG Programmer 3 | # 4 | 5 | adapter driver ftdi 6 | # ftdi_device_desc "Dual RS232-HS" 7 | ftdi_vid_pid 0x0403 0x6010 8 | ftdi_layout_init 0x3088 0x1f8b 9 | 10 | # default is port A if unspecified 11 | # pinout ADBUS 0-TCK 1-TDI 2-TDO 3-TMS 12 | #ftdi_channel 0 13 | 14 | # uncomment this to use port B 15 | # pinout BDBUS 0-TCK 1-TDI 2-TDO 3-TMS 16 | #ftdi_channel 1 17 | 18 | adapter speed 25000 19 | -------------------------------------------------------------------------------- /scripts/ft231x.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag nums and buffer_size 3 | # 4 | 5 | adapter driver ft232r 6 | ft232r_vid_pid 0x0403 0x6015 7 | # ft232r_serial_desc 123456 8 | ft232r_tck_num DSR 9 | ft232r_tms_num DCD 10 | ft232r_tdi_num RI 11 | ft232r_tdo_num CTS 12 | ft232r_trst_num RTS 13 | ft232r_srst_num DTR 14 | ft232r_restore_serial 0x15 15 | adapter speed 1000 16 | -------------------------------------------------------------------------------- /scripts/ft231x2.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag nums and buffer_size 3 | # pinout for ulx3s jtag-thru: 4 | 5 | # GP14 TMS 6 | # GN14 TDO 7 | # GP15 TDI 8 | # GN15 TCK 9 | 10 | adapter driver ft232r 11 | ft232r_vid_pid 0x0403 0x6015 12 | # ft232r_serial_desc 250001 13 | ft232r_tck_num DTR 14 | ft232r_tms_num RTS 15 | ft232r_tdi_num TXD 16 | ft232r_tdo_num RXD 17 | ft232r_trst_num DCD 18 | ft232r_srst_num RI 19 | adapter speed 1000 20 | -------------------------------------------------------------------------------- /scripts/ft232r.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # openocd_ft232r patched for custom jtag nums and buffer_size 3 | # low-cost FT232R board from ebay 4 | 5 | interface ft232r 6 | # ft232r_vid_pid 0x0403 0x6015 7 | # ft232r_serial_desc 250001 8 | ft232r_tck_num DTR 9 | ft232r_tms_num CTS 10 | ft232r_tdi_num TXD 11 | ft232r_tdo_num RXD 12 | ft232r_trst_num DCD 13 | ft232r_srst_num RI 14 | adapter speed 1000 15 | -------------------------------------------------------------------------------- /scripts/ft4232.ocd: -------------------------------------------------------------------------------- 1 | # 2 | # Generic FT4232 JTAG Programmer 3 | # 4 | 5 | adapter driver ftdi 6 | # ftdi_device_desc "Quad RS232-HS" 7 | ftdi_vid_pid 0x0403 0x6011 8 | ftdi_layout_init 0x3088 0x1f8b 9 | 10 | # default is port A if unspecified 11 | # pinout ADBUS 0-TCK 1-TDI 2-TDO 3-TMS 12 | #ftdi_channel 0 13 | 14 | # uncomment this to use port B 15 | # pinout BDBUS 0-TCK 1-TDI 2-TDO 3-TMS 16 | #ftdi_channel 1 17 | 18 | adapter speed 25000 19 | -------------------------------------------------------------------------------- /scripts/project.ldf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /scripts/trellis_path.mk: -------------------------------------------------------------------------------- 1 | # ******* tools installation paths ******* 2 | # https://github.com/SymbiFlow/prjtrellis 3 | TRELLIS ?= /mt/scratch/tmp/openfpga/prjtrellis 4 | # https://github.com/ldoolitt/vhd2vl 5 | VHDL2VL ?= vhd2vl 6 | # https://github.com/YosysHQ/yosys 7 | YOSYS ?= yosys 8 | # https://github.com/YosysHQ/nextpnr 9 | NEXTPNR-ECP5 ?= nextpnr-ecp5 10 | # trellis ecppack 11 | ECPPACK ?= LANG=C ecppack 12 | ECPPLL ?= LANG=C ecppll 13 | --------------------------------------------------------------------------------