├── .vscode ├── .gitignore └── settings.json ├── .gitattributes ├── transforms ├── GPIO.yaml ├── DCACHE.yaml ├── VREFBUF.yaml ├── FLASH_f0.yaml ├── CORDIC.yaml ├── TSC.yaml ├── LTDC.yaml ├── TIMER.yaml ├── PSSI.yaml ├── DTS.yaml ├── XSPIM.yaml ├── SPI.yaml ├── SYSCFG_F0.yaml ├── ADCCOMMON.yaml ├── ICACHE.yaml ├── COMP_h.yaml ├── PWR.yaml ├── AES.yaml ├── SAES.yaml ├── OPAMP.yaml ├── RTC.yaml ├── DBGMCU.yaml ├── GFXMMU.yaml ├── SDADC.yaml ├── XSPI.yaml ├── OTFDEC.yaml ├── USB_OTG.yaml ├── SAI.yaml ├── ADC.yaml ├── SYSCFG_F3.yaml ├── EXTI.yaml ├── LPTIM_v2.yaml ├── ETH.yaml ├── FMC.yaml ├── I3C.yaml ├── TAMP.yaml ├── RCC.yaml └── HRTIM.yaml ├── rustfmt.toml ├── .gitignore ├── data ├── extra │ └── family │ │ ├── STM32G0.yaml │ │ ├── STM32WL.yaml │ │ ├── STM32WB.yaml │ │ ├── STM32H5.yaml │ │ ├── STM32U0.yaml │ │ ├── STM32U3.yaml │ │ ├── STM32U5.yaml │ │ ├── STM32L5.yaml │ │ ├── STM32L4+.yaml │ │ ├── STM32L4.yaml │ │ ├── STM32H7.yaml │ │ └── STM32F3.yaml ├── registers │ ├── vrefintcal_v1.yaml │ ├── fdcanram_h7.yaml │ ├── usbram_32_1024.yaml │ ├── usbram_32_2048.yaml │ ├── usbram_16x1_512.yaml │ ├── usbram_16x2_512.yaml │ ├── usbram_16x2_1024.yaml │ ├── uid_v1.yaml │ ├── vrefintcal_v2.yaml │ ├── crc_v1.yaml │ ├── fdcanram_v1.yaml │ ├── xspim_v1.yaml │ ├── exti_h7.yaml │ ├── exti_wle.yaml │ ├── exti_v1.yaml │ ├── rng_v1.yaml │ ├── syscfg_l1.yaml │ ├── vrefbuf_v1.yaml │ ├── exti_w.yaml │ ├── pwr_f0x0.yaml │ ├── wwdg_v1.yaml │ ├── vrefbuf_v2b.yaml │ ├── adccommon_c0.yaml │ ├── pwr_f1.yaml │ ├── exti_c0.yaml │ ├── exti_g0.yaml │ ├── exti_u0.yaml │ ├── pwr_f0.yaml │ ├── wwdg_v2.yaml │ ├── syscfg_f4.yaml │ ├── syscfg_f2.yaml │ ├── comp_f3_v1.yaml │ ├── pwr_f2.yaml │ ├── pwr_f3.yaml │ ├── crc_v2.yaml │ ├── crc_v3.yaml │ ├── ipcc_v1.yaml │ ├── dbgmcu_c0.yaml │ ├── iwdg_v1.yaml │ ├── comp_v2.yaml │ ├── dbgmcu_l0.yaml │ ├── comp_v1.yaml │ ├── iwdg_v2.yaml │ ├── comp_v3.yaml │ ├── vrefbuf_v2a2.yaml │ ├── exti_h50.yaml │ ├── hash_v1.yaml │ ├── pwr_l1.yaml │ ├── dbgmcu_f1.yaml │ ├── octospim_v1.yaml │ ├── syscfg_f7.yaml │ ├── vrefbuf_v2a1.yaml │ ├── dbgmcu_g0.yaml │ ├── exti_l5.yaml │ ├── exti_u5.yaml │ ├── dbgmcu_f0.yaml │ ├── hash_v2.yaml │ └── exti_n6.yaml └── dmamux │ ├── U5_LPDMA.yaml │ ├── H7RS_HPDMA.yaml │ ├── H7_DMAMUX2.yaml │ ├── WB_DMAMUX1.yaml │ ├── WL_DMAMUX1.yaml │ ├── C0_DMAMUX1.yaml │ ├── WBA_GPDMA1.yaml │ ├── G0_DMAMUX1.yaml │ ├── U0_DMAMUX1.yaml │ ├── U3_GPDMA1.yaml │ ├── L4PQ_DMAMUX1.yaml │ ├── L4RS_DMAMUX1.yaml │ ├── L5_DMAMUX1.yaml │ ├── H7RS_GPDMA.yaml │ ├── U5_GPDMA1.yaml │ ├── G4_DMAMUX1.yaml │ ├── H5_GPDMA.yaml │ ├── H7_DMAMUX1.yaml │ ├── N6_HPDMA.yaml │ └── N6_GPDMA.yaml ├── stm32-data-macros ├── Cargo.toml ├── tests │ └── test_macros.rs └── src │ └── lib.rs ├── rust-toolchain.toml ├── stm32-metapac-gen ├── Cargo.toml ├── src │ └── main.rs └── res │ ├── src │ └── lib.rs │ ├── README.md │ ├── build.rs │ └── Cargo.toml ├── stm32-data-serde └── Cargo.toml ├── stm32-data-gen ├── src │ ├── normalize_peris.rs │ ├── check.rs │ ├── util.rs │ ├── registers.rs │ ├── main.rs │ └── low_power.rs └── Cargo.toml ├── Cargo.toml ├── .github └── ci │ ├── doc.sh │ ├── generated.sh │ └── build.sh ├── merge_regs.py └── d.ps1 /.vscode/.gitignore: -------------------------------------------------------------------------------- 1 | launch.json 2 | tasks.json -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | d -text eol=lf 2 | *.sh eol=lf 3 | *.json eol=lf -------------------------------------------------------------------------------- /transforms/GPIO.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(LCKK?)$ 4 | -------------------------------------------------------------------------------- /transforms/DCACHE.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteFieldsets 3 | from: (R|W)HMONR 4 | -------------------------------------------------------------------------------- /transforms/VREFBUF.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(ENVR|VRR)$ 4 | -------------------------------------------------------------------------------- /rustfmt.toml: -------------------------------------------------------------------------------- 1 | group_imports = "StdExternalCrate" 2 | imports_granularity = "Module" 3 | max_width=120 -------------------------------------------------------------------------------- /transforms/FLASH_f0.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(VDDA_MONITOR|nBOOT[01])$ 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /build 2 | /files 3 | /sources 4 | /tmp 5 | .idea/ 6 | .DS_Store 7 | # transform*.yaml 8 | __pycache__ 9 | regs_merged.yaml 10 | 11 | target/ 12 | venv/ -------------------------------------------------------------------------------- /transforms/CORDIC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !MergeEnums 3 | from: (ARG|RES)SIZE 4 | to: Size 5 | 6 | - !MergeEnums 7 | from: N(ARGS|RES) 8 | to: Num 9 | -------------------------------------------------------------------------------- /data/extra/family/STM32G0.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | - name: TAMP 4 | address: 0x4000B000 5 | registers: 6 | kind: tamp 7 | version: g0 8 | block: TAMP 9 | -------------------------------------------------------------------------------- /data/extra/family/STM32WL.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | - name: TAMP 4 | address: 0x4000B000 5 | registers: 6 | kind: tamp 7 | version: wl 8 | block: TAMP 9 | -------------------------------------------------------------------------------- /transforms/TSC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !MergeFieldsets 3 | from: (IOG)\d+(CR) 4 | to: $1$2 5 | - !MakeRegisterArray 6 | blocks: .* 7 | from: (IOG)\d+(CR) 8 | to: $1$2 9 | -------------------------------------------------------------------------------- /data/extra/family/STM32WB.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | - name: VREFINTCAL 4 | address: 0x1FFF75AA 5 | registers: 6 | kind: vrefintcal 7 | version: v1 8 | block: VREFINTCAL 9 | -------------------------------------------------------------------------------- /transforms/LTDC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(CLUTEN|COLKEN|DEN|FUIE|LEN|LIE|LTDCEN|RRIE|TERRIE)$ 4 | - !DeleteEnums 5 | from: ^(FUIF|HDES|HSYNCS|LIF|RRIF|TERRIF|VDES|VSYNCS)$ 6 | -------------------------------------------------------------------------------- /transforms/TIMER.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(ARPE|OCPE|OPM|ECE)$ 4 | 5 | - !DeleteFieldsets 6 | from: ^(CCR_GP32|ARR_GP32|CNT_GP32|DMAR_1CH_CMP|DMAR_ADV)$ 7 | bit_size: 32 8 | -------------------------------------------------------------------------------- /transforms/PSSI.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | 3 | - !DeleteEnums 4 | from: ^(DMAEN|ENABLE|OVR_(IE|ISC|MIS|RIS)|RTT(1|4)B)$ 5 | 6 | - !MakeFieldArray 7 | fieldsets: DR 8 | from: BYTE\d 9 | to: BYTE 10 | -------------------------------------------------------------------------------- /transforms/DTS.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | 3 | - !RenameFields 4 | fieldset: .+ 5 | from: ^TS1_(.+)$ 6 | to: $1 7 | 8 | - !MakeFieldArray 9 | fieldsets: OR 10 | from: TS_OP\d+ 11 | to: OP 12 | -------------------------------------------------------------------------------- /data/registers/vrefintcal_v1.yaml: -------------------------------------------------------------------------------- 1 | block/VREFINTCAL: 2 | description: VREFINT Factory Calibration 3 | items: 4 | - name: DATA 5 | description: Factory calibration 6 | byte_offset: 0 7 | bit_size: 16 8 | access: Read 9 | -------------------------------------------------------------------------------- /data/registers/fdcanram_h7.yaml: -------------------------------------------------------------------------------- 1 | block/FDCANRAM: 2 | description: FDCAN Message RAM 3 | items: 4 | - name: RAM 5 | description: FDCAN Message RAM 6 | array: 7 | len: 2560 8 | stride: 4 9 | byte_offset: 0 10 | -------------------------------------------------------------------------------- /stm32-data-macros/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32-data-macros" 3 | version = "0.1.0" 4 | edition = "2024" 5 | 6 | [lib] 7 | proc-macro = true 8 | 9 | [dependencies] 10 | proc-macro2 = "1.0.36" 11 | quote = "1.0.15" 12 | syn = "1.0" -------------------------------------------------------------------------------- /data/registers/usbram_32_1024.yaml: -------------------------------------------------------------------------------- 1 | block/USBRAM: 2 | description: USB Endpoint memory 3 | items: 4 | - name: MEM 5 | description: USB Endpoint memory 6 | array: 7 | len: 256 8 | stride: 4 9 | byte_offset: 0 10 | -------------------------------------------------------------------------------- /data/registers/usbram_32_2048.yaml: -------------------------------------------------------------------------------- 1 | block/USBRAM: 2 | description: USB Endpoint memory 3 | items: 4 | - name: MEM 5 | description: USB Endpoint memory 6 | array: 7 | len: 512 8 | stride: 4 9 | byte_offset: 0 10 | -------------------------------------------------------------------------------- /stm32-data-macros/tests/test_macros.rs: -------------------------------------------------------------------------------- 1 | #![allow(dead_code)] 2 | 3 | use stm32_data_macros::EnumDebug; 4 | 5 | #[derive(Debug)] 6 | struct A { 7 | pub b: String, 8 | } 9 | 10 | #[derive(EnumDebug)] 11 | enum C { 12 | D(A), 13 | E, 14 | } 15 | -------------------------------------------------------------------------------- /data/registers/usbram_16x1_512.yaml: -------------------------------------------------------------------------------- 1 | block/USBRAM: 2 | description: USB Endpoint memory 3 | items: 4 | - name: MEM 5 | description: USB Endpoint memory 6 | array: 7 | len: 256 8 | stride: 4 9 | byte_offset: 0 10 | bit_size: 16 11 | -------------------------------------------------------------------------------- /data/registers/usbram_16x2_512.yaml: -------------------------------------------------------------------------------- 1 | block/USBRAM: 2 | description: USB Endpoint memory 3 | items: 4 | - name: MEM 5 | description: USB Endpoint memory 6 | array: 7 | len: 256 8 | stride: 2 9 | byte_offset: 0 10 | bit_size: 16 11 | -------------------------------------------------------------------------------- /data/registers/usbram_16x2_1024.yaml: -------------------------------------------------------------------------------- 1 | block/USBRAM: 2 | description: USB Endpoint memory 3 | items: 4 | - name: MEM 5 | description: USB Endpoint memory 6 | array: 7 | len: 512 8 | stride: 2 9 | byte_offset: 0 10 | bit_size: 16 11 | -------------------------------------------------------------------------------- /transforms/XSPIM.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !Rename 3 | from: ^XSPIM1$ 4 | to: XSPIM 5 | type: Block 6 | 7 | - !Rename 8 | from: ^XSPIM_(.+) 9 | to: $1 10 | type: All 11 | 12 | - !RenameRegisters 13 | block: XSPIM 14 | from: ^XSPIM_(.+)$ 15 | to: $1 16 | -------------------------------------------------------------------------------- /transforms/SPI.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(ISE|MCKOE|AFCNTR|CRC_)$ 4 | - !RenameEnumVariants 5 | enum: ^BIDIOE$ 6 | from: OutputDisabled 7 | to: Receive 8 | - !RenameEnumVariants 9 | enum: ^BIDIOE$ 10 | from: OutputEnabled 11 | to: Transmit 12 | -------------------------------------------------------------------------------- /transforms/SYSCFG_F0.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: .*_RMP2? 4 | bit_size: 1 5 | keep_desc: true 6 | 7 | - !MergeEnums 8 | from: .*_FMP 9 | to: FMP 10 | keep_desc: true 11 | 12 | - !DeleteEnums 13 | from: ^(LOCKUP_LOCK|PVD_LOCK|SRAM_PARITY_LOCK)$ 14 | -------------------------------------------------------------------------------- /data/dmamux/U5_LPDMA.yaml: -------------------------------------------------------------------------------- 1 | LPUART1_RX: 0 2 | LPUART1_TX: 1 3 | SPI3_RX: 2 4 | SPI3_TX: 3 5 | I2C3_RX: 4 6 | I2C3_TX: 5 7 | I2C3_EVC: 6 8 | ADC4: 7 9 | DAC1_CH1: 8 10 | DAC1_CH2: 9 11 | ADF1_FLT0: 10 12 | LPTIM1_IC1: 11 13 | LPTIM1_IC2: 12 14 | LPTIM1_UE: 13 15 | LPTIM3_IC1: 14 16 | LPTIM3_IC2: 15 17 | LPTIM3_UE: 16 18 | -------------------------------------------------------------------------------- /transforms/ADCCOMMON.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !ModifyByteOffset 3 | blocks: ADC_COMMON 4 | exclude_items: ^CDR$ 5 | add_offset: -768 # 0x300 6 | 7 | - !MakeFieldArray 8 | fieldsets: CSR 9 | from: AWD\d_(MST|SLV) 10 | to: AWD_$1 11 | 12 | - !DeleteFieldsets 13 | from: ^(IPDR|SIDR)$ 14 | -------------------------------------------------------------------------------- /transforms/ICACHE.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | 3 | - !DeleteEnums 4 | from: ^(CACHEINV|HITMRST|MISSMRST)$ 5 | 6 | - !DeleteFieldsets 7 | from: HMONR 8 | 9 | - !MergeFieldsets 10 | from: CRR\d 11 | to: CRR 12 | 13 | - !MakeRegisterArray 14 | blocks: ICACHE 15 | from: CRR\d 16 | to: CRR 17 | -------------------------------------------------------------------------------- /data/registers/uid_v1.yaml: -------------------------------------------------------------------------------- 1 | block/UID: 2 | description: Device Factory programmed 96-bit unique device identifier 3 | items: 4 | - name: UID 5 | description: Factory programmed 96-bit unique device identifier word 0 6 | array: 7 | len: 3 8 | stride: 4 9 | byte_offset: 0 10 | access: Read 11 | -------------------------------------------------------------------------------- /data/dmamux/H7RS_HPDMA.yaml: -------------------------------------------------------------------------------- 1 | JPEG_RX: 0 2 | JPEG_TX: 1 3 | XSPI1_RX: 2 4 | XSPI2_RX: 3 5 | SPI3_RX: 4 6 | SPI3_TX: 5 7 | SPI4_RX: 6 8 | SPI4_TX: 7 9 | ADC1: 8 10 | ADC2: 9 11 | ADF1_FLT0: 10 12 | UART4_RX: 11 13 | UART4_TX: 12 14 | UART5_RX: 13 15 | UART5_TX: 14 16 | UART7_RX: 15 17 | UART7_TX: 16 18 | LPTIM2_IC1: 17 19 | LPTIM2_IC2: 18 20 | LPTIM2_UE: 19 21 | -------------------------------------------------------------------------------- /data/dmamux/H7_DMAMUX2.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | GENERATOR4: 5 6 | GENERATOR5: 6 7 | GENERATOR6: 7 8 | GENERATOR7: 8 9 | LPUART1_RX: 9 10 | LPUART1_TX: 10 11 | SPI6_RX: 11 12 | SPI6_TX: 12 13 | I2C4_RX: 13 14 | I2C4_TX: 14 15 | SAI4_A: 15 16 | SAI4_B: 16 17 | ADC3: 17 18 | DAC2_CH1: 17 19 | DFSDM2_FLT0: 18 20 | -------------------------------------------------------------------------------- /transforms/COMP_h.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | 3 | - !Rename 4 | from: ^(COMP)\d$ 5 | to: $1 6 | 7 | - !RenameRegisters 8 | block: COMP 9 | from: ^COMP_(.+)$ 10 | to: $1 11 | 12 | - !Rename 13 | from: ^COMP_(.+)$ 14 | to: $1 15 | 16 | - !MakeFieldArray 17 | fieldsets: ^(SR|ICFR)$ 18 | from: (C?C)\d(IF|VAL) 19 | to: $1$2 20 | -------------------------------------------------------------------------------- /data/extra/family/STM32H5.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | # Corresponds to cmosM40_opamp_v1_0_Cube 4 | # STM32H5 variant 5 | - name: OPAMP1 6 | pins: 7 | - pin: PC5 8 | signal: VINM0 9 | - pin: PB1 10 | signal: VINM1 11 | - pin: PB0 12 | signal: VINP0 13 | - pin: PA0 14 | signal: VINP2 15 | - pin: PA7 16 | signal: VOUT 17 | -------------------------------------------------------------------------------- /transforms/PWR.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(PRIV|RRSB|SEC|RADIORSB|REGPARDYVDDRFPA)$ 4 | 5 | - !MakeFieldArray 6 | fieldsets: WUSC?R 7 | from: (C?WUF)\d 8 | to: $1 9 | 10 | - !MakeFieldArray 11 | fieldsets: WUCR 12 | from: (WUPEN|WUPP(UPD)?)\d 13 | to: $1 14 | 15 | - !MakeFieldArray 16 | fieldsets: SECCFGR 17 | from: (WUP)\d(SEC) 18 | to: $1$2 19 | -------------------------------------------------------------------------------- /rust-toolchain.toml: -------------------------------------------------------------------------------- 1 | [toolchain] 2 | channel = "nightly-2025-09-26" 3 | components = [ "rust-src", "rustfmt", "llvm-tools", "miri" ] 4 | targets = [ 5 | "thumbv7em-none-eabi", 6 | "thumbv7m-none-eabi", 7 | "thumbv6m-none-eabi", 8 | "thumbv7em-none-eabihf", 9 | "thumbv8m.main-none-eabihf", 10 | "riscv32imac-unknown-none-elf", 11 | "wasm32-unknown-unknown", 12 | "armv7a-none-eabi", 13 | ] 14 | -------------------------------------------------------------------------------- /transforms/AES.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteFieldsets 3 | from: ^(DINR|DOUTR|IVR\d|KEYR\d|SUSP\dR)$ 4 | 5 | - !MakeRegisterArray 6 | blocks: AES 7 | from: ^(IVR)\d$ 8 | to: $1 9 | 10 | - !MakeRegisterArray 11 | blocks: AES 12 | allow_cursed: true 13 | from: ^(KEYR)\d$ 14 | to: $1 15 | 16 | - !MakeRegisterArray 17 | blocks: AES 18 | from: ^(SUSP)\d(R)$ 19 | to: $1$2 20 | -------------------------------------------------------------------------------- /stm32-metapac-gen/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32-metapac-gen" 3 | version = "0.1.0" 4 | edition = "2024" 5 | license = "MIT OR Apache-2.0" 6 | 7 | 8 | [dependencies] 9 | regex = "1.7.1" 10 | chiptool = { workspace = true } 11 | serde = { version = "1.0.157", features = [ "derive" ] } 12 | serde_json = "1.0.94" 13 | proc-macro2 = "1.0.52" 14 | stm32-data-macros = { version = "0.1.0", path = "../stm32-data-macros" } 15 | -------------------------------------------------------------------------------- /transforms/SAES.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteFieldsets 3 | from: ^(DINR|DOUTR|IVR\d|KEYR\d|SUSP\dR)$ 4 | 5 | - !MakeRegisterArray 6 | blocks: SAES 7 | from: ^(IVR)\d$ 8 | to: $1 9 | 10 | - !MakeRegisterArray 11 | blocks: SAES 12 | allow_cursed: true 13 | from: ^(KEYR)\d$ 14 | to: $1 15 | 16 | - !MakeRegisterArray 17 | blocks: SAES 18 | from: ^(SUSP)\d(R)$ 19 | to: $1$2 20 | -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "editor.formatOnSave": true, 3 | "[toml]": { 4 | "editor.formatOnSave": false 5 | }, 6 | "[yaml]": { 7 | "editor.formatOnSave": false 8 | }, 9 | "[c]": { 10 | "editor.formatOnSave": false 11 | }, 12 | "[cpp]": { 13 | "editor.formatOnSave": false 14 | }, 15 | "editor.rulers": [ 16 | 120 17 | ], 18 | "rust-analyzer.rustfmt.extraArgs": [ 19 | "+nightly" 20 | ], 21 | } -------------------------------------------------------------------------------- /stm32-data-serde/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32-data-serde" 3 | version = "0.1.0" 4 | edition = "2024" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | serde = { version = "1.0.157", features = ["derive"] } 10 | regex = "1.7.1" 11 | ref_thread_local = "0.1.1" 12 | 13 | [dev-dependencies] 14 | itertools = "0.10.5" 15 | rayon = "1.7.0" 16 | serde_json = "1.0.94" 17 | -------------------------------------------------------------------------------- /transforms/OPAMP.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(LOCK|OPAMP2_.*)$ 4 | 5 | - !DeleteFieldsets 6 | from: OPAMP2_.+ 7 | 8 | - !RenameRegisters 9 | block: OPAMP 10 | from: OPAMP1_(.+) 11 | to: $1 12 | 13 | - !Rename 14 | from: OPAMP1_(.+) 15 | to: $1 16 | type: All 17 | 18 | - !Rename 19 | from: ^CSR_(.+) 20 | to: $1 21 | type: All 22 | 23 | - !DeleteEnums 24 | from: ^(OPAEN|CALON)$ 25 | -------------------------------------------------------------------------------- /data/registers/vrefintcal_v2.yaml: -------------------------------------------------------------------------------- 1 | block/VREFINTCAL: 2 | description: VREFINT Factory Calibration 3 | items: 4 | - name: DATA 5 | description: Factory calibration 6 | byte_offset: 0 7 | access: Read 8 | fieldset: VREFINTCAL_DATA 9 | 10 | fieldset/VREFINTCAL_DATA: 11 | description: Factory calibration 12 | fields: 13 | - name: VREFINT_CAL 14 | description: VREFINT calibration value 15 | bit_offset: 8 16 | bit_size: 12 17 | -------------------------------------------------------------------------------- /data/extra/family/STM32U0.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | # Corresponds to tsmc018_ull_opamp_v1_0_L4_Cube, also used for U0 4 | - name: OPAMP1 5 | pins: 6 | - pin: PA0 7 | signal: VINP0 8 | - pin: PA1 9 | signal: VINM0 10 | - pin: PA3 11 | signal: VOUT 12 | - name: OPAMP2 13 | pins: 14 | - pin: PA6 15 | signal: VINP0 16 | - pin: PA7 17 | signal: VINM0 18 | - pin: PB0 19 | signal: VOUT 20 | -------------------------------------------------------------------------------- /data/extra/family/STM32U3.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | # Corresponds to tsmc018_ull_opamp_v1_0_L4_Cube, also used for U3 4 | - name: OPAMP1 5 | pins: 6 | - pin: PA0 7 | signal: VINP0 8 | - pin: PA1 9 | signal: VINM0 10 | - pin: PA3 11 | signal: VOUT 12 | - name: OPAMP2 13 | pins: 14 | - pin: PA6 15 | signal: VINP0 16 | - pin: PA7 17 | signal: VINM0 18 | - pin: PB0 19 | signal: VOUT 20 | -------------------------------------------------------------------------------- /data/extra/family/STM32U5.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | # Corresponds to tsmc018_ull_opamp_v1_0_L4_Cube, also used for U5 4 | - name: OPAMP1 5 | pins: 6 | - pin: PA0 7 | signal: VINP0 8 | - pin: PA1 9 | signal: VINM0 10 | - pin: PA3 11 | signal: VOUT 12 | - name: OPAMP2 13 | pins: 14 | - pin: PA6 15 | signal: VINP0 16 | - pin: PA7 17 | signal: VINM0 18 | - pin: PB0 19 | signal: VOUT 20 | -------------------------------------------------------------------------------- /data/extra/family/STM32L5.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | override_pins: 3 | # Corresponds to tsmc018_ull_opamp_v1_0_L4_Cube, also used for L5 4 | - name: OPAMP1 5 | pins: 6 | - pin: PA0 7 | signal: VINP0 8 | - pin: PA1 9 | signal: VINM0 10 | - pin: PA3 11 | signal: VOUT 12 | - name: OPAMP2 13 | pins: 14 | - pin: PA6 15 | signal: VINP0 16 | - pin: PA7 17 | signal: VINM0 18 | - pin: PB0 19 | signal: VOUT 20 | -------------------------------------------------------------------------------- /transforms/RTC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(CNF|REFCKON|ALRWF|INIT|TAMPALRM_PU)$ 4 | - !RenameEnumVariants 5 | enum: ^RTOFF$ 6 | from: Enabled 7 | to: Ongoing 8 | - !RenameEnumVariants 9 | enum: ^RTOFF$ 10 | from: Disabled 11 | to: Terminated 12 | - !RenameEnumVariants 13 | enum: ^ALRMR_MSK$ 14 | from: Mask 15 | to: ToMatch 16 | - !RenameEnumVariants 17 | enum: ^ALRMR_MSK$ 18 | from: NotMask 19 | to: NotMatch 20 | -------------------------------------------------------------------------------- /stm32-data-gen/src/normalize_peris.rs: -------------------------------------------------------------------------------- 1 | #[rustfmt::skip] 2 | static NORMALIZE: &[(&str, &str)] = &[ 3 | ("ADC", "ADC1"), 4 | ("DAC", "DAC1"), 5 | ("HRTIM", "HRTIM1"), 6 | ("HDMI_CEC", "CEC"), 7 | ("SUBGHZ", "SUBGHZSPI"), 8 | ("USB_DRD_FS", "USB"), 9 | ("SBS", "SYSCFG"), 10 | ("SPDIFRX", "SPDIFRX1") 11 | ]; 12 | 13 | pub fn normalize_peri_name(name: &str) -> &str { 14 | if let Some((_, res)) = NORMALIZE.iter().find(|(n, _)| *n == name) { 15 | return res; 16 | } 17 | name 18 | } 19 | -------------------------------------------------------------------------------- /transforms/DBGMCU.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !Rename 3 | from: ^DBG_(.+) 4 | to: $1 5 | - !RenameFields 6 | fieldset: .+ 7 | from: ^DBG_(.+) 8 | to: $1 9 | - !RenameRegisters 10 | block: .+ 11 | from: ^DBG_(.+) 12 | to: $1 13 | - !RenameEnumVariants 14 | enum: .+ 15 | from: ^DBG_(.+) 16 | to: $1 17 | 18 | - !MakeFieldArray 19 | fieldsets: AHB1FZR 20 | from: GPDMA(\d)_(\d{1,2})_STOP 21 | to: GPDMA${1}_STOP 22 | 23 | - !DeleteFieldsets 24 | from: AUTH_(DEVICE|HOST) 25 | -------------------------------------------------------------------------------- /data/registers/crc_v1.yaml: -------------------------------------------------------------------------------- 1 | block/CRC: 2 | description: Cyclic Redundancy Check calculation unit 3 | items: 4 | - name: DR 5 | description: Data register 6 | byte_offset: 0 7 | - name: IDR 8 | description: Independent Data register 9 | byte_offset: 4 10 | - name: CR 11 | description: Control register 12 | byte_offset: 8 13 | fieldset: CR 14 | fieldset/CR: 15 | description: Control register 16 | fields: 17 | - name: RESET 18 | description: RESET bit 19 | bit_offset: 0 20 | bit_size: 1 21 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [workspace] 2 | resolver = "2" 3 | members = [ 4 | "stm32-data-gen", 5 | "stm32-data-serde", 6 | "stm32-metapac-gen", 7 | "stm32-data-macros", 8 | ] 9 | exclude = [ 10 | "build" 11 | ] 12 | 13 | [workspace.dependencies] 14 | chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "030394157b9dd30c48c0e592a52149f501e3c3d4" } 15 | 16 | # Optimize for dev experience: shortest "build+run" time after making a small change. 17 | [profile.release] 18 | debug = true 19 | incremental = true 20 | panic = 'abort' 21 | opt-level = 2 22 | -------------------------------------------------------------------------------- /data/extra/family/STM32L4+.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | - name: VREFINTCAL 4 | address: 0x1FFF75AA 5 | registers: 6 | kind: vrefintcal 7 | version: v1 8 | block: VREFINTCAL 9 | # Corresponds to tsmc018_ull_opamp_v1_0_L4_Cube 10 | - name: OPAMP1 11 | pins: 12 | - pin: PA0 13 | signal: VINP0 14 | - pin: PA1 15 | signal: VINM0 16 | - pin: PA3 17 | signal: VOUT 18 | - name: OPAMP2 19 | pins: 20 | - pin: PA6 21 | signal: VINP0 22 | - pin: PA7 23 | signal: VINM0 24 | - pin: PB0 25 | signal: VOUT 26 | -------------------------------------------------------------------------------- /data/extra/family/STM32L4.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | - name: VREFINTCAL 4 | address: 0x1FFF75AA 5 | registers: 6 | kind: vrefintcal 7 | version: v1 8 | block: VREFINTCAL 9 | # Corresponds to tsmc018_ull_opamp_v1_0_L4_Cube 10 | - name: OPAMP1 11 | pins: 12 | - pin: PA0 13 | signal: VINP0 14 | - pin: PA1 15 | signal: VINM0 16 | - pin: PA3 17 | signal: VOUT 18 | - name: OPAMP2 19 | pins: 20 | - pin: PA6 21 | signal: VINP0 22 | - pin: PA7 23 | signal: VINM0 24 | - pin: PB0 25 | signal: VOUT 26 | -------------------------------------------------------------------------------- /transforms/GFXMMU.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !RenameRegisters 3 | block: .* 4 | from: GFXMMU_(.+) 5 | to: $1 6 | - !RenameFields 7 | fieldset: .* 8 | from: GFXMMU_(.+) 9 | to: $1 10 | - !Rename 11 | from: GFXMMU_(.+) 12 | to: $1 13 | - !DeleteEnums 14 | from: .*(IE|_EN|FI|FF|PD|OC|OB|FC|CL|CE)$ 15 | bit_size: 1 16 | - !MakeFieldArray 17 | fieldsets: .* 18 | from: ([A-Z]+)\d+([A-Z]*) 19 | to: $1$2 20 | - !MergeFieldsets 21 | from: ([A-Z]+)\d+([A-Z]*) 22 | to: $1$2 23 | - !MakeRegisterArray 24 | blocks: .* 25 | from: ([A-Z]+)\d+([A-Z]*) 26 | to: $1$2 27 | -------------------------------------------------------------------------------- /transforms/SDADC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !Rename 3 | from: ^SDADC\d$ 4 | to: SDADC 5 | 6 | - !Rename 7 | from: ^CONF0R$ 8 | to: CONFR 9 | 10 | - !MakeRegisterArray 11 | blocks: SDADC 12 | from: ^(CONF)\dR$ 13 | to: CONFR 14 | 15 | - !DeleteFieldsets 16 | from: ^CONF\dR$ 17 | 18 | - !DeleteFieldsets 19 | from: ^.*12R$ 20 | 21 | - !DeleteFieldsets 22 | from: ^.*13R$ 23 | 24 | - !MakeFieldArray 25 | fieldsets: ^CONFCHR\d$ 26 | from: ^CONFCH\d$ 27 | to: CONFCH 28 | 29 | - !RenameFields 30 | fieldset: CONFR 31 | from: ^(OFFSET|GAIN|SE|COMMON)0$ 32 | to: $1 33 | -------------------------------------------------------------------------------- /transforms/XSPI.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !Rename 3 | from: ^XSPI1$ 4 | to: XSPI 5 | type: Block 6 | 7 | - !Rename 8 | from: ^XSPI_(.+) 9 | to: $1 10 | type: All 11 | 12 | - !RenameRegisters 13 | block: XSPI 14 | from: ^XSPI_(.+)$ 15 | to: $1 16 | 17 | - !DeleteEnums 18 | from: ^(WCCR|WPCCR|TCR|WPTCR|WPDCR|CCR)_(SSHIFT|DHQC|DQSE|(AB|AD|D|I)DTR)$ 19 | 20 | - !DeleteEnums 21 | from: ^(TCIE|TCEN|SMIE|TEIE|FTIE|TOIE)?$ 22 | 23 | - !DeleteEnums 24 | from: ^(DMM|DMAEN|EN|ABORT|FRCK)?$ 25 | 26 | # prescaler is 0..255, not an enum 27 | - !DeleteEnums 28 | from: ^(PRESCALER)?$ 29 | -------------------------------------------------------------------------------- /data/dmamux/WB_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC1: 5 6 | SPI1_RX: 6 7 | SPI1_TX: 7 8 | SPI2_RX: 8 9 | SPI2_TX: 9 10 | I2C1_RX: 10 11 | I2C1_TX: 11 12 | I2C3_RX: 12 13 | I2C3_TX: 13 14 | USART1_RX: 14 15 | USART1_TX: 15 16 | LPUART1_RX: 16 17 | LPUART1_TX: 17 18 | SAI1_A: 18 19 | SAI1_B: 19 20 | QUADSPI: 20 21 | TIM1_CH1: 21 22 | TIM1_CH2: 22 23 | TIM1_CH3: 23 24 | TIM1_CH4: 24 25 | TIM1_UP: 25 26 | TIM1_TRIG: 26 27 | TIM1_COM: 27 28 | TIM2_CH1: 28 29 | TIM2_CH2: 29 30 | TIM2_CH3: 30 31 | TIM2_CH4: 31 32 | TIM2_UP: 32 33 | TIM16_CH1: 33 34 | TIM16_UP: 34 35 | TIM17_CH1: 35 36 | TIM17_UP: 36 37 | AES1_IN: 37 38 | AES1_OUT: 38 39 | AES2_IN: 39 40 | AES2_OUT: 40 41 | -------------------------------------------------------------------------------- /.github/ci/doc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## on push branch=main 3 | ## priority -100 4 | ## dedup dequeue 5 | ## cooldown 15m 6 | 7 | set -euo pipefail 8 | 9 | export RUSTUP_HOME=/ci/cache/rustup 10 | export CARGO_HOME=/ci/cache/cargo 11 | export CARGO_TARGET_DIR=/ci/cache/target 12 | export BUILDER_THREADS=6 13 | export BUILDER_COMPRESS=true 14 | 15 | hashtime restore /ci/cache/filetime.json || true 16 | hashtime save /ci/cache/filetime.json 17 | 18 | ./d ci 19 | 20 | docserver build -i ./build/stm32-metapac -o crates/stm32-metapac/git.zup 21 | 22 | export KUBECONFIG=/ci/secrets/kubeconfig.yml 23 | POD=$(kubectl -n embassy get po -l app=docserver -o jsonpath={.items[0].metadata.name}) 24 | kubectl cp crates $POD:/data 25 | -------------------------------------------------------------------------------- /data/dmamux/WL_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC: 5 6 | DAC_OUT1: 6 7 | SPI1_RX: 7 8 | SPI1_TX: 8 9 | SPI2_RX: 9 10 | SPI2_TX: 10 11 | I2C1_RX: 11 12 | I2C1_TX: 12 13 | I2C2_RX: 13 14 | I2C2_TX: 14 15 | I2C3_RX: 15 16 | I2C3_TX: 16 17 | USART1_RX: 17 18 | USART1_TX: 18 19 | USART2_RX: 19 20 | USART2_TX: 20 21 | LPUART1_RX: 21 22 | LPUART1_TX: 22 23 | TIM1_CH1: 23 24 | TIM1_CH2: 24 25 | TIM1_CH3: 25 26 | TIM1_CH4: 26 27 | TIM1_UP: 27 28 | TIM1_TRIG: 28 29 | TIM1_COM: 29 30 | TIM2_CH1: 30 31 | TIM2_CH2: 31 32 | TIM2_CH3: 32 33 | TIM2_CH4: 33 34 | TIM2_UP: 34 35 | TIM16_CH1: 35 36 | TIM16_UP: 36 37 | TIM17_CH1: 37 38 | TIM17_UP: 38 39 | AES_IN: 39 40 | AES_OUT: 40 41 | SUBGHZSPI_RX: 41 42 | SUBGHZSPI_TX: 42 43 | -------------------------------------------------------------------------------- /transforms/OTFDEC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !Rename 3 | from: ^(OTFDEC)\d$ 4 | to: $1 5 | 6 | - !DeleteFieldsets 7 | from: ^R\d(STARTADDR|ENDADDR|NONCER0|NONCER1|KEYR0|KEYR1|KEYR2|KEYR3)$ 8 | 9 | - !MergeFieldsets 10 | from: ^(R)\d(CFGR)$ 11 | to: ${1}egion$2 12 | 13 | - !MakeBlock 14 | blocks: ^OTFDEC$ 15 | from: ^R(\d)(.+)$ 16 | to_outer: Region${1} 17 | to_block: Region 18 | to_inner: ${2} 19 | 20 | - !MakeRegisterArray 21 | blocks: ^Region$ 22 | from: ^(NONCER|KEYR)\d$ 23 | to: $1 24 | 25 | - !MakeRegisterArray 26 | blocks: ^OTFDEC$ 27 | from: ^(Region)\d$ 28 | to: $1 29 | 30 | - !RenameFields 31 | fieldset: ^RegionCFGR$ 32 | from: (REG)x(_VERSION) 33 | to: $1$2 34 | -------------------------------------------------------------------------------- /transforms/USB_OTG.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | # OTG_FS_HOST 3 | - !ModifyByteOffset 4 | block: OTG_FS_HOST 5 | add_offset: 0x400 6 | - !MergeFieldsets 7 | from: (HCINT|HCCHAR|HCINTMSK|HCTSIZ)\d 8 | to: $1 9 | - !MakeRegisterArray 10 | blocks: .* 11 | from: (HCINT|HCCHAR|HCINTMSK|HCTSIZ)\d 12 | to: $1 13 | # OTG_FS_DEVICE 14 | - !ModifyByteOffset 15 | block: OTG_FS_DEVICE 16 | add_offset: 0x800 17 | # Excluding endpoint 0, it has special registers. 18 | - !MergeFieldsets 19 | from: (DIEPCTL|D[IO]EPINT|D[IO]EPTSIZ|DTXFSTS)[1-9] 20 | to: $1 21 | - !MakeRegisterArray 22 | blocks: .* 23 | from: (DIEPCTL|D[IO]EPINT|D[IO]EPTSIZ|DTXFSTS)[1-9] 24 | to: $1 25 | - !ModifyByteOffset 26 | block: OTG_FS_PWRCLK 27 | add_offset: 0xE00 28 | -------------------------------------------------------------------------------- /stm32-data-gen/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "stm32-data-gen" 3 | version = "0.1.0" 4 | edition = "2024" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [features] 9 | default = ["rayon"] 10 | rayon = ["dep:rayon"] 11 | 12 | [dependencies] 13 | anyhow = "1.0.79" 14 | glob = "0.3.1" 15 | num = "0.4.0" 16 | quick-xml = { version = "0.26.0", features = ["serialize"] } 17 | regex = "1.7.1" 18 | serde = { version = "1.0.157", features = ["derive"] } 19 | serde_yaml = "=0.9.34-deprecated" 20 | chiptool = { workspace = true } 21 | serde_json = "1.0.94" 22 | rayon = { version = "1.7.0", optional = true } 23 | stm32-data-serde = { version = "0.1.0", path = "../stm32-data-serde" } 24 | ref_thread_local = "0.1.1" 25 | log = "0.4.17" 26 | pretty_env_logger = "0.4.0" 27 | clap = { version = "4.0", features = ["derive"] } 28 | -------------------------------------------------------------------------------- /data/dmamux/C0_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC1: 5 6 | I2C1_RX: 10 7 | I2C1_TX: 11 8 | I2C2_RX: 12 9 | I2C2_TX: 13 10 | SPI1_RX: 16 11 | SPI1_TX: 17 12 | SPI2_RX: 18 13 | SPI2_TX: 19 14 | TIM1_CH1: 20 15 | TIM1_CH2: 21 16 | TIM1_CH3: 22 17 | TIM1_CH4: 23 18 | TIM1_TRIG_COM: 24 19 | TIM1_UP: 25 20 | TIM2_CH1: 26 21 | TIM2_CH2: 27 22 | TIM2_CH3: 28 23 | TIM2_CH4: 29 24 | TIM2_TRIG: 30 25 | TIM2_UP: 31 26 | TIM3_CH1: 32 27 | TIM3_CH2: 33 28 | TIM3_CH3: 34 29 | TIM3_CH4: 35 30 | TIM3_TRIG: 36 31 | TIM3_UP: 37 32 | TIM15_CH1: 40 33 | TIM15_CH2: 41 34 | TIM15_COM: 42 35 | TIM15_UP: 43 36 | TIM16_CH1: 44 37 | TIM16_COM: 45 38 | TIM16_UP: 46 39 | TIM17_CH1: 47 40 | TIM17_COM: 48 41 | TIM17_UP: 49 42 | USART1_RX: 50 43 | USART1_TX: 51 44 | USART2_RX: 52 45 | USART2_TX: 53 46 | USART3_RX: 54 47 | USART3_TX: 55 48 | USART4_RX: 56 49 | USART4_TX: 57 50 | -------------------------------------------------------------------------------- /stm32-data-gen/src/check.rs: -------------------------------------------------------------------------------- 1 | use std::collections::HashMap; 2 | use std::hash::Hash; 3 | 4 | use stm32_data_serde::Chip; 5 | 6 | pub fn check(chip: &Chip) { 7 | for core in &chip.cores { 8 | let peris = mapify(&core.peripherals, |p| &p.name); 9 | for ch in &core.dma_channels { 10 | let dma = peris.get(&ch.dma).unwrap(); 11 | let signal = ch.name.strip_prefix(&format!("{}_", dma.name)).unwrap(); 12 | if !dma.interrupts.iter().any(|i| i.signal == signal) { 13 | panic!("{}: missing irq for ch {}", chip.name, ch.name); 14 | } 15 | } 16 | } 17 | } 18 | 19 | fn mapify(iter: impl IntoIterator, f: impl Fn(&V) -> K) -> HashMap { 20 | let mut res = HashMap::new(); 21 | for v in iter { 22 | let k = f(&v); 23 | res.insert(k, v); 24 | } 25 | res 26 | } 27 | -------------------------------------------------------------------------------- /data/registers/fdcanram_v1.yaml: -------------------------------------------------------------------------------- 1 | block/FDCANRAM: 2 | description: FDCAN Message RAM 3 | items: 4 | - name: FLSSA 5 | description: 11-bit filter 6 | array: 7 | len: 28 8 | stride: 4 9 | byte_offset: 0 10 | - name: FLESA 11 | description: 29-bit filter 12 | array: 13 | len: 16 14 | stride: 4 15 | byte_offset: 112 16 | - name: RXFIFO0 17 | description: Rx FIFO 0 18 | array: 19 | len: 54 20 | stride: 4 21 | byte_offset: 176 22 | - name: RXFIFO1 23 | description: Rx FIFO 1 24 | array: 25 | len: 54 26 | stride: 4 27 | byte_offset: 392 28 | - name: TXEFIFO 29 | description: Tx event FIFO 30 | array: 31 | len: 6 32 | stride: 4 33 | byte_offset: 608 34 | - name: TXBUF 35 | description: Tx buffer 36 | array: 37 | len: 54 38 | stride: 4 39 | byte_offset: 632 40 | -------------------------------------------------------------------------------- /transforms/SAI.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !MergeEnums 3 | from: ^[AB](.*) 4 | to: $1 5 | - !Rename 6 | from: ^(.+?)_(.+) 7 | to: $2 8 | 9 | - !DeleteEnums 10 | from: ^(C?A?FSDET(IE)?|CCNRDY(IE)?|CNRDYIE|C?OVRUDR|CWCKCFG(IE)?|WCKCFGIE|DMAEN|FFLUSH|FREQ(IE)?|C?LFSDET(IE)?|MUTE|C?MUTEDET(IE)?|OVRUDR(IE)?|SAIEN)$ 11 | bit_size: 1 12 | 13 | - !MergeFieldsets 14 | from: ^[AB](.*) 15 | to: $1 16 | 17 | - !MakeFieldArray 18 | fieldsets: PDMCR 19 | from: CKEN\d 20 | to: CKEN 21 | 22 | - !MakeFieldArray 23 | fieldsets: PDMDLY 24 | from: DLYM\d(L|R) 25 | to: DLYM$1 26 | 27 | - !MakeBlock 28 | blocks: SAI\d 29 | from: ^(A|B)(.+) 30 | to_outer: $1 31 | to_inner: $2 32 | to_block: CH 33 | 34 | - !MakeRegisterArray 35 | blocks: SAI\d 36 | from: ^(A|B)$ 37 | to: CH 38 | 39 | - !Rename 40 | from: ^SAI\d$ 41 | to: SAI 42 | -------------------------------------------------------------------------------- /data/extra/family/STM32H7.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | pin_cleanup: 3 | # H7 has some _C pin variants (e.g. PC2 and PC2_C). Digital stuff should always be in the non-C pin. 4 | # cubedb puts it either in both, or in the -C pin only! (in chips where the package has only the -C pin) 5 | # so we fix that up here. 6 | strip_suffix: "_C" 7 | exclude_peripherals: 8 | - ADC 9 | - DAC 10 | - COMP 11 | 12 | peripherals: 13 | # Corresponds to cmosM40_opamp_v1_0_Cube 14 | # STM32H7 variant 15 | - name: OPAMP1 16 | pins: 17 | - pin: PC5 18 | signal: VINM0 19 | - pin: PA7 20 | signal: VINM1 21 | - pin: PB0 22 | signal: VINP0 23 | - pin: PC4 24 | signal: VOUT 25 | - name: OPAMP2 26 | pins: 27 | - pin: PE8 28 | signal: VINM0 29 | - pin: PG1 30 | signal: VINM1 31 | - pin: PE9 32 | signal: VINP0 33 | - pin: PE7 34 | signal: VOUT 35 | -------------------------------------------------------------------------------- /transforms/ADC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !Rename 3 | from: ^ADC1$ 4 | to: ADC 5 | 6 | - !DeleteEnums 7 | from: ^(AWD1?|J?EOC|JEOS|J?STRT|OVR|ADRDY|EOS(MP)?|JQOVF|ENDED)(_MST)?$ 8 | 9 | - !MakeFieldArray 10 | fieldsets: ^(IER|ISR)$ 11 | from: AWD\d(IE)? 12 | to: AWD$1 13 | 14 | - !MakeFieldArray 15 | fieldsets: ^(CFGR)$ 16 | from: EXTSEL\d 17 | to: EXTSEL 18 | 19 | - !MakeFieldArray 20 | fieldsets: SMPR\d 21 | from: SMP\d+ 22 | to: SMP 23 | 24 | - !MakeFieldArray 25 | fieldsets: JSQR 26 | from: JSQ\d 27 | to: JSQ 28 | 29 | - !MergeFieldsets 30 | from: OFR\d 31 | to: OFR 32 | 33 | - !MakeRegisterArray 34 | blocks: ADC 35 | from: OFR\d 36 | to: OFR 37 | 38 | - !MergeFieldsets 39 | from: JDR\d 40 | to: JDR 41 | 42 | - !MakeRegisterArray 43 | blocks: ADC 44 | from: JDR\d 45 | to: JDR 46 | 47 | - !MakeFieldArray 48 | fieldsets: ^SQR\d$ 49 | from: SQ\d+ 50 | to: SQ 51 | -------------------------------------------------------------------------------- /stm32-metapac-gen/src/main.rs: -------------------------------------------------------------------------------- 1 | use std::env::args; 2 | use std::path::PathBuf; 3 | 4 | use stm32_metapac_gen::*; 5 | 6 | fn main() { 7 | let out_dir = PathBuf::from("build/stm32-metapac"); 8 | let data_dir = PathBuf::from("build/data"); 9 | 10 | let args: Vec = args().collect(); 11 | 12 | let mut chips = match &args[..] { 13 | [_, chip] => { 14 | vec![chip.clone()] 15 | } 16 | [_] => std::fs::read_dir(data_dir.join("chips")) 17 | .unwrap() 18 | .filter_map(|res| res.unwrap().file_name().to_str().map(|s| s.to_string())) 19 | .filter(|s| s.ends_with(".json")) 20 | .map(|s| s.strip_suffix(".json").unwrap().to_string()) 21 | .collect(), 22 | _ => panic!("usage: stm32-metapac-gen [chip?]"), 23 | }; 24 | 25 | chips.sort(); 26 | 27 | let opts = Options { 28 | out_dir, 29 | data_dir, 30 | chips, 31 | }; 32 | Gen::new(opts).run_gen(); 33 | } 34 | -------------------------------------------------------------------------------- /transforms/SYSCFG_F3.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !MakeFieldArray 3 | fieldsets: RCR 4 | from: PAGE\d+_WP 5 | to: PAGE_WP 6 | - !MakeFieldArray 7 | fieldsets: CFGR1 8 | from: FPU_IE\d 9 | to: FPU_IE 10 | 11 | - !DeleteEnums 12 | from: ADC2_DMA_RMP_CFGR1 13 | bit_size: 1 14 | keep_desc: true 15 | 16 | - !DeleteEnums 17 | from: (DAC1_TRIG5_RMP|DAC1_TRIG_RMP|DAC2_CH1_DMA_RMP|DAC_TRIG_RMP) 18 | bit_size: 1 19 | keep_desc: true 20 | 21 | - !DeleteEnums 22 | from: (TIM16_DMA_RMP|TIM17_DMA_RMP|TIM18_DAC2_OUT1_DMA_RMP|TIM1_ITR3_RMP|TIM6_DAC1_CH1_DMA_RMP|TIM6_DAC1_DMA_RMP|TIM6_DAC1_OUT1_DMA_RMP|TIM7_DAC1_CH2_DMA_RMP|TIM7_DAC1_OUT2_DMA_RMP) 23 | bit_size: 1 24 | keep_desc: true 25 | 26 | - !DeleteEnums 27 | from: USB_IT_RMP 28 | bit_size: 1 29 | keep_desc: true 30 | 31 | - !MergeEnums 32 | from: .*_FMP 33 | to: FMP 34 | keep_desc: true 35 | 36 | - !DeleteEnums 37 | from: ^(BYP_ADDR_PAR|LOCKUP_LOCK|PVD_LOCK|SRAM_PARITY_LOCK)$ 38 | -------------------------------------------------------------------------------- /transforms/EXTI.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !MergeEnums 3 | from: CCMR\d_Input_CC\dS 4 | to: CCMR_Input_CCS 5 | check: Layout 6 | 7 | # Remove digits from enum names 8 | - !MergeEnums 9 | from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]* 10 | to: $1$2$3 11 | skip_unmergeable: true 12 | 13 | - !DeleteEnums 14 | from: ^(PRIV|SEC)$ 15 | 16 | - !MakeFieldArray 17 | fieldsets: .* 18 | from: ([A-Z]+)\d+ 19 | to: $1 20 | allow_cursed: true 21 | - !MakeFieldArray 22 | fieldsets: .* 23 | from: P\d+WP 24 | to: PWP 25 | # - !MakeRegisterArray 26 | # blocks: .* 27 | # from: ([A-Z]+)\d+ 28 | # to: $1 29 | - !MakeRegisterArray 30 | blocks: .* 31 | from: EXTICR\d+ 32 | to: EXTICR 33 | - !MergeEnums 34 | from: "[HL](IFCR|ISR)_(.*)" 35 | to: $2 36 | - !MergeFieldsets 37 | from: "[HL](IFCR|ISR)" 38 | to: $1 39 | - !MergeFieldsets 40 | from: EXTICR\d 41 | to: EXTICR 42 | - !MakeRegisterArray 43 | blocks: .* 44 | from: "[HL](IFCR|ISR)" 45 | to: $1 46 | -------------------------------------------------------------------------------- /stm32-metapac-gen/res/src/lib.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![allow(non_snake_case)] 3 | #![allow(unused)] 4 | #![allow(non_camel_case_types)] 5 | #![doc(html_no_source)] 6 | #![cfg_attr( 7 | docsrs, 8 | doc = "

You might want to browse the `stm32-metapac` documentation on the Embassy website instead.

The documentation here on `docs.rs` is built for a single chip only (stm32h755zi-cm7 in particular), while on the Embassy website you can pick your exact chip from the top menu. Available peripherals and their APIs change depending on the chip.

\n\n" 9 | )] 10 | #![doc = include_str!("../README.md")] 11 | 12 | pub mod common; 13 | 14 | #[cfg(feature = "pac")] 15 | include!(env!("STM32_METAPAC_PAC_PATH")); 16 | 17 | #[cfg(feature = "metadata")] 18 | pub mod metadata { 19 | include!("metadata.rs"); 20 | include!(env!("STM32_METAPAC_METADATA_PATH")); 21 | include!("all_chips.rs"); 22 | include!("all_peripheral_versions.rs"); 23 | } 24 | -------------------------------------------------------------------------------- /data/registers/xspim_v1.yaml: -------------------------------------------------------------------------------- 1 | block/XSPIM: 2 | description: XSPIM1 register block. 3 | items: 4 | - name: CR 5 | description: XSPIM control register. 6 | byte_offset: 0 7 | fieldset: CR 8 | fieldset/CR: 9 | description: XSPIM control register. 10 | fields: 11 | - name: MUXEN 12 | description: Multiplexed mode enable This bit enables the multiplexing of the two XSPIs. 13 | bit_offset: 0 14 | bit_size: 1 15 | - name: MODE 16 | description: XSPI multiplexing mode. 17 | bit_offset: 1 18 | bit_size: 1 19 | - name: CSSEL_OVR_EN 20 | description: Chip select selector override enable. 21 | bit_offset: 4 22 | bit_size: 1 23 | - name: CSSEL_OVR_O1 24 | description: Chip select selector override setting for XSPI1. 25 | bit_offset: 5 26 | bit_size: 1 27 | - name: CSSEL_OVR_O2 28 | description: Chip select selector override setting for XSPI2. 29 | bit_offset: 6 30 | bit_size: 1 31 | - name: REQ2ACK_TIME 32 | description: REQ to ACK time In Multiplexed mode (MUXEN = 1), this field defines the time between two transactions. 33 | bit_offset: 16 34 | bit_size: 8 35 | -------------------------------------------------------------------------------- /transforms/LPTIM_v2.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | 3 | - !Rename 4 | from: ^LPTIM1$ 5 | to: LPTIM_Adv 6 | 7 | - !RenameRegisters 8 | block: LPTIM_Adv 9 | from: (.*)intput 10 | to: ${1}input 11 | 12 | - !Rename 13 | from: (.*)intput 14 | to: ${1}input 15 | 16 | - !MakeBlock 17 | blocks: ^LPTIM_Adv$ 18 | from: ^(.+)_output$ 19 | to_outer: Output 20 | to_block: Output 21 | to_inner: ${1} 22 | 23 | - !MakeBlock 24 | blocks: ^LPTIM_Adv$ 25 | from: ^(.+)_input$ 26 | to_outer: Input 27 | to_block: Input 28 | to_inner: ${1} 29 | 30 | - !RenameFields 31 | fieldset: CCR\d 32 | from: CCR\d 33 | to: CCR 34 | 35 | - !MergeFieldsets 36 | from: CCR\d 37 | to: CCR 38 | 39 | - !MakeRegisterArray 40 | blocks: LPTIM_Adv 41 | from: CCR\d 42 | to: CCR 43 | 44 | - !MakeFieldArray 45 | fieldsets: CFGR2 46 | from: (I[CN])\d(SEL) 47 | to: $1$2 48 | 49 | - !MakeFieldArray 50 | fieldsets: CCMR\d 51 | from: (.*)\d(.*) 52 | to: $1$2 53 | 54 | - !MakeFieldArray 55 | fieldsets: (ISR|ICR|DIER).* 56 | from: (.*)\d(.*) 57 | to: $1$2 58 | -------------------------------------------------------------------------------- /data/dmamux/WBA_GPDMA1.yaml: -------------------------------------------------------------------------------- 1 | ADC4: 0 2 | SPI1_RX: 1 3 | SPI1_TX: 2 4 | SPI3_RX: 3 5 | SPI3_TX: 4 6 | I2C1_RX: 5 7 | I2C1_TX: 6 8 | I2C1_EVC: 7 9 | I2C3_RX: 8 10 | I2C3_TX: 9 11 | I2C3_EVC: 10 12 | USART1_RX: 11 13 | USART1_TX: 12 14 | USART2_RX: 13 15 | USART2_TX: 14 16 | LPUART1_RX: 15 17 | LPUART1_TX: 16 18 | SAI1_A: 17 19 | SAI1_B: 18 20 | TIM1_CH1: 19 21 | TIM1_CH2: 20 22 | TIM1_CH3: 21 23 | TIM1_CH4: 22 24 | TIM1_UP: 23 25 | TIM1_TRG: 24 26 | TIM1_COM: 25 27 | TIM2_CH1: 26 28 | TIM2_CH2: 27 29 | TIM2_CH3: 28 30 | TIM2_CH4: 29 31 | TIM2_UP: 30 32 | TIM3_CH1: 31 33 | TIM3_CH2: 32 34 | TIM3_CH3: 33 35 | TIM3_CH4: 34 36 | TIM3_UP: 35 37 | TIM3_TRG: 36 38 | TIM16_CC1: 37 39 | TIM16_UP: 38 40 | TIM17_CC1: 39 41 | TIM17_UP: 40 42 | AES_IN: 41 43 | AES_OUT: 42 44 | HASH_IN: 43 45 | SAES_IN: 44 46 | SAES_OUT: 45 47 | LPTIM1_IC1: 46 48 | LPTIM1_IC2: 47 49 | LPTIM1_UE: 48 50 | LPTIM2_IC1: 49 51 | LPTIM2_IC2: 50 52 | LPTIM2_UE: 51 53 | SPI2_RX: 52 54 | SPI2_TX: 53 55 | I2C2_RX: 54 56 | I2C2_TX: 55 57 | I2C2_EVC: 56 58 | I2C4_RX: 57 59 | I2C4_TX: 58 60 | I2C4_EVC: 59 61 | TIM4_CH1: 60 62 | TIM4_CH2: 61 63 | TIM4_CH3: 62 64 | TIM4_CH4: 63 65 | TIM4_UP: 64 66 | USART3_RX: 65 67 | USART3_TX: 66 68 | -------------------------------------------------------------------------------- /transforms/ETH.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(DC|GU|MPE|PAM|PM|RA|RFCE|ROR|SAF|TFCE|UPFD|WFE|CSTF|EDFE|MACAHR_AE|MCF|AAB)$ 4 | - !RenameEnumVariants 5 | enum: ^CSR$ 6 | from: Disabled 7 | to: Rollover 8 | - !RenameEnumVariants 9 | enum: ^CSR$ 10 | from: Enabled 11 | to: NotRollover 12 | 13 | - !MakeFieldArray 14 | fieldsets: ^MACACR$ 15 | from: ATSEN\d 16 | to: ATSEN 17 | 18 | # merge MAC Address 1/2/3 high/low register 19 | - !RenameFields 20 | fieldset: .* 21 | from: MACA[1-3]([HL]) 22 | to: MACA$1 23 | - !MergeFieldsets 24 | from: MACA[1-3]HR 25 | to: MACAHR 26 | - !MergeFieldsets 27 | from: MACA[1-3]LR 28 | to: MACALR 29 | - !MakeRegisterArray 30 | blocks: .* 31 | from: MACA[1-3]HR 32 | to: MACAHR 33 | - !MakeRegisterArray 34 | blocks: .* 35 | from: MACA[1-3]LR 36 | to: MACALR 37 | 38 | # merge Hash Table 0/1 register 39 | - !RenameFields 40 | fieldset: MACHT\dR 41 | from: HT.+ 42 | to: HT 43 | - !MergeFieldsets 44 | from: MACHT\dR 45 | to: MACHTR 46 | - !MakeRegisterArray 47 | blocks: ^ETHERNET_MAC$ 48 | from: MACHT\dR 49 | to: MACHTR 50 | -------------------------------------------------------------------------------- /transforms/FMC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteFieldsets 3 | from: ^ECCR$ 4 | 5 | - !MergeFieldsets 6 | from: ^(BCR)[2-4]$ 7 | to: $1 8 | 9 | - !MergeFieldsets 10 | from: ^(BTR|BWTR|SDCR|SDTR)\d+$ 11 | to: $1 12 | 13 | - !MakeRegisterArray 14 | blocks: FMC 15 | from: ^(BCR)[2-4]$ 16 | to: $1 17 | 18 | - !MakeRegisterArray 19 | blocks: FMC 20 | from: ^(BTR|BWTR|SDCR|SDTR)\d+$ 21 | to: $1 22 | 23 | - !MakeBlock 24 | blocks: FMC 25 | from: ^(BCR\d*|BW?TR\d*|PCSCNTR)$ 26 | to_outer: NOR_PSRAM 27 | to_block: NOR_PSRAM 28 | to_inner: $1 29 | 30 | - !MakeBlock 31 | blocks: FMC 32 | from: ^(PCR|SR|PMEM|PATT|ECCR)$ 33 | to_outer: NAND 34 | to_block: NAND 35 | to_inner: $1 36 | 37 | - !MakeBlock 38 | blocks: FMC 39 | from: ^(SDCR\d*|SDTR\d*|SDCMR|SDRTR|SDSR)$ 40 | to_outer: SDRAM 41 | to_block: SDRAM 42 | to_inner: $1 43 | 44 | - !MakeFieldArray 45 | fieldsets: ^PCSCNTR$ 46 | from: CNTB\dEN 47 | to: CNTBEN 48 | 49 | - !MakeFieldArray 50 | fieldsets: ^SDCMR$ 51 | from: CTB\d 52 | to: CTB 53 | 54 | - !MakeFieldArray 55 | fieldsets: ^SDSR$ 56 | from: MODES\d 57 | to: MODES 58 | -------------------------------------------------------------------------------- /.github/ci/generated.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## on push branch=main 3 | ## permission contents write 4 | ## permission_repo stm32-data-generated 5 | 6 | set -euxo pipefail 7 | 8 | export RUSTUP_HOME=/ci/cache/rustup 9 | export CARGO_HOME=/ci/cache/cargo 10 | export CARGO_TARGET_DIR=/ci/cache/target 11 | 12 | hashtime restore /ci/cache/filetime.json || true 13 | hashtime save /ci/cache/filetime.json 14 | 15 | git clone --depth 1 https://github.com/embassy-rs/stm32-data-generated/ build -q 16 | ./d ci 17 | 18 | # Generate peripheral summary and update README.md 19 | cat > build/README.md << 'EOF' 20 | # stm32-data generated output 21 | 22 | This repo contains generated output for [`stm32-data`](https://github.com/embassy-rs/stm32-data). It is updated for every push to the `main` branch. See the `stm32-data` README for more details. 23 | 24 | ## STM32 Peripheral Support Matrix 25 | 26 | The following table shows which STM32 peripheral versions are supported across different families: 27 | 28 | EOF 29 | cargo run --release --bin summary >> build/README.md 30 | 31 | COMMIT=$(git rev-parse HEAD) 32 | cd build 33 | git add data stm32-metapac README.md 34 | git commit -m "Generated from stm32-data $COMMIT" --allow-empty 35 | git tag -a stm32-data-$COMMIT -m "Generated from stm32-data $COMMIT" 36 | git push --follow-tags 37 | -------------------------------------------------------------------------------- /data/registers/exti_h7.yaml: -------------------------------------------------------------------------------- 1 | block/EXTI: 2 | description: External interrupt/event controller 3 | items: 4 | - name: RTSR 5 | description: Rising Trigger selection register 6 | array: 7 | len: 1 8 | stride: 0 9 | byte_offset: 0 10 | fieldset: LINES 11 | - name: FTSR 12 | description: Falling Trigger selection register 13 | array: 14 | len: 1 15 | stride: 0 16 | byte_offset: 4 17 | fieldset: LINES 18 | - name: SWIER 19 | description: Software interrupt event register 20 | array: 21 | len: 1 22 | stride: 0 23 | byte_offset: 8 24 | fieldset: LINES 25 | - name: IMR 26 | description: Interrupt mask register 27 | array: 28 | len: 1 29 | stride: 0 30 | byte_offset: 128 31 | fieldset: LINES 32 | - name: EMR 33 | description: Event mask register 34 | array: 35 | len: 1 36 | stride: 0 37 | byte_offset: 132 38 | fieldset: LINES 39 | - name: PR 40 | description: Pending register 41 | array: 42 | len: 1 43 | stride: 0 44 | byte_offset: 136 45 | fieldset: LINES 46 | fieldset/LINES: 47 | description: EXTI lines register, 1 bit per line 48 | fields: 49 | - name: LINE 50 | description: EXTI line 51 | bit_offset: 0 52 | bit_size: 1 53 | array: 54 | len: 32 55 | stride: 1 56 | -------------------------------------------------------------------------------- /data/registers/exti_wle.yaml: -------------------------------------------------------------------------------- 1 | block/EXTI: 2 | description: External interrupt/event controller 3 | items: 4 | - name: RTSR 5 | description: Rising Trigger selection register 6 | array: 7 | len: 2 8 | stride: 32 9 | byte_offset: 0 10 | fieldset: LINES 11 | - name: FTSR 12 | description: Falling Trigger selection register 13 | array: 14 | len: 2 15 | stride: 32 16 | byte_offset: 4 17 | fieldset: LINES 18 | - name: SWIER 19 | description: Software interrupt event register 20 | array: 21 | len: 2 22 | stride: 32 23 | byte_offset: 8 24 | fieldset: LINES 25 | - name: PR 26 | description: Pending register 27 | array: 28 | len: 2 29 | stride: 32 30 | byte_offset: 12 31 | fieldset: LINES 32 | - name: IMR 33 | description: Interrupt mask register 34 | array: 35 | len: 2 36 | stride: 16 37 | byte_offset: 128 38 | fieldset: LINES 39 | - name: EMR 40 | description: Event mask register 41 | array: 42 | len: 2 43 | stride: 16 44 | byte_offset: 132 45 | fieldset: LINES 46 | fieldset/LINES: 47 | description: EXTI lines register, 1 bit per line 48 | fields: 49 | - name: LINE 50 | description: EXTI line 51 | bit_offset: 0 52 | bit_size: 1 53 | array: 54 | len: 32 55 | stride: 1 56 | -------------------------------------------------------------------------------- /data/registers/exti_v1.yaml: -------------------------------------------------------------------------------- 1 | block/EXTI: 2 | description: External interrupt/event controller 3 | items: 4 | - name: IMR 5 | description: Interrupt mask register 6 | array: 7 | len: 2 8 | stride: 32 9 | byte_offset: 0 10 | fieldset: LINES 11 | - name: EMR 12 | description: Interrupt mask register 13 | array: 14 | len: 2 15 | stride: 32 16 | byte_offset: 4 17 | fieldset: LINES 18 | - name: RTSR 19 | description: Rising Trigger selection register 20 | array: 21 | len: 2 22 | stride: 32 23 | byte_offset: 8 24 | fieldset: LINES 25 | - name: FTSR 26 | description: Falling Trigger selection register 27 | array: 28 | len: 2 29 | stride: 32 30 | byte_offset: 12 31 | fieldset: LINES 32 | - name: SWIER 33 | description: Software interrupt event register 34 | array: 35 | len: 2 36 | stride: 32 37 | byte_offset: 16 38 | fieldset: LINES 39 | - name: PR 40 | description: Pending register 41 | array: 42 | len: 2 43 | stride: 32 44 | byte_offset: 20 45 | fieldset: LINES 46 | fieldset/LINES: 47 | description: EXTI lines register, 1 bit per line 48 | fields: 49 | - name: LINE 50 | description: EXTI line 51 | bit_offset: 0 52 | bit_size: 1 53 | array: 54 | len: 32 55 | stride: 1 56 | -------------------------------------------------------------------------------- /data/registers/rng_v1.yaml: -------------------------------------------------------------------------------- 1 | block/RNG: 2 | description: Random number generator 3 | items: 4 | - name: CR 5 | description: control register 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: SR 9 | description: status register 10 | byte_offset: 4 11 | fieldset: SR 12 | - name: DR 13 | description: data register 14 | byte_offset: 8 15 | access: Read 16 | fieldset/CR: 17 | description: control register 18 | fields: 19 | - name: RNGEN 20 | description: Random number generator enable 21 | bit_offset: 2 22 | bit_size: 1 23 | - name: IE 24 | description: Interrupt enable 25 | bit_offset: 3 26 | bit_size: 1 27 | - name: CED 28 | description: Clock error detection 29 | bit_offset: 5 30 | bit_size: 1 31 | fieldset/SR: 32 | description: status register 33 | fields: 34 | - name: DRDY 35 | description: Data ready 36 | bit_offset: 0 37 | bit_size: 1 38 | - name: CECS 39 | description: Clock error current status 40 | bit_offset: 1 41 | bit_size: 1 42 | - name: SECS 43 | description: Seed error current status 44 | bit_offset: 2 45 | bit_size: 1 46 | - name: CEIS 47 | description: Clock error interrupt status 48 | bit_offset: 5 49 | bit_size: 1 50 | - name: SEIS 51 | description: Seed error interrupt status 52 | bit_offset: 6 53 | bit_size: 1 54 | -------------------------------------------------------------------------------- /data/registers/syscfg_l1.yaml: -------------------------------------------------------------------------------- 1 | block/SYSCFG: 2 | description: System configuration controller 3 | items: 4 | - name: MEMRMP 5 | description: memory remap register 6 | byte_offset: 0 7 | fieldset: MEMRMP 8 | - name: PMC 9 | description: peripheral mode configuration register 10 | byte_offset: 4 11 | fieldset: PMC 12 | - name: EXTICR 13 | description: external interrupt configuration register 1 14 | array: 15 | len: 4 16 | stride: 4 17 | byte_offset: 8 18 | fieldset: EXTICR 19 | fieldset/EXTICR: 20 | description: external interrupt configuration register 3 21 | fields: 22 | - name: EXTI 23 | description: EXTI x configuration (x = 8 to 11) 24 | bit_offset: 0 25 | bit_size: 4 26 | array: 27 | len: 4 28 | stride: 4 29 | fieldset/MEMRMP: 30 | description: memory remap register 31 | fields: 32 | - name: MEM_MODE 33 | description: MEM_MODE 34 | bit_offset: 0 35 | bit_size: 2 36 | - name: BOOT_MODE 37 | description: BOOT_MODE 38 | bit_offset: 8 39 | bit_size: 2 40 | fieldset/PMC: 41 | description: peripheral mode configuration register 42 | fields: 43 | - name: USB_PU 44 | description: USB pull-up 45 | bit_offset: 0 46 | bit_size: 1 47 | - name: LCD_CAPA 48 | description: USB pull-up enable on DP line 49 | bit_offset: 1 50 | bit_size: 5 51 | -------------------------------------------------------------------------------- /data/dmamux/G0_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC1: 5 6 | AES_IN: 6 7 | AES_OUT: 7 8 | DAC1_CH1: 8 9 | DAC1_CH2: 9 10 | I2C1_RX: 10 11 | I2C1_TX: 11 12 | I2C2_RX: 12 13 | I2C2_TX: 13 14 | LPUART1_RX: 14 15 | LPUART1_TX: 15 16 | SPI1_RX: 16 17 | SPI1_TX: 17 18 | SPI2_RX: 18 19 | SPI2_TX: 19 20 | TIM1_CH1: 20 21 | TIM1_CH2: 21 22 | TIM1_CH3: 22 23 | TIM1_CH4: 23 24 | TIM1_TRIG_COM: 24 25 | TIM1_UP: 25 26 | TIM2_CH1: 26 27 | TIM2_CH2: 27 28 | TIM2_CH3: 28 29 | TIM2_CH4: 29 30 | TIM2_TRIG: 30 31 | TIM2_UP: 31 32 | TIM3_CH1: 32 33 | TIM3_CH2: 33 34 | TIM3_CH3: 34 35 | TIM3_CH4: 35 36 | TIM3_TRIG: 36 37 | TIM3_UP: 37 38 | TIM6_UP: 38 39 | TIM7_UP: 39 40 | TIM15_CH1: 40 41 | TIM15_CH2: 41 42 | TIM15_TRIG_COM: 42 43 | TIM15_UP: 43 44 | TIM16_CH1: 44 45 | TIM16_COM: 45 46 | TIM16_UP: 46 47 | TIM17_CH1: 47 48 | TIM17_COM: 48 49 | TIM17_UP: 49 50 | USART1_RX: 50 51 | USART1_TX: 51 52 | USART2_RX: 52 53 | USART2_TX: 53 54 | USART3_RX: 54 55 | USART3_TX: 55 56 | USART4_RX: 56 57 | USART4_TX: 57 58 | UCPD1_RX: 58 59 | UCPD1_TX: 59 60 | UCPD2_RX: 60 61 | UCPD2_TX: 61 62 | I2C3_RX: 62 63 | I2C3_TX: 63 64 | LPUART2_RX: 64 65 | LPUART2_TX: 65 66 | SPI3_RX: 66 67 | SPI3_TX: 67 68 | TIM4_CH1: 68 69 | TIM4_CH2: 69 70 | TIM4_CH3: 70 71 | TIM4_CH4: 71 72 | TIM4_TRIG: 72 73 | TIM4_UP: 73 74 | USART5_RX: 74 75 | USART5_TX: 75 76 | USART6_RX: 76 77 | USART6_TX: 77 78 | -------------------------------------------------------------------------------- /data/dmamux/U0_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC1: 5 6 | AES_IN: 6 7 | AES_OUT: 7 8 | DAC1_CH1: 8 9 | I2C1_RX: 9 10 | I2C1_TX: 10 11 | I2C2_RX: 11 12 | I2C2_TX: 12 13 | I2C3_RX: 13 14 | I2C3_TX: 14 15 | I2C4_RX: 15 16 | I2C4_TX: 16 17 | LPTIM1_IC1: 17 18 | LPTIM1_IC2: 18 19 | LPTIM1_IC3: 19 20 | LPTIM1_IC4: 20 21 | LPTIM1_UE4: 21 22 | LPTIM2_IC1: 22 23 | LPTIM2_IC2: 23 24 | LPTIM2_UE: 24 25 | LPTIM3_IC1: 25 26 | LPTIM3_IC2: 26 27 | LPTIM3_IC3: 27 28 | LPTIM3_IC4: 28 29 | LPTIM3_UE: 29 30 | LPUART1_RX: 30 31 | LPUART1_TX: 31 32 | LPUART2_RX: 32 33 | LPUART2_TX: 33 34 | LPUART3_RX: 34 35 | LPUART3_TX: 35 36 | SPI1_RX: 36 37 | SPI1_TX: 37 38 | SPI2_RX: 38 39 | SPI2_TX: 39 40 | SPI3_RX: 40 41 | SPI3_TX: 41 42 | TIM1_CH1: 42 43 | TIM1_CH2: 43 44 | TIM1_CH3: 44 45 | TIM1_CH4: 45 46 | TIM1_TRIG_COM: 46 47 | TIM1_UP: 47 48 | TIM2_CH1: 48 49 | TIM2_CH2: 49 50 | TIM2_CH3: 50 51 | TIM2_CH4: 51 52 | TIM2_TRIG: 52 53 | TIM2_UP: 53 54 | TIM3_CH1: 54 55 | TIM3_CH2: 55 56 | TIM3_CH3: 56 57 | TIM3_CH4: 57 58 | TIM3_TRIG: 58 59 | TIM3_UP: 59 60 | TIM6_UP: 60 61 | TIM7_UP: 61 62 | TIM15_CH1: 62 63 | TIM15_CH2: 63 64 | TIM15_TRIG_COM: 64 65 | TIM15_UP: 65 66 | TIM16_CH1: 66 67 | TIM16_COM: 67 68 | TIM16_UP: 68 69 | USART1_RX: 69 70 | USART1_TX: 70 71 | USART2_RX: 71 72 | USART2_TX: 72 73 | USART3_RX: 73 74 | USART3_TX: 74 75 | USART4_RX: 75 76 | USART4_TX: 76 -------------------------------------------------------------------------------- /transforms/I3C.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | ### Start of making DataRegs block ### 3 | 4 | # Make a DataRegs block that contain DR and DWR register, 5 | # then let Tx and Rx use that block 6 | 7 | # Eliminate Field name difference between Tx and Rx 8 | - !RenameFields 9 | fieldset: ^[RT]DR$ 10 | from: (R|T)(DB)\d 11 | to: $2 12 | - !MakeFieldArray 13 | fieldsets: ^[RT]DWR$ 14 | from: (R|T)(DB)\d 15 | to: $2 16 | 17 | # Make Tx and Rx register use same DR and DWR fieldsets 18 | # We can't tell whether Tx or Rx registers left after previous transforms, so we match both T and R for safe. 19 | - !MergeFieldsets 20 | from: ^[TR](DW?R)$ 21 | to: $1 22 | 23 | # Extract DR and DWR into DataRegs, left T and R as prefix 24 | - !MakeBlock 25 | blocks: ^I3C$ 26 | from: ^(R|T)(DW?R)$ 27 | to_outer: ${1}DataRegs 28 | to_block: DataRegs 29 | to_inner: ${2} 30 | 31 | # Expand single letter T and R to Tx and Rx, make it more readable 32 | - !RenameRegisters 33 | block: I3C 34 | from: (T|R)(DataRegs) 35 | to: ${1}x${2} 36 | 37 | ### End of making DataRegs block ### 38 | 39 | - !MakeFieldArray 40 | fieldsets: IBIDR 41 | from: ^(IBIDB)\d$ 42 | to: $1 43 | 44 | - !MergeFieldsets 45 | from: ^(DEVR)[1-4]$ 46 | to: $1 47 | 48 | - !MakeRegisterArray 49 | blocks: I3C 50 | from: ^(DEVR)[1-4]$ 51 | to: $1 52 | 53 | - !RenameFields 54 | fieldset: ^MAX[RW]LR$ 55 | from: ^M[RW]L$ 56 | to: ML 57 | -------------------------------------------------------------------------------- /stm32-metapac-gen/res/README.md: -------------------------------------------------------------------------------- 1 | # stm32-metapac 2 | 3 | This is a [Peripheral Access Crate](https://rust-embedded.github.io/book/start/registers.html) for STMicroelectronics STM32 microcontrollers. 4 | 5 | This crate has been automatically generated based on data in the [`stm32-data` project](https://github.com/embassy-rs/stm32-data), and is used for the [`embassy-stm32`](github.com/embassy-rs/embassy/) Rust Hardware Abstraction Layer (HAL) for the STM32 microcontrollers. 6 | 7 | ## Metadata 8 | 9 | This PAC additionally exports "metadata" about the chips. To use it, enable the `metadata` feature and access it at `stm32_metapac::METADATA`. It is intended to be consumed from `build.rs` scripts or code-generation tools running on PCs, not from the firmware itself. 10 | 11 | The metadata includes the following info: 12 | 13 | - Memory maps for RAM, flash. 14 | - Interrupts 15 | - GPIO Alternate Function mappings 16 | - Interrupt -> peripheral mappings 17 | - DMA channel -> peripehral mappings 18 | - RCC clock tree information for each peripheral (what clocks does it receive, which RCC registers to poke to enable, reset, or choose the clock) 19 | 20 | ## Supported chips 21 | 22 | This PAC aims to support all STM32 chip families: 23 | 24 | - STM32F0 25 | - STM32F1 26 | - STM32F2 27 | - STM32F3 28 | - STM32F4 29 | - STM32F7 30 | - STM32C0 31 | - STM32G0 32 | - STM32G4 33 | - STM32H5 34 | - STM32H7 35 | - STM32H7RS 36 | - STM32L0 37 | - STM32L1 38 | - STM32L4 39 | - STM32L5 40 | - STM32U0 41 | - STM32U5 42 | - STM32WB 43 | - STM32WBA 44 | - STM32WL 45 | -------------------------------------------------------------------------------- /data/dmamux/U3_GPDMA1.yaml: -------------------------------------------------------------------------------- 1 | ADC1: 0 2 | ADC2: 1 3 | DAC1: 2 4 | DAC2: 3 5 | TIM6_UP: 4 6 | TIM7_UP: 5 7 | SPI1_RX: 6 8 | SPI1_TX: 7 9 | SPI2_RX: 8 10 | SPI2_TX: 9 11 | SPI3_RX: 10 12 | SPI3_TX: 11 13 | I2C1_RX: 12 14 | I2C1_TX: 13 15 | I2C1_EVC: 14 16 | I2C2_RX: 15 17 | I2C2_TX: 16 18 | I2C2_EVC: 17 19 | I2C3_RX: 18 20 | I2C3_TX: 19 21 | I2C3_EVC: 20 22 | USART1_RX: 24 23 | USART1_TX: 25 24 | USART3_RX: 28 25 | USART3_TX: 29 26 | UART4_RX: 30 27 | UART4_TX: 31 28 | UART5_RX: 32 29 | UART5_TX: 33 30 | LPUART1_RX: 34 31 | LPUART1_TX: 35 32 | SAI1_A: 36 33 | SAI1_B: 37 34 | OCTOSPI1: 40 35 | TIM1_CH1: 42 36 | TIM1_CH2: 43 37 | TIM1_CH3: 44 38 | TIM1_CH4: 45 39 | TIM1_UP: 46 40 | TIM1_TRG: 47 41 | TIM1_COM: 48 42 | I3C1_RX: 49 43 | I3C1_TX: 50 44 | I3C1_TC: 51 45 | I3C1_RS: 52 46 | TIM2_CH1: 56 47 | TIM2_CH2: 57 48 | TIM2_CH3: 58 49 | TIM2_CH4: 59 50 | TIM2_UP: 60 51 | TIM3_CH1: 61 52 | TIM3_CH2: 62 53 | TIM3_CH3: 63 54 | TIM3_CH4: 64 55 | TIM3_UP: 65 56 | TIM3_TRG: 66 57 | TIM4_CH1: 67 58 | TIM4_CH2: 68 59 | TIM4_CH3: 69 60 | TIM4_CH4: 70 61 | TIM4_UP: 71 62 | I3C2_RX: 72 63 | I3C2_TX: 73 64 | I3C2_TC: 74 65 | I3C2_RS: 75 66 | TIM15_CC1: 78 67 | TIM15_UP: 79 68 | TIM15_TRG: 80 69 | TIM15_COM: 81 70 | TIM16_CC1: 82 71 | TIM16_UP: 83 72 | TIM17_CC1: 84 73 | TIM17_UP: 85 74 | AES_IN: 87 75 | AES_OUT: 88 76 | HASH_IN: 89 77 | ADF1_FLT0: 98 78 | SAES_IN: 103 79 | SAES_OUT: 104 80 | LPTIM1_IC1: 105 81 | LPTIM1_IC2: 106 82 | LPTIM1_UE: 107 83 | LPTIM2_IC1: 108 84 | LPTIM2_IC2: 109 85 | LPTIM2_UE: 110 86 | LPTIM3_IC1: 111 87 | LPTIM3_IC2: 112 88 | LPTIM3_UE: 113 89 | HSPI1: 114 90 | -------------------------------------------------------------------------------- /data/registers/vrefbuf_v1.yaml: -------------------------------------------------------------------------------- 1 | block/VREFBUF: 2 | description: Voltage reference buffer. 3 | items: 4 | - name: CSR 5 | description: control and status register. 6 | byte_offset: 0 7 | fieldset: CSR 8 | - name: CCR 9 | description: calibration control register. 10 | byte_offset: 4 11 | fieldset: CCR 12 | fieldset/CCR: 13 | description: calibration control register. 14 | fields: 15 | - name: TRIM 16 | description: Trimming code. 17 | bit_offset: 0 18 | bit_size: 6 19 | fieldset/CSR: 20 | description: control and status register. 21 | fields: 22 | - name: ENVR 23 | description: Voltage reference buffer mode enable. 24 | bit_offset: 0 25 | bit_size: 1 26 | - name: HIZ 27 | description: High impedance mode. 28 | bit_offset: 1 29 | bit_size: 1 30 | enum: HIZ 31 | - name: VRS 32 | description: Voltage reference scale. 33 | bit_offset: 2 34 | bit_size: 1 35 | enum: VRS 36 | - name: VRR 37 | description: Voltage reference buffer ready. 38 | bit_offset: 3 39 | bit_size: 1 40 | enum/HIZ: 41 | bit_size: 1 42 | variants: 43 | - name: Connected 44 | description: VREF+ pin is internally connected to the voltage reference buffer output. 45 | value: 0 46 | - name: HighZ 47 | description: VREF+ pin is high impedance. 48 | value: 1 49 | enum/VRS: 50 | bit_size: 1 51 | variants: 52 | - name: Vref0 53 | description: Voltage reference set to around 2.048 V. 54 | value: 0 55 | - name: Vref1 56 | description: Voltage reference set to around 2.5 V. 57 | value: 1 58 | -------------------------------------------------------------------------------- /data/registers/exti_w.yaml: -------------------------------------------------------------------------------- 1 | block/CPU: 2 | description: CPU-specific registers 3 | items: 4 | - name: IMR 5 | description: CPU x interrupt mask register 6 | array: 7 | len: 2 8 | stride: 16 9 | byte_offset: 0 10 | fieldset: LINES 11 | - name: EMR 12 | description: CPU x event mask register 13 | array: 14 | len: 2 15 | stride: 16 16 | byte_offset: 4 17 | fieldset: LINES 18 | block/EXTI: 19 | description: External interrupt/event controller 20 | items: 21 | - name: RTSR 22 | description: rising trigger selection register 23 | array: 24 | len: 2 25 | stride: 32 26 | byte_offset: 0 27 | fieldset: LINES 28 | - name: FTSR 29 | description: falling trigger selection register 30 | array: 31 | len: 2 32 | stride: 32 33 | byte_offset: 4 34 | fieldset: LINES 35 | - name: SWIER 36 | description: software interrupt event register 37 | array: 38 | len: 2 39 | stride: 32 40 | byte_offset: 8 41 | fieldset: LINES 42 | - name: PR 43 | description: EXTI pending register 44 | array: 45 | len: 2 46 | stride: 32 47 | byte_offset: 12 48 | fieldset: LINES 49 | - name: CPU 50 | description: CPU specific registers 51 | array: 52 | len: 2 53 | stride: 64 54 | byte_offset: 128 55 | block: CPU 56 | fieldset/LINES: 57 | description: EXTI lines register, 1 bit per line 58 | fields: 59 | - name: LINE 60 | description: EXTI line 61 | bit_offset: 0 62 | bit_size: 1 63 | array: 64 | len: 32 65 | stride: 1 66 | -------------------------------------------------------------------------------- /data/dmamux/L4PQ_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC1: 5 6 | ADC2: 6 7 | DAC1_CH1: 7 8 | DAC1_CH2: 8 9 | TIM6_UP: 9 10 | TIM7_UP: 10 11 | SPI1_RX: 11 12 | SPI1_TX: 12 13 | SPI2_RX: 13 14 | SPI2_TX: 14 15 | SPI3_RX: 15 16 | SPI3_TX: 16 17 | I2C1_RX: 17 18 | I2C1_TX: 18 19 | I2C2_RX: 19 20 | I2C2_TX: 20 21 | I2C3_RX: 21 22 | I2C3_TX: 22 23 | I2C4_RX: 23 24 | I2C4_TX: 24 25 | USART1_RX: 25 26 | USART1_TX: 26 27 | USART2_RX: 27 28 | USART2_TX: 28 29 | USART3_RX: 29 30 | USART3_TX: 30 31 | UART4_RX: 31 32 | UART4_TX: 32 33 | UART5_RX: 33 34 | UART5_TX: 34 35 | LPUART1_RX: 35 36 | LPUART1_TX: 36 37 | SAI1_A: 37 38 | SAI1_B: 38 39 | SAI2_A: 39 40 | SAI2_B: 40 41 | OCTOSPI1: 41 42 | OCTOSPI2: 42 43 | TIM1_CH1: 43 44 | TIM1_CH2: 44 45 | TIM1_CH3: 45 46 | TIM1_CH4: 46 47 | TIM1_UP: 47 48 | TIM1_TRIG: 48 49 | TIM1_COM: 49 50 | TIM8_CH1: 50 51 | TIM8_CH2: 51 52 | TIM8_CH3: 52 53 | TIM8_CH4: 53 54 | TIM8_UP: 54 55 | TIM8_TRIG: 55 56 | TIM8_COM: 56 57 | TIM2_CH1: 57 58 | TIM2_CH2: 58 59 | TIM2_CH3: 59 60 | TIM2_CH4: 60 61 | TIM2_UP: 61 62 | TIM3_CH1: 62 63 | TIM3_CH2: 63 64 | TIM3_CH3: 64 65 | TIM3_CH4: 65 66 | TIM3_UP: 66 67 | TIM3_TRIG: 67 68 | TIM4_CH1: 68 69 | TIM4_CH2: 69 70 | TIM4_CH3: 70 71 | TIM4_CH4: 71 72 | TIM4_UP: 72 73 | TIM5_CH1: 73 74 | TIM5_CH2: 74 75 | TIM5_CH3: 75 76 | TIM5_CH4: 76 77 | TIM5_UP: 77 78 | TIM5_TRIG: 78 79 | TIM15_CH1: 79 80 | TIM15_UP: 80 81 | TIM15_TRIG: 81 82 | TIM15_COM: 82 83 | TIM16_CH1: 83 84 | TIM16_UP: 84 85 | TIM17_CH1: 85 86 | TIM17_UP: 86 87 | DFSDM1_FLT0: 87 88 | DFSDM1_FLT1: 88 89 | DCMI_PSSI: 91 90 | AES_IN: 92 91 | AES_OUT: 93 92 | HASH_IN: 94 93 | -------------------------------------------------------------------------------- /data/registers/pwr_f0x0.yaml: -------------------------------------------------------------------------------- 1 | block/PWR: 2 | description: Power control 3 | items: 4 | - name: CR 5 | description: power control register 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: CSR 9 | description: power control/status register 10 | byte_offset: 4 11 | fieldset: CSR 12 | fieldset/CR: 13 | description: power control register 14 | fields: 15 | - name: LPDS 16 | description: Low-power deep sleep 17 | bit_offset: 0 18 | bit_size: 1 19 | - name: PDDS 20 | description: Power down deepsleep 21 | bit_offset: 1 22 | bit_size: 1 23 | enum: PDDS 24 | - name: CWUF 25 | description: Clear wakeup flag 26 | bit_offset: 2 27 | bit_size: 1 28 | - name: CSBF 29 | description: Clear standby flag 30 | bit_offset: 3 31 | bit_size: 1 32 | - name: DBP 33 | description: Disable backup domain write protection 34 | bit_offset: 8 35 | bit_size: 1 36 | fieldset/CSR: 37 | description: power control/status register 38 | fields: 39 | - name: WUF 40 | description: Wakeup flag 41 | bit_offset: 0 42 | bit_size: 1 43 | - name: SBF 44 | description: Standby flag 45 | bit_offset: 1 46 | bit_size: 1 47 | - name: EWUP 48 | description: Enable WKUP pin 1 49 | bit_offset: 8 50 | bit_size: 1 51 | array: 52 | len: 8 53 | stride: 1 54 | enum/PDDS: 55 | bit_size: 1 56 | variants: 57 | - name: STOP_MODE 58 | description: Enter Stop mode when the CPU enters deepsleep 59 | value: 0 60 | - name: STANDBY_MODE 61 | description: Enter Standby mode when the CPU enters deepsleep 62 | value: 1 63 | -------------------------------------------------------------------------------- /data/dmamux/L4RS_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC1: 5 6 | DAC1_CH1: 6 7 | DAC1_CH2: 7 8 | TIM6_UP: 8 9 | TIM7_UP: 9 10 | SPI1_RX: 10 11 | SPI1_TX: 11 12 | SPI2_RX: 12 13 | SPI2_TX: 13 14 | SPI3_RX: 14 15 | SPI3_TX: 15 16 | I2C1_RX: 16 17 | I2C1_TX: 17 18 | I2C2_RX: 18 19 | I2C2_TX: 19 20 | I2C3_RX: 20 21 | I2C3_TX: 21 22 | I2C4_RX: 22 23 | I2C4_TX: 23 24 | USART1_RX: 24 25 | USART1_TX: 25 26 | USART2_RX: 26 27 | USART2_TX: 27 28 | USART3_RX: 28 29 | USART3_TX: 29 30 | UART4_RX: 30 31 | UART4_TX: 31 32 | UART5_RX: 32 33 | UART5_TX: 33 34 | LPUART1_RX: 34 35 | LPUART1_TX: 35 36 | SAI1_A: 36 37 | SAI1_B: 37 38 | SAI2_A: 38 39 | SAI2_B: 39 40 | OCTOSPI1: 40 41 | OCTOSPI2: 41 42 | TIM1_CH1: 42 43 | TIM1_CH2: 43 44 | TIM1_CH3: 44 45 | TIM1_CH4: 45 46 | TIM1_UP: 46 47 | TIM1_TRIG: 47 48 | TIM1_COM: 48 49 | TIM8_CH1: 49 50 | TIM8_CH2: 50 51 | TIM8_CH3: 51 52 | TIM8_CH4: 52 53 | TIM8_UP: 53 54 | TIM8_TRIG: 54 55 | TIM8_COM: 55 56 | TIM2_CH1: 56 57 | TIM2_CH2: 57 58 | TIM2_CH3: 58 59 | TIM2_CH4: 59 60 | TIM2_UP: 60 61 | TIM3_CH1: 61 62 | TIM3_CH2: 62 63 | TIM3_CH3: 63 64 | TIM3_CH4: 64 65 | TIM3_UP: 65 66 | TIM3_TRIG: 66 67 | TIM4_CH1: 67 68 | TIM4_CH2: 68 69 | TIM4_CH3: 69 70 | TIM4_CH4: 70 71 | TIM4_UP: 71 72 | TIM5_CH1: 72 73 | TIM5_CH2: 73 74 | TIM5_CH3: 74 75 | TIM5_CH4: 75 76 | TIM5_UP: 76 77 | TIM5_TRIG: 77 78 | TIM15_CH1: 78 79 | TIM15_UP: 79 80 | TIM15_TRIG: 80 81 | TIM15_COM: 81 82 | TIM16_CH1: 82 83 | TIM16_UP: 83 84 | TIM17_CH1: 84 85 | TIM17_UP: 85 86 | DFSDM1_FLT0: 86 87 | DFSDM1_FLT1: 87 88 | DFSDM1_FLT2: 88 89 | DFSDM1_FLT3: 89 90 | DCMI_PSSI: 90 91 | AES_IN: 91 92 | AES_OUT: 92 93 | HASH_IN: 93 -------------------------------------------------------------------------------- /data/dmamux/L5_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC1: 5 6 | ADC2: 6 7 | DAC1_CH1: 7 8 | DAC1_CH2: 8 9 | TIM6_UP: 9 10 | TIM7_UP: 10 11 | SPI1_RX: 11 12 | SPI1_TX: 12 13 | SPI2_RX: 13 14 | SPI2_TX: 14 15 | SPI3_RX: 15 16 | SPI3_TX: 16 17 | I2C1_RX: 17 18 | I2C1_TX: 18 19 | I2C2_RX: 19 20 | I2C2_TX: 20 21 | I2C3_RX: 21 22 | I2C3_TX: 22 23 | I2C4_RX: 23 24 | I2C4_TX: 24 25 | USART1_RX: 25 26 | USART1_TX: 26 27 | USART2_RX: 27 28 | USART2_TX: 28 29 | USART3_RX: 29 30 | USART3_TX: 30 31 | UART4_RX: 31 32 | UART4_TX: 32 33 | UART5_RX: 33 34 | UART5_TX: 34 35 | LPUART1_RX: 35 36 | LPUART1_TX: 36 37 | SAI1_A: 37 38 | SAI1_B: 38 39 | SAI2_A: 39 40 | SAI2_B: 40 41 | OCTOSPI1: 41 42 | TIM1_CH1: 42 43 | TIM1_CH2: 43 44 | TIM1_CH3: 44 45 | TIM1_CH4: 45 46 | TIM1_UP: 46 47 | TIM1_TRIG: 47 48 | TIM1_COM: 48 49 | TIM8_CH1: 49 50 | TIM8_CH2: 50 51 | TIM8_CH3: 51 52 | TIM8_CH4: 52 53 | TIM8_UP: 53 54 | TIM8_TRIG: 54 55 | TIM8_COM: 55 56 | TIM2_CH1: 56 57 | TIM2_CH2: 57 58 | TIM2_CH3: 58 59 | TIM2_CH4: 59 60 | TIM2_UP: 60 61 | TIM3_CH1: 61 62 | TIM3_CH2: 62 63 | TIM3_CH3: 63 64 | TIM3_CH4: 64 65 | TIM3_UP: 65 66 | TIM3_TRIG: 66 67 | TIM4_CH1: 67 68 | TIM4_CH2: 68 69 | TIM4_CH3: 69 70 | TIM4_CH4: 70 71 | TIM4_UP: 71 72 | TIM5_CH1: 72 73 | TIM5_CH2: 73 74 | TIM5_CH3: 74 75 | TIM5_CH4: 75 76 | TIM5_UP: 76 77 | TIM5_TRIG: 77 78 | TIM15_CH1: 78 79 | TIM15_UP: 79 80 | TIM15_TRIG: 80 81 | TIM15_COM: 81 82 | TIM16_CH1: 82 83 | TIM16_UP: 83 84 | TIM17_CH1: 84 85 | TIM17_UP: 85 86 | DFSDM1_FLT0: 86 87 | DFSDM1_FLT1: 87 88 | DFSDM1_FLT2: 88 89 | DFSDM1_FLT3: 89 90 | AES_IN: 90 91 | AES_OUT: 91 92 | HASH_IN: 92 93 | UCPD1_TX: 93 94 | UCPD1_RX: 94 95 | -------------------------------------------------------------------------------- /data/registers/wwdg_v1.yaml: -------------------------------------------------------------------------------- 1 | block/WWDG: 2 | description: Window watchdog 3 | items: 4 | - name: CR 5 | description: Control register 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: CFR 9 | description: Configuration register 10 | byte_offset: 4 11 | fieldset: CFR 12 | - name: SR 13 | description: Status register 14 | byte_offset: 8 15 | fieldset: SR 16 | fieldset/CFR: 17 | description: Configuration register 18 | fields: 19 | - name: W 20 | description: 7-bit window value 21 | bit_offset: 0 22 | bit_size: 7 23 | - name: WDGTB 24 | description: Timer base 25 | bit_offset: 7 26 | bit_size: 2 27 | enum: WDGTB 28 | - name: EWI 29 | description: Early wakeup interrupt 30 | bit_offset: 9 31 | bit_size: 1 32 | fieldset/CR: 33 | description: Control register 34 | fields: 35 | - name: T 36 | description: 7-bit counter (MSB to LSB) 37 | bit_offset: 0 38 | bit_size: 7 39 | - name: WDGA 40 | description: Watchdog activated 41 | bit_offset: 7 42 | bit_size: 1 43 | fieldset/SR: 44 | description: Status register 45 | fields: 46 | - name: EWIF 47 | description: Early wakeup interrupt flag 48 | bit_offset: 0 49 | bit_size: 1 50 | enum/WDGTB: 51 | bit_size: 2 52 | variants: 53 | - name: Div1 54 | description: Counter clock (PCLK1 div 4096) div 1 55 | value: 0 56 | - name: Div2 57 | description: Counter clock (PCLK1 div 4096) div 2 58 | value: 1 59 | - name: Div4 60 | description: Counter clock (PCLK1 div 4096) div 4 61 | value: 2 62 | - name: Div8 63 | description: Counter clock (PCLK1 div 4096) div 8 64 | value: 3 65 | -------------------------------------------------------------------------------- /stm32-data-macros/src/lib.rs: -------------------------------------------------------------------------------- 1 | use proc_macro2::TokenStream; 2 | use quote::quote; 3 | use syn::Data; 4 | 5 | #[proc_macro_derive(EnumDebug)] 6 | pub fn enum_derive(input: proc_macro::TokenStream) -> proc_macro::TokenStream { 7 | let ast = syn::parse(input).unwrap(); 8 | 9 | impl_enum_derive(&ast).into() 10 | } 11 | 12 | fn impl_enum_derive(ast: &syn::DeriveInput) -> TokenStream { 13 | let name = &ast.ident; 14 | let enumm = match &ast.data { 15 | Data::Enum(e) => e, 16 | _ => unreachable!(), 17 | }; 18 | 19 | let match_variants: TokenStream = enumm 20 | .variants 21 | .iter() 22 | .map(|v| { 23 | let variant_name = &v.ident; 24 | let variant_debug = format!("{}::{}", name, variant_name); 25 | 26 | match v.fields.len() { 27 | 0 => quote! { 28 | #name::#variant_name => ::core::fmt::Formatter::write_str(f, #variant_debug), 29 | }, 30 | 1 => quote! { 31 | #name::#variant_name(__self_0) => ::core::fmt::Formatter::debug_tuple(f, #variant_debug) 32 | .field(&__self_0) 33 | .finish(), 34 | }, 35 | _ => unimplemented!(), 36 | } 37 | }) 38 | .collect(); 39 | 40 | quote! { 41 | #[automatically_derived] 42 | impl ::core::fmt::Debug for #name { 43 | fn fmt(self: &Self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result { 44 | match self { 45 | #match_variants 46 | } 47 | } 48 | } 49 | } 50 | } 51 | -------------------------------------------------------------------------------- /data/registers/vrefbuf_v2b.yaml: -------------------------------------------------------------------------------- 1 | block/VREFBUF: 2 | description: Voltage reference buffer. 3 | items: 4 | - name: CSR 5 | description: VREFBUF Control and Status Register. 6 | byte_offset: 0 7 | fieldset: CSR 8 | - name: CCR 9 | description: VREFBUF Calibration Control Register. 10 | byte_offset: 4 11 | fieldset: CCR 12 | fieldset/CCR: 13 | description: VREFBUF Calibration Control Register. 14 | fields: 15 | - name: TRIM 16 | description: Trimming code. 17 | bit_offset: 0 18 | bit_size: 6 19 | fieldset/CSR: 20 | description: VREFBUF Control and Status Register. 21 | fields: 22 | - name: ENVR 23 | description: Enable Voltage Reference. 24 | bit_offset: 0 25 | bit_size: 1 26 | - name: HIZ 27 | description: High impedence mode for the VREFBUF. 28 | bit_offset: 1 29 | bit_size: 1 30 | enum: HIZ 31 | - name: VRR 32 | description: Voltage reference buffer ready. 33 | bit_offset: 3 34 | bit_size: 1 35 | - name: VRS 36 | description: Voltage reference scale. 37 | bit_offset: 4 38 | bit_size: 2 39 | enum: VRS 40 | enum/HIZ: 41 | bit_size: 1 42 | variants: 43 | - name: Connected 44 | description: VREF+ pin is internally connected to the voltage reference buffer output. 45 | value: 0 46 | - name: HighZ 47 | description: VREF+ pin is high impedance. 48 | value: 1 49 | enum/VRS: 50 | bit_size: 2 51 | variants: 52 | - name: Vref0 53 | description: Voltage reference set to around 2.048 V. 54 | value: 0 55 | - name: Vref1 56 | description: Voltage reference set to around 2.5 V. 57 | value: 1 58 | - name: Vref2 59 | description: Voltage reference set to around 2.9 V. 60 | value: 2 61 | -------------------------------------------------------------------------------- /data/extra/family/STM32F3.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | peripherals: 3 | - name: VREFINTCAL 4 | address: 0x1FFFF7BA 5 | registers: 6 | kind: vrefintcal 7 | version: v1 8 | block: VREFINTCAL 9 | - name: OPAMP1 10 | pins: 11 | # Corresponds to tsmc018_ull_opamp_v1_0_Cube 12 | - pin: PA1 13 | signal: VINP0 14 | - pin: PA7 15 | signal: VINP1 16 | - pin: PA3 17 | signal: VINP2 18 | - pin: PA5 19 | signal: VINP3 20 | - pin: PC5 21 | signal: VINM0 22 | - pin: PA3 23 | signal: VINM1 24 | - pin: PA2 25 | signal: VOUT 26 | - name: OPAMP2 27 | pins: 28 | - pin: PA7 29 | signal: VINP0 30 | - pin: PD14 31 | signal: VINP1 32 | - pin: PB0 33 | signal: VINP2 34 | - pin: PB14 35 | signal: VINP3 36 | - pin: PC5 37 | signal: VINM0 38 | - pin: PA5 39 | signal: VINM1 40 | - pin: PA6 41 | signal: VOUT 42 | - name: OPAMP3 43 | pins: 44 | - pin: PB0 45 | signal: VINP0 46 | - pin: PB13 47 | signal: VINP1 48 | - pin: PA1 49 | signal: VINP2 50 | - pin: PA5 51 | signal: VINP3 52 | - pin: PB10 53 | signal: VINM0 54 | - pin: PB2 55 | signal: VINM1 56 | - pin: PB1 57 | signal: VOUT 58 | - name: OPAMP4 59 | pins: 60 | - pin: PB13 61 | signal: VINP0 62 | - pin: PD11 63 | signal: VINP1 64 | - pin: PA4 65 | signal: VINP2 66 | - pin: PB11 67 | signal: VINP3 68 | - pin: PB10 69 | signal: VINM0 70 | - pin: PD8 71 | signal: VINM1 72 | - pin: PB12 73 | signal: VOUT 74 | -------------------------------------------------------------------------------- /data/registers/adccommon_c0.yaml: -------------------------------------------------------------------------------- 1 | block/ADC_COMMON: 2 | description: ADC common registers 3 | items: 4 | - name: CCR 5 | description: common configuration register 6 | byte_offset: 8 7 | fieldset: CCR 8 | fieldset/CCR: 9 | description: common configuration register 10 | fields: 11 | - name: PRESC 12 | description: prescaler 13 | bit_offset: 18 14 | bit_size: 4 15 | enum: PRESC 16 | - name: VREFEN 17 | description: VREFINT enable 18 | bit_offset: 22 19 | bit_size: 1 20 | - name: TSEN 21 | description: Temperature sensor enable 22 | bit_offset: 23 23 | bit_size: 1 24 | enum/PRESC: 25 | bit_size: 4 26 | variants: 27 | - name: Div1 28 | description: adc_ker_ck_input not divided 29 | value: 0 30 | - name: Div2 31 | description: adc_ker_ck_input divided by 2 32 | value: 1 33 | - name: Div4 34 | description: adc_ker_ck_input divided by 4 35 | value: 2 36 | - name: Div6 37 | description: adc_ker_ck_input divided by 6 38 | value: 3 39 | - name: Div8 40 | description: adc_ker_ck_input divided by 8 41 | value: 4 42 | - name: Div10 43 | description: adc_ker_ck_input divided by 10 44 | value: 5 45 | - name: Div12 46 | description: adc_ker_ck_input divided by 12 47 | value: 6 48 | - name: Div16 49 | description: adc_ker_ck_input divided by 16 50 | value: 7 51 | - name: Div32 52 | description: adc_ker_ck_input divided by 32 53 | value: 8 54 | - name: Div64 55 | description: adc_ker_ck_input divided by 64 56 | value: 9 57 | - name: Div128 58 | description: adc_ker_ck_input divided by 128 59 | value: 10 60 | - name: Div256 61 | description: adc_ker_ck_input divided by 256 62 | value: 11 -------------------------------------------------------------------------------- /stm32-metapac-gen/res/build.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | #[cfg(feature = "rt")] 3 | use std::path::PathBuf; 4 | 5 | enum GetOneError { 6 | None, 7 | Multiple, 8 | } 9 | 10 | trait IteratorExt: Iterator { 11 | fn get_one(self) -> Result; 12 | } 13 | 14 | impl IteratorExt for T { 15 | fn get_one(mut self) -> Result { 16 | match self.next() { 17 | None => Err(GetOneError::None), 18 | Some(res) => match self.next() { 19 | Some(_) => Err(GetOneError::Multiple), 20 | None => Ok(res), 21 | }, 22 | } 23 | } 24 | } 25 | 26 | fn main() { 27 | #[cfg(feature = "rt")] 28 | let crate_dir = PathBuf::from(env::var_os("CARGO_MANIFEST_DIR").unwrap()); 29 | 30 | let chip_core_name = match env::vars() 31 | .map(|(a, _)| a) 32 | .filter(|x| x.starts_with("CARGO_FEATURE_STM32")) 33 | .get_one() 34 | { 35 | Ok(x) => x, 36 | Err(GetOneError::None) => panic!("No stm32xx Cargo feature enabled"), 37 | Err(GetOneError::Multiple) => panic!("Multiple stm32xx Cargo features enabled"), 38 | } 39 | .strip_prefix("CARGO_FEATURE_") 40 | .unwrap() 41 | .to_ascii_lowercase() 42 | .replace('_', "-"); 43 | 44 | #[cfg(feature = "rt")] 45 | println!( 46 | "cargo:rustc-link-search={}/src/chips/{}", 47 | crate_dir.display(), 48 | chip_core_name, 49 | ); 50 | 51 | println!("cargo:rustc-env=STM32_METAPAC_PAC_PATH=chips/{}/pac.rs", chip_core_name); 52 | println!( 53 | "cargo:rustc-env=STM32_METAPAC_METADATA_PATH=chips/{}/metadata.rs", 54 | chip_core_name 55 | ); 56 | 57 | println!("cargo:rerun-if-changed=build.rs"); 58 | } 59 | -------------------------------------------------------------------------------- /transforms/TAMP.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !DeleteEnums 3 | from: ^(BHKLOCK|ERCFG|PRIV|SEC)$ 4 | 5 | - !DeleteFieldsets 6 | from: ^(BKP\d+R|COUNT\dR)$ 7 | 8 | - !MakeRegisterArray 9 | blocks: ^TAMP$ 10 | from: ^BKP\d+R$ 11 | to: BKPR 12 | 13 | - !MakeFieldArray 14 | fieldsets: ATCR1 15 | from: TAMP\dAM 16 | to: TAMPAM 17 | 18 | - !MakeFieldArray 19 | fieldsets: ATCR\d 20 | from: ATOSEL\d 21 | to: ATOSEL 22 | 23 | - !MakeFieldArray 24 | fieldsets: CR1 25 | from: ^TAMP\d(E|NOER|MSK|TRG)$ 26 | to: TAMP${1} 27 | 28 | - !RenameFields 29 | fieldset: CR2 30 | from: TAMP(\d)NOER 31 | to: TAMP${1}POM 32 | 33 | - !MakeFieldArray 34 | fieldsets: CR2 35 | from: ^TAMP\d(POM|MSK|TRG)$ 36 | to: TAMP${1} 37 | 38 | - !RenameFields 39 | fieldset: CR3 40 | from: ITAMP(\d+)NOER 41 | to: ITAMP${1}POM 42 | 43 | - !RenameRegisters 44 | block: TAMP 45 | from: ERCFGR 46 | to: RPCFGR 47 | 48 | - !Rename 49 | from: ERCFGR 50 | to: RPCFGR 51 | 52 | - !RenameFields 53 | fieldset: RPCFGR 54 | from: ERCFG(\d) 55 | to: RPCFG${1} 56 | 57 | - !MakeFieldArray 58 | fieldsets: IER 59 | from: TAMP\dIE 60 | to: TAMPIE 61 | 62 | - !MakeFieldArray 63 | fieldsets: CR2 64 | from: ^TAMP\d(POM|MSK|TRG)$ 65 | to: TAMP${1} 66 | 67 | - !MakeFieldArray 68 | fieldsets: MISR 69 | from: ^TAMP\dMF$ 70 | to: TAMPMF 71 | 72 | - !MakeFieldArray 73 | fieldsets: SCR 74 | from: ^CTAMP\dF$ 75 | to: CTAMPF 76 | 77 | - !MakeFieldArray 78 | fieldsets: SMISR 79 | from: ^TAMP\dMF$ 80 | to: TAMPMF 81 | 82 | - !MakeFieldArray 83 | fieldsets: SR 84 | from: ^TAMP\dF$ 85 | to: TAMPF 86 | 87 | - !DeleteFieldsets 88 | from: ATSEEDR 89 | -------------------------------------------------------------------------------- /data/registers/pwr_f1.yaml: -------------------------------------------------------------------------------- 1 | block/PWR: 2 | description: Power control 3 | items: 4 | - name: CR 5 | description: Power control register (PWR_CR) 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: CSR 9 | description: Power control register (PWR_CR) 10 | byte_offset: 4 11 | fieldset: CSR 12 | fieldset/CR: 13 | description: Power control register (PWR_CR) 14 | fields: 15 | - name: LPDS 16 | description: Low Power Deep Sleep 17 | bit_offset: 0 18 | bit_size: 1 19 | - name: PDDS 20 | description: Power Down Deep Sleep 21 | bit_offset: 1 22 | bit_size: 1 23 | enum: PDDS 24 | - name: CWUF 25 | description: Clear Wake-up Flag 26 | bit_offset: 2 27 | bit_size: 1 28 | - name: CSBF 29 | description: Clear STANDBY Flag 30 | bit_offset: 3 31 | bit_size: 1 32 | - name: PVDE 33 | description: Power Voltage Detector Enable 34 | bit_offset: 4 35 | bit_size: 1 36 | - name: PLS 37 | description: PVD Level Selection 38 | bit_offset: 5 39 | bit_size: 3 40 | - name: DBP 41 | description: Disable Backup Domain write protection 42 | bit_offset: 8 43 | bit_size: 1 44 | fieldset/CSR: 45 | description: Power control register (PWR_CR) 46 | fields: 47 | - name: WUF 48 | description: Wake-Up Flag 49 | bit_offset: 0 50 | bit_size: 1 51 | - name: SBF 52 | description: STANDBY Flag 53 | bit_offset: 1 54 | bit_size: 1 55 | - name: PVDO 56 | description: PVD Output 57 | bit_offset: 2 58 | bit_size: 1 59 | - name: EWUP 60 | description: Enable WKUP pin 61 | bit_offset: 8 62 | bit_size: 1 63 | enum/PDDS: 64 | bit_size: 1 65 | variants: 66 | - name: STOP_MODE 67 | description: Enter Stop mode when the CPU enters deepsleep 68 | value: 0 69 | - name: STANDBY_MODE 70 | description: Enter Standby mode when the CPU enters deepsleep 71 | value: 1 72 | -------------------------------------------------------------------------------- /transforms/RCC.yaml: -------------------------------------------------------------------------------- 1 | transforms: 2 | - !RenameFields 3 | fieldset: .+ 4 | from: ^RCC_(.+)$ 5 | to: $1 6 | 7 | - !RenameRegisters 8 | block: .+ 9 | from: ^RCC_(.+)$ 10 | to: $1 11 | 12 | - !Rename 13 | type: Fieldset 14 | from: ^RCC_(.+)$ 15 | to: $1 16 | 17 | - !Rename 18 | type: Enum 19 | from: ^RCC_(.+)$ 20 | to: $1 21 | 22 | - !MergeEnums 23 | from: CCMR\d_Input_CC\dS 24 | to: CCMR_Input_CCS 25 | check: Layout 26 | 27 | # Remove digits from enum names 28 | - !MergeEnums 29 | from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]* 30 | to: $1$2$3 31 | skip_unmergeable: true 32 | 33 | - !DeleteEnums 34 | from: ^(SEC|PRIV|SECURITY)$ 35 | 36 | #- !MakeFieldArray 37 | # fieldsets: .* 38 | # from: ([A-Z]+)\d([A-Z]*) 39 | # to: $1$2 40 | # allow_cursed: true 41 | - !MakeFieldArray 42 | fieldsets: .* 43 | from: P\d+WP 44 | to: PWP 45 | # - !MakeRegisterArray 46 | # blocks: .* 47 | # from: ([A-Z]+)\d+ 48 | # to: $1 49 | - !MakeRegisterArray 50 | blocks: .* 51 | from: EXTICR\d+ 52 | to: EXTICR 53 | - !MergeEnums 54 | from: "[HL](IFCR|ISR)_(.*)" 55 | to: $2 56 | - !MergeFieldsets 57 | from: "[HL](IFCR|ISR)" 58 | to: $1 59 | - !MergeFieldsets 60 | from: EXTICR\d 61 | to: EXTICR 62 | - !MakeRegisterArray 63 | blocks: .* 64 | from: "[HL](IFCR|ISR)" 65 | to: $1 66 | - !DeleteEnums 67 | from: ".*EN" 68 | bit_size: 1 69 | - !DeleteEnums 70 | from: ".*RST" 71 | bit_size: 1 72 | - !DeleteEnums 73 | from: ".*ON" 74 | bit_size: 1 75 | - !MakeRegisterArray 76 | blocks: .* 77 | from: PLL\d+(.*) 78 | to: PLL$1 79 | - !MakeFieldArray 80 | fieldsets: .* 81 | from: PLL\d+(.*) 82 | to: PLL$1 83 | - !MakeFieldArray 84 | fieldsets: (PLLCFGR|PLLCKSELR) 85 | from: DIV([A-Z]+)\d+([A-Z]*) 86 | to: DIV$1$2 87 | -------------------------------------------------------------------------------- /data/registers/exti_c0.yaml: -------------------------------------------------------------------------------- 1 | block/EXTI: 2 | description: External interrupt/event controller 3 | items: 4 | - name: RTSR 5 | description: Rising Trigger selection register 6 | array: 7 | len: 1 8 | stride: 40 9 | byte_offset: 0 10 | fieldset: LINES 11 | - name: FTSR 12 | description: Falling Trigger selection register 13 | array: 14 | len: 1 15 | stride: 40 16 | byte_offset: 4 17 | fieldset: LINES 18 | - name: SWIER 19 | description: Software interrupt event register 20 | array: 21 | len: 1 22 | stride: 40 23 | byte_offset: 8 24 | fieldset: LINES 25 | - name: RPR 26 | description: Rising pending register 27 | array: 28 | len: 1 29 | stride: 40 30 | byte_offset: 12 31 | fieldset: LINES 32 | - name: FPR 33 | description: Falling pending register 34 | array: 35 | len: 1 36 | stride: 40 37 | byte_offset: 16 38 | fieldset: LINES 39 | - name: EXTICR 40 | description: Configuration register 41 | array: 42 | len: 4 43 | stride: 4 44 | byte_offset: 96 45 | fieldset: EXTICR 46 | - name: IMR 47 | description: Interrupt mask register 48 | array: 49 | len: 1 50 | stride: 16 51 | byte_offset: 128 52 | fieldset: LINES 53 | - name: EMR 54 | description: Event mask register 55 | array: 56 | len: 1 57 | stride: 16 58 | byte_offset: 132 59 | fieldset: LINES 60 | fieldset/EXTICR: 61 | description: external interrupt configuration register 1 62 | fields: 63 | - name: EXTI 64 | description: EXTI configuration bits 65 | bit_offset: 0 66 | bit_size: 8 67 | array: 68 | len: 4 69 | stride: 8 70 | fieldset/LINES: 71 | description: EXTI lines register, 1 bit per line 72 | fields: 73 | - name: LINE 74 | description: EXTI line 75 | bit_offset: 0 76 | bit_size: 1 77 | array: 78 | len: 32 79 | stride: 1 80 | -------------------------------------------------------------------------------- /data/registers/exti_g0.yaml: -------------------------------------------------------------------------------- 1 | block/EXTI: 2 | description: External interrupt/event controller 3 | items: 4 | - name: RTSR 5 | description: Rising Trigger selection register 6 | array: 7 | len: 2 8 | stride: 40 9 | byte_offset: 0 10 | fieldset: LINES 11 | - name: FTSR 12 | description: Falling Trigger selection register 13 | array: 14 | len: 2 15 | stride: 40 16 | byte_offset: 4 17 | fieldset: LINES 18 | - name: SWIER 19 | description: Software interrupt event register 20 | array: 21 | len: 2 22 | stride: 40 23 | byte_offset: 8 24 | fieldset: LINES 25 | - name: RPR 26 | description: Rising pending register 27 | array: 28 | len: 2 29 | stride: 40 30 | byte_offset: 12 31 | fieldset: LINES 32 | - name: FPR 33 | description: Falling pending register 34 | array: 35 | len: 2 36 | stride: 40 37 | byte_offset: 16 38 | fieldset: LINES 39 | - name: EXTICR 40 | description: Configuration register 41 | array: 42 | len: 4 43 | stride: 4 44 | byte_offset: 96 45 | fieldset: EXTICR 46 | - name: IMR 47 | description: Interrupt mask register 48 | array: 49 | len: 2 50 | stride: 16 51 | byte_offset: 128 52 | fieldset: LINES 53 | - name: EMR 54 | description: Event mask register 55 | array: 56 | len: 2 57 | stride: 16 58 | byte_offset: 132 59 | fieldset: LINES 60 | fieldset/EXTICR: 61 | description: external interrupt configuration register 1 62 | fields: 63 | - name: EXTI 64 | description: EXTI configuration bits 65 | bit_offset: 0 66 | bit_size: 8 67 | array: 68 | len: 4 69 | stride: 8 70 | fieldset/LINES: 71 | description: EXTI lines register, 1 bit per line 72 | fields: 73 | - name: LINE 74 | description: EXTI line 75 | bit_offset: 0 76 | bit_size: 1 77 | array: 78 | len: 32 79 | stride: 1 80 | -------------------------------------------------------------------------------- /data/registers/exti_u0.yaml: -------------------------------------------------------------------------------- 1 | block/EXTI: 2 | description: External interrupt/event controller 3 | items: 4 | - name: RTSR 5 | description: Rising Trigger selection register 6 | array: 7 | len: 1 8 | stride: 40 9 | byte_offset: 0 10 | fieldset: LINES 11 | - name: FTSR 12 | description: Falling Trigger selection register 13 | array: 14 | len: 1 15 | stride: 40 16 | byte_offset: 4 17 | fieldset: LINES 18 | - name: SWIER 19 | description: Software interrupt event register 20 | array: 21 | len: 1 22 | stride: 40 23 | byte_offset: 8 24 | fieldset: LINES 25 | - name: RPR 26 | description: Rising pending register 27 | array: 28 | len: 1 29 | stride: 40 30 | byte_offset: 12 31 | fieldset: LINES 32 | - name: FPR 33 | description: Falling pending register 34 | array: 35 | len: 1 36 | stride: 40 37 | byte_offset: 16 38 | fieldset: LINES 39 | - name: EXTICR 40 | description: Configuration register 41 | array: 42 | len: 4 43 | stride: 4 44 | byte_offset: 96 45 | fieldset: EXTICR 46 | - name: IMR 47 | description: Interrupt mask register 48 | array: 49 | len: 2 50 | stride: 16 51 | byte_offset: 128 52 | fieldset: LINES 53 | - name: EMR 54 | description: Event mask register 55 | array: 56 | len: 2 57 | stride: 16 58 | byte_offset: 132 59 | fieldset: LINES 60 | fieldset/EXTICR: 61 | description: external interrupt configuration register 1 62 | fields: 63 | - name: EXTI 64 | description: EXTI configuration bits 65 | bit_offset: 0 66 | bit_size: 8 67 | array: 68 | len: 4 69 | stride: 8 70 | fieldset/LINES: 71 | description: EXTI lines register, 1 bit per line 72 | fields: 73 | - name: LINE 74 | description: EXTI line 75 | bit_offset: 0 76 | bit_size: 1 77 | array: 78 | len: 32 79 | stride: 1 80 | -------------------------------------------------------------------------------- /merge_regs.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # /// script 3 | # requires-python = ">=3.13" 4 | # dependencies = [ 5 | # "pyyaml", 6 | # "xmltodict", 7 | # ] 8 | # /// 9 | 10 | import xmltodict 11 | import yaml 12 | import re 13 | import json 14 | import sys 15 | import os 16 | from glob import glob 17 | 18 | 19 | def item_key(a): 20 | return int(a["byte_offset"]) 21 | 22 | 23 | def field_key(a): 24 | return int(a["bit_offset"]) 25 | 26 | 27 | def merge_block(origin, new): 28 | for newval in new: 29 | found = False 30 | for val in origin: 31 | if val["name"] == newval["name"] and val["byte_offset"] == newval["byte_offset"]: 32 | found = True 33 | if not found: 34 | origin.append(newval) 35 | origin.sort(key=item_key) 36 | 37 | 38 | def merge_fields(origin, new): 39 | for newval in new: 40 | found = False 41 | for val in origin: 42 | if val["name"] == newval["name"] and val["bit_offset"] == newval["bit_offset"]: 43 | found = True 44 | if not found: 45 | origin.append(newval) 46 | origin.sort(key=field_key) 47 | 48 | 49 | def merge_dicts(origin, new): 50 | for k, v in new.items(): 51 | if k in origin: 52 | if type(v) is dict: 53 | merge_dicts(origin[k], v) 54 | elif type(v) is list: 55 | if k == "items": 56 | merge_block(origin[k], v) 57 | if k == "fields": 58 | merge_fields(origin[k], v) 59 | else: 60 | origin[k] = v 61 | else: 62 | origin[k] = v 63 | 64 | 65 | first = True 66 | reg_map = {} 67 | for regfile in sys.argv[1:]: 68 | print("Loading", regfile) 69 | with open(regfile, 'r') as f: 70 | y = yaml.load(f, Loader=yaml.SafeLoader) 71 | merge_dicts(reg_map, y) 72 | 73 | 74 | with open('regs_merged.yaml', 'w') as f: 75 | f.write(yaml.dump(reg_map)) 76 | -------------------------------------------------------------------------------- /data/dmamux/H7RS_GPDMA.yaml: -------------------------------------------------------------------------------- 1 | ADC1: 0 2 | ADC2: 1 3 | CRYP_IN: 2 4 | CRYP_OUT: 3 5 | SAES_OUT: 4 6 | SAES_IN: 5 7 | HASH: 6 8 | TIM1_CC: 7 9 | TIM1_CC: 8 10 | TIM1_CC: 9 11 | TIM1_CC: 10 12 | TIM1_UP: 11 13 | TIM1_TRG: 12 14 | TIM1_COM: 13 15 | TIM2_CC: 14 16 | TIM2_CC: 15 17 | TIM2_CC: 16 18 | TIM2_CC: 17 19 | TIM2_UP: 18 20 | TIM2_TRG: 19 21 | TIM3_CC: 20 22 | TIM3_CC: 21 23 | TIM3_CC: 22 24 | TIM3_CC: 23 25 | TIM3_UP: 24 26 | TIM3_TRG: 25 27 | TIM4_CC: 26 28 | TIM4_CC: 27 29 | TIM4_CC: 28 30 | TIM4_CC: 29 31 | TIM4_UP: 30 32 | TIM4_TRG: 31 33 | TIM5_CC: 32 34 | TIM5_CC: 33 35 | TIM5_CC: 34 36 | TIM5_CC: 35 37 | TIM5_UP: 36 38 | TIM5_TRG: 37 39 | TIM6_UP: 38 40 | TIM7_UP: 39 41 | TIM15_CC: 40 42 | TIM15_CC: 41 43 | TIM15_UP: 42 44 | TIM15_TRG: 43 45 | TIM15_COM: 44 46 | TIM16_CC: 45 47 | TIM16_UP: 46 48 | TIM16_COM: 47 49 | TIM17_CC: 48 50 | TIM17_UP: 49 51 | TIM17_COM: 50 52 | SPI1_RX: 51 53 | SPI1_TX: 52 54 | SPI2_RX: 53 55 | SPI2_TX: 54 56 | SPI3_RX: 55 57 | SPI3_TX: 56 58 | SPI4_RX: 57 59 | SPI4_TX: 58 60 | SPI5_RX: 59 61 | SPI5_TX: 60 62 | SPI6_RX: 61 63 | SPI6_TX: 62 64 | SAI1_A: 63 65 | SAI1_B: 64 66 | SAI2_A: 65 67 | SAI2_B: 66 68 | I2C1_RX: 67 69 | I2C1_TX: 68 70 | I2C2_RX: 69 71 | I2C2_TX: 70 72 | I2C3_RX: 71 73 | I2C3_TX: 72 74 | USART1_RX: 73 75 | USART1_TX: 74 76 | USART2_RX: 75 77 | USART2_TX: 76 78 | USART3_RX: 77 79 | USART3_TX: 78 80 | UART4_RX: 79 81 | UART4_TX: 80 82 | UART5_RX: 81 83 | UART5_TX: 82 84 | UART7_RX: 83 85 | UART7_TX: 84 86 | UART8_RX: 85 87 | UART8_TX: 86 88 | CORDIC_READ: 87 89 | CORDIC_WRITE: 88 90 | LPTIM1_IC1: 89 91 | LPTIM1_IC2: 90 92 | LPTIM1_UE: 91 93 | LPTIM2_IC1: 92 94 | LPTIM2_IC2: 93 95 | LPTIM2_UE: 94 96 | SPDIFRX_DAT: 95 97 | SPDIFRX_CTRL: 96 98 | ADF1_FLT0: 97 99 | UCPD_TX: 98 100 | UCPD_RX: 99 101 | PSSI: 100 102 | LPUART1_RX: 101 103 | LPUART1_TX: 102 104 | LPTIM3_IC1: 103 105 | LPTIM3_IC2: 104 106 | LPTIM3_UE: 105 107 | I3C1_RX: 106 108 | I3C1_TX: 107 109 | I3C1_TC: 108 110 | I3C1_RS: 109 111 | -------------------------------------------------------------------------------- /data/registers/pwr_f0.yaml: -------------------------------------------------------------------------------- 1 | block/PWR: 2 | description: Power control 3 | items: 4 | - name: CR 5 | description: power control register 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: CSR 9 | description: power control/status register 10 | byte_offset: 4 11 | fieldset: CSR 12 | fieldset/CR: 13 | description: power control register 14 | fields: 15 | - name: LPDS 16 | description: Low-power deep sleep 17 | bit_offset: 0 18 | bit_size: 1 19 | - name: PDDS 20 | description: Power down deepsleep 21 | bit_offset: 1 22 | bit_size: 1 23 | enum: PDDS 24 | - name: CWUF 25 | description: Clear wakeup flag 26 | bit_offset: 2 27 | bit_size: 1 28 | - name: CSBF 29 | description: Clear standby flag 30 | bit_offset: 3 31 | bit_size: 1 32 | - name: PVDE 33 | description: Power voltage detector enable 34 | bit_offset: 4 35 | bit_size: 1 36 | - name: PLS 37 | description: PVD level selection 38 | bit_offset: 5 39 | bit_size: 3 40 | - name: DBP 41 | description: Disable backup domain write protection 42 | bit_offset: 8 43 | bit_size: 1 44 | fieldset/CSR: 45 | description: power control/status register 46 | fields: 47 | - name: WUF 48 | description: Wakeup flag 49 | bit_offset: 0 50 | bit_size: 1 51 | - name: SBF 52 | description: Standby flag 53 | bit_offset: 1 54 | bit_size: 1 55 | - name: PVDO 56 | description: PVD output 57 | bit_offset: 2 58 | bit_size: 1 59 | - name: VREFINTRDY 60 | description: VREFINT reference voltage ready 61 | bit_offset: 3 62 | bit_size: 1 63 | - name: EWUP 64 | description: Enable WKUP pin 1 65 | bit_offset: 8 66 | bit_size: 1 67 | array: 68 | len: 8 69 | stride: 1 70 | enum/PDDS: 71 | bit_size: 1 72 | variants: 73 | - name: STOP_MODE 74 | description: Enter Stop mode when the CPU enters deepsleep 75 | value: 0 76 | - name: STANDBY_MODE 77 | description: Enter Standby mode when the CPU enters deepsleep 78 | value: 1 79 | -------------------------------------------------------------------------------- /data/registers/wwdg_v2.yaml: -------------------------------------------------------------------------------- 1 | block/WWDG: 2 | description: Window watchdog 3 | items: 4 | - name: CR 5 | description: Control register 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: CFR 9 | description: Configuration register 10 | byte_offset: 4 11 | fieldset: CFR 12 | - name: SR 13 | description: Status register 14 | byte_offset: 8 15 | fieldset: SR 16 | fieldset/CFR: 17 | description: Configuration register 18 | fields: 19 | - name: W 20 | description: 7-bit window value 21 | bit_offset: 0 22 | bit_size: 7 23 | - name: EWI 24 | description: Early wakeup interrupt 25 | bit_offset: 9 26 | bit_size: 1 27 | - name: WDGTB 28 | description: Timer base 29 | bit_offset: 11 30 | bit_size: 3 31 | enum: WDGTB 32 | fieldset/CR: 33 | description: Control register 34 | fields: 35 | - name: T 36 | description: 7-bit counter (MSB to LSB) 37 | bit_offset: 0 38 | bit_size: 7 39 | - name: WDGA 40 | description: Activation bit (true is enabled, false is disabled) 41 | bit_offset: 7 42 | bit_size: 1 43 | fieldset/SR: 44 | description: Status register 45 | fields: 46 | - name: EWIF 47 | description: Early wakeup interrupt flag 48 | bit_offset: 0 49 | bit_size: 1 50 | enum/WDGTB: 51 | bit_size: 3 52 | variants: 53 | - name: Div1 54 | description: Counter clock (PCLK1 div 4096) div 1 55 | value: 0 56 | - name: Div2 57 | description: Counter clock (PCLK1 div 4096) div 2 58 | value: 1 59 | - name: Div4 60 | description: Counter clock (PCLK1 div 4096) div 4 61 | value: 2 62 | - name: Div8 63 | description: Counter clock (PCLK1 div 4096) div 8 64 | value: 3 65 | - name: Div16 66 | description: Counter clock (PCLK1 div 4096) div 16 67 | value: 4 68 | - name: Div32 69 | description: Counter clock (PCLK1 div 4096) div 32 70 | value: 5 71 | - name: Div64 72 | description: Counter clock (PCLK1 div 4096) div 64 73 | value: 6 74 | - name: Div128 75 | description: Counter clock (PCLK1 div 4096) div 128 76 | value: 7 77 | -------------------------------------------------------------------------------- /data/registers/syscfg_f4.yaml: -------------------------------------------------------------------------------- 1 | block/SYSCFG: 2 | description: System configuration controller 3 | items: 4 | - name: MEMRM 5 | description: memory remap register 6 | byte_offset: 0 7 | fieldset: MEMRM 8 | - name: PMC 9 | description: peripheral mode configuration register 10 | byte_offset: 4 11 | fieldset: PMC 12 | - name: EXTICR 13 | description: external interrupt configuration register 14 | array: 15 | len: 4 16 | stride: 4 17 | byte_offset: 8 18 | fieldset: EXTICR 19 | - name: CMPCR 20 | description: Compensation cell control register 21 | byte_offset: 32 22 | access: Read 23 | fieldset: CMPCR 24 | fieldset/CMPCR: 25 | description: Compensation cell control register 26 | fields: 27 | - name: CMP_PD 28 | description: Compensation cell power-down 29 | bit_offset: 0 30 | bit_size: 1 31 | - name: READY 32 | description: READY 33 | bit_offset: 8 34 | bit_size: 1 35 | fieldset/EXTICR: 36 | description: external interrupt configuration register 37 | fields: 38 | - name: EXTI 39 | description: EXTI x configuration 40 | bit_offset: 0 41 | bit_size: 4 42 | array: 43 | len: 4 44 | stride: 4 45 | fieldset/MEMRM: 46 | description: memory remap register 47 | fields: 48 | - name: MEM_MODE 49 | description: Memory mapping selection 50 | bit_offset: 0 51 | bit_size: 3 52 | - name: FB_MODE 53 | description: Flash bank mode selection 54 | bit_offset: 8 55 | bit_size: 1 56 | - name: SWP_FMC 57 | description: FMC memory mapping swap 58 | bit_offset: 10 59 | bit_size: 2 60 | fieldset/PMC: 61 | description: peripheral mode configuration register 62 | fields: 63 | - name: ADC1DC2 64 | description: ADC1DC2 65 | bit_offset: 16 66 | bit_size: 1 67 | - name: ADC2DC2 68 | description: ADC2DC2 69 | bit_offset: 17 70 | bit_size: 1 71 | - name: ADC3DC2 72 | description: ADC3DC2 73 | bit_offset: 18 74 | bit_size: 1 75 | - name: MII_RMII_SEL 76 | description: Ethernet PHY interface selection 77 | bit_offset: 23 78 | bit_size: 1 79 | -------------------------------------------------------------------------------- /data/dmamux/U5_GPDMA1.yaml: -------------------------------------------------------------------------------- 1 | ADC1: 0 2 | ADC4: 1 3 | DAC1_CH1: 2 4 | DAC1_CH2: 3 5 | TIM6_UP: 4 6 | TIM7_UP: 5 7 | SPI1_RX: 6 8 | SPI1_TX: 7 9 | SPI2_RX: 8 10 | SPI2_TX: 9 11 | SPI3_RX: 10 12 | SPI3_TX: 11 13 | I2C1_RX: 12 14 | I2C1_TX: 13 15 | I2C1_EVC: 14 16 | I2C2_RX: 15 17 | I2C2_TX: 16 18 | I2C2_EVC: 17 19 | I2C3_RX: 18 20 | I2C3_TX: 19 21 | I2C3_EVC: 20 22 | I2C4_RX: 21 23 | I2C4_TX: 22 24 | I2C4_EVC: 23 25 | USART1_RX: 24 26 | USART1_TX: 25 27 | USART2_RX: 26 28 | USART2_TX: 27 29 | USART3_RX: 28 30 | USART3_TX: 29 31 | UART4_RX: 30 32 | UART4_TX: 31 33 | UART5_RX: 32 34 | UART5_TX: 33 35 | LPUART1_RX: 34 36 | LPUART1_TX: 35 37 | SAI1_A: 36 38 | SAI1_B: 37 39 | SAI2_A: 38 40 | SAI2_B: 39 41 | OCTOSPI1: 40 42 | OCTOSPI2: 41 43 | TIM1_CH1: 42 44 | TIM1_CH2: 43 45 | TIM1_CH3: 44 46 | TIM1_CH4: 45 47 | TIM1_UP: 46 48 | TIM1_TRG: 47 49 | TIM1_COM: 48 50 | TIM8_CH1: 49 51 | TIM8_CH2: 50 52 | TIM8_CH3: 51 53 | TIM8_CH4: 52 54 | TIM8_UP: 53 55 | TIM8_TRG: 54 56 | TIM8_COM: 55 57 | TIM2_CH1: 56 58 | TIM2_CH2: 57 59 | TIM2_CH3: 58 60 | TIM2_CH4: 59 61 | TIM2_UP: 60 62 | TIM3_CH1: 61 63 | TIM3_CH2: 62 64 | TIM3_CH3: 63 65 | TIM3_CH4: 64 66 | TIM3_UP: 65 67 | TIM3_TRG: 66 68 | TIM4_CH1: 67 69 | TIM4_CH2: 68 70 | TIM4_CH3: 69 71 | TIM4_CH4: 70 72 | TIM4_UP: 71 73 | TIM5_CH1: 72 74 | TIM5_CH2: 73 75 | TIM5_CH3: 74 76 | TIM5_CH4: 75 77 | TIM5_UP: 76 78 | TIM5_TRG: 77 79 | TIM15_CC1: 78 80 | TIM15_UP: 79 81 | TIM15_TRG: 80 82 | TIM15_COM: 81 83 | TIM16_CC1: 82 84 | TIM16_UP: 83 85 | TIM17_CC1: 84 86 | TIM17_UP: 85 87 | DCMI: 86 88 | AES_IN: 87 89 | AES_OUT: 88 90 | HASH_IN: 89 91 | UCPD1_TX: 90 92 | UCPD1_RX: 91 93 | MDF1_FLT0: 92 94 | MDF1_FLT1: 93 95 | MDF1_FLT2: 94 96 | MDF1_FLT3: 95 97 | MDF1_FLT4: 96 98 | MDF1_FLT5: 97 99 | ADF1_FLT0: 98 100 | FMAC_READ: 99 101 | FMAC_WRITE: 100 102 | CORDIC_READ: 101 103 | CORDIC_WRITE: 102 104 | SAES_IN: 103 105 | SAES_OUT: 104 106 | LPTIM1_IC1: 105 107 | LPTIM1_IC2: 106 108 | LPTIM1_UE: 107 109 | LPTIM2_IC1: 108 110 | LPTIM2_IC2: 109 111 | LPTIM2_UE: 110 112 | LPTIM3_IC1: 111 113 | LPTIM3_IC2: 112 114 | LPTIM3_UE: 113 115 | HSPI1: 114 -------------------------------------------------------------------------------- /data/dmamux/G4_DMAMUX1.yaml: -------------------------------------------------------------------------------- 1 | GENERATOR0: 1 2 | GENERATOR1: 2 3 | GENERATOR2: 3 4 | GENERATOR3: 4 5 | ADC1: 5 6 | DAC1_CH1: 6 7 | DAC1_CH2: 7 8 | TIM6_UP: 8 9 | TIM7_UP: 9 10 | SPI1_RX: 10 11 | SPI1_TX: 11 12 | SPI2_RX: 12 13 | SPI2_TX: 13 14 | SPI3_RX: 14 15 | SPI3_TX: 15 16 | I2C1_RX: 16 17 | I2C1_TX: 17 18 | I2C2_RX: 18 19 | I2C2_TX: 19 20 | I2C3_RX: 20 21 | I2C3_TX: 21 22 | I2C4_RX: 22 23 | I2C4_TX: 23 24 | USART1_RX: 24 25 | USART1_TX: 25 26 | USART2_RX: 26 27 | USART2_TX: 27 28 | USART3_RX: 28 29 | USART3_TX: 29 30 | UART4_RX: 30 31 | UART4_TX: 31 32 | UART5_RX: 32 33 | UART5_TX: 33 34 | LPUART1_RX: 34 35 | LPUART1_TX: 35 36 | ADC2: 36 37 | ADC3: 37 38 | ADC4: 38 39 | ADC5: 39 40 | QUADSPI: 40 41 | DAC2_CH1: 41 42 | TIM1_CH1: 42 43 | TIM1_CH2: 43 44 | TIM1_CH3: 44 45 | TIM1_CH4: 45 46 | TIM1_UP: 46 47 | TIM1_TRIG: 47 48 | TIM1_COM: 48 49 | TIM8_CH1: 49 50 | TIM8_CH2: 50 51 | TIM8_CH3: 51 52 | TIM8_CH4: 52 53 | TIM8_UP: 53 54 | TIM8_TRIG: 54 55 | TIM8_COM: 55 56 | TIM2_CH1: 56 57 | TIM2_CH2: 57 58 | TIM2_CH3: 58 59 | TIM2_CH4: 59 60 | TIM2_UP: 60 61 | TIM3_CH1: 61 62 | TIM3_CH2: 62 63 | TIM3_CH3: 63 64 | TIM3_CH4: 64 65 | TIM3_UP: 65 66 | TIM3_TRIG: 66 67 | TIM4_CH1: 67 68 | TIM4_CH2: 68 69 | TIM4_CH3: 69 70 | TIM4_CH4: 70 71 | TIM4_UP: 71 72 | TIM5_CH1: 72 73 | TIM5_CH2: 73 74 | TIM5_CH3: 74 75 | TIM5_CH4: 75 76 | TIM5_UP: 76 77 | TIM5_TRIG: 77 78 | TIM15_CH1: 78 79 | TIM15_UP: 79 80 | TIM15_TRIG: 80 81 | TIM15_COM: 81 82 | TIM16_CH1: 82 83 | TIM16_UP: 83 84 | TIM17_CH1: 84 85 | TIM17_UP: 85 86 | TIM20_CH1: 86 87 | TIM20_CH2: 87 88 | TIM20_CH3: 88 89 | TIM20_CH4: 89 90 | TIM20_UP: 90 91 | AES_IN: 91 92 | AES_OUT: 92 93 | TIM20_TRIG: 93 94 | TIM20_COM: 94 95 | HRTIM1_M: 95 96 | HRTIM1_A: 96 97 | HRTIM1_B: 97 98 | HRTIM1_C: 98 99 | HRTIM1_D: 99 100 | HRTIM1_E: 100 101 | HRTIM1_F: 101 102 | DAC3_CH1: 102 103 | DAC3_CH2: 103 104 | DAC4_CH1: 104 105 | DAC4_CH2: 105 106 | SPI4_RX: 106 107 | SPI4_TX: 107 108 | SAI1_A: 108 109 | SAI1_B: 109 110 | FMAC_READ: 110 111 | FMAC_WRITE: 111 112 | CORDIC_READ: 112 113 | CORDIC_WRITE: 113 114 | UCPD1_RX: 114 115 | UCPD1_TX: 115 116 | -------------------------------------------------------------------------------- /data/registers/syscfg_f2.yaml: -------------------------------------------------------------------------------- 1 | block/SYSCFG: 2 | description: System configuration controller 3 | items: 4 | - name: MEMRMP 5 | description: memory remap register 6 | byte_offset: 0 7 | fieldset: MEMRMP 8 | - name: PMC 9 | description: peripheral mode configuration register 10 | byte_offset: 4 11 | fieldset: PMC 12 | - name: EXTICR 13 | description: external interrupt configuration register 1 14 | array: 15 | len: 4 16 | stride: 4 17 | byte_offset: 8 18 | fieldset: EXTICR 19 | - name: CMPCR 20 | description: Compensation cell control register 21 | byte_offset: 32 22 | access: Read 23 | fieldset: CMPCR 24 | fieldset/CMPCR: 25 | description: Compensation cell control register 26 | fields: 27 | - name: CMP_PD 28 | description: Compensation cell power-down 29 | bit_offset: 0 30 | bit_size: 1 31 | - name: READY 32 | description: Compensation cell ready flag 33 | bit_offset: 8 34 | bit_size: 1 35 | fieldset/EXTICR: 36 | description: external interrupt configuration register 1 37 | fields: 38 | - name: EXTI 39 | description: EXTI x configuration (x = 0 to 3) 40 | bit_offset: 0 41 | bit_size: 4 42 | array: 43 | len: 4 44 | stride: 4 45 | fieldset/MEMRMP: 46 | description: memory remap register 47 | fields: 48 | - name: MEM_MODE 49 | description: Memory mapping selection 50 | bit_offset: 0 51 | bit_size: 2 52 | enum: MEM_MODE 53 | fieldset/PMC: 54 | description: peripheral mode configuration register 55 | fields: 56 | - name: MII_RMII_SEL 57 | description: Ethernet PHY interface selection 58 | bit_offset: 23 59 | bit_size: 1 60 | enum/MEM_MODE: 61 | bit_size: 2 62 | variants: 63 | - name: MainFlash 64 | description: Main Flash memory mapped at 0x0000_0000 65 | value: 0 66 | - name: SystemFlash 67 | description: System Flash memory mapped at 0x0000_0000 68 | value: 1 69 | - name: FSMC 70 | description: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000_0000 71 | value: 2 72 | - name: SRAM 73 | description: Embedded SRAM mapped at 0x0000_0000 74 | value: 3 75 | -------------------------------------------------------------------------------- /data/registers/comp_f3_v1.yaml: -------------------------------------------------------------------------------- 1 | block/COMP: 2 | description: General purpose comparators. 3 | items: 4 | - name: CSR 5 | description: control and status register. 6 | byte_offset: 0 7 | fieldset: CSR 8 | 9 | fieldset/CSR: 10 | description: control and status register. 11 | fields: 12 | - name: EN 13 | description: Comparator enable. 14 | bit_offset: 0 15 | bit_size: 1 16 | - name: INP_DAC 17 | description: Comparator 1 non inverting input connection to DAC output. Only available on COMP1 18 | bit_offset: 1 19 | bit_size: 1 20 | - name: MODE 21 | description: Comparator mode. 22 | bit_offset: 2 23 | bit_size: 2 24 | enum: MODE 25 | - name: INSEL 26 | description: Comparator inverting input selection. 27 | bit_offset: 4 28 | bit_size: 3 29 | - name: WNDWEN 30 | description: Window mode enable. Only available on COMP2 31 | bit_offset: 7 32 | bit_size: 1 33 | - name: OUTSEL 34 | description: Comparator output selection. 35 | bit_offset: 8 36 | bit_size: 3 37 | - name: POL 38 | description: Comparator output polarity. 39 | bit_offset: 11 40 | bit_size: 1 41 | - name: HYST 42 | description: Comparator hysteresis. 43 | bit_offset: 12 44 | bit_size: 2 45 | enum: HYST 46 | - name: OUT 47 | description: Comparator output. 48 | bit_offset: 14 49 | bit_size: 1 50 | - name: LOCK 51 | description: Comparator lock. 52 | bit_offset: 15 53 | bit_size: 1 54 | 55 | enum/HYST: 56 | bit_size: 2 57 | variants: 58 | - name: None 59 | value: 0 60 | - name: Low 61 | description: Low hysteresis 62 | value: 1 63 | - name: Medium 64 | description: Medium hysteresis 65 | value: 2 66 | - name: High 67 | description: High hysteresis 68 | value: 3 69 | 70 | enum/MODE: 71 | bit_size: 2 72 | variants: 73 | - name: HighSpeed 74 | description: High Speed mode 75 | value: 0 76 | - name: MediumSpeed 77 | description: Medium Speed mode 78 | value: 1 79 | - name: LowSpeed 80 | description: Low Speed mode 81 | value: 2 82 | - name: VeryLowSpeed 83 | description: Very Low Speed mode 84 | value: 3 85 | -------------------------------------------------------------------------------- /stm32-data-gen/src/util.rs: -------------------------------------------------------------------------------- 1 | use std::collections::HashMap; 2 | use std::sync::{Mutex, OnceLock}; 3 | 4 | use regex::Regex; 5 | 6 | pub struct RegexMap<'a, T> { 7 | map: &'a [(&'a str, T)], 8 | regexes: OnceLock>, 9 | cache: Mutex>>>, 10 | } 11 | 12 | impl<'a, T> RegexMap<'a, T> { 13 | pub const fn new(map: &'a [(&'a str, T)]) -> Self { 14 | Self { 15 | map, 16 | regexes: OnceLock::new(), 17 | cache: Mutex::new(None), 18 | } 19 | } 20 | 21 | pub fn get(&self, key: &str) -> Option<&'a T> { 22 | if let Some(&val) = self.cache.lock().unwrap().get_or_insert_with(Default::default).get(key) { 23 | return val.map(|i| &self.map[i].1); 24 | } 25 | let val = self.get_uncached(key); 26 | self.cache 27 | .lock() 28 | .unwrap() 29 | .as_mut() 30 | .unwrap() 31 | .insert(key.to_string(), val); 32 | val.map(|i| &self.map[i].1) 33 | } 34 | 35 | fn get_uncached(&self, key: &str) -> Option { 36 | let regexes = self.regexes.get_or_init(|| { 37 | self.map 38 | .iter() 39 | .map(|(k, _)| Regex::new(&format!("^{k}$")).unwrap()) 40 | .collect() 41 | }); 42 | 43 | for (i, k) in regexes.iter().enumerate() { 44 | if k.is_match(key) { 45 | return Some(i); 46 | } 47 | } 48 | None 49 | } 50 | 51 | #[track_caller] 52 | pub fn must_get(&self, key: &str) -> &T { 53 | let Some(res) = self.get(key) else { 54 | panic!("no regexmap for key '{key}'") 55 | }; 56 | res 57 | } 58 | } 59 | 60 | pub struct RegexSet<'a> { 61 | map: RegexMap<'a, ()>, 62 | } 63 | 64 | impl<'a> RegexSet<'a> { 65 | pub const fn new(map: &'a [&'a str]) -> Self { 66 | Self { 67 | map: RegexMap::new(unsafe { std::mem::transmute::<&[&str], &[(&str, ())]>(map) }), 68 | } 69 | } 70 | 71 | pub fn contains(&self, key: &str) -> bool { 72 | self.map.get(key).is_some() 73 | } 74 | } 75 | -------------------------------------------------------------------------------- /data/registers/pwr_f2.yaml: -------------------------------------------------------------------------------- 1 | block/PWR: 2 | description: Power control 3 | items: 4 | - name: CR 5 | description: power control register 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: CSR 9 | description: power control/status register 10 | byte_offset: 4 11 | fieldset: CSR 12 | fieldset/CR: 13 | description: power control register 14 | fields: 15 | - name: LPDS 16 | description: Low-power deep sleep 17 | bit_offset: 0 18 | bit_size: 1 19 | - name: PDDS 20 | description: Power down deepsleep 21 | bit_offset: 1 22 | bit_size: 1 23 | enum: PDDS 24 | - name: CWUF 25 | description: Clear wakeup flag 26 | bit_offset: 2 27 | bit_size: 1 28 | - name: CSBF 29 | description: Clear standby flag 30 | bit_offset: 3 31 | bit_size: 1 32 | - name: PVDE 33 | description: Power voltage detector enable 34 | bit_offset: 4 35 | bit_size: 1 36 | - name: PLS 37 | description: PVD level selection 38 | bit_offset: 5 39 | bit_size: 3 40 | - name: DBP 41 | description: Disable backup domain write protection 42 | bit_offset: 8 43 | bit_size: 1 44 | - name: FPDS 45 | description: Flash power down in Stop mode 46 | bit_offset: 9 47 | bit_size: 1 48 | fieldset/CSR: 49 | description: power control/status register 50 | fields: 51 | - name: WUF 52 | description: Wakeup flag 53 | bit_offset: 0 54 | bit_size: 1 55 | - name: SBF 56 | description: Standby flag 57 | bit_offset: 1 58 | bit_size: 1 59 | - name: PVDO 60 | description: PVD output 61 | bit_offset: 2 62 | bit_size: 1 63 | - name: BRR 64 | description: Backup regulator ready 65 | bit_offset: 3 66 | bit_size: 1 67 | - name: EWUP 68 | description: Enable WKUP pin 69 | bit_offset: 8 70 | bit_size: 1 71 | - name: BRE 72 | description: Backup regulator enable 73 | bit_offset: 9 74 | bit_size: 1 75 | enum/PDDS: 76 | bit_size: 1 77 | variants: 78 | - name: STOP_MODE 79 | description: Enter Stop mode when the CPU enters deepsleep 80 | value: 0 81 | - name: STANDBY_MODE 82 | description: Enter Standby mode when the CPU enters deepsleep 83 | value: 1 84 | -------------------------------------------------------------------------------- /data/registers/pwr_f3.yaml: -------------------------------------------------------------------------------- 1 | block/PWR: 2 | description: Power control 3 | items: 4 | - name: CR 5 | description: power control register 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: CSR 9 | description: power control/status register 10 | byte_offset: 4 11 | fieldset: CSR 12 | fieldset/CR: 13 | description: power control register 14 | fields: 15 | - name: LPDS 16 | description: Low-power deep sleep 17 | bit_offset: 0 18 | bit_size: 1 19 | - name: PDDS 20 | description: Power down deepsleep 21 | bit_offset: 1 22 | bit_size: 1 23 | enum: PDDS 24 | - name: CWUF 25 | description: Clear wakeup flag 26 | bit_offset: 2 27 | bit_size: 1 28 | - name: CSBF 29 | description: Clear standby flag 30 | bit_offset: 3 31 | bit_size: 1 32 | - name: PVDE 33 | description: Power voltage detector enable 34 | bit_offset: 4 35 | bit_size: 1 36 | - name: PLS 37 | description: PVD level selection 38 | bit_offset: 5 39 | bit_size: 3 40 | - name: DBP 41 | description: Disable backup domain write protection 42 | bit_offset: 8 43 | bit_size: 1 44 | - name: ENSD 45 | description: ENable SD1 ADC 46 | bit_offset: 9 47 | bit_size: 1 48 | array: 49 | len: 3 50 | stride: 1 51 | fieldset/CSR: 52 | description: power control/status register 53 | fields: 54 | - name: WUF 55 | description: Wakeup flag 56 | bit_offset: 0 57 | bit_size: 1 58 | - name: SBF 59 | description: Standby flag 60 | bit_offset: 1 61 | bit_size: 1 62 | - name: PVDO 63 | description: PVD output 64 | bit_offset: 2 65 | bit_size: 1 66 | - name: VREFINTRDYF 67 | description: Internal voltage reference ready flag 68 | bit_offset: 3 69 | bit_size: 1 70 | - name: EWUP 71 | description: Enable WKUP1 pin 72 | bit_offset: 8 73 | bit_size: 1 74 | array: 75 | len: 2 76 | stride: 1 77 | enum/PDDS: 78 | bit_size: 1 79 | variants: 80 | - name: STOP_MODE 81 | description: Enter Stop mode when the CPU enters deepsleep 82 | value: 0 83 | - name: STANDBY_MODE 84 | description: Enter Standby mode when the CPU enters deepsleep 85 | value: 1 86 | -------------------------------------------------------------------------------- /data/registers/crc_v2.yaml: -------------------------------------------------------------------------------- 1 | block/CRC: 2 | description: Cyclic Redundancy Check calculation unit 3 | items: 4 | - name: DR16 5 | description: Data register - half-word sized 6 | byte_offset: 0 7 | bit_size: 16 8 | - name: DR32 9 | description: Data register 10 | byte_offset: 0 11 | - name: DR8 12 | description: Data register - byte sized 13 | byte_offset: 0 14 | bit_size: 8 15 | - name: IDR 16 | description: Independent Data register 17 | byte_offset: 4 18 | - name: CR 19 | description: Control register 20 | byte_offset: 8 21 | fieldset: CR 22 | - name: INIT 23 | description: Initial CRC value 24 | byte_offset: 16 25 | fieldset/CR: 26 | description: Control register 27 | fields: 28 | - name: RESET 29 | description: RESET bit 30 | bit_offset: 0 31 | bit_size: 1 32 | - name: POLYSIZE 33 | description: Polynomial size 34 | bit_offset: 3 35 | bit_size: 2 36 | enum: POLYSIZE 37 | - name: REV_IN 38 | description: Reverse input data 39 | bit_offset: 5 40 | bit_size: 2 41 | enum: REV_IN 42 | - name: REV_OUT 43 | description: Reverse output data 44 | bit_offset: 7 45 | bit_size: 1 46 | enum: REV_OUT 47 | enum/POLYSIZE: 48 | bit_size: 2 49 | variants: 50 | - name: Polysize32 51 | description: 32-bit polynomial 52 | value: 0 53 | - name: Polysize16 54 | description: 16-bit polynomial 55 | value: 1 56 | - name: Polysize8 57 | description: 8-bit polynomial 58 | value: 2 59 | - name: Polysize7 60 | description: 7-bit polynomial 61 | value: 3 62 | enum/REV_IN: 63 | bit_size: 2 64 | variants: 65 | - name: Normal 66 | description: Bit order not affected 67 | value: 0 68 | - name: Byte 69 | description: Bit reversal done by byte 70 | value: 1 71 | - name: HalfWord 72 | description: Bit reversal done by half-word 73 | value: 2 74 | - name: Word 75 | description: Bit reversal done by word 76 | value: 3 77 | enum/REV_OUT: 78 | bit_size: 1 79 | variants: 80 | - name: Normal 81 | description: Bit order not affected 82 | value: 0 83 | - name: Reversed 84 | description: Bit reversed output 85 | value: 1 86 | -------------------------------------------------------------------------------- /d.ps1: -------------------------------------------------------------------------------- 1 | <# #> 2 | param ( 3 | [Parameter(Mandatory = $true)] 4 | [string]$CMD, 5 | 6 | [string]$peri 7 | ) 8 | 9 | $REV = "6069ecbad229a1c5354b0e1274ec2ea0132d7d31" 10 | 11 | Switch ($CMD) { 12 | "download-all" { 13 | rm -r -Force ./sources/ -ErrorAction SilentlyContinue 14 | git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/ 15 | cd ./sources/ 16 | git checkout $REV 17 | cd .. 18 | } 19 | "install-chiptool" { 20 | cargo install --git https://github.com/embassy-rs/chiptool 21 | } 22 | "extract-all" { 23 | rm -r -Force tmp/$peri -ErrorAction SilentlyContinue 24 | mkdir tmp/$peri | Out-Null 25 | 26 | ls sources/svd | foreach-object { 27 | $f = $_.Name.TrimStart("stm32").TrimEnd(".svd") 28 | echo $f 29 | 30 | echo "processing $f ..." 31 | chiptool extract-peripheral --svd "sources/svd/stm32$f.svd" --peripheral "$peri" | Out-File -FilePath "tmp/$peri/$f.yaml" -Encoding ASCII 2> "tmp/$peri/$f.err" 32 | if ($LASTEXITCODE -eq 0) { 33 | rm "tmp/$peri/$f.err" 34 | echo OK 35 | } 36 | else { 37 | rm "tmp/$peri/$f.yaml" 38 | echo FAIL 39 | } 40 | 41 | } 42 | } 43 | "gen" { 44 | rm -r -Force build/data -ErrorAction SilentlyContinue 45 | cargo run --release --bin stm32-data-gen 46 | } 47 | "gen-all" { 48 | rm -r -Force build/data -ErrorAction SilentlyContinue 49 | rm -r -Force build/stm32-metapac -ErrorAction SilentlyContinue 50 | cargo run --release --bin stm32-data-gen 51 | cargo run --release --bin stm32-metapac-gen 52 | cd build/stm32-metapac 53 | 54 | $files = ls -Recurse -Filter '*.rs' | Where-Object { $_.FullName -notmatch 'target' } | % { $_.FullName } | Resolve-Path -Relative 55 | $counter = [pscustomobject] @{ Value = 0 } 56 | $files | Group-Object -Property { [math]::Floor($counter.Value++ / 200 ) } | % { rustfmt --skip-children --unstable-features --edition 2021 $_.Group } 57 | } 58 | default { 59 | echo "unknown command" 60 | } 61 | } -------------------------------------------------------------------------------- /stm32-data-gen/src/registers.rs: -------------------------------------------------------------------------------- 1 | use std::collections::HashMap; 2 | 3 | use anyhow::anyhow; 4 | use chiptool::ir::IR; 5 | use chiptool::validate; 6 | 7 | pub struct Registers { 8 | /// Maps the file name (without the .yaml extension) to the IR object which is parsed from the mcu .svd file 9 | pub registers: HashMap, 10 | } 11 | 12 | impl Registers { 13 | pub fn parse() -> Result { 14 | let mut registers = HashMap::new(); 15 | 16 | for f in glob::glob("data/registers/*")? { 17 | let f = f?; 18 | let ff = f 19 | .file_name() 20 | .unwrap() 21 | .to_string_lossy() 22 | .strip_suffix(".yaml") 23 | .unwrap() 24 | .to_string(); 25 | let ir: IR = serde_yaml::from_str(&std::fs::read_to_string(&f)?) 26 | .map_err(|e| anyhow!("failed to parse {f:?}: {e:?}"))?; 27 | 28 | // validate yaml file 29 | // we allow register overlap and field overlap for now 30 | let validate_option = validate::Options { 31 | allow_register_overlap: true, 32 | allow_field_overlap: true, 33 | allow_enum_dup_value: false, 34 | allow_unused_enums: false, 35 | allow_unused_fieldsets: false, 36 | }; 37 | let err_vec = validate::validate(&ir, validate_option); 38 | let err_string = err_vec.iter().fold(String::new(), |mut acc, cur| { 39 | acc.push_str(cur); 40 | acc.push('\n'); 41 | acc 42 | }); 43 | 44 | if !err_string.is_empty() { 45 | return Err(anyhow!(format!("\n{ff}:\n{err_string}"))); 46 | } 47 | 48 | registers.insert(ff, ir); 49 | } 50 | 51 | Ok(Self { registers }) 52 | } 53 | 54 | pub fn write(&self) -> Result<(), anyhow::Error> { 55 | std::fs::create_dir_all("build/data/registers")?; 56 | 57 | for (name, ir) in &self.registers { 58 | let dump = serde_json::to_string_pretty(ir)?; 59 | std::fs::write(format!("build/data/registers/{name}.json"), dump)?; 60 | } 61 | Ok(()) 62 | } 63 | } 64 | -------------------------------------------------------------------------------- /data/registers/crc_v3.yaml: -------------------------------------------------------------------------------- 1 | block/CRC: 2 | description: Cyclic Redundancy Check calculation unit 3 | items: 4 | - name: DR16 5 | description: Data register - half-word sized 6 | byte_offset: 0 7 | bit_size: 16 8 | - name: DR32 9 | description: Data register 10 | byte_offset: 0 11 | - name: DR8 12 | description: Data register - byte sized 13 | byte_offset: 0 14 | bit_size: 8 15 | - name: IDR 16 | description: Independent Data register 17 | byte_offset: 4 18 | - name: CR 19 | description: Control register 20 | byte_offset: 8 21 | fieldset: CR 22 | - name: INIT 23 | description: Initial CRC value 24 | byte_offset: 16 25 | - name: POL 26 | description: CRC polynomial 27 | byte_offset: 20 28 | fieldset/CR: 29 | description: Control register 30 | fields: 31 | - name: RESET 32 | description: RESET bit 33 | bit_offset: 0 34 | bit_size: 1 35 | - name: POLYSIZE 36 | description: Polynomial size 37 | bit_offset: 3 38 | bit_size: 2 39 | enum: POLYSIZE 40 | - name: REV_IN 41 | description: Reverse input data 42 | bit_offset: 5 43 | bit_size: 2 44 | enum: REV_IN 45 | - name: REV_OUT 46 | description: Reverse output data 47 | bit_offset: 7 48 | bit_size: 1 49 | enum: REV_OUT 50 | enum/POLYSIZE: 51 | bit_size: 2 52 | variants: 53 | - name: Polysize32 54 | description: 32-bit polynomial 55 | value: 0 56 | - name: Polysize16 57 | description: 16-bit polynomial 58 | value: 1 59 | - name: Polysize8 60 | description: 8-bit polynomial 61 | value: 2 62 | - name: Polysize7 63 | description: 7-bit polynomial 64 | value: 3 65 | enum/REV_IN: 66 | bit_size: 2 67 | variants: 68 | - name: Normal 69 | description: Bit order not affected 70 | value: 0 71 | - name: Byte 72 | description: Bit reversal done by byte 73 | value: 1 74 | - name: HalfWord 75 | description: Bit reversal done by half-word 76 | value: 2 77 | - name: Word 78 | description: Bit reversal done by word 79 | value: 3 80 | enum/REV_OUT: 81 | bit_size: 1 82 | variants: 83 | - name: Normal 84 | description: Bit order not affected 85 | value: 0 86 | - name: Reversed 87 | description: Bit reversed output 88 | value: 1 89 | -------------------------------------------------------------------------------- /data/registers/ipcc_v1.yaml: -------------------------------------------------------------------------------- 1 | block/IPCC: 2 | description: IPCC 3 | items: 4 | - name: CPU 5 | description: CPU specific registers 6 | array: 7 | len: 2 8 | stride: 16 9 | byte_offset: 0 10 | block: IPCC_CPU 11 | block/IPCC_CPU: 12 | description: IPCC 13 | items: 14 | - name: CR 15 | description: Control register CPUx 16 | byte_offset: 0 17 | fieldset: CxCR 18 | - name: MR 19 | description: Mask register CPUx 20 | byte_offset: 4 21 | fieldset: CxMR 22 | - name: SCR 23 | description: Status Set or Clear register CPUx 24 | byte_offset: 8 25 | access: Write 26 | fieldset: CxSCR 27 | - name: SR 28 | description: CPUx to CPUy status register 29 | byte_offset: 12 30 | access: Read 31 | fieldset: CxTOySR 32 | fieldset/CxCR: 33 | description: Control register CPUx 34 | fields: 35 | - name: RXOIE 36 | description: processor x Receive channel occupied interrupt enable 37 | bit_offset: 0 38 | bit_size: 1 39 | - name: TXFIE 40 | description: processor x Transmit channel free interrupt enable 41 | bit_offset: 16 42 | bit_size: 1 43 | fieldset/CxMR: 44 | description: Mask register CPUx 45 | fields: 46 | - name: CHOM 47 | description: processor x Receive channel y occupied interrupt enable 48 | bit_offset: 0 49 | bit_size: 1 50 | array: 51 | len: 6 52 | stride: 1 53 | - name: CHFM 54 | description: processor x Transmit channel y free interrupt mask 55 | bit_offset: 16 56 | bit_size: 1 57 | array: 58 | len: 6 59 | stride: 1 60 | fieldset/CxSCR: 61 | description: Status Set or Clear register CPUx 62 | fields: 63 | - name: CHC 64 | description: processor x Receive channel y status clear 65 | bit_offset: 0 66 | bit_size: 1 67 | array: 68 | len: 6 69 | stride: 1 70 | - name: CHS 71 | description: processor x Transmit channel y status set 72 | bit_offset: 16 73 | bit_size: 1 74 | array: 75 | len: 6 76 | stride: 1 77 | fieldset/CxTOySR: 78 | description: CPUx to CPUy status register 79 | fields: 80 | - name: CHF 81 | description: processor x transmit to process y Receive channel z status flag 82 | bit_offset: 0 83 | bit_size: 1 84 | array: 85 | len: 6 86 | stride: 1 87 | -------------------------------------------------------------------------------- /data/registers/dbgmcu_c0.yaml: -------------------------------------------------------------------------------- 1 | block/DBGMCU: 2 | description: Debug support 3 | items: 4 | - name: IDCODE 5 | description: MCU Device ID Code Register 6 | byte_offset: 0 7 | access: Read 8 | fieldset: IDCODE 9 | - name: CR 10 | description: Debug MCU Configuration Register 11 | byte_offset: 4 12 | fieldset: CR 13 | - name: APB1FZR 14 | description: DBG APB freeze register 1 15 | byte_offset: 8 16 | fieldset: APB1FZR 17 | - name: APB2FZR 18 | description: DBG APB freeze register 2 19 | byte_offset: 12 20 | fieldset: APB2FZR 21 | fieldset/APB1FZR: 22 | description: DBG APB freeze register 1 23 | fields: 24 | - name: TIM3 25 | description: TIM3 counter stopped when core is halted 26 | bit_offset: 1 27 | bit_size: 1 28 | - name: RTC 29 | description: Debug RTC stopped when Core is halted 30 | bit_offset: 10 31 | bit_size: 1 32 | - name: WWDG 33 | description: Debug Window Wachdog stopped when Core is halted 34 | bit_offset: 11 35 | bit_size: 1 36 | - name: IWDG 37 | description: Debug Independent Wachdog stopped when Core is halted 38 | bit_offset: 12 39 | bit_size: 1 40 | - name: I2C1 41 | description: I2C1 SMBUS timeout mode stopped when core is halted 42 | bit_offset: 21 43 | bit_size: 1 44 | fieldset/APB2FZR: 45 | description: DBG APB freeze register 2 46 | fields: 47 | - name: TIM1 48 | description: TIM1 49 | bit_offset: 11 50 | bit_size: 1 51 | - name: TIM14 52 | description: TIM14 53 | bit_offset: 15 54 | bit_size: 1 55 | - name: TIM16 56 | description: TIM16 57 | bit_offset: 17 58 | bit_size: 1 59 | - name: TIM17 60 | description: TIM17 61 | bit_offset: 18 62 | bit_size: 1 63 | fieldset/CR: 64 | description: Debug MCU Configuration Register 65 | fields: 66 | - name: DBG_STOP 67 | description: Debug Stop Mode 68 | bit_offset: 1 69 | bit_size: 1 70 | - name: DBG_STANDBY 71 | description: Debug Standby Mode 72 | bit_offset: 2 73 | bit_size: 1 74 | fieldset/IDCODE: 75 | description: MCU Device ID Code Register 76 | fields: 77 | - name: DEV_ID 78 | description: Device Identifier 79 | bit_offset: 0 80 | bit_size: 16 81 | - name: REV_ID 82 | description: Revision Identifier 83 | bit_offset: 16 84 | bit_size: 16 85 | -------------------------------------------------------------------------------- /.github/ci/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ## on push branch~=gh-readonly-queue/main/.* 3 | ## on pull_request 4 | 5 | set -euxo pipefail 6 | 7 | # prevent "fatal: gc is already running" errors 8 | git config --global gc.autoDetach false 9 | 10 | export RUSTUP_HOME=/ci/cache/rustup 11 | export CARGO_HOME=/ci/cache/cargo 12 | export CARGO_TARGET_DIR=/ci/cache/target 13 | 14 | hashtime restore /ci/cache/filetime.json || true 15 | hashtime save /ci/cache/filetime.json 16 | 17 | cargo fmt -- --check 18 | 19 | # clone stm32-data-generated at the merge base 20 | # so the diff will show this PR's effect 21 | git remote add upstream https://github.com/embassy-rs/stm32-data 22 | git fetch --depth 15 upstream main 23 | if git branch --remote --contains HEAD | grep upstream/main; then 24 | echo "on base branch" 25 | else 26 | echo "not on base branch" 27 | git pull -q upstream main 28 | fi 29 | set +e 30 | git clone --depth 1 --branch stm32-data-$(git merge-base HEAD upstream/main) https://github.com/embassy-rs/stm32-data-generated/ build -q 31 | DIFF_OK=$? 32 | set -e 33 | 34 | # move the sources directory out of the cache if it exists 35 | mv /ci/cache/sources ./sources || true 36 | 37 | ./d ci 38 | ./d check 39 | 40 | # move the sources directory into the cache 41 | mv ./sources /ci/cache/sources 42 | 43 | if [ $DIFF_OK -eq 0 ]; then 44 | # upload diff 45 | ( 46 | cd build 47 | git add . 48 | git diff --staged --color data | aha --black > /ci/artifacts/diff.html 49 | ) 50 | 51 | cat > /ci/comment.md < /ci/comment.md < {{ 21 | ::ref_thread_local::ref_thread_local! { 22 | static managed REGEX: ::regex::Regex = ::regex::Regex::new($re).unwrap(); 23 | } 24 | >::borrow(®EX) 25 | }}; 26 | } 27 | 28 | struct Stopwatch { 29 | start: std::time::Instant, 30 | section_start: Option, 31 | } 32 | 33 | impl Stopwatch { 34 | fn new() -> Self { 35 | eprintln!("Starting timer"); 36 | let start = std::time::Instant::now(); 37 | Self { 38 | start, 39 | section_start: None, 40 | } 41 | } 42 | 43 | fn section(&mut self, status: &str) { 44 | let now = std::time::Instant::now(); 45 | self.print_done(now); 46 | eprintln!(" {status}"); 47 | self.section_start = Some(now); 48 | } 49 | 50 | fn stop(self) { 51 | let now = std::time::Instant::now(); 52 | self.print_done(now); 53 | let total_elapsed = now - self.start; 54 | eprintln!("Total time: {:.2} seconds", total_elapsed.as_secs_f32()); 55 | } 56 | 57 | fn print_done(&self, now: std::time::Instant) { 58 | if let Some(section_start) = self.section_start { 59 | let elapsed = now - section_start; 60 | eprintln!(" done in {:.2} seconds", elapsed.as_secs_f32()); 61 | } 62 | } 63 | } 64 | 65 | fn main() -> anyhow::Result<()> { 66 | pretty_env_logger::init(); 67 | 68 | let mut stopwatch = Stopwatch::new(); 69 | 70 | stopwatch.section("Parsing headers"); 71 | let headers = header::Headers::parse()?; 72 | 73 | stopwatch.section("Parsing other stuff"); 74 | 75 | // stopwatch.section("Parsing registers"); 76 | let registers = registers::Registers::parse()?; 77 | registers.write()?; 78 | 79 | // stopwatch.section("Parsing interrupts"); 80 | let chip_interrupts = interrupts::ChipInterrupts::parse()?; 81 | 82 | // stopwatch.section("Parsing RCC registers"); 83 | let peripheral_to_clock = rcc::ParsedRccs::parse(®isters)?; 84 | 85 | // stopwatch.section("Parsing docs"); 86 | let docs = docs::Docs::parse()?; 87 | 88 | // stopwatch.section("Parsing DMA"); 89 | let dma_channels = dma::DmaChannels::parse()?; 90 | 91 | // stopwatch.section("Parsing GPIO AF"); 92 | let af = gpio_af::Af::parse()?; 93 | 94 | stopwatch.section("Parsing chip groups"); 95 | let (chips, chip_groups) = chips::parse_groups()?; 96 | 97 | stopwatch.section("Processing chips"); 98 | generator::dump_all_chips( 99 | chip_groups, 100 | headers, 101 | af, 102 | chip_interrupts, 103 | peripheral_to_clock, 104 | dma_channels, 105 | chips, 106 | docs, 107 | )?; 108 | 109 | stopwatch.stop(); 110 | 111 | Ok(()) 112 | } 113 | -------------------------------------------------------------------------------- /data/registers/dbgmcu_f0.yaml: -------------------------------------------------------------------------------- 1 | block/DBGMCU: 2 | description: Debug support 3 | items: 4 | - name: IDCODE 5 | description: MCU Device ID Code Register 6 | byte_offset: 0 7 | access: Read 8 | fieldset: IDCODE 9 | - name: CR 10 | description: Debug MCU Configuration Register 11 | byte_offset: 4 12 | fieldset: CR 13 | - name: APB1_FZ 14 | description: Debug MCU APB1 freeze register 15 | byte_offset: 8 16 | fieldset: APB1_FZ 17 | - name: APB2_FZ 18 | description: Debug MCU APB2 freeze register 19 | byte_offset: 12 20 | fieldset: APB2_FZ 21 | fieldset/APB1_FZ: 22 | description: Debug MCU APB1 freeze register 23 | fields: 24 | - name: TIM2 25 | description: TIM2 counter stopped when core is halted 26 | bit_offset: 0 27 | bit_size: 1 28 | - name: TIM3 29 | description: TIM3 counter stopped when core is halted 30 | bit_offset: 1 31 | bit_size: 1 32 | - name: TIM6 33 | description: TIM6 counter stopped when core is halted 34 | bit_offset: 4 35 | bit_size: 1 36 | - name: TIM7 37 | description: TIM7 counter stopped when core is halted 38 | bit_offset: 5 39 | bit_size: 1 40 | - name: TIM14 41 | description: TIM14 counter stopped when core is halted 42 | bit_offset: 8 43 | bit_size: 1 44 | - name: RTC 45 | description: Debug RTC stopped when core is halted 46 | bit_offset: 10 47 | bit_size: 1 48 | - name: WWDG 49 | description: Debug window watchdog stopped when core is halted 50 | bit_offset: 11 51 | bit_size: 1 52 | - name: IWDG 53 | description: Debug independent watchdog stopped when core is halted 54 | bit_offset: 12 55 | bit_size: 1 56 | - name: DBG_I2C1_SMBUS_TIMEOUT 57 | description: SMBUS timeout mode stopped when core is halted 58 | bit_offset: 21 59 | bit_size: 1 60 | - name: CAN 61 | description: CAN stopped when core is halted 62 | bit_offset: 25 63 | bit_size: 1 64 | fieldset/APB2_FZ: 65 | description: Debug MCU APB2 freeze register 66 | fields: 67 | - name: TIM1 68 | description: TIM1 counter stopped when core is halted 69 | bit_offset: 11 70 | bit_size: 1 71 | - name: TIM15 72 | description: TIM15 counter stopped when core is halted 73 | bit_offset: 16 74 | bit_size: 1 75 | - name: TIM16 76 | description: TIM16 counter stopped when core is halted 77 | bit_offset: 17 78 | bit_size: 1 79 | - name: TIM17 80 | description: TIM17 counter stopped when core is halted 81 | bit_offset: 18 82 | bit_size: 1 83 | fieldset/CR: 84 | description: Debug MCU Configuration Register 85 | fields: 86 | - name: DBG_STOP 87 | description: Debug Stop Mode 88 | bit_offset: 1 89 | bit_size: 1 90 | - name: DBG_STANDBY 91 | description: Debug Standby Mode 92 | bit_offset: 2 93 | bit_size: 1 94 | fieldset/IDCODE: 95 | description: MCU Device ID Code Register 96 | fields: 97 | - name: DEV_ID 98 | description: Device Identifier 99 | bit_offset: 0 100 | bit_size: 12 101 | - name: DIV_ID 102 | description: Division Identifier 103 | bit_offset: 12 104 | bit_size: 4 105 | - name: REV_ID 106 | description: Revision Identifier 107 | bit_offset: 16 108 | bit_size: 16 109 | -------------------------------------------------------------------------------- /data/registers/hash_v2.yaml: -------------------------------------------------------------------------------- 1 | block/HASH: 2 | description: Hash processor. 3 | items: 4 | - name: CR 5 | description: control register. 6 | byte_offset: 0 7 | fieldset: CR 8 | - name: DIN 9 | description: data input register. 10 | byte_offset: 4 11 | access: Write 12 | - name: STR 13 | description: start register. 14 | byte_offset: 8 15 | fieldset: STR 16 | - name: HRA 17 | description: digest registers. 18 | array: 19 | len: 5 20 | stride: 4 21 | byte_offset: 12 22 | access: Read 23 | - name: IMR 24 | description: interrupt enable register. 25 | byte_offset: 32 26 | fieldset: IMR 27 | - name: SR 28 | description: status register. 29 | byte_offset: 36 30 | fieldset: SR 31 | - name: CSR 32 | description: context swap registers. 33 | array: 34 | len: 54 35 | stride: 4 36 | byte_offset: 248 37 | - name: HR 38 | description: HASH digest register. 39 | array: 40 | len: 8 41 | stride: 4 42 | byte_offset: 784 43 | access: Read 44 | fieldset/CR: 45 | description: control register. 46 | fields: 47 | - name: INIT 48 | description: Initialize message digest calculation. 49 | bit_offset: 2 50 | bit_size: 1 51 | - name: DMAE 52 | description: DMA enable. 53 | bit_offset: 3 54 | bit_size: 1 55 | - name: DATATYPE 56 | description: Data type selection. 57 | bit_offset: 4 58 | bit_size: 2 59 | - name: MODE 60 | description: Mode selection. 61 | bit_offset: 6 62 | bit_size: 1 63 | - name: ALGO0 64 | description: Algorithm selection. 65 | bit_offset: 7 66 | bit_size: 1 67 | - name: NBW 68 | description: Number of words already pushed. 69 | bit_offset: 8 70 | bit_size: 4 71 | - name: DINNE 72 | description: DIN not empty. 73 | bit_offset: 12 74 | bit_size: 1 75 | - name: MDMAT 76 | description: Multiple DMA Transfers. 77 | bit_offset: 13 78 | bit_size: 1 79 | - name: LKEY 80 | description: Long key selection. 81 | bit_offset: 16 82 | bit_size: 1 83 | - name: ALGO1 84 | description: ALGO. 85 | bit_offset: 18 86 | bit_size: 1 87 | fieldset/IMR: 88 | description: interrupt enable register. 89 | fields: 90 | - name: DINIE 91 | description: Data input interrupt enable. 92 | bit_offset: 0 93 | bit_size: 1 94 | - name: DCIE 95 | description: Digest calculation completion interrupt enable. 96 | bit_offset: 1 97 | bit_size: 1 98 | fieldset/SR: 99 | description: status register. 100 | fields: 101 | - name: DINIS 102 | description: Data input interrupt status. 103 | bit_offset: 0 104 | bit_size: 1 105 | - name: DCIS 106 | description: Digest calculation completion interrupt status. 107 | bit_offset: 1 108 | bit_size: 1 109 | - name: DMAS 110 | description: DMA Status. 111 | bit_offset: 2 112 | bit_size: 1 113 | - name: BUSY 114 | description: Busy bit. 115 | bit_offset: 3 116 | bit_size: 1 117 | fieldset/STR: 118 | description: start register. 119 | fields: 120 | - name: NBLW 121 | description: Number of valid bits in the last word of the message. 122 | bit_offset: 0 123 | bit_size: 5 124 | - name: DCAL 125 | description: Digest calculation. 126 | bit_offset: 8 127 | bit_size: 1 128 | -------------------------------------------------------------------------------- /data/registers/exti_n6.yaml: -------------------------------------------------------------------------------- 1 | block/EXTI: 2 | description: Extended interrupts and event controller. 3 | items: 4 | - name: RTSR 5 | description: EXTI rising trigger selection register. 6 | array: 7 | len: 3 8 | stride: 32 9 | byte_offset: 0 10 | fieldset: LINES 11 | - name: FTSR 12 | description: EXTI falling trigger selection register. 13 | array: 14 | len: 3 15 | stride: 32 16 | byte_offset: 4 17 | fieldset: LINES 18 | - name: SWIER 19 | description: EXTI software interrupt event register. 20 | array: 21 | len: 3 22 | stride: 32 23 | byte_offset: 8 24 | fieldset: LINES 25 | - name: RPR 26 | description: EXTI rising edge pending register. 27 | array: 28 | len: 3 29 | stride: 32 30 | byte_offset: 12 31 | fieldset: LINES 32 | - name: FPR 33 | description: EXTI falling edge pending register. 34 | array: 35 | len: 3 36 | stride: 32 37 | byte_offset: 16 38 | fieldset: LINES 39 | - name: SECCFGR 40 | description: EXTI security configuration register. 41 | array: 42 | len: 3 43 | stride: 32 44 | byte_offset: 20 45 | fieldset: SEC 46 | - name: PRIVCFGR 47 | description: EXTI privilege configuration register. 48 | array: 49 | len: 3 50 | stride: 32 51 | byte_offset: 24 52 | fieldset: PRIV 53 | - name: EXTICR 54 | description: EXTI external interrupt selection register 1. 55 | array: 56 | len: 4 57 | stride: 4 58 | byte_offset: 96 59 | fieldset: EXTI 60 | - name: LOCKR 61 | description: EXTI lock register. 62 | byte_offset: 112 63 | fieldset: LOCKR 64 | - name: IMR 65 | description: EXTI CPU wake-up with interrupt mask register 1. 66 | array: 67 | len: 3 68 | stride: 16 69 | byte_offset: 128 70 | fieldset: LINES 71 | - name: EMR 72 | description: EXTI CPU wake-up with event mask register 1. 73 | array: 74 | len: 3 75 | stride: 16 76 | byte_offset: 132 77 | fieldset: LINES 78 | fieldset/EXTI: 79 | description: EXTI external interrupt selection register 1. 80 | fields: 81 | - name: EXTI 82 | description: EXTI GPIO port selection. 83 | bit_offset: 0 84 | bit_size: 16 85 | array: 86 | len: 4 87 | stride: 8 88 | fieldset/LOCKR: 89 | description: EXTI lock register. 90 | fields: 91 | - name: LOCK 92 | description: Global security privilege SECCFGRx/PRIVCFGRx. 93 | bit_offset: 0 94 | bit_size: 1 95 | fieldset/PRIV: 96 | description: EXTI privilege configuration register. 97 | fields: 98 | - name: PRIV 99 | description: Privilege enable on event input x. 100 | bit_offset: 0 101 | bit_size: 1 102 | array: 103 | len: 32 104 | stride: 1 105 | fieldset/SEC: 106 | description: EXTI security configuration register. 107 | fields: 108 | - name: SEC 109 | description: Security enable on event input x. 110 | bit_offset: 0 111 | bit_size: 1 112 | array: 113 | len: 32 114 | stride: 1 115 | fieldset/LINES: 116 | description: EXTI lines register, 1 bit per line 117 | fields: 118 | - name: LINE 119 | description: EXTI line 120 | bit_offset: 0 121 | bit_size: 1 122 | array: 123 | len: 32 124 | stride: 1 125 | -------------------------------------------------------------------------------- /stm32-data-gen/src/low_power.rs: -------------------------------------------------------------------------------- 1 | use stm32_data_serde::chip::core::peripheral::rcc::StopMode; 2 | 3 | use crate::util::RegexMap; 4 | 5 | /// Get the stop mode limit for a peripheral based on the MCU and peripheral name. 6 | /// Determines the lowest possible stop mode when a peripheral is enabled. 7 | /// 8 | /// Parameters: 9 | /// - mcu_name: the full name of the MCU (e.g., "STM32WB55RG") 10 | /// - peripheral: the name of the peripheral (e.g., "USART1") 11 | pub(crate) fn peripheral_stop_mode_info(mcu_name: &str, peripheral: &str) -> Option { 12 | /// Regexmap where the key is mcu_name:peripheral and the value is the stop mode. 13 | /// Example: STM32WB55RG:USART1 -> StopMode::Stop2 14 | #[rustfmt::skip] 15 | static STOP_MODE_OVERRIDE_RULES: RegexMap = RegexMap::new(&[ 16 | (r"^STM32WB55.*:LPTIM1", StopMode::Standby), 17 | (r"^STM32WB55.*:USART1", StopMode::Stop2), 18 | (r"^STM32WB55.*:LPUART1", StopMode::Standby), 19 | (r"^STM32WB55.*:I2C1", StopMode::Stop2), 20 | (r"^STM32WB55.*:I2C3", StopMode::Standby), 21 | (r"^STM32WLE5.*:LPUART1", StopMode::Standby), 22 | (r"^STM32WLE5.*:I2C1", StopMode::Stop2), 23 | (r"^STM32WLE5.*:I2C2", StopMode::Stop2), 24 | (r"^STM32WLE5.*:I2C3", StopMode::Standby), 25 | (r"^STM32WLE5.*:LPTIM1", StopMode::Standby), 26 | (r"^STM32WLE5.*:SUBGHZSPI", StopMode::Stop2), 27 | (r"^STM32WLE5.*:ADC1", StopMode::Stop2), 28 | 29 | (r"^STM32WL55.*:LPUART1", StopMode::Standby), 30 | (r"^STM32WL55.*:I2C1", StopMode::Stop2), 31 | (r"^STM32WL55.*:I2C2", StopMode::Stop2), 32 | (r"^STM32WL55.*:I2C3", StopMode::Standby), 33 | (r"^STM32WL55.*:LPTIM1", StopMode::Standby), 34 | (r"^STM32WL55.*:SUBGHZSPI", StopMode::Stop2), 35 | (r"^STM32WL55.*:ADC1", StopMode::Stop2), 36 | 37 | (r"^STM32U3.*:GPDMA.*", StopMode::Stop2), 38 | (r"^STM32U3.*:LPDMA.*", StopMode::Standby), 39 | (r"^STM32U5.*:GPDMA.*", StopMode::Stop2), 40 | (r"^STM32U5.*:LPDMA.*", StopMode::Standby), 41 | 42 | // __ATTENTION__: Keep these rules at the bottom to grant precedence to the more specific rules above 43 | // Every peripheral with LP prefix is assumed to be able enter up to Stop1 mode 44 | (r".*:LP.*", StopMode::Stop2), 45 | // The RTC peripheral is assumed to be able to enter up to Stop2 mode 46 | (r".*:RTC", StopMode::Standby), 47 | ]); 48 | 49 | STOP_MODE_OVERRIDE_RULES 50 | .get(&format!("{mcu_name}:{peripheral}")) 51 | .cloned() 52 | } 53 | 54 | #[cfg(test)] 55 | mod tests { 56 | use super::*; 57 | 58 | #[test] 59 | fn test_get_peripheral_stop_mode_info() { 60 | // MCU independent rule for RTC 61 | assert_eq!(peripheral_stop_mode_info("my-test-mcu", "RTC"), Some(StopMode::Standby)); 62 | 63 | // No rule for this but starting with LP prefix, so assumed to be Stop2 64 | assert_eq!( 65 | peripheral_stop_mode_info("my-test-mcu", "LPTIM2"), 66 | Some(StopMode::Stop2) 67 | ); 68 | 69 | // MCU independent rule for RTC. Must match RTC exactly 70 | assert_eq!(peripheral_stop_mode_info("my-test-mcu", "RTC1"), None); 71 | 72 | // Rule covering all STM32WB55 for LPTIM1 73 | assert_eq!( 74 | peripheral_stop_mode_info("STM32WB55RG", "LPTIM1"), 75 | Some(StopMode::Standby) 76 | ); 77 | } 78 | } 79 | --------------------------------------------------------------------------------