├── .gitignore ├── LICENSE.GPL3 ├── LICENSE.solderpad ├── README.md ├── alu.sv ├── alu_div.sv ├── compressed_decoder.sv ├── controller.sv ├── cs_registers.sv ├── debug_unit.sv ├── decoder.sv ├── docs └── datasheet │ ├── .gitignore │ ├── Makefile │ ├── content │ ├── aluext.tex │ ├── csr.tex │ ├── debug.tex │ ├── exceptions.tex │ ├── hwloop.tex │ ├── if.tex │ ├── lsu.tex │ ├── mac.tex │ ├── overview.tex │ ├── perfcounters.tex │ ├── pipeline.tex │ ├── rf.tex │ └── title.tex │ ├── datasheet.tex │ ├── figures │ └── .gitignore │ ├── figures_raw │ ├── events.obj │ ├── pipeline.obj │ └── ri5cy_overview.obj │ └── preamble │ └── preamble.tex ├── ex_stage.sv ├── exc_controller.sv ├── hwloop_controller.sv ├── hwloop_regs.sv ├── id_stage.sv ├── if_stage.sv ├── include ├── riscv_config.sv ├── riscv_defines.sv └── riscv_tracer_defines.sv ├── load_store_unit.sv ├── mult.sv ├── prefetch_L0_buffer.sv ├── prefetch_buffer.sv ├── register_file.sv ├── register_file_ff.sv ├── riscv_core.sv ├── riscv_simchecker.sv ├── riscv_tracer.sv ├── src_files.yml ├── tb └── serDiv │ ├── scripts │ ├── compile.sh │ ├── sim.sh │ ├── tb.do │ ├── tb_nogui.do │ └── wave.do │ ├── tb.sv │ ├── tb_div.sv │ ├── tb_rem.sv │ ├── tb_udiv.sv │ └── tb_urem.sv └── verilator-model ├── .gitignore ├── Makefile ├── cluster_clock_gating.sv ├── dp_ram.sv ├── ram.sv ├── testbench.cpp └── top.sv /.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | -------------------------------------------------------------------------------- /LICENSE.GPL3: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/embecosm/ri5cy/HEAD/LICENSE.GPL3 -------------------------------------------------------------------------------- /LICENSE.solderpad: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/embecosm/ri5cy/HEAD/LICENSE.solderpad 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