├── Cfg └── Template │ ├── can_cfg.c │ └── can_cfg.h ├── Drivers ├── ADSPBF537 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── Kinetis_Kxx │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── LM3S9B96 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── LPC21XX │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── LPC22XX │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── LPC24XX │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── MB96F340 │ ├── drv_can.c │ ├── drv_can.h │ ├── drv_can_reg.c │ └── drv_can_reg.h ├── MCF5485C │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── MPC5200B │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── MPC5554 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── RM48L950 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── RX200 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── RX600 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── SJA1000 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── STM32F10X │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── STM32F20X │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── STM32F4XX │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── STR91X │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── TMS28XX │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── Template │ ├── BSP │ │ └── Template │ │ │ ├── can_bsp.c │ │ │ └── can_bsp.h │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── V850E2Fx4 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── XC167CI │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── ZC7xxx │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── drv_def.h └── iMX6 │ ├── drv_can.c │ ├── drv_can.h │ └── drv_can_reg.h ├── Examples ├── NONE │ ├── can_demo.c │ └── can_demo.h ├── uCOS-II │ ├── can_demo.c │ └── can_demo.h └── uCOS-III │ ├── can_demo.c │ └── can_demo.h ├── OS ├── NONE │ ├── can_os.c │ └── can_os.h ├── uCOS-II │ ├── can_os.c │ └── can_os.h └── uCOS-III │ ├── can_os.c │ └── can_os.h ├── README.md ├── Source ├── can_bus.c ├── can_bus.h ├── can_drv.h ├── can_err.h ├── can_frm.c ├── can_frm.h ├── can_msg.c ├── can_msg.h ├── can_sig.c └── can_sig.h └── license.txt /Drivers/ADSPBF537/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_CAN_REG_H_ 27 | #define _DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | #include "cpu.h" 35 | 36 | /* 37 | **************************************************************************************************** 38 | * DEFINES 39 | **************************************************************************************************** 40 | */ 41 | 42 | #define ADSPBF537_CAN0_BASE_ADDR (CPU_REG32 *)0xFFC02A00 43 | 44 | 45 | 46 | /*------------------------------------------------------------------------------------------------*/ 47 | /*! 48 | * \brief BIT DEFINITIONS 49 | * \ingroup ADSPBF537_CAN 50 | * 51 | * This member holds a bit defintions for various registers of ADSPBF537 52 | */ 53 | /*------------------------------------------------------------------------------------------------*/ 54 | 55 | #define CAN_PORT_MUX *(CPU_REG16 *)0xFFC0320C /* Port Multiplexer Control Register */ 56 | #define CAN_PJCE 0x0002 /* Enable CAN RX/TX */ 57 | #define CAN_PJCE_MASK 0x0006 /* CAN RX/TX mask */ 58 | 59 | #define CAN_SIC_IAR0 *(CPU_REG32 *)0xFFC00110 /* Interrupt Assignment register */ 60 | #define CAN_SIC_IAR1 *(CPU_REG32 *)0xFFC00114 61 | #define CAN_SIC_IAR2 *(CPU_REG32 *)0xFFC00118 62 | /* Interrupt Mask Register */ 63 | #define CAN_SIC_IMASK *(CPU_REG32 *)0xFFC0010C 64 | #define CAN_SIC_IMASK_TX_IRQ 0x00010000 65 | #define CAN_SIC_IMASK_RX_IRQ 0x00008000 66 | #define CAN_SIC_IMASK_ERR_IRQ 0x00000004 67 | 68 | 69 | #define CAN_CONTROL_CCR 0x0080 /* CAN Configuration Mode Request */ 70 | 71 | #define CAN_STATUS_CCA 0x0080 /* CAN Configuration mode acknowledge */ 72 | #define CAN_STATUS_WTR 0x0003 /* CAN Warning flags RX/TX */ 73 | #define CAN_STATUS_EP 0x0004 /* CAN Error passive flag */ 74 | #define CAN_STATUS_EBO 0x0008 /* CAN Bus Off flag */ 75 | 76 | #define CAN_MB_ID1_IDE 0x2000 /* Identifier Extension (IDE) bit */ 77 | #define CAN_MB_ID1_RTR 0x4000 /* Remote transmission request bit */ 78 | #define CAN_MB_ID1_AME 0x8000 /* Acceptance Mask Identification bit */ 79 | 80 | #define CAN_AMxx_AMIDE 0x2000 /* Acceptance Mask IDE bit */ 81 | 82 | #define CAN_GIM_EPIM 0x0004 /* Error Passive Interrupt */ 83 | #define CAN_GIM_BOIM 0x0008 /* Bus Off Interrupt */ 84 | 85 | #define CAN_GIS_EPIS 0x0004 /* CAN Error passive flag */ 86 | #define CAN_GIS_EBOIS 0x0008 /* CAN Bus Off flag */ 87 | 88 | /* 89 | **************************************************************************************************** 90 | * DATA TYPES 91 | **************************************************************************************************** 92 | */ 93 | 94 | /*------------------------------------------------------------------------------------------------*/ 95 | /*! 96 | * \brief REGISTER LAYOUT CAN MODULE OF ADSPBF537 97 | * \ingroup ADSPBF537_CAN 98 | * 99 | * This definition holds the register layout of the CAN module of ADSPBF537. For detailed 100 | * register descriptions please refer to the reference manual. 101 | */ 102 | /*------------------------------------------------------------------------------------------------*/ 103 | 104 | /* Mailbox Registers */ 105 | 106 | typedef struct { 107 | CPU_INT16U AM_x_L; /* Mailbox 0 Low Acceptance Mask */ 108 | CPU_INT16U Spare43; 109 | CPU_INT16U AM_x_H; /* Mailbox 0 Low Acceptance Mask */ 110 | CPU_INT16U Spare44; 111 | } CAN_MB_ACC; 112 | 113 | /* 0xFFC02C00 -- 0xFFC02FFC */ 114 | typedef struct { 115 | CPU_INT16U DATA0; /* Mailbox Data Word 0 [15:0] Register */ 116 | CPU_INT16U Spare45; 117 | CPU_INT16U DATA1; /* Mailbox Data Word 1 [31:16] Register */ 118 | CPU_INT16U Spare46; 119 | CPU_INT16U DATA2; /* Mailbox Data Word 2 [47:32] Register */ 120 | CPU_INT16U Spare47; 121 | CPU_INT16U DATA3; /* Mailbox Data Word 3 [63:48] Register */ 122 | CPU_INT16U Spare48; 123 | CPU_INT16U LENGTH; /* Mailbox Data Length Code Register */ 124 | CPU_INT16U Spare49; 125 | CPU_INT16U TIMESTAMP; /* Mailbox Time Stamp Value Register */ 126 | CPU_INT16U Spare50; 127 | CPU_INT16U ID0; /* Mailbox Identifier Low Register */ 128 | CPU_INT16U Spare51; 129 | CPU_INT16U ID1; /* Mailbox Identifier High Register */ 130 | CPU_INT16U Spare52; 131 | } CAN_MB; 132 | 133 | 134 | /* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ 135 | 136 | 137 | typedef volatile struct { 138 | CPU_INT16U MC1; /* Mailbox config reg 1 */ 139 | CPU_INT16U Spare0; 140 | CPU_INT16U MD1; /* Mailbox direction reg 1 */ 141 | CPU_INT16U Spare1; 142 | CPU_INT16U TRS1; /* Transmit Request Set reg 1 */ 143 | CPU_INT16U Spare2; 144 | CPU_INT16U TRR1; /* Transmit Request Reset reg 1 */ 145 | CPU_INT16U Spare3; 146 | CPU_INT16U TA1; /* Transmit Acknowledge reg 1 */ 147 | CPU_INT16U Spare4; 148 | CPU_INT16U AA1; /* Transmit Abort Acknowledge reg 1 */ 149 | CPU_INT16U Spare5; 150 | CPU_INT16U RMP1; /* Receive Message Pending reg 1 */ 151 | CPU_INT16U Spare6; 152 | CPU_INT16U RML1; /* Receive Message Lost reg 1 */ 153 | CPU_INT16U Spare7; 154 | CPU_INT16U MBTIF1; /* Mailbox Transmit Interrupt Flag reg 1 */ 155 | CPU_INT16U Spare8; 156 | CPU_INT16U MBRIF1; /* Mailbox Receive Interrupt Flag reg 1 */ 157 | CPU_INT16U Spare9; 158 | CPU_INT16U MBIM1; /* Mailbox Interrupt Mask reg 1 */ 159 | CPU_INT16U Spare10; 160 | CPU_INT16U RFH1; /* Remote Frame Handling reg 1 */ 161 | CPU_INT16U Spare11; 162 | CPU_INT16U OPSS1; /* Overwrite Protection Single Shot Xmit reg 1 */ 163 | CPU_INT16U Spare12; 164 | 165 | CPU_INT32U Rsvd0[3]; 166 | 167 | CPU_INT16U MC2; /* Mailbox config reg 2 */ 168 | CPU_INT16U Spare13; 169 | CPU_INT16U MD2; /* Mailbox direction reg 2 */ 170 | CPU_INT16U Spare14; 171 | CPU_INT16U TRS2; /* Transmit Request Set rg 2 */ 172 | CPU_INT16U Spare15; 173 | CPU_INT16U TRR2; /* Transmit Request Reset reg 2 */ 174 | CPU_INT16U Spare16; 175 | CPU_INT16U TA2; /* Transmit Acknowledge reg 2 */ 176 | CPU_INT16U Spare17; 177 | CPU_INT16U AA2; /* Transmit Abort Acknowledge reg 2 */ 178 | CPU_INT16U Spare18; 179 | CPU_INT16U RMP2; /* Receive Message Pending reg 2 */ 180 | CPU_INT16U Spare19; 181 | CPU_INT16U RML2; /* Receive Message Lost reg 2 */ 182 | CPU_INT16U Spare20; 183 | CPU_INT16U MBTIF2; /* Mailbox Transmit Interrupt Flag reg 2 */ 184 | CPU_INT16U Spare21; 185 | CPU_INT16U MBRIF2; /* Mailbox Receive Interrupt Flag reg 2 */ 186 | CPU_INT16U Spare22; 187 | CPU_INT16U MBIM2; /* Mailbox Interrupt Mask reg 2 */ 188 | CPU_INT16U Spare23; 189 | CPU_INT16U RFH2; /* Remote Frame Handling reg 2 */ 190 | CPU_INT16U Spare24; 191 | CPU_INT16U OPSS2; /* Overwrite Protection Single Shot Xmit reg 2 */ 192 | CPU_INT16U Spare25; 193 | 194 | CPU_INT32U Rsvd1[3]; 195 | 196 | CPU_INT16U CLOCK; /* Bit Timing Configuration register 0 0xFFC02A80*/ 197 | CPU_INT16U Spare26; 198 | CPU_INT16U TIMING; /* Bit Timing Configuration register 1 */ 199 | CPU_INT16U Spare27; 200 | CPU_INT16U DEBUG; /* Debug Register */ 201 | CPU_INT16U Spare28; 202 | CPU_INT16U STATUS; /* Global Status Register */ 203 | CPU_INT16U Spare29; 204 | CPU_INT16U CEC; /* Error Counter Register */ 205 | CPU_INT16U Spare30; 206 | CPU_INT16U GIS; /* Global Interrupt Status Register */ 207 | CPU_INT16U Spare31; 208 | CPU_INT16U GIM; /* Global Interrupt Mask Register */ 209 | CPU_INT16U Spare32; 210 | CPU_INT16U GIF; /* Global Interrupt Flag Register */ 211 | CPU_INT16U Spare33; 212 | CPU_INT16U CONTROL; /* Master Control Register */ 213 | CPU_INT16U Spare34; 214 | CPU_INT16U INTR; /* Interrupt Pending Register 0xFFC02AA4 */ 215 | CPU_INT16U Spare35; 216 | CPU_INT16U Rsvd2; 217 | CPU_INT16U Spare36; 218 | CPU_INT16U MBTD; /* Mailbox Temporary Disable Feature 0xFFC02AAC */ 219 | CPU_INT16U Spare37; 220 | CPU_INT16U EWR; /* Programmable Warning Level */ 221 | CPU_INT16U Spare38; 222 | CPU_INT16U ESR; /* Error Status Register */ 223 | CPU_INT16U Spare39; 224 | 225 | CPU_INT32U Rsvd3[4]; 226 | 227 | CPU_INT16U UCCNT; /* Universal Counter 0xFFC02AC4 */ 228 | CPU_INT16U Spare40; 229 | CPU_INT16U UCRC; /* Universal Counter Reload/Capture Register */ 230 | CPU_INT16U Spare41; 231 | CPU_INT16U UCCNF; /* Universal Counter Configuration Register 0xFFC02ACC */ 232 | CPU_INT16U Spare42; 233 | 234 | CPU_INT32U Rsvd4[11]; 235 | 236 | CAN_MB_ACC MB_ACC[32]; /* Mailbox Acceptance Masks 0-31 0xFFC02B00--0xFFC02BFC */ 237 | 238 | CAN_MB MB[32]; /* Mailbox register 0-31 0xFFC02C00--0xFFC02FFC */ 239 | 240 | }CAN_ADSPBF537; 241 | 242 | 243 | 244 | 245 | /* 246 | **************************************************************************************************** 247 | * FUNCTION PROTOTYPES 248 | **************************************************************************************************** 249 | */ 250 | 251 | /* 252 | **************************************************************************************************** 253 | * ERROR SECTION 254 | **************************************************************************************************** 255 | */ 256 | 257 | 258 | #endif /* #ifndef _DRV_CAN_REG_H_ */ 259 | 260 | 261 | 262 | 263 | -------------------------------------------------------------------------------- /Drivers/LM3S9B96/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_CAN_REG_H_ 27 | #define _DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | #include "cpu.h" 35 | 36 | /* 37 | **************************************************************************************************** 38 | * DEFINES 39 | **************************************************************************************************** 40 | */ 41 | /* CAN base address */ 42 | #define LM3S9B96_CAN0_BASE_ADDR (volatile CPU_INT32U *) 0x40040000 43 | #define LM3S9B96_CAN1_BASE_ADDR (volatile CPU_INT32U *) 0x40041000 44 | 45 | /* registers used for CAN initialisation */ 46 | 47 | /* Clock Settings */ 48 | #define RCGC0_REG *(volatile CPU_INT32U *) 0x400FE100 /* Run Mode Clock Gating Control Register 0 */ 49 | 50 | #define RCGC0_CAN0_BIT 0x01000000 51 | #define RCGC0_CAN1_BIT 0x02000000 52 | 53 | #define RCGC2_REG *(volatile CPU_INT32U *) 0x400FE108 /* Run Mode Clock Gating Control Register 2 */ 54 | 55 | #define RCGC0_GPIOA_BIT 0x00000001 56 | #define RCGC0_GPIOB_BIT 0x00000002 57 | #define RCGC0_GPIOC_BIT 0x00000004 58 | #define RCGC0_GPIOD_BIT 0x00000008 59 | #define RCGC0_GPIOE_BIT 0x00000010 60 | #define RCGC0_GPIOF_BIT 0x00000020 61 | #define RCGC0_GPIOG_BIT 0x00000040 62 | #define RCGC0_GPIOH_BIT 0x00000080 63 | #define RCGC0_GPIOJ_BIT 0x00000100 64 | 65 | 66 | /* Pin Settings */ 67 | #define GPIO_PORTA_REG 0x40004000 68 | #define GPIO_PORTB_REG 0x40005000 69 | #define GPIO_PORTD_REG 0x40007000 70 | #define GPIO_PORTF_REG 0x40025000 71 | #define GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate function select */ 72 | #define GPIO_PCTL_OFFSET 0x52C /* GPIO Port Control */ 73 | #define GPIO_DIR_OFFSET 0x400 /* GPIO Dir Control */ 74 | 75 | #define PIN_PA4 0x5 /* Bit field encoding for GPIOPCTL PMCx */ 76 | #define PIN_PA5 0x5 77 | #define PIN_PA6 0x6 78 | #define PIN_PA7 0x6 79 | #define PIN_PB4 0x5 80 | #define PIN_PB5 0x5 81 | #define PIN_PD0 0x2 82 | #define PIN_PD1 0x2 83 | #define PIN_PF0 0x1 84 | #define PIN_PF1 0x1 85 | 86 | #define PIN_PA4_PA5 1 87 | #define PIN_PA6_PA7 2 88 | #define PIN_PB4_PB5 3 89 | #define PIN_PD0_PD1 4 90 | #define PIN_PF0_PF1 5 91 | 92 | 93 | /* Interrupt Settings */ 94 | #define VIC0_INTER_REG *(volatile CPU_INT32U *) 0xFFFFF010 95 | #define VIC0_VAR_REG *(volatile CPU_INT32U *) 0xFFFFF030 96 | #define VIC0_VA0R_ADDR (volatile CPU_INT32U *) 0xFFFFF100 97 | #define VIC0_VC0R_ADDR (volatile CPU_INT32U *) 0xFFFFF200 98 | 99 | 100 | /*------------------------------------------------------------------------------------------------*/ 101 | /*! 102 | * \brief BIT DEFINITIONS 103 | * \ingroup LM3S9B96_CAN 104 | * 105 | * This member holds a bit defintions for various registers of LM3S9B96 106 | */ 107 | /*------------------------------------------------------------------------------------------------*/ 108 | 109 | /* Control register*/ 110 | #define CAN_CR_TEST 0x0080 111 | #define CAN_CR_CCE 0x0040 112 | #define CAN_CR_DAR 0x0020 113 | #define CAN_CR_EIE 0x0008 114 | #define CAN_CR_SIE 0x0004 115 | #define CAN_CR_IE 0x0002 116 | #define CAN_CR_INIT 0x0001 117 | 118 | /* Status register */ 119 | #define CAN_SR_BOFF 0x0080 120 | #define CAN_SR_EWARN 0x0040 121 | #define CAN_SR_EPASS 0x0020 122 | #define CAN_SR_RXOK 0x0010 123 | #define CAN_SR_TXOK 0x0008 124 | #define CAN_SR_LEC 0x0007 125 | 126 | /* Test register*/ 127 | #define CAN_TESTR_RX 0x0080 128 | #define CAN_TESTR_TX1 0x0040 129 | #define CAN_TESTR_TX0 0x0020 130 | #define CAN_TESTR_LBACK 0x0010 131 | #define CAN_TESTR_SILENT 0x0008 132 | #define CAN_TESTR_BASIC 0x0004 133 | 134 | /* IFn / Command Request register*/ 135 | #define CAN_CRR_BUSY 0x8000 136 | 137 | /* IFn / Command Mask register*/ 138 | #define CAN_CMR_WRRD 0x0080 139 | #define CAN_CMR_MASK 0x0040 140 | #define CAN_CMR_ARB 0x0020 141 | #define CAN_CMR_CONTROL 0x0010 142 | #define CAN_CMR_CLRINTPND 0x0008 143 | #define CAN_CMR_TXRQSTNEWDAT 0x0004 144 | #define CAN_CMR_DATAA 0x0002 145 | #define CAN_CMR_DATAB 0x0001 146 | 147 | /* IFn / Mask 2 register*/ 148 | #define CAN_M2R_MXTD 0x8000 149 | #define CAN_M2R_MDIR 0x4000 150 | 151 | /* IFn / Arbitration 2 register*/ 152 | #define CAN_A2R_MSGVAL 0x8000 153 | #define CAN_A2R_XTD 0x4000 154 | #define CAN_A2R_DIR 0x2000 155 | 156 | /* IFn / Message Control register*/ 157 | #define CAN_MCR_NEWDAT 0x8000 158 | #define CAN_MCR_MSGLST 0x4000 159 | #define CAN_MCR_INTPND 0x2000 160 | #define CAN_MCR_UMASK 0x1000 161 | #define CAN_MCR_TXIE 0x0800 162 | #define CAN_MCR_RXIE 0x0400 163 | #define CAN_MCR_RMTEN 0x0200 164 | #define CAN_MCR_TXRQST 0x0100 165 | #define CAN_MCR_EOB 0x0080 166 | 167 | /* 168 | **************************************************************************************************** 169 | * DATA TYPES 170 | **************************************************************************************************** 171 | */ 172 | 173 | /*------------------------------------------------------------------------------------------------*/ 174 | /*! 175 | * \brief REGISTER LAYOUT CAN MODULE OF LM3S9B96 176 | * \ingroup LM3S9B96_CAN 177 | * 178 | * This definition holds the register layout of the CAN module of LM3S9B96. For detailed 179 | * register descriptions please refer to STR91F reference manual. 180 | */ 181 | /*------------------------------------------------------------------------------------------------*/ 182 | 183 | typedef struct { 184 | CPU_INT16U CRR; /* IFn Command request Register */ 185 | CPU_INT16U EMPTY1; 186 | CPU_INT16U CMR; /* IFn Command Mask Register */ 187 | CPU_INT16U EMPTY2; 188 | CPU_INT16U M1R; /* IFn Message Mask 1 Register */ 189 | CPU_INT16U EMPTY3; 190 | CPU_INT16U M2R; /* IFn Message Mask 2 Register */ 191 | CPU_INT16U EMPTY4; 192 | CPU_INT16U A1R; /* IFn Message Arbitration 1 Register */ 193 | CPU_INT16U EMPTY5; 194 | CPU_INT16U A2R; /* IFn Message Arbitration 2 Register */ 195 | CPU_INT16U EMPTY6; 196 | CPU_INT16U MCR; /* IFn Message Control Register */ 197 | CPU_INT16U EMPTY7; 198 | CPU_INT16U DA1R; /* IFn DATA A 1 Register */ 199 | CPU_INT16U EMPTY8; 200 | CPU_INT16U DA2R; /* IFn DATA A 2 Register */ 201 | CPU_INT16U EMPTY9; 202 | CPU_INT16U DB1R; /* IFn DATA B 1 Register */ 203 | CPU_INT16U EMPTY10; 204 | CPU_INT16U DB2R; /* IFn DATA B 2 Register */ 205 | CPU_INT16U EMPTY11[27]; 206 | } CAN_MSG_OBJS; 207 | 208 | 209 | typedef struct { 210 | CPU_INT16U CR; /* Control Register */ 211 | CPU_INT16U EMPTY1; 212 | CPU_INT16U SR; /* Status Register */ 213 | CPU_INT16U EMPTY2; 214 | CPU_INT16U ERR; /* Error counter Register */ 215 | CPU_INT16U EMPTY3; 216 | CPU_INT16U BTR; /* Bit Timing Register */ 217 | CPU_INT16U EMPTY4; 218 | CPU_INT16U IDR; /* Interrupt Identifier Register */ 219 | CPU_INT16U EMPTY5; 220 | CPU_INT16U TESTR; /* Test Register */ 221 | CPU_INT16U EMPTY6; 222 | CPU_INT16U BRPR; /* BRP Extension Register */ 223 | CPU_INT16U EMPTY7[3]; 224 | CAN_MSG_OBJS MsgObj[2]; 225 | CPU_INT16U EMPTY8[16]; 226 | CPU_INT16U TXR1R; /* Transmission request 1 Register */ 227 | CPU_INT16U EMPTY9; 228 | CPU_INT16U TXR2R; /* Transmission Request 2 Register */ 229 | CPU_INT16U EMPTY10[13]; 230 | CPU_INT16U ND1R; /* New Data 1 Register */ 231 | CPU_INT16U EMPTY11; 232 | CPU_INT16U ND2R; /* New Data 2 Register */ 233 | CPU_INT16U EMPTY12[13]; 234 | CPU_INT16U IP1R; /* Interrupt Pending 1 Register */ 235 | CPU_INT16U EMPTY13; 236 | CPU_INT16U IP2R; /* Interrupt Pending 2 Register */ 237 | CPU_INT16U EMPTY14[13]; 238 | CPU_INT16U MV1R; /* Message Valid 1 Register */ 239 | CPU_INT16U EMPTY15; 240 | CPU_INT16U MV2R; /* Message VAlid 2 Register */ 241 | CPU_INT16U EMPTY16; 242 | } CAN_LM3S9B96; 243 | 244 | /* 245 | **************************************************************************************************** 246 | * FUNCTION PROTOTYPES 247 | **************************************************************************************************** 248 | */ 249 | 250 | /* 251 | **************************************************************************************************** 252 | * ERROR SECTION 253 | **************************************************************************************************** 254 | */ 255 | 256 | 257 | #endif /* #ifndef _DRV_CAN_REG_H_ */ 258 | 259 | 260 | 261 | 262 | -------------------------------------------------------------------------------- /Drivers/LPC21XX/drv_can.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRVCAN_H 27 | #define _DRVCAN_H 28 | 29 | #include "cpu.h" /* basic type definitions */ 30 | #include "can_bsp.h" 31 | 32 | /* 33 | *************************************************************************************************** 34 | * CONSTANTS 35 | *************************************************************************************************** 36 | */ 37 | 38 | /*! \brief The unique driver name for installation and searching */ 39 | #define LPC21XX_CAN_NAME "LPC21XX:CAN Module" 40 | 41 | /*! \brief following bit definitions as defined in can_frame.h */ 42 | /*! - bit30: marks a remote transmission request (1=rtr, 0=data frame) */ 43 | /*! - bit29: marks an extended identifier (1=extended, 0=standard) */ 44 | #define LPC21XX_CAN_RTR_FRAME_BIT 0x40000000 45 | #define LPC21XX_CAN_FF_FRAME_BIT 0x20000000 46 | 47 | /* 48 | *************************************************************************************************** 49 | * TYPE DEFINITIONS 50 | *************************************************************************************************** 51 | */ 52 | 53 | enum 54 | { 55 | LPC21XX_CAN_BUS_0, /*!< Internal can controller #0 */ 56 | LPC21XX_CAN_BUS_1, /*!< Internal can controller #1 */ 57 | LPC21XX_CAN_N_DEV /*!< Number of used can controller */ 58 | }; 59 | 60 | 61 | /* 62 | * The global errorcode variable 'DrvError' is supported with the following errorcodes. 63 | */ 64 | enum { 65 | /*! \brief NO ERROR 66 | * 67 | * This code is used, if everything is ok. 68 | */ 69 | LPC21XX_CAN_NO_ERR = 0, 70 | 71 | /*! \brief BUS ERROR 72 | * 73 | * This code indicates, that a wrong bus was chosen.. 74 | */ 75 | LPC21XX_CAN_BUS_ERR, 76 | 77 | /*! \brief BUSY ERROR 78 | * 79 | * This code indicates, that a a msg can not ne send because the bus is busy. 80 | */ 81 | LPC21XX_CAN_BUSY_ERR, 82 | 83 | /*! \brief INIT ERROR 84 | * 85 | * This code indicates, that the devices were not initialised because they are not in reset state. 86 | */ 87 | LPC21XX_CAN_INIT_ERR, 88 | 89 | /*! \brief MODE ERROR 90 | * 91 | * This code indicates, that the device cannot be accessed with the wanted mode. 92 | */ 93 | LPC21XX_CAN_MODE_ERR, 94 | 95 | /*! \brief OPEN ERROR 96 | * 97 | * This code indicates, that a device cannot be used, because it is not opened. 98 | */ 99 | LPC21XX_CAN_OPEN_ERR, 100 | 101 | /*! \brief CLOSE ERROR 102 | * 103 | * This code indicates, that the device cannot be closed. 104 | */ 105 | LPC21XX_CAN_CLOSE_ERR, 106 | 107 | /*! \brief FUNCTION CODE ERROR 108 | * 109 | * This code indicates, that the given function code is not valid. 110 | */ 111 | LPC21XX_CAN_FUNC_ERR, 112 | 113 | /*! \brief ARGUMENT ERROR 114 | * 115 | * This code indicates, that an argument check has failed. 116 | */ 117 | LPC21XX_CAN_ARG_ERR, 118 | 119 | /*! \brief NO DATA ERROR 120 | * 121 | * This code indicates, that no data is available. 122 | */ 123 | LPC21XX_CAN_NO_DATA_ERR 124 | }; 125 | 126 | 127 | /*------------------------------------------------------------------------------------------------*/ 128 | /*! \brief Functioncodes for CANIoCtl() */ 129 | /*------------------------------------------------------------------------------------------------*/ 130 | /*! \brief I/O CONTROL FUNCTIONCODES 131 | * 132 | * This enumeration defines the required functioncode values for the lowlevel 133 | * device driver function IoCtl(). 134 | */ 135 | /*------------------------------------------------------------------------------------------------*/ 136 | enum { 137 | /*! \brief GET DRIVER IDENT CODE 138 | * 139 | * This standard function code gets the driver identification code. 140 | * 141 | * arg = pointer to local ident variable (CPU_INT32U *) 142 | */ 143 | IO_LPC21XX_CAN_GET_IDENT = 0x0, 144 | 145 | /*! \brief GET DRIVER ERRORCODE 146 | * 147 | * This standard function code gets the driver errorcode. 148 | * 149 | * arg = pointer to local errorcode variable (CPU_INT16U *) 150 | */ 151 | IO_LPC21XX_CAN_GET_ERRNO, 152 | 153 | /*! \brief GET DRIVER NAME 154 | * 155 | * This standard function code gets the (human readable) driver name. 156 | * 157 | * arg = pointer to local string variable (char *) 158 | */ 159 | IO_LPC21XX_CAN_GET_DRVNAME, 160 | 161 | /*! \brief SET BUS BAUDRATE 162 | * 163 | * This function code sets the bus baudrate. 164 | * 165 | * arg = pointer to local baudrate variable (CPU_INT32U *) 166 | */ 167 | IO_LPC21XX_CAN_SET_BAUDRATE = 0x10, 168 | /*! \brief Enable Bus 169 | * 170 | * This enum value is the functioncode to start the CAN controller interface. Most common 171 | * is to set the CAN controller in active mode. 172 | * 173 | * The parameter pointer is not used for this function. 174 | */ 175 | IO_LPC21XX_CAN_START, 176 | /*! \brief Disable Bus 177 | * 178 | * This enum value is the functioncode to stop the CAN controller interface. Most common 179 | * is to set the CAN controller in passive mode. 180 | * 181 | * The parameter pointer is not used for this function. 182 | */ 183 | IO_LPC21XX_CAN_STOP, 184 | /*! \brief Set Receiver to Standard Identifier 185 | * 186 | * This enum value is the functioncode to configure the CAN receiver to receive only 187 | * CAN standard identifiers. 188 | * 189 | * The parameter pointer is not used for this function. 190 | */ 191 | IO_LPC21XX_CAN_RX_STANDARD, 192 | /*! \brief Set Receiver to Extended Identifier 193 | * 194 | * This enum value is the functioncode to configure the CAN receiver to receive only 195 | * CAN extended identifiers. 196 | * 197 | * The parameter pointer is not used for this function. 198 | */ 199 | IO_LPC21XX_CAN_RX_EXTENDED, 200 | /*! \brief Get TX Buffer Status 201 | * 202 | * This enum value is the functioncode to get the status of the current transmit 203 | * buffer. 204 | * 205 | * The parameter pointer shall point to a CPU_INT08U variable, where the status 206 | * shall be written to. 207 | */ 208 | IO_LPC21XX_CAN_TX_READY, 209 | /*! \brief Disable RX Interrupts 210 | * 211 | * This enum value is the functioncode to disable the receiption complete interrupt. 212 | * 213 | */ 214 | IO_LPC21XX_CAN_GET_NODE_STATUS, 215 | /*! \brief Set standard filter 216 | * 217 | * This enum value is the functioncode to set standard acceptance filter for the 218 | * CAN controller. 219 | * 220 | * The parameter pointer is not used for this function. 221 | */ 222 | IO_LPC21XX_CAN_SET_STD_FILTER, 223 | /*! \brief Set standard group filter 224 | * 225 | * This enum value is the functioncode to set standard group acceptance filter for the 226 | * CAN controller. 227 | * 228 | * The parameter pointer is not used for this function. 229 | */ 230 | IO_LPC21XX_CAN_SET_STD_GROUP_FILTER, 231 | /*! \brief Set extended filter 232 | * 233 | * This enum value is the functioncode to set extended acceptance filter for the 234 | * CAN controller. 235 | * 236 | * The parameter pointer is not used for this function. 237 | */ 238 | IO_LPC21XX_CAN_SET_EXT_FILTER, 239 | /*! \brief Set extended group filter 240 | * 241 | * This enum value is the functioncode to set extended group acceptance filter for the 242 | * CAN controller. 243 | * 244 | * The parameter pointer is not used for this function. 245 | */ 246 | IO_LPC21XX_CAN_SET_EXT_GROUP_FILTER, 247 | /*! \brief Number of Needed IO Function Codes 248 | * 249 | * This enum value holds the number of function codes, which are used within the 250 | * can bus layer. 251 | */ 252 | IO_LPC21XX_CAN_IO_FUNC_N 253 | }; 254 | 255 | /*------------------------------------------------------------------------------------------------*/ 256 | /*! \brief Dynamic CAN driver data */ 257 | typedef struct 258 | { 259 | /*! \brief Use Marker 260 | * 261 | * This member holds a marker which indicates, that this device is in use: 262 | * 0 = Device idle, 263 | * 1 = Device in use 264 | */ 265 | CPU_INT08U Use; 266 | 267 | } LPC21XX_CAN_DATA; 268 | 269 | 270 | /*------------------------------------------------------------------------------------------------*/ 271 | /*! 272 | * \brief CAN FRAME 273 | * 274 | * This structure contains all needed data to handle a single CAN frame 275 | */ 276 | /*------------------------------------------------------------------------------------------------*/ 277 | typedef struct { 278 | /*--------------------------------------------------------------------------------------------*/ 279 | /*! 280 | * \brief CAN IDENTIFIER 281 | * 282 | * This member holds the CAN identifier. 283 | * 284 | */ 285 | /*--------------------------------------------------------------------------------------------*/ 286 | CPU_INT32U Identifier; 287 | /*--------------------------------------------------------------------------------------------*/ 288 | /*! 289 | * \brief CAN PAYLOAD 290 | * 291 | * This member holds up to 8 bytes, which can be handled with a single CAN message. 292 | */ 293 | /*--------------------------------------------------------------------------------------------*/ 294 | CPU_INT08U Data[8]; 295 | /*--------------------------------------------------------------------------------------------*/ 296 | /*! 297 | * \brief CAN DLC 298 | * 299 | * This member holds the number of valid datas in the payload. 300 | */ 301 | /*--------------------------------------------------------------------------------------------*/ 302 | CPU_INT08U DLC; 303 | /*--------------------------------------------------------------------------------------------*/ 304 | /*! 305 | * \brief SPARE 306 | * 307 | * These bytes are added to get a frame size of an integral number of pointers. 308 | */ 309 | /*--------------------------------------------------------------------------------------------*/ 310 | CPU_INT08U Spare[3]; 311 | 312 | } LPC21XX_CANFRM; 313 | 314 | /* 315 | *************************************************************************************************** 316 | * FUNCTION PROTOTYPES 317 | *************************************************************************************************** 318 | */ 319 | 320 | CPU_INT16S LPC21XXCANInit(CPU_INT32U arg); 321 | CPU_INT16S LPC21XXCANOpen(CPU_INT16S drvId, CPU_INT32U devName, CPU_INT16U mode); 322 | CPU_INT16S LPC21XXCANClose(CPU_INT16S paraId); 323 | CPU_INT16S LPC21XXCANIoCtl(CPU_INT16S paraId, CPU_INT16U func, void *argp); 324 | CPU_INT16S LPC21XXCANRead(CPU_INT16S paraId, CPU_INT08U *buffer, CPU_INT16U size); 325 | CPU_INT16S LPC21XXCANWrite(CPU_INT16S paraId, CPU_INT08U *buffer, CPU_INT16U size); 326 | 327 | 328 | /* 329 | *************************************************************************************************** 330 | * ERROR SECTION 331 | *************************************************************************************************** 332 | */ 333 | 334 | 335 | #endif 336 | 337 | /*! } */ 338 | -------------------------------------------------------------------------------- /Drivers/LPC21XX/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRVCANREG_H 27 | #define _DRVCANREG_H 28 | 29 | #include "cpu.h" 30 | 31 | /* Vectored Interrupt Controller (VIC) */ 32 | #define LPC21XX_CAN_VICINTENABLE (*((volatile CPU_INT32U *) 0xFFFFF010)) 33 | #define LPC21XX_CAN_VICINTENCLR (*((volatile CPU_INT32U *) 0xFFFFF014)) 34 | #define LPC21XX_CAN_VICVECTADDR (*((volatile CPU_INT32U *) 0xFFFFF030)) 35 | #define LPC21XX_CAN_VICINTSELECT (*((volatile CPU_INT32U *) 0xFFFFF00C)) 36 | 37 | #define LPC21XX_CAN_VICVECTADDR4 (*((volatile CPU_INT32U *) 0xFFFFF110)) 38 | #define LPC21XX_CAN_VICVECTADDR5 (*((volatile CPU_INT32U *) 0xFFFFF114)) 39 | #define LPC21XX_CAN_VICVECTADDR6 (*((volatile CPU_INT32U *) 0xFFFFF118)) 40 | #define LPC21XX_CAN_VICVECTADDR7 (*((volatile CPU_INT32U *) 0xFFFFF11C)) 41 | #define LPC21XX_CAN_VICVECTADDR8 (*((volatile CPU_INT32U *) 0xFFFFF120)) 42 | #define LPC21XX_CAN_VICVECTADDR9 (*((volatile CPU_INT32U *) 0xFFFFF124)) 43 | 44 | #define LPC21XX_CAN_VICVECTCTRL4 (*((volatile CPU_INT32U *) 0xFFFFF210)) 45 | #define LPC21XX_CAN_VICVECTCTRL5 (*((volatile CPU_INT32U *) 0xFFFFF214)) 46 | #define LPC21XX_CAN_VICVECTCTRL6 (*((volatile CPU_INT32U *) 0xFFFFF218)) 47 | #define LPC21XX_CAN_VICVECTCTRL7 (*((volatile CPU_INT32U *) 0xFFFFF21C)) 48 | #define LPC21XX_CAN_VICVECTCTRL8 (*((volatile CPU_INT32U *) 0xFFFFF220)) 49 | #define LPC21XX_CAN_VICVECTCTRL9 (*((volatile CPU_INT32U *) 0xFFFFF224)) 50 | 51 | /* Pin Connect Block */ 52 | #define LPC21XX_CAN_PINSEL1 (*((volatile CPU_INT32U *) 0xE002C004)) 53 | 54 | /* CAN Acceptance Filter */ 55 | #define LPC21XX_CAN_AFMR (*((volatile CPU_INT32U *) 0xE003C000)) 56 | #define LPC21XX_CAN_SFF_SA (*((volatile CPU_INT32U *) 0xE003C004)) 57 | #define LPC21XX_CAN_SFF_GRP_SA (*((volatile CPU_INT32U *) 0xE003C008)) 58 | #define LPC21XX_CAN_EFF_SA (*((volatile CPU_INT32U *) 0xE003C00C)) 59 | #define LPC21XX_CAN_EFF_GRP_SA (*((volatile CPU_INT32U *) 0xE003C010)) 60 | #define LPC21XX_CAN_END_OF_TABLE (*((volatile CPU_INT32U *) 0xE003C014)) 61 | 62 | /* CAN Central Registers */ 63 | #define LPC21XX_CAN_CANTXSR (*((volatile CPU_INT32U *) 0xE0040000)) 64 | #define LPC21XX_CAN_CANRXSR (*((volatile CPU_INT32U *) 0xE0040004)) 65 | #define LPC21XX_CAN_CANMSR (*((volatile CPU_INT32U *) 0xE0040008)) 66 | 67 | /* CAN Controller 1 (CAN1) */ 68 | #define LPC21XX_CAN_C1MOD (*((volatile CPU_INT32U *) 0xE0044000)) 69 | #define LPC21XX_CAN_C1CMR (*((volatile CPU_INT32U *) 0xE0044004)) 70 | #define LPC21XX_CAN_C1GSR (*((volatile CPU_INT32U *) 0xE0044008)) 71 | #define LPC21XX_CAN_C1ICR (*((volatile CPU_INT32U *) 0xE004400C)) 72 | #define LPC21XX_CAN_C1IER (*((volatile CPU_INT32U *) 0xE0044010)) 73 | #define LPC21XX_CAN_C1BTR (*((volatile CPU_INT32U *) 0xE0044014)) 74 | #define LPC21XX_CAN_C1EWL (*((volatile CPU_INT32U *) 0xE0044018)) 75 | #define LPC21XX_CAN_C1SR (*((volatile CPU_INT32U *) 0xE004401C)) 76 | #define LPC21XX_CAN_C1RFS (*((volatile CPU_INT32U *) 0xE0044020)) 77 | #define LPC21XX_CAN_C1RID (*((volatile CPU_INT32U *) 0xE0044024)) 78 | #define LPC21XX_CAN_C1RDA (*((volatile CPU_INT32U *) 0xE0044028)) 79 | #define LPC21XX_CAN_C1RDB (*((volatile CPU_INT32U *) 0xE004402C)) 80 | #define LPC21XX_CAN_C1TFI1 (*((volatile CPU_INT32U *) 0xE0044030)) 81 | #define LPC21XX_CAN_C1TID1 (*((volatile CPU_INT32U *) 0xE0044034)) 82 | #define LPC21XX_CAN_C1TDA1 (*((volatile CPU_INT32U *) 0xE0044038)) 83 | #define LPC21XX_CAN_C1TDB1 (*((volatile CPU_INT32U *) 0xE004403C)) 84 | #define LPC21XX_CAN_C1TFI2 (*((volatile CPU_INT32U *) 0xE0044040)) 85 | #define LPC21XX_CAN_C1TID2 (*((volatile CPU_INT32U *) 0xE0044044)) 86 | #define LPC21XX_CAN_C1TDA2 (*((volatile CPU_INT32U *) 0xE0044048)) 87 | #define LPC21XX_CAN_C1TDB2 (*((volatile CPU_INT32U *) 0xE004404C)) 88 | #define LPC21XX_CAN_C1TFI3 (*((volatile CPU_INT32U *) 0xE0044050)) 89 | #define LPC21XX_CAN_C1TID3 (*((volatile CPU_INT32U *) 0xE0044054)) 90 | #define LPC21XX_CAN_C1TDA3 (*((volatile CPU_INT32U *) 0xE0044058)) 91 | #define LPC21XX_CAN_C1TDB3 (*((volatile CPU_INT32U *) 0xE004405C)) 92 | 93 | /* CAN Controller 2 (CAN2) */ 94 | #define LPC21XX_CAN_C2MOD (*((volatile CPU_INT32U *) 0xE0048000)) 95 | #define LPC21XX_CAN_C2CMR (*((volatile CPU_INT32U *) 0xE0048004)) 96 | #define LPC21XX_CAN_C2GSR (*((volatile CPU_INT32U *) 0xE0048008)) 97 | #define LPC21XX_CAN_C2ICR (*((volatile CPU_INT32U *) 0xE004800C)) 98 | #define LPC21XX_CAN_C2IER (*((volatile CPU_INT32U *) 0xE0048010)) 99 | #define LPC21XX_CAN_C2BTR (*((volatile CPU_INT32U *) 0xE0048014)) 100 | #define LPC21XX_CAN_C2EWL (*((volatile CPU_INT32U *) 0xE0048018)) 101 | #define LPC21XX_CAN_C2SR (*((volatile CPU_INT32U *) 0xE004801C)) 102 | #define LPC21XX_CAN_C2RFS (*((volatile CPU_INT32U *) 0xE0048020)) 103 | #define LPC21XX_CAN_C2RID (*((volatile CPU_INT32U *) 0xE0048024)) 104 | #define LPC21XX_CAN_C2RDA (*((volatile CPU_INT32U *) 0xE0048028)) 105 | #define LPC21XX_CAN_C2RDB (*((volatile CPU_INT32U *) 0xE004802C)) 106 | #define LPC21XX_CAN_C2TFI1 (*((volatile CPU_INT32U *) 0xE0048030)) 107 | #define LPC21XX_CAN_C2TID1 (*((volatile CPU_INT32U *) 0xE0048034)) 108 | #define LPC21XX_CAN_C2TDA1 (*((volatile CPU_INT32U *) 0xE0048038)) 109 | #define LPC21XX_CAN_C2TDB1 (*((volatile CPU_INT32U *) 0xE004803C)) 110 | #define LPC21XX_CAN_C2TFI2 (*((volatile CPU_INT32U *) 0xE0048040)) 111 | #define LPC21XX_CAN_C2TID2 (*((volatile CPU_INT32U *) 0xE0048044)) 112 | #define LPC21XX_CAN_C2TDA2 (*((volatile CPU_INT32U *) 0xE0048048)) 113 | #define LPC21XX_CAN_C2TDB2 (*((volatile CPU_INT32U *) 0xE004804C)) 114 | #define LPC21XX_CAN_C2TFI3 (*((volatile CPU_INT32U *) 0xE0048050)) 115 | #define LPC21XX_CAN_C2TID3 (*((volatile CPU_INT32U *) 0xE0048054)) 116 | #define LPC21XX_CAN_C2TDA3 (*((volatile CPU_INT32U *) 0xE0048058)) 117 | #define LPC21XX_CAN_C2TDB3 (*((volatile CPU_INT32U *) 0xE004805C)) 118 | 119 | /* CAN Int Enable Register Bit definitions */ 120 | #define LPC21XX_CAN_IER_RX 0x00000001 /* RIE */ 121 | #define LPC21XX_CAN_IER_TX 0x00000602 /* TIE1-3 */ 122 | #define LPC21XX_CAN_IER_NS 0x000000A4 /* EIE, EPIE, BEIE */ 123 | 124 | /* CAN Interrupt and Capture Register Bit definitions */ 125 | #define LPC21XX_CAN_ICR_RI 0x00000001 126 | #define LPC21XX_CAN_ICR_TI1 0x00000002 127 | #define LPC21XX_CAN_ICR_EI 0x00000004 128 | #define LPC21XX_CAN_ICR_DOI 0x00000008 129 | #define LPC21XX_CAN_ICR_WUI 0x00000010 130 | #define LPC21XX_CAN_ICR_EPI 0x00000020 131 | #define LPC21XX_CAN_ICR_ALI 0x00000040 132 | #define LPC21XX_CAN_ICR_BEI 0x00000080 133 | #define LPC21XX_CAN_ICR_IDI 0x00000100 134 | #define LPC21XX_CAN_ICR_TI2 0x00000200 135 | #define LPC21XX_CAN_ICR_TI3 0x00000400 136 | 137 | /* CAN frame status register Bit definitions */ 138 | #define LPC21XX_CAN_DLC_MASK 0x000F0000L 139 | #define LPC21XX_CAN_RTR_MASK 0x40000000L 140 | #define LPC21XX_CAN_FF_MASK 0x80000000L 141 | 142 | #endif 143 | -------------------------------------------------------------------------------- /Drivers/LPC22XX/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRVCANREG_H 27 | #define _DRVCANREG_H 28 | 29 | #include "cpu.h" 30 | 31 | /* Vectored Interrupt Controller (VIC) */ 32 | #define LPC22XX_CAN_VICINTENABLE (*((volatile CPU_INT32U *) 0xFFFFF010)) 33 | #define LPC22XX_CAN_VICINTENCLR (*((volatile CPU_INT32U *) 0xFFFFF014)) 34 | #define LPC22XX_CAN_VICVECTADDR (*((volatile CPU_INT32U *) 0xFFFFF030)) 35 | #define LPC22XX_CAN_VICINTSELECT (*((volatile CPU_INT32U *) 0xFFFFF00C)) 36 | 37 | #define LPC22XX_CAN_VICVECTADDR4 (*((volatile CPU_INT32U *) 0xFFFFF110)) 38 | #define LPC22XX_CAN_VICVECTADDR5 (*((volatile CPU_INT32U *) 0xFFFFF114)) 39 | #define LPC22XX_CAN_VICVECTADDR6 (*((volatile CPU_INT32U *) 0xFFFFF118)) 40 | #define LPC22XX_CAN_VICVECTADDR7 (*((volatile CPU_INT32U *) 0xFFFFF11C)) 41 | #define LPC22XX_CAN_VICVECTADDR8 (*((volatile CPU_INT32U *) 0xFFFFF120)) 42 | #define LPC22XX_CAN_VICVECTADDR9 (*((volatile CPU_INT32U *) 0xFFFFF124)) 43 | 44 | #define LPC22XX_CAN_VICVECTCTRL4 (*((volatile CPU_INT32U *) 0xFFFFF210)) 45 | #define LPC22XX_CAN_VICVECTCTRL5 (*((volatile CPU_INT32U *) 0xFFFFF214)) 46 | #define LPC22XX_CAN_VICVECTCTRL6 (*((volatile CPU_INT32U *) 0xFFFFF218)) 47 | #define LPC22XX_CAN_VICVECTCTRL7 (*((volatile CPU_INT32U *) 0xFFFFF21C)) 48 | #define LPC22XX_CAN_VICVECTCTRL8 (*((volatile CPU_INT32U *) 0xFFFFF220)) 49 | #define LPC22XX_CAN_VICVECTCTRL9 (*((volatile CPU_INT32U *) 0xFFFFF224)) 50 | 51 | /* Pin Connect Block */ 52 | #define LPC22XX_CAN_PINSEL1 (*((volatile CPU_INT32U *) 0xE002C004)) 53 | 54 | /* CAN Acceptance Filter */ 55 | #define LPC22XX_CAN_AFMR (*((volatile CPU_INT32U *) 0xE003C000)) 56 | #define LPC22XX_CAN_SFF_SA (*((volatile CPU_INT32U *) 0xE003C004)) 57 | #define LPC22XX_CAN_SFF_GRP_SA (*((volatile CPU_INT32U *) 0xE003C008)) 58 | #define LPC22XX_CAN_EFF_SA (*((volatile CPU_INT32U *) 0xE003C00C)) 59 | #define LPC22XX_CAN_EFF_GRP_SA (*((volatile CPU_INT32U *) 0xE003C010)) 60 | #define LPC22XX_CAN_END_OF_TABLE (*((volatile CPU_INT32U *) 0xE003C014)) 61 | 62 | /* CAN Central Registers */ 63 | #define LPC22XX_CAN_CANTXSR (*((volatile CPU_INT32U *) 0xE0040000)) 64 | #define LPC22XX_CAN_CANRXSR (*((volatile CPU_INT32U *) 0xE0040004)) 65 | #define LPC22XX_CAN_CANMSR (*((volatile CPU_INT32U *) 0xE0040008)) 66 | 67 | /* CAN Controller 1 (CAN1) */ 68 | #define LPC22XX_CAN_C1MOD (*((volatile CPU_INT32U *) 0xE0044000)) 69 | #define LPC22XX_CAN_C1CMR (*((volatile CPU_INT32U *) 0xE0044004)) 70 | #define LPC22XX_CAN_C1GSR (*((volatile CPU_INT32U *) 0xE0044008)) 71 | #define LPC22XX_CAN_C1ICR (*((volatile CPU_INT32U *) 0xE004400C)) 72 | #define LPC22XX_CAN_C1IER (*((volatile CPU_INT32U *) 0xE0044010)) 73 | #define LPC22XX_CAN_C1BTR (*((volatile CPU_INT32U *) 0xE0044014)) 74 | #define LPC22XX_CAN_C1EWL (*((volatile CPU_INT32U *) 0xE0044018)) 75 | #define LPC22XX_CAN_C1SR (*((volatile CPU_INT32U *) 0xE004401C)) 76 | #define LPC22XX_CAN_C1RFS (*((volatile CPU_INT32U *) 0xE0044020)) 77 | #define LPC22XX_CAN_C1RID (*((volatile CPU_INT32U *) 0xE0044024)) 78 | #define LPC22XX_CAN_C1RDA (*((volatile CPU_INT32U *) 0xE0044028)) 79 | #define LPC22XX_CAN_C1RDB (*((volatile CPU_INT32U *) 0xE004402C)) 80 | #define LPC22XX_CAN_C1TFI1 (*((volatile CPU_INT32U *) 0xE0044030)) 81 | #define LPC22XX_CAN_C1TID1 (*((volatile CPU_INT32U *) 0xE0044034)) 82 | #define LPC22XX_CAN_C1TDA1 (*((volatile CPU_INT32U *) 0xE0044038)) 83 | #define LPC22XX_CAN_C1TDB1 (*((volatile CPU_INT32U *) 0xE004403C)) 84 | #define LPC22XX_CAN_C1TFI2 (*((volatile CPU_INT32U *) 0xE0044040)) 85 | #define LPC22XX_CAN_C1TID2 (*((volatile CPU_INT32U *) 0xE0044044)) 86 | #define LPC22XX_CAN_C1TDA2 (*((volatile CPU_INT32U *) 0xE0044048)) 87 | #define LPC22XX_CAN_C1TDB2 (*((volatile CPU_INT32U *) 0xE004404C)) 88 | #define LPC22XX_CAN_C1TFI3 (*((volatile CPU_INT32U *) 0xE0044050)) 89 | #define LPC22XX_CAN_C1TID3 (*((volatile CPU_INT32U *) 0xE0044054)) 90 | #define LPC22XX_CAN_C1TDA3 (*((volatile CPU_INT32U *) 0xE0044058)) 91 | #define LPC22XX_CAN_C1TDB3 (*((volatile CPU_INT32U *) 0xE004405C)) 92 | 93 | /* CAN Controller 2 (CAN2) */ 94 | #define LPC22XX_CAN_C2MOD (*((volatile CPU_INT32U *) 0xE0048000)) 95 | #define LPC22XX_CAN_C2CMR (*((volatile CPU_INT32U *) 0xE0048004)) 96 | #define LPC22XX_CAN_C2GSR (*((volatile CPU_INT32U *) 0xE0048008)) 97 | #define LPC22XX_CAN_C2ICR (*((volatile CPU_INT32U *) 0xE004800C)) 98 | #define LPC22XX_CAN_C2IER (*((volatile CPU_INT32U *) 0xE0048010)) 99 | #define LPC22XX_CAN_C2BTR (*((volatile CPU_INT32U *) 0xE0048014)) 100 | #define LPC22XX_CAN_C2EWL (*((volatile CPU_INT32U *) 0xE0048018)) 101 | #define LPC22XX_CAN_C2SR (*((volatile CPU_INT32U *) 0xE004801C)) 102 | #define LPC22XX_CAN_C2RFS (*((volatile CPU_INT32U *) 0xE0048020)) 103 | #define LPC22XX_CAN_C2RID (*((volatile CPU_INT32U *) 0xE0048024)) 104 | #define LPC22XX_CAN_C2RDA (*((volatile CPU_INT32U *) 0xE0048028)) 105 | #define LPC22XX_CAN_C2RDB (*((volatile CPU_INT32U *) 0xE004802C)) 106 | #define LPC22XX_CAN_C2TFI1 (*((volatile CPU_INT32U *) 0xE0048030)) 107 | #define LPC22XX_CAN_C2TID1 (*((volatile CPU_INT32U *) 0xE0048034)) 108 | #define LPC22XX_CAN_C2TDA1 (*((volatile CPU_INT32U *) 0xE0048038)) 109 | #define LPC22XX_CAN_C2TDB1 (*((volatile CPU_INT32U *) 0xE004803C)) 110 | #define LPC22XX_CAN_C2TFI2 (*((volatile CPU_INT32U *) 0xE0048040)) 111 | #define LPC22XX_CAN_C2TID2 (*((volatile CPU_INT32U *) 0xE0048044)) 112 | #define LPC22XX_CAN_C2TDA2 (*((volatile CPU_INT32U *) 0xE0048048)) 113 | #define LPC22XX_CAN_C2TDB2 (*((volatile CPU_INT32U *) 0xE004804C)) 114 | #define LPC22XX_CAN_C2TFI3 (*((volatile CPU_INT32U *) 0xE0048050)) 115 | #define LPC22XX_CAN_C2TID3 (*((volatile CPU_INT32U *) 0xE0048054)) 116 | #define LPC22XX_CAN_C2TDA3 (*((volatile CPU_INT32U *) 0xE0048058)) 117 | #define LPC22XX_CAN_C2TDB3 (*((volatile CPU_INT32U *) 0xE004805C)) 118 | 119 | /* CAN Int Enable Register Bit definitions */ 120 | #define LPC22XX_CAN_IER_RX 0x00000001 /* RIE */ 121 | #define LPC22XX_CAN_IER_TX 0x00000602 /* TIE1-3 */ 122 | #define LPC22XX_CAN_IER_NS 0x000000A4 /* EIE, EPIE, BEIE */ 123 | 124 | /* CAN Interrupt and Capture Register Bit definitions */ 125 | #define LPC22XX_CAN_ICR_RI 0x00000001 126 | #define LPC22XX_CAN_ICR_TI1 0x00000002 127 | #define LPC22XX_CAN_ICR_EI 0x00000004 128 | #define LPC22XX_CAN_ICR_DOI 0x00000008 129 | #define LPC22XX_CAN_ICR_WUI 0x00000010 130 | #define LPC22XX_CAN_ICR_EPI 0x00000020 131 | #define LPC22XX_CAN_ICR_ALI 0x00000040 132 | #define LPC22XX_CAN_ICR_BEI 0x00000080 133 | #define LPC22XX_CAN_ICR_IDI 0x00000100 134 | #define LPC22XX_CAN_ICR_TI2 0x00000200 135 | #define LPC22XX_CAN_ICR_TI3 0x00000400 136 | 137 | /* CAN frame status register Bit definitions */ 138 | #define LPC22XX_CAN_DLC_MASK 0x000F0000L 139 | #define LPC22XX_CAN_RTR_MASK 0x40000000L 140 | #define LPC22XX_CAN_FF_MASK 0x80000000L 141 | 142 | #endif 143 | -------------------------------------------------------------------------------- /Drivers/LPC24XX/drv_can.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRVCAN_H 27 | #define _DRVCAN_H 28 | 29 | #include "cpu.h" /* basic type definitions */ 30 | #include "can_bsp.h" 31 | 32 | /* 33 | *************************************************************************************************** 34 | * CONSTANTS 35 | *************************************************************************************************** 36 | */ 37 | 38 | /*! \brief The unique driver name for installation and searching */ 39 | #define LPC24XX_CAN_NAME "LPC24XX:CAN Module" 40 | 41 | /*! \brief following bit definitions as defined in can_frame.h */ 42 | /*! - bit30: marks a remote transmission request (1=rtr, 0=data frame) */ 43 | /*! - bit29: marks an extended identifier (1=extended, 0=standard) */ 44 | #define LPC24XX_CAN_RTR_FRAME_BIT 0x40000000 45 | #define LPC24XX_CAN_FF_FRAME_BIT 0x20000000 46 | /* 47 | *************************************************************************************************** 48 | * TYPE DEFINITIONS 49 | *************************************************************************************************** 50 | */ 51 | 52 | enum 53 | { 54 | LPC24XX_CAN_BUS_0, /* Internal can controller #0 */ 55 | LPC24XX_CAN_BUS_1, /* Internal can controller #1 */ 56 | LPC24XX_CAN_N_DEV /* Number of used can controller */ 57 | }; 58 | 59 | 60 | /* 61 | * The global errorcode variable 'DrvError' is supported with the following errorcodes. 62 | */ 63 | enum { 64 | /*! \brief NO ERROR 65 | * 66 | * This code is used, if everything is ok. 67 | */ 68 | LPC24XX_CAN_NO_ERR = 0, 69 | 70 | /*! \brief BUS ERROR 71 | * 72 | * This code indicates, that a wrong bus was chosen.. 73 | */ 74 | LPC24XX_CAN_BUS_ERR, 75 | 76 | /*! \brief BUSY ERROR 77 | * 78 | * This code indicates, that a a msg can not ne send because the bus is busy. 79 | */ 80 | LPC24XX_CAN_BUSY_ERR, 81 | 82 | /*! \brief INIT ERROR 83 | * 84 | * This code indicates, that the devices were not initialised because they are not in reset state. 85 | */ 86 | LPC24XX_CAN_INIT_ERR, 87 | 88 | /*! \brief MODE ERROR 89 | * 90 | * This code indicates, that the device cannot be accessed with the wanted mode. 91 | */ 92 | LPC24XX_CAN_MODE_ERR, 93 | 94 | /*! \brief OPEN ERROR 95 | * 96 | * This code indicates, that a device cannot be used, because it is not opened. 97 | */ 98 | LPC24XX_CAN_OPEN_ERR, 99 | 100 | /*! \brief CLOSE ERROR 101 | * 102 | * This code indicates, that the device cannot be closed. 103 | */ 104 | LPC24XX_CAN_CLOSE_ERR, 105 | 106 | /*! \brief FUNCTION CODE ERROR 107 | * 108 | * This code indicates, that the given function code is not valid. 109 | */ 110 | LPC24XX_CAN_FUNC_ERR, 111 | 112 | /*! \brief ARGUMENT ERROR 113 | * 114 | * This code indicates, that an argument check has failed. 115 | */ 116 | LPC24XX_CAN_ARG_ERR, 117 | 118 | /*! \brief NO DATA ERROR 119 | * 120 | * This code indicates, that no data is available. 121 | */ 122 | LPC24XX_CAN_NO_DATA_ERR 123 | }; 124 | 125 | 126 | /*------------------------------------------------------------------------------------------------*/ 127 | /*! \brief Functioncodes for CANIoCtl() */ 128 | /*------------------------------------------------------------------------------------------------*/ 129 | /*! \brief I/O CONTROL FUNCTIONCODES 130 | * 131 | * This enumeration defines the required functioncode values for the lowlevel 132 | * device driver function IoCtl(). 133 | */ 134 | /*------------------------------------------------------------------------------------------------*/ 135 | enum { 136 | /*! \brief GET DRIVER IDENT CODE 137 | * 138 | * This standard function code gets the driver identification code. 139 | * 140 | * arg = pointer to local ident variable (CPU_INT32U *) 141 | */ 142 | IO_LPC24XX_CAN_GET_IDENT = 0x0, 143 | 144 | /*! \brief GET DRIVER ERRORCODE 145 | * 146 | * This standard function code gets the driver errorcode. 147 | * 148 | * arg = pointer to local errorcode variable (CPU_INT16U *) 149 | */ 150 | IO_LPC24XX_CAN_GET_ERRNO, 151 | 152 | /*! \brief GET DRIVER NAME 153 | * 154 | * This standard function code gets the (human readable) driver name. 155 | * 156 | * arg = pointer to local string variable (char *) 157 | */ 158 | IO_LPC24XX_CAN_GET_DRVNAME, 159 | 160 | /*! \brief SET BUS BAUDRATE 161 | * 162 | * This function code sets the bus baudrate. 163 | * 164 | * arg = pointer to local baudrate variable (CPU_INT32U *) 165 | */ 166 | IO_LPC24XX_CAN_SET_BAUDRATE = 0x10, 167 | /*! \brief Enable Bus 168 | * 169 | * This enum value is the functioncode to start the CAN controller interface. Most common 170 | * is to set the CAN controller in active mode. 171 | * 172 | * The parameter pointer is not used for this function. 173 | */ 174 | IO_LPC24XX_CAN_START, 175 | /*! \brief Disable Bus 176 | * 177 | * This enum value is the functioncode to stop the CAN controller interface. Most common 178 | * is to set the CAN controller in passive mode. 179 | * 180 | * The parameter pointer is not used for this function. 181 | */ 182 | IO_LPC24XX_CAN_STOP, 183 | /*! \brief Set Receiver to Standard Identifier 184 | * 185 | * This enum value is the functioncode to configure the CAN receiver to receive only 186 | * CAN standard identifiers. 187 | * 188 | * The parameter pointer is not used for this function. 189 | */ 190 | IO_LPC24XX_CAN_RX_STANDARD, 191 | /*! \brief Set Receiver to Extended Identifier 192 | * 193 | * This enum value is the functioncode to configure the CAN receiver to receive only 194 | * CAN extended identifiers. 195 | * 196 | * The parameter pointer is not used for this function. 197 | */ 198 | IO_LPC24XX_CAN_RX_EXTENDED, 199 | /*! \brief Get TX Buffer Status 200 | * 201 | * This enum value is the functioncode to get the status of the current transmit 202 | * buffer. 203 | * 204 | * The parameter pointer shall point to a CPU_INT08U variable, where the status 205 | * shall be written to. 206 | */ 207 | IO_LPC24XX_CAN_TX_READY, 208 | /*! \brief Disable RX Interrupts 209 | * 210 | * This enum value is the functioncode to disable the receiption complete interrupt. 211 | * 212 | */ 213 | IO_LPC24XX_CAN_GET_NODE_STATUS, 214 | /*! \brief Set standard filter 215 | * 216 | * This enum value is the functioncode to set standard acceptance filter for the 217 | * CAN controller. 218 | * 219 | * The parameter pointer is not used for this function. 220 | */ 221 | IO_LPC24XX_CAN_SET_STD_FILTER, 222 | /*! \brief Set standard group filter 223 | * 224 | * This enum value is the functioncode to set standard group acceptance filter for the 225 | * CAN controller. 226 | * 227 | * The parameter pointer is not used for this function. 228 | */ 229 | IO_LPC24XX_CAN_SET_STD_GROUP_FILTER, 230 | /*! \brief Set extended filter 231 | * 232 | * This enum value is the functioncode to set extended acceptance filter for the 233 | * CAN controller. 234 | * 235 | * The parameter pointer is not used for this function. 236 | */ 237 | IO_LPC24XX_CAN_SET_EXT_FILTER, 238 | /*! \brief Set extended group filter 239 | * 240 | * This enum value is the functioncode to set extended group acceptance filter for the 241 | * CAN controller. 242 | * 243 | * The parameter pointer is not used for this function. 244 | */ 245 | IO_LPC24XX_CAN_SET_EXT_GROUP_FILTER, 246 | /*! \brief Number of Needed IO Function Codes 247 | * 248 | * This enum value holds the number of function codes, which are used within the 249 | * can bus layer. 250 | */ 251 | IO_LPC24XX_CAN_IO_FUNC_N 252 | }; 253 | 254 | /*------------------------------------------------------------------------------------------------*/ 255 | /*! \brief Dynamic CAN driver data */ 256 | typedef struct 257 | { 258 | /*! \brief Use Marker 259 | * 260 | * This member holds a marker which indicates, that this device is in use: 261 | * 0 = Device idle, 262 | * 1 = Device in use 263 | */ 264 | CPU_INT08U Use; 265 | 266 | } LPC24XX_CAN_DATA; 267 | 268 | 269 | /*------------------------------------------------------------------------------------------------*/ 270 | /*! 271 | * \brief CAN FRAME 272 | * 273 | * This structure contains all needed data to handle a single CAN frame 274 | */ 275 | /*------------------------------------------------------------------------------------------------*/ 276 | typedef struct { 277 | /*--------------------------------------------------------------------------------------------*/ 278 | /*! 279 | * \brief CAN IDENTIFIER 280 | * 281 | * This member holds the CAN identifier. 282 | * 283 | */ 284 | /*--------------------------------------------------------------------------------------------*/ 285 | CPU_INT32U Identifier; 286 | /*--------------------------------------------------------------------------------------------*/ 287 | /*! 288 | * \brief CAN PAYLOAD 289 | * 290 | * This member holds up to 8 bytes, which can be handled with a single CAN message. 291 | */ 292 | /*--------------------------------------------------------------------------------------------*/ 293 | CPU_INT08U Data[8]; 294 | /*--------------------------------------------------------------------------------------------*/ 295 | /*! 296 | * \brief CAN DLC 297 | * 298 | * This member holds the number of valid datas in the payload. 299 | */ 300 | /*--------------------------------------------------------------------------------------------*/ 301 | CPU_INT08U DLC; 302 | /*--------------------------------------------------------------------------------------------*/ 303 | /*! 304 | * \brief SPARE 305 | * 306 | * These bytes are added to get a frame size of an integral number of pointers. 307 | */ 308 | /*--------------------------------------------------------------------------------------------*/ 309 | CPU_INT08U Spare[3]; 310 | 311 | } LPC24XX_CANFRM; 312 | 313 | /* 314 | *************************************************************************************************** 315 | * FUNCTION PROTOTYPES 316 | *************************************************************************************************** 317 | */ 318 | 319 | CPU_INT16S LPC24XXCANInit(CPU_INT32U arg); 320 | CPU_INT16S LPC24XXCANOpen(CPU_INT16S drvId, CPU_INT32U devName, CPU_INT16U mode); 321 | CPU_INT16S LPC24XXCANClose(CPU_INT16S paraId); 322 | CPU_INT16S LPC24XXCANIoCtl(CPU_INT16S paraId, CPU_INT16U func, void *argp); 323 | CPU_INT16S LPC24XXCANRead(CPU_INT16S paraId, CPU_INT08U *buffer, CPU_INT16U size); 324 | CPU_INT16S LPC24XXCANWrite(CPU_INT16S paraId, CPU_INT08U *buffer, CPU_INT16U size); 325 | 326 | 327 | /* 328 | *************************************************************************************************** 329 | * ERROR SECTION 330 | *************************************************************************************************** 331 | */ 332 | 333 | 334 | #endif 335 | 336 | /*! } */ 337 | -------------------------------------------------------------------------------- /Drivers/LPC24XX/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | #ifndef _DRVCANREG_H 26 | #define _DRVCANREG_H 27 | 28 | #include "cpu.h" 29 | 30 | /* Vectored Interrupt Controller (VIC) */ 31 | #define LPC24XX_CAN_VICINTENABLE (*((volatile CPU_INT32U *) 0xFFFFF010)) 32 | #define LPC24XX_CAN_VICINTENCLR (*((volatile CPU_INT32U *) 0xFFFFF014)) 33 | #define LPC24XX_CAN_VICSOFTINTCLR (*((volatile CPU_INT32U *) 0xFFFFF01C)) 34 | #define LPC24XX_CAN_VICSWPRIOMASK (*((volatile CPU_INT32U *) 0xFFFFF024)) 35 | #define LPC24XX_CAN_VICVECTADDR (*((volatile CPU_INT32U *) 0xFFFFF030)) 36 | #define LPC24XX_CAN_VICINTSELECT (*((volatile CPU_INT32U *) 0xFFFFF00C)) 37 | 38 | #define LPC24XX_CAN_VICVECTADDR23 (*((volatile CPU_INT32U *) 0xFFFFF15C)) 39 | 40 | #define LPC24XX_CAN_VICVECTPRIO23 (*((volatile CPU_INT32U *) 0xFFFFF25C)) 41 | 42 | /* Clocking and Power Control */ 43 | #define LPC24XX_CAN_PCONP (*((volatile CPU_INT32U *) 0xE01FC0C4)) 44 | 45 | /* Pin Connect Block */ 46 | #define LPC24XX_CAN_PINSEL0 (*((volatile CPU_INT32U *) 0xE002C000)) 47 | #define LPC24XX_CAN_PINSEL1 (*((volatile CPU_INT32U *) 0xE002C004)) 48 | 49 | /* CAN Acceptance Filter */ 50 | #define LPC24XX_CAN_AFMR (*((volatile CPU_INT32U *) 0xE003C000)) 51 | #define LPC24XX_CAN_SFF_SA (*((volatile CPU_INT32U *) 0xE003C004)) 52 | #define LPC24XX_CAN_SFF_GRP_SA (*((volatile CPU_INT32U *) 0xE003C008)) 53 | #define LPC24XX_CAN_EFF_SA (*((volatile CPU_INT32U *) 0xE003C00C)) 54 | #define LPC24XX_CAN_EFF_GRP_SA (*((volatile CPU_INT32U *) 0xE003C010)) 55 | #define LPC24XX_CAN_END_OF_TABLE (*((volatile CPU_INT32U *) 0xE003C014)) 56 | 57 | /* CAN Central Registers */ 58 | #define LPC24XX_CAN_CANTXSR (*((volatile CPU_INT32U *) 0xE0040000)) 59 | #define LPC24XX_CAN_CANRXSR (*((volatile CPU_INT32U *) 0xE0040004)) 60 | #define LPC24XX_CAN_CANMSR (*((volatile CPU_INT32U *) 0xE0040008)) 61 | 62 | /* CAN Controller 1 (CAN1) */ 63 | #define LPC24XX_CAN_C1MOD (*((volatile CPU_INT32U *) 0xE0044000)) 64 | #define LPC24XX_CAN_C1CMR (*((volatile CPU_INT32U *) 0xE0044004)) 65 | #define LPC24XX_CAN_C1GSR (*((volatile CPU_INT32U *) 0xE0044008)) 66 | #define LPC24XX_CAN_C1ICR (*((volatile CPU_INT32U *) 0xE004400C)) 67 | #define LPC24XX_CAN_C1IER (*((volatile CPU_INT32U *) 0xE0044010)) 68 | #define LPC24XX_CAN_C1BTR (*((volatile CPU_INT32U *) 0xE0044014)) 69 | #define LPC24XX_CAN_C1EWL (*((volatile CPU_INT32U *) 0xE0044018)) 70 | #define LPC24XX_CAN_C1SR (*((volatile CPU_INT32U *) 0xE004401C)) 71 | #define LPC24XX_CAN_C1RFS (*((volatile CPU_INT32U *) 0xE0044020)) 72 | #define LPC24XX_CAN_C1RID (*((volatile CPU_INT32U *) 0xE0044024)) 73 | #define LPC24XX_CAN_C1RDA (*((volatile CPU_INT32U *) 0xE0044028)) 74 | #define LPC24XX_CAN_C1RDB (*((volatile CPU_INT32U *) 0xE004402C)) 75 | #define LPC24XX_CAN_C1TFI1 (*((volatile CPU_INT32U *) 0xE0044030)) 76 | #define LPC24XX_CAN_C1TID1 (*((volatile CPU_INT32U *) 0xE0044034)) 77 | #define LPC24XX_CAN_C1TDA1 (*((volatile CPU_INT32U *) 0xE0044038)) 78 | #define LPC24XX_CAN_C1TDB1 (*((volatile CPU_INT32U *) 0xE004403C)) 79 | #define LPC24XX_CAN_C1TFI2 (*((volatile CPU_INT32U *) 0xE0044040)) 80 | #define LPC24XX_CAN_C1TID2 (*((volatile CPU_INT32U *) 0xE0044044)) 81 | #define LPC24XX_CAN_C1TDA2 (*((volatile CPU_INT32U *) 0xE0044048)) 82 | #define LPC24XX_CAN_C1TDB2 (*((volatile CPU_INT32U *) 0xE004404C)) 83 | #define LPC24XX_CAN_C1TFI3 (*((volatile CPU_INT32U *) 0xE0044050)) 84 | #define LPC24XX_CAN_C1TID3 (*((volatile CPU_INT32U *) 0xE0044054)) 85 | #define LPC24XX_CAN_C1TDA3 (*((volatile CPU_INT32U *) 0xE0044058)) 86 | #define LPC24XX_CAN_C1TDB3 (*((volatile CPU_INT32U *) 0xE004405C)) 87 | 88 | /* CAN Controller 2 (CAN2) */ 89 | #define LPC24XX_CAN_C2MOD (*((volatile CPU_INT32U *) 0xE0048000)) 90 | #define LPC24XX_CAN_C2CMR (*((volatile CPU_INT32U *) 0xE0048004)) 91 | #define LPC24XX_CAN_C2GSR (*((volatile CPU_INT32U *) 0xE0048008)) 92 | #define LPC24XX_CAN_C2ICR (*((volatile CPU_INT32U *) 0xE004800C)) 93 | #define LPC24XX_CAN_C2IER (*((volatile CPU_INT32U *) 0xE0048010)) 94 | #define LPC24XX_CAN_C2BTR (*((volatile CPU_INT32U *) 0xE0048014)) 95 | #define LPC24XX_CAN_C2EWL (*((volatile CPU_INT32U *) 0xE0048018)) 96 | #define LPC24XX_CAN_C2SR (*((volatile CPU_INT32U *) 0xE004801C)) 97 | #define LPC24XX_CAN_C2RFS (*((volatile CPU_INT32U *) 0xE0048020)) 98 | #define LPC24XX_CAN_C2RID (*((volatile CPU_INT32U *) 0xE0048024)) 99 | #define LPC24XX_CAN_C2RDA (*((volatile CPU_INT32U *) 0xE0048028)) 100 | #define LPC24XX_CAN_C2RDB (*((volatile CPU_INT32U *) 0xE004802C)) 101 | #define LPC24XX_CAN_C2TFI1 (*((volatile CPU_INT32U *) 0xE0048030)) 102 | #define LPC24XX_CAN_C2TID1 (*((volatile CPU_INT32U *) 0xE0048034)) 103 | #define LPC24XX_CAN_C2TDA1 (*((volatile CPU_INT32U *) 0xE0048038)) 104 | #define LPC24XX_CAN_C2TDB1 (*((volatile CPU_INT32U *) 0xE004803C)) 105 | #define LPC24XX_CAN_C2TFI2 (*((volatile CPU_INT32U *) 0xE0048040)) 106 | #define LPC24XX_CAN_C2TID2 (*((volatile CPU_INT32U *) 0xE0048044)) 107 | #define LPC24XX_CAN_C2TDA2 (*((volatile CPU_INT32U *) 0xE0048048)) 108 | #define LPC24XX_CAN_C2TDB2 (*((volatile CPU_INT32U *) 0xE004804C)) 109 | #define LPC24XX_CAN_C2TFI3 (*((volatile CPU_INT32U *) 0xE0048050)) 110 | #define LPC24XX_CAN_C2TID3 (*((volatile CPU_INT32U *) 0xE0048054)) 111 | #define LPC24XX_CAN_C2TDA3 (*((volatile CPU_INT32U *) 0xE0048058)) 112 | #define LPC24XX_CAN_C2TDB3 (*((volatile CPU_INT32U *) 0xE004805C)) 113 | 114 | /* CAN Int Enable Register Bit definitions */ 115 | #define LPC24XX_CAN_IER_RX 0x00000001 /* RIE */ 116 | #define LPC24XX_CAN_IER_TX 0x00000602 /* TIE1-3 */ 117 | #define LPC24XX_CAN_IER_NS 0x000000A4 /* EIE, EPIE, BEIE */ 118 | 119 | /* CAN Interrupt and Capture Register Bit definitions */ 120 | #define LPC24XX_CAN_ICR_RI 0x00000001 121 | #define LPC24XX_CAN_ICR_TI1 0x00000002 122 | #define LPC24XX_CAN_ICR_EI 0x00000004 123 | #define LPC24XX_CAN_ICR_DOI 0x00000008 124 | #define LPC24XX_CAN_ICR_WUI 0x00000010 125 | #define LPC24XX_CAN_ICR_EPI 0x00000020 126 | #define LPC24XX_CAN_ICR_ALI 0x00000040 127 | #define LPC24XX_CAN_ICR_BEI 0x00000080 128 | #define LPC24XX_CAN_ICR_IDI 0x00000100 129 | #define LPC24XX_CAN_ICR_TI2 0x00000200 130 | #define LPC24XX_CAN_ICR_TI3 0x00000400 131 | 132 | /* CAN frame status register Bit definitions */ 133 | #define LPC24XX_CAN_DLC_MASK 0x000F0000L 134 | #define LPC24XX_CAN_RTR_MASK 0x40000000L 135 | #define LPC24XX_CAN_FF_MASK 0x80000000L 136 | 137 | #endif 138 | -------------------------------------------------------------------------------- /Drivers/MB96F340/drv_can_reg.c: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.c 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | /* 27 | **************************************************************************************************** 28 | * INCLUDES 29 | **************************************************************************************************** 30 | */ 31 | #include "drv_can.h" /* MB96F340 CAN driver declarations */ 32 | 33 | 34 | /* 35 | **************************************************************************************************** 36 | * GLOBAL DATA 37 | **************************************************************************************************** 38 | */ 39 | 40 | #if MB96F340_CAN_DEV_N == 1 41 | 42 | #if MB96F340_CAN_SELECT_CFG == 0 /*=== CHECK FOR SELECTED BUS: CAN 0 ========*/ 43 | 44 | #pragma asm 45 | .SECTION CAN_REG, DATA, LOCATE=0x0700 46 | .GLOBAL _CanReg 47 | _CanReg: .RES.B 16 48 | 49 | #pragma endasm 50 | 51 | #elif MB96F340_CAN_SELECT_CFG == 1 /*=== CHECK FOR SELECTED BUS: CAN 1 ========*/ 52 | 53 | #pragma asm 54 | .SECTION CAN_REG, DATA, LOCATE=0x0800 55 | .GLOBAL _CanReg 56 | _CanReg: .RES.B 16 57 | 58 | #pragma endasm 59 | 60 | #elif MB96F340_CAN_SELECT_CFG == 2 /*=== CHECK FOR SELECTED BUS: CAN 2 ========*/ 61 | 62 | #pragma asm 63 | .SECTION CAN_REG, DATA, LOCATE=0x0900 64 | .GLOBAL _CanReg 65 | _CanReg: .RES.B 16 66 | 67 | #pragma endasm 68 | 69 | #elif MB96F340_CAN_SELECT_CFG == 3 /*=== CHECK FOR SELECTED BUS: CAN 3 ========*/ 70 | 71 | #pragma asm 72 | .SECTION CAN_REG, DATA, LOCATE=0x0A00 73 | .GLOBAL _CanReg 74 | _CanReg: .RES.B 16 75 | 76 | #pragma endasm 77 | 78 | #elif MB96F340_CAN_SELECT_CFG == 4 /*=== CHECK FOR SELECTED BUS: CAN 4 ========*/ 79 | 80 | #pragma asm 81 | .SECTION CAN_REG, DATA, LOCATE=0x0B00 82 | .GLOBAL _CanReg 83 | _CanReg: .RES.B 16 84 | 85 | #pragma endasm 86 | 87 | #endif /*==========================================*/ 88 | 89 | #endif /* #if MB96F340_CAN_DEV_N == 1 */ 90 | -------------------------------------------------------------------------------- /Drivers/MB96F340/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_CAN_REG_H_ 27 | #define _DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | #include "cpu.h" /* CPU configuration */ 35 | 36 | /* 37 | **************************************************************************************************** 38 | * DATA TYPES 39 | **************************************************************************************************** 40 | */ 41 | 42 | /*------------------------------------------------------------------------------------------------*/ 43 | /*! 44 | * \brief OVERALL CAN REGISTERS 45 | * \ingroup MB96F340_CAN 46 | */ 47 | /*------------------------------------------------------------------------------------------------*/ 48 | typedef struct { 49 | CPU_INT16U CTRLR; /*!< CAN Control Register +0x0 */ 50 | CPU_INT16U STATR; /*!< CAN Status Register +0x2 */ 51 | CPU_INT08U ERRCNTL; /*!< CAN Error Counter (Transmit) +0x4 */ 52 | CPU_INT08U ERRCNTH; /*!< CAN Error Counter (Receive) +0x5 */ 53 | CPU_INT16U BTR; /*!< CAN BittTiming Register +0x6 */ 54 | CPU_INT16U INTR; /*!< CAN Interrupt Register +0x8 */ 55 | CPU_INT16U TESTR; /*!< CAN Test Register +0xA */ 56 | CPU_INT16U BRPER; /*!< CAN BRP Extension Register +0xC */ 57 | CPU_INT16U _r1; /*!< reserved +0xE */ 58 | CPU_INT16U IF1CREQ; /*!< CAN IF1 Command Request Register +0x10 */ 59 | CPU_INT16U IF1CMSK; /*!< CAN IF1 Command Mask Register +0x12 */ 60 | CPU_INT16U IF1MSK1; /*!< CAN IF1 Mask Register +0x14 */ 61 | CPU_INT16U IF1MSK2; /*!< CAN IF1 Mask Register +0x16 */ 62 | CPU_INT16U IF1ARB1; /*!< CAN IF1 Arbitration register +0x18 */ 63 | CPU_INT16U IF1ARB2; /*!< CAN IF1 Arbitration register +0x1A */ 64 | CPU_INT16U IF1MCTR; /*!< CAN IF1 Message Control Register +0x1C */ 65 | CPU_INT16U IF1DTA1; /*!< CAN IF1 Data A1 +0x1E */ 66 | CPU_INT16U IF1DTA2; /*!< CAN IF1 Data A2 +0x20 */ 67 | CPU_INT16U IF1DTB1; /*!< CAN IF1 Data B1 +0x22 */ 68 | CPU_INT16U IF1DTB2; /*!< CAN IF1 Data B2 +0x24 */ 69 | 70 | CPU_INT16U _r2[0xD]; /*!< reserved +0x26 .. 0x3E */ 71 | 72 | CPU_INT16U IF2CREQ; /*!< CAN IF2 Command Request Register +0x40 */ 73 | CPU_INT16U IF2CMSK; /*!< CAN IF2 Command Mask Register +0x42 */ 74 | CPU_INT16U IF2MSK1; /*!< CAN IF2 Mask Register +0x44 */ 75 | CPU_INT16U IF2MSK2; /*!< CAN IF2 Mask Register +0x46 */ 76 | CPU_INT16U IF2ARB1; /*!< CAN IF2 Arbitration register +0x48 */ 77 | CPU_INT16U IF2ARB2; /*!< CAN IF2 Arbitration register +0x4A */ 78 | CPU_INT16U IF2MCTR; /*!< CAN IF2 Message Control Register +0x4C */ 79 | CPU_INT16U IF2DTA1; /*!< CAN IF2 Data A1 +0x4E */ 80 | CPU_INT16U IF2DTA2; /*!< CAN IF2 Data A2 +0x50 */ 81 | CPU_INT16U IF2DTB1; /*!< CAN IF2 Data B1 +0x52 */ 82 | CPU_INT16U IF2DTB2; /*!< CAN IF1 Data B2 +0x54 */ 83 | 84 | CPU_INT16U _r3[0x15]; /*!< reserved +0x56 .. 0x7E */ 85 | 86 | CPU_INT16U TREQR1; /*!< CAN Transmission Request Register +0x80 */ 87 | CPU_INT16U TREQR2; /*!< CAN Transmission Request Register +0x82 */ 88 | 89 | CPU_INT16U _r4[0x6]; /*!< reserved +0x84 .. 0x8E */ 90 | 91 | CPU_INT16U NEWDT1; /*!< CAN New Data Register +0x90 */ 92 | CPU_INT16U NEWDT2; /*!< CAN New Data Register +0x92 */ 93 | 94 | CPU_INT16U _r5[0x6]; /*!< reserved +0x94 .. 0x9E */ 95 | 96 | CPU_INT16U INTPND1; /*!< CAN Interrupt Pending Register +0xA0 */ 97 | CPU_INT16U INTPND2; /*!< CAN Interrupt Pending Register +0xA2 */ 98 | 99 | CPU_INT16U _r6[0x6]; /*!< reserved +0xA4 .. 0xAE */ 100 | 101 | CPU_INT16U MSGVAL1; /*!< CAN Message Valid Register +0xB0 */ 102 | CPU_INT16U MSGVAL2; /*!< CAN Message Valid Register +0xB2 */ 103 | 104 | CPU_INT16U _r7[0xD]; /*!< reserved +0xB4 .. 0xCC */ 105 | 106 | CPU_INT16U COER; /*!< CAN Output enable register +0xCE */ 107 | 108 | 109 | 110 | 111 | } CAN_REG; 112 | 113 | 114 | #endif /* #ifndef _DRV_CAN_REG_H_ */ 115 | 116 | -------------------------------------------------------------------------------- /Drivers/RM48L950/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_CAN_REG_H_ 27 | #define _DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | 35 | #include "cpu.h" 36 | 37 | /* 38 | **************************************************************************************************** 39 | * DEFINES 40 | **************************************************************************************************** 41 | */ 42 | 43 | #define TIRM48_CAN_REG_BASE_ADDR_DCAN1 0xFFF7DC00 44 | #define TIRM48_CAN_REG_BASE_ADDR_DCAN2 0xFFF7DE00 45 | #define TIRM48_CAN_REG_BASE_ADDR_DCAN3 0xFFF7E000 46 | 47 | /* CAN Control Register */ 48 | #define TIRM48_CAN_REG_CTL_INIT_SET 0x00000001 49 | #define TIRM48_CAN_REG_CTL_IE0_SET 0x00000002 50 | #define TIRM48_CAN_REG_CTL_EIE_SET 0x00000008 51 | #define TIRM48_CAN_REG_CTL_CCE_SET 0x00000040 52 | #define TIRM48_CAN_REG_CTL_PMD_DIS 0x00001400 53 | 54 | /* Error and Status Register */ 55 | #define TIRM48_CAN_REG_ES_EPASS_SET 0x00000020 56 | #define TIRM48_CAN_REG_ES_BOFF_SET 0x00000080 57 | 58 | /* Interrupt Register */ 59 | #define TIRM48_CAN_REG_INT_ERR 0x00008000 60 | 61 | /* IF1/IF2 Command Registers */ 62 | //#define TIRM48_CAN_REG_IF_CMD_WR_SET 0x00800000 63 | //#define TIRM48_CAN_REG_IF_CMD_MASK_SET 0x00400000 64 | //#define TIRM48_CAN_REG_IF_CMD_ARB_SET 0x00200000 65 | //#define TIRM48_CAN_REG_IF_CMD_CONTROL_SET 0x00100000 66 | //#define TIRM48_CAN_REG_IF_CMD_CLRINTPND_SET 0x00080000 67 | //#define TIRM48_CAN_REG_IF_CMD_TXRQST_SET 0x00040000 68 | //#define TIRM48_CAN_REG_IF_CMD_NEWDAT_SET 0x00040000 69 | //#define TIRM48_CAN_REG_IF_CMD_DATA_SET 0x00020000 70 | //#define TIRM48_CAN_REG_IF_CMD_DATB_SET 0x00010000 71 | 72 | #define TIRM48_CAN_REG_IF_STAT_BUSY_SET 0x80 73 | 74 | /* IF1/IF2 Mask Registers */ 75 | #define TIRM48_CAN_REG_IF_MSK_MXTD_SET 0x80000000 76 | 77 | /* IF1/IF2 Arbitration Registers */ 78 | #define TIRM48_CAN_REG_IF_ARB_MSGVAL_SET 0x80000000 79 | #define TIRM48_CAN_REG_IF_ARB_XTD_SET 0x40000000 80 | #define TIRM48_CAN_REG_IF_ARB_DIR_SET 0x20000000 81 | 82 | /* IF1/IF2 Message Control Registers */ 83 | #define TIRM48_CAN_REG_IF_MCTL_DLC_MASK 0x0000000F 84 | #define TIRM48_CAN_REG_IF_MCTL_EOB_SET 0x00000080 85 | #define TIRM48_CAN_REG_IF_MCTL_RXIE_SET 0x00000400 86 | #define TIRM48_CAN_REG_IF_MCTL_TXIE_SET 0x00000800 87 | #define TIRM48_CAN_REG_IF_MCTL_UMASK_SET 0x00001000 88 | 89 | /* CAN TX IO Control Register */ 90 | #define TIRM48_CAN_REG_TIOC_FUNC_SET 0x00000008 91 | 92 | /* CAN RX IO Control Register */ 93 | #define TIRM48_CAN_REG_RIOC_FUNC_SET 0x00000008 94 | 95 | /* 96 | **************************************************************************************************** 97 | * DATA TYPES 98 | **************************************************************************************************** 99 | */ 100 | 101 | /*------------------------------------------------------------------------------------------------*/ 102 | /*! 103 | * \brief TIRM48 CAN MESSAGE INTERFACE REGISTERS 104 | * 105 | * \ingroup TIRM48_CAN 106 | * 107 | * This structure defines the TIRM48 CAN message interface registers. 108 | */ 109 | /*------------------------------------------------------------------------------------------------*/ 110 | typedef volatile struct { 111 | #if CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_LITTLE 112 | CPU_INT08U NBR; /*!< Command Register, Message Number */ 113 | CPU_INT08U STAT; /*!< Command Register, Status */ 114 | CPU_INT08U CMD; /*!< Command Register, Command */ 115 | CPU_INT08U RES1; /*!< Command Register, Reserved */ 116 | #else 117 | CPU_INT08U RES1; /*!< Command Register, Reserved */ 118 | CPU_INT08U CMD; /*!< Command Register, Command */ 119 | CPU_INT08U STAT; /*!< Command Register, Status */ 120 | CPU_INT08U NBR; /*!< Command Register, Message Number */ 121 | #endif 122 | CPU_INT32U MSK; /*!< Mask Registers */ 123 | CPU_INT32U ARB; /*!< Arbitration Registers */ 124 | CPU_INT32U MCTL; /*!< Message Control Registers */ 125 | CPU_INT08U DATx[8]; /*!< Data A and Data B Registers */ 126 | CPU_INT32U RES2; /*!< Reserved */ 127 | CPU_INT32U RES3; /*!< Reserved */ 128 | } TIRM48_CAN_IF; 129 | 130 | /*------------------------------------------------------------------------------------------------*/ 131 | /*! 132 | * \brief TIRM48 CAN REGISTERS 133 | * 134 | * \ingroup TIRM48_CAN 135 | * 136 | * This structure defines the TIRM48 CAN registers. 137 | */ 138 | /*------------------------------------------------------------------------------------------------*/ 139 | typedef volatile struct { 140 | CPU_INT32U CTL; /*!< CAN Control Register */ 141 | CPU_INT32U ES; /*!< Error and Status Register */ 142 | CPU_INT32U ERRC; /*!< Error Counter Register */ 143 | CPU_INT32U BTR; /*!< Bit Timing Register */ 144 | CPU_INT32U INT; /*!< Interrupt Register */ 145 | CPU_INT32U TEST; /*!< Test Register */ 146 | CPU_INT32U RES_0x18; /*!< 0x18 Reserved */ 147 | CPU_INT32U PERR; /*!< Parity Error Code Register */ 148 | CPU_INT32U RES_0x20_0x7C[24]; /*!< 0x20 - 0x7C Reserved */ 149 | CPU_INT32U ABOTR; /*!< Auto-Bus-On Time Register */ 150 | CPU_INT32U TXRQX; /*!< Transmission Request X Register */ 151 | CPU_INT32U TXRQx[4]; /*!< Transmission Request Registers */ 152 | CPU_INT32U NWDATX; /*!< New Data X Register */ 153 | CPU_INT32U NWDATx[4]; /*!< New Data Registers */ 154 | CPU_INT32U INTPNDX; /*!< Interrupt Pending X Register */ 155 | CPU_INT32U INTPNDx[4]; /*!< Interrupt Pending Registers */ 156 | CPU_INT32U MSGVALX; /*!< Message Valid X Register */ 157 | CPU_INT32U MSGVALx[4]; /*!< Message Valid Registers */ 158 | CPU_INT32U RES_0xD4; /*!< 0xD4 Reserved */ 159 | CPU_INT32U INTMUXx[4]; /*!< Interrupt Multiplexer Registers */ 160 | CPU_INT32U RES_0xE8_0xFC[6]; /*!< 0xE8 - 0xFC Reserved */ 161 | TIRM48_CAN_IF IFx[2]; /*!< Message Interface Registers */ 162 | CPU_INT32U IF3OBS; /*!< IF3 Observation Register */ 163 | CPU_INT32U IF3MSK; /*!< IF3 Mask Register */ 164 | CPU_INT32U IF3ARB; /*!< IF3 Arbitration Register */ 165 | CPU_INT32U IF3MCTL; /*!< IF3 Message Control Register */ 166 | CPU_INT32U IF3DATA; /*!< IF3 Data A Register */ 167 | CPU_INT32U IF3DATB; /*!< IF3 Data B Register */ 168 | CPU_INT32U RES_0x158_0x15C[2]; /*!< 0x158 - 0x15C Reserved */ 169 | CPU_INT32U IF3UPD[4]; /*!< IF3 Update Enable Registers */ 170 | CPU_INT32U RES_0x170_0x1DC[28]; /*!< 0x170 - 0x1DC Reserved */ 171 | CPU_INT32U TIOC; /*!< CAN TX IO Control Register */ 172 | CPU_INT32U RIOC; /*!< CAN RX IO Control Register */ 173 | } TIRM48_CAN_REG; 174 | 175 | 176 | #endif /* #ifndef _DRV_CAN_REG_H_ */ 177 | 178 | -------------------------------------------------------------------------------- /Drivers/STM32F10X/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRVSTM32F10X_CANREG_H 27 | #define _DRVSTM32F10X_CANREG_H 28 | 29 | #include "cpu.h" 30 | 31 | /* 32 | **************************************************************************************************** 33 | * DEFINES 34 | **************************************************************************************************** 35 | */ 36 | 37 | #define STM32F10X_CAN1_BASE 0x40006400 /* CAN 1 base address */ 38 | #define STM32F10X_CAN2_BASE 0x40006800 /* CAN 2 base address */ 39 | 40 | /* STM32F10X_CAN Master Control Register bits */ 41 | #define STM32F10X_CAN_MCR_INRQ ((CPU_INT32U)0x00000001) /* Initialization request */ 42 | #define STM32F10X_CAN_MCR_SLEEP ((CPU_INT32U)0x00000002) /* Sleep mode request */ 43 | #define STM32F10X_CAN_MCR_TXFP ((CPU_INT32U)0x00000004) /* Transmit FIFO priority */ 44 | #define STM32F10X_CAN_MCR_RFLM ((CPU_INT32U)0x00000008) /* Receive FIFO locked mode */ 45 | #define STM32F10X_CAN_MCR_NART ((CPU_INT32U)0x00000010) /* No automatic retransmission */ 46 | #define STM32F10X_CAN_MCR_AWUM ((CPU_INT32U)0x00000020) /* Automatic wake up mode */ 47 | #define STM32F10X_CAN_MCR_ABOM ((CPU_INT32U)0x00000040) /* Automatic bus-off management */ 48 | #define STM32F10X_CAN_MCR_TTCM ((CPU_INT32U)0x00000080) /* time triggered communication */ 49 | 50 | /* STM32F10X_CAN Master Status Register bits */ 51 | #define STM32F10X_CAN_MSR_INAK ((CPU_INT32U)0x00000001) /* Initialization acknowledge */ 52 | #define STM32F10X_CAN_MSR_ERRI ((CPU_INT32U)0x00000004) /* Error interrupt */ 53 | #define STM32F10X_CAN_MSR_WKUI ((CPU_INT32U)0x00000008) /* Wake-up interrupt */ 54 | #define STM32F10X_CAN_MSR_SLAKI ((CPU_INT32U)0x00000010) /* Sleep acknowledge interrupt */ 55 | 56 | /* STM32F10X_CAN Transmit Status Register bits */ 57 | #define STM32F10X_CAN_TSR_RQCP0 ((CPU_INT32U)0x00000001) /* Request completed mailbox0 */ 58 | #define STM32F10X_CAN_TSR_TXOK0 ((CPU_INT32U)0x00000002) /* Transmission OK of mailbox0 */ 59 | #define STM32F10X_CAN_TSR_ABRQ0 ((CPU_INT32U)0x00000080) /* Abort request for mailbox0 */ 60 | #define STM32F10X_CAN_TSR_RQCP1 ((CPU_INT32U)0x00000100) /* Request completed mailbox1 */ 61 | #define STM32F10X_CAN_TSR_TXOK1 ((CPU_INT32U)0x00000200) /* Transmission OK of mailbox1 */ 62 | #define STM32F10X_CAN_TSR_ABRQ1 ((CPU_INT32U)0x00008000) /* Abort request for mailbox1 */ 63 | #define STM32F10X_CAN_TSR_RQCP2 ((CPU_INT32U)0x00010000) /* Request completed mailbox2 */ 64 | #define STM32F10X_CAN_TSR_TXOK2 ((CPU_INT32U)0x00020000) /* Transmission OK of mailbox2 */ 65 | #define STM32F10X_CAN_TSR_ABRQ2 ((CPU_INT32U)0x00800000) /* Abort request for mailbox2 */ 66 | #define STM32F10X_CAN_TSR_TME0 ((CPU_INT32U)0x04000000) /* Transmit mailbox 0 empty */ 67 | #define STM32F10X_CAN_TSR_TME1 ((CPU_INT32U)0x08000000) /* Transmit mailbox 1 empty */ 68 | #define STM32F10X_CAN_TSR_TME2 ((CPU_INT32U)0x10000000) /* Transmit mailbox 2 empty */ 69 | 70 | /* STM32F10X_CAN Receive FIFO 0 Register bits */ 71 | #define STM32F10X_CAN_RF0R_FULL0 ((CPU_INT32U)0x00000008) /* FIFO 0 full */ 72 | #define STM32F10X_CAN_RF0R_FOVR0 ((CPU_INT32U)0x00000010) /* FIFO 0 overrun */ 73 | #define STM32F10X_CAN_RF0R_RFOM0 ((CPU_INT32U)0x00000020) /* Release FIFO 0 output mailbox */ 74 | 75 | /* STM32F10X_CAN Receive FIFO 1 Register bits */ 76 | #define STM32F10X_CAN_RF1R_FULL1 ((CPU_INT32U)0x00000008) /* FIFO 1 full */ 77 | #define STM32F10X_CAN_RF1R_FOVR1 ((CPU_INT32U)0x00000010) /* FIFO 1 overrun */ 78 | #define STM32F10X_CAN_RF1R_RFOM1 ((CPU_INT32U)0x00000020) /* Release FIFO 1 output mailbox */ 79 | 80 | /* STM32F10X_CAN Error Status Register bits */ 81 | #define STM32F10X_CAN_ESR_EWGF ((CPU_INT32U)0x00000001) /* Error warning flag */ 82 | #define STM32F10X_CAN_ESR_EPVF ((CPU_INT32U)0x00000002) /* Error passive flag */ 83 | #define STM32F10X_CAN_ESR_BOFF ((CPU_INT32U)0x00000004) /* Bus-off flag */ 84 | 85 | /* STM32F10X_CAN Mailbox Transmit Request */ 86 | #define STM32F10X_CAN_TMIDxR_TXRQ ((CPU_INT32U)0x00000001) /* Transmit mailbox request */ 87 | 88 | /* STM32F10X_CAN Filter Master Register bits */ 89 | #define STM32F10X_CAN_FMR_FINIT ((CPU_INT32U)0x00000001) /* Filter init mode */ 90 | 91 | /* 92 | **************************************************************************************************** 93 | * DATA TYPES 94 | **************************************************************************************************** 95 | */ 96 | 97 | /*------------------------------------------------------------------------------------------------*/ 98 | /*! \brief CAN DEVICE REGISTER LAYOUT 99 | * 100 | * This types defines the register layout of the STM32F10X CAN TRANSCEIVER 101 | */ 102 | /*------------------------------------------------------------------------------------------------*/ 103 | 104 | typedef volatile struct { 105 | CPU_INT32U TIR; 106 | CPU_INT32U TDTR; 107 | CPU_INT32U TDLR; 108 | CPU_INT32U TDHR; 109 | } STM32F10X_CAN_TxMailBox_t; 110 | 111 | typedef volatile struct { 112 | CPU_INT32U RIR; 113 | CPU_INT32U RDTR; 114 | CPU_INT32U RDLR; 115 | CPU_INT32U RDHR; 116 | } STM32F10X_CAN_FIFOMailBox_t; 117 | 118 | typedef volatile struct { 119 | CPU_INT32U FR1; 120 | CPU_INT32U FR2; 121 | } STM32F10X_CAN_FilterRegister_t; 122 | 123 | typedef volatile struct { 124 | CPU_INT32U MCR; 125 | CPU_INT32U MSR; 126 | CPU_INT32U TSR; 127 | CPU_INT32U RF0R; 128 | CPU_INT32U RF1R; 129 | CPU_INT32U IER; 130 | CPU_INT32U ESR; 131 | CPU_INT32U BTR; 132 | CPU_INT32U RESERVED0[88]; 133 | STM32F10X_CAN_TxMailBox_t TxMailBox[3]; 134 | STM32F10X_CAN_FIFOMailBox_t FIFOMailBox[2]; 135 | CPU_INT32U RESERVED1[12]; 136 | CPU_INT32U FMR; 137 | CPU_INT32U FM1R; 138 | CPU_INT32U RESERVED2; 139 | CPU_INT32U FS1R; 140 | CPU_INT32U RESERVED3; 141 | CPU_INT32U FFA1R; 142 | CPU_INT32U RESERVED4; 143 | CPU_INT32U FA1R; 144 | CPU_INT32U RESERVED5[8]; 145 | STM32F10X_CAN_FilterRegister_t FilterRegister[28]; 146 | } STM32F10X_CAN_t; 147 | 148 | #endif 149 | -------------------------------------------------------------------------------- /Drivers/STM32F20X/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_CAN_REG_H_ 27 | #define _DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | 35 | #include "cpu.h" 36 | 37 | /* 38 | **************************************************************************************************** 39 | * DEFINES 40 | **************************************************************************************************** 41 | */ 42 | 43 | /* CAN 1/2 base addresses */ 44 | #define STM32F20X_CAN1_BASE 0x40006400 /* CAN 1 base address */ 45 | #define STM32F20X_CAN2_BASE 0x40006800 /* CAN 2 base address */ 46 | 47 | /* Master Control Register bits */ 48 | #define STM32F20X_CAN_MCR_INRQ ((CPU_INT32U)0x00000001) /* Initialization request */ 49 | #define STM32F20X_CAN_MCR_SLEEP ((CPU_INT32U)0x00000002) /* Sleep mode request */ 50 | #define STM32F20X_CAN_MCR_TXFP ((CPU_INT32U)0x00000004) /* Transmit FIFO priority */ 51 | #define STM32F20X_CAN_MCR_RFLM ((CPU_INT32U)0x00000008) /* Receive FIFO locked mode */ 52 | #define STM32F20X_CAN_MCR_NART ((CPU_INT32U)0x00000010) /* No automatic retransmission */ 53 | #define STM32F20X_CAN_MCR_AWUM ((CPU_INT32U)0x00000020) /* Automatic wake-up mode */ 54 | #define STM32F20X_CAN_MCR_ABOM ((CPU_INT32U)0x00000040) /* Automatic bus-off management */ 55 | #define STM32F20X_CAN_MCR_TTCM ((CPU_INT32U)0x00000080) /* Time triggered communication mode */ 56 | 57 | /* Master Status Register bits */ 58 | #define STM32F20X_CAN_MSR_INAK ((CPU_INT32U)0x00000001) /* Initialization acknowledge */ 59 | #define STM32F20X_CAN_MSR_ERRI ((CPU_INT32U)0x00000004) /* Error interrupt */ 60 | #define STM32F20X_CAN_MSR_WKUI ((CPU_INT32U)0x00000008) /* Wake-up interrupt */ 61 | #define STM32F20X_CAN_MSR_SLAKI ((CPU_INT32U)0x00000010) /* Sleep acknowledge interrupt */ 62 | 63 | /* Transmit Status Register bits */ 64 | #define STM32F20X_CAN_TSR_RQCP0 ((CPU_INT32U)0x00000001) /* Request completed mailbox0 */ 65 | #define STM32F20X_CAN_TSR_TXOK0 ((CPU_INT32U)0x00000002) /* Transmission OK of mailbox0 */ 66 | #define STM32F20X_CAN_TSR_ABRQ0 ((CPU_INT32U)0x00000080) /* Abort request for mailbox0 */ 67 | #define STM32F20X_CAN_TSR_RQCP1 ((CPU_INT32U)0x00000100) /* Request completed mailbox1 */ 68 | #define STM32F20X_CAN_TSR_TXOK1 ((CPU_INT32U)0x00000200) /* Transmission OK of mailbox1 */ 69 | #define STM32F20X_CAN_TSR_ABRQ1 ((CPU_INT32U)0x00008000) /* Abort request for mailbox1 */ 70 | #define STM32F20X_CAN_TSR_RQCP2 ((CPU_INT32U)0x00010000) /* Request completed mailbox2 */ 71 | #define STM32F20X_CAN_TSR_TXOK2 ((CPU_INT32U)0x00020000) /* Transmission OK of mailbox2 */ 72 | #define STM32F20X_CAN_TSR_ABRQ2 ((CPU_INT32U)0x00800000) /* Abort request for mailbox2 */ 73 | #define STM32F20X_CAN_TSR_TME0 ((CPU_INT32U)0x04000000) /* Transmit mailbox 0 empty */ 74 | #define STM32F20X_CAN_TSR_TME1 ((CPU_INT32U)0x08000000) /* Transmit mailbox 1 empty */ 75 | #define STM32F20X_CAN_TSR_TME2 ((CPU_INT32U)0x10000000) /* Transmit mailbox 2 empty */ 76 | 77 | /* Receive FIFO 0 Register bits */ 78 | #define STM32F20X_CAN_RF0R_FULL0 ((CPU_INT32U)0x00000008) /* FIFO 0 full */ 79 | #define STM32F20X_CAN_RF0R_FOVR0 ((CPU_INT32U)0x00000010) /* FIFO 0 overrun */ 80 | #define STM32F20X_CAN_RF0R_RFOM0 ((CPU_INT32U)0x00000020) /* Release FIFO 0 output mailbox */ 81 | 82 | /* Receive FIFO 1 Register bits */ 83 | #define STM32F20X_CAN_RF1R_FULL1 ((CPU_INT32U)0x00000008) /* FIFO 1 full */ 84 | #define STM32F20X_CAN_RF1R_FOVR1 ((CPU_INT32U)0x00000010) /* FIFO 1 overrun */ 85 | #define STM32F20X_CAN_RF1R_RFOM1 ((CPU_INT32U)0x00000020) /* Release FIFO 1 output mailbox */ 86 | 87 | /* Error Status Register bits */ 88 | #define STM32F20X_CAN_ESR_EWGF ((CPU_INT32U)0x00000001) /* Error warning flag */ 89 | #define STM32F20X_CAN_ESR_EPVF ((CPU_INT32U)0x00000002) /* Error passive flag */ 90 | #define STM32F20X_CAN_ESR_BOFF ((CPU_INT32U)0x00000004) /* Bus-off flag */ 91 | 92 | /* Mailbox Identifier Register */ 93 | #define STM32F20X_CAN_TIxR_TXRQ ((CPU_INT32U)0x00000001) /* Transmit mailbox request */ 94 | 95 | /* Filter Master Register bits */ 96 | #define STM32F20X_CAN_FMR_FINIT ((CPU_INT32U)0x00000001) /* Filter init mode */ 97 | 98 | /* 99 | **************************************************************************************************** 100 | * DATA TYPES 101 | **************************************************************************************************** 102 | */ 103 | 104 | /* TX Mailbox */ 105 | typedef volatile struct { 106 | CPU_INT32U TIR; 107 | CPU_INT32U TDTR; 108 | CPU_INT32U TDLR; 109 | CPU_INT32U TDHR; 110 | } STM32F20X_CAN_TxMailBox_t; 111 | 112 | /* FIFO Mailbox */ 113 | typedef volatile struct { 114 | CPU_INT32U RIR; 115 | CPU_INT32U RDTR; 116 | CPU_INT32U RDLR; 117 | CPU_INT32U RDHR; 118 | } STM32F20X_CAN_FIFOMailBox_t; 119 | 120 | /* Filter Register */ 121 | typedef volatile struct { 122 | CPU_INT32U FR1; 123 | CPU_INT32U FR2; 124 | } STM32F20X_CAN_FilterRegister_t; 125 | 126 | /* CAN Controller */ 127 | typedef volatile struct { 128 | CPU_INT32U MCR; 129 | CPU_INT32U MSR; 130 | CPU_INT32U TSR; 131 | CPU_INT32U RF0R; 132 | CPU_INT32U RF1R; 133 | CPU_INT32U IER; 134 | CPU_INT32U ESR; 135 | CPU_INT32U BTR; 136 | CPU_INT32U RESERVED0[88]; 137 | STM32F20X_CAN_TxMailBox_t TxMailBox[3]; 138 | STM32F20X_CAN_FIFOMailBox_t FIFOMailBox[2]; 139 | CPU_INT32U RESERVED1[12]; 140 | CPU_INT32U FMR; 141 | CPU_INT32U FM1R; 142 | CPU_INT32U RESERVED2; 143 | CPU_INT32U FS1R; 144 | CPU_INT32U RESERVED3; 145 | CPU_INT32U FFA1R; 146 | CPU_INT32U RESERVED4; 147 | CPU_INT32U FA1R; 148 | CPU_INT32U RESERVED5[8]; 149 | STM32F20X_CAN_FilterRegister_t FilterRegister[28]; 150 | } STM32F20X_CAN_t; 151 | 152 | #endif 153 | -------------------------------------------------------------------------------- /Drivers/STM32F4XX/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_CAN_REG_H_ 27 | #define _DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | 35 | #include "cpu.h" 36 | 37 | /* 38 | **************************************************************************************************** 39 | * DEFINES 40 | **************************************************************************************************** 41 | */ 42 | 43 | /* CAN 1/2 base addresses */ 44 | #define STM32F4XX_CAN1_BASE 0x40006400 /* CAN 1 base address */ 45 | #define STM32F4XX_CAN2_BASE 0x40006800 /* CAN 2 base address */ 46 | 47 | /* Master Control Register bits */ 48 | #define STM32F4XX_CAN_MCR_INRQ ((CPU_INT32U)0x00000001) /* Initialization request */ 49 | #define STM32F4XX_CAN_MCR_SLEEP ((CPU_INT32U)0x00000002) /* Sleep mode request */ 50 | #define STM32F4XX_CAN_MCR_TXFP ((CPU_INT32U)0x00000004) /* Transmit FIFO priority */ 51 | #define STM32F4XX_CAN_MCR_RFLM ((CPU_INT32U)0x00000008) /* Receive FIFO locked mode */ 52 | #define STM32F4XX_CAN_MCR_NART ((CPU_INT32U)0x00000010) /* No automatic retransmission */ 53 | #define STM32F4XX_CAN_MCR_AWUM ((CPU_INT32U)0x00000020) /* Automatic wake-up mode */ 54 | #define STM32F4XX_CAN_MCR_ABOM ((CPU_INT32U)0x00000040) /* Automatic bus-off management */ 55 | #define STM32F4XX_CAN_MCR_TTCM ((CPU_INT32U)0x00000080) /* Time triggered communication mode */ 56 | 57 | /* Master Status Register bits */ 58 | #define STM32F4XX_CAN_MSR_INAK ((CPU_INT32U)0x00000001) /* Initialization acknowledge */ 59 | #define STM32F4XX_CAN_MSR_ERRI ((CPU_INT32U)0x00000004) /* Error interrupt */ 60 | #define STM32F4XX_CAN_MSR_WKUI ((CPU_INT32U)0x00000008) /* Wake-up interrupt */ 61 | #define STM32F4XX_CAN_MSR_SLAKI ((CPU_INT32U)0x00000010) /* Sleep acknowledge interrupt */ 62 | 63 | /* Transmit Status Register bits */ 64 | #define STM32F4XX_CAN_TSR_RQCP0 ((CPU_INT32U)0x00000001) /* Request completed mailbox0 */ 65 | #define STM32F4XX_CAN_TSR_TXOK0 ((CPU_INT32U)0x00000002) /* Transmission OK of mailbox0 */ 66 | #define STM32F4XX_CAN_TSR_ABRQ0 ((CPU_INT32U)0x00000080) /* Abort request for mailbox0 */ 67 | #define STM32F4XX_CAN_TSR_RQCP1 ((CPU_INT32U)0x00000100) /* Request completed mailbox1 */ 68 | #define STM32F4XX_CAN_TSR_TXOK1 ((CPU_INT32U)0x00000200) /* Transmission OK of mailbox1 */ 69 | #define STM32F4XX_CAN_TSR_ABRQ1 ((CPU_INT32U)0x00008000) /* Abort request for mailbox1 */ 70 | #define STM32F4XX_CAN_TSR_RQCP2 ((CPU_INT32U)0x00010000) /* Request completed mailbox2 */ 71 | #define STM32F4XX_CAN_TSR_TXOK2 ((CPU_INT32U)0x00020000) /* Transmission OK of mailbox2 */ 72 | #define STM32F4XX_CAN_TSR_ABRQ2 ((CPU_INT32U)0x00800000) /* Abort request for mailbox2 */ 73 | #define STM32F4XX_CAN_TSR_TME0 ((CPU_INT32U)0x04000000) /* Transmit mailbox 0 empty */ 74 | #define STM32F4XX_CAN_TSR_TME1 ((CPU_INT32U)0x08000000) /* Transmit mailbox 1 empty */ 75 | #define STM32F4XX_CAN_TSR_TME2 ((CPU_INT32U)0x10000000) /* Transmit mailbox 2 empty */ 76 | 77 | /* Receive FIFO 0 Register bits */ 78 | #define STM32F4XX_CAN_RF0R_FULL0 ((CPU_INT32U)0x00000008) /* FIFO 0 full */ 79 | #define STM32F4XX_CAN_RF0R_FOVR0 ((CPU_INT32U)0x00000010) /* FIFO 0 overrun */ 80 | #define STM32F4XX_CAN_RF0R_RFOM0 ((CPU_INT32U)0x00000020) /* Release FIFO 0 output mailbox */ 81 | 82 | /* Receive FIFO 1 Register bits */ 83 | #define STM32F4XX_CAN_RF1R_FULL1 ((CPU_INT32U)0x00000008) /* FIFO 1 full */ 84 | #define STM32F4XX_CAN_RF1R_FOVR1 ((CPU_INT32U)0x00000010) /* FIFO 1 overrun */ 85 | #define STM32F4XX_CAN_RF1R_RFOM1 ((CPU_INT32U)0x00000020) /* Release FIFO 1 output mailbox */ 86 | 87 | /* Error Status Register bits */ 88 | #define STM32F4XX_CAN_ESR_EWGF ((CPU_INT32U)0x00000001) /* Error warning flag */ 89 | #define STM32F4XX_CAN_ESR_EPVF ((CPU_INT32U)0x00000002) /* Error passive flag */ 90 | #define STM32F4XX_CAN_ESR_BOFF ((CPU_INT32U)0x00000004) /* Bus-off flag */ 91 | 92 | /* Mailbox Identifier Register */ 93 | #define STM32F4XX_CAN_TIxR_TXRQ ((CPU_INT32U)0x00000001) /* Transmit mailbox request */ 94 | 95 | /* Filter Master Register bits */ 96 | #define STM32F4XX_CAN_FMR_FINIT ((CPU_INT32U)0x00000001) /* Filter init mode */ 97 | 98 | /* 99 | **************************************************************************************************** 100 | * DATA TYPES 101 | **************************************************************************************************** 102 | */ 103 | 104 | /* TX Mailbox */ 105 | typedef volatile struct { 106 | CPU_INT32U TIR; 107 | CPU_INT32U TDTR; 108 | CPU_INT32U TDLR; 109 | CPU_INT32U TDHR; 110 | } STM32F4XX_CAN_TxMailBox_t; 111 | 112 | /* FIFO Mailbox */ 113 | typedef volatile struct { 114 | CPU_INT32U RIR; 115 | CPU_INT32U RDTR; 116 | CPU_INT32U RDLR; 117 | CPU_INT32U RDHR; 118 | } STM32F4XX_CAN_FIFOMailBox_t; 119 | 120 | /* Filter Register */ 121 | typedef volatile struct { 122 | CPU_INT32U FR1; 123 | CPU_INT32U FR2; 124 | } STM32F4XX_CAN_FilterRegister_t; 125 | 126 | /* CAN Controller */ 127 | typedef volatile struct { 128 | CPU_INT32U MCR; 129 | CPU_INT32U MSR; 130 | CPU_INT32U TSR; 131 | CPU_INT32U RF0R; 132 | CPU_INT32U RF1R; 133 | CPU_INT32U IER; 134 | CPU_INT32U ESR; 135 | CPU_INT32U BTR; 136 | CPU_INT32U RESERVED0[88]; 137 | STM32F4XX_CAN_TxMailBox_t TxMailBox[3]; 138 | STM32F4XX_CAN_FIFOMailBox_t FIFOMailBox[2]; 139 | CPU_INT32U RESERVED1[12]; 140 | CPU_INT32U FMR; 141 | CPU_INT32U FM1R; 142 | CPU_INT32U RESERVED2; 143 | CPU_INT32U FS1R; 144 | CPU_INT32U RESERVED3; 145 | CPU_INT32U FFA1R; 146 | CPU_INT32U RESERVED4; 147 | CPU_INT32U FA1R; 148 | CPU_INT32U RESERVED5[8]; 149 | STM32F4XX_CAN_FilterRegister_t FilterRegister[28]; 150 | } STM32F4XX_CAN_t; 151 | 152 | #endif 153 | -------------------------------------------------------------------------------- /Drivers/STR91X/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_CAN_REG_H_ 27 | #define _DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | #include "cpu.h" 35 | 36 | /* 37 | **************************************************************************************************** 38 | * DEFINES 39 | **************************************************************************************************** 40 | */ 41 | /* unbuffered CAN base address */ 42 | #define ST91X_CAN_BASE_ADDR (volatile CPU_INT32U *) 0x5C009000 43 | 44 | /* registers used for CAN initialisation */ 45 | #define SCU_PRR1_REG *(volatile CPU_INT32U *) 0x5C002020 46 | #define SCU_PCGR1_REG *(volatile CPU_INT32U *) 0x5C002018 47 | #define SCU_GPIOOUT3_REG *(volatile CPU_INT32U *) 0x5C002050 48 | #define SCU_GPIOOUT5_REG *(volatile CPU_INT32U *) 0x5C002058 49 | #define SCU_GPIOIN3_REG *(volatile CPU_INT32U *) 0x5C002070 50 | #define SCU_GPIOIN5_REG *(volatile CPU_INT32U *) 0x5C002078 51 | 52 | #define GPIO3_DIR_REG *(volatile CPU_INT32U *) 0x58009400 53 | #define GPIO5_DIR_REG *(volatile CPU_INT32U *) 0x5800B400 54 | 55 | #define VIC0_INTER_REG *(volatile CPU_INT32U *) 0xFFFFF010 56 | #define VIC0_VAR_REG *(volatile CPU_INT32U *) 0xFFFFF030 57 | #define VIC0_VA0R_ADDR (volatile CPU_INT32U *) 0xFFFFF100 58 | #define VIC0_VC0R_ADDR (volatile CPU_INT32U *) 0xFFFFF200 59 | 60 | 61 | /*------------------------------------------------------------------------------------------------*/ 62 | /*! 63 | * \brief BIT DEFINITIONS 64 | * \ingroup ST91X_CAN 65 | * 66 | * This member holds a bit defintions for various registers of ST91X 67 | */ 68 | /*------------------------------------------------------------------------------------------------*/ 69 | 70 | /* Control register*/ 71 | #define CAN_CR_TEST 0x0080 72 | #define CAN_CR_CCE 0x0040 73 | #define CAN_CR_DAR 0x0020 74 | #define CAN_CR_EIE 0x0008 75 | #define CAN_CR_SIE 0x0004 76 | #define CAN_CR_IE 0x0002 77 | #define CAN_CR_INIT 0x0001 78 | 79 | /* Status register */ 80 | #define CAN_SR_BOFF 0x0080 81 | #define CAN_SR_EWARN 0x0040 82 | #define CAN_SR_EPASS 0x0020 83 | #define CAN_SR_RXOK 0x0010 84 | #define CAN_SR_TXOK 0x0008 85 | #define CAN_SR_LEC 0x0007 86 | 87 | /* Test register*/ 88 | #define CAN_TESTR_RX 0x0080 89 | #define CAN_TESTR_TX1 0x0040 90 | #define CAN_TESTR_TX0 0x0020 91 | #define CAN_TESTR_LBACK 0x0010 92 | #define CAN_TESTR_SILENT 0x0008 93 | #define CAN_TESTR_BASIC 0x0004 94 | 95 | /* IFn / Command Request register*/ 96 | #define CAN_CRR_BUSY 0x8000 97 | 98 | /* IFn / Command Mask register*/ 99 | #define CAN_CMR_WRRD 0x0080 100 | #define CAN_CMR_MASK 0x0040 101 | #define CAN_CMR_ARB 0x0020 102 | #define CAN_CMR_CONTROL 0x0010 103 | #define CAN_CMR_CLRINTPND 0x0008 104 | #define CAN_CMR_TXRQSTNEWDAT 0x0004 105 | #define CAN_CMR_DATAA 0x0002 106 | #define CAN_CMR_DATAB 0x0001 107 | 108 | /* IFn / Mask 2 register*/ 109 | #define CAN_M2R_MXTD 0x8000 110 | #define CAN_M2R_MDIR 0x4000 111 | 112 | /* IFn / Arbitration 2 register*/ 113 | #define CAN_A2R_MSGVAL 0x8000 114 | #define CAN_A2R_XTD 0x4000 115 | #define CAN_A2R_DIR 0x2000 116 | 117 | /* IFn / Message Control register*/ 118 | #define CAN_MCR_NEWDAT 0x8000 119 | #define CAN_MCR_MSGLST 0x4000 120 | #define CAN_MCR_INTPND 0x2000 121 | #define CAN_MCR_UMASK 0x1000 122 | #define CAN_MCR_TXIE 0x0800 123 | #define CAN_MCR_RXIE 0x0400 124 | #define CAN_MCR_RMTEN 0x0200 125 | #define CAN_MCR_TXRQST 0x0100 126 | #define CAN_MCR_EOB 0x0080 127 | 128 | /* 129 | **************************************************************************************************** 130 | * DATA TYPES 131 | **************************************************************************************************** 132 | */ 133 | 134 | /*------------------------------------------------------------------------------------------------*/ 135 | /*! 136 | * \brief REGISTER LAYOUT CAN MODULE OF ST91X 137 | * \ingroup ST91X_CAN 138 | * 139 | * This definition holds the register layout of the CAN module of ST91X. For detailed 140 | * register descriptions please refer to STR91F reference manual. 141 | */ 142 | /*------------------------------------------------------------------------------------------------*/ 143 | 144 | typedef struct { 145 | CPU_INT16U CRR; /* IFn Command request Register */ 146 | CPU_INT16U EMPTY1; 147 | CPU_INT16U CMR; /* IFn Command Mask Register */ 148 | CPU_INT16U EMPTY2; 149 | CPU_INT16U M1R; /* IFn Message Mask 1 Register */ 150 | CPU_INT16U EMPTY3; 151 | CPU_INT16U M2R; /* IFn Message Mask 2 Register */ 152 | CPU_INT16U EMPTY4; 153 | CPU_INT16U A1R; /* IFn Message Arbitration 1 Register */ 154 | CPU_INT16U EMPTY5; 155 | CPU_INT16U A2R; /* IFn Message Arbitration 2 Register */ 156 | CPU_INT16U EMPTY6; 157 | CPU_INT16U MCR; /* IFn Message Control Register */ 158 | CPU_INT16U EMPTY7; 159 | CPU_INT16U DA1R; /* IFn DATA A 1 Register */ 160 | CPU_INT16U EMPTY8; 161 | CPU_INT16U DA2R; /* IFn DATA A 2 Register */ 162 | CPU_INT16U EMPTY9; 163 | CPU_INT16U DB1R; /* IFn DATA B 1 Register */ 164 | CPU_INT16U EMPTY10; 165 | CPU_INT16U DB2R; /* IFn DATA B 2 Register */ 166 | CPU_INT16U EMPTY11[27]; 167 | } CAN_MSG_OBJS; 168 | 169 | 170 | typedef struct { 171 | CPU_INT16U CR; /* Control Register */ 172 | CPU_INT16U EMPTY1; 173 | CPU_INT16U SR; /* Status Register */ 174 | CPU_INT16U EMPTY2; 175 | CPU_INT16U ERR; /* Error counter Register */ 176 | CPU_INT16U EMPTY3; 177 | CPU_INT16U BTR; /* Bit Timing Register */ 178 | CPU_INT16U EMPTY4; 179 | CPU_INT16U IDR; /* Interrupt Identifier Register */ 180 | CPU_INT16U EMPTY5; 181 | CPU_INT16U TESTR; /* Test Register */ 182 | CPU_INT16U EMPTY6; 183 | CPU_INT16U BRPR; /* BRP Extension Register */ 184 | CPU_INT16U EMPTY7[3]; 185 | CAN_MSG_OBJS MsgObj[2]; 186 | CPU_INT16U EMPTY8[16]; 187 | CPU_INT16U TXR1R; /* Transmission request 1 Register */ 188 | CPU_INT16U EMPTY9; 189 | CPU_INT16U TXR2R; /* Transmission Request 2 Register */ 190 | CPU_INT16U EMPTY10[13]; 191 | CPU_INT16U ND1R; /* New Data 1 Register */ 192 | CPU_INT16U EMPTY11; 193 | CPU_INT16U ND2R; /* New Data 2 Register */ 194 | CPU_INT16U EMPTY12[13]; 195 | CPU_INT16U IP1R; /* Interrupt Pending 1 Register */ 196 | CPU_INT16U EMPTY13; 197 | CPU_INT16U IP2R; /* Interrupt Pending 2 Register */ 198 | CPU_INT16U EMPTY14[13]; 199 | CPU_INT16U MV1R; /* Message Valid 1 Register */ 200 | CPU_INT16U EMPTY15; 201 | CPU_INT16U MV2R; /* Message VAlid 2 Register */ 202 | CPU_INT16U EMPTY16; 203 | } CAN_ST91X; 204 | 205 | /* 206 | **************************************************************************************************** 207 | * FUNCTION PROTOTYPES 208 | **************************************************************************************************** 209 | */ 210 | 211 | /* 212 | **************************************************************************************************** 213 | * ERROR SECTION 214 | **************************************************************************************************** 215 | */ 216 | 217 | 218 | #endif /* #ifndef _DRV_CAN_REG_H_ */ 219 | 220 | 221 | 222 | 223 | -------------------------------------------------------------------------------- /Drivers/TMS28XX/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _TMS28XX_DRV_CAN_REG_H_ 27 | #define _TMS28XX_DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | #include "cpu.h" /* cpu declarations */ 35 | 36 | /* 37 | **************************************************************************************************** 38 | * DEFINES 39 | **************************************************************************************************** 40 | */ 41 | 42 | /*------------------------------------------------------------------------------------------------*/ 43 | /*! 44 | * \brief ECANA CONTROL AND STATUS REGISTER BASE ADDRESS 45 | * \ingroup TMS28XX_ECAN 46 | * 47 | * This Constant holds the Base Address of the eCANA Control and Status Register Base 48 | * Address. 49 | */ 50 | /*------------------------------------------------------------------------------------------------*/ 51 | #define TMS28XX_ECANA_BASE_ADDRESS 0x006000 52 | 53 | /*------------------------------------------------------------------------------------------------*/ 54 | /*! 55 | * \brief ECANB CONTROL AND STATUS REGISTER BASE ADDRESS 56 | * \ingroup TMS28XX_ECAN 57 | * 58 | * This Constant holds the Base Address of the eCANB Control and Status Register Base 59 | * Address. 60 | */ 61 | /*------------------------------------------------------------------------------------------------*/ 62 | #define TMS28XX_ECANB_BASE_ADDRESS 0x006200 63 | 64 | /*------------------------------------------------------------------------------------------------*/ 65 | /*! 66 | * \brief ECAN LOCAL ACCEPTANCE MASK ADDRESS OFFSET 67 | * \ingroup TMS28XX_ECAN 68 | * 69 | * This Constant holds the Address Offset of the eCAN Local Acceptance Mask. 70 | */ 71 | /*------------------------------------------------------------------------------------------------*/ 72 | #define TMS28XX_ECAN_LAM_OFFS_ADDRESS 0x000040 73 | 74 | /*------------------------------------------------------------------------------------------------*/ 75 | /*! 76 | * \brief ECAN MAILBOX REGISTERS ADDRESS OFFESET 77 | * \ingroup TMS28XX_ECAN 78 | * 79 | * This Constant holds the Address Offeset of the eCAN Mailbox Registers. 80 | */ 81 | /*------------------------------------------------------------------------------------------------*/ 82 | #define TMS28XX_ECAN_MBOX_OFFS_ADDRESS 0x000100 83 | 84 | /*------------------------------------------------------------------------------------------------*/ 85 | /*! 86 | * \brief ECAN RX MESSAGE NUMBER 87 | * \ingroup TMS28XX_ECAN 88 | * 89 | * This Constant holds the Number of the used Receive Message Buffer. 90 | */ 91 | /*------------------------------------------------------------------------------------------------*/ 92 | #define TMS_28XX_ECAN_RX_BUFFER 16 93 | 94 | /*------------------------------------------------------------------------------------------------*/ 95 | /*! 96 | * \brief ECAN TX MESSAGE NUMBER 97 | * \ingroup TMS28XX_ECAN 98 | * 99 | * This Constant holds the Number of the used Transmit Message Buffer. 100 | */ 101 | /*------------------------------------------------------------------------------------------------*/ 102 | #define TMS_28XX_ECAN_TX_BUFFER 0L 103 | 104 | #if (TMS_28XX_ECAN_RX_BUFFER == TMS_28XX_ECAN_TX_BUFFER) 105 | #error: "Not Allowed! RX and TX Buffer must be different!" 106 | #endif 107 | 108 | /* 109 | **************************************************************************************************** 110 | * DATA TYPES 111 | **************************************************************************************************** 112 | */ 113 | /*------------------------------------------------------------------------------------------------*/ 114 | /*! 115 | * \brief ECAN CONTROL & STATUS REGISTER 116 | * \ingroup TMS28XX_ECAN 117 | * 118 | * This structure holds the eCAN Control and Status registers. 119 | */ 120 | /*------------------------------------------------------------------------------------------------*/ 121 | typedef struct { 122 | volatile CPU_INT32U CANME; /*!< Mailbox Enable */ 123 | volatile CPU_INT32U CANMD; /*!< Mailbox Direction */ 124 | volatile CPU_INT32U CANTRS; /*!< Transmit Request Set */ 125 | volatile CPU_INT32U CANTRR; /*!< Transmit Request Reset */ 126 | volatile CPU_INT32U CANTA; /*!< Transmit Acknowledge */ 127 | volatile CPU_INT32U CANAA; /*!< Abort Acknowledge */ 128 | volatile CPU_INT32U CANRMP; /*!< Received Message Pending */ 129 | volatile CPU_INT32U CANRML; /*!< Received Message Lost */ 130 | volatile CPU_INT32U CANRFP; /*!< Remote Frame Pending */ 131 | volatile CPU_INT32U CANGAM; /*!< Global Acceptance Mask */ 132 | volatile CPU_INT32U CANMC; /*!< Master Control */ 133 | volatile CPU_INT32U CANBTC; /*!< Bit Timing */ 134 | volatile CPU_INT32U CANES; /*!< Error Status */ 135 | volatile CPU_INT32U CANTEC; /*!< Transmit Error Counter */ 136 | volatile CPU_INT32U CANREC; /*!< Receive Error Counter */ 137 | volatile CPU_INT32U CANGIF0; /*!< Global Interrupt Flag 0 */ 138 | volatile CPU_INT32U CANGIM; /*!< Global Interrupt Mask 0 */ 139 | volatile CPU_INT32U CANGIF1; /*!< Global Interrupt Flag 1 */ 140 | volatile CPU_INT32U CANMIM; /*!< Mailbox Interrupt Mask */ 141 | volatile CPU_INT32U CANMIL; /*!< Mailbox Interrupt Level */ 142 | volatile CPU_INT32U CANOPC; /*!< Overwrite Protection Control */ 143 | volatile CPU_INT32U CANTIOC; /*!< TX I/O Control */ 144 | volatile CPU_INT32U CANRIOC; /*!< RX I/O Control */ 145 | volatile CPU_INT32U CANTSC; /*!< Time-stamp counter */ 146 | volatile CPU_INT32U CANTOC; /*!< Time-out Control */ 147 | volatile CPU_INT32U CANTOS; /*!< Time-out Status */ 148 | 149 | }TMS28XX_ECAN_REGS; 150 | 151 | /*------------------------------------------------------------------------------------------------*/ 152 | /*! 153 | * \brief ECAN MAILBOX REGISTERS 154 | * \ingroup TMS28XX_ECAN 155 | * 156 | * This structure holds the eCAN Mailbox Registers. 157 | */ 158 | /*------------------------------------------------------------------------------------------------*/ 159 | typedef struct { 160 | volatile CPU_INT32U MSGID; /*!< eCAN Message ID (MSGID) */ 161 | volatile CPU_INT32U MSGCTRL; /*!< eCAN Message Control Field */ 162 | /* (MSGCTRL) */ 163 | volatile CPU_INT32U MDL; /*!< eCAN Message Data Register low */ 164 | /* (MDR_H) */ 165 | volatile CPU_INT32U MDH; /*!< eCAN Message Data Register high */ 166 | /* (MDR_H) */ 167 | }TMS28XX_ECAN_MBOX; 168 | 169 | 170 | typedef interrupt void(*ECANINT)(void); 171 | 172 | 173 | 174 | #endif /* #ifndef _TMS28XX_DRV_CAN_REG_H_ */ 175 | -------------------------------------------------------------------------------- /Drivers/Template/BSP/Template/can_bsp.c: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * CAN BSP DRIVER CODE 22 | * 23 | * Template 24 | * 25 | * Filename : can_bsp.c 26 | * Version : V2.42.01 27 | ********************************************************************************************************* 28 | */ 29 | 30 | /* 31 | ********************************************************************************************************* 32 | * INCLUDES 33 | ********************************************************************************************************* 34 | */ 35 | 36 | #include "drv_can.h" 37 | #include "drv_def.h" 38 | #include "can_bsp.h" 39 | 40 | #if ((CANBUS_RX_HANDLER_EN > 0u) || \ 41 | (CANBUS_TX_HANDLER_EN > 0u) || \ 42 | (CANBUS_NS_HANDLER_EN > 0u)) 43 | #include "can_bus.h" 44 | #endif 45 | 46 | 47 | /* 48 | ********************************************************************************************************* 49 | * DEFINES 50 | ********************************************************************************************************* 51 | */ 52 | 53 | 54 | /* 55 | ********************************************************************************************************* 56 | * MACROS 57 | ********************************************************************************************************* 58 | */ 59 | 60 | 61 | /* 62 | ********************************************************************************************************* 63 | * INTERNAL DATA TYPES 64 | ********************************************************************************************************* 65 | */ 66 | 67 | 68 | /* 69 | ********************************************************************************************************* 70 | * LOCAL DATA 71 | ********************************************************************************************************* 72 | */ 73 | /* Array Holds Initialized Node ID of Module */ 74 | static CPU_INT08U _CAN_DevIds[_CAN_N_DEV]; 75 | 76 | 77 | /* 78 | ********************************************************************************************************* 79 | * GLOBAL DATA 80 | ********************************************************************************************************* 81 | */ 82 | 83 | 84 | /* 85 | ********************************************************************************************************* 86 | CONSTANTS 87 | ********************************************************************************************************* 88 | */ 89 | 90 | 91 | /* 92 | ********************************************************************************************************* 93 | * FUNCTIONS 94 | ********************************************************************************************************* 95 | */ 96 | 97 | /* 98 | ********************************************************************************************************* 99 | * _CAN_BSP_IntVectSet() 100 | * 101 | * Description : This function is used to assign ISR handlers for CAN functionality. 102 | * 103 | * Argument(s) : none. 104 | * 105 | * Return(s) : none. 106 | * 107 | * Caller(s) : none. 108 | * 109 | * Note(s) : none. 110 | ********************************************************************************************************* 111 | */ 112 | 113 | void _CAN_BSP_IntVectSet (void) 114 | { 115 | 116 | #if ((CANBUS_RX_HANDLER_EN > 0u) || \ 117 | (CANBUS_TX_HANDLER_EN > 0u) || \ 118 | (CANBUS_NS_HANDLER_EN > 0u)) 119 | 120 | #endif 121 | } 122 | 123 | 124 | /* 125 | ********************************************************************************************************* 126 | * _CAN_PinSetting() 127 | * 128 | * Description : This Function provides all the necessary Pin Settings for the required CAN Device. 129 | * 130 | * Argument(s) : para_id Selects the CAN Device [_CAN_BUS_0, _CAN_BUS_1]. 131 | * 132 | * Return(s) : Returns error value if improper CAN Device used, if not returns 'DEF_OK'. 133 | * 134 | * Caller(s) : _CAN_Init(). 135 | * 136 | * Note(s) : none. 137 | ********************************************************************************************************* 138 | */ 139 | 140 | CPU_BOOLEAN _CAN_PinSetting (CPU_INT08U para_id) 141 | { 142 | CPU_BOOLEAN bsp_err; 143 | 144 | 145 | bsp_err = DEF_OK; /* Init Var(s). */ 146 | 147 | return (bsp_err); 148 | } 149 | 150 | 151 | /* 152 | ********************************************************************************************************* 153 | * _CAN_CalcTimingReg() 154 | * 155 | * Description : Calculates the Timing Register Values according to the given Baudrate Settings. 156 | * 157 | * Argument(s) : data Pointer to the Baudrate Settings. 158 | * 159 | * Return(s) : Returns error value of 'DEF_FAIL' if Timeout occurred, if not returns 'DEF_OK'. 160 | * 161 | * Caller(s) : _CAN_Init(). 162 | * _CAN_IoCtl(). 163 | * 164 | * Note(s) : none. 165 | ********************************************************************************************************* 166 | */ 167 | 168 | CPU_BOOLEAN _CAN_CalcTimingReg (_CAN_BAUD *data) 169 | { 170 | 171 | return (DEF_OK); 172 | } 173 | 174 | 175 | /* 176 | ********************************************************************************************************* 177 | * _CAN_SetDevIds() 178 | * 179 | * Description : This Function sets the Device IDs for the ISRs. 180 | * 181 | * Argument(s) : dev_id CAN Device ID. 182 | * 183 | * dev_name CAN Device Name. 184 | * 185 | * Return(s) : none. 186 | * 187 | * Caller(s) : _CAN_Open(). 188 | * 189 | * Note(s) : none. 190 | ********************************************************************************************************* 191 | */ 192 | 193 | #if ((CANBUS_RX_HANDLER_EN > 0u) || \ 194 | (CANBUS_TX_HANDLER_EN > 0u) || \ 195 | (CANBUS_NS_HANDLER_EN > 0u)) 196 | void _CAN_SetDevIds (CPU_INT08U dev_id, 197 | CPU_INT08U dev_name) 198 | { 199 | _CAN_DevIds[dev_name] = dev_id; 200 | } 201 | #endif 202 | 203 | 204 | /* 205 | ********************************************************************************************************* 206 | * _CANx_ISR_Handler() 207 | * 208 | * Description : This holds the Generic CAN Interrupt Handler(s) for a given CAN Channel. This can be 209 | * configured differently based on the IVT table requirements for CAN Rx, Tx, and NS handling. 210 | * It is assumed that only one CAN ISR handler is needed. Additional ISR handlers must be 211 | * added based on the quantity of CAN channels (One ISR Handler per channel). 212 | * 213 | * Argument(s) : cpu_id Function pointer ID from CPU. 214 | * 215 | * Return(s) : none. 216 | * 217 | * Caller(s) : _CAN_BSP_IntVectSet(). 218 | * 219 | * Note(s) : none. 220 | ********************************************************************************************************* 221 | */ 222 | 223 | #if ((CANBUS_RX_HANDLER_EN > 0u) || \ 224 | (CANBUS_TX_HANDLER_EN > 0u) || \ 225 | (CANBUS_NS_HANDLER_EN > 0u)) 226 | void _CAN0_ISR_Handler (CPU_INT32U cpu_id) 227 | { 228 | 229 | } 230 | 231 | #endif 232 | -------------------------------------------------------------------------------- /Drivers/Template/BSP/Template/can_bsp.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * CAN BSP DRIVER CODE 22 | * 23 | * Template 24 | * 25 | * Filename : can_bsp.h 26 | * Version : V2.42.01 27 | ********************************************************************************************************* 28 | */ 29 | 30 | #ifndef _CAN_BSP_H_ 31 | #define _CAN_BSP_H_ 32 | 33 | 34 | /* 35 | ********************************************************************************************************* 36 | * INCLUDES 37 | ********************************************************************************************************* 38 | */ 39 | 40 | #include "cpu.h" 41 | #include "lib_def.h" 42 | #include 43 | 44 | 45 | /* 46 | ********************************************************************************************************* 47 | * DEFINES 48 | ********************************************************************************************************* 49 | */ 50 | 51 | 52 | /* 53 | ********************************************************************************************************* 54 | * REGISTER DEFINITIONS 55 | ********************************************************************************************************* 56 | */ 57 | 58 | 59 | /* 60 | ********************************************************************************************************* 61 | * REGISTERS 62 | ********************************************************************************************************* 63 | */ 64 | 65 | 66 | /* 67 | ********************************************************************************************************* 68 | * MACROS 69 | ********************************************************************************************************* 70 | */ 71 | 72 | 73 | /* 74 | ********************************************************************************************************* 75 | * FUNCTION PROTOTYPES 76 | ********************************************************************************************************* 77 | */ 78 | 79 | CPU_BOOLEAN _CAN_PinSetting (CPU_INT08U para_id); 80 | 81 | CPU_BOOLEAN _CAN_CalcTimingReg (_CAN_BAUD *data); 82 | 83 | 84 | #if ((CANBUS_RX_HANDLER_EN > 0) || \ 85 | (CANBUS_TX_HANDLER_EN > 0) || \ 86 | (CANBUS_NS_HANDLER_EN > 0)) 87 | void _CAN_BSP_IntVectSet(void); 88 | 89 | void _CAN_SetDevIds (CPU_INT08U dev_id, 90 | CPU_INT08U dev_name); 91 | 92 | void _CAN0_ISR_Handler (CPU_INT32U cpu_id); 93 | 94 | #endif 95 | 96 | 97 | /* 98 | ********************************************************************************************************* 99 | * MODULE END 100 | ********************************************************************************************************* 101 | */ 102 | 103 | #endif 104 | -------------------------------------------------------------------------------- /Drivers/Template/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * CAN DRIVER REGISTER CODE 22 | * 23 | * Template 24 | * 25 | * Filename : drv_can_reg.h 26 | * Version : V2.42.01 27 | ********************************************************************************************************* 28 | */ 29 | 30 | #ifndef _DRV_CAN_REG_H 31 | #define _DRV_CAN_REG_H 32 | 33 | 34 | /* 35 | ********************************************************************************************************* 36 | * INCLUDES 37 | ********************************************************************************************************* 38 | */ 39 | 40 | #include "cpu.h" 41 | #include "can_cfg.h" 42 | 43 | 44 | /* 45 | ********************************************************************************************************* 46 | * DEFAULT CONFIGURATION 47 | ********************************************************************************************************* 48 | */ 49 | 50 | 51 | /* 52 | ********************************************************************************************************* 53 | * ADDRESS REGISTERS 54 | ********************************************************************************************************* 55 | */ 56 | 57 | 58 | /* 59 | **************************************************************************************************** 60 | * BIT DEFINITIONS 61 | **************************************************************************************************** 62 | */ 63 | 64 | 65 | /* 66 | ********************************************************************************************************* 67 | * MACROS 68 | * 69 | * Note(s) : (1) When Using Extended IDs for Rx'd Messages, its required to save both the Standard 70 | * Section and Extended Section of the ID and placed both in the Rx Frame in the 71 | * following Format: 72 | * Bits: 31 30 29 18 0 73 | * uC/CAN Frame: [ 0u | RTR | IDE | Standard ID | Extended ID ] 74 | ********************************************************************************************************* 75 | */ 76 | 77 | 78 | /* 79 | ********************************************************************************************************* 80 | * DATA ARRAY 81 | ********************************************************************************************************* 82 | */ 83 | 84 | 85 | /* 86 | ********************************************************************************************************* 87 | * DATA TYPES 88 | ********************************************************************************************************* 89 | */ 90 | 91 | 92 | /* 93 | ********************************************************************************************************* 94 | * CAN REGISTER 95 | * 96 | * Description : Structure defines the CAN Register Structure. 97 | * 98 | * Note(s) : none. 99 | ********************************************************************************************************* 100 | */ 101 | 102 | typedef volatile struct _can_reg { /* ---------- CAN CONTROLLER REGISTER SUMMARY --------- */ 103 | /* $$$ - Insert CAN Register Map Structure - $$$ */ 104 | } _CAN_REG; 105 | 106 | 107 | /* 108 | ********************************************************************************************************* 109 | * CAN BAUDRATE REGISTER 110 | * 111 | * Description : Structure defines the CAN BaudRate Register Structure. 112 | * 113 | * Note(s) : none. 114 | ********************************************************************************************************* 115 | */ 116 | 117 | typedef struct _can_baud { 118 | CPU_INT32U BaudRate; /* Holds the Baudrate. */ 119 | CPU_INT32U SamplePoint; /* Holds the Sample point in 0.1% */ 120 | CPU_INT32U ReSynchJumpWidth; /* Holds the Re-Synchronization Jump Width in 0.1% */ 121 | CPU_INT08U PrescalerDiv; /* Holds the Prescaler Divide Factor */ 122 | CPU_INT08U SJW; /* Holds the Re-Synch Jump Width (StdValue = 1) */ 123 | CPU_INT08U PropagationSeg; /* Holds the Propagation Segment Time (StdValue = 2) */ 124 | CPU_INT08U PhaseBufSeg1; /* Holds the Phase Buffer Segment 1 (StdValue = 7) */ 125 | CPU_INT08U PhaseBufSeg2; /* Holds the Phase Buffer Segment 2 (StdValue = 7) */ 126 | } _CAN_BAUD; 127 | 128 | 129 | /* 130 | ********************************************************************************************************* 131 | * FUNCTION PROTOTYPES 132 | ********************************************************************************************************* 133 | */ 134 | 135 | 136 | /* 137 | ********************************************************************************************************* 138 | * ERROR SECTION 139 | ********************************************************************************************************* 140 | */ 141 | 142 | #endif 143 | -------------------------------------------------------------------------------- /Drivers/V850E2Fx4/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRVSTM32F10X_CANREG_H 27 | #define _DRVSTM32F10X_CANREG_H 28 | 29 | #include "cpu.h" 30 | 31 | 32 | /* 33 | **************************************************************************************************** 34 | * DEFINES 35 | **************************************************************************************************** 36 | */ 37 | 38 | #define FCN0_CAN_BASE 0xFF480000 39 | #define FCN1_CAN_BASE 0xFF4A0000 40 | #define FCN2_CAN_BASE 0xFF4C0000 41 | #define FCN3_CAN_BASE 0xFF4E0000 42 | #define FCN4_CAN_BASE 0xFF500000 43 | #define DCN0_CAN_BASE 0xFF520000 44 | 45 | #define FCN0_NUMBER_MB 64 46 | #define FCN1_NUMBER_MB 64 47 | #define FCN2_NUMBER_MB 64 48 | #define FCN3_NUMBER_MB 128 49 | #define FCN4_NUMBER_MB 128 50 | #define DCN0_NUMBER_MB 128 51 | 52 | 53 | /* V850E2-Fx4 Clock domain registers */ 54 | #define CKSC_113_ADDR (CPU_REG32 *) 0xFF42A0D0 55 | #define CKSC_115_ADDR (CPU_REG32 *) 0xFF42A0F0 56 | #define CKSC_PROTCMD1 (CPU_REG32 *) 0xFF428000 57 | 58 | #define CKSC_CLK_SRC_ID_HIGHSPEED 0x07 /* High Speed IntOsc */ 59 | #define CKSC_CLK_SRC_ID_MAINOSC 0x0C /* MainOsc */ 60 | #define CKSC_CLK_SRC_ID_PLL1_1 0x1C /* PLL1/1 */ 61 | #define CKSC_CLK_SRC_ID_PLL1_2 0x1D /* PLL1/2 */ 62 | #define CKSC_CLK_SRC_ID_PLL1_4 0x1F /* PLL1/4 */ 63 | #define CKSC_CLK_SRC_ID_PLL1_8 0x22 /* PLL1/8 */ 64 | 65 | 66 | /* 8 Bit Message Buffer Registers */ 67 | #define FCNxM000DAT0B 0x00001000 68 | 69 | /* 16 Bit Message Buffer Register */ 70 | #define FCNxM000DAT0H 0x00009000 71 | 72 | /* Module Registers - mask control register */ 73 | #define FCNxCMMKCTL01H 0x00008300 74 | 75 | /* Module Register - mask control */ 76 | #define FCNxCMMKCTL01W 0x00010300 77 | 78 | 79 | /* 80 | **************************************************************************************************** 81 | * DATA TYPES 82 | **************************************************************************************************** 83 | */ 84 | 85 | /*------------------------------------------------------------------------------------------------*/ 86 | /*! \brief CAN DEVICE REGISTER LAYOUT 87 | * 88 | * This type defines the global and module CAN register layout. 89 | */ 90 | /*------------------------------------------------------------------------------------------------*/ 91 | 92 | typedef volatile struct { 93 | 94 | CPU_INT08U spare0[8]; 95 | CPU_INT08U FCNnGMCSPRE; 96 | CPU_INT08U spare1[23]; 97 | CPU_INT08U FCNnGMADCTL; 98 | CPU_INT08U spare2[0x227]; 99 | CPU_INT08U FCNnCMLCSTR; 100 | CPU_INT08U spare3[3]; 101 | CPU_INT08U FCNnCMINSTR; 102 | CPU_INT08U spare4[27]; 103 | CPU_INT08U FCNnCMBRPRS; 104 | CPU_INT08U spare5[15]; 105 | CPU_INT08U FCNnCMLISTR; 106 | CPU_INT08U spare6[15]; 107 | CPU_INT08U FCNnCMLOSTR; 108 | CPU_INT08U spare7[0x7D77]; 109 | 110 | CPU_INT16U FCNnGMCLCTL; 111 | CPU_INT08U spare8[0x16]; 112 | CPU_INT16U FCNnGMABCTL; 113 | CPU_INT08U spare9[0x226]; 114 | CPU_INT16U FCNnCMCLCTL; 115 | CPU_INT08U spare10[0xE]; 116 | CPU_INT16U FCNnCMERCNT; 117 | CPU_INT08U spare11[0x6]; 118 | CPU_INT16U FCNnCMIECTL; 119 | CPU_INT08U spare12[0x6]; 120 | CPU_INT16U FCNnCMISCTL; 121 | CPU_INT08U spare13[0xE]; 122 | CPU_INT16U FCNnCMBTCTL; 123 | CPU_INT08U spare14[0xE]; 124 | CPU_INT16U FCNnCMRGRX; 125 | CPU_INT08U spare15[0xE]; 126 | CPU_INT16U FCNnCMTGTX; 127 | CPU_INT08U spare16[0x6]; 128 | CPU_INT16U FCNnCMTSCTL; 129 | } V850E2_GLOB_MOD_REG; 130 | 131 | /*------------------------------------------------------------------------------------------------*/ 132 | /*! \brief CAN DEVICE REGISTER LAYOUT 133 | * 134 | * This type defines the message buffer register layout in 8 bit and 16 bit format. 135 | */ 136 | /*------------------------------------------------------------------------------------------------*/ 137 | typedef volatile struct { 138 | struct { 139 | CPU_INT08U DATA; 140 | CPU_INT08U spare1[3]; 141 | }FCNnMmDATA[8]; 142 | 143 | CPU_INT08U FCNnMmDTLGB; 144 | CPU_INT08U spare3[3]; 145 | CPU_INT08U FCNnMmSTRB; 146 | CPU_INT08U spare4[27]; 147 | } V850E2_MB_8BIT; 148 | 149 | typedef volatile struct { 150 | struct { 151 | CPU_INT16U DATA; 152 | CPU_INT16U spare1[3]; 153 | }FCNnMmDAT[4]; 154 | 155 | CPU_INT16U spare2[4]; 156 | CPU_INT16U FCNnMmMID0; 157 | CPU_INT16U spare3[3]; 158 | CPU_INT16U FCNnMmMID1; 159 | CPU_INT16U spare4[3]; 160 | CPU_INT16U FCNnMmCTL; 161 | CPU_INT16U spare5[3]; 162 | } V850E2_MB_16BIT; 163 | 164 | /*------------------------------------------------------------------------------------------------*/ 165 | /*! \brief CAN DEVICE REGISTER LAYOUT 166 | * 167 | * This type defines the mask control register layout for 32 bit access. 168 | */ 169 | /*------------------------------------------------------------------------------------------------*/ 170 | typedef volatile struct { 171 | CPU_INT32U FCnNCMMKCTL01; 172 | CPU_INT08U spare1[12]; 173 | CPU_INT32U FCnNCMMKCTL03; 174 | CPU_INT08U spare2[12]; 175 | CPU_INT32U FCnNCMMKCTL05; 176 | CPU_INT08U spare3[12]; 177 | CPU_INT32U FCnNCMMKCTL07; 178 | CPU_INT08U spare4[12]; 179 | CPU_INT32U FCnNCMMKCTL09; 180 | CPU_INT08U spare5[12]; 181 | CPU_INT32U FCnNCMMKCTL11; 182 | CPU_INT08U spare6[12]; 183 | CPU_INT32U FCnNCMMKCTL13; 184 | CPU_INT08U spare7[12]; 185 | CPU_INT32U FCnNCMMKCTL15; 186 | CPU_INT08U spare8[12]; 187 | } V850E2_MASK_CONTROL; 188 | 189 | 190 | #endif 191 | -------------------------------------------------------------------------------- /Drivers/XC167CI/drv_can_reg.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_can_reg.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_CAN_REG_H_ 27 | #define _DRV_CAN_REG_H_ 28 | 29 | /* 30 | **************************************************************************************************** 31 | * INCLUDES 32 | **************************************************************************************************** 33 | */ 34 | #include "cpu.h" 35 | 36 | /* 37 | **************************************************************************************************** 38 | * DEFINES 39 | **************************************************************************************************** 40 | */ 41 | /* 42 | **************************************************************************************************** 43 | * NODE A REGISTERS 44 | **************************************************************************************************** 45 | */ 46 | #define XC167_CAN_A_CR (*(volatile CPU_INT16U *) 0x200200L) 47 | #define XC167_CAN_A_SR (*(volatile CPU_INT16U *) 0x200204L) 48 | #define XC167_CAN_A_IR (*(volatile CPU_INT16U *) 0x200208L) 49 | #define XC167_CAN_A_BTRL (*(volatile CPU_INT16U *) 0x20020CL) 50 | #define XC167_CAN_A_BTRH (*(volatile CPU_INT16U *) 0x20020EL) 51 | #define XC167_CAN_A_GINP (*(volatile CPU_INT16U *) 0x200210L) 52 | #define XC167_CAN_A_FCRL (*(volatile CPU_INT16U *) 0x200214L) 53 | #define XC167_CAN_A_FCRH (*(volatile CPU_INT16U *) 0x200216L) 54 | #define XC167_CAN_A_IMRL0 (*(volatile CPU_INT16U *) 0x200218L) 55 | #define XC167_CAN_A_IMRH0 (*(volatile CPU_INT16U *) 0x20021AL) 56 | #define XC167_CAN_A_IMR4 (*(volatile CPU_INT16U *) 0x20021CL) 57 | #define XC167_CAN_A_ECNTL (*(volatile CPU_INT16U *) 0x200220L) 58 | #define XC167_CAN_A_ECNTH (*(volatile CPU_INT16U *) 0x200222L) 59 | 60 | /* 61 | **************************************************************************************************** 62 | * NODE B REGISTERS 63 | **************************************************************************************************** 64 | */ 65 | #define XC167_CAN_B_CR (*(volatile CPU_INT16U *) 0x200240L) 66 | #define XC167_CAN_B_SR (*(volatile CPU_INT16U *) 0x200244L) 67 | #define XC167_CAN_B_IR (*(volatile CPU_INT16U *) 0x200248L) 68 | #define XC167_CAN_B_BTRL (*(volatile CPU_INT16U *) 0x20024CL) 69 | #define XC167_CAN_B_BTRH (*(volatile CPU_INT16U *) 0x20024EL) 70 | #define XC167_CAN_B_GINP (*(volatile CPU_INT16U *) 0x200250L) 71 | #define XC167_CAN_B_FCRL (*(volatile CPU_INT16U *) 0x200254L) 72 | #define XC167_CAN_B_FCRH (*(volatile CPU_INT16U *) 0x200256L) 73 | #define XC167_CAN_B_IMRL0 (*(volatile CPU_INT16U *) 0x200258L) 74 | #define XC167_CAN_B_IMRH0 (*(volatile CPU_INT16U *) 0x20025AL) 75 | #define XC167_CAN_B_IMR4 (*(volatile CPU_INT16U *) 0x20025CL) 76 | #define XC167_CAN_B_ECNTL (*(volatile CPU_INT16U *) 0x200250L) 77 | #define XC167_CAN_B_ECNTH (*(volatile CPU_INT16U *) 0x200252L) 78 | 79 | /* 80 | **************************************************************************************************** 81 | * GLOBLA CONTROL REGISTERS 82 | **************************************************************************************************** 83 | */ 84 | #define XC167_CAN_RXIPNDL (*(volatile CPU_INT16U *) 0x200284L) 85 | #define XC167_CAN_RXIPNDH (*(volatile CPU_INT16U *) 0x200286L) 86 | #define XC167_CAN_TXIPNDL (*(volatile CPU_INT16U *) 0x200288L) 87 | #define XC167_CAN_TXIPNDH (*(volatile CPU_INT16U *) 0x20028AL) 88 | 89 | /* 90 | **************************************************************************************************** 91 | * MESSAGE OBJECTS 0 REGISTERS 92 | **************************************************************************************************** 93 | */ 94 | #define XC167_CAN_MSG0_BASEADDRESS (volatile CPU_INT16U *) 0x200300L 95 | 96 | /* 97 | **************************************************************************************************** 98 | * INTERRUPT CONTROL REGISTERS 99 | **************************************************************************************************** 100 | */ 101 | #define XC167_CAN_0IC (* (volatile CPU_INT16U *) 0x00F196L) 102 | #define XC167_CAN_1IC (* (volatile CPU_INT16U *) 0x00F142L) 103 | #define XC167_CAN_2IC (* (volatile CPU_INT16U *) 0x00F144L) 104 | #define XC167_CAN_3IC (* (volatile CPU_INT16U *) 0x00F146L) 105 | #define XC167_CAN_4IC (* (volatile CPU_INT16U *) 0x00F148L) 106 | #define XC167_CAN_5IC (* (volatile CPU_INT16U *) 0x00F14AL) 107 | #define XC167_CAN_6IC (* (volatile CPU_INT16U *) 0x00F14CL) 108 | #define XC167_CAN_7IC (* (volatile CPU_INT16U *) 0x00F14EL) 109 | 110 | #define XC167_ALTSEL0P9 (* (volatile CPU_INT16U *) 0xF138L) 111 | #define XC167_ALTSEL1P9 (* (volatile CPU_INT16U *) 0xF13AL) 112 | 113 | #define XC167_DP9 (* (volatile CPU_INT16U *) 0xFF18L) 114 | 115 | 116 | /* 117 | **************************************************************************************************** 118 | * MACROS 119 | **************************************************************************************************** 120 | */ 121 | 122 | /* 123 | **************************************************************************************************** 124 | * DATA TYPES 125 | **************************************************************************************************** 126 | */ 127 | typedef volatile struct MsgBOX_tag 128 | { 129 | CPU_INT16U MSGDRL0; 130 | CPU_INT16U MSGDRH0; 131 | CPU_INT16U MSGDRL4; 132 | CPU_INT16U MSGDRH4; 133 | CPU_INT16U MSGARL; 134 | CPU_INT16U MSGARH; 135 | CPU_INT16U MSGAMRL; 136 | CPU_INT16U MSGAMRH; 137 | CPU_INT16U MSGCTRL; 138 | CPU_INT16U MSGCTRH; 139 | CPU_INT16U MSGCFGL; 140 | CPU_INT16U MSGCFGH; 141 | CPU_INT16U MSGFGCRL; 142 | CPU_INT16U MSGFGCRH; 143 | CPU_INT32U Spare; 144 | } MsgBOX_t; 145 | 146 | /* 147 | **************************************************************************************************** 148 | * FUNCTION PROTOTYPES 149 | **************************************************************************************************** 150 | */ 151 | 152 | /* 153 | **************************************************************************************************** 154 | * ERROR SECTION 155 | **************************************************************************************************** 156 | */ 157 | 158 | 159 | #endif /* #ifndef _DRV_CAN_REG_H_ */ 160 | 161 | -------------------------------------------------------------------------------- /Drivers/drv_def.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | **************************************************************************************************** 21 | * Filename : drv_def.h 22 | * Version : V2.42.01 23 | **************************************************************************************************** 24 | */ 25 | 26 | #ifndef _DRV_DEF_H 27 | #define _DRV_DEF_H 28 | 29 | 30 | /**************************************************************************************************/ 31 | /* ACCESS TYPE DEFINITIONS */ 32 | /**************************************************************************************************/ 33 | 34 | 35 | /*------------------------------------------------------------------------------------------------*/ 36 | /*! \brief EXLCUSIVE ACCESS 37 | * 38 | * This define holds the value for mode coding bit 7: exclusive access 39 | */ 40 | /*------------------------------------------------------------------------------------------------*/ 41 | #define DEV_EXCLUSIVE (0u << 7u) 42 | 43 | /*------------------------------------------------------------------------------------------------*/ 44 | /*! \brief SHARED ACCESS 45 | * 46 | * This define holds the value for mode coding bit 7: shared access 47 | */ 48 | /*------------------------------------------------------------------------------------------------*/ 49 | #define DEV_SHARE (1u << 7u) 50 | 51 | 52 | /**************************************************************************************************/ 53 | /* PERMISSION DEFINITIONS */ 54 | /**************************************************************************************************/ 55 | 56 | 57 | /*------------------------------------------------------------------------------------------------*/ 58 | /*! \brief EXECUTE PERMISSION 59 | * 60 | * This define holds the value for mode coding bit 0: execute permission enabled 61 | */ 62 | /*------------------------------------------------------------------------------------------------*/ 63 | #define DEV_EXE (1u << 0u) 64 | 65 | /*------------------------------------------------------------------------------------------------*/ 66 | /*! \brief WRITE PERMISSION 67 | * 68 | * This define holds the value for mode coding bit 1: write permission enabled 69 | */ 70 | /*------------------------------------------------------------------------------------------------*/ 71 | #define DEV_WO (1u << 1u) 72 | 73 | /*------------------------------------------------------------------------------------------------*/ 74 | /*! \brief READ PERMISSION 75 | * 76 | * This define holds the value for mode coding bit 2: read permission enabled 77 | */ 78 | /*------------------------------------------------------------------------------------------------*/ 79 | #define DEV_RO (1u << 2u) 80 | 81 | 82 | /**************************************************************************************************/ 83 | /* ACCESS MODE DEFINITIONS */ 84 | /**************************************************************************************************/ 85 | 86 | 87 | /*------------------------------------------------------------------------------------------------*/ 88 | /*! \brief EXCLUSIVE READ/WRITE ACCESS 89 | * 90 | * This define holds the value for mode: exclusive read/write access 91 | */ 92 | /*------------------------------------------------------------------------------------------------*/ 93 | #define DEV_RW (DEV_EXCLUSIVE | DEV_WO | DEV_RO) 94 | 95 | /*------------------------------------------------------------------------------------------------*/ 96 | /*! \brief EXCLUSIVE READ/WRITE/EXECUTE ACCESS 97 | * 98 | * This define holds the value for mode: exclusive read/write/execute access 99 | */ 100 | /*------------------------------------------------------------------------------------------------*/ 101 | #define DEV_RWX (DEV_EXCLUSIVE | DEV_WO | DEV_RO | DEV_EXE) 102 | 103 | /*------------------------------------------------------------------------------------------------*/ 104 | /*! \brief SHARED WRITE ACCESS 105 | * 106 | * This define holds the value for mode: shared write access 107 | */ 108 | /*------------------------------------------------------------------------------------------------*/ 109 | #define DEV_SHWO (DEV_SHARE | DEV_WO) 110 | 111 | /*------------------------------------------------------------------------------------------------*/ 112 | /*! \brief SHARED READ ACCESS 113 | * 114 | * This define holds the value for mode: shared read access 115 | */ 116 | /*------------------------------------------------------------------------------------------------*/ 117 | #define DEV_SHRO (DEV_SHARE | DEV_RO) 118 | 119 | /*------------------------------------------------------------------------------------------------*/ 120 | /*! \brief SHARED READ/WRITE ACCESS 121 | * 122 | * This define holds the value for mode: shared read/write access 123 | */ 124 | /*------------------------------------------------------------------------------------------------*/ 125 | #define DEV_SHRW (DEV_SHARE | DEV_WO | DEV_RO) 126 | 127 | /*------------------------------------------------------------------------------------------------*/ 128 | /*! \brief SHARED READ/WRITE/EXECUTE ACCESS 129 | * 130 | * This define holds the value for mode: shared read/write/execute access 131 | */ 132 | /*------------------------------------------------------------------------------------------------*/ 133 | #define DEV_SHRWX (DEV_SHARE | DEV_WO | DEV_RO | DEV_EXE) 134 | 135 | 136 | #endif /* #ifndef _DRV_DEF_H */ 137 | 138 | -------------------------------------------------------------------------------- /Examples/NONE/can_demo.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * EXAMPLE CODE 4 | * 5 | * This file is provided as an example on how to use Micrium products. 6 | * 7 | * Please feel free to use any application code labeled as 'EXAMPLE CODE' in 8 | * your application products. Example code may be used as is, in whole or in 9 | * part, or may be used as a reference only. This file can be modified as 10 | * required to meet the end-product requirements. 11 | * 12 | ********************************************************************************************************* 13 | */ 14 | 15 | 16 | /* 17 | ********************************************************************************************************* 18 | * uC/CAN EXAMPLE DEMO 19 | * 20 | * Filename : can_demo.h 21 | * Version : V2.42.01 22 | ********************************************************************************************************* 23 | */ 24 | 25 | #ifndef _CAN_DEMO_H_ 26 | #define _CAN_DEMO_H_ 27 | 28 | 29 | /* 30 | ********************************************************************************************************* 31 | * INLCUDES 32 | ********************************************************************************************************* 33 | */ 34 | 35 | #include "cpu.h" 36 | 37 | #include "can_bus.h" 38 | #include "can_frm.h" 39 | #include "can_msg.h" 40 | #include "can_sig.h" 41 | #include "can_err.h" 42 | 43 | 44 | /* 45 | ********************************************************************************************************* 46 | * FUNCTION PROTOTYPES 47 | ********************************************************************************************************* 48 | */ 49 | 50 | void App_CAN_Startup(void); 51 | void StatusChange (void *Signal, 52 | CANSIG_VAL_T *NewVal, 53 | CPU_INT32U CallbackId); 54 | 55 | 56 | /* 57 | ********************************************************************************************************* 58 | * END 59 | ********************************************************************************************************* 60 | */ 61 | 62 | #endif /* #ifndef _CAN_DEMO_H_ */ 63 | -------------------------------------------------------------------------------- /Examples/uCOS-II/can_demo.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * EXAMPLE CODE 4 | * 5 | * This file is provided as an example on how to use Micrium products. 6 | * 7 | * Please feel free to use any application code labeled as 'EXAMPLE CODE' in 8 | * your application products. Example code may be used as is, in whole or in 9 | * part, or may be used as a reference only. This file can be modified as 10 | * required to meet the end-product requirements. 11 | * 12 | ********************************************************************************************************* 13 | */ 14 | 15 | 16 | /* 17 | ********************************************************************************************************* 18 | * uC/CAN EXAMPLE DEMO 19 | * 20 | * Filename : can_demo.h 21 | * Version : V2.42.01 22 | ********************************************************************************************************* 23 | */ 24 | 25 | #ifndef _CAN_DEMO_H_ 26 | #define _CAN_DEMO_H_ 27 | 28 | 29 | /* 30 | ********************************************************************************************************* 31 | * INLCUDES 32 | ********************************************************************************************************* 33 | */ 34 | 35 | #include "cpu.h" 36 | #include "app_cfg.h" 37 | #include "lib_def.h" 38 | 39 | #include "can_bus.h" 40 | #include "can_frm.h" 41 | #include "can_msg.h" 42 | #include "can_sig.h" 43 | #include "can_err.h" 44 | 45 | 46 | /* 47 | ********************************************************************************************************* 48 | * FUNCTION PROTOTYPES 49 | ********************************************************************************************************* 50 | */ 51 | 52 | void App_CAN_Startup(void); 53 | void StatusChange (void *Signal, 54 | CANSIG_VAL_T *NewVal, 55 | CPU_INT32U CallbackId); 56 | 57 | 58 | /* 59 | ********************************************************************************************************* 60 | * CONFIGURATION ERRORS 61 | ********************************************************************************************************* 62 | */ 63 | /* -------------- RX TASK PRIO & STK SIZE ------------- */ 64 | #ifndef APP_CFG_CAN_RX_TASK_PRIO 65 | #error "APP_CFG_CAN_RX_TASK_PRIO not #define'd in 'app_cfg.h'" 66 | #endif 67 | 68 | #ifndef APP_CFG_CAN_RX_TASK_STK_SIZE 69 | #error "APP_CFG_CAN_RX_TASK_STK_SIZE not #define'd in 'app_cfg.h'" 70 | #endif 71 | 72 | /* -------------- TX TASK PRIO & STK SIZE ------------- */ 73 | #ifndef APP_CFG_CAN_TX_TASK_PRIO 74 | #error "APP_CFG_CAN_TX_TASK_PRIO not #define'd in 'app_cfg.h'" 75 | #endif 76 | 77 | #ifndef APP_CFG_CAN_TX_TASK_STK_SIZE 78 | #error "APP_CFG_CAN_TX_TASK_STK_SIZE not #define'd in 'app_cfg.h'" 79 | #endif 80 | 81 | 82 | /* 83 | ********************************************************************************************************* 84 | * END 85 | ********************************************************************************************************* 86 | */ 87 | 88 | #endif /* #ifndef _CAN_DEMO_H_ */ 89 | -------------------------------------------------------------------------------- /Examples/uCOS-III/can_demo.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * EXAMPLE CODE 4 | * 5 | * This file is provided as an example on how to use Micrium products. 6 | * 7 | * Please feel free to use any application code labeled as 'EXAMPLE CODE' in 8 | * your application products. Example code may be used as is, in whole or in 9 | * part, or may be used as a reference only. This file can be modified as 10 | * required to meet the end-product requirements. 11 | * 12 | ********************************************************************************************************* 13 | */ 14 | 15 | 16 | /* 17 | ********************************************************************************************************* 18 | * uC/CAN EXAMPLE DEMO 19 | * 20 | * Filename : can_demo.h 21 | * Version : V2.42.01 22 | ********************************************************************************************************* 23 | */ 24 | 25 | #ifndef _CAN_DEMO_H_ 26 | #define _CAN_DEMO_H_ 27 | 28 | 29 | /* 30 | ********************************************************************************************************* 31 | * INLCUDES 32 | ********************************************************************************************************* 33 | */ 34 | 35 | #include "cpu.h" 36 | #include "app_cfg.h" 37 | #include "lib_def.h" 38 | 39 | #include "can_bus.h" 40 | #include "can_frm.h" 41 | #include "can_msg.h" 42 | #include "can_sig.h" 43 | #include "can_err.h" 44 | 45 | 46 | /* 47 | ********************************************************************************************************* 48 | * FUNCTION PROTOTYPES 49 | ********************************************************************************************************* 50 | */ 51 | 52 | void App_CAN_Startup(void); 53 | void StatusChange (void *Signal, 54 | CANSIG_VAL_T *NewVal, 55 | CPU_INT32U CallbackId); 56 | 57 | 58 | /* 59 | ********************************************************************************************************* 60 | * CONFIGURATION ERRORS 61 | ********************************************************************************************************* 62 | */ 63 | /* -------------- RX TASK PRIO & STK SIZE ------------- */ 64 | #ifndef APP_CFG_CAN_RX_TASK_PRIO 65 | #error "APP_CFG_CAN_RX_TASK_PRIO not #define'd in 'app_cfg.h'" 66 | #endif 67 | 68 | #ifndef APP_CFG_CAN_RX_TASK_STK_SIZE 69 | #error "APP_CFG_CAN_RX_TASK_STK_SIZE not #define'd in 'app_cfg.h'" 70 | #endif 71 | 72 | /* -------------- TX TASK PRIO & STK SIZE ------------- */ 73 | #ifndef APP_CFG_CAN_TX_TASK_PRIO 74 | #error "APP_CFG_CAN_TX_TASK_PRIO not #define'd in 'app_cfg.h'" 75 | #endif 76 | 77 | #ifndef APP_CFG_CAN_TX_TASK_STK_SIZE 78 | #error "APP_CFG_CAN_TX_TASK_STK_SIZE not #define'd in 'app_cfg.h'" 79 | #endif 80 | 81 | 82 | /* 83 | ********************************************************************************************************* 84 | * END 85 | ********************************************************************************************************* 86 | */ 87 | 88 | #endif /* #ifndef _CAN_DEMO_H_ */ 89 | -------------------------------------------------------------------------------- /OS/NONE/can_os.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * Filename : can_os.h 22 | * Version : V2.42.01 23 | ********************************************************************************************************* 24 | */ 25 | 26 | #ifndef _CAN_OS_H_ 27 | #define _CAN_OS_H_ 28 | 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | 35 | /* 36 | ********************************************************************************************************* 37 | * INCLUDES 38 | ********************************************************************************************************* 39 | */ 40 | 41 | #include "can_frm.h" /* CAN Frame handling */ 42 | #include "can_cfg.h" /* CAN Configuration defines */ 43 | 44 | 45 | /*-----------------------------------------------------------------------------------------------------*/ 46 | /*! \brief OS: NO ERROR 47 | * 48 | * This errorcode indicates 'no error detected'. 49 | */ 50 | /*-----------------------------------------------------------------------------------------------------*/ 51 | 52 | #define CANOS_NO_ERR (CPU_INT08U)0 53 | 54 | 55 | /* 56 | ********************************************************************************************************* 57 | * FUNCTION PROTOTYPES 58 | ********************************************************************************************************* 59 | */ 60 | 61 | CPU_INT16S CANOS_Init (void); 62 | 63 | CPU_INT08U CANOS_PendRxFrame(CPU_INT16U timeout, 64 | CPU_INT16S busId); 65 | 66 | void CANOS_PostRxFrame(CPU_INT16S busId); 67 | 68 | void CANOS_ResetRx (CPU_INT16S busId); 69 | 70 | CPU_INT08U CANOS_PendTxFrame(CPU_INT16U timeout, 71 | CPU_INT16S busId); 72 | 73 | void CANOS_PostTxFrame(CPU_INT16S busId); 74 | 75 | void CANOS_ResetTx (CPU_INT16S busId); 76 | 77 | CPU_INT32U CANOS_GetTime (void); 78 | 79 | #ifdef __cplusplus 80 | } 81 | #endif 82 | 83 | 84 | /* 85 | ********************************************************************************************************* 86 | * MODULE END 87 | ********************************************************************************************************* 88 | */ 89 | 90 | #endif /* #ifndef _CAN_OS_H */ 91 | -------------------------------------------------------------------------------- /OS/uCOS-II/can_os.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * Filename : can_os.h 22 | * Version : V2.42.01 23 | ********************************************************************************************************* 24 | */ 25 | 26 | #ifndef _CAN_OS_H_ 27 | #define _CAN_OS_H_ 28 | 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | 35 | /* 36 | ********************************************************************************************************* 37 | * INCLUDES 38 | ********************************************************************************************************* 39 | */ 40 | 41 | #include "can_frm.h" /* CAN Frame handling */ 42 | #include "can_cfg.h" /* CAN Configuration defines */ 43 | #include "ucos_ii.h" /* RTOS: uC/OS-II services */ 44 | 45 | 46 | /*-----------------------------------------------------------------------------------------------------*/ 47 | /*! \brief OS: NO ERROR 48 | * 49 | * This errorcode indicates 'no error detected'. 50 | */ 51 | /*-----------------------------------------------------------------------------------------------------*/ 52 | 53 | #define CANOS_NO_ERR (CPU_INT08U)0 54 | 55 | 56 | /* 57 | ********************************************************************************************************* 58 | * FUNCTION PROTOTYPES 59 | ********************************************************************************************************* 60 | */ 61 | 62 | CPU_INT16S CANOS_Init (void); 63 | 64 | CPU_INT08U CANOS_PendRxFrame(CPU_INT16U timeout, 65 | CPU_INT16S busId); 66 | 67 | void CANOS_PostRxFrame(CPU_INT16S busId); 68 | 69 | void CANOS_ResetRx (CPU_INT16S busId); 70 | 71 | CPU_INT08U CANOS_PendTxFrame(CPU_INT16U timeout, 72 | CPU_INT16S busId); 73 | 74 | void CANOS_PostTxFrame(CPU_INT16S busId); 75 | 76 | void CANOS_ResetTx (CPU_INT16S busId); 77 | 78 | CPU_INT32U CANOS_GetTime (void); 79 | 80 | 81 | #ifdef __cplusplus 82 | } 83 | #endif 84 | 85 | 86 | /* 87 | ********************************************************************************************************* 88 | * MODULE END 89 | ********************************************************************************************************* 90 | */ 91 | 92 | #endif /* #ifndef _CAN_OS_H */ 93 | -------------------------------------------------------------------------------- /OS/uCOS-III/can_os.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * Filename : can_os.h 22 | * Version : V2.42.01 23 | ********************************************************************************************************* 24 | */ 25 | 26 | #ifndef _CAN_OS_H_ 27 | #define _CAN_OS_H_ 28 | 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | 35 | /* 36 | ********************************************************************************************************* 37 | * INCLUDES 38 | ********************************************************************************************************* 39 | */ 40 | 41 | #include "can_frm.h" /* CAN Frame handling */ 42 | #include "can_cfg.h" /* CAN Configuration defines */ 43 | #include "os.h" /* RTOS: uC/OS-III services */ 44 | 45 | 46 | /*-----------------------------------------------------------------------------------------------------*/ 47 | /*! \brief OS: NO ERROR 48 | * 49 | * This errorcode indicates 'no error detected'. 50 | */ 51 | /*-----------------------------------------------------------------------------------------------------*/ 52 | 53 | #define CANOS_NO_ERR (CPU_INT08U)0 54 | 55 | 56 | /* 57 | ********************************************************************************************************* 58 | * FUNCTION PROTOTYPES 59 | ********************************************************************************************************* 60 | */ 61 | 62 | CPU_INT16S CANOS_Init (void); 63 | 64 | CPU_INT08U CANOS_PendRxFrame(CPU_INT16U timeout, 65 | CPU_INT16S busId); 66 | 67 | void CANOS_PostRxFrame(CPU_INT16S busId); 68 | 69 | void CANOS_ResetRx (CPU_INT16S busId); 70 | 71 | CPU_INT08U CANOS_PendTxFrame(CPU_INT16U timeout, 72 | CPU_INT16S busId); 73 | 74 | void CANOS_PostTxFrame(CPU_INT16S busId); 75 | 76 | void CANOS_ResetTx (CPU_INT16S busId); 77 | 78 | CPU_INT32U CANOS_GetTime (void); 79 | 80 | 81 | #ifdef __cplusplus 82 | } 83 | #endif 84 | 85 | 86 | /* 87 | ********************************************************************************************************* 88 | * MODULE END 89 | ********************************************************************************************************* 90 | */ 91 | 92 | #endif /* #ifndef _CAN_OS_H */ 93 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # uC/CAN 2 | 3 | The μC/OS CAN module reduces development efforts to embed CAN. Developers need only an understanding of signals, messages and bus configurations. Different abstraction layers can be used independently. 4 | 5 | The μC/OS CAN module can communicate via one or more CAN buses simultaneously. The bus management layer organizes the CAN buses and distributes messages to different device drivers. The device driver layer buffers the CAN messages to be sent and received. All hardware dependencies are capsulated in this layer. An embedded target can also have multiple, different CAN controllers. 6 | 7 | ## For the complete documentation, visit https://doc.micrium.com/display/candoc/ 8 | -------------------------------------------------------------------------------- /Source/can_drv.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * Filename : can_drv.h 22 | * Version : V2.42.01 23 | * Purpose : This include file defines the CAN low-level device driver interface. 24 | ********************************************************************************************************* 25 | */ 26 | 27 | #ifndef _CAN_DRV_H_ 28 | #define _CAN_DRV_H_ 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | 35 | /*-----------------------------------------------------------------------------------------------------*/ 36 | /*! \brief I/O CONTROL FUNCTIONCODES 37 | * 38 | * This enumeration defines the required functioncode values for the lowlevel 39 | * device driver function IoCtl(). 40 | */ 41 | /*-----------------------------------------------------------------------------------------------------*/ 42 | 43 | enum CANDRV_IOCTL_FUNC { 44 | /*! \brief Set Baudrate 45 | * 46 | * This enum value is the functioncode to set the baudrate of the CAN controller interface. 47 | * 48 | * The parameter pointer shall point to an CPU_INT32U variable, which holds the baudrate 49 | * in bit/s. 50 | */ 51 | CAN_SET_BAUDRATE = 0, 52 | /*! \brief Enable Bus 53 | * 54 | * This enum value is the functioncode to start the CAN controller interface. Most common 55 | * is to set the CAN controller in active mode. 56 | * 57 | * The parameter pointer is not used for this function. 58 | */ 59 | CAN_START, 60 | /*! \brief Disable Bus 61 | * 62 | * This enum value is the functioncode to stop the CAN controller interface. Most common 63 | * is to set the CAN controller in passive mode. 64 | * 65 | * The parameter pointer is not used for this function. 66 | */ 67 | CAN_STOP, 68 | /*! \brief Set Receiver to Standard Identifier 69 | * 70 | * This enum value is the functioncode to configure the CAN receiver to receive only 71 | * CAN standard identifiers. 72 | * 73 | * The parameter pointer is not used for this function. 74 | */ 75 | CAN_RX_STANDARD, 76 | /*! \brief Set Receiver to Extended Identifier 77 | * 78 | * This enum value is the functioncode to configure the CAN receiver to receive only 79 | * CAN extended identifiers. 80 | * 81 | * The parameter pointer is not used for this function. 82 | */ 83 | CAN_RX_EXTENDED, 84 | /*! \brief Get TX Buffer Status 85 | * 86 | * This enum value is the functioncode to get the status of the current transmit 87 | * buffer. 88 | * 89 | * The parameter pointer shall point to a CPU_INT08U variable, where the status 90 | * shall be written to. 91 | */ 92 | CAN_TX_READY, 93 | /*! \brief Get Node Status 94 | * 95 | * This enum value is the functioncode to get the node status from the 96 | * CAN controller. 97 | * 98 | * The parameter pointer shall point to a CPU_INT08U variable, where the status 99 | * shall be written to. 100 | */ 101 | CAN_GET_NODE_STATUS, 102 | 103 | /*! \brief Number of Needed IO Function Codes 104 | * 105 | * This enum value holds the number of function codes, which are used within the 106 | * can bus layer. 107 | */ 108 | CAN_IO_FUNC_N 109 | }; 110 | 111 | #ifdef __cplusplus 112 | } 113 | #endif 114 | 115 | 116 | /* 117 | ********************************************************************************************************* 118 | * MODULE END 119 | ********************************************************************************************************* 120 | */ 121 | 122 | #endif /* #ifndef _CAN_DRV_H_ */ 123 | -------------------------------------------------------------------------------- /Source/can_err.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * Filename : can_err.h 22 | * Version : V2.42.01 23 | * Purpose : This include file holds the error codes and error macro used in the uC/CAN layers. 24 | ********************************************************************************************************* 25 | */ 26 | 27 | #ifndef CAN_ERR__H 28 | #define CAN_ERR__H 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | 35 | /****************************************************************************/ 36 | /* uC/CAN global error variable (contains latest CAN error code */ 37 | /****************************************************************************/ 38 | 39 | extern volatile CPU_INT16S can_errnum; 40 | 41 | 42 | /****************************************************************************/ 43 | /* uC/CAN error codes */ 44 | /****************************************************************************/ 45 | 46 | #define CAN_ERR_NONE 0 47 | #define CAN_ERR_NULLPTR -1 48 | #define CAN_ERR_SIGMOD -4 49 | #define CAN_ERR_BUSID -10 50 | #define CAN_ERR_FRMSIZE -11 51 | #define CAN_ERR_OPEN -12 52 | #define CAN_ERR_ENABLE -14 53 | #define CAN_ERR_IOCTRLFUNC -15 54 | #define CAN_ERR_NULLMSG -17 55 | #define CAN_ERR_MSGID -18 56 | #define CAN_ERR_MSGUNUSED -19 57 | #define CAN_ERR_MSGCREATE -20 58 | #define CAN_ERR_SIGID -21 59 | #define CAN_ERR_NULLSIGCFG -22 60 | #define CAN_ERR_CANSIZE -23 61 | #define CAN_ERR_BUFFSIZE -24 62 | #define CAN_ERR_SIGCREATE -25 63 | #define CAN_ERR_FRMWIDTH -26 64 | #define CAN_ERR_BUSINIT -27 65 | #define CAN_ERR_OSINIT -240 66 | #define CAN_ERR_OSFREE -241 67 | #define CAN_ERR_OSQUEUE -242 68 | #define CAN_ERR_OSALLOC -244 69 | #define CAN_ERR_OSSEM -245 70 | #define CAN_ERR_OSQPEND -246 71 | #define CAN_ERR_NOFRM -247 72 | #define CAN_ERR_OSSEMPEND -248 73 | #define CAN_ERR_OSSEMPOST -248 74 | #define CAN_ERR_OSQACCEPT -249 75 | #define CAN_ERR_UNKNOWN -255 76 | 77 | 78 | /****************************************************************************/ 79 | /* uC/CAN macros */ 80 | /****************************************************************************/ 81 | /*lint emacro( {717}, CANSetErrRegister ) */ 82 | 83 | #define CANSetErrRegister(errorcode) do { if (errorcode < CAN_ERR_NONE) {can_errnum = errorcode;} } while (0) 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | 90 | /* 91 | ********************************************************************************************************* 92 | * MODULE END 93 | ********************************************************************************************************* 94 | */ 95 | 96 | #endif /* CAN_ERR__H */ 97 | -------------------------------------------------------------------------------- /Source/can_frm.h: -------------------------------------------------------------------------------- 1 | /* 2 | ********************************************************************************************************* 3 | * uC/CAN 4 | * The Embedded CAN suite 5 | * 6 | * Copyright by Embedded Office GmbH & Co. KG www.embedded-office.com 7 | * Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com 8 | * 9 | * SPDX-License-Identifier: APACHE-2.0 10 | * 11 | * This software is subject to an open source license and is distributed by 12 | * Silicon Laboratories Inc. pursuant to the terms of the Apache License, 13 | * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0. 14 | * 15 | ********************************************************************************************************* 16 | */ 17 | 18 | 19 | /* 20 | ********************************************************************************************************* 21 | * Filename : can_frm.h 22 | * Version : V2.42.01 23 | * Purpose : This include file defines the symbolic constants and function prototypes for 24 | * the CAN frame handling. 25 | ********************************************************************************************************* 26 | */ 27 | 28 | #ifndef _CAN_FRM_H_ 29 | #define _CAN_FRM_H_ 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | 36 | /* 37 | ********************************************************************************************************* 38 | * INCLUDES 39 | ********************************************************************************************************* 40 | */ 41 | 42 | #include "cpu.h" /* CPU configuration */ 43 | 44 | 45 | /* 46 | ********************************************************************************************************* 47 | * DEFINES 48 | ********************************************************************************************************* 49 | */ 50 | 51 | /*-----------------------------------------------------------------------------------------------------*/ 52 | /*! 53 | * \brief CODING: BIT MASK 54 | * 55 | * The position byte is encoded in the following way: 56 | * - Bit 0..5: BYte position of first byte in payload 57 | * - Bit 6..7: Encoding of bytes (0=big endian, 1=little endian) 58 | */ 59 | /*-----------------------------------------------------------------------------------------------------*/ 60 | 61 | #define CANFRM_CODING_MSK 0xC0u 62 | 63 | 64 | /*-----------------------------------------------------------------------------------------------------*/ 65 | /*! 66 | * \brief CODING: BIG ENDIAN 67 | * 68 | * Encoding of bytes in big endian format. 69 | */ 70 | /*-----------------------------------------------------------------------------------------------------*/ 71 | 72 | #define CANFRM_BIG_ENDIAN 0x00u 73 | 74 | 75 | /*-----------------------------------------------------------------------------------------------------*/ 76 | /*! 77 | * \brief CODING: LITTLE ENDIAN 78 | * 79 | * Encoding of bytes in little endian format. 80 | */ 81 | /*-----------------------------------------------------------------------------------------------------*/ 82 | 83 | #define CANFRM_LITTLE_ENDIAN 0x40u 84 | 85 | 86 | /* 87 | ********************************************************************************************************* 88 | * DATA TYPES 89 | ********************************************************************************************************* 90 | */ 91 | 92 | /*-----------------------------------------------------------------------------------------------------*/ 93 | /*! 94 | * \brief CAN FRAME 95 | * 96 | * This structure contains all needed data to handle a single CAN frame 97 | */ 98 | /*-----------------------------------------------------------------------------------------------------*/ 99 | 100 | typedef struct { 101 | /*-------------------------------------------------------------------------------------------------*/ 102 | /*! 103 | * \brief CAN IDENTIFIER 104 | * 105 | * This member holds the CAN identifier. 106 | * 107 | * \note To differentiate standard and extended identifiers the following addition to the 108 | * identifier is implemented: 109 | * - bit31: reserved (always 0) 110 | * - bit30: marks a remote transmission request (1=rtr, 0=data frame) 111 | * - bit29: marks an extended identifier (1=extended, 0=standard) 112 | * - bit28-0: the identifier (standard or extended) 113 | */ 114 | /*-------------------------------------------------------------------------------------------------*/ 115 | CPU_INT32U Identifier; 116 | /*-------------------------------------------------------------------------------------------------*/ 117 | /*! 118 | * \brief CAN PAYLOAD 119 | * 120 | * This member holds up to 8 bytes, which can be handled with a single CAN message. 121 | */ 122 | /*-------------------------------------------------------------------------------------------------*/ 123 | CPU_INT08U Data[8]; 124 | /*-------------------------------------------------------------------------------------------------*/ 125 | /*! 126 | * \brief CAN DLC 127 | * 128 | * This member holds the number of valid datas in the payload. 129 | */ 130 | /*-------------------------------------------------------------------------------------------------*/ 131 | CPU_INT08U DLC; 132 | /*-------------------------------------------------------------------------------------------------*/ 133 | /*! 134 | * \brief SPARE 135 | * 136 | * These bytes are added to get a frame size of an integral number of pointers. 137 | */ 138 | /*-------------------------------------------------------------------------------------------------*/ 139 | CPU_INT08U Spare[3]; 140 | 141 | } CANFRM; 142 | 143 | 144 | /* 145 | ********************************************************************************************************* 146 | * FUNCTION PROTOTYPES 147 | ********************************************************************************************************* 148 | */ 149 | 150 | void CanFrmSet(CANFRM *frm, CPU_INT32U value, CPU_INT08U width, CPU_INT08U pos); 151 | CPU_INT32U CanFrmGet(CANFRM *frm, CPU_INT08U width, CPU_INT08U pos); 152 | 153 | #ifdef __cplusplus 154 | } 155 | #endif 156 | 157 | 158 | /* 159 | ********************************************************************************************************* 160 | * MODULE END 161 | ********************************************************************************************************* 162 | */ 163 | 164 | #endif /* #ifndef _CAN_FRM_H_ */ 165 | -------------------------------------------------------------------------------- /license.txt: -------------------------------------------------------------------------------- 1 | ATTENTION ALL USERS OF THIS REPOSITORY: 2 | 3 | The original work found in this repository is provided by Silicon Labs under the 4 | Apache License, Version 2.0. 5 | 6 | Any third party may contribute derivative works to the original work in which 7 | modifications are clearly identified as being licensed under: 8 | 9 | (1) the Apache License, Version 2.0 or a compatible open source license; or 10 | (2) under a proprietary license with a copy of such license deposited. 11 | 12 | All posted derivative works must clearly identify which license choice has been 13 | elected. 14 | 15 | No such posted derivative works will be considered to be a “Contribution” under 16 | the Apache License, Version 2.0. 17 | 18 | SILICON LABS MAKES NO WARRANTY WITH RESPECT TO ALL POSTED THIRD PARTY CONTENT 19 | AND DISCLAIMS ALL OTHER WARRANTIES OR LIABILITIES, INCLUDING ALL WARRANTIES OF 20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, OWNERSHIP, 21 | NON-INFRINGEMENT, AND NON-MISAPPROPRIATION. 22 | 23 | In the event a derivative work is desired to be submitted to Silicon Labs as a 24 | “Contribution” under the Apache License, Version 2.0, a “Contributor” must give 25 | written email notice to micrium@weston-embedded.com. Unless an email response in 26 | the affirmative to accept the derivative work as a “Contribution”, such email 27 | submission should be considered to have not been incorporated into the original 28 | work. 29 | 30 | --------------------------------------------------------------------------------