├── .project
├── LICENSE.txt
├── Mojo-Base.xise
├── ipcore_dir
    └── .gitignore
├── iseconfig
    ├── Mojo-Base.projectmgr
    └── mojo_top.xreport
├── src
    ├── avr_interface.v
    ├── cclk_detector.v
    ├── mojo.ucf
    ├── mojo_top.v
    ├── serial_rx.v
    ├── serial_tx.v
    └── spi_slave.v
└── syn
    └── .gitignore


/.project:
--------------------------------------------------------------------------------
 1 | <?xml version="1.0" encoding="UTF-8"?>
 2 | <projectDescription>
 3 | 	<name>Mojo-Demo</name>
 4 | 	<comment></comment>
 5 | 	<projects>
 6 | 	</projects>
 7 | 	<buildSpec>
 8 | 		<buildCommand>
 9 | 			<name>net.sourceforge.veditor.simulateBuilder</name>
10 | 			<arguments>
11 | 				<dictionary>
12 | 					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.CleanCommand</key>
13 | 					<value>echo &apos;Clean&apos;</value>
14 | 				</dictionary>
15 | 				<dictionary>
16 | 					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.buildOrder</key>
17 | 					<value>0</value>
18 | 				</dictionary>
19 | 				<dictionary>
20 | 					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.command</key>
21 | 					<value>echo &apos;No Build Configuration Specified&apos;</value>
22 | 				</dictionary>
23 | 				<dictionary>
24 | 					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.enable</key>
25 | 					<value>false</value>
26 | 				</dictionary>
27 | 				<dictionary>
28 | 					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.name</key>
29 | 					<value>Default</value>
30 | 				</dictionary>
31 | 				<dictionary>
32 | 					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.parser</key>
33 | 					<value></value>
34 | 				</dictionary>
35 | 				<dictionary>
36 | 					<key>net.sourceforge.veditor.simulateBuilder.00000000Default.workFolder</key>
37 | 					<value></value>
38 | 				</dictionary>
39 | 			</arguments>
40 | 		</buildCommand>
41 | 	</buildSpec>
42 | 	<natures>
43 | 		<nature>net.sourceforge.veditor.HdlNature</nature>
44 | 	</natures>
45 | </projectDescription>
46 | 


--------------------------------------------------------------------------------
/LICENSE.txt:
--------------------------------------------------------------------------------
 1 | The MIT License (MIT)
 2 | 
 3 | Copyright (c) 2015 Embedded Micro
 4 | 
 5 | Permission is hereby granted, free of charge, to any person obtaining a copy
 6 | of this software and associated documentation files (the "Software"), to deal
 7 | in the Software without restriction, including without limitation the rights
 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 9 | copies of the Software, and to permit persons to whom the Software is
10 | furnished to do so, subject to the following conditions:
11 | 
12 | The above copyright notice and this permission notice shall be included in
13 | all copies or substantial portions of the Software.
14 | 
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 | THE SOFTWARE.
22 | 


--------------------------------------------------------------------------------
/Mojo-Base.xise:
--------------------------------------------------------------------------------
  1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
  2 | <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
  3 | 
  4 |   <header>
  5 |     <!-- ISE source project file created by Project Navigator.             -->
  6 |     <!--                                                                   -->
  7 |     <!-- This file contains project source information including a list of -->
  8 |     <!-- project source files, project and process properties.  This file, -->
  9 |     <!-- along with the project source files, is sufficient to open and    -->
 10 |     <!-- implement in ISE Project Navigator.                               -->
 11 |     <!--                                                                   -->
 12 |     <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 13 |   </header>
 14 | 
 15 |   <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 16 | 
 17 |   <files>
 18 |     <file xil_pn:name="src/mojo.ucf" xil_pn:type="FILE_UCF">
 19 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 20 |     </file>
 21 |     <file xil_pn:name="src/mojo_top.v" xil_pn:type="FILE_VERILOG">
 22 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
 23 |       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
 24 |     </file>
 25 |     <file xil_pn:name="src/cclk_detector.v" xil_pn:type="FILE_VERILOG">
 26 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
 27 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 28 |     </file>
 29 |     <file xil_pn:name="src/avr_interface.v" xil_pn:type="FILE_VERILOG">
 30 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
 31 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 32 |     </file>
 33 |     <file xil_pn:name="src/spi_slave.v" xil_pn:type="FILE_VERILOG">
 34 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
 35 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 36 |     </file>
 37 |     <file xil_pn:name="src/serial_rx.v" xil_pn:type="FILE_VERILOG">
 38 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
 39 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 40 |     </file>
 41 |     <file xil_pn:name="src/serial_tx.v" xil_pn:type="FILE_VERILOG">
 42 |       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
 43 |       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
 44 |     </file>
 45 |   </files>
 46 | 
 47 |   <properties>
 48 |     <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
 49 |     <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
 50 |     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
 51 |     <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
 52 |     <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
 53 |     <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
 54 |     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
 55 |     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
 56 |     <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
 57 |     <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
 58 |     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
 59 |     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
 60 |     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
 61 |     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
 62 |     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
 63 |     <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
 64 |     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
 65 |     <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
 66 |     <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
 67 |     <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
 68 |     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
 69 |     <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
 70 |     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
 71 |     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
 72 |     <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
 73 |     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
 74 |     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
 75 |     <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
 76 |     <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
 77 |     <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
 78 |     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
 79 |     <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
 80 |     <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
 81 |     <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
 82 |     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
 83 |     <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
 84 |     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
 85 |     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
 86 |     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
 87 |     <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
 88 |     <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
 89 |     <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
 90 |     <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
 91 |     <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
 92 |     <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
 93 |     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
 94 |     <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
 95 |     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
 96 |     <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
 97 |     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
 98 |     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
 99 |     <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
100 |     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
101 |     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
102 |     <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
103 |     <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
104 |     <property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
105 |     <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
106 |     <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
107 |     <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
108 |     <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
109 |     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
110 |     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
111 |     <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
112 |     <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
113 |     <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
114 |     <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
115 |     <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
116 |     <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
117 |     <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
118 |     <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
119 |     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
120 |     <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
121 |     <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
122 |     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
123 |     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
124 |     <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
125 |     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
126 |     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
127 |     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
128 |     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
129 |     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
130 |     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
131 |     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
132 |     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
133 |     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
134 |     <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
135 |     <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
136 |     <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
137 |     <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
138 |     <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
139 |     <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
140 |     <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
141 |     <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
142 |     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
143 |     <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
144 |     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
145 |     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
146 |     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
147 |     <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
148 |     <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
149 |     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
150 |     <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
151 |     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
152 |     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
153 |     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
154 |     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
155 |     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
156 |     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
157 |     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
158 |     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
159 |     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
160 |     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
161 |     <property xil_pn:name="Implementation Top" xil_pn:value="Module|mojo_top" xil_pn:valueState="non-default"/>
162 |     <property xil_pn:name="Implementation Top File" xil_pn:value="../src/mojo_top.v" xil_pn:valueState="non-default"/>
163 |     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mojo_top" xil_pn:valueState="non-default"/>
164 |     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
165 |     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
166 |     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
167 |     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
168 |     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
169 |     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
170 |     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
171 |     <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
172 |     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
173 |     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
174 |     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
175 |     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
176 |     <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
177 |     <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
178 |     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
179 |     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
180 |     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
181 |     <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
182 |     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
183 |     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
184 |     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
185 |     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
186 |     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
187 |     <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
188 |     <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
189 |     <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
190 |     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
191 |     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
192 |     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
193 |     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
194 |     <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
195 |     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
196 |     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
197 |     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
198 |     <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
199 |     <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
200 |     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
201 |     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
202 |     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
203 |     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
204 |     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
205 |     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
206 |     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
207 |     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
208 |     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
209 |     <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
210 |     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
211 |     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
212 |     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
213 |     <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
214 |     <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
215 |     <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
216 |     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
217 |     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
218 |     <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
219 |     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
220 |     <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
221 |     <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
222 |     <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
223 |     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
224 |     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
225 |     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
226 |     <property xil_pn:name="Output File Name" xil_pn:value="pwm_top" xil_pn:valueState="non-default"/>
227 |     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
228 |     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
229 |     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
230 |     <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
231 |     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
232 |     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
233 |     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
234 |     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
235 |     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
236 |     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
237 |     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
238 |     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
239 |     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
240 |     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pwm_top_map.v" xil_pn:valueState="non-default"/>
241 |     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="pwm_top_timesim.v" xil_pn:valueState="non-default"/>
242 |     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pwm_top_synthesis.v" xil_pn:valueState="non-default"/>
243 |     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pwm_top_translate.v" xil_pn:valueState="non-default"/>
244 |     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
245 |     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
246 |     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
247 |     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
248 |     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
249 |     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
250 |     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
251 |     <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
252 |     <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
253 |     <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
254 |     <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
255 |     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
256 |     <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
257 |     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
258 |     <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
259 |     <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
260 |     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
261 |     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
262 |     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
263 |     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
264 |     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
265 |     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
266 |     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
267 |     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
268 |     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
269 |     <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
270 |     <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
271 |     <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
272 |     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
273 |     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
274 |     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
275 |     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
276 |     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
277 |     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
278 |     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
279 |     <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
280 |     <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
281 |     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
282 |     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
283 |     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
284 |     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
285 |     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
286 |     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
287 |     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
288 |     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mojo_top/spi" xil_pn:valueState="non-default"/>
289 |     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spi" xil_pn:valueState="non-default"/>
290 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
291 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
292 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
293 |     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
294 |     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
295 |     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
296 |     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
297 |     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
298 |     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
299 |     <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
300 |     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
301 |     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
302 |     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
303 |     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
304 |     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
305 |     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
306 |     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
307 |     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spi" xil_pn:valueState="default"/>
308 |     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
309 |     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
310 |     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
311 |     <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
312 |     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
313 |     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
314 |     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
315 |     <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
316 |     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
317 |     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
318 |     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
319 |     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
320 |     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
321 |     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
322 |     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
323 |     <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
324 |     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
325 |     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
326 |     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
327 |     <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
328 |     <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
329 |     <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
330 |     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
331 |     <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
332 |     <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
333 |     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
334 |     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
335 |     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
336 |     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
337 |     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
338 |     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
339 |     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
340 |     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
341 |     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
342 |     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
343 |     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
344 |     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
345 |     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
346 |     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
347 |     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
348 |     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
349 |     <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
350 |     <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
351 |     <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
352 |     <property xil_pn:name="Working Directory" xil_pn:value="syn" xil_pn:valueState="non-default"/>
353 |     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
354 |     <!--                                                                                  -->
355 |     <!-- The following properties are for internal use only. These should not be modified.-->
356 |     <!--                                                                                  -->
357 |     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|spi_tb" xil_pn:valueState="non-default"/>
358 |     <property xil_pn:name="PROP_DesignName" xil_pn:value="PWM-Demo" xil_pn:valueState="non-default"/>
359 |     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
360 |     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
361 |     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
362 |     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
363 |     <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
364 |     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
365 |     <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
366 |     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-06T11:19:28" xil_pn:valueState="non-default"/>
367 |     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F04BE7BB4526104AA483BCD2B63930B5" xil_pn:valueState="non-default"/>
368 |     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
369 |     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
370 |   </properties>
371 | 
372 |   <bindings>
373 |     <binding xil_pn:location="/mojo_top" xil_pn:name="src/mojo.ucf"/>
374 |   </bindings>
375 | 
376 |   <libraries/>
377 | 
378 |   <autoManagedFiles>
379 |     <!-- The following files are identified by `include statements in verilog -->
380 |     <!-- source files and are automatically managed by Project Navigator.     -->
381 |     <!--                                                                      -->
382 |     <!-- Do not hand-edit this section, as it will be overwritten when the    -->
383 |     <!-- project is analyzed based on files automatically identified as       -->
384 |     <!-- include files.                                                       -->
385 |   </autoManagedFiles>
386 | 
387 | </project>
388 | 


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/ipcore_dir/.gitignore:
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https://raw.githubusercontent.com/embmicro/mojo-base-project/469b6ee60b143c5f4fca25f63be0f18cee15e5c1/ipcore_dir/.gitignore


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/iseconfig/Mojo-Base.projectmgr:
--------------------------------------------------------------------------------
 1 | <?xml version='1.0' encoding='utf-8'?>
 2 | <!--This is an ISE project configuration file.-->
 3 | <!--It holds project specific layout data for the projectmgr plugin.-->
 4 | <!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
 5 | <Project version="2" owner="projectmgr" name="Mojo-Base" >
 6 |    <!--This is an ISE project configuration file.-->
 7 |    <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
 8 |       <ClosedNodes>
 9 |          <ClosedNodesVersion>2</ClosedNodesVersion>
10 |          <ClosedNode>/avr_interface |home|justin|workspace|Mojo-Tutorials|Mojo-Base|src|avr_interface.v</ClosedNode>
11 |       </ClosedNodes>
12 |       <SelectedItems>
13 |          <SelectedItem>mojo_top (/home/justin/workspace/Mojo-Tutorials/Mojo-Base/src/mojo_top.v)</SelectedItem>
14 |       </SelectedItems>
15 |       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
16 |       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
17 |       <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010a0000000100000003000000000000000100000003</ViewHeaderState>
18 |       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
19 |       <CurrentItem>mojo_top (/home/justin/workspace/Mojo-Tutorials/Mojo-Base/src/mojo_top.v)</CurrentItem>
20 |    </ItemView>
21 |    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
22 |       <ClosedNodes>
23 |          <ClosedNodesVersion>1</ClosedNodesVersion>
24 |          <ClosedNode>Configure Target Device</ClosedNode>
25 |          <ClosedNode>Design Utilities</ClosedNode>
26 |          <ClosedNode>Implement Design/Map</ClosedNode>
27 |          <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
28 |          <ClosedNode>Implement Design/Translate</ClosedNode>
29 |          <ClosedNode>Synthesize - XST</ClosedNode>
30 |          <ClosedNode>User Constraints</ClosedNode>
31 |       </ClosedNodes>
32 |       <SelectedItems>
33 |          <SelectedItem>Generate Programming File</SelectedItem>
34 |       </SelectedItems>
35 |       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
36 |       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
37 |       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000</ViewHeaderState>
38 |       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
39 |       <CurrentItem>Generate Programming File</CurrentItem>
40 |    </ItemView>
41 |    <ItemView guiview="File" >
42 |       <ClosedNodes>
43 |          <ClosedNodesVersion>1</ClosedNodesVersion>
44 |       </ClosedNodes>
45 |       <SelectedItems/>
46 |       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
47 |       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
48 |       <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000005a7000000040101000100000000000000000000000064ffffffff000000810000000000000004000000770000000100000000000000c50000000100000000000000790000000100000000000003f20000000100000000</ViewHeaderState>
49 |       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
50 |       <CurrentItem>avr_interface.v</CurrentItem>
51 |    </ItemView>
52 |    <ItemView guiview="Library" >
53 |       <ClosedNodes>
54 |          <ClosedNodesVersion>1</ClosedNodesVersion>
55 |          <ClosedNode>work</ClosedNode>
56 |       </ClosedNodes>
57 |       <SelectedItems/>
58 |       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
59 |       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
60 |       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000</ViewHeaderState>
61 |       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
62 |       <CurrentItem>work</CurrentItem>
63 |    </ItemView>
64 |    <SourceProcessView>000000ff0000000000000002000001380000011b01000000040100000002</SourceProcessView>
65 |    <CurrentView>Implementation</CurrentView>
66 |    <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
67 |       <ClosedNodes>
68 |          <ClosedNodesVersion>1</ClosedNodesVersion>
69 |          <ClosedNode>Design Utilities</ClosedNode>
70 |       </ClosedNodes>
71 |       <SelectedItems>
72 |          <SelectedItem/>
73 |       </SelectedItems>
74 |       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
75 |       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
76 |       <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
77 |       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
78 |       <CurrentItem/>
79 |    </ItemView>
80 |    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
81 |       <ClosedNodes>
82 |          <ClosedNodesVersion>1</ClosedNodesVersion>
83 |          <ClosedNode>User Constraints</ClosedNode>
84 |       </ClosedNodes>
85 |       <SelectedItems>
86 |          <SelectedItem/>
87 |       </SelectedItems>
88 |       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
89 |       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
90 |       <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
91 |       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
92 |       <CurrentItem/>
93 |    </ItemView>
94 | </Project>
95 | 


--------------------------------------------------------------------------------
/iseconfig/mojo_top.xreport:
--------------------------------------------------------------------------------
  1 | <?xml version='1.0' encoding='UTF-8'?>
  2 | <report-views version="2.0" >
  3 |  <header>
  4 |   <DateModified>2014-02-20T09:25:01</DateModified>
  5 |   <ModuleName>mojo_top</ModuleName>
  6 |   <SummaryTimeStamp>2013-04-16T10:54:27</SummaryTimeStamp>
  7 |   <SavedFilePath>/home/justin/workspace/Mojo-Tutorials/Mojo-Base/iseconfig/mojo_top.xreport</SavedFilePath>
  8 |   <ImplementationReportsDirectory>/home/justin/workspace/Mojo-Tutorials/Mojo-Base/syn/</ImplementationReportsDirectory>
  9 |   <DateInitialized>2012-11-08T12:38:20</DateInitialized>
 10 |   <EnableMessageFiltering>false</EnableMessageFiltering>
 11 |  </header>
 12 |  <body>
 13 |   <viewgroup label="Design Overview" >
 14 |    <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="mojo_top_summary.html" label="Summary" >
 15 |     <toc-item title="Design Overview" target="Design Overview" />
 16 |     <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
 17 |     <toc-item title="Performance Summary" target="Performance Summary" />
 18 |     <toc-item title="Failing Constraints" target="Failing Constraints" />
 19 |     <toc-item title="Detailed Reports" target="Detailed Reports" />
 20 |    </view>
 21 |    <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="mojo_top_envsettings.html" label="System Settings" />
 22 |    <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="mojo_top_map.xrpt" label="IOB Properties" />
 23 |    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="mojo_top_map.xrpt" label="Control Set Information" />
 24 |    <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="mojo_top_map.xrpt" label="Module Level Utilization" />
 25 |    <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="mojo_top.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
 26 |    <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="mojo_top_par.xrpt" label="Pinout Report" />
 27 |    <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="mojo_top_par.xrpt" label="Clock Report" />
 28 |    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="mojo_top.twx" label="Static Timing" />
 29 |    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="mojo_top_html/fit/report.htm" label="CPLD Fitter Report" />
 30 |    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="mojo_top_html/tim/report.htm" label="CPLD Timing Report" />
 31 |   </viewgroup>
 32 |   <viewgroup label="XPS Errors and Warnings" >
 33 |    <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
 34 |    <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
 35 |    <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
 36 |   </viewgroup>
 37 |   <viewgroup label="XPS Reports" >
 38 |    <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
 39 |    <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
 40 |    <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
 41 |    <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="mojo_top.log" label="System Log File" />
 42 |   </viewgroup>
 43 |   <viewgroup label="Errors and Warnings" >
 44 |    <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
 45 |    <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
 46 |    <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
 47 |    <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
 48 |    <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
 49 |    <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
 50 |    <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
 51 |    <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
 52 |    <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
 53 |    <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
 54 |    <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
 55 |   </viewgroup>
 56 |   <viewgroup label="Detailed Reports" >
 57 |    <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="mojo_top.syr" label="Synthesis Report" >
 58 |     <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
 59 |     <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
 60 |     <toc-item title="HDL Compilation" target="   HDL Compilation   " />
 61 |     <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
 62 |     <toc-item title="HDL Analysis" target="   HDL Analysis   " />
 63 |     <toc-item title="HDL Parsing" target="   HDL Parsing   " />
 64 |     <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
 65 |     <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
 66 |     <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
 67 |     <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
 68 |     <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
 69 |     <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
 70 |     <toc-item title="Partition Report" target="   Partition Report     " />
 71 |     <toc-item title="Final Report" target="   Final Report   " />
 72 |     <toc-item title="Design Summary" target="   Design Summary   " />
 73 |     <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
 74 |     <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
 75 |     <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
 76 |     <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
 77 |     <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
 78 |     <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
 79 |     <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
 80 |     <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
 81 |     <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
 82 |    </view>
 83 |    <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="mojo_top.srr" label="Synplify Report" />
 84 |    <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="mojo_top.prec_log" label="Precision Report" />
 85 |    <view inputState="Synthesized" program="ngdbuild" type="Report" file="mojo_top.bld" label="Translation Report" >
 86 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
 87 |     <toc-item title="Command Line" target="Command Line:" />
 88 |     <toc-item title="Partition Status" target="Partition Implementation Status" />
 89 |     <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
 90 |    </view>
 91 |    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="mojo_top_map.mrp" label="Map Report" >
 92 |     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
 93 |     <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
 94 |     <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
 95 |     <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
 96 |     <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
 97 |     <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
 98 |     <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
 99 |     <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
100 |     <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
101 |     <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
102 |     <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
103 |     <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
104 |     <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
105 |     <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
106 |    </view>
107 |    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="mojo_top.par" label="Place and Route Report" >
108 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
109 |     <toc-item title="Device Utilization" target="Device Utilization Summary:" />
110 |     <toc-item title="Router Information" target="Starting Router" />
111 |     <toc-item title="Partition Status" target="Partition Implementation Status" />
112 |     <toc-item title="Clock Report" target="Generating Clock Report" />
113 |     <toc-item title="Timing Results" target="Timing Score:" />
114 |     <toc-item title="Final Summary" target="Peak Memory Usage:" />
115 |    </view>
116 |    <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="mojo_top.twr" label="Post-PAR Static Timing Report" >
117 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
118 |     <toc-item title="Timing Report Description" target="Device,package,speed:" />
119 |     <toc-item title="Informational Messages" target="INFO:" />
120 |     <toc-item title="Warning Messages" target="WARNING:" />
121 |     <toc-item title="Timing Constraints" target="Timing constraint:" />
122 |     <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
123 |     <toc-item title="Data Sheet Report" target="Data Sheet report:" />
124 |     <toc-item title="Timing Summary" target="Timing summary:" />
125 |     <toc-item title="Trace Settings" target="Trace Settings:" />
126 |    </view>
127 |    <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="mojo_top.rpt" label="CPLD Fitter Report (Text)" >
128 |     <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
129 |     <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
130 |     <toc-item title="Pin Resources" target="** Pin Resources **" />
131 |     <toc-item title="Global Resources" target="** Global Control Resources **" />
132 |    </view>
133 |    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="mojo_top.tim" label="CPLD Timing Report (Text)" >
134 |     <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
135 |     <toc-item title="Performance Summary" target="Performance Summary:" />
136 |    </view>
137 |    <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="mojo_top.pwr" label="Power Report" >
138 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
139 |     <toc-item title="Power summary" target="Power summary" />
140 |     <toc-item title="Thermal summary" target="Thermal summary" />
141 |    </view>
142 |    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="mojo_top.bgn" label="Bitgen Report" >
143 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
144 |     <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
145 |     <toc-item title="Final Summary" target="DRC detected" />
146 |    </view>
147 |   </viewgroup>
148 |   <viewgroup label="Secondary Reports" >
149 |    <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
150 |    <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/mojo_top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
151 |     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
152 |    </view>
153 |    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/mojo_top_translate.nlf" label="Post-Translate Simulation Model Report" >
154 |     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
155 |    </view>
156 |    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="mojo_top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
157 |    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="mojo_top_map.map" label="Map Log File" >
158 |     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
159 |     <toc-item title="Design Information" target="Design Information" />
160 |     <toc-item title="Design Summary" target="Design Summary" />
161 |    </view>
162 |    <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
163 |    <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top_preroute.twr" label="Post-Map Static Timing Report" >
164 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
165 |     <toc-item title="Timing Report Description" target="Device,package,speed:" />
166 |     <toc-item title="Informational Messages" target="INFO:" />
167 |     <toc-item title="Warning Messages" target="WARNING:" />
168 |     <toc-item title="Timing Constraints" target="Timing constraint:" />
169 |     <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
170 |     <toc-item title="Data Sheet Report" target="Data Sheet report:" />
171 |     <toc-item title="Timing Summary" target="Timing summary:" />
172 |     <toc-item title="Trace Settings" target="Trace Settings:" />
173 |    </view>
174 |    <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/mojo_top_map.nlf" label="Post-Map Simulation Model Report" />
175 |    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top_map.psr" label="Physical Synthesis Report" >
176 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
177 |    </view>
178 |    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="mojo_top_pad.txt" label="Pad Report" >
179 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
180 |    </view>
181 |    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="mojo_top.unroutes" label="Unroutes Report" >
182 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
183 |    </view>
184 |    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
185 |     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
186 |    </view>
187 |    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.grf" label="Guide Results Report" />
188 |    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.dly" label="Asynchronous Delay Report" />
189 |    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.clk_rgn" label="Clock Region Report" />
190 |    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.tsi" label="Post-Place and Route Constraints Interaction Report" >
191 |     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
192 |    </view>
193 |    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="mojo_top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
194 |    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/mojo_top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
195 |    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="mojo_top_sta.nlf" label="Primetime Netlist Report" >
196 |     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
197 |    </view>
198 |    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="mojo_top.ibs" label="IBIS Model" >
199 |     <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
200 |     <toc-item title="Component" target="Component " />
201 |    </view>
202 |    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.lck" label="Back-annotate Pin Report" >
203 |     <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
204 |     <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
205 |    </view>
206 |    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="mojo_top.lpc" label="Locked Pin Constraints" >
207 |     <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
208 |     <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
209 |    </view>
210 |    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/mojo_top_timesim.nlf" label="Post-Fit Simulation Model Report" />
211 |    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
212 |    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
213 |   </viewgroup>
214 |  </body>
215 | </report-views>
216 | 


--------------------------------------------------------------------------------
/src/avr_interface.v:
--------------------------------------------------------------------------------
  1 | module avr_interface #(
  2 |     parameter CLK_RATE = 50000000,
  3 |     parameter SERIAL_BAUD_RATE = 500000
  4 |   )(
  5 |     input clk,
  6 |     input rst,
  7 |     
  8 |     // cclk, or configuration clock is used when the FPGA is begin configured.
  9 |     // The AVR will hold cclk high when it has finished initializing.
 10 |     // It is important not to drive the lines connecting to the AVR
 11 |     // until cclk is high for a short period of time to avoid contention.
 12 |     input cclk,
 13 |     
 14 |     // AVR SPI Signals
 15 |     output spi_miso,
 16 |     input spi_mosi,
 17 |     input spi_sck,
 18 |     input spi_ss,
 19 |     output [3:0] spi_channel,
 20 |     
 21 |     // AVR Serial Signals
 22 |     output tx,
 23 |     input rx,
 24 |     
 25 |     // ADC Interface Signals
 26 |     input [3:0] channel,
 27 |     output new_sample,
 28 |     output [9:0] sample,
 29 |     output [3:0] sample_channel,
 30 |     
 31 |     // Serial TX User Interface
 32 |     input [7:0] tx_data,
 33 |     input new_tx_data,
 34 |     output tx_busy,
 35 |     input tx_block,
 36 |     
 37 |     // Serial Rx User Interface
 38 |     output [7:0] rx_data,
 39 |     output new_rx_data
 40 |   );
 41 |   
 42 |   wire ready;
 43 |   wire n_rdy = !ready;
 44 |   wire spi_done;
 45 |   wire [7:0] spi_dout;
 46 |   
 47 |   wire tx_m;
 48 |   wire spi_miso_m;
 49 |   
 50 |   reg byte_ct_d, byte_ct_q;
 51 |   reg [9:0] sample_d, sample_q;
 52 |   reg new_sample_d, new_sample_q;
 53 |   reg [3:0] sample_channel_d, sample_channel_q;
 54 |   reg [3:0] block_d, block_q;
 55 |   reg busy_d, busy_q;
 56 |   
 57 |   // cclk_detector is used to detect when cclk is high signaling when
 58 |   // the AVR is ready
 59 |   cclk_detector #(.CLK_RATE(CLK_RATE)) cclk_detector (
 60 |     .clk(clk),
 61 |     .rst(rst),
 62 |     .cclk(cclk),
 63 |     .ready(ready)
 64 |   );
 65 |   
 66 |   spi_slave spi_slave (
 67 |     .clk(clk),
 68 |     .rst(n_rdy),
 69 |     .ss(spi_ss),
 70 |     .mosi(spi_mosi),
 71 |     .miso(spi_miso_m),
 72 |     .sck(spi_sck),
 73 |     .done(spi_done),
 74 |     .din(8'hff),
 75 |     .dout(spi_dout)
 76 |   );
 77 |   
 78 |   // CLK_PER_BIT is the number of cycles each 'bit' lasts for
 79 |   // rtoi converts a 'real' number to an 'integer'
 80 |   parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
 81 |   
 82 |   serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
 83 |     .clk(clk),
 84 |     .rst(n_rdy),
 85 |     .rx(rx),
 86 |     .data(rx_data),
 87 |     .new_data(new_rx_data)
 88 |   );
 89 |   
 90 |   serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
 91 |     .clk(clk),
 92 |     .rst(n_rdy),
 93 |     .tx(tx_m),
 94 |     .block(busy_q),
 95 |     .busy(tx_busy),
 96 |     .data(tx_data),
 97 |     .new_data(new_tx_data)
 98 |   );
 99 |   
100 |   // Output declarations
101 |   assign new_sample = new_sample_q;
102 |   assign sample = sample_q;
103 |   assign sample_channel = sample_channel_q;
104 |   
105 |   // these signals connect to the AVR and should be Z when the AVR isn't ready
106 |   assign spi_channel = ready ? channel : 4'bZZZZ;
107 |   assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
108 |   assign tx = ready ? tx_m : 1'bZ;
109 |   
110 |   always @(*) begin
111 |     byte_ct_d = byte_ct_q;
112 |     sample_d = sample_q;
113 |     new_sample_d = 1'b0;
114 |     sample_channel_d = sample_channel_q;
115 | 
116 |     busy_d = busy_q;
117 |     block_d = {block_q[2:0], tx_block};
118 | 
119 |     if (block_q[3] ^ block_q[2])
120 |       busy_d = 1'b0;
121 | 
122 |     if (!tx_busy && new_tx_data)
123 |       busy_d = 1'b1;
124 |     
125 |     if (spi_ss) begin // device is not selected
126 |       byte_ct_d = 1'b0;
127 |     end
128 |     
129 |     if (spi_done) begin // sent/received data from SPI
130 |       if (byte_ct_q == 1'b0) begin
131 |         sample_d[7:0] = spi_dout; // first byte is the 8 LSB of the sample
132 |         byte_ct_d = 1'b1;
133 |       end else begin
134 |         sample_d[9:8] = spi_dout[1:0]; // second byte is the channel 2 MSB of the sample
135 |         sample_channel_d = spi_dout[7:4]; // and the channel that was sampled
136 |         byte_ct_d = 1'b1; // slave-select must be brought high before the next transfer
137 |         new_sample_d = 1'b1;
138 |       end
139 |     end
140 |   end
141 |   
142 |   always @(posedge clk) begin
143 |     if (n_rdy) begin
144 |       byte_ct_q <= 1'b0;
145 |       sample_q <= 10'b0;
146 |       new_sample_q <= 1'b0;
147 |     end else begin
148 |       byte_ct_q <= byte_ct_d;
149 |       sample_q <= sample_d;
150 |       new_sample_q <= new_sample_d;
151 |     end
152 |     
153 |     block_q <= block_d;
154 |     busy_q <= busy_d;
155 |     sample_channel_q <= sample_channel_d;
156 |   end
157 |   
158 | endmodule


--------------------------------------------------------------------------------
/src/cclk_detector.v:
--------------------------------------------------------------------------------
 1 | module cclk_detector #(
 2 |     parameter CLK_RATE = 50000000
 3 |     )(
 4 |     input clk,
 5 |     input rst,
 6 |     input cclk,
 7 |     output ready
 8 | );
 9 | 
10 |     parameter CTR_SIZE = $clog2(CLK_RATE/50000);
11 | 
12 |     reg [CTR_SIZE-1:0] ctr_d, ctr_q;
13 |     reg ready_d, ready_q;
14 | 
15 |     assign ready = ready_q;
16 | 
17 |     // ready should only go high once cclk has been high for a while
18 |     // if cclk ever falls, ready should go low again
19 |     always @(ctr_q or cclk) begin
20 |         ready_d = 1'b0;
21 |         if (cclk == 1'b0) begin // when cclk is 0 reset the counter
22 |             ctr_d = 1'b0;
23 |         end else if (ctr_q != {CTR_SIZE{1'b1}}) begin
24 |             ctr_d = ctr_q + 1'b1; // counter isn't max value yet
25 |         end else begin
26 |             ctr_d = ctr_q;
27 |             ready_d = 1'b1; // counter reached the max, we are ready
28 |         end
29 | 
30 |     end
31 | 
32 |     always @(posedge clk) begin
33 |         if (rst) begin
34 |             ctr_q <= 1'b0;
35 |             ready_q <= 1'b0;
36 |         end else begin
37 |             ctr_q <= ctr_d;
38 |             ready_q <= ready_d;
39 |         end
40 |     end
41 | endmodule
42 | 


--------------------------------------------------------------------------------
/src/mojo.ucf:
--------------------------------------------------------------------------------
 1 | #Created by Constraints Editor (xc6slx9-tqg144-3) - 2012/11/05
 2 | NET "clk" TNM_NET = clk;
 3 | TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
 4 | 
 5 | # PlanAhead Generated physical constraints 
 6 | NET "clk" LOC = P56 | IOSTANDARD = LVTTL;
 7 | NET "rst_n" LOC = P38 | IOSTANDARD = LVTTL;
 8 | 
 9 | NET "cclk" LOC = P70 | IOSTANDARD = LVTTL;
10 | 
11 | NET "led<0>" LOC = P134 | IOSTANDARD = LVTTL;
12 | NET "led<1>" LOC = P133 | IOSTANDARD = LVTTL;
13 | NET "led<2>" LOC = P132 | IOSTANDARD = LVTTL;
14 | NET "led<3>" LOC = P131 | IOSTANDARD = LVTTL;
15 | NET "led<4>" LOC = P127 | IOSTANDARD = LVTTL;
16 | NET "led<5>" LOC = P126 | IOSTANDARD = LVTTL;
17 | NET "led<6>" LOC = P124 | IOSTANDARD = LVTTL;
18 | NET "led<7>" LOC = P123 | IOSTANDARD = LVTTL;
19 | 
20 | NET "spi_mosi" LOC = P44 | IOSTANDARD = LVTTL;
21 | NET "spi_miso" LOC = P45 | IOSTANDARD = LVTTL;
22 | NET "spi_ss" LOC = P48 | IOSTANDARD = LVTTL;
23 | NET "spi_sck" LOC = P43 | IOSTANDARD = LVTTL;
24 | NET "spi_channel<0>" LOC = P46 | IOSTANDARD = LVTTL;
25 | NET "spi_channel<1>" LOC = P61 | IOSTANDARD = LVTTL;
26 | NET "spi_channel<2>" LOC = P62 | IOSTANDARD = LVTTL;
27 | NET "spi_channel<3>" LOC = P65 | IOSTANDARD = LVTTL;
28 | 
29 | NET "avr_tx" LOC = P55 | IOSTANDARD = LVTTL;
30 | NET "avr_rx" LOC = P59 | IOSTANDARD = LVTTL;
31 | NET "avr_rx_busy" LOC = P39 | IOSTANDARD = LVTTL;
32 | 
33 | 


--------------------------------------------------------------------------------
/src/mojo_top.v:
--------------------------------------------------------------------------------
 1 | module mojo_top(
 2 |     // 50MHz clock input
 3 |     input clk,
 4 |     // Input from reset button (active low)
 5 |     input rst_n,
 6 |     // cclk input from AVR, high when AVR is ready
 7 |     input cclk,
 8 |     // Outputs to the 8 onboard LEDs
 9 |     output[7:0]led,
10 |     // AVR SPI connections
11 |     output spi_miso,
12 |     input spi_ss,
13 |     input spi_mosi,
14 |     input spi_sck,
15 |     // AVR ADC channel select
16 |     output [3:0] spi_channel,
17 |     // Serial connections
18 |     input avr_tx, // AVR Tx => FPGA Rx
19 |     output avr_rx, // AVR Rx => FPGA Tx
20 |     input avr_rx_busy // AVR Rx buffer full
21 |     );
22 | 
23 | wire rst = ~rst_n; // make reset active high
24 | 
25 | // these signals should be high-z when not used
26 | assign spi_miso = 1'bz;
27 | assign avr_rx = 1'bz;
28 | assign spi_channel = 4'bzzzz;
29 | 
30 | assign led = 8'b0;
31 | 
32 | endmodule


--------------------------------------------------------------------------------
/src/serial_rx.v:
--------------------------------------------------------------------------------
 1 | module serial_rx #(
 2 |         parameter CLK_PER_BIT = 50
 3 |     )(
 4 |         input clk,
 5 |         input rst,
 6 |         input rx,
 7 |         output [7:0] data,
 8 |         output new_data
 9 |     );
10 | 
11 |     // clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
12 |     parameter CTR_SIZE = $clog2(CLK_PER_BIT);
13 | 
14 |     localparam STATE_SIZE = 2;
15 |     localparam IDLE = 2'd0,
16 |     WAIT_HALF = 2'd1,
17 |     WAIT_FULL = 2'd2,
18 |     WAIT_HIGH = 2'd3;
19 | 
20 |     reg [CTR_SIZE-1:0] ctr_d, ctr_q;
21 |     reg [2:0] bit_ctr_d, bit_ctr_q;
22 |     reg [7:0] data_d, data_q;
23 |     reg new_data_d, new_data_q;
24 |     reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
25 |     reg rx_d, rx_q;
26 | 
27 |     assign new_data = new_data_q;
28 |     assign data = data_q;
29 | 
30 |     always @(*) begin
31 |         rx_d = rx;
32 |         state_d = state_q;
33 |         ctr_d = ctr_q;
34 |         bit_ctr_d = bit_ctr_q;
35 |         data_d = data_q;
36 |         new_data_d = 1'b0;
37 | 
38 |         case (state_q)
39 |             IDLE: begin
40 |                 bit_ctr_d = 3'b0;
41 |                 ctr_d = 1'b0;
42 |                 if (rx_q == 1'b0) begin
43 |                     state_d = WAIT_HALF;
44 |                 end
45 |             end
46 |             WAIT_HALF: begin
47 |                 ctr_d = ctr_q + 1'b1;
48 |                 if (ctr_q == (CLK_PER_BIT >> 1)) begin
49 |                     ctr_d = 1'b0;
50 |                     state_d = WAIT_FULL;
51 |                 end
52 |             end
53 |             WAIT_FULL: begin
54 |                 ctr_d = ctr_q + 1'b1;
55 |                 if (ctr_q == CLK_PER_BIT - 1) begin
56 |                     data_d = {rx_q, data_q[7:1]};
57 |                     bit_ctr_d = bit_ctr_q + 1'b1;
58 |                     ctr_d = 1'b0;
59 |                     if (bit_ctr_q == 3'd7) begin
60 |                         state_d = WAIT_HIGH;
61 |                         new_data_d = 1'b1;
62 |                     end
63 |                 end
64 |             end
65 |             WAIT_HIGH: begin
66 |                 if (rx_q == 1'b1) begin
67 |                     state_d = IDLE;
68 |                 end
69 |             end
70 |             default: begin
71 |                 state_d = IDLE;
72 |             end
73 |         endcase
74 | 
75 |     end
76 | 
77 |     always @(posedge clk) begin
78 |         if (rst) begin
79 |             ctr_q <= 1'b0;
80 |             bit_ctr_q <= 3'b0;
81 |             new_data_q <= 1'b0;
82 |             state_q <= IDLE;
83 |         end else begin
84 |             ctr_q <= ctr_d;
85 |             bit_ctr_q <= bit_ctr_d;
86 |             new_data_q <= new_data_d;
87 |             state_q <= state_d;
88 |         end
89 | 
90 |         rx_q <= rx_d;
91 |         data_q <= data_d;
92 |     end
93 | 
94 | endmodule


--------------------------------------------------------------------------------
/src/serial_tx.v:
--------------------------------------------------------------------------------
  1 | module serial_tx #(
  2 |         parameter CLK_PER_BIT = 50
  3 |     )(
  4 |         input clk,
  5 |         input rst,
  6 |         output tx,
  7 |         input block,
  8 |         output busy,
  9 |         input [7:0] data,
 10 |         input new_data
 11 |     );
 12 | 
 13 |     // clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
 14 |     parameter CTR_SIZE = $clog2(CLK_PER_BIT);
 15 | 
 16 |     localparam STATE_SIZE = 2;
 17 |     localparam IDLE = 2'd0,
 18 |     START_BIT = 2'd1,
 19 |     DATA = 2'd2,
 20 |     STOP_BIT = 2'd3;
 21 | 
 22 |     reg [CTR_SIZE-1:0] ctr_d, ctr_q;
 23 |     reg [2:0] bit_ctr_d, bit_ctr_q;
 24 |     reg [7:0] data_d, data_q;
 25 |     reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
 26 |     reg tx_d, tx_q;
 27 |     reg busy_d, busy_q;
 28 |     reg block_d, block_q;
 29 | 
 30 |     assign tx = tx_q;
 31 |     assign busy = busy_q;
 32 | 
 33 |     always @(*) begin
 34 |         block_d = block;
 35 |         ctr_d = ctr_q;
 36 |         bit_ctr_d = bit_ctr_q;
 37 |         data_d = data_q;
 38 |         state_d = state_q;
 39 |         busy_d = busy_q;
 40 | 
 41 |         case (state_q)
 42 |             IDLE: begin
 43 |                 if (block_q) begin
 44 |                     busy_d = 1'b1;
 45 |                     tx_d = 1'b1;
 46 |                 end else begin
 47 |                     busy_d = 1'b0;
 48 |                     tx_d = 1'b1;
 49 |                     bit_ctr_d = 3'b0;
 50 |                     ctr_d = 1'b0;
 51 |                     if (new_data) begin
 52 |                         data_d = data;
 53 |                         state_d = START_BIT;
 54 |                         busy_d = 1'b1;
 55 |                     end
 56 |                 end
 57 |             end
 58 |             START_BIT: begin
 59 |                 busy_d = 1'b1;
 60 |                 ctr_d = ctr_q + 1'b1;
 61 |                 tx_d = 1'b0;
 62 |                 if (ctr_q == CLK_PER_BIT - 1) begin
 63 |                     ctr_d = 1'b0;
 64 |                     state_d = DATA;
 65 |                 end
 66 |             end
 67 |             DATA: begin
 68 |                 busy_d = 1'b1;
 69 |                 tx_d = data_q[bit_ctr_q];
 70 |                 ctr_d = ctr_q + 1'b1;
 71 |                 if (ctr_q == CLK_PER_BIT - 1) begin
 72 |                     ctr_d = 1'b0;
 73 |                     bit_ctr_d = bit_ctr_q + 1'b1;
 74 |                     if (bit_ctr_q == 7) begin
 75 |                         state_d = STOP_BIT;
 76 |                     end
 77 |                 end
 78 |             end
 79 |             STOP_BIT: begin
 80 |                 busy_d = 1'b1;
 81 |                 tx_d = 1'b1;
 82 |                 ctr_d = ctr_q + 1'b1;
 83 |                 if (ctr_q == CLK_PER_BIT - 1) begin
 84 |                     state_d = IDLE;
 85 |                 end
 86 |             end
 87 |             default: begin
 88 |                 state_d = IDLE;
 89 |             end
 90 |         endcase
 91 |     end
 92 | 
 93 |     always @(posedge clk) begin
 94 |         if (rst) begin
 95 |             state_q <= IDLE;
 96 |             tx_q <= 1'b1;
 97 |         end else begin
 98 |             state_q <= state_d;
 99 |             tx_q <= tx_d;
100 |         end
101 | 
102 |         block_q <= block_d;
103 |         data_q <= data_d;
104 |         bit_ctr_q <= bit_ctr_d;
105 |         ctr_q <= ctr_d;
106 |         busy_q <= busy_d;
107 |     end
108 | 
109 | endmodule


--------------------------------------------------------------------------------
/src/spi_slave.v:
--------------------------------------------------------------------------------
 1 | module spi_slave(
 2 |     input clk,
 3 |     input rst,
 4 |     input ss,
 5 |     input mosi,
 6 |     output miso,
 7 |     input sck,
 8 |     output done,
 9 |     input [7:0] din,
10 |     output [7:0] dout
11 |     );
12 | 
13 | reg mosi_d, mosi_q;
14 | reg ss_d, ss_q;
15 | reg sck_d, sck_q;
16 | reg sck_old_d, sck_old_q;
17 | reg [7:0] data_d, data_q;
18 | reg done_d, done_q;
19 | reg [2:0] bit_ct_d, bit_ct_q;
20 | reg [7:0] dout_d, dout_q;
21 | reg miso_d, miso_q;
22 | 
23 | assign miso = miso_q;
24 | assign done = done_q;
25 | assign dout = dout_q;
26 | 
27 | always @(*) begin
28 |     ss_d = ss;
29 |     mosi_d = mosi;
30 |     miso_d = miso_q;
31 |     sck_d = sck;
32 |     sck_old_d = sck_q;
33 |     data_d = data_q;
34 |     done_d = 1'b0;
35 |     bit_ct_d = bit_ct_q;
36 |     dout_d = dout_q;
37 | 
38 |     if (ss_q) begin
39 |         bit_ct_d = 3'b0;
40 |         data_d = din;
41 |         miso_d = data_q[7];
42 |     end else begin
43 |         if (!sck_old_q && sck_q) begin // rising edge
44 |             data_d = {data_q[6:0], mosi_q};
45 |             bit_ct_d = bit_ct_q + 1'b1;
46 |             if (bit_ct_q == 3'b111) begin
47 |                 dout_d = {data_q[6:0], mosi_q};
48 |                 done_d = 1'b1;
49 |                 data_d = din;
50 |             end
51 |         end else if (sck_old_q && !sck_q) begin // falling edge
52 |             miso_d = data_q[7];
53 |         end
54 |     end
55 | end
56 | 
57 | always @(posedge clk) begin
58 |     if (rst) begin
59 |         done_q <= 1'b0;
60 |         bit_ct_q <= 3'b0;
61 |         dout_q <= 8'b0;
62 |         miso_q <= 1'b1;
63 |     end else begin
64 |         done_q <= done_d;
65 |         bit_ct_q <= bit_ct_d;
66 |         dout_q <= dout_d;
67 |         miso_q <= miso_d;
68 |     end
69 | 
70 |     sck_q <= sck_d;
71 |     mosi_q <= mosi_d;
72 |     ss_q <= ss_d;
73 |     data_q <= data_d;
74 |     sck_old_q <= sck_old_d;
75 | 
76 | end
77 | 
78 | 
79 | endmodule
80 | 


--------------------------------------------------------------------------------
/syn/.gitignore:
--------------------------------------------------------------------------------
1 | # Ignore everything in this directory
2 | *
3 | # Except this file
4 | !.gitignore


--------------------------------------------------------------------------------