├── LICENSE
├── README.md
├── f303_ice5_fw
├── .gdbinit
├── CMSIS
│ ├── arm_math.h
│ ├── core_cm4.h
│ ├── core_cm4_simd.h
│ ├── core_cmFunc.h
│ ├── core_cmInstr.h
│ ├── startup_stm32f30x.s
│ ├── system_stm32f30x.c
│ └── system_stm32f30x.h
├── Makefile
├── README.md
├── STM32_FLASH.ld
├── StdPeriph
│ ├── stm32f30x.h
│ ├── stm32f30x_adc.c
│ ├── stm32f30x_adc.h
│ ├── stm32f30x_can.c
│ ├── stm32f30x_can.h
│ ├── stm32f30x_comp.h
│ ├── stm32f30x_conf.h
│ ├── stm32f30x_crc.h
│ ├── stm32f30x_dac.c
│ ├── stm32f30x_dac.h
│ ├── stm32f30x_dbgmcu.c
│ ├── stm32f30x_dbgmcu.h
│ ├── stm32f30x_dma.c
│ ├── stm32f30x_dma.h
│ ├── stm32f30x_exti.c
│ ├── stm32f30x_exti.h
│ ├── stm32f30x_flash.c
│ ├── stm32f30x_flash.h
│ ├── stm32f30x_fmc.c
│ ├── stm32f30x_fmc.h
│ ├── stm32f30x_gpio.c
│ ├── stm32f30x_gpio.h
│ ├── stm32f30x_hrtim.c
│ ├── stm32f30x_hrtim.h
│ ├── stm32f30x_i2c.c
│ ├── stm32f30x_i2c.h
│ ├── stm32f30x_iwdg.c
│ ├── stm32f30x_iwdg.h
│ ├── stm32f30x_misc.c
│ ├── stm32f30x_misc.h
│ ├── stm32f30x_opamp.c
│ ├── stm32f30x_opamp.h
│ ├── stm32f30x_pwr.c
│ ├── stm32f30x_pwr.h
│ ├── stm32f30x_rcc.c
│ ├── stm32f30x_rcc.h
│ ├── stm32f30x_rtc.c
│ ├── stm32f30x_rtc.h
│ ├── stm32f30x_spi.c
│ ├── stm32f30x_spi.h
│ ├── stm32f30x_syscfg.c
│ ├── stm32f30x_syscfg.h
│ ├── stm32f30x_tim.c
│ ├── stm32f30x_tim.h
│ ├── stm32f30x_usart.c
│ ├── stm32f30x_usart.h
│ ├── stm32f30x_wwdg.c
│ └── stm32f30x_wwdg.h
├── bitmap.bin
├── cmd.c
├── cmd.h
├── cyclesleep.c
├── cyclesleep.h
├── ff9a
│ ├── 00readme.txt
│ ├── diskio.c
│ ├── diskio.h
│ ├── ff.c
│ ├── ff.h
│ ├── ffconf.h
│ ├── integer.h
│ └── option
│ │ ├── cc932.c
│ │ ├── cc936.c
│ │ ├── cc949.c
│ │ ├── cc950.c
│ │ ├── ccsbcs.c
│ │ ├── syscall.c
│ │ └── unicode.c
├── flash_cmd.gdb
├── ice5.c
├── ice5.h
├── led.c
├── led.h
├── main.c
├── openocd.cfg
├── openocd_j-link.cfg
├── openocd_stlinkv2.1.cfg
├── shared_spi.c
├── shared_spi.h
├── stubs.c
├── systick.c
├── systick.h
├── usart.c
└── usart.h
└── f303_ice5_hw
├── README.md
├── f303_ice5_test
├── f303_ice5_test_sbt.project
└── f303_ice5_test_syn.prj
└── src
├── f303_ice5_test.pcf
├── f303_ice5_test.v
└── spi_slave.v
/LICENSE:
--------------------------------------------------------------------------------
1 | The MIT License (MIT)
2 |
3 | Copyright (c) 2016 Eric Brombaugh
4 |
5 | Permission is hereby granted, free of charge, to any person obtaining a copy
6 | of this software and associated documentation files (the "Software"), to deal
7 | in the Software without restriction, including without limitation the rights
8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 | copies of the Software, and to permit persons to whom the Software is
10 | furnished to do so, subject to the following conditions:
11 |
12 | The above copyright notice and this permission notice shall be included in all
13 | copies or substantial portions of the Software.
14 |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 | SOFTWARE.
22 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # f303_ice5
2 |
3 | This is MCU firmware and FPGA hardware source for the f303_ice5 board. For
4 | more information, please see the main project web page here:
5 |
6 | http://ebrombaugh.studionebula.com/embedded/f303_ice5/index.html
7 |
8 |
9 |
--------------------------------------------------------------------------------
/f303_ice5_fw/.gdbinit:
--------------------------------------------------------------------------------
1 | define flash
2 | file main.elf
3 | load
4 | end
5 |
6 | define restart
7 | run
8 | end
9 |
10 | define attach_swd
11 | mon swdp_scan
12 | attach 1
13 | end
14 |
15 | file main.elf
16 | target extended-remote /dev/ttyACM0
17 |
18 | set mem inaccessible-by-default off
19 |
20 | attach_swd
21 |
--------------------------------------------------------------------------------
/f303_ice5_fw/CMSIS/system_stm32f30x.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f30x.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2015 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /** @addtogroup CMSIS
29 | * @{
30 | */
31 |
32 | /** @addtogroup stm32f30x_system
33 | * @{
34 | */
35 |
36 | /**
37 | * @brief Define to prevent recursive inclusion
38 | */
39 | #ifndef __SYSTEM_STM32F30X_H
40 | #define __SYSTEM_STM32F30X_H
41 |
42 | #ifdef __cplusplus
43 | extern "C" {
44 | #endif
45 |
46 | /* Exported types ------------------------------------------------------------*/
47 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
48 | /* Exported constants --------------------------------------------------------*/
49 | /* Exported macro ------------------------------------------------------------*/
50 | /* Exported functions ------------------------------------------------------- */
51 |
52 | /** @addtogroup STM32F30x_System_Exported_Functions
53 | * @{
54 | */
55 |
56 | extern void SystemInit(void);
57 | extern void SystemCoreClockUpdate(void);
58 |
59 | /**
60 | * @}
61 | */
62 |
63 | #ifdef __cplusplus
64 | }
65 | #endif
66 |
67 | #endif /*__SYSTEM_STM32F30X_H */
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
77 |
--------------------------------------------------------------------------------
/f303_ice5_fw/Makefile:
--------------------------------------------------------------------------------
1 | # Makefile for STM32F30x
2 | # 01-28-2013 E. Brombaugh
3 |
4 | # sub directories
5 | VPATH = .:CMSIS:StdPeriph:ff9a
6 |
7 | # Object files
8 | OBJECTS = startup_stm32f30x.o system_stm32f30x.o main.o cyclesleep.o \
9 | systick.o usart.o stubs.o led.o ice5.o cmd.o bitmap.o \
10 | shared_spi.o ff.o diskio.o \
11 | stm32f30x_gpio.o stm32f30x_misc.o stm32f30x_rcc.o \
12 | stm32f30x_usart.o stm32f30x_spi.o stm32f30x_dma.o
13 |
14 |
15 | # Linker script
16 | LDSCRIPT = STM32_FLASH.ld
17 |
18 | CFLAGS = -g -O3 -mlittle-endian -mthumb -ffunction-sections -std=c99
19 | CFLAGS += -Wall -Wno-strict-aliasing
20 | CFLAGS += -I. -ICMSIS -IStdPeriph -Iff9a
21 | CFLAGS += -DARM_MATH_CM4 -D'__FPU_PRESENT=1' -DUSE_STDPERIPH_DRIVER
22 | CFLAGS += -DSTM32F303xC -D'HSE_VALUE=((uint32_t)8000000)'
23 | CFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16
24 | AFLAGS = -mlittle-endian -mthumb -mcpu=cortex-m4
25 | LFLAGS = $(CFLAGS) -nostartfiles -T $(LDSCRIPT) -Wl,-Map=main.map
26 | LFLAGS += -Wl,--gc-sections
27 | #LFLAGS += --specs=nano.specs
28 | CPFLAGS = --output-target=binary
29 | ODFLAGS = -x --syms
30 |
31 | # Executables
32 | ARCH = arm-none-eabi
33 | CC = $(ARCH)-gcc
34 | CPP = $(ARCH)-g++
35 | LD = $(ARCH)-ld -v
36 | AS = $(ARCH)-as
37 | OBJCPY = $(ARCH)-objcopy
38 | OBJDMP = $(ARCH)-objdump
39 | GDB = $(ARCH)-gdb
40 | OPENOCD = openocd
41 | DFU = dfu-util
42 |
43 | #CPFLAGS = --output-target=binary -j .text -j .data
44 | CPFLAGS = --output-target=binary
45 | ODFLAGS = -x --syms
46 |
47 | # Targets
48 | all: main.bin
49 |
50 | clean:
51 | -rm -f $(OBJECTS) *.lst *.elf *.map *.dmp main.bin
52 |
53 | flash: gdb_flash
54 | #flash: openocd_flash
55 | #flash: openocd_v2.1_flash
56 |
57 | gdb_flash: main.elf
58 | $(GDB) -x flash_cmd.gdb -batch
59 | stty sane
60 |
61 | openocd_flash: main.elf
62 | $(OPENOCD) -f openocd.cfg -c "program main.elf verify reset exit"
63 |
64 | openocd_jlink_flash: main.elf
65 | $(OPENOCD) -f openocd_j-link.cfg -c "program main.elf verify reset exit"
66 |
67 | openocd_v2.1_flash: main.elf
68 | $(OPENOCD) -f openocd_stlinkv2.1.cfg -c "program main.elf verify reset exit"
69 |
70 | dfu: main.bin
71 | $(DFU) -a 0 -d 0483:df11 -s 0x8000000 -D main.bin
72 |
73 | disassemble: main.elf
74 | $(OBJDMP) -dS main.elf > main.dis
75 |
76 | dist:
77 | tar -c *.h *.c *.s Makefile *.cmd *.cfg openocd_doflash | gzip > minimal_hello_world.tar.gz
78 |
79 | main.ihex: main.elf
80 | $(OBJCPY) --output-target=ihex main.elf main.ihex
81 |
82 | main.bin: main.elf
83 | $(OBJCPY) $(CPFLAGS) main.elf main.bin
84 | $(OBJDMP) $(ODFLAGS) main.elf > main.dmp
85 | ls -l main.elf main.bin
86 |
87 | main.elf: $(OBJECTS) $(LDSCRIPT)
88 | $(CC) $(LFLAGS) -o main.elf $(OBJECTS) -lnosys -lm
89 |
90 | bitmap.o: bitmap.bin
91 | $(OBJCPY) -I binary -O elf32-littlearm -B arm --rename-section .data=.rodata bitmap.bin bitmap.o
92 |
93 | %.o: %.c %.h
94 | $(CC) $(CFLAGS) -c -o $@ $<
95 |
--------------------------------------------------------------------------------
/f303_ice5_fw/README.md:
--------------------------------------------------------------------------------
1 | # f303_ice5_fw
2 |
3 | This is MCU firmware source for the f303_ice5 board.
4 |
5 | Building
6 | --------
7 |
8 | * Ensure you've got the Gnu ARM Embedded toolchain installed
9 |
10 | * Just run
11 | make
12 |
13 | Flashing
14 | --------
15 |
16 | There are several flashing options in the Makefile
17 |
18 | * gdb_flash - flash using gdb and Black Magic Probe (BMP)
19 | * openocd_flash - flash using OpenOCD and ST-Link V2
20 | * openocd_v2.1_flash - flash using OpenOCD and ST-Link V2.1
21 | * openocd_jlink_flash - flash via OpenOCD and Segger J-Link
22 |
23 | Hook up your download pod and run
24 |
25 | make [flash option from above list]
26 |
27 | * dfu - flash using the STM32F303 USB DFU bootloader
28 |
29 | Hold down the BOOT button on the f303_ice5 while inserting the USB connector.
30 | The board should be recognized by Linux as a DFU device. Then run
31 |
32 | make dfu
33 |
34 | Running
35 | -------
36 |
37 | Plug into USB cable. This basic firmware doesn't provide USB functionality but
38 | it does provide a serial 115k command processor on pins 5/6 of the expansion
39 | connector. Type 'help' to get the latest list of supported commands. At this
40 | point these commands are provided:
41 |
42 | * help - this message
43 | * spi_read (addr) - FPGA SPI read reg
44 | * spi_write (addr) (data) - FPGA SPI write reg, data
45 | * dir - directory of SD card root
46 | * config_file (file) - Configure FPGA from file
47 |
48 | The included bitmap.bin FPGA bitstream contains just two
49 | registers accessible via the SPI bus thru the commands "spi_read" and
50 | "spi_write" - a device ID (0XDEADBEEF) at register 0 and a timer divider
51 | at register 1 which controls the speed of the 3 LED blinker.
52 |
53 | Debugging
54 | ---------
55 |
56 | 1) in a separate window start up openocd as a GDB server
57 | openocd -f openocd.cfg
58 |
59 | 2) run gdb with your favorite UI
60 | ddd --debugger arm-none-eabi-gdb main.elf
61 |
62 | 3) connect to the server within gdb
63 | target extended-remote localhost:3333
64 |
65 | 4) Start debugging!
66 |
--------------------------------------------------------------------------------
/f303_ice5_fw/STM32_FLASH.ld:
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https://raw.githubusercontent.com/emeb/f303_ice5/f89a719ab5ab2dc17449907835ca88a616ade192/f303_ice5_fw/STM32_FLASH.ld
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/f303_ice5_fw/StdPeriph/stm32f30x.h:
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https://raw.githubusercontent.com/emeb/f303_ice5/f89a719ab5ab2dc17449907835ca88a616ade192/f303_ice5_fw/StdPeriph/stm32f30x.h
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/f303_ice5_fw/StdPeriph/stm32f30x_conf.h:
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1 | /**
2 | ******************************************************************************
3 | * @file Lib_DEBUG/Lib_DEBUG_Example/stm32f30x_conf.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 23-October-2012
7 | * @brief Library configuration file.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2012 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F30X_CONF_H
30 | #define __STM32F30X_CONF_H
31 |
32 | /* Includes ------------------------------------------------------------------*/
33 | /* Comment the line below to disable peripheral header file inclusion */
34 | //#include "stm32f30x_adc.h"
35 | //#include "stm32f30x_can.h"
36 | //#include "stm32f30x_crc.h"
37 | //#include "stm32f30x_comp.h"
38 | //#include "stm32f30x_dac.h"
39 | //#include "stm32f30x_dbgmcu.h"
40 | #include "stm32f30x_dma.h"
41 | //#include "stm32f30x_exti.h"
42 | //#include "stm32f30x_flash.h"
43 | #include "stm32f30x_gpio.h"
44 | //#include "stm32f30x_syscfg.h"
45 | //#include "stm32f30x_i2c.h"
46 | //#include "stm32f30x_iwdg.h"
47 | //#include "stm32f30x_opamp.h"
48 | //#include "stm32f30x_pwr.h"
49 | #include "stm32f30x_rcc.h"
50 | //#include "stm32f30x_rtc.h"
51 | #include "stm32f30x_spi.h"
52 | //#include "stm32f30x_tim.h"
53 | #include "stm32f30x_usart.h"
54 | //#include "stm32f30x_wwdg.h"
55 | #include "stm32f30x_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
56 |
57 | /* Exported types ------------------------------------------------------------*/
58 | /* Exported constants --------------------------------------------------------*/
59 | /* Uncomment the line below to expanse the "assert_param" macro in the
60 | Standard Peripheral Library drivers code */
61 | #define USE_FULL_ASSERT 1
62 |
63 | /* Exported macro ------------------------------------------------------------*/
64 | #ifdef USE_FULL_ASSERT
65 |
66 | /**
67 | * @brief The assert_param macro is used for function's parameters check.
68 | * @param expr: If expr is false, it calls assert_failed function which reports
69 | * the name of the source file and the source line number of the call
70 | * that failed. If expr is true, it returns no value.
71 | * @retval None
72 | */
73 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
74 | /* Exported functions ------------------------------------------------------- */
75 | void assert_failed(uint8_t* file, uint32_t line);
76 | #else
77 | #define assert_param(expr) ((void)0)
78 | #endif /* USE_FULL_ASSERT */
79 |
80 | #endif /* __STM32F30X_CONF_H */
81 |
82 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
83 |
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/f303_ice5_fw/StdPeriph/stm32f30x_crc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_crc.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file contains all the functions prototypes for the CRC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2015 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_CRC_H
31 | #define __STM32F30x_CRC_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /*!< Includes ----------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup CRC
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup CRC_ReverseInputData
52 | * @{
53 | */
54 | #define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
55 | #define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
56 | #define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
57 | #define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
58 |
59 | #define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
60 | ((DATA) == CRC_ReverseInputData_8bits) || \
61 | ((DATA) == CRC_ReverseInputData_16bits) || \
62 | ((DATA) == CRC_ReverseInputData_32bits))
63 |
64 | /**
65 | * @}
66 | */
67 |
68 | /** @defgroup CRC_PolynomialSize
69 | * @{
70 | */
71 | #define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
72 | #define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
73 | #define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
74 | #define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
75 |
76 | #define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
77 | ((SIZE) == CRC_PolSize_8) || \
78 | ((SIZE) == CRC_PolSize_16) || \
79 | ((SIZE) == CRC_PolSize_32))
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | /* Exported macro ------------------------------------------------------------*/
86 | /* Exported functions ------------------------------------------------------- */
87 | /* Configuration of the CRC computation unit **********************************/
88 | void CRC_DeInit(void);
89 | void CRC_ResetDR(void);
90 | void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize);
91 | void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
92 | void CRC_ReverseOutputDataCmd(FunctionalState NewState);
93 | void CRC_SetInitRegister(uint32_t CRC_InitValue);
94 | void CRC_SetPolynomial(uint32_t CRC_Pol);
95 |
96 | /* CRC computation ************************************************************/
97 | uint32_t CRC_CalcCRC(uint32_t CRC_Data);
98 | uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
99 | uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
100 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
101 | uint32_t CRC_GetCRC(void);
102 |
103 | /* Independent register (IDR) access (write/read) *****************************/
104 | void CRC_SetIDRegister(uint8_t CRC_IDValue);
105 | uint8_t CRC_GetIDRegister(void);
106 |
107 | #ifdef __cplusplus
108 | }
109 | #endif
110 |
111 | #endif /* __STM32F30x_CRC_H */
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | /**
118 | * @}
119 | */
120 |
121 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
122 |
--------------------------------------------------------------------------------
/f303_ice5_fw/StdPeriph/stm32f30x_dbgmcu.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_dbgmcu.c
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the Debug MCU (DBGMCU) peripheral:
9 | * + Device and Revision ID management
10 | * + Peripherals Configuration
11 | ******************************************************************************
12 | * @attention
13 | *
14 | * © COPYRIGHT 2015 STMicroelectronics
15 | *
16 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
17 | * You may not use this file except in compliance with the License.
18 | * You may obtain a copy of the License at:
19 | *
20 | * http://www.st.com/software_license_agreement_liberty_v2
21 | *
22 | * Unless required by applicable law or agreed to in writing, software
23 | * distributed under the License is distributed on an "AS IS" BASIS,
24 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 | * See the License for the specific language governing permissions and
26 | * limitations under the License.
27 | *
28 | ******************************************************************************
29 | */
30 |
31 | /* Includes ------------------------------------------------------------------*/
32 | #include "stm32f30x_dbgmcu.h"
33 |
34 | /** @addtogroup STM32F30x_StdPeriph_Driver
35 | * @{
36 | */
37 |
38 | /** @defgroup DBGMCU
39 | * @brief DBGMCU driver modules
40 | * @{
41 | */
42 |
43 | /* Private typedef -----------------------------------------------------------*/
44 | /* Private define ------------------------------------------------------------*/
45 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
46 |
47 | /* Private macro -------------------------------------------------------------*/
48 | /* Private variables ---------------------------------------------------------*/
49 | /* Private function prototypes -----------------------------------------------*/
50 | /* Private functions ---------------------------------------------------------*/
51 |
52 | /** @defgroup DBGMCU_Private_Functions
53 | * @{
54 | */
55 |
56 | /** @defgroup DBGMCU_Group1 Device and Revision ID management functions
57 | * @brief Device and Revision ID management functions
58 | *
59 | @verbatim
60 | ==============================================================================
61 | ##### Device and Revision ID management functions #####
62 | ==============================================================================
63 |
64 | @endverbatim
65 | * @{
66 | */
67 |
68 | /**
69 | * @brief Returns the device revision identifier.
70 | * @param None
71 | * @retval Device revision identifier
72 | */
73 | uint32_t DBGMCU_GetREVID(void)
74 | {
75 | return(DBGMCU->IDCODE >> 16);
76 | }
77 |
78 | /**
79 | * @brief Returns the device identifier.
80 | * @param None
81 | * @retval Device identifier
82 | */
83 | uint32_t DBGMCU_GetDEVID(void)
84 | {
85 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
86 | }
87 |
88 | /**
89 | * @}
90 | */
91 |
92 | /** @defgroup DBGMCU_Group2 Peripherals Configuration functions
93 | * @brief Peripherals Configuration
94 | *
95 | @verbatim
96 | ==============================================================================
97 | ##### Peripherals Configuration functions #####
98 | ==============================================================================
99 |
100 | @endverbatim
101 | * @{
102 | */
103 |
104 | /**
105 | * @brief Configures low power mode behavior when the MCU is in Debug mode.
106 | * @param DBGMCU_Periph: specifies the low power mode.
107 | * This parameter can be any combination of the following values:
108 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.
109 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode.
110 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.
111 | * @param NewState: new state of the specified low power mode in Debug mode.
112 | * This parameter can be: ENABLE or DISABLE.
113 | * @retval None
114 | */
115 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
116 | {
117 | /* Check the parameters */
118 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
119 | assert_param(IS_FUNCTIONAL_STATE(NewState));
120 | if (NewState != DISABLE)
121 | {
122 | DBGMCU->CR |= DBGMCU_Periph;
123 | }
124 | else
125 | {
126 | DBGMCU->CR &= ~DBGMCU_Periph;
127 | }
128 | }
129 |
130 | /**
131 | * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
132 | * @param DBGMCU_Periph: specifies the APB1 peripheral.
133 | * This parameter can be any combination of the following values:
134 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.
135 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.
136 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
137 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.
138 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
139 | * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when
140 | * Core is halted.
141 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
142 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.
143 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when
144 | * Core is halted.
145 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when
146 | * Core is halted.
147 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.
148 | * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when
149 | * Core is halted.
150 | * @param NewState: new state of the specified APB1 peripheral in Debug mode.
151 | * This parameter can be: ENABLE or DISABLE.
152 | * @retval None
153 | */
154 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
155 | {
156 | /* Check the parameters */
157 | assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
158 | assert_param(IS_FUNCTIONAL_STATE(NewState));
159 |
160 | if (NewState != DISABLE)
161 | {
162 | DBGMCU->APB1FZ |= DBGMCU_Periph;
163 | }
164 | else
165 | {
166 | DBGMCU->APB1FZ &= ~DBGMCU_Periph;
167 | }
168 | }
169 |
170 | /**
171 | * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
172 | * @param DBGMCU_Periph: specifies the APB2 peripheral.
173 | * This parameter can be any combination of the following values:
174 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.
175 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted.
176 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.
177 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
178 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.
179 | * @arg DBGMCU_TIM20_STOP: TIM20 counter stopped when Core is halted.
180 | * @param NewState: new state of the specified APB2 peripheral in Debug mode.
181 | * This parameter can be: ENABLE or DISABLE.
182 | * @retval None
183 | */
184 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
185 | {
186 | /* Check the parameters */
187 | assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
188 | assert_param(IS_FUNCTIONAL_STATE(NewState));
189 |
190 | if (NewState != DISABLE)
191 | {
192 | DBGMCU->APB2FZ |= DBGMCU_Periph;
193 | }
194 | else
195 | {
196 | DBGMCU->APB2FZ &= ~DBGMCU_Periph;
197 | }
198 | }
199 |
200 | /**
201 | * @}
202 | */
203 |
204 | /**
205 | * @}
206 | */
207 |
208 | /**
209 | * @}
210 | */
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
217 |
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/f303_ice5_fw/StdPeriph/stm32f30x_dbgmcu.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_dbgmcu.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2015 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F30x_DBGMCU_H
30 | #define __STM32F30x_DBGMCU_H
31 |
32 | #ifdef __cplusplus
33 | extern "C" {
34 | #endif
35 |
36 | /* Includes ------------------------------------------------------------------*/
37 | #include "stm32f30x.h"
38 |
39 | /** @addtogroup STM32F30x_StdPeriph_Driver
40 | * @{
41 | */
42 |
43 | /** @addtogroup DBGMCU
44 | * @{
45 | */
46 |
47 | /* Exported types ------------------------------------------------------------*/
48 | /* Exported constants --------------------------------------------------------*/
49 |
50 | /** @defgroup DBGMCU_Exported_Constants
51 | * @{
52 | */
53 | #define DBGMCU_SLEEP ((uint32_t)0x00000001)
54 | #define DBGMCU_STOP ((uint32_t)0x00000002)
55 | #define DBGMCU_STANDBY ((uint32_t)0x00000004)
56 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
57 |
58 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
59 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
60 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
61 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
62 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
63 | #define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
64 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
65 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
66 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
67 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
68 | #define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
69 | #define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
70 |
71 | #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xBD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
72 |
73 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
74 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
75 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
76 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
77 | #define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
78 | #define DBGMCU_TIM20_STOP ((uint32_t)0x00000020)
79 | #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFC0) == 0x00) && ((PERIPH) != 0x00))
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | /* Exported macro ------------------------------------------------------------*/
86 | /* Exported functions --------------------------------------------------------*/
87 | /* Device and Revision ID management functions ********************************/
88 | uint32_t DBGMCU_GetREVID(void);
89 | uint32_t DBGMCU_GetDEVID(void);
90 |
91 | /* Peripherals Configuration functions ****************************************/
92 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
93 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
94 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
95 |
96 | #ifdef __cplusplus
97 | }
98 | #endif
99 |
100 | #endif /* __STM32F30x_DBGMCU_H */
101 |
102 | /**
103 | * @}
104 | */
105 |
106 | /**
107 | * @}
108 | */
109 |
110 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
111 |
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/f303_ice5_fw/StdPeriph/stm32f30x_exti.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_exti.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file contains all the functions prototypes for the EXTI
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2015 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_EXTI_H
31 | #define __STM32F30x_EXTI_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup EXTI
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief EXTI mode enumeration
52 | */
53 |
54 | typedef enum
55 | {
56 | EXTI_Mode_Interrupt = 0x00,
57 | EXTI_Mode_Event = 0x04
58 | }EXTIMode_TypeDef;
59 |
60 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
61 |
62 | /**
63 | * @brief EXTI Trigger enumeration
64 | */
65 |
66 | typedef enum
67 | {
68 | EXTI_Trigger_Rising = 0x08,
69 | EXTI_Trigger_Falling = 0x0C,
70 | EXTI_Trigger_Rising_Falling = 0x10
71 | }EXTITrigger_TypeDef;
72 |
73 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
74 | ((TRIGGER) == EXTI_Trigger_Falling) || \
75 | ((TRIGGER) == EXTI_Trigger_Rising_Falling))
76 | /**
77 | * @brief EXTI Init Structure definition
78 | */
79 |
80 | typedef struct
81 | {
82 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
83 | This parameter can be any combination of @ref EXTI_Lines */
84 |
85 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
86 | This parameter can be a value of @ref EXTIMode_TypeDef */
87 |
88 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
89 | This parameter can be a value of @ref EXTITrigger_TypeDef */
90 |
91 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
92 | This parameter can be set either to ENABLE or DISABLE */
93 | }EXTI_InitTypeDef;
94 |
95 | /* Exported constants --------------------------------------------------------*/
96 |
97 | /** @defgroup EXTI_Exported_Constants
98 | * @{
99 | */
100 | /** @defgroup EXTI_Lines
101 | * @{
102 | */
103 |
104 | #define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
105 | #define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
106 | #define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
107 | #define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
108 | #define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
109 | #define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
110 | #define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
111 | #define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
112 | #define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
113 | #define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
114 | #define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
115 | #define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
116 | #define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
117 | #define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
118 | #define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
119 | #define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
120 | #define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
121 | Connected to the PVD Output */
122 | #define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
123 | Connected to the RTC Alarm
124 | event */
125 | #define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
126 | Connected to the USB Device
127 | Wakeup from suspend event */
128 | #define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
129 | Connected to the RTC Tamper
130 | and Time Stamp events */
131 | #define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
132 | Connected to the RTC wakeup
133 | event */
134 | #define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
135 | Connected to the Comparator 1
136 | event */
137 | #define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
138 | Connected to the Comparator 2
139 | event */
140 | #define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
141 | Connected to the I2C1 wakeup
142 | event */
143 | #define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
144 | Connected to the I2C2 wakeup
145 | event */
146 | #define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
147 | Connected to the USART1 wakeup
148 | event */
149 | #define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
150 | Connected to the USART2 wakeup
151 | event */
152 | #define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
153 | reserved */
154 | #define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
155 | Connected to the USART3 wakeup
156 | event */
157 | #define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
158 | Connected to the Comparator 3
159 | event */
160 | #define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
161 | Connected to the Comparator 4
162 | event */
163 | #define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
164 | Connected to the Comparator 5
165 | event */
166 | #define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
167 | Connected to the Comparator 6
168 | event */
169 | #define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
170 | Connected to the Comparator 7
171 | event */
172 | #define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
173 | Connected to the USART4 wakeup
174 | event */
175 | #define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
176 | Connected to the USART5 wakeup
177 | event */
178 |
179 | #define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
180 | #define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
181 | ((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
182 |
183 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
184 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
185 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
186 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
187 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
188 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
189 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
190 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
191 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
192 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
193 | ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
194 | ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
195 | ((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
196 | ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
197 | /**
198 | * @}
199 | */
200 |
201 | /**
202 | * @}
203 | */
204 |
205 | /* Exported macro ------------------------------------------------------------*/
206 | /* Exported functions ------------------------------------------------------- */
207 | /* Function used to set the EXTI configuration to the default reset state *****/
208 | void EXTI_DeInit(void);
209 |
210 | /* Initialization and Configuration functions *********************************/
211 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
212 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
213 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
214 |
215 | /* Interrupts and flags management functions **********************************/
216 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
217 | void EXTI_ClearFlag(uint32_t EXTI_Line);
218 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
219 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
220 |
221 | #ifdef __cplusplus
222 | }
223 | #endif
224 |
225 | #endif /* __STM32F30x_EXTI_H */
226 | /**
227 | * @}
228 | */
229 |
230 | /**
231 | * @}
232 | */
233 |
234 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
235 |
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/f303_ice5_fw/StdPeriph/stm32f30x_hrtim.h:
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https://raw.githubusercontent.com/emeb/f303_ice5/f89a719ab5ab2dc17449907835ca88a616ade192/f303_ice5_fw/StdPeriph/stm32f30x_hrtim.h
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/f303_ice5_fw/StdPeriph/stm32f30x_iwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_iwdg.c
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the Independent watchdog (IWDG) peripheral:
9 | * + Prescaler and Counter configuration
10 | * + IWDG activation
11 | * + Flag management
12 | *
13 | @verbatim
14 |
15 | ===============================================================================
16 | ##### IWDG features #####
17 | ===============================================================================
18 | [..] The IWDG can be started by either software or hardware (configurable
19 | through option byte).
20 | [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
21 | thus stays active even if the main clock fails.
22 | Once the IWDG is started, the LSI is forced ON and cannot be disabled
23 | (LSI cannot be disabled too), and the counter starts counting down from
24 | the reset value of 0xFFF. When it reaches the end of count value (0x000)
25 | a system reset is generated.
26 | The IWDG counter should be reloaded at regular intervals to prevent
27 | an MCU reset.
28 | [..] The IWDG is implemented in the VDD voltage domain that is still functional
29 | in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
30 | [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
31 | reset occurs.
32 | [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
33 | The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x
34 | devices provide the capability to measure the LSI frequency (LSI clock
35 | connected internally to TIM16 CH1 input capture). The measured value
36 | can be used to have an IWDG timeout with an acceptable accuracy.
37 | For more information, please refer to the STM32F30x Reference manual.
38 |
39 | ##### How to use this driver #####
40 | ===============================================================================
41 | [..] This driver allows to use IWDG peripheral with either window option enabled
42 | or disabled. To do so follow one of the two procedures below.
43 | (#) Window option is enabled:
44 | (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
45 | in software mode (no need to enable the LSI, it will be enabled
46 | by hardware).
47 | (++) Enable write access to IWDG_PR and IWDG_RLR registers using
48 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
49 | (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
50 | (++) Configure the IWDG counter value using IWDG_SetReload() function.
51 | This value will be loaded in the IWDG counter each time the counter
52 | is reloaded, then the IWDG will start counting down from this value.
53 | (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
54 | (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
55 |
56 | (#) Window option is disabled:
57 | (++) Enable write access to IWDG_PR and IWDG_RLR registers using
58 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
59 | (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
60 | (++) Configure the IWDG counter value using IWDG_SetReload() function.
61 | This value will be loaded in the IWDG counter each time the counter
62 | is reloaded, then the IWDG will start counting down from this value.
63 | (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
64 | (++) reload the IWDG counter at regular intervals during normal operation
65 | to prevent an MCU reset, using IWDG_ReloadCounter() function.
66 | (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
67 | in software mode (no need to enable the LSI, it will be enabled
68 | by hardware).
69 |
70 | @endverbatim
71 |
72 | ******************************************************************************
73 | * @attention
74 | *
75 | * © COPYRIGHT 2015 STMicroelectronics
76 | *
77 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
78 | * You may not use this file except in compliance with the License.
79 | * You may obtain a copy of the License at:
80 | *
81 | * http://www.st.com/software_license_agreement_liberty_v2
82 | *
83 | * Unless required by applicable law or agreed to in writing, software
84 | * distributed under the License is distributed on an "AS IS" BASIS,
85 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
86 | * See the License for the specific language governing permissions and
87 | * limitations under the License.
88 | *
89 | ******************************************************************************
90 | */
91 |
92 | /* Includes ------------------------------------------------------------------*/
93 | #include "stm32f30x_iwdg.h"
94 |
95 | /** @addtogroup STM32F30x_StdPeriph_Driver
96 | * @{
97 | */
98 |
99 | /** @defgroup IWDG
100 | * @brief IWDG driver modules
101 | * @{
102 | */
103 |
104 | /* Private typedef -----------------------------------------------------------*/
105 | /* Private define ------------------------------------------------------------*/
106 | /* ---------------------- IWDG registers bit mask ----------------------------*/
107 | /* KR register bit mask */
108 | #define KR_KEY_RELOAD ((uint16_t)0xAAAA)
109 | #define KR_KEY_ENABLE ((uint16_t)0xCCCC)
110 |
111 | /* Private macro -------------------------------------------------------------*/
112 | /* Private variables ---------------------------------------------------------*/
113 | /* Private function prototypes -----------------------------------------------*/
114 | /* Private functions ---------------------------------------------------------*/
115 |
116 | /** @defgroup IWDG_Private_Functions
117 | * @{
118 | */
119 |
120 | /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
121 | * @brief Prescaler and Counter configuration functions
122 | *
123 | @verbatim
124 | ===============================================================================
125 | ##### Prescaler and Counter configuration functions #####
126 | ===============================================================================
127 |
128 | @endverbatim
129 | * @{
130 | */
131 |
132 | /**
133 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
134 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
135 | * This parameter can be one of the following values:
136 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
137 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
138 | * @retval None
139 | */
140 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
141 | {
142 | /* Check the parameters */
143 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
144 | IWDG->KR = IWDG_WriteAccess;
145 | }
146 |
147 | /**
148 | * @brief Sets IWDG Prescaler value.
149 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
150 | * This parameter can be one of the following values:
151 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
152 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
153 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
154 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
155 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
156 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
157 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
158 | * @retval None
159 | */
160 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
161 | {
162 | /* Check the parameters */
163 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
164 | IWDG->PR = IWDG_Prescaler;
165 | }
166 |
167 | /**
168 | * @brief Sets IWDG Reload value.
169 | * @param Reload: specifies the IWDG Reload value.
170 | * This parameter must be a number between 0 and 0x0FFF.
171 | * @retval None
172 | */
173 | void IWDG_SetReload(uint16_t Reload)
174 | {
175 | /* Check the parameters */
176 | assert_param(IS_IWDG_RELOAD(Reload));
177 | IWDG->RLR = Reload;
178 | }
179 |
180 | /**
181 | * @brief Reloads IWDG counter with value defined in the reload register
182 | * (write access to IWDG_PR and IWDG_RLR registers disabled).
183 | * @param None
184 | * @retval None
185 | */
186 | void IWDG_ReloadCounter(void)
187 | {
188 | IWDG->KR = KR_KEY_RELOAD;
189 | }
190 |
191 |
192 | /**
193 | * @brief Sets the IWDG window value.
194 | * @param WindowValue: specifies the window value to be compared to the downcounter.
195 | * @retval None
196 | */
197 | void IWDG_SetWindowValue(uint16_t WindowValue)
198 | {
199 | /* Check the parameters */
200 | assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
201 | IWDG->WINR = WindowValue;
202 | }
203 |
204 | /**
205 | * @}
206 | */
207 |
208 | /** @defgroup IWDG_Group2 IWDG activation function
209 | * @brief IWDG activation function
210 | *
211 | @verbatim
212 | ===============================================================================
213 | ##### IWDG activation function #####
214 | ===============================================================================
215 |
216 | @endverbatim
217 | * @{
218 | */
219 |
220 | /**
221 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
222 | * @param None
223 | * @retval None
224 | */
225 | void IWDG_Enable(void)
226 | {
227 | IWDG->KR = KR_KEY_ENABLE;
228 | }
229 |
230 | /**
231 | * @}
232 | */
233 |
234 | /** @defgroup IWDG_Group3 Flag management function
235 | * @brief Flag management function
236 | *
237 | @verbatim
238 | ===============================================================================
239 | ##### Flag management function #####
240 | ===============================================================================
241 |
242 | @endverbatim
243 | * @{
244 | */
245 |
246 | /**
247 | * @brief Checks whether the specified IWDG flag is set or not.
248 | * @param IWDG_FLAG: specifies the flag to check.
249 | * This parameter can be one of the following values:
250 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
251 | * @arg IWDG_FLAG_RVU: Reload Value Update on going
252 | * @arg IWDG_FLAG_WVU: Counter Window Value Update on going
253 | * @retval The new state of IWDG_FLAG (SET or RESET).
254 | */
255 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
256 | {
257 | FlagStatus bitstatus = RESET;
258 | /* Check the parameters */
259 | assert_param(IS_IWDG_FLAG(IWDG_FLAG));
260 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
261 | {
262 | bitstatus = SET;
263 | }
264 | else
265 | {
266 | bitstatus = RESET;
267 | }
268 | /* Return the flag status */
269 | return bitstatus;
270 | }
271 |
272 | /**
273 | * @}
274 | */
275 |
276 | /**
277 | * @}
278 | */
279 |
280 | /**
281 | * @}
282 | */
283 |
284 | /**
285 | * @}
286 | */
287 |
288 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
289 |
--------------------------------------------------------------------------------
/f303_ice5_fw/StdPeriph/stm32f30x_iwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_iwdg.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file contains all the functions prototypes for the IWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2015 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_IWDG_H
31 | #define __STM32F30x_IWDG_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup IWDG
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup IWDG_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup IWDG_WriteAccess
56 | * @{
57 | */
58 |
59 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
60 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
61 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
62 | ((ACCESS) == IWDG_WriteAccess_Disable))
63 | /**
64 | * @}
65 | */
66 |
67 | /** @defgroup IWDG_prescaler
68 | * @{
69 | */
70 |
71 | #define IWDG_Prescaler_4 ((uint8_t)0x00)
72 | #define IWDG_Prescaler_8 ((uint8_t)0x01)
73 | #define IWDG_Prescaler_16 ((uint8_t)0x02)
74 | #define IWDG_Prescaler_32 ((uint8_t)0x03)
75 | #define IWDG_Prescaler_64 ((uint8_t)0x04)
76 | #define IWDG_Prescaler_128 ((uint8_t)0x05)
77 | #define IWDG_Prescaler_256 ((uint8_t)0x06)
78 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
79 | ((PRESCALER) == IWDG_Prescaler_8) || \
80 | ((PRESCALER) == IWDG_Prescaler_16) || \
81 | ((PRESCALER) == IWDG_Prescaler_32) || \
82 | ((PRESCALER) == IWDG_Prescaler_64) || \
83 | ((PRESCALER) == IWDG_Prescaler_128)|| \
84 | ((PRESCALER) == IWDG_Prescaler_256))
85 | /**
86 | * @}
87 | */
88 |
89 | /** @defgroup IWDG_Flag
90 | * @{
91 | */
92 |
93 | #define IWDG_FLAG_PVU ((uint16_t)0x0001)
94 | #define IWDG_FLAG_RVU ((uint16_t)0x0002)
95 | #define IWDG_FLAG_WVU ((uint16_t)0x0002)
96 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
97 | ((FLAG) == IWDG_FLAG_WVU))
98 | /**
99 | * @}
100 | */
101 |
102 | /** @defgroup IWDG_Reload_Value
103 | * @{
104 | */
105 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /** @defgroup IWDG_CounterWindow_Value
112 | * @{
113 | */
114 | #define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
115 | /**
116 | * @}
117 | */
118 |
119 | /**
120 | * @}
121 | */
122 |
123 | /* Exported macro ------------------------------------------------------------*/
124 | /* Exported functions --------------------------------------------------------*/
125 |
126 | /* Prescaler and Counter configuration functions ******************************/
127 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
128 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
129 | void IWDG_SetReload(uint16_t Reload);
130 | void IWDG_ReloadCounter(void);
131 | void IWDG_SetWindowValue(uint16_t WindowValue);
132 |
133 | /* IWDG activation function ***************************************************/
134 | void IWDG_Enable(void);
135 |
136 | /* Flag management function ***************************************************/
137 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
138 |
139 | #ifdef __cplusplus
140 | }
141 | #endif
142 |
143 | #endif /* __STM32F30x_IWDG_H */
144 |
145 | /**
146 | * @}
147 | */
148 |
149 | /**
150 | * @}
151 | */
152 |
153 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
154 |
--------------------------------------------------------------------------------
/f303_ice5_fw/StdPeriph/stm32f30x_misc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_misc.c
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file provides all the miscellaneous firmware functions (add-on
8 | * to CMSIS functions).
9 | *
10 | @verbatim
11 |
12 | ===============================================================================
13 | ##### How to configure Interrupts using driver #####
14 | ===============================================================================
15 | [..] This section provide functions allowing to configure the NVIC interrupts
16 | (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
17 | (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
18 | function according to the following table.
19 | The table below gives the allowed values of the pre-emption priority
20 | and subpriority according to the Priority Grouping configuration
21 | performed by NVIC_PriorityGroupConfig function.
22 |
23 | (#) Enable and Configure the priority of the selected IRQ Channels.
24 | [..]
25 | (@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
26 | the IRQ priority will be managed only by subpriority.
27 | The sub-priority is only used to sort pending exception priorities,
28 | and does not affect active exceptions.
29 | (@) Lower priority values gives higher priority.
30 | (@) Priority Order:
31 | (#@) Lowest Preemption priority.
32 | (#@) Lowest Subpriority.
33 | (#@) Lowest hardware priority (IRQn position).
34 |
35 | @endverbatim
36 |
37 | ******************************************************************************
38 | * @attention
39 | *
40 | * © COPYRIGHT 2015 STMicroelectronics
41 | *
42 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
43 | * You may not use this file except in compliance with the License.
44 | * You may obtain a copy of the License at:
45 | *
46 | * http://www.st.com/software_license_agreement_liberty_v2
47 | *
48 | * Unless required by applicable law or agreed to in writing, software
49 | * distributed under the License is distributed on an "AS IS" BASIS,
50 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
51 | * See the License for the specific language governing permissions and
52 | * limitations under the License.
53 | *
54 | ******************************************************************************
55 | */
56 |
57 | /* Includes ------------------------------------------------------------------*/
58 | #include "stm32f30x_misc.h"
59 |
60 | /** @addtogroup STM32F30x_StdPeriph_Driver
61 | * @{
62 | */
63 |
64 | /** @defgroup MISC
65 | * @brief MISC driver modules
66 | * @{
67 | */
68 |
69 | /* Private typedef -----------------------------------------------------------*/
70 | /* Private define ------------------------------------------------------------*/
71 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
72 |
73 | /* Private macro -------------------------------------------------------------*/
74 | /* Private variables ---------------------------------------------------------*/
75 | /* Private function prototypes -----------------------------------------------*/
76 | /* Private functions ---------------------------------------------------------*/
77 |
78 | /** @defgroup MISC_Private_Functions
79 | * @{
80 | */
81 |
82 | /**
83 | * @brief Configures the priority grouping: pre-emption priority and subpriority.
84 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
85 | * This parameter can be one of the following values:
86 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority.
87 | * 4 bits for subpriority.
88 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority.
89 | * 3 bits for subpriority.
90 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority.
91 | * 2 bits for subpriority.
92 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority.
93 | * 1 bits for subpriority.
94 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority.
95 | * 0 bits for subpriority.
96 | * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
97 | * interrupt. This interrupts priority is managed only with subpriority.
98 | * @retval None
99 | */
100 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
101 | {
102 | /* Check the parameters */
103 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
104 |
105 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
106 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
107 | }
108 |
109 | /**
110 | * @brief Initializes the NVIC peripheral according to the specified
111 | * parameters in the NVIC_InitStruct.
112 | * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
113 | * function should be called before.
114 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
115 | * the configuration information for the specified NVIC peripheral.
116 | * @retval None
117 | */
118 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
119 | {
120 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
121 |
122 | /* Check the parameters */
123 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
124 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
125 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
126 |
127 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
128 | {
129 | /* Compute the Corresponding IRQ Priority --------------------------------*/
130 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
131 | tmppre = (0x4 - tmppriority);
132 | tmpsub = tmpsub >> tmppriority;
133 |
134 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
135 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
136 | tmppriority = tmppriority << 0x04;
137 |
138 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
139 |
140 | /* Enable the Selected IRQ Channels --------------------------------------*/
141 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
142 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
143 | }
144 | else
145 | {
146 | /* Disable the Selected IRQ Channels -------------------------------------*/
147 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
148 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
149 | }
150 | }
151 |
152 | /**
153 | * @brief Sets the vector table location and Offset.
154 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
155 | * This parameter can be one of the following values:
156 | * @arg NVIC_VectTab_RAM
157 | * @arg NVIC_VectTab_FLASH
158 | * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
159 | * @retval None
160 | */
161 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
162 | {
163 | /* Check the parameters */
164 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
165 | assert_param(IS_NVIC_OFFSET(Offset));
166 |
167 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
168 | }
169 |
170 | /**
171 | * @brief Selects the condition for the system to enter low power mode.
172 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
173 | * This parameter can be one of the following values:
174 | * @arg NVIC_LP_SEVONPEND
175 | * @arg NVIC_LP_SLEEPDEEP
176 | * @arg NVIC_LP_SLEEPONEXIT
177 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
178 | * @retval None
179 | */
180 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
181 | {
182 | /* Check the parameters */
183 | assert_param(IS_NVIC_LP(LowPowerMode));
184 | assert_param(IS_FUNCTIONAL_STATE(NewState));
185 |
186 | if (NewState != DISABLE)
187 | {
188 | SCB->SCR |= LowPowerMode;
189 | }
190 | else
191 | {
192 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
193 | }
194 | }
195 |
196 | /**
197 | * @brief Configures the SysTick clock source.
198 | * @param SysTick_CLKSource: specifies the SysTick clock source.
199 | * This parameter can be one of the following values:
200 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
201 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
202 | * @retval None
203 | */
204 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
205 | {
206 | /* Check the parameters */
207 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
208 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
209 | {
210 | SysTick->CTRL |= SysTick_CLKSource_HCLK;
211 | }
212 | else
213 | {
214 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
215 | }
216 | }
217 |
218 | /**
219 | * @}
220 | */
221 |
222 | /**
223 | * @}
224 | */
225 |
226 | /**
227 | * @}
228 | */
229 |
230 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
231 |
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/f303_ice5_fw/StdPeriph/stm32f30x_misc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_misc.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file contains all the functions prototypes for the miscellaneous
8 | * firmware library functions (add-on to CMSIS functions).
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2015 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_MISC_H
31 | #define __STM32F30x_MISC_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup MISC
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief NVIC Init Structure definition
52 | */
53 |
54 | typedef struct
55 | {
56 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
57 | This parameter can be a value of @ref IRQn_Type (For
58 | the complete STM32 Devices IRQ Channels list, please
59 | refer to stm32f30x.h file) */
60 |
61 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
62 | specified in NVIC_IRQChannel. This parameter can be a value
63 | between 0 and 15.
64 | A lower priority value indicates a higher priority */
65 |
66 |
67 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
68 | in NVIC_IRQChannel. This parameter can be a value
69 | between 0 and 15.
70 | A lower priority value indicates a higher priority */
71 |
72 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
73 | will be enabled or disabled.
74 | This parameter can be set either to ENABLE or DISABLE */
75 | } NVIC_InitTypeDef;
76 |
77 | /**
78 | *
79 | @verbatim
80 | The table below gives the allowed values of the pre-emption priority and subpriority according
81 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
82 | ============================================================================================================================
83 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
84 | ============================================================================================================================
85 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
86 | | | | 4 bits for subpriority
87 | ----------------------------------------------------------------------------------------------------------------------------
88 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
89 | | | | 3 bits for subpriority
90 | ----------------------------------------------------------------------------------------------------------------------------
91 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
92 | | | | 2 bits for subpriority
93 | ----------------------------------------------------------------------------------------------------------------------------
94 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
95 | | | | 1 bits for subpriority
96 | ----------------------------------------------------------------------------------------------------------------------------
97 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
98 | | | | 0 bits for subpriority
99 | ============================================================================================================================
100 | @endverbatim
101 | */
102 |
103 | /* Exported constants --------------------------------------------------------*/
104 |
105 | /** @defgroup MISC_Exported_Constants
106 | * @{
107 | */
108 |
109 | /** @defgroup MISC_Vector_Table_Base
110 | * @{
111 | */
112 |
113 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
114 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
115 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
116 | ((VECTTAB) == NVIC_VectTab_FLASH))
117 | /**
118 | * @}
119 | */
120 |
121 | /** @defgroup MISC_System_Low_Power
122 | * @{
123 | */
124 |
125 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
126 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
127 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
128 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
129 | ((LP) == NVIC_LP_SLEEPDEEP) || \
130 | ((LP) == NVIC_LP_SLEEPONEXIT))
131 | /**
132 | * @}
133 | */
134 |
135 | /** @defgroup MISC_Preemption_Priority_Group
136 | * @{
137 | */
138 |
139 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
140 | 4 bits for subpriority */
141 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
142 | 3 bits for subpriority */
143 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
144 | 2 bits for subpriority */
145 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
146 | 1 bits for subpriority */
147 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
148 | 0 bits for subpriority */
149 |
150 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
151 | ((GROUP) == NVIC_PriorityGroup_1) || \
152 | ((GROUP) == NVIC_PriorityGroup_2) || \
153 | ((GROUP) == NVIC_PriorityGroup_3) || \
154 | ((GROUP) == NVIC_PriorityGroup_4))
155 |
156 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
157 |
158 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
159 |
160 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
161 |
162 | /**
163 | * @}
164 | */
165 |
166 | /** @defgroup MISC_SysTick_clock_source
167 | */
168 |
169 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
170 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
171 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
172 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
173 | /**
174 | * @}
175 | */
176 |
177 | /**
178 | * @}
179 | */
180 |
181 | /* Exported macro ------------------------------------------------------------*/
182 | /* Exported functions --------------------------------------------------------*/
183 |
184 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
185 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
186 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
187 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
188 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
189 |
190 | #ifdef __cplusplus
191 | }
192 | #endif
193 |
194 | #endif /* __STM32F30x_MISC_H */
195 |
196 | /**
197 | * @}
198 | */
199 |
200 | /**
201 | * @}
202 | */
203 |
204 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
205 |
--------------------------------------------------------------------------------
/f303_ice5_fw/StdPeriph/stm32f30x_opamp.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_opamp.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file contains all the functions prototypes for the operational
8 | * amplifiers (OPAMP) firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2015 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_OPAMP_H
31 | #define __STM32F30x_OPAMP_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup OPAMP
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief OPAMP Init structure definition
52 | */
53 |
54 | typedef struct
55 | {
56 |
57 | uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier.
58 | This parameter can be a value of @ref OPAMP_InvertingInput */
59 |
60 | uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier.
61 | This parameter can be a value of @ref OPAMP_NonInvertingInput */
62 |
63 | }OPAMP_InitTypeDef;
64 |
65 | /* Exported constants --------------------------------------------------------*/
66 |
67 | /** @defgroup OPAMP_Exported_Constants
68 | * @{
69 | */
70 |
71 | /** @defgroup OPAMP_Selection
72 | * @{
73 | */
74 |
75 | #define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */
76 | #define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */
77 | #define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */
78 | #define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */
79 |
80 | #define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
81 | ((PERIPH) == OPAMP_Selection_OPAMP2) || \
82 | ((PERIPH) == OPAMP_Selection_OPAMP3) || \
83 | ((PERIPH) == OPAMP_Selection_OPAMP4))
84 |
85 | /**
86 | * @}
87 | */
88 |
89 | /** @defgroup OPAMP_InvertingInput
90 | * @{
91 | */
92 |
93 | #define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
94 | connected to OPAMPx inverting input */
95 | #define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
96 | connected to OPAMPx inverting input */
97 | #define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */
98 | #define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */
99 |
100 | #define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \
101 | ((INPUT) == OPAMP_InvertingInput_IO2) || \
102 | ((INPUT) == OPAMP_InvertingInput_PGA) || \
103 | ((INPUT) == OPAMP_InvertingInput_Vout))
104 | /**
105 | * @}
106 | */
107 |
108 | /** @defgroup OPAMP_NonInvertingInput
109 | * @{
110 | */
111 |
112 | #define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
113 | connected to OPAMPx non inverting input */
114 | #define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
115 | connected to OPAMPx non inverting input */
116 | #define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
117 | connected to OPAMPx non inverting input */
118 | #define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
119 | connected to OPAMPx non inverting input */
120 |
121 | #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \
122 | ((INPUT) == OPAMP_NonInvertingInput_IO2) || \
123 | ((INPUT) == OPAMP_NonInvertingInput_IO3) || \
124 | ((INPUT) == OPAMP_NonInvertingInput_IO4))
125 | /**
126 | * @}
127 | */
128 |
129 | /** @defgroup OPAMP_PGAGain_Config
130 | * @{
131 | */
132 |
133 | #define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000)
134 | #define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0
135 | #define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1
136 | #define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000)
137 |
138 | #define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \
139 | ((GAIN) == OPAMP_OPAMP_PGAGain_4) || \
140 | ((GAIN) == OPAMP_OPAMP_PGAGain_8) || \
141 | ((GAIN) == OPAMP_OPAMP_PGAGain_16))
142 | /**
143 | * @}
144 | */
145 |
146 | /** @defgroup OPAMP_PGAConnect_Config
147 | * @{
148 | */
149 |
150 | #define OPAMP_PGAConnect_No ((uint32_t)0x00000000)
151 | #define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3
152 | #define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000)
153 |
154 | #define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \
155 | ((CONNECT) == OPAMP_PGAConnect_IO1) || \
156 | ((CONNECT) == OPAMP_PGAConnect_IO2))
157 | /**
158 | * @}
159 | */
160 |
161 | /** @defgroup OPAMP_SecondaryInvertingInput
162 | * @{
163 | */
164 |
165 | #define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \
166 | ((INVINPUT) == OPAMP_InvertingInput_IO2))
167 | /**
168 | * @}
169 | */
170 |
171 | /** @defgroup OPAMP_Input
172 | * @{
173 | */
174 |
175 | #define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */
176 | #define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */
177 |
178 | #define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \
179 | ((INPUT) == OPAMP_Input_NonInverting))
180 |
181 | /**
182 | * @}
183 | */
184 |
185 | /** @defgroup OPAMP_Vref
186 | * @{
187 | */
188 |
189 | #define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
190 | #define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
191 | #define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
192 | #define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
193 |
194 | #define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \
195 | ((VREF) == OPAMP_Vref_10VDDA) || \
196 | ((VREF) == OPAMP_Vref_50VDDA) || \
197 | ((VREF) == OPAMP_Vref_90VDDA))
198 |
199 | /**
200 | * @}
201 | */
202 |
203 | /** @defgroup OPAMP_Trimming
204 | */
205 |
206 | #define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
207 | #define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */
208 |
209 | #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
210 | ((TRIMMING) == OPAMP_Trimming_User))
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /** @defgroup OPAMP_TrimValue
217 | * @{
218 | */
219 |
220 | #define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
221 |
222 | /**
223 | * @}
224 | */
225 |
226 | /** @defgroup OPAMP_OutputLevel
227 | * @{
228 | */
229 |
230 | #define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL
231 | #define OPAMP_OutputLevel_Low ((uint32_t)0x00000000)
232 |
233 | /**
234 | * @}
235 | */
236 |
237 | /* Exported macro ------------------------------------------------------------*/
238 | /* Exported functions ------------------------------------------------------- */
239 |
240 | /* Function used to set the OPAMP configuration to the default reset state ***/
241 | void OPAMP_DeInit(uint32_t OPAMP_Selection);
242 |
243 | /* Initialization and Configuration functions *********************************/
244 | void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
245 | void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct);
246 | void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect);
247 | void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref);
248 | void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
249 | void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
250 | void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
251 | void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
252 | uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection);
253 |
254 | /* Calibration functions ******************************************************/
255 | void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState);
256 | void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming);
257 | void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
258 | void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState);
259 |
260 | /* OPAMP configuration locking function ***************************************/
261 | void OPAMP_LockConfig(uint32_t OPAMP_Selection);
262 |
263 | #ifdef __cplusplus
264 | }
265 | #endif
266 |
267 | #endif /*__STM32F30x_OPAMP_H */
268 |
269 | /**
270 | * @}
271 | */
272 |
273 | /**
274 | * @}
275 | */
276 |
277 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
278 |
--------------------------------------------------------------------------------
/f303_ice5_fw/StdPeriph/stm32f30x_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_pwr.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file contains all the functions prototypes for the PWR firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2015 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_PWR_H
31 | #define __STM32F30x_PWR_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup PWR
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup PWR_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup PWR_PVD_detection_level
56 | * @{
57 | */
58 |
59 | #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
60 | #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
61 | #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
62 | #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
63 | #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
64 | #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
65 | #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
66 | #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
67 |
68 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
69 | ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
70 | ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
71 | ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
72 | /**
73 | * @}
74 | */
75 |
76 | /** @defgroup PWR_WakeUp_Pins
77 | * @{
78 | */
79 |
80 | #define PWR_WakeUpPin_1 PWR_CSR_EWUP1
81 | #define PWR_WakeUpPin_2 PWR_CSR_EWUP2
82 | #define PWR_WakeUpPin_3 PWR_CSR_EWUP3
83 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
84 | ((PIN) == PWR_WakeUpPin_2) || \
85 | ((PIN) == PWR_WakeUpPin_3))
86 | /**
87 | * @}
88 | */
89 |
90 |
91 | /** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
92 | * @{
93 | */
94 |
95 | #define PWR_Regulator_ON ((uint32_t)0x00000000)
96 | #define PWR_Regulator_LowPower PWR_CR_LPSDSR
97 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
98 | ((REGULATOR) == PWR_Regulator_LowPower))
99 | /**
100 | * @}
101 | */
102 |
103 | /** @defgroup PWR_SLEEP_mode_entry
104 | * @{
105 | */
106 |
107 | #define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
108 | #define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
109 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /** @defgroup PWR_STOP_mode_entry
116 | * @{
117 | */
118 |
119 | #define PWR_STOPEntry_WFI ((uint8_t)0x01)
120 | #define PWR_STOPEntry_WFE ((uint8_t)0x02)
121 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
122 |
123 | /**
124 | * @}
125 | */
126 |
127 | /** @defgroup PWR_Flag
128 | * @{
129 | */
130 |
131 | #define PWR_FLAG_WU PWR_CSR_WUF
132 | #define PWR_FLAG_SB PWR_CSR_SBF
133 | #define PWR_FLAG_PVDO PWR_CSR_PVDO
134 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
135 |
136 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
137 | ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
138 |
139 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
140 | /**
141 | * @}
142 | */
143 |
144 | /**
145 | * @}
146 | */
147 |
148 | /* Exported macro ------------------------------------------------------------*/
149 | /* Exported functions ------------------------------------------------------- */
150 |
151 | /* Function used to set the PWR configuration to the default reset state ******/
152 | void PWR_DeInit(void);
153 |
154 | /* Backup Domain Access function **********************************************/
155 | void PWR_BackupAccessCmd(FunctionalState NewState);
156 |
157 | /* PVD configuration functions ************************************************/
158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
159 | void PWR_PVDCmd(FunctionalState NewState);
160 |
161 | /* WakeUp pins configuration functions ****************************************/
162 | void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
163 |
164 | /* Low Power modes configuration functions ************************************/
165 | void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
166 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
167 | void PWR_EnterSTANDBYMode(void);
168 |
169 | /* Flags management functions *************************************************/
170 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
171 | void PWR_ClearFlag(uint32_t PWR_FLAG);
172 |
173 | #ifdef __cplusplus
174 | }
175 | #endif
176 |
177 | #endif /* __STM32F30x_PWR_H */
178 |
179 | /**
180 | * @}
181 | */
182 |
183 | /**
184 | * @}
185 | */
186 |
187 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
188 |
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/f303_ice5_fw/StdPeriph/stm32f30x_wwdg.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_wwdg.c
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the Window watchdog (WWDG) peripheral:
9 | * + Prescaler, Refresh window and Counter configuration
10 | * + WWDG activation
11 | * + Interrupts and flags management
12 | *
13 | * @verbatim
14 | *
15 | ==============================================================================
16 | ##### WWDG features #####
17 | ==============================================================================
18 |
19 | [..] Once enabled the WWDG generates a system reset on expiry of a programmed
20 | time period, unless the program refreshes the counter (downcounter)
21 | before to reach 0x3F value (i.e. a reset is generated when the counter
22 | value rolls over from 0x40 to 0x3F).
23 | [..] An MCU reset is also generated if the counter value is refreshed
24 | before the counter has reached the refresh window value. This
25 | implies that the counter must be refreshed in a limited window.
26 |
27 | [..] Once enabled the WWDG cannot be disabled except by a system reset.
28 |
29 | [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
30 | reset occurs.
31 |
32 | [..] The WWDG counter input clock is derived from the APB clock divided
33 | by a programmable prescaler.
34 |
35 | [..] WWDG counter clock = PCLK1 / Prescaler.
36 | [..] WWDG timeout = (WWDG counter clock) * (counter value).
37 |
38 | [..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.
39 |
40 | ##### How to use this driver #####
41 | ==============================================================================
42 | [..]
43 | (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
44 | function.
45 |
46 | (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
47 |
48 | (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
49 |
50 | (#) Set the WWDG counter value and start it using WWDG_Enable() function.
51 | When the WWDG is enabled the counter value should be configured to
52 | a value greater than 0x40 to prevent generating an immediate reset.
53 |
54 | (#) Optionally you can enable the Early wakeup interrupt which is
55 | generated when the counter reach 0x40.
56 | Once enabled this interrupt cannot be disabled except by a system reset.
57 |
58 | (#) Then the application program must refresh the WWDG counter at regular
59 | intervals during normal operation to prevent an MCU reset, using
60 | WWDG_SetCounter() function. This operation must occur only when
61 | the counter value is lower than the refresh window value,
62 | programmed using WWDG_SetWindowValue().
63 |
64 | @endverbatim
65 |
66 | ******************************************************************************
67 | * @attention
68 | *
69 | * © COPYRIGHT 2015 STMicroelectronics
70 | *
71 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
72 | * You may not use this file except in compliance with the License.
73 | * You may obtain a copy of the License at:
74 | *
75 | * http://www.st.com/software_license_agreement_liberty_v2
76 | *
77 | * Unless required by applicable law or agreed to in writing, software
78 | * distributed under the License is distributed on an "AS IS" BASIS,
79 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
80 | * See the License for the specific language governing permissions and
81 | * limitations under the License.
82 | *
83 | ******************************************************************************
84 | */
85 |
86 | /* Includes ------------------------------------------------------------------*/
87 | #include "stm32f30x_wwdg.h"
88 | #include "stm32f30x_rcc.h"
89 |
90 | /** @addtogroup STM32F30x_StdPeriph_Driver
91 | * @{
92 | */
93 |
94 | /** @defgroup WWDG
95 | * @brief WWDG driver modules
96 | * @{
97 | */
98 |
99 | /* Private typedef -----------------------------------------------------------*/
100 | /* Private define ------------------------------------------------------------*/
101 | /* --------------------- WWDG registers bit mask ---------------------------- */
102 | /* CFR register bit mask */
103 | #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
104 | #define CFR_W_MASK ((uint32_t)0xFFFFFF80)
105 | #define BIT_MASK ((uint8_t)0x7F)
106 |
107 | /* Private macro -------------------------------------------------------------*/
108 | /* Private variables ---------------------------------------------------------*/
109 | /* Private function prototypes -----------------------------------------------*/
110 | /* Private functions ---------------------------------------------------------*/
111 |
112 | /** @defgroup WWDG_Private_Functions
113 | * @{
114 | */
115 |
116 | /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
117 | * @brief Prescaler, Refresh window and Counter configuration functions
118 | *
119 | @verbatim
120 | ==============================================================================
121 | ##### Prescaler, Refresh window and Counter configuration functions #####
122 | ==============================================================================
123 |
124 | @endverbatim
125 | * @{
126 | */
127 |
128 | /**
129 | * @brief Deinitializes the WWDG peripheral registers to their default reset values.
130 | * @param None
131 | * @retval None
132 | */
133 | void WWDG_DeInit(void)
134 | {
135 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
136 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
137 | }
138 |
139 | /**
140 | * @brief Sets the WWDG Prescaler.
141 | * @param WWDG_Prescaler: specifies the WWDG Prescaler.
142 | * This parameter can be one of the following values:
143 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
144 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
145 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
146 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
147 | * @retval None
148 | */
149 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
150 | {
151 | uint32_t tmpreg = 0;
152 | /* Check the parameters */
153 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
154 | /* Clear WDGTB[1:0] bits */
155 | tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
156 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
157 | tmpreg |= WWDG_Prescaler;
158 | /* Store the new value */
159 | WWDG->CFR = tmpreg;
160 | }
161 |
162 | /**
163 | * @brief Sets the WWDG window value.
164 | * @param WindowValue: specifies the window value to be compared to the downcounter.
165 | * This parameter value must be lower than 0x80.
166 | * @retval None
167 | */
168 | void WWDG_SetWindowValue(uint8_t WindowValue)
169 | {
170 | __IO uint32_t tmpreg = 0;
171 |
172 | /* Check the parameters */
173 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
174 | /* Clear W[6:0] bits */
175 |
176 | tmpreg = WWDG->CFR & CFR_W_MASK;
177 |
178 | /* Set W[6:0] bits according to WindowValue value */
179 | tmpreg |= WindowValue & (uint32_t) BIT_MASK;
180 |
181 | /* Store the new value */
182 | WWDG->CFR = tmpreg;
183 | }
184 |
185 | /**
186 | * @brief Enables the WWDG Early Wakeup interrupt(EWI).
187 | * @note Once enabled this interrupt cannot be disabled except by a system reset.
188 | * @param None
189 | * @retval None
190 | */
191 | void WWDG_EnableIT(void)
192 | {
193 | WWDG->CFR |= WWDG_CFR_EWI;
194 | }
195 |
196 | /**
197 | * @brief Sets the WWDG counter value.
198 | * @param Counter: specifies the watchdog counter value.
199 | * This parameter must be a number between 0x40 and 0x7F (to prevent generating
200 | * an immediate reset).
201 | * @retval None
202 | */
203 | void WWDG_SetCounter(uint8_t Counter)
204 | {
205 | /* Check the parameters */
206 | assert_param(IS_WWDG_COUNTER(Counter));
207 | /* Write to T[6:0] bits to configure the counter value, no need to do
208 | a read-modify-write; writing a 0 to WDGA bit does nothing */
209 | WWDG->CR = Counter & BIT_MASK;
210 | }
211 |
212 | /**
213 | * @}
214 | */
215 |
216 | /** @defgroup WWDG_Group2 WWDG activation functions
217 | * @brief WWDG activation functions
218 | *
219 | @verbatim
220 | ==============================================================================
221 | ##### WWDG activation function #####
222 | ==============================================================================
223 |
224 | @endverbatim
225 | * @{
226 | */
227 |
228 | /**
229 | * @brief Enables WWDG and load the counter value.
230 | * @param Counter: specifies the watchdog counter value.
231 | * This parameter must be a number between 0x40 and 0x7F (to prevent generating
232 | * an immediate reset).
233 | * @retval None
234 | */
235 | void WWDG_Enable(uint8_t Counter)
236 | {
237 | /* Check the parameters */
238 | assert_param(IS_WWDG_COUNTER(Counter));
239 | WWDG->CR = WWDG_CR_WDGA | Counter;
240 | }
241 |
242 | /**
243 | * @}
244 | */
245 |
246 | /** @defgroup WWDG_Group3 Interrupts and flags management functions
247 | * @brief Interrupts and flags management functions
248 | *
249 | @verbatim
250 | ==============================================================================
251 | ##### Interrupts and flags management functions #####
252 | ==============================================================================
253 |
254 | @endverbatim
255 | * @{
256 | */
257 |
258 | /**
259 | * @brief Checks whether the Early Wakeup interrupt flag is set or not.
260 | * @param None
261 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
262 | */
263 | FlagStatus WWDG_GetFlagStatus(void)
264 | {
265 | FlagStatus bitstatus = RESET;
266 |
267 | if ((WWDG->SR) != (uint32_t)RESET)
268 | {
269 | bitstatus = SET;
270 | }
271 | else
272 | {
273 | bitstatus = RESET;
274 | }
275 | return bitstatus;
276 | }
277 |
278 | /**
279 | * @brief Clears Early Wakeup interrupt flag.
280 | * @param None
281 | * @retval None
282 | */
283 | void WWDG_ClearFlag(void)
284 | {
285 | WWDG->SR = (uint32_t)RESET;
286 | }
287 |
288 | /**
289 | * @}
290 | */
291 |
292 | /**
293 | * @}
294 | */
295 |
296 | /**
297 | * @}
298 | */
299 |
300 | /**
301 | * @}
302 | */
303 |
304 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
305 |
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/f303_ice5_fw/StdPeriph/stm32f30x_wwdg.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f30x_wwdg.h
4 | * @author MCD Application Team
5 | * @version V1.2.2
6 | * @date 27-February-2015
7 | * @brief This file contains all the functions prototypes for the WWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2015 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F30x_WWDG_H
31 | #define __STM32F30x_WWDG_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f30x.h"
39 |
40 | /** @addtogroup STM32F30x_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup WWDG
45 | * @{
46 | */
47 | /* Exported types ------------------------------------------------------------*/
48 | /* Exported constants --------------------------------------------------------*/
49 |
50 | /** @defgroup WWDG_Exported_Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup WWDG_Prescaler
55 | * @{
56 | */
57 |
58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
63 | ((PRESCALER) == WWDG_Prescaler_2) || \
64 | ((PRESCALER) == WWDG_Prescaler_4) || \
65 | ((PRESCALER) == WWDG_Prescaler_8))
66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /* Exported macro ------------------------------------------------------------*/
78 | /* Exported functions ------------------------------------------------------- */
79 | /* Function used to set the WWDG configuration to the default reset state ****/
80 | void WWDG_DeInit(void);
81 |
82 | /* Prescaler, Refresh window and Counter configuration functions **************/
83 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
84 | void WWDG_SetWindowValue(uint8_t WindowValue);
85 | void WWDG_EnableIT(void);
86 | void WWDG_SetCounter(uint8_t Counter);
87 |
88 | /* WWDG activation functions **************************************************/
89 | void WWDG_Enable(uint8_t Counter);
90 |
91 | /* Interrupts and flags management functions **********************************/
92 | FlagStatus WWDG_GetFlagStatus(void);
93 | void WWDG_ClearFlag(void);
94 |
95 | #ifdef __cplusplus
96 | }
97 | #endif
98 |
99 | #endif /* __STM32F30x_WWDG_H */
100 |
101 | /**
102 | * @}
103 | */
104 |
105 | /**
106 | * @}
107 | */
108 |
109 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
110 |
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/f303_ice5_fw/bitmap.bin:
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https://raw.githubusercontent.com/emeb/f303_ice5/f89a719ab5ab2dc17449907835ca88a616ade192/f303_ice5_fw/bitmap.bin
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/f303_ice5_fw/cmd.c:
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1 | /*
2 | * cmd.c - Command parsing routines for STM32F303 breakout SPI to ice5 FPGA
3 | * 05-11-16 E. Brombaugh
4 | */
5 | #include "stm32f30x.h"
6 | #include "arm_math.h"
7 | #include
8 | #include
9 | #include
10 | #include
11 | #include "arm_math.h"
12 | #include "usart.h"
13 | #include "cyclesleep.h"
14 | #include "ice5.h"
15 | #include "ff.h"
16 |
17 | #define MAX_ARGS 4
18 |
19 | /* locals we use here */
20 | char cmd_buffer[256];
21 | char *cmd_wptr;
22 | const char *cmd_commands[] =
23 | {
24 | "help",
25 | "spi_read",
26 | "spi_write",
27 | "dir",
28 | "config_file",
29 | ""
30 | };
31 |
32 | /* Fat FS stuff */
33 | FRESULT fres;
34 | FATFS Fatfs, *fs; /* File system object for each logical drive */
35 | FIL File; /* File object */
36 | DIR Dir; /* Directory object */
37 | FILINFO Finfo;
38 |
39 | /* reset buffer & display the prompt */
40 | void cmd_prompt(void)
41 | {
42 | /* reset input buffer */
43 | cmd_wptr = &cmd_buffer[0];
44 |
45 | /* prompt user */
46 | printf("\rCommand>");
47 | }
48 |
49 | /* process command line after */
50 | void cmd_proc(void)
51 | {
52 | char *token, *argv[MAX_ARGS];
53 | int argc, cmd, reg;
54 | unsigned long data;
55 |
56 | /* parse out three tokens: cmd arg arg */
57 | argc = 0;
58 | token = strtok(cmd_buffer, " ");
59 | while(token != NULL && argc < MAX_ARGS)
60 | {
61 | argv[argc++] = token;
62 | token = strtok(NULL, " ");
63 | }
64 |
65 | /* figure out which command it is */
66 | if(argc > 0)
67 | {
68 | cmd = 0;
69 | while(cmd_commands[cmd] != '\0')
70 | {
71 | if(strcmp(argv[0], cmd_commands[cmd])==0)
72 | break;
73 | cmd++;
74 | }
75 |
76 | /* Can we handle this? */
77 | if(cmd_commands[cmd] != '\0')
78 | {
79 | printf("\r\n");
80 |
81 | /* Handle commands */
82 | switch(cmd)
83 | {
84 | case 0: /* Help */
85 | printf("help - this message\r\n");
86 | printf("spi_read - FPGA SPI read reg\r\n");
87 | printf("spi_write - FPGA SPI write reg, data\r\n");
88 | printf("dir - directory of SD card root\r\n");
89 | printf("config_file - Configure FPGA from \r\n");
90 | break;
91 |
92 | case 1: /* spi_read */
93 | if(argc < 2)
94 | printf("spi_read - missing arg(s)\r\n");
95 | else
96 | {
97 | reg = (int)strtoul(argv[1], NULL, 0) & 0x7f;
98 | ICE5_FPGA_Slave_Read(reg, &data);
99 | printf("spi_read: 0x%02X = 0x%08lX\r\n", reg, data);
100 | }
101 | break;
102 |
103 | case 2: /* spi_write */
104 | if(argc < 3)
105 | printf("spi_write - missing arg(s)\r\n");
106 | else
107 | {
108 | reg = (int)strtoul(argv[1], NULL, 0) & 0x7f;
109 | data = strtoul(argv[2], NULL, 0);
110 | ICE5_FPGA_Slave_Write(reg, data);
111 | printf("spi_write: 0x%02X 0x%08lX\r\n", reg, data);
112 | }
113 | break;
114 |
115 | case 3: /* dir */
116 | /* Open the root directory */
117 | fres = f_opendir(&Dir, "\\");
118 | printf("opened directory /: 0x%x\n", fres);
119 |
120 | if(fres == 0)
121 | {
122 | /* dump top-level directory */
123 | int32_t p1 = 0;
124 | uint32_t s1 = 0, s2 = 0;
125 | for(;;) {
126 | fres = f_readdir(&Dir, &Finfo);
127 | if ((fres != FR_OK) || !Finfo.fname[0]) break;
128 | if (Finfo.fattrib & AM_DIR) {
129 | s2++;
130 | } else {
131 | s1++; p1 += Finfo.fsize;
132 | }
133 | printf("%c%c%c%c%c %u/%02u/%02u %02u:%02u %9lu %s\n",
134 | (Finfo.fattrib & AM_DIR) ? 'D' : '-',
135 | (Finfo.fattrib & AM_RDO) ? 'R' : '-',
136 | (Finfo.fattrib & AM_HID) ? 'H' : '-',
137 | (Finfo.fattrib & AM_SYS) ? 'S' : '-',
138 | (Finfo.fattrib & AM_ARC) ? 'A' : '-',
139 | (Finfo.fdate >> 9) + 1980,
140 | (Finfo.fdate >> 5) & 15,
141 | Finfo.fdate & 31,
142 | (Finfo.ftime >> 11),
143 | (Finfo.ftime >> 5) & 63,
144 | Finfo.fsize,
145 | &(Finfo.fname[0]));
146 | }
147 | printf("%4u File(s),%10lu bytes total\n%4u Dir(s)\n",
148 | (unsigned int)s1, p1, (unsigned int)s2);
149 | //if (f_getfree("\\", (DWORD*)&p1, &fs) == FR_OK)
150 | // printf(", %10lu bytes free\n", p1 * fs->csize * 512);
151 | }
152 | break;
153 |
154 | case 4: /* config_file */
155 | if(argc < 2)
156 | printf("config_file - missing filename argument\r\n");
157 | else
158 | {
159 | /* try to open the file */
160 | fres = f_open(&File, argv[1], FA_READ);
161 | if(!fres)
162 | {
163 | /* try to configure FPGA */
164 | uint8_t result = ICE5_FPGA_Config_File(&File);
165 |
166 | if(result)
167 | printf("config_file - ICE5_FPGA_Config_File returned %d\r\n", result);
168 | }
169 | else
170 | {
171 | printf("config_file - can't open file %s\r\n", argv[1]);
172 | }
173 | }
174 | break;
175 |
176 | default: /* shouldn't get here */
177 | break;
178 | }
179 | }
180 | else
181 | printf("Unknown command\r\n");
182 | }
183 | }
184 |
185 | void init_cmd(void)
186 | {
187 | /* mount the SD card */
188 | fres = f_mount(0, &Fatfs);
189 | printf("mounted drive 0: %x\n", fres);
190 |
191 | /* prompt */
192 | cmd_prompt();
193 | }
194 |
195 | void cmd_parse(char ch)
196 | {
197 | /* accumulate chars until cr, handle backspace */
198 | if(ch == '\b')
199 | {
200 | /* check for buffer underflow */
201 | if(cmd_wptr - &cmd_buffer[0] > 0)
202 | {
203 | printf("\b \b"); /* Erase & backspace */
204 | cmd_wptr--; /* remove previous char */
205 | }
206 | }
207 | else if(ch == '\r')
208 | {
209 | *cmd_wptr = '\0'; /* null terminate, no inc */
210 | cmd_proc();
211 | cmd_prompt();
212 | }
213 | else
214 | {
215 | /* check for buffer full (leave room for null) */
216 | if(cmd_wptr - &cmd_buffer[0] < 254)
217 | {
218 | *cmd_wptr++ = ch; /* store to buffer */
219 | putc(ch, stdout); /* echo */
220 | }
221 | }
222 | fflush(stdout);
223 | }
224 |
--------------------------------------------------------------------------------
/f303_ice5_fw/cmd.h:
--------------------------------------------------------------------------------
1 | /*
2 | * cmd.h - Command parsing routines for STM32F303 breakout SPI to ice5 FPGA
3 | * 05-11-16 E. Brombaugh
4 | */
5 |
6 | #ifndef __cmd__
7 | #define __cmd__
8 |
9 | extern void init_cmd(void);
10 | extern void cmd_parse(char ch);
11 |
12 | #endif
13 |
--------------------------------------------------------------------------------
/f303_ice5_fw/cyclesleep.c:
--------------------------------------------------------------------------------
1 | /*
2 | * cyclesleep.c - zyp's cycle counter sleep routines
3 | * 12-20-12 E. Brombaugh
4 | */
5 |
6 | #include "cyclesleep.h"
7 |
8 | volatile uint32_t* demcr = (uint32_t*)0xE000EDFC;
9 | volatile uint32_t* dwt_ctrl = (uint32_t*)0xe0001000;
10 | volatile uint32_t* dwt_cyccnt = (uint32_t*)0xe0001004;
11 | uint32_t DelayCyc1s;
12 |
13 | /* get sysclock freq */
14 | uint32_t get_sysclk(void)
15 | {
16 | RCC_ClocksTypeDef RCC_Clocks;
17 |
18 | /* Compute Delay amount */
19 | RCC_GetClocksFreq(&RCC_Clocks);
20 | return RCC_Clocks.SYSCLK_Frequency;
21 | }
22 |
23 | // turn on cycle counter
24 | void cyccnt_enable()
25 | {
26 | *demcr |= (1<<24);
27 | *dwt_ctrl |= 1;
28 | DelayCyc1s = get_sysclk();
29 | }
30 |
31 | uint32_t cyclegoal(uint32_t cycles)
32 | {
33 | return cycles + *dwt_cyccnt;
34 | }
35 |
36 | uint32_t cyclegoal_ms(uint32_t ms)
37 | {
38 | return ms*(DelayCyc1s/1000) + *dwt_cyccnt;
39 | }
40 |
41 | uint32_t cyclecheck(uint32_t goal)
42 | {
43 | return *dwt_cyccnt < goal;
44 | }
45 |
46 | // sleep for a certain number of cycles
47 | void cyclesleep(uint32_t cycles)
48 | {
49 | uint32_t goal = cyclegoal(cycles);
50 |
51 | while(cyclecheck(goal));
52 | }
53 |
54 | // sleep for a certain number of milliseconds
55 | void delay(uint32_t ms)
56 | {
57 | cyclesleep(ms*(DelayCyc1s/1000));
58 | }
59 |
--------------------------------------------------------------------------------
/f303_ice5_fw/cyclesleep.h:
--------------------------------------------------------------------------------
1 | /*
2 | * cyclesleep.h - zyp's cycle counter sleep routines
3 | * 12-20-12 E. Brombaugh
4 | */
5 |
6 | #ifndef __cyclesleep__
7 | #define __cyclesleep__
8 |
9 | #include "stm32f30x.h"
10 |
11 | #define CYCLES_PER_SEC 0x044aa200
12 |
13 | void cyccnt_enable();
14 | void cyclesleep(uint32_t cycles);
15 | uint32_t cyclegoal(uint32_t cycles);
16 | uint32_t cyclegoal_ms(uint32_t ms);
17 | uint32_t cyclecheck(uint32_t goal);
18 | void delay(uint32_t ms);
19 |
20 | #endif
21 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ff9a/00readme.txt:
--------------------------------------------------------------------------------
1 | FatFs Module Source Files R0.09a (C)ChaN, 2012
2 |
3 |
4 | FILES
5 |
6 | ffconf.h Configuration file for FatFs module.
7 | ff.h Common include file for FatFs and application module.
8 | ff.c FatFs module.
9 | diskio.h Common include file for FatFs and disk I/O module.
10 | diskio.c An example of glue function to attach existing disk I/O module to FatFs.
11 | integer.h Integer type definitions for FatFs.
12 | option Optional external functions.
13 |
14 | Low level disk I/O module is not included in this archive because the FatFs
15 | module is only a generic file system layer and not depend on any specific
16 | storage device. You have to provide a low level disk I/O module that written
17 | to control your storage device.
18 |
19 |
20 |
21 | AGREEMENTS
22 |
23 | FatFs module is an open source software to implement FAT file system to
24 | small embedded systems. This is a free software and is opened for education,
25 | research and commercial developments under license policy of following trems.
26 |
27 | Copyright (C) 2012, ChaN, all right reserved.
28 |
29 | * The FatFs module is a free software and there is NO WARRANTY.
30 | * No restriction on use. You can use, modify and redistribute it for
31 | personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
32 | * Redistributions of source code must retain the above copyright notice.
33 |
34 |
35 |
36 | REVISION HISTORY
37 |
38 | Feb 26, 2006 R0.00 Prototype
39 |
40 | Apr 29, 2006 R0.01 First release.
41 |
42 | Jun 01, 2006 R0.02 Added FAT12.
43 | Removed unbuffered mode.
44 | Fixed a problem on small (<32M) patition.
45 |
46 | Jun 10, 2006 R0.02a Added a configuration option _FS_MINIMUM.
47 |
48 | Sep 22, 2006 R0.03 Added f_rename.
49 | Changed option _FS_MINIMUM to _FS_MINIMIZE.
50 |
51 | Dec 11, 2006 R0.03a Improved cluster scan algolithm to write files fast.
52 | Fixed f_mkdir creates incorrect directory on FAT32.
53 |
54 | Feb 04, 2007 R0.04 Supported multiple drive system. (FatFs)
55 | Changed some APIs for multiple drive system.
56 | Added f_mkfs. (FatFs)
57 | Added _USE_FAT32 option. (Tiny-FatFs)
58 |
59 | Apr 01, 2007 R0.04a Supported multiple partitions on a plysical drive. (FatFs)
60 | Fixed an endian sensitive code in f_mkfs. (FatFs)
61 | Added a capability of extending the file size to f_lseek.
62 | Added minimization level 3.
63 | Fixed a problem that can collapse a sector when recreate an
64 | existing file in any sub-directory at non FAT32 cfg. (Tiny-FatFs)
65 |
66 | May 05, 2007 R0.04b Added _USE_NTFLAG option.
67 | Added FSInfo support.
68 | Fixed some problems corresponds to FAT32. (Tiny-FatFs)
69 | Fixed DBCS name can result FR_INVALID_NAME.
70 | Fixed short seek (0 < ofs <= csize) collapses the file object.
71 |
72 | Aug 25, 2007 R0.05 Changed arguments of f_read, f_write.
73 | Changed arguments of f_mkfs. (FatFs)
74 | Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs)
75 | Fixed f_mkdir on FAT32 creates incorrect directory. (FatFs)
76 |
77 | Feb 03, 2008 R0.05a Added f_truncate().
78 | Added f_utime().
79 | Fixed off by one error at FAT sub-type determination.
80 | Fixed btr in f_read() can be mistruncated.
81 | Fixed cached sector is not flushed when create and close without write.
82 |
83 | Apr 01, 2008 R0.06 Added f_forward(). (Tiny-FatFs)
84 | Added string functions: fputc(), fputs(), fprintf() and fgets().
85 | Improved performance of f_lseek() on move to the same or following cluster.
86 |
87 | Apr 01, 2009, R0.07 Merged Tiny-FatFs as a buffer configuration option.
88 | Added long file name support.
89 | Added multiple code page support.
90 | Added re-entrancy for multitask operation.
91 | Added auto cluster size selection to f_mkfs().
92 | Added rewind option to f_readdir().
93 | Changed result code of critical errors.
94 | Renamed string functions to avoid name collision.
95 |
96 | Apr 14, 2009, R0.07a Separated out OS dependent code on reentrant cfg.
97 | Added multiple sector size support.
98 |
99 | Jun 21, 2009, R0.07c Fixed f_unlink() may return FR_OK on error.
100 | Fixed wrong cache control in f_lseek().
101 | Added relative path feature.
102 | Added f_chdir().
103 | Added f_chdrive().
104 | Added proper case conversion for extended characters.
105 |
106 | Nov 03, 2009 R0.07e Separated out configuration options from ff.h to ffconf.h.
107 | Added a configuration option, _LFN_UNICODE.
108 | Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
109 | Fixed name matching error on the 13 char boundary.
110 | Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
111 |
112 | May 15, 2010, R0.08 Added a memory configuration option. (_USE_LFN)
113 | Added file lock feature. (_FS_SHARE)
114 | Added fast seek feature. (_USE_FASTSEEK)
115 | Changed some types on the API, XCHAR->TCHAR.
116 | Changed fname member in the FILINFO structure on Unicode cfg.
117 | String functions support UTF-8 encoding files on Unicode cfg.
118 |
119 | Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2)
120 | Added sector erase feature. (_USE_ERASE)
121 | Moved file lock semaphore table from fs object to the bss.
122 | Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
123 | Fixed f_mkfs() creates wrong FAT32 volume.
124 |
125 | Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write().
126 | f_lseek() reports required table size on creating CLMP.
127 | Extended format syntax of f_printf function.
128 | Ignores duplicated directory separators in given path names.
129 |
130 | Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature.
131 | Added f_fdisk(). (_MULTI_PARTITION = 2)
132 |
133 | Aug 27,'12 R0.09a Fixed assertion failure due to OS/2 EA on FAT12/16.
134 | Changed f_open() and f_opendir() reject null object pointer to avoid crash.
135 | Changed option name _FS_SHARE to _FS_LOCK.
136 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ff9a/diskio.h:
--------------------------------------------------------------------------------
1 | /*-----------------------------------------------------------------------
2 | / Low level disk interface modlue include file (C)ChaN, 2012
3 | /-----------------------------------------------------------------------*/
4 |
5 | #ifndef _DISKIO_DEFINED
6 | #define _DISKIO_DEFINED
7 |
8 | #ifdef __cplusplus
9 | extern "C" {
10 | #endif
11 |
12 | #define _USE_WRITE 1 /* 1: Enable disk_write function */
13 | #define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */
14 |
15 | #include "integer.h"
16 |
17 |
18 | /* Status of Disk Functions */
19 | typedef BYTE DSTATUS;
20 |
21 | /* Results of Disk Functions */
22 | typedef enum {
23 | RES_OK = 0, /* 0: Successful */
24 | RES_ERROR, /* 1: R/W Error */
25 | RES_WRPRT, /* 2: Write Protected */
26 | RES_NOTRDY, /* 3: Not Ready */
27 | RES_PARERR /* 4: Invalid Parameter */
28 | } DRESULT;
29 |
30 |
31 | /*---------------------------------------*/
32 | /* Prototypes for disk control functions */
33 |
34 |
35 | DSTATUS disk_initialize (BYTE);
36 | DSTATUS disk_status (BYTE);
37 | DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
38 | DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
39 | DRESULT disk_ioctl (BYTE, BYTE, void*);
40 |
41 |
42 | /* Disk Status Bits (DSTATUS) */
43 | #define STA_NOINIT 0x01 /* Drive not initialized */
44 | #define STA_NODISK 0x02 /* No medium in the drive */
45 | #define STA_PROTECT 0x04 /* Write protected */
46 |
47 |
48 | /* Command code for disk_ioctrl fucntion */
49 |
50 | /* Generic command (used by FatFs) */
51 | #define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
52 | #define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
53 | #define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
54 | #define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
55 | #define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */
56 |
57 | /* Generic command (not used by FatFs) */
58 | #define CTRL_POWER 5 /* Get/Set power status */
59 | #define CTRL_LOCK 6 /* Lock/Unlock media removal */
60 | #define CTRL_EJECT 7 /* Eject media */
61 | #define CTRL_FORMAT 8 /* Create physical format on the media */
62 |
63 | /* MMC/SDC specific ioctl command */
64 | #define MMC_GET_TYPE 10 /* Get card type */
65 | #define MMC_GET_CSD 11 /* Get CSD */
66 | #define MMC_GET_CID 12 /* Get CID */
67 | #define MMC_GET_OCR 13 /* Get OCR */
68 | #define MMC_GET_SDSTAT 14 /* Get SD status */
69 |
70 | /* ATA/CF specific ioctl command */
71 | #define ATA_GET_REV 20 /* Get F/W revision */
72 | #define ATA_GET_MODEL 21 /* Get model name */
73 | #define ATA_GET_SN 22 /* Get serial number */
74 |
75 |
76 | /* MMC card type flags (MMC_GET_TYPE) */
77 | #define CT_MMC 0x01 /* MMC ver 3 */
78 | #define CT_SD1 0x02 /* SD ver 1 */
79 | #define CT_SD2 0x04 /* SD ver 2 */
80 | #define CT_SDC (CT_SD1|CT_SD2) /* SD */
81 | #define CT_BLOCK 0x08 /* Block addressing */
82 |
83 |
84 | #ifdef __cplusplus
85 | }
86 | #endif
87 |
88 | #endif
89 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ff9a/ff.h:
--------------------------------------------------------------------------------
1 | /*---------------------------------------------------------------------------/
2 | / FatFs - FAT file system module include file R0.09a (C)ChaN, 2012
3 | /----------------------------------------------------------------------------/
4 | / FatFs module is a generic FAT file system module for small embedded systems.
5 | / This is a free software that opened for education, research and commercial
6 | / developments under license policy of following terms.
7 | /
8 | / Copyright (C) 2012, ChaN, all right reserved.
9 | /
10 | / * The FatFs module is a free software and there is NO WARRANTY.
11 | / * No restriction on use. You can use, modify and redistribute it for
12 | / personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
13 | / * Redistributions of source code must retain the above copyright notice.
14 | /
15 | /----------------------------------------------------------------------------*/
16 |
17 | #ifndef _FATFS
18 | #define _FATFS 4004 /* Revision ID */
19 |
20 | #ifdef __cplusplus
21 | extern "C" {
22 | #endif
23 |
24 | #include "integer.h" /* Basic integer types */
25 | #include "ffconf.h" /* FatFs configuration options */
26 |
27 | #if _FATFS != _FFCONF
28 | #error Wrong configuration file (ffconf.h).
29 | #endif
30 |
31 |
32 |
33 | /* Definitions of volume management */
34 |
35 | #if _MULTI_PARTITION /* Multiple partition configuration */
36 | typedef struct {
37 | BYTE pd; /* Physical drive number */
38 | BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
39 | } PARTITION;
40 | extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
41 | #define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */
42 | #define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */
43 |
44 | #else /* Single partition configuration */
45 | #define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */
46 | #define LD2PT(vol) 0 /* Always mounts the 1st partition or in SFD */
47 |
48 | #endif
49 |
50 |
51 |
52 | /* Type of path name strings on FatFs API */
53 |
54 | #if _LFN_UNICODE /* Unicode string */
55 | #if !_USE_LFN
56 | #error _LFN_UNICODE must be 0 in non-LFN cfg.
57 | #endif
58 | #ifndef _INC_TCHAR
59 | typedef WCHAR TCHAR;
60 | #define _T(x) L ## x
61 | #define _TEXT(x) L ## x
62 | #endif
63 |
64 | #else /* ANSI/OEM string */
65 | #ifndef _INC_TCHAR
66 | typedef char TCHAR;
67 | #define _T(x) x
68 | #define _TEXT(x) x
69 | #endif
70 |
71 | #endif
72 |
73 |
74 |
75 | /* File system object structure (FATFS) */
76 |
77 | typedef struct {
78 | BYTE fs_type; /* FAT sub-type (0:Not mounted) */
79 | BYTE drv; /* Physical drive number */
80 | BYTE csize; /* Sectors per cluster (1,2,4...128) */
81 | BYTE n_fats; /* Number of FAT copies (1,2) */
82 | BYTE wflag; /* win[] dirty flag (1:must be written back) */
83 | BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */
84 | WORD id; /* File system mount ID */
85 | WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
86 | #if _MAX_SS != 512
87 | WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */
88 | #endif
89 | #if _FS_REENTRANT
90 | _SYNC_t sobj; /* Identifier of sync object */
91 | #endif
92 | #if !_FS_READONLY
93 | DWORD last_clust; /* Last allocated cluster */
94 | DWORD free_clust; /* Number of free clusters */
95 | DWORD fsi_sector; /* fsinfo sector (FAT32) */
96 | #endif
97 | #if _FS_RPATH
98 | DWORD cdir; /* Current directory start cluster (0:root) */
99 | #endif
100 | DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */
101 | DWORD fsize; /* Sectors per FAT */
102 | DWORD fatbase; /* FAT start sector */
103 | DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */
104 | DWORD database; /* Data start sector */
105 | DWORD winsect; /* Current sector appearing in the win[] */
106 | BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
107 | } FATFS;
108 |
109 |
110 |
111 | /* File object structure (FIL) */
112 |
113 | typedef struct {
114 | FATFS* fs; /* Pointer to the related file system object */
115 | WORD id; /* File system mount ID of the related file system object */
116 | BYTE flag; /* File status flags */
117 | BYTE pad1;
118 | DWORD fptr; /* File read/write pointer (0ed on file open) */
119 | DWORD fsize; /* File size */
120 | DWORD sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */
121 | DWORD clust; /* Current cluster of fpter */
122 | DWORD dsect; /* Current data sector of fpter */
123 | #if !_FS_READONLY
124 | DWORD dir_sect; /* Sector containing the directory entry */
125 | BYTE* dir_ptr; /* Pointer to the directory entry in the window */
126 | #endif
127 | #if _USE_FASTSEEK
128 | DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */
129 | #endif
130 | #if _FS_LOCK
131 | UINT lockid; /* File lock ID (index of file semaphore table Files[]) */
132 | #endif
133 | #if !_FS_TINY
134 | BYTE buf[_MAX_SS]; /* File data read/write buffer */
135 | #endif
136 | } FIL;
137 |
138 |
139 |
140 | /* Directory object structure (DIR) */
141 |
142 | typedef struct {
143 | FATFS* fs; /* Pointer to the owner file system object */
144 | WORD id; /* Owner file system mount ID */
145 | WORD index; /* Current read/write index number */
146 | DWORD sclust; /* Table start cluster (0:Root dir) */
147 | DWORD clust; /* Current cluster */
148 | DWORD sect; /* Current sector */
149 | BYTE* dir; /* Pointer to the current SFN entry in the win[] */
150 | BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
151 | #if _USE_LFN
152 | WCHAR* lfn; /* Pointer to the LFN working buffer */
153 | WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
154 | #endif
155 | } DIR;
156 |
157 |
158 |
159 | /* File status structure (FILINFO) */
160 |
161 | typedef struct {
162 | DWORD fsize; /* File size */
163 | WORD fdate; /* Last modified date */
164 | WORD ftime; /* Last modified time */
165 | BYTE fattrib; /* Attribute */
166 | TCHAR fname[13]; /* Short file name (8.3 format) */
167 | #if _USE_LFN
168 | TCHAR* lfname; /* Pointer to the LFN buffer */
169 | UINT lfsize; /* Size of LFN buffer in TCHAR */
170 | #endif
171 | } FILINFO;
172 |
173 |
174 |
175 | /* File function return code (FRESULT) */
176 |
177 | typedef enum {
178 | FR_OK = 0, /* (0) Succeeded */
179 | FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
180 | FR_INT_ERR, /* (2) Assertion failed */
181 | FR_NOT_READY, /* (3) The physical drive cannot work */
182 | FR_NO_FILE, /* (4) Could not find the file */
183 | FR_NO_PATH, /* (5) Could not find the path */
184 | FR_INVALID_NAME, /* (6) The path name format is invalid */
185 | FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
186 | FR_EXIST, /* (8) Access denied due to prohibited access */
187 | FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
188 | FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
189 | FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
190 | FR_NOT_ENABLED, /* (12) The volume has no work area */
191 | FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
192 | FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
193 | FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
194 | FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
195 | FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
196 | FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */
197 | FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
198 | } FRESULT;
199 |
200 |
201 |
202 | /*--------------------------------------------------------------*/
203 | /* FatFs module application interface */
204 |
205 | FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */
206 | FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */
207 | FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */
208 | FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */
209 | FRESULT f_close (FIL*); /* Close an open file object */
210 | FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */
211 | FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */
212 | FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */
213 | FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */
214 | FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */
215 | FRESULT f_truncate (FIL*); /* Truncate file */
216 | FRESULT f_sync (FIL*); /* Flush cached data of a writing file */
217 | FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */
218 | FRESULT f_mkdir (const TCHAR*); /* Create a new directory */
219 | FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attribute of the file/dir */
220 | FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change times-tamp of the file/dir */
221 | FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */
222 | FRESULT f_chdrive (BYTE); /* Change current drive */
223 | FRESULT f_chdir (const TCHAR*); /* Change current directory */
224 | FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */
225 | FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */
226 | FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */
227 | FRESULT f_fdisk (BYTE, const DWORD[], void*); /* Divide a physical drive into some partitions */
228 | int f_putc (TCHAR, FIL*); /* Put a character to the file */
229 | int f_puts (const TCHAR*, FIL*); /* Put a string to the file */
230 | int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */
231 | TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */
232 |
233 | #define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
234 | #define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
235 | #define f_tell(fp) ((fp)->fptr)
236 | #define f_size(fp) ((fp)->fsize)
237 |
238 | #ifndef EOF
239 | #define EOF (-1)
240 | #endif
241 |
242 |
243 |
244 |
245 | /*--------------------------------------------------------------*/
246 | /* Additional user defined functions */
247 |
248 | /* RTC function */
249 | #if !_FS_READONLY
250 | DWORD get_fattime (void);
251 | #endif
252 |
253 | /* Unicode support functions */
254 | #if _USE_LFN /* Unicode - OEM code conversion */
255 | WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */
256 | WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */
257 | #if _USE_LFN == 3 /* Memory functions */
258 | void* ff_memalloc (UINT); /* Allocate memory block */
259 | void ff_memfree (void*); /* Free memory block */
260 | #endif
261 | #endif
262 |
263 | /* Sync functions */
264 | #if _FS_REENTRANT
265 | int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */
266 | int ff_req_grant (_SYNC_t); /* Lock sync object */
267 | void ff_rel_grant (_SYNC_t); /* Unlock sync object */
268 | int ff_del_syncobj (_SYNC_t); /* Delete a sync object */
269 | #endif
270 |
271 |
272 |
273 |
274 | /*--------------------------------------------------------------*/
275 | /* Flags and offset address */
276 |
277 |
278 | /* File access control and file status flags (FIL.flag) */
279 |
280 | #define FA_READ 0x01
281 | #define FA_OPEN_EXISTING 0x00
282 | #define FA__ERROR 0x80
283 |
284 | #if !_FS_READONLY
285 | #define FA_WRITE 0x02
286 | #define FA_CREATE_NEW 0x04
287 | #define FA_CREATE_ALWAYS 0x08
288 | #define FA_OPEN_ALWAYS 0x10
289 | #define FA__WRITTEN 0x20
290 | #define FA__DIRTY 0x40
291 | #endif
292 |
293 |
294 | /* FAT sub type (FATFS.fs_type) */
295 |
296 | #define FS_FAT12 1
297 | #define FS_FAT16 2
298 | #define FS_FAT32 3
299 |
300 |
301 | /* File attribute bits for directory entry */
302 |
303 | #define AM_RDO 0x01 /* Read only */
304 | #define AM_HID 0x02 /* Hidden */
305 | #define AM_SYS 0x04 /* System */
306 | #define AM_VOL 0x08 /* Volume label */
307 | #define AM_LFN 0x0F /* LFN entry */
308 | #define AM_DIR 0x10 /* Directory */
309 | #define AM_ARC 0x20 /* Archive */
310 | #define AM_MASK 0x3F /* Mask of defined bits */
311 |
312 |
313 | /* Fast seek feature */
314 | #define CREATE_LINKMAP 0xFFFFFFFF
315 |
316 |
317 |
318 | /*--------------------------------*/
319 | /* Multi-byte word access macros */
320 |
321 | #if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
322 | #define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr))
323 | #define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr))
324 | #define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val)
325 | #define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
326 | #else /* Use byte-by-byte access to the FAT structure */
327 | #define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
328 | #define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
329 | #define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
330 | #define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
331 | #endif
332 |
333 | #ifdef __cplusplus
334 | }
335 | #endif
336 |
337 | #endif /* _FATFS */
338 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ff9a/ffconf.h:
--------------------------------------------------------------------------------
1 | /*---------------------------------------------------------------------------/
2 | / FatFs - FAT file system module configuration file R0.09a (C)ChaN, 2012
3 | /----------------------------------------------------------------------------/
4 | /
5 | / CAUTION! Do not forget to make clean the project after any changes to
6 | / the configuration options.
7 | /
8 | /----------------------------------------------------------------------------*/
9 | #ifndef _FFCONF
10 | #define _FFCONF 4004 /* Revision ID */
11 |
12 |
13 | /*---------------------------------------------------------------------------/
14 | / Functions and Buffer Configurations
15 | /----------------------------------------------------------------------------*/
16 |
17 | #define _FS_TINY 0 /* 0:Normal or 1:Tiny */
18 | /* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
19 | / object instead of the sector buffer in the individual file object for file
20 | / data transfer. This reduces memory consumption 512 bytes each file object. */
21 |
22 |
23 | #define _FS_READONLY 1 /* 0:Read/Write or 1:Read only */
24 | /* Setting _FS_READONLY to 1 defines read only configuration. This removes
25 | / writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
26 | / f_truncate and useless f_getfree. */
27 |
28 |
29 | #define _FS_MINIMIZE 1 /* 0 to 3 */
30 | /* The _FS_MINIMIZE option defines minimization level to remove some functions.
31 | /
32 | / 0: Full function.
33 | / 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
34 | / are removed.
35 | / 2: f_opendir and f_readdir are removed in addition to 1.
36 | / 3: f_lseek is removed in addition to 2. */
37 |
38 |
39 | #define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */
40 | /* To enable string functions, set _USE_STRFUNC to 1 or 2. */
41 |
42 |
43 | #define _USE_MKFS 0 /* 0:Disable or 1:Enable */
44 | /* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
45 |
46 |
47 | #define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
48 | /* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
49 |
50 |
51 | #define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
52 | /* To enable fast seek feature, set _USE_FASTSEEK to 1. */
53 |
54 |
55 |
56 | /*---------------------------------------------------------------------------/
57 | / Locale and Namespace Configurations
58 | /----------------------------------------------------------------------------*/
59 |
60 | #define _CODE_PAGE 1
61 | /* The _CODE_PAGE specifies the OEM code page to be used on the target system.
62 | / Incorrect setting of the code page can cause a file open failure.
63 | /
64 | / 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
65 | / 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
66 | / 949 - Korean (DBCS, OEM, Windows)
67 | / 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
68 | / 1250 - Central Europe (Windows)
69 | / 1251 - Cyrillic (Windows)
70 | / 1252 - Latin 1 (Windows)
71 | / 1253 - Greek (Windows)
72 | / 1254 - Turkish (Windows)
73 | / 1255 - Hebrew (Windows)
74 | / 1256 - Arabic (Windows)
75 | / 1257 - Baltic (Windows)
76 | / 1258 - Vietnam (OEM, Windows)
77 | / 437 - U.S. (OEM)
78 | / 720 - Arabic (OEM)
79 | / 737 - Greek (OEM)
80 | / 775 - Baltic (OEM)
81 | / 850 - Multilingual Latin 1 (OEM)
82 | / 858 - Multilingual Latin 1 + Euro (OEM)
83 | / 852 - Latin 2 (OEM)
84 | / 855 - Cyrillic (OEM)
85 | / 866 - Russian (OEM)
86 | / 857 - Turkish (OEM)
87 | / 862 - Hebrew (OEM)
88 | / 874 - Thai (OEM, Windows)
89 | / 1 - ASCII only (Valid for non LFN cfg.)
90 | */
91 |
92 |
93 | #define _USE_LFN 0 /* 0 to 3 */
94 | #define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
95 | /* The _USE_LFN option switches the LFN support.
96 | /
97 | / 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
98 | / 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
99 | / 2: Enable LFN with dynamic working buffer on the STACK.
100 | / 3: Enable LFN with dynamic working buffer on the HEAP.
101 | /
102 | / The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
103 | / Unicode handling functions ff_convert() and ff_wtoupper() must be added
104 | / to the project. When enable to use heap, memory control functions
105 | / ff_memalloc() and ff_memfree() must be added to the project. */
106 |
107 |
108 | #define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
109 | /* To switch the character code set on FatFs API to Unicode,
110 | / enable LFN feature and set _LFN_UNICODE to 1. */
111 |
112 |
113 | #define _FS_RPATH 0 /* 0 to 2 */
114 | /* The _FS_RPATH option configures relative path feature.
115 | /
116 | / 0: Disable relative path feature and remove related functions.
117 | / 1: Enable relative path. f_chdrive() and f_chdir() are available.
118 | / 2: f_getcwd() is available in addition to 1.
119 | /
120 | / Note that output of the f_readdir fnction is affected by this option. */
121 |
122 |
123 |
124 | /*---------------------------------------------------------------------------/
125 | / Physical Drive Configurations
126 | /----------------------------------------------------------------------------*/
127 |
128 | #define _VOLUMES 1
129 | /* Number of volumes (logical drives) to be used. */
130 |
131 |
132 | #define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
133 | /* Maximum sector size to be handled.
134 | / Always set 512 for memory card and hard disk but a larger value may be
135 | / required for on-board flash memory, floppy disk and optical disk.
136 | / When _MAX_SS is larger than 512, it configures FatFs to variable sector size
137 | / and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
138 |
139 |
140 | #define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */
141 | /* When set to 0, each volume is bound to the same physical drive number and
142 | / it can mount only first primaly partition. When it is set to 1, each volume
143 | / is tied to the partitions listed in VolToPart[]. */
144 |
145 |
146 | #define _USE_ERASE 0 /* 0:Disable or 1:Enable */
147 | /* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
148 | / should be added to the disk_ioctl functio. */
149 |
150 |
151 |
152 | /*---------------------------------------------------------------------------/
153 | / System Configurations
154 | /----------------------------------------------------------------------------*/
155 |
156 | #define _WORD_ACCESS 0 /* 0 or 1 */
157 | /* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
158 | / option defines which access method is used to the word data on the FAT volume.
159 | /
160 | / 0: Byte-by-byte access.
161 | / 1: Word access. Do not choose this unless following condition is met.
162 | /
163 | / When the byte order on the memory is big-endian or address miss-aligned word
164 | / access results incorrect behavior, the _WORD_ACCESS must be set to 0.
165 | / If it is not the case, the value can also be set to 1 to improve the
166 | / performance and code size.
167 | */
168 |
169 |
170 | /* A header file that defines sync object types on the O/S, such as
171 | / windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
172 |
173 | #define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
174 | #define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
175 | #define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
176 |
177 | /* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
178 | /
179 | / 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
180 | / 1: Enable reentrancy. Also user provided synchronization handlers,
181 | / ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
182 | / function must be added to the project. */
183 |
184 |
185 | #define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
186 | /* To enable file lock control feature, set _FS_LOCK to 1 or greater.
187 | The value defines how many files can be opened simultaneously. */
188 |
189 |
190 | #endif /* _FFCONFIG */
191 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ff9a/integer.h:
--------------------------------------------------------------------------------
1 | /*-------------------------------------------*/
2 | /* Integer type definitions for FatFs module */
3 | /*-------------------------------------------*/
4 |
5 | #ifndef _INTEGER
6 | #define _INTEGER
7 |
8 | #ifdef _WIN32 /* FatFs development platform */
9 |
10 | #include
11 | #include
12 |
13 | #else /* Embedded platform */
14 |
15 | /* These types must be 16-bit, 32-bit or larger integer */
16 | typedef int INT;
17 | typedef unsigned int UINT;
18 |
19 | /* These types must be 8-bit integer */
20 | typedef char CHAR;
21 | typedef unsigned char UCHAR;
22 | typedef unsigned char BYTE;
23 |
24 | /* These types must be 16-bit integer */
25 | typedef short SHORT;
26 | typedef unsigned short USHORT;
27 | typedef unsigned short WORD;
28 | typedef unsigned short WCHAR;
29 |
30 | /* These types must be 32-bit integer */
31 | typedef long LONG;
32 | typedef unsigned long ULONG;
33 | typedef unsigned long DWORD;
34 |
35 | #endif
36 |
37 | #endif
38 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ff9a/option/syscall.c:
--------------------------------------------------------------------------------
1 | /*------------------------------------------------------------------------*/
2 | /* Sample code of OS dependent controls for FatFs */
3 | /* (C)ChaN, 2012 */
4 | /*------------------------------------------------------------------------*/
5 |
6 | #include /* ANSI memory controls */
7 | #include /* ANSI memory controls */
8 |
9 | #include "../ff.h"
10 |
11 |
12 | #if _FS_REENTRANT
13 | /*------------------------------------------------------------------------*/
14 | /* Create a Synchronization Object
15 | /*------------------------------------------------------------------------*/
16 | /* This function is called in f_mount function to create a new
17 | / synchronization object, such as semaphore and mutex. When a zero is
18 | / returned, the f_mount function fails with FR_INT_ERR.
19 | */
20 |
21 | int ff_cre_syncobj ( /* TRUE:Function succeeded, FALSE:Could not create due to any error */
22 | BYTE vol, /* Corresponding logical drive being processed */
23 | _SYNC_t *sobj /* Pointer to return the created sync object */
24 | )
25 | {
26 | int ret;
27 |
28 | *sobj = CreateMutex(NULL, FALSE, NULL); /* Win32 */
29 | ret = (*sobj != INVALID_HANDLE_VALUE);
30 |
31 | // *sobj = SyncObjects[vol]; /* uITRON (give a static sync object) */
32 | // ret = 1; /* The initial value of the semaphore must be 1. */
33 |
34 | // *sobj = OSMutexCreate(0, &err); /* uC/OS-II */
35 | // ret = (err == OS_NO_ERR);
36 |
37 | // *sobj = xSemaphoreCreateMutex(); /* FreeRTOS */
38 | // ret = (*sobj != NULL);
39 |
40 | return ret;
41 | }
42 |
43 |
44 |
45 | /*------------------------------------------------------------------------*/
46 | /* Delete a Synchronization Object */
47 | /*------------------------------------------------------------------------*/
48 | /* This function is called in f_mount function to delete a synchronization
49 | / object that created with ff_cre_syncobj function. When a zero is
50 | / returned, the f_mount function fails with FR_INT_ERR.
51 | */
52 |
53 | int ff_del_syncobj ( /* TRUE:Function succeeded, FALSE:Could not delete due to any error */
54 | _SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
55 | )
56 | {
57 | BOOL ret;
58 |
59 | ret = CloseHandle(sobj); /* Win32 */
60 |
61 | // ret = 1; /* uITRON (nothing to do) */
62 |
63 | // OSMutexDel(sobj, OS_DEL_ALWAYS, &err); /* uC/OS-II */
64 | // ret = (err == OS_NO_ERR);
65 |
66 | // ret = 1; /* FreeRTOS (nothing to do) */
67 |
68 | return ret;
69 | }
70 |
71 |
72 |
73 | /*------------------------------------------------------------------------*/
74 | /* Request Grant to Access the Volume */
75 | /*------------------------------------------------------------------------*/
76 | /* This function is called on entering file functions to lock the volume.
77 | / When a zero is returned, the file function fails with FR_TIMEOUT.
78 | */
79 |
80 | int ff_req_grant ( /* TRUE:Got a grant to access the volume, FALSE:Could not get a grant */
81 | _SYNC_t sobj /* Sync object to wait */
82 | )
83 | {
84 | int ret;
85 |
86 | ret = (WaitForSingleObject(sobj, _FS_TIMEOUT) == WAIT_OBJECT_0); /* Win32 */
87 |
88 | // ret = (wai_sem(sobj) == E_OK); /* uITRON */
89 |
90 | // OSMutexPend(sobj, _FS_TIMEOUT, &err)); /* uC/OS-II */
91 | // ret = (err == OS_NO_ERR);
92 |
93 | // ret = (xSemaphoreTake(sobj, _FS_TIMEOUT) == pdTRUE); /* FreeRTOS */
94 |
95 | return ret;
96 | }
97 |
98 |
99 |
100 | /*------------------------------------------------------------------------*/
101 | /* Release Grant to Access the Volume */
102 | /*------------------------------------------------------------------------*/
103 | /* This function is called on leaving file functions to unlock the volume.
104 | */
105 |
106 | void ff_rel_grant (
107 | _SYNC_t sobj /* Sync object to be signaled */
108 | )
109 | {
110 | ReleaseMutex(sobj); /* Win32 */
111 |
112 | // sig_sem(sobj); /* uITRON */
113 |
114 | // OSMutexPost(sobj); /* uC/OS-II */
115 |
116 | // xSemaphoreGive(sobj); /* FreeRTOS */
117 |
118 | }
119 |
120 | #endif
121 |
122 |
123 |
124 |
125 | #if _USE_LFN == 3 /* LFN with a working buffer on the heap */
126 | /*------------------------------------------------------------------------*/
127 | /* Allocate a memory block */
128 | /*------------------------------------------------------------------------*/
129 | /* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE.
130 | */
131 |
132 | void* ff_memalloc ( /* Returns pointer to the allocated memory block */
133 | UINT size /* Number of bytes to allocate */
134 | )
135 | {
136 | return malloc(size);
137 | }
138 |
139 |
140 | /*------------------------------------------------------------------------*/
141 | /* Free a memory block */
142 | /*------------------------------------------------------------------------*/
143 |
144 | void ff_memfree(
145 | void* mblock /* Pointer to the memory block to free */
146 | )
147 | {
148 | free(mblock);
149 | }
150 |
151 | #endif
152 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ff9a/option/unicode.c:
--------------------------------------------------------------------------------
1 | #include "../ff.h"
2 |
3 | #if _USE_LFN != 0
4 |
5 | #if _CODE_PAGE == 932
6 | #include "cc932.c"
7 | #elif _CODE_PAGE == 936
8 | #include "cc936.c"
9 | #elif _CODE_PAGE == 949
10 | #include "cc949.c"
11 | #elif _CODE_PAGE == 950
12 | #include "cc950.c"
13 | #else
14 | #include "ccsbcs.c"
15 | #endif
16 |
17 | #endif
18 |
--------------------------------------------------------------------------------
/f303_ice5_fw/flash_cmd.gdb:
--------------------------------------------------------------------------------
1 | attach_swd
2 |
3 | flash
4 |
5 | quit
6 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ice5.c:
--------------------------------------------------------------------------------
1 | /*
2 | * ice5.c - interface routines for STM32F303 SPI to ice5 FPGA
3 | * 07-02-16 E. Brombaugh
4 | */
5 |
6 | #include "ice5.h"
7 | #include "cyclesleep.h"
8 |
9 | /* fool the compiler */
10 | #define UNUSED(x) ((void)(x))
11 | /**
12 | * @brief SPI Interface pins
13 | */
14 | #define ICE5_SPI SPI1
15 | #define ICE5_SPI_CLK RCC_APB2Periph_SPI1
16 | #define ICE5_SPI_SCK_PIN GPIO_Pin_5
17 | #define ICE5_SPI_SCK_GPIO_PORT GPIOA
18 | #define ICE5_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOA
19 | #define ICE5_SPI_SCK_SOURCE GPIO_PinSource5
20 | #define ICE5_SPI_SCK_AF GPIO_AF_5
21 |
22 | #define ICE5_SPI_MISO_PIN GPIO_Pin_6
23 | #define ICE5_SPI_MISO_GPIO_PORT GPIOA
24 | #define ICE5_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOA
25 | #define ICE5_SPI_MISO_SOURCE GPIO_PinSource6
26 | #define ICE5_SPI_MISO_AF GPIO_AF_5
27 |
28 | #define ICE5_SPI_MOSI_PIN GPIO_Pin_7
29 | #define ICE5_SPI_MOSI_GPIO_PORT GPIOA
30 | #define ICE5_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOA
31 | #define ICE5_SPI_MOSI_SOURCE GPIO_PinSource7
32 | #define ICE5_SPI_MOSI_AF GPIO_AF_5
33 |
34 | #define ICE5_SPI_CS_PIN GPIO_Pin_0
35 | #define ICE5_SPI_CS_GPIO_PORT GPIOB
36 | #define ICE5_SPI_CS_GPIO_CLK RCC_AHBPeriph_GPIOB
37 |
38 | #define ICE5_CDONE_PIN GPIO_Pin_2
39 | #define ICE5_CDONE_GPIO_PORT GPIOB
40 | #define ICE5_CDONE_GPIO_CLK RCC_AHBPeriph_GPIOB
41 |
42 | #define ICE5_CRST_PIN GPIO_Pin_1
43 | #define ICE5_CRST_GPIO_PORT GPIOB
44 | #define ICE5_CRST_GPIO_CLK RCC_AHBPeriph_GPIOB
45 |
46 | #define ICE5_SPI_CS_LOW() GPIO_ResetBits(ICE5_SPI_CS_GPIO_PORT, ICE5_SPI_CS_PIN)
47 | #define ICE5_SPI_CS_HIGH() GPIO_SetBits(ICE5_SPI_CS_GPIO_PORT, ICE5_SPI_CS_PIN)
48 | #define ICE5_CRST_LOW() GPIO_ResetBits(ICE5_CRST_GPIO_PORT, ICE5_CRST_PIN)
49 | #define ICE5_CRST_HIGH() GPIO_SetBits(ICE5_CRST_GPIO_PORT, ICE5_CRST_PIN)
50 | #define ICE5_CDONE_GET() GPIO_ReadInputDataBit(ICE5_CDONE_GPIO_PORT, ICE5_CDONE_PIN)
51 | #define ICE5_SPI_DUMMY_BYTE 0xFF
52 |
53 | void ICE5_Init(void)
54 | {
55 | GPIO_InitTypeDef GPIO_InitStructure;
56 | SPI_InitTypeDef SPI_InitStructure;
57 |
58 | /* GPIO Periph clock enables */
59 | RCC_AHBPeriphClockCmd(ICE5_CDONE_GPIO_CLK |
60 | ICE5_SPI_CS_GPIO_CLK | ICE5_SPI_MOSI_GPIO_CLK |
61 | ICE5_SPI_MISO_GPIO_CLK | ICE5_SPI_SCK_GPIO_CLK, ENABLE);
62 |
63 | /* ICE5_SPI Periph clock enable */
64 | RCC_APB2PeriphClockCmd(ICE5_SPI_CLK, ENABLE);
65 |
66 | /* Configure ICE5_SPI pin: SCK */
67 | GPIO_InitStructure.GPIO_Pin = ICE5_SPI_SCK_PIN;
68 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
69 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
70 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
71 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
72 | GPIO_Init(ICE5_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
73 |
74 | /* Configure ICE5_SPI pin: MISO */
75 | GPIO_InitStructure.GPIO_Pin = ICE5_SPI_MISO_PIN;
76 | GPIO_Init(ICE5_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
77 |
78 | /* Configure ICE5_SPI pin: MOSI */
79 | GPIO_InitStructure.GPIO_Pin = ICE5_SPI_MOSI_PIN;
80 | GPIO_Init(ICE5_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
81 |
82 | /* Configure ICE5_SPI_CS_PIN pin */
83 | GPIO_InitStructure.GPIO_Pin = ICE5_SPI_CS_PIN;
84 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
85 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
86 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
87 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
88 | GPIO_Init(ICE5_SPI_CS_GPIO_PORT, &GPIO_InitStructure);
89 | ICE5_SPI_CS_HIGH();
90 |
91 | /* Configure ICE5_CRST_PIN pin */
92 | GPIO_InitStructure.GPIO_Pin = ICE5_CRST_PIN;
93 | GPIO_Init(ICE5_CRST_GPIO_PORT, &GPIO_InitStructure);
94 | ICE5_CRST_HIGH();
95 |
96 | /* leave ICE5_CDONE_PIN pin as input with pullup */
97 | GPIO_InitStructure.GPIO_Pin = ICE5_CDONE_PIN;
98 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
99 | GPIO_Init(ICE5_CDONE_GPIO_PORT, &GPIO_InitStructure);
100 |
101 | /* Connect PXx to ICE5_SPI_SCK */
102 | GPIO_PinAFConfig(ICE5_SPI_SCK_GPIO_PORT, ICE5_SPI_SCK_SOURCE, ICE5_SPI_SCK_AF);
103 |
104 | /* Connect PXx to ICE5_SPI_MISO */
105 | GPIO_PinAFConfig(ICE5_SPI_MISO_GPIO_PORT, ICE5_SPI_MISO_SOURCE, ICE5_SPI_MISO_AF);
106 |
107 | /* Connect PXx to ICE5_SPI_MOSI */
108 | GPIO_PinAFConfig(ICE5_SPI_MOSI_GPIO_PORT, ICE5_SPI_MOSI_SOURCE, ICE5_SPI_MOSI_AF);
109 |
110 | /* ICE5_SPI Config */
111 | SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
112 | SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
113 | SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
114 | #if 0
115 | // original setup from ST eval code - works
116 | SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
117 | SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
118 | #else
119 | // Martin Thomas setup - works too
120 | SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
121 | SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
122 | #endif
123 | SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
124 | SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
125 |
126 | SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
127 | SPI_InitStructure.SPI_CRCPolynomial = 7;
128 | SPI_Init(ICE5_SPI, &SPI_InitStructure);
129 |
130 | SPI_RxFIFOThresholdConfig(ICE5_SPI, SPI_RxFIFOThreshold_QF);
131 |
132 | SPI_Cmd(ICE5_SPI, ENABLE); /* ICE5_SPI enable */
133 | }
134 |
135 | void ICE5_SPI_WriteByte(uint8_t Data)
136 | {
137 | /* Wait until the transmit buffer is empty */
138 | //while(SPI_I2S_GetFlagStatus(ICE5_SPI, SPI_I2S_FLAG_TXE) == RESET)
139 | while((ICE5_SPI->SR & SPI_I2S_FLAG_TXE) == (uint16_t)RESET)
140 | {
141 | }
142 |
143 | /* Send the byte */
144 | //SPI_SendData8(ICE5_SPI, Data);
145 | //ICE5_SPI->DR = (uint16_t)Data;
146 | *(__IO uint8_t *) ((uint32_t)ICE5_SPI+0x0C) = Data;
147 |
148 | /*!< Wait to receive a byte*/
149 | //while(SPI_I2S_GetFlagStatus(ICE5_SPI, SPI_I2S_FLAG_RXNE) == RESET)
150 | while((ICE5_SPI->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET)
151 | {
152 | }
153 |
154 | /* Return the byte read from the SPI bus */
155 | //return SPI_ReceiveData8(ICE5_SPI);
156 | //return *(__IO uint8_t *) ((uint32_t)ICE5_SPI+0x0C);
157 | uint8_t dummy = *(__IO uint8_t *) ((uint32_t)ICE5_SPI+0x0C);
158 | UNUSED(dummy); /* To avoid GCC warning */
159 |
160 | }
161 |
162 | uint8_t ICE5_SPI_WriteReadByte(uint8_t Data)
163 | {
164 | /* Wait until the transmit buffer is empty */
165 | //while(SPI_I2S_GetFlagStatus(ICE5_SPI, SPI_I2S_FLAG_TXE) == RESET)
166 | while((ICE5_SPI->SR & SPI_I2S_FLAG_TXE) == (uint16_t)RESET)
167 | {
168 | }
169 |
170 | /*!< Send the byte */
171 | //SPI_SendData8(ICE5_SPI, Data);
172 | //ICE5_SPI->DR = (uint16_t)Data;
173 | *(__IO uint8_t *) ((uint32_t)ICE5_SPI+0x0C) = Data;
174 |
175 | /* Wait to receive a byte*/
176 | //while(SPI_I2S_GetFlagStatus(ICE5_SPI, SPI_I2S_FLAG_RXNE) == RESET)
177 | while((ICE5_SPI->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET)
178 | {
179 | }
180 |
181 | /* Return the byte read from the SPI bus */
182 | //return SPI_ReceiveData8(ICE5_SPI);
183 | return *(__IO uint8_t *) ((uint32_t)ICE5_SPI+0x0C);
184 | }
185 |
186 | /*
187 | * Read a byte from SPI with dummy write
188 | */
189 | uint8_t ICE5_SPI_ReadByte(void)
190 | {
191 | uint8_t Data = 0;
192 |
193 | /* Wait until the transmit buffer is empty */
194 | while (SPI_I2S_GetFlagStatus(ICE5_SPI, SPI_I2S_FLAG_TXE) == RESET)
195 | {
196 | }
197 | /* Send the byte */
198 | SPI_SendData8(ICE5_SPI, ICE5_SPI_DUMMY_BYTE);
199 |
200 | /* Wait until a data is received */
201 | while (SPI_I2S_GetFlagStatus(ICE5_SPI, SPI_I2S_FLAG_RXNE) == RESET)
202 | {
203 | }
204 | /* Get the received data */
205 | Data = SPI_ReceiveData8(ICE5_SPI);
206 |
207 | /* Return the shifted data */
208 | return Data;
209 | }
210 |
211 | /*
212 | * Write a block of bytes to the ICE5 SPI
213 | */
214 | void ICE5_SPI_WriteBlk(uint8_t *Data, uint32_t Count)
215 | {
216 | while(Count--)
217 | {
218 | ICE5_SPI_WriteByte(*Data++);
219 | }
220 | }
221 |
222 | /*
223 | * private function to start the config process
224 | */
225 | uint8_t ICE5_FPGA_Config_start(void)
226 | {
227 | uint32_t timeout;
228 |
229 | /* drop CS bit to signal slave mode */
230 | ICE5_SPI_CS_LOW();
231 |
232 | /* drop reset bit */
233 | ICE5_CRST_LOW();
234 |
235 | /* delay */
236 | delay(1);
237 |
238 | /* Wait for done bit to go inactive */
239 | timeout = 100;
240 | while(timeout && (ICE5_CDONE_GET()==Bit_SET))
241 | {
242 | timeout--;
243 | }
244 | if(!timeout)
245 | {
246 | /* Done bit didn't respond to Reset */
247 | ICE5_CRST_HIGH();
248 | ICE5_SPI_CS_HIGH();
249 | return 1;
250 | }
251 |
252 | /* raise reset */
253 | ICE5_CRST_HIGH();
254 |
255 | /* delay to allow FPGA to reset */
256 | delay(1);
257 |
258 | return 0;
259 | }
260 |
261 | /*
262 | * private function to finish the config process
263 | */
264 | uint8_t ICE5_FPGA_Config_finish(void)
265 | {
266 | uint32_t timeout;
267 |
268 | /* send clocks while waiting for DONE to assert */
269 | timeout = 100;
270 | while(timeout && (ICE5_CDONE_GET()==Bit_RESET))
271 | {
272 | ICE5_SPI_WriteByte(ICE5_SPI_DUMMY_BYTE);
273 | timeout--;
274 | }
275 | if(!timeout)
276 | {
277 | /* FPGA didn't configure correctly */
278 | return 2;
279 | }
280 |
281 | /* send at least 49 more clocks */
282 | ICE5_SPI_WriteByte(ICE5_SPI_DUMMY_BYTE);
283 | ICE5_SPI_WriteByte(ICE5_SPI_DUMMY_BYTE);
284 | ICE5_SPI_WriteByte(ICE5_SPI_DUMMY_BYTE);
285 | ICE5_SPI_WriteByte(ICE5_SPI_DUMMY_BYTE);
286 | ICE5_SPI_WriteByte(ICE5_SPI_DUMMY_BYTE);
287 | ICE5_SPI_WriteByte(ICE5_SPI_DUMMY_BYTE);
288 | ICE5_SPI_WriteByte(ICE5_SPI_DUMMY_BYTE);
289 |
290 | /* Raise CS bit for subsequent slave transactions */
291 | ICE5_SPI_CS_HIGH();
292 |
293 | /* no error handling for now */
294 | return 0;
295 | }
296 |
297 | /*
298 | * configure the FPGA from MCU memory
299 | */
300 | uint8_t ICE5_FPGA_Config(uint8_t *bitmap, uint32_t size)
301 | {
302 | /* start configuration */
303 | if(ICE5_FPGA_Config_start())
304 | {
305 | /* error */
306 | return 1;
307 | }
308 |
309 | /* send the bitstream */
310 | ICE5_SPI_WriteBlk(bitmap, size);
311 |
312 | /* finish the configuration */
313 | return ICE5_FPGA_Config_finish();
314 | }
315 |
316 | /*
317 | * configure the FPGA from a FatFS file
318 | */
319 | uint8_t ICE5_FPGA_Config_File(FIL *File)
320 | {
321 | uint8_t buffer[512];
322 | FRESULT fres;
323 | uint32_t br;
324 |
325 | /* start configuration */
326 | if(ICE5_FPGA_Config_start())
327 | {
328 | /* error */
329 | return 1;
330 | }
331 |
332 | /* iterate over blocks */
333 | while((fres = f_read(File, buffer, 512, (UINT *)&br))==FR_OK)
334 | {
335 | /* done? */
336 | if(br == 0)
337 | break;
338 |
339 | /* send the block */
340 | ICE5_SPI_WriteBlk(buffer, br);
341 | }
342 |
343 | /* check for error */
344 | if(fres)
345 | {
346 | /* file error */
347 | ICE5_CRST_HIGH();
348 | ICE5_SPI_CS_HIGH();
349 | return 3;
350 | }
351 |
352 | /* finish the configuration */
353 | return ICE5_FPGA_Config_finish();
354 | }
355 |
356 | /*
357 | * Write a long to the FPGA SPI slave
358 | */
359 | void ICE5_FPGA_Slave_Write(uint8_t Reg, uint32_t Data)
360 | {
361 | /* Drop CS */
362 | ICE5_SPI_CS_LOW();
363 |
364 | /* msbit of byte 0 is 0 for write */
365 | ICE5_SPI_WriteByte(Reg & 0x7f);
366 |
367 | /* send next four bytes */
368 | ICE5_SPI_WriteByte((Data>>24) & 0xff);
369 | ICE5_SPI_WriteByte((Data>>16) & 0xff);
370 | ICE5_SPI_WriteByte((Data>> 8) & 0xff);
371 | ICE5_SPI_WriteByte((Data>> 0) & 0xff);
372 |
373 | /* Raise CS */
374 | ICE5_SPI_CS_HIGH();
375 | }
376 |
377 | /*
378 | * Read a long from the FPGA SPI slave
379 | */
380 | void ICE5_FPGA_Slave_Read(uint8_t Reg, uint32_t *Data)
381 | {
382 | uint8_t rx[4];
383 |
384 | /* Drop CS */
385 | ICE5_SPI_CS_LOW();
386 |
387 | /* msbit of byte 0 is 1 for write */
388 | ICE5_SPI_WriteByte(Reg | 0x80);
389 |
390 | /* get next four bytes */
391 | rx[0] = ICE5_SPI_ReadByte();
392 | rx[1] = ICE5_SPI_ReadByte();
393 | rx[2] = ICE5_SPI_ReadByte();
394 | rx[3] = ICE5_SPI_ReadByte();
395 |
396 | /* assemble result */
397 | *Data = (rx[0]<<24) | (rx[1]<<16) | (rx[2]<<8) | rx[3];
398 |
399 | /* Raise CS */
400 | ICE5_SPI_CS_HIGH();
401 | }
402 |
403 |
--------------------------------------------------------------------------------
/f303_ice5_fw/ice5.h:
--------------------------------------------------------------------------------
1 | /*
2 | * ice5.c - interface routines for STM32F303 SPI to ice5 FPGA
3 | * 07-02-16 E. Brombaugh
4 | */
5 |
6 | #ifndef __ICE5__
7 | #define __ICE5__
8 |
9 | #include "stm32f30x.h"
10 | #include "ff.h"
11 |
12 | void ICE5_Init(void);
13 | uint8_t ICE5_FPGA_Config(uint8_t *bitmap, uint32_t size);
14 | uint8_t ICE5_FPGA_Config_File(FIL *File);
15 | void ICE5_FPGA_Slave_Write(uint8_t Reg, uint32_t Data);
16 | void ICE5_FPGA_Slave_Read(uint8_t Reg, uint32_t *Data);
17 |
18 | #endif
19 |
--------------------------------------------------------------------------------
/f303_ice5_fw/led.c:
--------------------------------------------------------------------------------
1 | /*
2 | * led.c - F303_ice5 LED setup
3 | */
4 |
5 | #include "led.h"
6 |
7 | /*
8 | * Initialize the breakout board LED
9 | */
10 | void LEDInit(void)
11 | {
12 | GPIO_InitTypeDef GPIO_InitStructure;
13 |
14 | /* Enable GPIO A Clock */
15 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
16 |
17 | /* Enable PA9 for output */
18 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
19 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
20 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
21 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
22 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
23 | GPIO_Init(GPIOA, &GPIO_InitStructure);
24 | }
25 |
26 | /*
27 | * Turn on LED
28 | */
29 | void LEDOn(void)
30 | {
31 | GPIOA->BSRR = (1<<9);
32 | }
33 |
34 | /*
35 | * Turn off LED
36 | */
37 | void LEDOff(void)
38 | {
39 | GPIOA->BRR = (1<<9);
40 | }
41 |
42 | /*
43 | * Toggle LED
44 | */
45 | void LEDToggle(void)
46 | {
47 | GPIOA->ODR ^= (1<<9);
48 | }
49 |
50 |
--------------------------------------------------------------------------------
/f303_ice5_fw/led.h:
--------------------------------------------------------------------------------
1 | /*
2 | * led.h - F303_ice5 LED setup
3 | */
4 |
5 | #ifndef __led__
6 | #define __led__
7 |
8 | #include "stm32f30x.h"
9 |
10 | void LEDInit(void);
11 | void LEDOn(void);
12 | void LEDOff(void);
13 | void LEDToggle(void);
14 |
15 | #endif
16 |
--------------------------------------------------------------------------------
/f303_ice5_fw/main.c:
--------------------------------------------------------------------------------
1 | /*
2 | main.c
3 |
4 | Part of f303_ice5 - stm32f303 & ice5lp4k FPGA
5 | Copyright 07-02-2016 E. Brombaugh
6 | */
7 | #include
8 | #include
9 | #include "stm32f30x.h"
10 | #include "cyclesleep.h"
11 | #include "systick.h"
12 | #include "usart.h"
13 | #include "led.h"
14 | #include "ice5.h"
15 | #include "cmd.h"
16 | #include "diskio.h"
17 | #include "ff.h"
18 |
19 | /* FPGA bitstream */
20 | extern uint8_t _binary_bitmap_bin_start;
21 | extern uint8_t _binary_bitmap_bin_end;
22 |
23 | /*
24 | * start
25 | */
26 | int main(void)
27 | {
28 | uint32_t bitmap_size = &_binary_bitmap_bin_end - &_binary_bitmap_bin_start;
29 | int rxchar;
30 | uint32_t delaygoal;
31 | uint8_t result;
32 |
33 | /* start cycle counter */
34 | cyccnt_enable();
35 |
36 | /* init LEDs & Switches */
37 | SysTick_Init();
38 | LEDInit();
39 |
40 | /* Setup USART diag output */
41 | setup_usart1();
42 | printf("\nSTM32F303 ice5\n");
43 |
44 | /* enable shared spi */
45 | setup_shared_spi();
46 | printf("Shared SPI configured\n");
47 |
48 | /* Setup FPGA */
49 | ICE5_Init();
50 | printf("Configuring %d bytes....", (unsigned int)bitmap_size);
51 | result = ICE5_FPGA_Config(&_binary_bitmap_bin_start, bitmap_size);
52 | if(result)
53 | printf("FPGA configure error: %d.\n", result);
54 | else
55 | printf("FPGA configured.\n");
56 |
57 | /* loop forever */
58 | init_cmd();
59 | delaygoal = cyclegoal_ms(100);
60 | while(1)
61 | {
62 | /* Blink the heartbeat LED */
63 | if(!cyclecheck(delaygoal))
64 | {
65 | LEDToggle();
66 | delaygoal = cyclegoal_ms(100);
67 | }
68 |
69 | /* UART command processing */
70 | if((rxchar = get_usart())!= EOF)
71 | {
72 | /* Parse commands */
73 | cmd_parse(rxchar);
74 | }
75 | }
76 | }
77 |
78 | #ifdef USE_FULL_ASSERT
79 |
80 | /**
81 | * @brief Reports the name of the source file and the source line number
82 | * where the assert_param error has occurred.
83 | * @param file: pointer to the source file name
84 | * @param line: assert_param error line source number
85 | * @retval None
86 | */
87 | void assert_failed(uint8_t* file, uint32_t line)
88 | {
89 | /* User can add his own implementation to report the file name and line number,
90 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
91 |
92 | /* Infinite loop */
93 | while (1)
94 | {
95 | }
96 | }
97 | #endif
98 |
--------------------------------------------------------------------------------
/f303_ice5_fw/openocd.cfg:
--------------------------------------------------------------------------------
1 | # This is an STM32F30x
2 | #
3 |
4 | source [find interface/stlink-v2.cfg]
5 | transport select hla_swd
6 |
7 | source [find target/stm32f3x.cfg]
8 |
9 | reset_config none
10 |
11 | init
12 |
--------------------------------------------------------------------------------
/f303_ice5_fw/openocd_j-link.cfg:
--------------------------------------------------------------------------------
1 | # This is an STM32F30x
2 | #
3 |
4 | source [find interface/jlink.cfg]
5 | transport select swd
6 |
7 | source [find target/stm32f3x.cfg]
8 |
9 | reset_config none
10 |
11 | init
12 |
--------------------------------------------------------------------------------
/f303_ice5_fw/openocd_stlinkv2.1.cfg:
--------------------------------------------------------------------------------
1 | # This is an STM32F031C6
2 | #
3 |
4 | source [find interface/stlink-v2-1.cfg]
5 | transport select hla_swd
6 |
7 | source [find target/stm32f3x.cfg]
8 |
9 | reset_config none
10 |
11 | init
12 |
--------------------------------------------------------------------------------
/f303_ice5_fw/shared_spi.c:
--------------------------------------------------------------------------------
1 | /*
2 | * shared_spi.c - interface routines for F303_ICE5 SPI
3 | * 07-05-16 E. Brombaugh
4 | */
5 |
6 | #include "shared_spi.h"
7 |
8 | /* fool the compiler */
9 | #define UNUSED(x) ((void)(x))
10 |
11 | void setup_shared_spi(void)
12 | {
13 | GPIO_InitTypeDef GPIO_InitStructure;
14 | SPI_InitTypeDef SPI_InitStructure;
15 |
16 | /* GPIO Periph clock enables */
17 | RCC_AHBPeriphClockCmd(LCD_CS_GPIO_CLK | LCD_DC_GPIO_CLK |
18 | LCD_LITE_GPIO_CLK | SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK |
19 | SD_SPI_MISO_GPIO_CLK | SD_SPI_SCK_GPIO_CLK, ENABLE);
20 |
21 | /* SD_SPI Periph clock enable */
22 | RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE);
23 |
24 | /* Configure SD_SPI pins: SCK */
25 | GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
26 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
27 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
28 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
29 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
30 | GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
31 |
32 | /* Configure SD_SPI pins: MISO */
33 | GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
34 | GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
35 |
36 | /* Configure SD_SPI pins: MOSI */
37 | GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
38 | GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
39 |
40 | /* Configure SD_SPI_CS_PIN pin: SD Card CS pin */
41 | GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
42 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
43 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
44 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
45 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
46 | GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
47 | SD_CS_HIGH();
48 |
49 | /* Configure LCD_CS_PIN pin: LCD CS pin */
50 | GPIO_InitStructure.GPIO_Pin = LCD_CS_PIN;
51 | GPIO_Init(LCD_CS_GPIO_PORT, &GPIO_InitStructure);
52 | LCD_CS_HIGH();
53 |
54 | /* Configure LCD_DC_PIN pin: LCD D/C pin */
55 | GPIO_InitStructure.GPIO_Pin = LCD_DC_PIN;
56 | GPIO_Init(LCD_DC_GPIO_PORT, &GPIO_InitStructure);
57 | LCD_DC_CMD();
58 |
59 | /* Configure LCD_RST_PIN pin: LCD Reset pin */
60 | GPIO_InitStructure.GPIO_Pin = LCD_RST_PIN;
61 | GPIO_Init(LCD_RST_GPIO_PORT, &GPIO_InitStructure);
62 | LCD_RST_HIGH();
63 |
64 | /* Configure LCD_LITE_PIN pin: LCD Lite pin */
65 | GPIO_InitStructure.GPIO_Pin = LCD_LITE_PIN;
66 | GPIO_Init(LCD_LITE_GPIO_PORT, &GPIO_InitStructure);
67 | LCD_LITE_HIGH();
68 |
69 | /* Connect PXx to SD_SPI_SCK */
70 | GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);
71 |
72 | /* Connect PXx to SD_SPI_MISO */
73 | GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF);
74 |
75 | /* Connect PXx to SD_SPI_MOSI */
76 | GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);
77 |
78 | /* SD_SPI Config */
79 | SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
80 | SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
81 | SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
82 | #if 0
83 | // original setup from ST eval code - works
84 | SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
85 | SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
86 | #else
87 | // Martin Thomas setup - works too
88 | SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
89 | SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
90 | #endif
91 | SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
92 | SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
93 |
94 | SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
95 | SPI_InitStructure.SPI_CRCPolynomial = 7;
96 | SPI_Init(SD_SPI, &SPI_InitStructure);
97 |
98 | SPI_RxFIFOThresholdConfig(SD_SPI, SPI_RxFIFOThreshold_QF);
99 |
100 | SPI_Cmd(SD_SPI, ENABLE); /* SD_SPI enable */
101 |
102 | SPI_InitDMA(); /* setup DMA structure for fast ops */
103 | }
104 |
105 | void SPI_WriteByte(uint8_t Data)
106 | {
107 | /* Wait until the transmit buffer is empty */
108 | //while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
109 | while((SD_SPI->SR & SPI_I2S_FLAG_TXE) == (uint16_t)RESET)
110 | {
111 | }
112 |
113 | /* Send the byte */
114 | //SPI_SendData8(SD_SPI, Data);
115 | //SD_SPI->DR = (uint16_t)Data;
116 | *(__IO uint8_t *) ((uint32_t)SD_SPI+0x0C) = Data;
117 |
118 | /*!< Wait to receive a byte*/
119 | //while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
120 | while((SD_SPI->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET)
121 | {
122 | }
123 |
124 | /* Return the byte read from the SPI bus */
125 | //return SPI_ReceiveData8(SD_SPI);
126 | //return *(__IO uint8_t *) ((uint32_t)SD_SPI+0x0C);
127 | uint8_t dummy = *(__IO uint8_t *) ((uint32_t)SD_SPI+0x0C);
128 | UNUSED(dummy); /* To avoid GCC warning */
129 |
130 | }
131 |
132 | uint8_t SPI_WriteReadByte(uint8_t Data)
133 | {
134 | /* Wait until the transmit buffer is empty */
135 | //while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
136 | while((SD_SPI->SR & SPI_I2S_FLAG_TXE) == (uint16_t)RESET)
137 | {
138 | }
139 |
140 | /*!< Send the byte */
141 | //SPI_SendData8(SD_SPI, Data);
142 | //SD_SPI->DR = (uint16_t)Data;
143 | *(__IO uint8_t *) ((uint32_t)SD_SPI+0x0C) = Data;
144 |
145 | /* Wait to receive a byte*/
146 | //while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
147 | while((SD_SPI->SR & SPI_I2S_FLAG_RXNE) == (uint16_t)RESET)
148 | {
149 | }
150 |
151 | /* Return the byte read from the SPI bus */
152 | //return SPI_ReceiveData8(SD_SPI);
153 | return *(__IO uint8_t *) ((uint32_t)SD_SPI+0x0C);
154 | }
155 |
156 | uint8_t SPI_ReadByte(void)
157 | {
158 | uint8_t Data = 0;
159 |
160 | /* Wait until the transmit buffer is empty */
161 | while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
162 | {
163 | }
164 | /* Send the byte */
165 | SPI_SendData8(SD_SPI, SD_DUMMY_BYTE);
166 |
167 | /* Wait until a data is received */
168 | while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
169 | {
170 | }
171 | /* Get the received data */
172 | Data = SPI_ReceiveData8(SD_SPI);
173 |
174 | /* Return the shifted data */
175 | return Data;
176 | }
177 |
178 | DMA_InitTypeDef DMA_InitStructure;
179 |
180 | void SPI_InitDMA(void)
181 | {
182 | // turn on DMA1 clock
183 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
184 |
185 | DMA_Cmd(DMA2_Channel2, DISABLE);
186 | DMA_DeInit(DMA2_Channel2);
187 |
188 | // Common
189 | DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&(SD_SPI->DR);
190 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
191 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
192 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
193 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
194 | DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
195 | DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
196 | DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
197 | DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
198 | }
199 |
200 | void SPI_start_DMA_WriteBytes(uint8_t *buffer, uint16_t len)
201 | {
202 | /* Setup buffer loc / len */
203 | DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
204 | DMA_InitStructure.DMA_BufferSize = len;
205 | DMA_Init(DMA2_Channel2, &DMA_InitStructure);
206 |
207 | /* Enable SPI_DMA_TX */
208 | DMA_Cmd(DMA2_Channel2, ENABLE);
209 |
210 | /* Enable SPI_DMA TX request */
211 | SPI_I2S_DMACmd(SD_SPI, SPI_I2S_DMAReq_Tx, ENABLE);
212 | }
213 |
214 | void SPI_end_DMA_WriteBytes(void)
215 | {
216 | /* Wait until SPI_DMA_TX Complete */
217 | while (DMA_GetFlagStatus(DMA1_FLAG_TC3) == RESET);
218 |
219 | /* DISABLE SPI_DMA_TX */
220 | DMA_Cmd(DMA2_Channel2, DISABLE);
221 | SPI_I2S_DMACmd(SD_SPI, SPI_I2S_DMAReq_Tx, DISABLE);
222 |
223 | /* Clear DMA TransferComplete Flag */
224 | DMA_ClearFlag(DMA2_FLAG_TC2);
225 | //DMA_ClearITPendingBit(DMA1_IT_TC3);
226 |
227 | /* Wait to receive a byte */
228 | while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET);
229 | }
230 |
231 | void SPI_real_DMA_WriteBytes(uint8_t *buffer, uint16_t len)
232 | {
233 | SPI_start_DMA_WriteBytes(buffer, len);
234 | SPI_end_DMA_WriteBytes();
235 | }
236 |
--------------------------------------------------------------------------------
/f303_ice5_fw/shared_spi.h:
--------------------------------------------------------------------------------
1 | /*
2 | * shared_spi.c - interface routines for F303_ICE5 SPI
3 | * 07-05-16 E. Brombaugh
4 | */
5 |
6 | #ifndef __SHARED_SPI__
7 | #define __SHARED_SPI_
8 |
9 | #include "stm32f30x.h"
10 |
11 | /*
12 | * SPI Interface pins
13 | */
14 | #define SD_SPI SPI3
15 | #define SD_SPI_CLK RCC_APB1Periph_SPI3
16 | #define SD_SPI_SCK_PIN GPIO_Pin_3
17 | #define SD_SPI_SCK_GPIO_PORT GPIOB
18 | #define SD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOB
19 | #define SD_SPI_SCK_SOURCE GPIO_PinSource3
20 | #define SD_SPI_SCK_AF GPIO_AF_6
21 |
22 | #define SD_SPI_MISO_PIN GPIO_Pin_4
23 | #define SD_SPI_MISO_GPIO_PORT GPIOB
24 | #define SD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOB
25 | #define SD_SPI_MISO_SOURCE GPIO_PinSource4
26 | #define SD_SPI_MISO_AF GPIO_AF_6
27 |
28 | #define SD_SPI_MOSI_PIN GPIO_Pin_5
29 | #define SD_SPI_MOSI_GPIO_PORT GPIOB
30 | #define SD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOB
31 | #define SD_SPI_MOSI_SOURCE GPIO_PinSource5
32 | #define SD_SPI_MOSI_AF GPIO_AF_6
33 |
34 | #define SD_CS_PIN GPIO_Pin_15
35 | #define SD_CS_GPIO_PORT GPIOA
36 | #define SD_CS_GPIO_CLK RCC_AHBPeriph_GPIOA
37 |
38 | #define LCD_LITE_PIN GPIO_Pin_8
39 | #define LCD_LITE_GPIO_PORT GPIOB
40 | #define LCD_LITE_GPIO_CLK RCC_AHBPeriph_GPIOB
41 |
42 | #define LCD_CS_PIN GPIO_Pin_9
43 | #define LCD_CS_GPIO_PORT GPIOB
44 | #define LCD_CS_GPIO_CLK RCC_AHBPeriph_GPIOB
45 |
46 | #define LCD_DC_PIN GPIO_Pin_14
47 | #define LCD_DC_GPIO_PORT GPIOC
48 | #define LCD_DC_GPIO_CLK RCC_AHBPeriph_GPIOC
49 |
50 | #define LCD_RST_PIN GPIO_Pin_15
51 | #define LCD_RST_GPIO_PORT GPIOC
52 | #define LCD_RST_GPIO_CLK RCC_AHBPeriph_GPIOC
53 |
54 | #define SD_CS_LOW() GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
55 | #define SD_CS_HIGH() GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
56 | #define LCD_CS_LOW() GPIO_ResetBits(LCD_CS_GPIO_PORT, LCD_CS_PIN)
57 | #define LCD_CS_HIGH() GPIO_SetBits(LCD_CS_GPIO_PORT, LCD_CS_PIN)
58 | #define LCD_DC_CMD() GPIO_ResetBits(LCD_DC_GPIO_PORT, LCD_DC_PIN)
59 | #define LCD_DC_DATA() GPIO_SetBits(LCD_DC_GPIO_PORT, LCD_DC_PIN)
60 | #define LCD_RST_LOW() GPIO_ResetBits(LCD_RST_GPIO_PORT, LCD_RST_PIN)
61 | #define LCD_RST_HIGH() GPIO_SetBits(LCD_RST_GPIO_PORT, LCD_RST_PIN)
62 | #define LCD_LITE_LOW() GPIO_ResetBits(LCD_LITE_GPIO_PORT, LCD_LITE_PIN)
63 | #define LCD_LITE_HIGH() GPIO_SetBits(LCD_LITE_GPIO_PORT, LCD_LITE_PIN)
64 | #define SD_DUMMY_BYTE 0xFF
65 |
66 | void setup_shared_spi(void);
67 | void SPI_WriteByte(uint8_t Data);
68 | uint8_t SPI_WriteReadByte(uint8_t Data);
69 | uint8_t SPI_ReadByte(void);
70 | void SPI_fake_DMA_WriteBytes(uint8_t *buffer, uint16_t len);
71 | void SPI_InitDMA(void);
72 | void SPI_start_DMA_WriteBytes(uint8_t *buffer, uint16_t len);
73 | void SPI_end_DMA_WriteBytes(void);
74 | void SPI_real_DMA_WriteBytes(uint8_t *buffer, uint16_t len);
75 |
76 | #endif
77 |
--------------------------------------------------------------------------------
/f303_ice5_fw/stubs.c:
--------------------------------------------------------------------------------
1 | /*
2 | * libstubs.c - stubs that the library wants since libnosys doesn't do anything
3 | */
4 |
5 | #include
6 | #include
7 | #include "usart.h"
8 |
9 | /* _end is set in the linker command file
10 | extern caddr_t _end;*/
11 |
12 | /* just in case, most boards have at least some memory */
13 | #ifndef RAMSIZE
14 | # define RAMSIZE (caddr_t)0x100000
15 | #endif
16 |
17 | /*
18 | * sbrk -- changes heap size size. Get nbytes more
19 | * RAM. We just increment a pointer in what's
20 | * left of memory on the board.
21 | */
22 | caddr_t
23 | _sbrk(nbytes)
24 | int nbytes;
25 | {
26 | static caddr_t heap_ptr = NULL;
27 | caddr_t base;
28 |
29 | if (heap_ptr == NULL) {
30 | heap_ptr = (caddr_t)0x20007fff;
31 | }
32 |
33 | if ((RAMSIZE - heap_ptr) >= 0) {
34 | base = heap_ptr;
35 | heap_ptr += nbytes;
36 | return (base);
37 | } else {
38 | errno = ENOMEM;
39 | return ((caddr_t)-1);
40 | }
41 | }
42 |
43 | /*
44 | * isatty -- returns 1 if connected to a terminal device,
45 | * returns 0 if not. Since we're hooked up to a
46 | * serial port, we'll say yes and return a 1.
47 | */
48 | int
49 | _isatty(fd)
50 | int fd;
51 | {
52 | return (1);
53 | }
54 |
55 | /*
56 | * getpid -- only one process, so just return 1.
57 | */
58 | #define __MYPID 1
59 | int
60 | _getpid()
61 | {
62 | return __MYPID;
63 | }
64 |
65 | /*
66 | * exit
67 | */
68 | void
69 | _exit(int val)
70 | {
71 | while(1);
72 | }
73 |
74 | /*
75 | * kill -- go out via exit...
76 | */
77 | int
78 | _kill(pid, sig)
79 | int pid;
80 | int sig;
81 | {
82 | if(pid == __MYPID)
83 | _exit(sig);
84 | return 0;
85 | }
86 |
87 | /*
88 | * read -- read bytes from the serial port. Ignore fd, since
89 | * we only have stdin.
90 | */
91 | int
92 | _read(fd, buf, nbytes)
93 | int fd;
94 | char *buf;
95 | int nbytes;
96 | {
97 | int i = 0;
98 |
99 | for (i = 0; i < nbytes; i++) {
100 | *(buf + i) = inbyte();
101 | if ((*(buf + i) == '\n') || (*(buf + i) == '\r')) {
102 | (*(buf + i)) = 0;
103 | break;
104 | }
105 | }
106 | return (i);
107 | }
108 |
109 | /*
110 | * write -- write bytes to the serial port. Ignore fd, since
111 | * stdout and stderr are the same. Since we have no filesystem,
112 | * open will only return an error.
113 | */
114 | int
115 | _write(fd, buf, nbytes)
116 | int fd;
117 | char *buf;
118 | int nbytes;
119 | {
120 | int i;
121 |
122 | for (i = 0; i < nbytes; i++) {
123 | if (*(buf + i) == '\n') {
124 | outbyte ('\r');
125 | }
126 | outbyte (*(buf + i));
127 | }
128 | return (nbytes);
129 | }
130 |
131 |
132 | /*
133 | * close -- close a file descriptor. We don't need
134 | * to do anything, but pretend we did.
135 | */
136 | int
137 | _close(fd)
138 | int fd;
139 | {
140 | return (0);
141 | }
142 |
143 | /*
144 | * lseek -- move read/write pointer. Since a serial port
145 | * is non-seekable, we return an error.
146 | */
147 | off_t
148 | _lseek(fd, offset, whence)
149 | int fd;
150 | off_t offset;
151 | int whence;
152 | {
153 | errno = ESPIPE;
154 | return ((off_t)-1);
155 | }
156 |
157 | /*
158 | * fstat -- get status of a file. Since we have no file
159 | * system, we just return an error.
160 | */
161 | int
162 | _fstat(fd, buf)
163 | int fd;
164 | struct stat *buf;
165 | {
166 | errno = EIO;
167 | return (-1);
168 | }
169 |
--------------------------------------------------------------------------------
/f303_ice5_fw/systick.c:
--------------------------------------------------------------------------------
1 | /*
2 | * systick.c - 1ms system tick timer & related services.
3 | * - also handles switches, encoder and button debounce
4 | */
5 |
6 | #include "systick.h"
7 |
8 | uint32_t SysTick_Counter;
9 |
10 | /*
11 | * SysTick_Init - sets up all the System Tick and UI state
12 | */
13 | void SysTick_Init(void)
14 | {
15 | GPIO_InitTypeDef GPIO_InitStructure;
16 |
17 | /* Enable GPIOB Periph clock for diags */
18 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
19 |
20 | /* Configure PC14 PC15 as input w/ pullup */
21 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14|GPIO_Pin_15;
22 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
23 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ;
24 | GPIO_Init(GPIOC, &GPIO_InitStructure);
25 |
26 | /* Init tick counter */
27 | SysTick_Counter = 0;
28 |
29 | /* start Tick IRQ */
30 | if(SysTick_Config(SystemCoreClock/1000))
31 | {
32 | /* Hang here to capture error */
33 | while(1);
34 | }
35 | }
36 |
37 | /*
38 | * SysTick_Handler - Called by System Tick IRQ @ 1ms intervals to update UI elements
39 | */
40 | void SysTick_Handler(void)
41 | {
42 | /* Update SysTick Counter */
43 | SysTick_Counter++;
44 | }
45 |
--------------------------------------------------------------------------------
/f303_ice5_fw/systick.h:
--------------------------------------------------------------------------------
1 | /*
2 | * systick.h - 1ms system tick setup
3 | */
4 |
5 | #ifndef __systick__
6 | #define __systick__
7 |
8 | #include "stm32f30x.h"
9 |
10 | void SysTick_Init(void);
11 |
12 | #endif
13 |
--------------------------------------------------------------------------------
/f303_ice5_fw/usart.c:
--------------------------------------------------------------------------------
1 | /*
2 | * usart.c - serial i/o routines
3 | * 12-24-12 E. Brombaugh
4 | */
5 |
6 | #include
7 | #include "stm32f30x.h"
8 |
9 | uint8_t RX_buffer[256];
10 | uint8_t *RX_wptr, *RX_rptr;
11 |
12 | /* USART1 setup */
13 | void setup_usart1(void)
14 | {
15 | GPIO_InitTypeDef GPIO_InitStructure;
16 | USART_InitTypeDef USART_InitStructure;
17 | NVIC_InitTypeDef NVIC_InitStructure;
18 |
19 | /* init RX buffer write/read pointers*/
20 | RX_wptr = &RX_buffer[0];
21 | RX_rptr = &RX_buffer[0];
22 |
23 | /* Setup USART */
24 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
25 |
26 | /* Connect PB6 to USARTx_Tx */
27 | GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_7);
28 |
29 | /* Connect PB7 to USARTx_Rx */
30 | GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_7);
31 |
32 | /* Configure USART Tx as alternate function push-pull */
33 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
34 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
35 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
36 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
37 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
38 | GPIO_Init(GPIOB, &GPIO_InitStructure);
39 |
40 | /* Configure USART Rx as alternate function push-pull */
41 | /* RX not used */
42 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
43 | GPIO_Init(GPIOB, &GPIO_InitStructure);
44 |
45 | /* USART configuration */
46 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
47 |
48 | /* USART = 115k-8-N-1 */
49 | USART_InitStructure.USART_BaudRate = 115200;
50 | USART_InitStructure.USART_WordLength = USART_WordLength_8b;
51 | USART_InitStructure.USART_StopBits = USART_StopBits_1;
52 | USART_InitStructure.USART_Parity = USART_Parity_No;
53 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
54 | USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
55 | USART_Init(USART1, &USART_InitStructure);
56 |
57 | /* Enable RX interrupt */
58 | USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
59 |
60 | /* Enable the USART6 Interrupt */
61 | NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
62 | NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
63 | NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
64 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
65 | NVIC_Init(&NVIC_InitStructure);
66 |
67 | /* Enable USART */
68 | USART_Cmd(USART1, ENABLE);
69 | }
70 |
71 | int get_usart(void)
72 | {
73 | #if 0
74 | /* Non-interrupt version */
75 | if(USART_GetFlagStatus(USART6, USART_FLAG_RXNE) == SET)
76 | return USART_ReceiveData(USART6);
77 | else
78 | return EOF;
79 | #else
80 | /* interrupt version */
81 | int retval;
82 |
83 | /* check if there's data in the buffer */
84 | if(RX_rptr != RX_wptr)
85 | {
86 | /* get the data */
87 | retval = *RX_rptr++;
88 |
89 | /* wrap the pointer */
90 | if((RX_rptr - &RX_buffer[0])>=256)
91 | RX_rptr = &RX_buffer[0];
92 | }
93 | else
94 | retval = EOF;
95 |
96 | return retval;
97 | #endif
98 | }
99 |
100 | /**
101 | * @brief Retargets the C library printf function to the USART.
102 | * @param None
103 | * @retval None
104 | */
105 | int outbyte(int ch)
106 | {
107 | /* Place your implementation of fputc here */
108 | /* e.g. write a character to the USART */
109 | USART_SendData(USART1, (uint8_t) ch);
110 |
111 | /* Loop until transmit data register is empty */
112 | while (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)
113 | {}
114 |
115 | return ch;
116 | }
117 |
118 | /**
119 | * @brief Retargets the C library printf function to the USART.
120 | * @param None
121 | * @retval None
122 | */
123 | int inbyte(void)
124 | {
125 | /* nothing happening yet */
126 | return 0;
127 | }
128 |
129 | /*
130 | * USART IRQ handler - used only for Rx for now
131 | */
132 | void USART1_IRQHandler(void)
133 | {
134 | if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)
135 | {
136 | /* get the character */
137 | uint8_t rxchar = USART_ReceiveData(USART1);
138 |
139 | /* check if there's room in the buffer */
140 | if((RX_wptr != RX_rptr-1) &&
141 | (RX_wptr - RX_rptr != 255))
142 | {
143 | /* Yes - Queue the new char */
144 | *RX_wptr++ = rxchar;
145 |
146 | /* Wrap pointer */
147 | if((RX_wptr - &RX_buffer[0])>=256)
148 | RX_wptr = &RX_buffer[0];
149 | }
150 | }
151 |
152 | if(USART_GetITStatus(USART1, USART_IT_TXE) != RESET)
153 | {
154 | }
155 | }
--------------------------------------------------------------------------------
/f303_ice5_fw/usart.h:
--------------------------------------------------------------------------------
1 | /*
2 | * usart.h - usart printf stuff
3 | * 12-24-12 E. Brombaugh
4 | */
5 |
6 | #ifndef __usart__
7 | #define __usart__
8 |
9 | void setup_usart1(void);
10 | int get_usart(void);
11 | int outbyte(int ch);
12 | int inbyte(void);
13 |
14 | #endif
15 |
--------------------------------------------------------------------------------
/f303_ice5_hw/README.md:
--------------------------------------------------------------------------------
1 | # f303_ice5_hw
2 |
3 | This is FPGA hardware source for the f303_ice5 board. Use the Lattice
4 | iCEcube2 tools to open and synthesize the project in the f303_ice5_test
5 | directory.
6 |
7 |
8 |
--------------------------------------------------------------------------------
/f303_ice5_hw/f303_ice5_test/f303_ice5_test_sbt.project:
--------------------------------------------------------------------------------
1 | [Project]
2 | ProjectVersion=2.0
3 | Version=Lattice Semiconductor Corporation iCEcube - Release: 2016.02.27810 - Build Date: Jan 28 2016 18:12:42
4 | ProjectName=f303_ice5_test
5 | Vendor=SiliconBlue
6 | Synthesis=synplify
7 | ProjectVFiles=../src/f303_ice5_test.v,../src/spi_slave.v
8 | ProjectCFiles=
9 | CurImplementation=f303_ice5_test_Implmnt
10 | Implementations=f303_ice5_test_Implmnt
11 | StartFromSynthesis=yes
12 | IPGeneration=false
13 |
14 | [f303_ice5_test_Implmnt]
15 | DeviceFamily=iCE5LP
16 | Device=4K
17 | DevicePackage=SG48
18 | DevicePower=
19 | NetlistFile=f303_ice5_test_Implmnt/f303_ice5_test.edf
20 | AdditionalEDIFFile=
21 | IPEDIFFile=
22 | DesignLib=f303_ice5_test_Implmnt/sbt/netlist/oadb-f303_ice5_test
23 | DesignView=_rt
24 | DesignCell=f303_ice5_test
25 | SynthesisSDCFile=f303_ice5_test_Implmnt/f303_ice5_test.scf
26 | UserPinConstraintFile=
27 | UserSDCFile=
28 | PhysicalConstraintFile=../src/f303_ice5_test.pcf
29 | BackendImplPathName=
30 | Devicevoltage=1.14
31 | DevicevoltagePerformance=+/-5%(datasheet default)
32 | DeviceTemperature=85
33 | TimingAnalysisBasedOn=Worst
34 | OperationRange=Commercial
35 | TypicalCustomTemperature=25
36 | WorstCustomTemperature=85
37 | BestCustomTemperature=0
38 | IOBankVoltages=topBank,2.5 bottomBank,2.5
39 | derValue=1.32445
40 | TimingPathNumberStick=0
41 |
42 | [lse options]
43 | CarryChain=True
44 | CarryChainLength=0
45 | CommandLineOptions=
46 | EBRUtilization=100.00
47 | FSMEncodingStyle=Auto
48 | FixGatedClocks=True
49 | I/OInsertion=True
50 | IntermediateFileDump=False
51 | LoopLimit=1950
52 | MaximalFanout=10000
53 | MemoryInitialValueFileSearchPath=
54 | NumberOfCriticalPaths=3
55 | OptimizationGoal=Area
56 | PropagateConstants=True
57 | RAMStyle=Auto
58 | ROMStyle=Auto
59 | RWCheckOnRam=False
60 | RemoveDuplicateRegisters=True
61 | ResolvedMixedDrivers=False
62 | ResourceSharing=True
63 | TargetFrequency=
64 | TopLevelUnit=
65 | UseIORegister=Auto
66 | VHDL2008=False
67 | VerilogIncludeSearchPath=
68 |
69 | [tool options]
70 | PlacerEffortLevel=std
71 | PlacerAutoLutCascade=yes
72 | PlacerAutoRamCascade=yes
73 | PlacerPowerDriven=no
74 | RouteWithTimingDriven=yes
75 | RouteWithPinPermutation=yes
76 | BitmapSPIFlashMode=yes
77 | BitmapRAM4KInit=yes
78 | BitmapInitRamBank=1111
79 | BitmapOscillatorFR=low
80 | BitmapEnableWarmBoot=yes
81 | BitmapDisableHeader=no
82 | BitmapSetSecurity=no
83 | BitmapSetNoUsedIONoPullup=no
84 | FloorPlannerShowFanInNets=yes
85 | FloorPlannerShowFanOutNets=yes
86 | HookTo3rdPartyTextEditor=
87 |
88 |
--------------------------------------------------------------------------------
/f303_ice5_hw/f303_ice5_test/f303_ice5_test_syn.prj:
--------------------------------------------------------------------------------
1 | #-- Synopsys, Inc.
2 | #-- Project file C:\Users\ericb\KBADC\KBADC\lattice\f303_ice5_test\f303_ice5_test\f303_ice5_test_syn.prj
3 | #project files
4 | add_file -verilog -lib work "../src/f303_ice5_test.v"
5 | add_file -verilog -lib work "../src/spi_slave.v"
6 |
7 | #implementation: "f303_ice5_test_Implmnt"
8 | impl -add f303_ice5_test_Implmnt -type fpga
9 |
10 | #implementation attributes
11 | set_option -vlog_std v2001
12 | set_option -project_relative_includes 1
13 |
14 | #device options
15 | set_option -technology SBTiCE5LP
16 | set_option -part iCE5LP4K
17 | set_option -package SG48
18 | set_option -speed_grade
19 | set_option -part_companion ""
20 |
21 | #compilation/mapping options
22 |
23 | # mapper_options
24 | set_option -frequency auto
25 | set_option -write_verilog 0
26 | set_option -write_vhdl 0
27 |
28 | # Silicon Blue iCE5LP
29 | set_option -maxfan 10000
30 | set_option -disable_io_insertion 0
31 | set_option -pipe 1
32 | set_option -retiming 0
33 | set_option -update_models_cp 0
34 | set_option -fixgatedclocks 2
35 | set_option -fixgeneratedclocks 0
36 |
37 | # NFilter
38 | set_option -popfeed 0
39 | set_option -constprop 0
40 | set_option -createhierarchy 0
41 |
42 | # sequential_optimization_options
43 | set_option -symbolic_fsm_compiler 1
44 |
45 | # Compiler Options
46 | set_option -compiler_compatible 0
47 | set_option -resource_sharing 1
48 |
49 | #automatic place and route (vendor) options
50 | set_option -write_apr_constraint 1
51 |
52 | #set result format/file last
53 | project -result_format "edif"
54 | project -result_file ./f303_ice5_test_Implmnt/f303_ice5_test.edf
55 | project -log_file "./f303_ice5_test_Implmnt/f303_ice5_test.srr"
56 | impl -active "f303_ice5_test_Implmnt"
57 | project -run synthesis -clean
58 |
--------------------------------------------------------------------------------
/f303_ice5_hw/src/f303_ice5_test.pcf:
--------------------------------------------------------------------------------
1 | # ##############################################################################
2 |
3 | # iCEcube PCF
4 |
5 | # Version: 2016.02.27810
6 |
7 | # File Generated: May 3 2016 09:34:27
8 |
9 | # Family & Device: iCE5LP4K
10 |
11 | # Package: SG48
12 |
13 | # ##############################################################################
14 |
15 | ###IOSet List 4
16 | set_io SPI_MISO 14
17 | set_io SPI_SCLK 15
18 | set_io SPI_CSL 16
19 | set_io SPI_MOSI 17
20 |
21 |
--------------------------------------------------------------------------------
/f303_ice5_hw/src/f303_ice5_test.v:
--------------------------------------------------------------------------------
1 | // lattice ice5lp4k i2s osc + spi_slave + R G B blinky
2 | // 05-02-16 E. Brombaugh
3 |
4 | module f303_ice5_test(
5 | // I2S output
6 | output mclk,
7 | output sdout,
8 | output sclk,
9 | output lrck,
10 |
11 | // SPI slave port
12 | input SPI_CSL,
13 | input SPI_MOSI,
14 | output SPI_MISO,
15 | input SPI_SCLK,
16 |
17 | // RGB output
18 | output wire o_red,
19 | output wire o_green,
20 | output wire o_blue
21 | );
22 |
23 | // This should be unique so firmware knows who it's talking to
24 | parameter DESIGN_ID = 32'hDEADBEEF;
25 |
26 | //------------------------------
27 | // Instantiate HF Osc with div 1
28 | //------------------------------
29 | wire clk;
30 | SB_HFOSC #(.CLKHF_DIV("0b00")) OSCInst0 (
31 | .CLKHFEN(1'b1),
32 | .CLKHFPU(1'b1),
33 | .CLKHF(clk)
34 | ) /* synthesis ROUTE_THROUGH_FABRIC= 0 */;
35 |
36 | //------------------------------
37 | // reset generator
38 | //------------------------------
39 | reg [3:0] reset_pipe = 4'hf;
40 | reg reset = 1'b1;
41 | always @(posedge clk)
42 | begin
43 | reset <= |reset_pipe;
44 | reset_pipe <= {reset_pipe[2:0],1'b0};
45 | end
46 |
47 | //------------------------------
48 | // Internal SPI slave port
49 | //------------------------------
50 | wire [31:0] wdat;
51 | reg [31:0] rdat;
52 | wire [6:0] addr;
53 | wire re, we, spi_slave_miso;
54 | spi_slave
55 | uspi(.clk(clk), .reset(reset),
56 | .spiclk(SPI_SCLK), .spimosi(SPI_MOSI),
57 | .spimiso(SPI_MISO), .spicsl(SPI_CSL),
58 | .we(we), .re(re), .wdat(wdat), .addr(addr), .rdat(rdat));
59 |
60 | //------------------------------
61 | // Writeable registers
62 | //------------------------------
63 | reg [13:0] cnt_limit_reg;
64 | reg [31:0] freq;
65 | reg gate;
66 | always @(posedge clk)
67 | if(reset)
68 | begin
69 | cnt_limit_reg <= 14'd2499; // 1/4 sec blink rate
70 | end
71 | else if(we)
72 | case(addr)
73 | 7'h01: cnt_limit_reg <= wdat;
74 | endcase
75 |
76 | //------------------------------
77 | // readback
78 | //------------------------------
79 | always @(*)
80 | case(addr)
81 | 7'h00: rdat = DESIGN_ID;
82 | 7'h01: rdat = cnt_limit_reg;
83 | default: rdat = 32'd0;
84 | endcase
85 |
86 | // Audio Sample rate enable
87 | wire audio_ena;
88 |
89 | //------------------------------
90 | // Instantiate LF Osc
91 | //------------------------------
92 | wire CLKLF;
93 | SB_LFOSC OSCInst1 (
94 | .CLKLFEN(1'b1),
95 | .CLKLFPU(1'b1),
96 | .CLKLF(CLKLF)
97 | ) /* synthesis ROUTE_THROUGH_FABRIC= 0 */;
98 |
99 | //------------------------------
100 | // Divide the clock
101 | //------------------------------
102 | reg [13:0] clkdiv;
103 | reg onepps;
104 | always @(posedge CLKLF)
105 | begin
106 | if(clkdiv == 14'd0)
107 | begin
108 | onepps <= 1'b1;
109 | clkdiv <= cnt_limit_reg;
110 | end
111 | else
112 | begin
113 | onepps <= 1'b0;
114 | clkdiv <= clkdiv - 14'd1;
115 | end
116 | end
117 |
118 | //------------------------------
119 | // LED signals
120 | //------------------------------
121 | reg [2:0] state;
122 | always @(posedge CLKLF)
123 | begin
124 | if(onepps)
125 | state <= state + 3'd1;
126 | end
127 |
128 | //------------------------------
129 | // Instantiate RGB DRV
130 | //------------------------------
131 | wire red_pwm_i = state[0];
132 | wire grn_pwm_i = state[1];
133 | wire blu_pwm_i = state[2];
134 | SB_RGB_DRV RGB_DRIVER (
135 | .RGBLEDEN (1'b1), // Enable current for all 3 RGB LED pins
136 | .RGB0PWM (red_pwm_i), // Input to drive RGB0 - from LEDD HardIP
137 | .RGB1PWM (grn_pwm_i), // Input to drive RGB1 - from LEDD HardIP
138 | .RGB2PWM (blu_pwm_i), // Input to drive RGB2 - from LEDD HardIP
139 | .RGBPU (led_power_up_i), //Connects to LED_DRV_CUR primitive
140 | .RGB0 (o_red),
141 | .RGB1 (o_green),
142 | .RGB2 (o_blue)
143 | );
144 | defparam RGB_DRIVER.RGB0_CURRENT = "0b000111";
145 | defparam RGB_DRIVER.RGB1_CURRENT = "0b000111";
146 | defparam RGB_DRIVER.RGB2_CURRENT = "0b000111";
147 |
148 | //------------------------------
149 | // Instantiate LED CUR DRV
150 | //------------------------------
151 | SB_LED_DRV_CUR LED_CUR_inst (
152 | .EN (1'b1), //Enable to supply reference current to the LED drivers
153 | .LEDPU (led_power_up_i) //Connects to SB_RGB_DRV primitive
154 | );
155 |
156 | endmodule
157 |
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/f303_ice5_hw/src/spi_slave.v:
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1 | // spi_slave.v: SPI Bus interface for 128 x 32
2 | // 2009-02-28 E. Brombaugh
3 | // 2009-03-22 E. Brombaugh - backported early read logic
4 | //
5 | // This is a simple SPI (serial peripheral interface) slave module.
6 | // These SPI parameters are used in this module:
7 | // CPOL = 0 (spiclk idles low)
8 | // CPHA = 0 (data clocked in on rising edge when CPOL is 1)
9 | //
10 | // Note: addr/wdat are synchronous to the SPI clock. we & re are synchronized
11 | //
12 | // A SPI transfer consists of 40 bits, MSB first.
13 | // The first bit is read/write_n.
14 | // The next 7 are address bits.
15 | // The last 32 are data bits
16 | // Read data is sent in current transfer based on early address/direction
17 |
18 | `timescale 1 ns/1 ps
19 |
20 | module spi_slave(clk, reset,
21 | spiclk, spimosi, spimiso, spicsl,
22 | we, re, wdat, addr, rdat);
23 | parameter asz = 7; // address size
24 | parameter dsz = 32; // databus word size
25 |
26 | input clk; // System clock
27 | input reset; // System POR
28 | input spiclk; // ARM SPI Clock output
29 | input spimosi; // ARM SPI Master Out Slave In
30 | output spimiso; // ARM SPI Master In Slave Out
31 | input spicsl; // ARM SPI Chip Select Low
32 | output we; // Write Enable
33 | output re; // Read enable
34 | output [dsz-1:0] wdat; // write databus
35 | output [asz-1:0] addr; // address
36 | input [dsz-1:0] rdat; // read databus
37 |
38 | // SPI Posedge Process
39 | reg [5:0] mosi_cnt; // input bit counter
40 | reg [dsz-1:0] mosi_shift; // shift reg
41 | reg rd; // direction flag
42 | reg [asz-1:0] addr; // address bits
43 | reg eoa; // end of address flag
44 | reg re; // read flag
45 | reg [dsz-1:0] wdat; // write data reg
46 | reg eot; // end of transfer flag
47 | wire spi_reset = reset | spicsl; // combined reset
48 | always@(posedge spiclk or posedge spi_reset)
49 | if (spi_reset)
50 | begin
51 | mosi_cnt <= 'b0;
52 | mosi_shift <= 32'h0;
53 | eoa <= 'b0;
54 | rd <= 'b0;
55 | eot <= 'b0;
56 | end
57 | else
58 | begin
59 | // Counter keeps track of bits received
60 | mosi_cnt <= mosi_cnt + 1;
61 |
62 | // Shift register grabs incoming data
63 | mosi_shift <= {mosi_shift[dsz-2:0], spimosi};
64 |
65 | // Grab Read bit
66 | if(mosi_cnt == 0)
67 | rd <= spimosi;
68 |
69 | // Grab Address
70 | if(mosi_cnt == asz)
71 | begin
72 | addr <= {mosi_shift[asz-2:0],spimosi};
73 | eoa <= 1'b1;
74 | end
75 |
76 | // Generate Read pulse
77 | re <= rd & (mosi_cnt == asz);
78 |
79 | if(mosi_cnt == (asz+dsz))
80 | begin
81 | // Grab data
82 | wdat <= {mosi_shift[dsz-2:0],spimosi};
83 |
84 | // End-of-transmission (used to generate Write pulse)
85 | eot <= 1'b1;
86 | end
87 | end
88 |
89 | // outgoing shift register is clocked on falling edge
90 | reg [dsz-1:0] miso_shift;
91 | always @(negedge spiclk or posedge spi_reset)
92 | if (spi_reset)
93 | begin
94 | miso_shift <= 32'h0;
95 | end
96 | else
97 | begin
98 | if(re)
99 | miso_shift <= rdat;
100 | else
101 | miso_shift <= {miso_shift[dsz-2:0],1'b0};
102 | end
103 |
104 | // MISO is just msb of shift reg
105 | assign spimiso = eoa ? miso_shift[dsz-1] : 1'b0;
106 |
107 | // Delay/Sync & edge detect on eot to generate we
108 | reg [2:0] we_dly;
109 | reg we;
110 | always @(posedge clk)
111 | if(reset)
112 | begin
113 | we_dly <= 0;
114 | we <= 0;
115 | end
116 | else
117 | begin
118 | we_dly <= {we_dly[1:0],eot};
119 | we <= ~we_dly[2] & we_dly[1] & ~rd;
120 | end
121 | endmodule
122 |
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