├── f030_r820t2 ├── flash_cmd.gdb ├── STM32F030R8_FLASH.ld ├── .gdbinit ├── openocd.cfg ├── systick.h ├── cmd.h ├── usart.h ├── led.h ├── r820t2.h ├── systick.c ├── led.c ├── README.TXT ├── main.c ├── Makefile ├── CMSIS │ ├── system_stm32f0xx.h │ ├── startup_stm32f030.s │ └── system_stm32f0xx.c ├── StdPeriph │ ├── stm32f0xx_conf.h │ ├── stm32f0xx_wwdg.h │ ├── stm32f0xx_dbgmcu.h │ ├── stm32f0xx_misc.h │ ├── stm32f0xx_iwdg.h │ ├── stm32f0xx_crc.h │ ├── stm32f0xx_misc.c │ ├── stm32f0xx_pwr.h │ ├── stm32f0xx_dbgmcu.c │ ├── stm32f0xx_crs.h │ ├── stm32f0xx_wwdg.c │ ├── stm32f0xx_exti.h │ ├── stm32f0xx_comp.h │ ├── stm32f0xx_exti.c │ ├── stm32f0xx_iwdg.c │ ├── stm32f0xx_crc.c │ └── stm32f0xx_cec.h ├── printf.h ├── usart.c ├── printf.c └── cmd.c ├── doc ├── r820t2_breakout_bom.ods ├── r820t2_breakout_bom.pdf ├── r820t2_breakout_sch.pdf ├── r820t2_breakout_gerber.zip ├── R820T2_Register_Description.pdf └── R820T-Rafael Microelectronics.pdf ├── README.md └── r820t2_breakout ├── r820t2_breakout-rescue.lib ├── LICENSE ├── r820t2_breakout.pro ├── r820t2_breakout.csv └── r820t2_breakout-cache.lib /f030_r820t2/flash_cmd.gdb: -------------------------------------------------------------------------------- 1 | attach_swd 2 | 3 | flash 4 | 5 | quit 6 | -------------------------------------------------------------------------------- /doc/r820t2_breakout_bom.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emeb/r820t2/HEAD/doc/r820t2_breakout_bom.ods -------------------------------------------------------------------------------- /doc/r820t2_breakout_bom.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emeb/r820t2/HEAD/doc/r820t2_breakout_bom.pdf -------------------------------------------------------------------------------- /doc/r820t2_breakout_sch.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emeb/r820t2/HEAD/doc/r820t2_breakout_sch.pdf -------------------------------------------------------------------------------- /doc/r820t2_breakout_gerber.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emeb/r820t2/HEAD/doc/r820t2_breakout_gerber.zip -------------------------------------------------------------------------------- /f030_r820t2/STM32F030R8_FLASH.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emeb/r820t2/HEAD/f030_r820t2/STM32F030R8_FLASH.ld -------------------------------------------------------------------------------- /doc/R820T2_Register_Description.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emeb/r820t2/HEAD/doc/R820T2_Register_Description.pdf -------------------------------------------------------------------------------- /doc/R820T-Rafael Microelectronics.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emeb/r820t2/HEAD/doc/R820T-Rafael Microelectronics.pdf -------------------------------------------------------------------------------- /f030_r820t2/.gdbinit: -------------------------------------------------------------------------------- 1 | define flash 2 | file main.elf 3 | load 4 | end 5 | 6 | define restart 7 | run 8 | end 9 | 10 | define attach_swd 11 | mon swdp_scan 12 | attach 1 13 | end 14 | 15 | file main.elf 16 | target extended-remote /dev/ttyACM0 17 | 18 | set mem inaccessible-by-default off -------------------------------------------------------------------------------- /f030_r820t2/openocd.cfg: -------------------------------------------------------------------------------- 1 | # This is an STM32F051 discovery board with a single STM32F051R8 chip. 2 | # 3 | 4 | source [find interface/stlink-v2.cfg] 5 | transport select hla_swd 6 | 7 | #set CPUTAPID 0x0bc11477 8 | source [find target/stm32f3x.cfg] 9 | 10 | reset_config none 11 | 12 | init 13 | -------------------------------------------------------------------------------- /f030_r820t2/systick.h: -------------------------------------------------------------------------------- 1 | /* 2 | * systick.h - systick routines 3 | */ 4 | 5 | #ifndef __systick__ 6 | #define __systick__ 7 | 8 | #include "stm32f0xx.h" 9 | 10 | void systick_init(void); 11 | void systick_delayms(uint32_t ms); 12 | uint32_t systick_gettick(void); 13 | 14 | #endif 15 | -------------------------------------------------------------------------------- /f030_r820t2/cmd.h: -------------------------------------------------------------------------------- 1 | /* 2 | * cmd.h - Command parsing routines for STM32F030 breakout 3 | * 02-15-17 E. Brombaugh 4 | */ 5 | 6 | #ifndef __cmd__ 7 | #define __cmd__ 8 | 9 | #include "stm32f0xx.h" 10 | 11 | extern void init_cmd(void); 12 | extern void cmd_parse(char ch); 13 | 14 | #endif 15 | -------------------------------------------------------------------------------- /f030_r820t2/usart.h: -------------------------------------------------------------------------------- 1 | /* 2 | * usart.h - serial i/o routines for STM32F030F4 3 | * 05-30-15 E. Brombaugh 4 | */ 5 | 6 | #ifndef __usart__ 7 | #define __usart__ 8 | 9 | #include "stm32f0xx.h" 10 | 11 | void usart_init(void); 12 | int usart_getc(void); 13 | void usart_putc(void* p, char c); 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /f030_r820t2/led.h: -------------------------------------------------------------------------------- 1 | /* 2 | * led.c - f030 breakout LED setup 3 | */ 4 | 5 | #ifndef __led__ 6 | #define __led__ 7 | 8 | #include "stm32f0xx.h" 9 | 10 | #define LED1 (1 << 1) /* port B bit 1 */ 11 | 12 | void led_init(void); 13 | void led_on(uint32_t LED); 14 | void led_off(uint32_t LED); 15 | void led_toggle(uint32_t LED); 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # r820t2 2 | Breakout PCB design and STM32F0 firmware for the Rafael R820T2 tuner chip 3 | 4 | Contents 5 | -------- 6 | 7 | doc - documents for the chip and PCB design. This includes both the orginal 8 | mfgs datasheet as well as schematic and BOM for the PCB design. 9 | 10 | f030_r820t2 - STM32F030 firmware. A simple serial command line interface 11 | to access registers and set frequency & gain parameters. 12 | 13 | r820t2_breakout - KiCAD PCB design. 14 | 15 | 16 | LICENSE 17 | ------- 18 | 19 | The PCB design is licensed separately from the driver code. Please see 20 | the LICENSE files within each sub-directory. -------------------------------------------------------------------------------- /r820t2_breakout/r820t2_breakout-rescue.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # LD1117S33CTR-RESCUE-r820t2_breakout 5 | # 6 | DEF LD1117S33CTR-RESCUE-r820t2_breakout U 0 30 Y Y 1 F N 7 | F0 "U" 0 250 50 H V C CNN 8 | F1 "LD1117S33CTR-RESCUE-r820t2_breakout" 0 200 50 H V C CNN 9 | F2 "SOT-223" 0 100 50 H V C CNN 10 | F3 "" 0 0 50 H V C CNN 11 | $FPLIST 12 | SOT223 13 | $ENDFPLIST 14 | DRAW 15 | S -250 -150 250 150 0 1 10 f 16 | X GND 1 0 -250 100 U 40 40 1 1 W 17 | X VO 2 400 50 150 L 40 40 1 1 w 18 | X VI 3 -400 50 150 R 40 40 1 1 W 19 | X tab 4 400 -50 150 L 50 50 1 1 I 20 | ENDDRAW 21 | ENDDEF 22 | # 23 | #End Library 24 | -------------------------------------------------------------------------------- /f030_r820t2/r820t2.h: -------------------------------------------------------------------------------- 1 | /* 2 | * r820t2.h - R820T2 downconverter driver for STM32F030 3 | * 02-12-2017 E. Brombaugh 4 | */ 5 | 6 | #ifndef __r820t2__ 7 | #define __r820t2__ 8 | 9 | #include "stm32f0xx.h" 10 | 11 | extern uint32_t r820t_freq; 12 | extern uint32_t r820t_xtal_freq; 13 | extern uint32_t r820t_if_freq; 14 | 15 | void R820T2_init(void); 16 | void R820T2_i2c_write_reg(uint8_t reg, uint8_t data); 17 | void R820T2_i2c_read_raw(uint8_t *data, uint8_t sz); 18 | uint8_t R820T2_i2c_read_reg_uncached(uint8_t reg); 19 | uint8_t R820T2_i2c_read_reg_cached(uint8_t reg); 20 | void R820T2_set_freq(uint32_t freq); 21 | void R820T2_set_lna_gain(uint8_t gain_index); 22 | void R820T2_set_mixer_gain(uint8_t gain_index); 23 | void R820T2_set_vga_gain(uint8_t gain_index); 24 | void R820T2_set_lna_agc(uint8_t value); 25 | void R820T2_set_mixer_agc(uint8_t value); 26 | void R820T2_set_if_bandwidth(uint8_t bw); 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /f030_r820t2/systick.c: -------------------------------------------------------------------------------- 1 | /* 2 | * systick.c - systick routines 3 | */ 4 | 5 | #include "systick.h" 6 | 7 | static __IO uint32_t TimingDelay, Ticks; 8 | 9 | /* 10 | * init the system tick infrastructure 11 | */ 12 | void systick_init(void) 13 | { 14 | Ticks = 0; 15 | 16 | /* start the 1ms system tick */ 17 | if (SysTick_Config(SystemCoreClock / 1000)) 18 | { 19 | /* Capture error */ 20 | while (1); 21 | } 22 | } 23 | 24 | /* 25 | * blocking delay for number of milliseconds 26 | */ 27 | void systick_delayms(uint32_t ms) 28 | { 29 | TimingDelay = ms; 30 | 31 | while(TimingDelay != 0); 32 | } 33 | 34 | /* 35 | * Get tick count for nonblocking delays 36 | */ 37 | uint32_t systick_gettick(void) 38 | { 39 | return Ticks; 40 | } 41 | 42 | /* 43 | * IRQ handler 44 | */ 45 | void SysTick_Handler(void) 46 | { 47 | /* update ms delay timer */ 48 | if (TimingDelay != 0x00) 49 | { 50 | TimingDelay--; 51 | } 52 | 53 | Ticks++; 54 | } 55 | 56 | -------------------------------------------------------------------------------- /f030_r820t2/led.c: -------------------------------------------------------------------------------- 1 | /* 2 | * led.c - f030 breakout LED setup 3 | */ 4 | 5 | #include "led.h" 6 | 7 | /* 8 | * Initialize the breakout board LED 9 | */ 10 | void led_init(void) 11 | { 12 | GPIO_InitTypeDef GPIO_InitStructure; 13 | 14 | /* turn on clock for LED GPIO */ 15 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); 16 | 17 | /* Enable PB1 for output */ 18 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; 19 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; 20 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 21 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 22 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; 23 | GPIO_Init(GPIOB, &GPIO_InitStructure); 24 | } 25 | 26 | /* 27 | * Turn on LED 28 | */ 29 | void led_on(uint32_t LED) 30 | { 31 | GPIOB->ODR |= LED; 32 | } 33 | 34 | /* 35 | * Turn off LED 36 | */ 37 | void led_off(uint32_t LED) 38 | { 39 | GPIOB->ODR &= ~LED; 40 | } 41 | 42 | /* 43 | * Toggle LED 44 | */ 45 | void led_toggle(uint32_t LED) 46 | { 47 | GPIOB->ODR ^= LED; 48 | } 49 | 50 | -------------------------------------------------------------------------------- /f030_r820t2/README.TXT: -------------------------------------------------------------------------------- 1 | README.TXT 2 | 3 | Building 4 | -------- 5 | 6 | Just run 7 | make 8 | 9 | Flashing 10 | -------- 11 | 12 | 1) Ensure openocd isn't running as a server already. 13 | 14 | 2) Make sure that your STM32F0 Discovery board is connected via USB and the 15 | ST-LINK jumpers are set correctly (this example is for the on-board processor, 16 | so 1-2 and 3-4 should be shorted) 17 | 18 | 3) run 19 | make flash 20 | 21 | 4) Done! 22 | 23 | Debugging 24 | --------- 25 | 26 | 1) in a separate window start up openocd as a GDB server 27 | openocd -f openocd.cfg 28 | 29 | 2) run gdb with your favorite UI 30 | ddd --debugger arm-none-eabi-gdb main.elf 31 | 32 | 3) connect to the server within gdb 33 | target extended-remote localhost:3333 34 | 35 | 4) Start debugging! 36 | 37 | LICENSE 38 | ------- 39 | 40 | The r820t2 driver code (r820t2.[ch]) herein originated with the Airspy product 41 | which derived from the Linux driver. Consequently my revisions are subject to 42 | the LICENSE file from those projects. 43 | 44 | The CMSIS and StdPeriph directories are from ARM ans ST Microelectronics and 45 | are suject to the licenses therein. 46 | 47 | -------------------------------------------------------------------------------- /r820t2_breakout/LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 Eric Brombaugh 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /f030_r820t2/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * STM32F030 driver for R820T2 3 | * E. Brombaugh 02-12-2017 4 | */ 5 | 6 | #include 7 | #include 8 | #include 9 | #include "stm32f0xx.h" 10 | #include "led.h" 11 | #include "systick.h" 12 | #include "usart.h" 13 | #include "printf.h" 14 | #include "r820t2.h" 15 | #include "cmd.h" 16 | 17 | int main(void) 18 | { 19 | uint8_t regs[32], reg; 20 | int rxchar; 21 | uint32_t i, tick; 22 | 23 | /* initialize the hardware */ 24 | led_init(); 25 | systick_init(); 26 | usart_init(); 27 | init_printf(0,usart_putc); 28 | 29 | /* Startup message */ 30 | printf("\r\nSTM32F030 R820T2 driver.\n\r"); 31 | 32 | /* init R820T2 */ 33 | R820T2_init(); 34 | printf("R820T2 initialized.\n\r"); 35 | 36 | /* Loop forever */ 37 | init_cmd(); 38 | tick = systick_gettick() + 100; 39 | while(1) 40 | { 41 | /* UART command processing */ 42 | if((rxchar = usart_getc())!= EOF) 43 | { 44 | /* Parse commands */ 45 | cmd_parse(rxchar); 46 | } 47 | 48 | /* nonblocking wait to flash light */ 49 | if(tick < systick_gettick()) 50 | { 51 | led_toggle(LED1); 52 | tick = systick_gettick() + 100; 53 | } 54 | } 55 | } 56 | -------------------------------------------------------------------------------- /r820t2_breakout/r820t2_breakout.pro: -------------------------------------------------------------------------------- 1 | update=Wed 15 Feb 2017 08:21:47 AM MST 2 | version=1 3 | last_client=kicad 4 | [pcbnew] 5 | version=1 6 | LastNetListRead= 7 | UseCmpFile=1 8 | PadDrill=0.600000000000 9 | PadDrillOvalY=0.600000000000 10 | PadSizeH=1.500000000000 11 | PadSizeV=1.500000000000 12 | PcbTextSizeV=1.500000000000 13 | PcbTextSizeH=1.500000000000 14 | PcbTextThickness=0.300000000000 15 | ModuleTextSizeV=1.000000000000 16 | ModuleTextSizeH=1.000000000000 17 | ModuleTextSizeThickness=0.150000000000 18 | SolderMaskClearance=0.000000000000 19 | SolderMaskMinWidth=0.000000000000 20 | DrawSegmentWidth=0.200000000000 21 | BoardOutlineThickness=0.100000000000 22 | ModuleOutlineThickness=0.150000000000 23 | [cvpcb] 24 | version=1 25 | NetIExt=net 26 | [general] 27 | version=1 28 | [eeschema] 29 | version=1 30 | LibDir= 31 | [eeschema/libraries] 32 | LibName1=r820t2_breakout-rescue 33 | LibName2=power 34 | LibName3=device 35 | LibName4=transistors 36 | LibName5=conn 37 | LibName6=linear 38 | LibName7=regul 39 | LibName8=74xx 40 | LibName9=cmos4000 41 | LibName10=adc-dac 42 | LibName11=memory 43 | LibName12=xilinx 44 | LibName13=microcontrollers 45 | LibName14=dsp 46 | LibName15=microchip 47 | LibName16=analog_switches 48 | LibName17=motorola 49 | LibName18=texas 50 | LibName19=intel 51 | LibName20=audio 52 | LibName21=interface 53 | LibName22=digital-audio 54 | LibName23=philips 55 | LibName24=display 56 | LibName25=cypress 57 | LibName26=siliconi 58 | LibName27=opto 59 | LibName28=atmel 60 | LibName29=contrib 61 | LibName30=valves 62 | LibName31=/home/ericb/KBADC/kicad/library/emeb_library 63 | [schematic_editor] 64 | version=1 65 | PageLayoutDescrFile= 66 | PlotDirectoryName= 67 | SubpartIdSeparator=0 68 | SubpartFirstId=65 69 | NetFmtName=Pcbnew 70 | SpiceForceRefPrefix=0 71 | SpiceUseNetNumbers=0 72 | LabSize=60 73 | -------------------------------------------------------------------------------- /f030_r820t2/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for STM32F030 2 | # 03-30-2015 E. Brombaugh 3 | 4 | # sub directories 5 | VPATH = .:CMSIS:StdPeriph 6 | 7 | # Object files 8 | OBJECTS = startup_stm32f030.o system_stm32f0xx.o main.o systick.o led.o \ 9 | r820t2.o printf.o usart.o cmd.o \ 10 | stm32f0xx_rcc.o stm32f0xx_gpio.o stm32f0xx_i2c.o stm32f0xx_usart.o \ 11 | stm32f0xx_adc.o stm32f0xx_dma.o stm32f0xx_misc.o 12 | 13 | # Must define the MCU type 14 | CDEFS=-DSTM32F030 -DUSE_STDPERIPH_DRIVER 15 | 16 | # Linker script 17 | LDSCRIPT = STM32F030R8_FLASH.ld 18 | 19 | # Compiler Flags 20 | OPTLVL:=s # Optimization level, can be [0, 1, 2, 3, s]. 21 | COMMONFLAGS=-O$(OPTLVL) -g -ffunction-sections -std=c99 -Wall 22 | MCUFLAGS=-mthumb -mcpu=cortex-m0 23 | CFLAGS=$(COMMONFLAGS) $(MCUFLAGS) -I. -ICMSIS -IStdPeriph $(CDEFS) 24 | LDFLAGS=$(COMMONFLAGS) $(MCUFLAGS) -fno-exceptions \ 25 | -fdata-sections -nostartfiles -Wl,--gc-sections,-T$(LDSCRIPT),-Map=main.map 26 | 27 | # Executables 28 | ARCH = arm-none-eabi 29 | CC = $(ARCH)-gcc 30 | LD = $(ARCH)-ld -v 31 | AS = $(ARCH)-as 32 | OBJCPY = $(ARCH)-objcopy 33 | OBJDMP = $(ARCH)-objdump 34 | GDB = $(ARCH)-gdb 35 | OPENOCD = openocd 36 | 37 | CPFLAGS = --output-target=binary 38 | ODFLAGS = -x --syms 39 | 40 | # Targets 41 | all: main.bin 42 | 43 | clean: 44 | -rm -f $(OBJECTS) *.lst *.elf *.bin *.dmp *.map 45 | 46 | flash: gdb_flash 47 | 48 | gdb_flash: main.elf 49 | $(GDB) -x flash_cmd.gdb -batch 50 | stty sane 51 | 52 | openocd_flash: main.elf 53 | $(OPENOCD) -f openocd.cfg -c "program main.elf verify reset" 54 | 55 | disassemble: main.elf 56 | $(OBJDMP) -d main.elf > main.dis 57 | 58 | dist: 59 | tar -c *.h *.c *.s Makefile *.cmd *.cfg openocd_doflash | gzip > minimal_hello_world.tar.gz 60 | 61 | main.ihex: main.elf 62 | $(OBJCPY) --output-target=ihex main.elf main.ihex 63 | 64 | main.bin: main.elf 65 | $(OBJCPY) $(CPFLAGS) main.elf main.bin 66 | $(OBJDMP) $(ODFLAGS) main.elf > main.dmp 67 | ls -l main.elf main.bin 68 | 69 | main.elf: $(OBJECTS) $(LDSCRIPT) 70 | $(CC) -o main.elf $(LDFLAGS) $(OBJECTS) -lnosys -lm 71 | 72 | %.o: %.c %.h 73 | $(CC) $(CFLAGS) -c -o $@ $< 74 | 75 | -------------------------------------------------------------------------------- /f030_r820t2/CMSIS/system_stm32f0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f0xx.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2014 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /** @addtogroup CMSIS 29 | * @{ 30 | */ 31 | 32 | /** @addtogroup stm32f0xx_system 33 | * @{ 34 | */ 35 | 36 | /** 37 | * @brief Define to prevent recursive inclusion 38 | */ 39 | #ifndef __SYSTEM_STM32F0XX_H 40 | #define __SYSTEM_STM32F0XX_H 41 | 42 | #ifdef __cplusplus 43 | extern "C" { 44 | #endif 45 | 46 | /** @addtogroup STM32F0xx_System_Includes 47 | * @{ 48 | */ 49 | 50 | /** 51 | * @} 52 | */ 53 | 54 | 55 | /** @addtogroup STM32F0xx_System_Exported_types 56 | * @{ 57 | */ 58 | 59 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @addtogroup STM32F0xx_System_Exported_Constants 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @addtogroup STM32F0xx_System_Exported_Macros 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @addtogroup STM32F0xx_System_Exported_Functions 82 | * @{ 83 | */ 84 | 85 | extern void SystemInit(void); 86 | extern void SystemCoreClockUpdate(void); 87 | /** 88 | * @} 89 | */ 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif /*__SYSTEM_STM32F0XX_H */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** 102 | * @} 103 | */ 104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 105 | -------------------------------------------------------------------------------- /r820t2_breakout/r820t2_breakout.csv: -------------------------------------------------------------------------------- 1 | Reference, Value, Footprint,Cnt,Qty,Mfg P/N,Distributor,Distributor P/N,Notes 2 | C101,0.01uf,Capacitors_SMD:C_0603_HandSoldering,1,1,,,, 3 | C108,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 4 | C116,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 5 | C117,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 6 | C104,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 7 | C109,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 8 | C113,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 9 | C114,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 10 | C118,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 11 | C121,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 12 | C103,0.1uf,Capacitors_SMD:C_0603_HandSoldering,1,10,C1608X7R1E104K080AA,Digi-Key,445-1316-1-ND, 13 | C106,1uf,Capacitors_SMD:C_0603_HandSoldering,1,1,GCM188R71E105KA64D,Mouser,81-GCM188R71E105KA4D, 14 | C110,27pf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 15 | C111,27pf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 16 | C105,27pf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 17 | C107,27pf,Capacitors_SMD:C_0603_HandSoldering,1,4,,,, 18 | C102,330pf,Capacitors_SMD:C_0603_HandSoldering,1,,,,, 19 | C119,330pf,Capacitors_SMD:C_0603_HandSoldering,1,2,,,, 20 | C120,6800pf,Capacitors_SMD:C_0603_HandSoldering,1,1,,,, 21 | C112,10uf,Capacitors_SMD:C_0805_HandSoldering,1,,,,, 22 | C115,10uf,Capacitors_SMD:C_0805_HandSoldering,1,2,EMK212BB7106MG-T,Mouser,963-EMK212BB7106MG-T, 23 | P102,DNI,Connect:PINTST,1,,,,, 24 | P103,DNI,Connect:PINTST,1,,,,, 25 | P108,DNI,Connect:PINTST,1,,,,, 26 | P106,DNI,Connect:PINTST,1,,,,, 27 | P104,DNI,Connect:PINTST,1,,,,, 28 | P107,DNI,Connect:PINTST,1,,,,, 29 | P105,DNI,Connect:PINTST,1,7,,,, 30 | U101,TWEAALSANF-28.800000,Crystals:Crystal_SMD_Abracon_ABM3C-4pin_5.0x3.2mm,1,1,,,, 31 | Y101,28.8MHz,Crystals:Crystal_SMD_HC49-SD,1,1,,,, 32 | T101,TRANSFO4,footprints:Pulse_SMD_Balun,1,1,,,, 33 | U102,R820T2,footprints:QFN-24-1EP_4x4mm_Pitch0.5mm_extended_pad,1,1,,,, 34 | J101,SMA,footprints:SMA_END,1,,,,, 35 | J102,SMA,footprints:SMA_END,1,2,,,, 36 | P101,CONN_01X04,Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm,1,1,,,, 37 | R111,0,Resistors_SMD:R_0603_HandSoldering,1,,,,, 38 | R105,0,Resistors_SMD:R_0603_HandSoldering,1,2,,,, 39 | R106,10,Resistors_SMD:R_0603_HandSoldering,1,1,,,, 40 | R101,220,Resistors_SMD:R_0603_HandSoldering,1,,,,, 41 | R102,220,Resistors_SMD:R_0603_HandSoldering,1,,,,, 42 | R107,220,Resistors_SMD:R_0603_HandSoldering,1,,,,, 43 | R108,220,Resistors_SMD:R_0603_HandSoldering,1,4,,,, 44 | R112,10k,Resistors_SMD:R_0603_HandSoldering,1,1,,,, 45 | L102,150nh,Resistors_SMD:R_0603_HandSoldering,1,,,,, 46 | L103,150nh,Resistors_SMD:R_0603_HandSoldering,1,2,,,, 47 | R110,1k8,Resistors_SMD:R_0603_HandSoldering,1,1,,,, 48 | R103,4k7,Resistors_SMD:R_0603_HandSoldering,1,,,,, 49 | R104,4k7,Resistors_SMD:R_0603_HandSoldering,1,2,,,, 50 | L101,8.2nH,Resistors_SMD:R_0603_HandSoldering,1,1,,,, 51 | R109,DNI,Resistors_SMD:R_0603_HandSoldering,1,1,,,, 52 | U103,LD1117S33CTR,SOT-223,1,1,,,, 53 | D101,BAV99,TO_SOT_Packages_SMD:SOT-23,1,1,,,, 54 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_conf.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2014 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __STM32F0XX_CONF_H 30 | #define __STM32F0XX_CONF_H 31 | 32 | /* Includes ------------------------------------------------------------------*/ 33 | /* Comment the line below to disable peripheral header file inclusion */ 34 | #include "stm32f0xx_adc.h" 35 | #include "stm32f0xx_can.h" 36 | #include "stm32f0xx_cec.h" 37 | #include "stm32f0xx_crc.h" 38 | #include "stm32f0xx_crs.h" 39 | #include "stm32f0xx_comp.h" 40 | #include "stm32f0xx_dac.h" 41 | #include "stm32f0xx_dbgmcu.h" 42 | #include "stm32f0xx_dma.h" 43 | #include "stm32f0xx_exti.h" 44 | #include "stm32f0xx_flash.h" 45 | #include "stm32f0xx_gpio.h" 46 | #include "stm32f0xx_syscfg.h" 47 | #include "stm32f0xx_i2c.h" 48 | #include "stm32f0xx_iwdg.h" 49 | #include "stm32f0xx_pwr.h" 50 | #include "stm32f0xx_rcc.h" 51 | #include "stm32f0xx_rtc.h" 52 | #include "stm32f0xx_spi.h" 53 | #include "stm32f0xx_tim.h" 54 | #include "stm32f0xx_usart.h" 55 | #include "stm32f0xx_wwdg.h" 56 | #include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 57 | 58 | /* Exported types ------------------------------------------------------------*/ 59 | /* Exported constants --------------------------------------------------------*/ 60 | /* Uncomment the line below to expanse the "assert_param" macro in the 61 | Standard Peripheral Library drivers code */ 62 | /* #define USE_FULL_ASSERT 1 */ 63 | 64 | /* Exported macro ------------------------------------------------------------*/ 65 | #ifdef USE_FULL_ASSERT 66 | 67 | /** 68 | * @brief The assert_param macro is used for function's parameters check. 69 | * @param expr: If expr is false, it calls assert_failed function which reports 70 | * the name of the source file and the source line number of the call 71 | * that failed. If expr is true, it returns no value. 72 | * @retval None 73 | */ 74 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 75 | /* Exported functions ------------------------------------------------------- */ 76 | void assert_failed(uint8_t* file, uint32_t line); 77 | #else 78 | #define assert_param(expr) ((void)0) 79 | #endif /* USE_FULL_ASSERT */ 80 | 81 | #endif /* __STM32F0XX_CONF_H */ 82 | 83 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 84 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_wwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_wwdg.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the WWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_WWDG_H 31 | #define __STM32F0XX_WWDG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup WWDG 45 | * @{ 46 | */ 47 | /* Exported types ------------------------------------------------------------*/ 48 | /* Exported constants --------------------------------------------------------*/ 49 | 50 | /** @defgroup WWDG_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup WWDG_Prescaler 55 | * @{ 56 | */ 57 | 58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ 63 | ((PRESCALER) == WWDG_Prescaler_2) || \ 64 | ((PRESCALER) == WWDG_Prescaler_4) || \ 65 | ((PRESCALER) == WWDG_Prescaler_8)) 66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) 67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** 74 | * @} 75 | */ 76 | 77 | /* Exported macro ------------------------------------------------------------*/ 78 | /* Exported functions ------------------------------------------------------- */ 79 | /* Function used to set the WWDG configuration to the default reset state ****/ 80 | void WWDG_DeInit(void); 81 | 82 | /* Prescaler, Refresh window and Counter configuration functions **************/ 83 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 84 | void WWDG_SetWindowValue(uint8_t WindowValue); 85 | void WWDG_EnableIT(void); 86 | void WWDG_SetCounter(uint8_t Counter); 87 | 88 | /* WWDG activation functions **************************************************/ 89 | void WWDG_Enable(uint8_t Counter); 90 | 91 | /* Interrupts and flags management functions **********************************/ 92 | FlagStatus WWDG_GetFlagStatus(void); 93 | void WWDG_ClearFlag(void); 94 | 95 | #ifdef __cplusplus 96 | } 97 | #endif 98 | 99 | #endif /* __STM32F0XX_WWDG_H */ 100 | 101 | /** 102 | * @} 103 | */ 104 | 105 | /** 106 | * @} 107 | */ 108 | 109 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 110 | -------------------------------------------------------------------------------- /f030_r820t2/printf.h: -------------------------------------------------------------------------------- 1 | /* 2 | File: printf.h 3 | 4 | Copyright (C) 2004 Kustaa Nyholm 5 | 6 | This library is free software; you can redistribute it and/or 7 | modify it under the terms of the GNU Lesser General Public 8 | License as published by the Free Software Foundation; either 9 | version 2.1 of the License, or (at your option) any later version. 10 | 11 | This library is distributed in the hope that it will be useful, 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 14 | See the GNU Lesser General Public License for more details. 15 | 16 | You should have received a copy of the GNU Lesser General Public 17 | License along with this library; if not, write to the Free Software 18 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 | 20 | This library is realy just two files: 'printf.h' and 'printf.c'. 21 | 22 | They provide a simple and small (+200 loc) printf functionality to 23 | be used in embedded systems. 24 | 25 | I've found them so usefull in debugging that I do not bother with a 26 | debugger at all. 27 | 28 | They are distributed in source form, so to use them, just compile them 29 | into your project. 30 | 31 | Two printf variants are provided: printf and sprintf. 32 | 33 | The formats supported by this implementation are: 'd' 'u' 'c' 's' 'x' 'X'. 34 | 35 | Zero padding and field width are also supported. 36 | 37 | If the library is compiled with 'PRINTF_SUPPORT_LONG' defined then the 38 | long specifier is also 39 | supported. Note that this will pull in some long math routines (pun intended!) 40 | and thus make your executable noticably longer. 41 | 42 | The memory foot print of course depends on the target cpu, compiler and 43 | compiler options, but a rough guestimate (based on a H8S target) is about 44 | 1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack space. 45 | Not too bad. Your milage may vary. By hacking the source code you can 46 | get rid of some hunred bytes, I'm sure, but personally I feel the balance of 47 | functionality and flexibility versus code size is close to optimal for 48 | many embedded systems. 49 | 50 | To use the printf you need to supply your own character output function, 51 | something like : 52 | 53 | void putc ( void* p, char c) 54 | { 55 | while (!SERIAL_PORT_EMPTY) ; 56 | SERIAL_PORT_TX_REGISTER = c; 57 | } 58 | 59 | Before you can call printf you need to initialize it to use your 60 | character output function with something like: 61 | 62 | init_printf(NULL,putc); 63 | 64 | Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc', 65 | the NULL (or any pointer) you pass into the 'init_printf' will eventually be 66 | passed to your 'putc' routine. This allows you to pass some storage space (or 67 | anything realy) to the character output function, if necessary. 68 | This is not often needed but it was implemented like that because it made 69 | implementing the sprintf function so neat (look at the source code). 70 | 71 | The code is re-entrant, except for the 'init_printf' function, so it 72 | is safe to call it from interupts too, although this may result in mixed output. 73 | If you rely on re-entrancy, take care that your 'putc' function is re-entrant! 74 | 75 | The printf and sprintf functions are actually macros that translate to 76 | 'tfp_printf' and 'tfp_sprintf'. This makes it possible 77 | to use them along with 'stdio.h' printf's in a single source file. 78 | You just need to undef the names before you include the 'stdio.h'. 79 | Note that these are not function like macros, so if you have variables 80 | or struct members with these names, things will explode in your face. 81 | Without variadic macros this is the best we can do to wrap these 82 | fucnction. If it is a problem just give up the macros and use the 83 | functions directly or rename them. 84 | 85 | For further details see source code. 86 | 87 | regs Kusti, 23.10.2004 88 | */ 89 | 90 | 91 | #ifndef __TFP_PRINTF__ 92 | #define __TFP_PRINTF__ 93 | 94 | #include 95 | 96 | void init_printf(void* putp,void (*putf) (void*,char)); 97 | 98 | void tfp_printf(char *fmt, ...); 99 | void tfp_sprintf(char* s,char *fmt, ...); 100 | 101 | void tfp_format(void* putp,void (*putf) (void*,char),char *fmt, va_list va); 102 | 103 | #define printf tfp_printf 104 | #define sprintf tfp_sprintf 105 | 106 | #endif 107 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_dbgmcu.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the DBGMCU firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_DBGMCU_H 31 | #define __STM32F0XX_DBGMCU_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup DBGMCU 45 | * @{ 46 | */ 47 | /* Exported types ------------------------------------------------------------*/ 48 | /* Exported constants --------------------------------------------------------*/ 49 | 50 | 51 | /** @defgroup DBGMCU_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | #define DBGMCU_STOP DBGMCU_CR_DBG_STOP 56 | #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY 57 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00)) 58 | 59 | #define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< Not applicable for STM32F030 devices */ 60 | #define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP 61 | #define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP 62 | #define DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< Only applicable for STM32F072 devices */ 63 | #define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP 64 | #define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP 65 | #define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP 66 | #define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP 67 | #define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 68 | #define DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< Only applicable for STM32F042 and STM32F072 devices */ 69 | #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00)) 70 | 71 | #define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP 72 | #define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP 73 | #define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP 74 | #define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP 75 | #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00)) 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /* Exported macro ------------------------------------------------------------*/ 82 | /* Exported functions ------------------------------------------------------- */ 83 | 84 | /* Device and Revision ID management functions ********************************/ 85 | uint32_t DBGMCU_GetREVID(void); 86 | uint32_t DBGMCU_GetDEVID(void); 87 | 88 | /* Peripherals Configuration functions ****************************************/ 89 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 90 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); 91 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); 92 | 93 | #ifdef __cplusplus 94 | } 95 | #endif 96 | 97 | #endif /* __STM32F0XX_DBGMCU_H */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 108 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_misc.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_MISC_H 31 | #define __STM32F0XX_MISC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup MISC 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /** 51 | * @brief NVIC Init Structure definition 52 | */ 53 | 54 | typedef struct 55 | { 56 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 57 | This parameter can be a value of @ref IRQn_Type 58 | (For the complete STM32 Devices IRQ Channels list, 59 | please refer to stm32f0xx.h file) */ 60 | 61 | uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified 62 | in NVIC_IRQChannel. This parameter can be a value 63 | between 0 and 3. */ 64 | 65 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 66 | will be enabled or disabled. 67 | This parameter can be set either to ENABLE or DISABLE */ 68 | } NVIC_InitTypeDef; 69 | 70 | /** 71 | * 72 | @verbatim 73 | 74 | @endverbatim 75 | */ 76 | 77 | /* Exported constants --------------------------------------------------------*/ 78 | 79 | /** @defgroup MISC_Exported_Constants 80 | * @{ 81 | */ 82 | 83 | /** @defgroup MISC_System_Low_Power 84 | * @{ 85 | */ 86 | 87 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 88 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 89 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 90 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 91 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 92 | ((LP) == NVIC_LP_SLEEPONEXIT)) 93 | /** 94 | * @} 95 | */ 96 | 97 | /** @defgroup MISC_Preemption_Priority_Group 98 | * @{ 99 | */ 100 | #define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04) 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** @defgroup MISC_SysTick_clock_source 107 | * @{ 108 | */ 109 | 110 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 111 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 112 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 113 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 114 | /** 115 | * @} 116 | */ 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | /* Exported macro ------------------------------------------------------------*/ 123 | /* Exported functions ------------------------------------------------------- */ 124 | 125 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 126 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 127 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 128 | 129 | #ifdef __cplusplus 130 | } 131 | #endif 132 | 133 | #endif /* __STM32F0XX_MISC_H */ 134 | 135 | /** 136 | * @} 137 | */ 138 | 139 | /** 140 | * @} 141 | */ 142 | 143 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 144 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_iwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_iwdg.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the IWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_IWDG_H 31 | #define __STM32F0XX_IWDG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup IWDG 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup IWDG_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | /** @defgroup IWDG_WriteAccess 56 | * @{ 57 | */ 58 | 59 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 60 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 61 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 62 | ((ACCESS) == IWDG_WriteAccess_Disable)) 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup IWDG_prescaler 68 | * @{ 69 | */ 70 | 71 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 72 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 73 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 74 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 75 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 76 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 77 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 78 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 79 | ((PRESCALER) == IWDG_Prescaler_8) || \ 80 | ((PRESCALER) == IWDG_Prescaler_16) || \ 81 | ((PRESCALER) == IWDG_Prescaler_32) || \ 82 | ((PRESCALER) == IWDG_Prescaler_64) || \ 83 | ((PRESCALER) == IWDG_Prescaler_128)|| \ 84 | ((PRESCALER) == IWDG_Prescaler_256)) 85 | /** 86 | * @} 87 | */ 88 | 89 | /** @defgroup IWDG_Flag 90 | * @{ 91 | */ 92 | 93 | #define IWDG_FLAG_PVU IWDG_SR_PVU 94 | #define IWDG_FLAG_RVU IWDG_SR_RVU 95 | #define IWDG_FLAG_WVU IWDG_SR_WVU 96 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \ 97 | ((FLAG) == IWDG_FLAG_WVU)) 98 | 99 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) 100 | 101 | #define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) 102 | /** 103 | * @} 104 | */ 105 | 106 | /** 107 | * @} 108 | */ 109 | 110 | /* Exported macro ------------------------------------------------------------*/ 111 | /* Exported functions ------------------------------------------------------- */ 112 | 113 | /* Prescaler and Counter configuration functions ******************************/ 114 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 115 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 116 | void IWDG_SetReload(uint16_t Reload); 117 | void IWDG_ReloadCounter(void); 118 | void IWDG_SetWindowValue(uint16_t WindowValue); 119 | 120 | /* IWDG activation function ***************************************************/ 121 | void IWDG_Enable(void); 122 | 123 | /* Flag management function ***************************************************/ 124 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 125 | 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | 130 | #endif /* __STM32F0XX_IWDG_H */ 131 | 132 | /** 133 | * @} 134 | */ 135 | 136 | /** 137 | * @} 138 | */ 139 | 140 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 141 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_crc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_crc.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the CRC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_CRC_H 31 | #define __STM32F0XX_CRC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /*!< Includes ----------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CRC 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup CRC_ReverseInputData 52 | * @{ 53 | */ 54 | #define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */ 55 | #define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */ 56 | #define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */ 57 | #define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */ 58 | 59 | #define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \ 60 | ((DATA) == CRC_ReverseInputData_8bits) || \ 61 | ((DATA) == CRC_ReverseInputData_16bits) || \ 62 | ((DATA) == CRC_ReverseInputData_32bits)) 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup CRC_PolynomialSize 69 | * @brief Only applicable for STM32F042 and STM32F072 devices 70 | * @{ 71 | */ 72 | #define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */ 73 | #define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */ 74 | #define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */ 75 | #define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */ 76 | 77 | #define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \ 78 | ((SIZE) == CRC_PolSize_8) || \ 79 | ((SIZE) == CRC_PolSize_16) || \ 80 | ((SIZE) == CRC_PolSize_32)) 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | /* Exported macro ------------------------------------------------------------*/ 87 | /* Exported functions ------------------------------------------------------- */ 88 | /* Configuration of the CRC computation unit **********************************/ 89 | void CRC_DeInit(void); 90 | void CRC_ResetDR(void); 91 | void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for STM32F042 and STM32F072 devices */ 92 | void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData); 93 | void CRC_ReverseOutputDataCmd(FunctionalState NewState); 94 | void CRC_SetInitRegister(uint32_t CRC_InitValue); 95 | void CRC_SetPolynomial(uint32_t CRC_Pol); /*!< Only applicable for STM32F042 and STM32F072 devices */ 96 | 97 | /* CRC computation ************************************************************/ 98 | uint32_t CRC_CalcCRC(uint32_t CRC_Data); 99 | uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */ 100 | uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */ 101 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 102 | uint32_t CRC_GetCRC(void); 103 | 104 | /* Independent register (IDR) access (write/read) *****************************/ 105 | void CRC_SetIDRegister(uint8_t CRC_IDValue); 106 | uint8_t CRC_GetIDRegister(void); 107 | 108 | #ifdef __cplusplus 109 | } 110 | #endif 111 | 112 | #endif /* __STM32F0XX_CRC_H */ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 123 | -------------------------------------------------------------------------------- /f030_r820t2/usart.c: -------------------------------------------------------------------------------- 1 | /* 2 | * usart.c - serial i/o routines for STM32F030F4 3 | * 09-04-16 E. Brombaugh 4 | */ 5 | 6 | #include 7 | #include "usart.h" 8 | 9 | /* uncomment this to enable interrupt-based USART processing */ 10 | #define USART_IRQ 11 | 12 | /* uncomment this for RX */ 13 | #define USART_RX 14 | 15 | #ifdef USART_IRQ 16 | #ifdef USART_RX 17 | /* rx buffer */ 18 | #define RX_BUFLEN 256 19 | uint8_t RX_buffer[RX_BUFLEN]; 20 | uint8_t *RX_wptr, *RX_rptr; 21 | #endif 22 | /* tx buffer */ 23 | #define TX_BUFLEN 400 24 | uint8_t TX_buffer[TX_BUFLEN]; 25 | uint8_t *TX_wptr, *TX_rptr; 26 | #endif 27 | 28 | /* USART1 setup */ 29 | void usart_init(void) 30 | { 31 | GPIO_InitTypeDef GPIO_InitStructure; 32 | USART_InitTypeDef USART_InitStructure; 33 | NVIC_InitTypeDef NVIC_InitStructure; 34 | 35 | #ifdef USART_IRQ 36 | #ifdef USART_RX 37 | /* init RX buffer write/read pointers*/ 38 | RX_wptr = &RX_buffer[0]; 39 | RX_rptr = &RX_buffer[0]; 40 | #endif 41 | /* init TX buffer */ 42 | TX_wptr = &TX_buffer[0]; 43 | TX_rptr = &TX_buffer[0]; 44 | #endif 45 | 46 | /* Setup USART */ 47 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); 48 | 49 | /* Connect PA2 to USART1_Tx */ 50 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_1); 51 | 52 | /* Configure USART Tx as alternate function push-pull */ 53 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 54 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 55 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 56 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 57 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; 58 | GPIO_Init(GPIOA, &GPIO_InitStructure); 59 | 60 | #ifdef USART_RX 61 | /* Connect PA3 to USART1_Rx */ 62 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_1); 63 | 64 | /* Configure USART Rx as alternate function w/ pullup */ 65 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; 66 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 67 | GPIO_Init(GPIOA, &GPIO_InitStructure); 68 | #endif 69 | 70 | /* USART configuration */ 71 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); 72 | 73 | /* USART = 115k-8-N-1 */ 74 | USART_InitStructure.USART_BaudRate = 115200; 75 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 76 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 77 | USART_InitStructure.USART_Parity = USART_Parity_No; 78 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 79 | USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 80 | USART_Init(USART1, &USART_InitStructure); 81 | 82 | #ifdef USART_IRQ 83 | #ifdef USART_RX 84 | /* Enable RX interrupt */ 85 | USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); 86 | #endif 87 | 88 | /* Enable the USART1 Interrupt */ 89 | NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; 90 | NVIC_InitStructure.NVIC_IRQChannelPriority = 2; 91 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 92 | NVIC_Init(&NVIC_InitStructure); 93 | #endif 94 | 95 | /* Enable USART */ 96 | USART_Cmd(USART1, ENABLE); 97 | } 98 | 99 | int usart_getc(void) 100 | { 101 | #ifdef USART_RX 102 | #ifndef USART_IRQ 103 | /* Non-interrupt version */ 104 | if(USART_GetFlagStatus(USART6, USART_FLAG_RXNE) == SET) 105 | return USART_ReceiveData(USART6); 106 | else 107 | return EOF; 108 | #else 109 | /* interrupt version */ 110 | int retval; 111 | 112 | /* check if there's data in the buffer */ 113 | if(RX_rptr != RX_wptr) 114 | { 115 | /* get the data */ 116 | retval = *RX_rptr++; 117 | 118 | /* wrap the pointer */ 119 | if((RX_rptr - &RX_buffer[0])>=RX_BUFLEN) 120 | RX_rptr = &RX_buffer[0]; 121 | } 122 | else 123 | retval = EOF; 124 | 125 | return retval; 126 | #endif 127 | #else 128 | return 0; 129 | #endif 130 | } 131 | 132 | /* 133 | * output for tiny printf 134 | */ 135 | void usart_putc(void* p, char c) 136 | { 137 | #ifndef USART_IRQ 138 | /* Non-interrupt version */ 139 | while (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET) 140 | {} 141 | USART_SendData(USART1, (uint8_t) c); 142 | #else 143 | /* interrupt version */ 144 | /* check if there's room in the buffer */ 145 | if((TX_wptr != TX_rptr-1) && 146 | (TX_wptr - TX_rptr != (TX_BUFLEN-1))) 147 | { 148 | /* Yes - Queue the new char & enable IRQ */ 149 | *TX_wptr++ = c; 150 | USART_ITConfig(USART1, USART_IT_TXE, ENABLE); 151 | 152 | /* Wrap pointer */ 153 | if((TX_wptr - &TX_buffer[0])>=TX_BUFLEN) 154 | TX_wptr = &TX_buffer[0]; 155 | } 156 | #endif 157 | } 158 | 159 | #ifdef USART_IRQ 160 | /* 161 | * USART IRQ handler - used only for Rx for now 162 | */ 163 | void USART1_IRQHandler(void) 164 | { 165 | /* receive */ 166 | if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET) 167 | { 168 | /* get the character */ 169 | uint8_t rxchar = USART_ReceiveData(USART1); 170 | 171 | #ifdef USART_RX 172 | /* check if there's room in the buffer */ 173 | if((RX_wptr != RX_rptr-1) && 174 | (RX_wptr - RX_rptr != (RX_BUFLEN-1))) 175 | { 176 | /* Yes - Queue the new char */ 177 | *RX_wptr++ = rxchar; 178 | 179 | /* Wrap pointer */ 180 | if((RX_wptr - &RX_buffer[0])>=RX_BUFLEN) 181 | RX_wptr = &RX_buffer[0]; 182 | } 183 | #endif 184 | } 185 | 186 | /* transmit */ 187 | if(USART_GetITStatus(USART1, USART_IT_TXE) != RESET) 188 | { 189 | /* check if there's data in the buffer */ 190 | if(TX_rptr != TX_wptr) 191 | { 192 | /* get data out of the buffer */ 193 | uint8_t c = *TX_rptr++; 194 | 195 | /* wrap the pointer */ 196 | if((TX_rptr - &TX_buffer[0])>=TX_BUFLEN) 197 | TX_rptr = &TX_buffer[0]; 198 | 199 | /* send the data */ 200 | USART_SendData(USART1, c); 201 | } 202 | else 203 | { 204 | /* No TX data ready so disable the interrupt */ 205 | USART_ITConfig(USART1, USART_IT_TXE, DISABLE); 206 | } 207 | } 208 | } 209 | #endif 210 | 211 | -------------------------------------------------------------------------------- /f030_r820t2/printf.c: -------------------------------------------------------------------------------- 1 | /* 2 | File: printf.c 3 | 4 | Copyright (C) 2004 Kustaa Nyholm 5 | 6 | This library is free software; you can redistribute it and/or 7 | modify it under the terms of the GNU Lesser General Public 8 | License as published by the Free Software Foundation; either 9 | version 2.1 of the License, or (at your option) any later version. 10 | 11 | This library is distributed in the hope that it will be useful, 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 | Lesser General Public License for more details. 15 | 16 | You should have received a copy of the GNU Lesser General Public 17 | License along with this library; if not, write to the Free Software 18 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 | 20 | */ 21 | 22 | #include "printf.h" 23 | 24 | typedef void (*putcf) (void*,char); 25 | static putcf stdout_putf; 26 | static void* stdout_putp; 27 | 28 | #define PRINTF_LONG_SUPPORT 29 | 30 | #ifdef PRINTF_LONG_SUPPORT 31 | 32 | static void uli2a(unsigned long int num, unsigned int base, int uc,char * bf) 33 | { 34 | int n=0; 35 | unsigned int d=1; 36 | while (num/d >= base) 37 | d*=base; 38 | while (d!=0) { 39 | int dgt = num / d; 40 | num%=d; 41 | d/=base; 42 | if (n || dgt>0|| d==0) { 43 | *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); 44 | ++n; 45 | } 46 | } 47 | *bf=0; 48 | } 49 | 50 | static void li2a (long num, char * bf) 51 | { 52 | if (num<0) { 53 | num=-num; 54 | *bf++ = '-'; 55 | } 56 | uli2a(num,10,0,bf); 57 | } 58 | 59 | #endif 60 | 61 | static void ui2a(unsigned int num, unsigned int base, int uc,char * bf) 62 | { 63 | int n=0; 64 | unsigned int d=1; 65 | while (num/d >= base) 66 | d*=base; 67 | while (d!=0) { 68 | int dgt = num / d; 69 | num%= d; 70 | d/=base; 71 | if (n || dgt>0 || d==0) { 72 | *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); 73 | ++n; 74 | } 75 | } 76 | *bf=0; 77 | } 78 | 79 | static void i2a (int num, char * bf) 80 | { 81 | if (num<0) { 82 | num=-num; 83 | *bf++ = '-'; 84 | } 85 | ui2a(num,10,0,bf); 86 | } 87 | 88 | static int a2d(char ch) 89 | { 90 | if (ch>='0' && ch<='9') 91 | return ch-'0'; 92 | else if (ch>='a' && ch<='f') 93 | return ch-'a'+10; 94 | else if (ch>='A' && ch<='F') 95 | return ch-'A'+10; 96 | else return -1; 97 | } 98 | 99 | static char a2i(char ch, char** src,int base,int* nump) 100 | { 101 | char* p= *src; 102 | int num=0; 103 | int digit; 104 | while ((digit=a2d(ch))>=0) { 105 | if (digit>base) break; 106 | num=num*base+digit; 107 | ch=*p++; 108 | } 109 | *src=p; 110 | *nump=num; 111 | return ch; 112 | } 113 | 114 | static void putchw(void* putp,putcf putf,int n, char z, char* bf) 115 | { 116 | char fc=z? '0' : ' '; 117 | char ch; 118 | char* p=bf; 119 | while (*p++ && n > 0) 120 | n--; 121 | while (n-- > 0) 122 | putf(putp,fc); 123 | while ((ch= *bf++)) 124 | putf(putp,ch); 125 | } 126 | 127 | void tfp_format(void* putp,putcf putf,char *fmt, va_list va) 128 | { 129 | char bf[12]; 130 | 131 | char ch; 132 | 133 | 134 | while ((ch=*(fmt++))) { 135 | if (ch!='%') 136 | putf(putp,ch); 137 | else { 138 | char lz=0; 139 | #ifdef PRINTF_LONG_SUPPORT 140 | char lng=0; 141 | #endif 142 | int w=0; 143 | ch=*(fmt++); 144 | if (ch=='0') { 145 | ch=*(fmt++); 146 | lz=1; 147 | } 148 | if (ch>='0' && ch<='9') { 149 | ch=a2i(ch,&fmt,10,&w); 150 | } 151 | #ifdef PRINTF_LONG_SUPPORT 152 | if (ch=='l') { 153 | ch=*(fmt++); 154 | lng=1; 155 | } 156 | #endif 157 | switch (ch) { 158 | case 0: 159 | goto abort; 160 | case 'u' : { 161 | #ifdef PRINTF_LONG_SUPPORT 162 | if (lng) 163 | uli2a(va_arg(va, unsigned long int),10,0,bf); 164 | else 165 | #endif 166 | ui2a(va_arg(va, unsigned int),10,0,bf); 167 | putchw(putp,putf,w,lz,bf); 168 | break; 169 | } 170 | case 'd' : { 171 | #ifdef PRINTF_LONG_SUPPORT 172 | if (lng) 173 | li2a(va_arg(va, unsigned long int),bf); 174 | else 175 | #endif 176 | i2a(va_arg(va, int),bf); 177 | putchw(putp,putf,w,lz,bf); 178 | break; 179 | } 180 | case 'x': case 'X' : 181 | #ifdef PRINTF_LONG_SUPPORT 182 | if (lng) 183 | uli2a(va_arg(va, unsigned long int),16,(ch=='X'),bf); 184 | else 185 | #endif 186 | ui2a(va_arg(va, unsigned int),16,(ch=='X'),bf); 187 | putchw(putp,putf,w,lz,bf); 188 | break; 189 | case 'c' : 190 | putf(putp,(char)(va_arg(va, int))); 191 | break; 192 | case 's' : 193 | putchw(putp,putf,w,0,va_arg(va, char*)); 194 | break; 195 | case '%' : 196 | putf(putp,ch); 197 | default: 198 | break; 199 | } 200 | } 201 | } 202 | abort:; 203 | } 204 | 205 | 206 | void init_printf(void* putp,void (*putf) (void*,char)) 207 | { 208 | stdout_putf=putf; 209 | stdout_putp=putp; 210 | } 211 | 212 | void tfp_printf(char *fmt, ...) 213 | { 214 | va_list va; 215 | va_start(va,fmt); 216 | tfp_format(stdout_putp,stdout_putf,fmt,va); 217 | va_end(va); 218 | } 219 | 220 | static void putcp(void* p,char c) 221 | { 222 | *(*((char**)p))++ = c; 223 | } 224 | 225 | 226 | 227 | void tfp_sprintf(char* s,char *fmt, ...) 228 | { 229 | va_list va; 230 | va_start(va,fmt); 231 | tfp_format(&s,putcp,fmt,va); 232 | putcp(&s,0); 233 | va_end(va); 234 | } -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_misc.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f0xx_misc.h" 31 | 32 | /** @addtogroup STM32F0xx_StdPeriph_Driver 33 | * @{ 34 | */ 35 | 36 | /** @defgroup MISC 37 | * @brief MISC driver modules 38 | * @{ 39 | */ 40 | 41 | /* Private typedef -----------------------------------------------------------*/ 42 | /* Private define ------------------------------------------------------------*/ 43 | /* Private macro -------------------------------------------------------------*/ 44 | /* Private variables ---------------------------------------------------------*/ 45 | /* Private function prototypes -----------------------------------------------*/ 46 | /* Private functions ---------------------------------------------------------*/ 47 | 48 | /** @defgroup MISC_Private_Functions 49 | * @{ 50 | */ 51 | /** 52 | * 53 | @verbatim 54 | ******************************************************************************* 55 | ##### Interrupts configuration functions ##### 56 | ******************************************************************************* 57 | [..] This section provide functions allowing to configure the NVIC interrupts 58 | (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions. 59 | (#) Enable and Configure the priority of the selected IRQ Channels. 60 | The priority can be 0..3. 61 | 62 | -@- Lower priority values gives higher priority. 63 | -@- Priority Order: 64 | (#@) Lowest priority. 65 | (#@) Lowest hardware priority (IRQn position). 66 | 67 | @endverbatim 68 | */ 69 | 70 | /** 71 | * @brief Initializes the NVIC peripheral according to the specified 72 | * parameters in the NVIC_InitStruct. 73 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 74 | * the configuration information for the specified NVIC peripheral. 75 | * @retval None 76 | */ 77 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 78 | { 79 | uint32_t tmppriority = 0x00; 80 | 81 | /* Check the parameters */ 82 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 83 | assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority)); 84 | 85 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 86 | { 87 | /* Compute the Corresponding IRQ Priority --------------------------------*/ 88 | tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02]; 89 | tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8))); 90 | tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)); 91 | 92 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority; 93 | 94 | /* Enable the Selected IRQ Channels --------------------------------------*/ 95 | NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 96 | } 97 | else 98 | { 99 | /* Disable the Selected IRQ Channels -------------------------------------*/ 100 | NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 101 | } 102 | } 103 | 104 | /** 105 | * @brief Selects the condition for the system to enter low power mode. 106 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 107 | * This parameter can be one of the following values: 108 | * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. 109 | * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. 110 | * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. 111 | * @param NewState: new state of LP condition. 112 | * This parameter can be: ENABLE or DISABLE. 113 | * @retval None 114 | */ 115 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 116 | { 117 | /* Check the parameters */ 118 | assert_param(IS_NVIC_LP(LowPowerMode)); 119 | 120 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 121 | 122 | if (NewState != DISABLE) 123 | { 124 | SCB->SCR |= LowPowerMode; 125 | } 126 | else 127 | { 128 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 129 | } 130 | } 131 | 132 | /** 133 | * @brief Configures the SysTick clock source. 134 | * @param SysTick_CLKSource: specifies the SysTick clock source. 135 | * This parameter can be one of the following values: 136 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 137 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 138 | * @retval None 139 | */ 140 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 141 | { 142 | /* Check the parameters */ 143 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 144 | 145 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 146 | { 147 | SysTick->CTRL |= SysTick_CLKSource_HCLK; 148 | } 149 | else 150 | { 151 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 152 | } 153 | } 154 | 155 | /** 156 | * @} 157 | */ 158 | 159 | /** 160 | * @} 161 | */ 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 168 | -------------------------------------------------------------------------------- /f030_r820t2/cmd.c: -------------------------------------------------------------------------------- 1 | /* 2 | * cmd.c - Command parsing routines for STM32F303 breakout SPI to ice5 FPGA 3 | * 05-11-16 E. Brombaugh 4 | */ 5 | #include 6 | #include 7 | #include 8 | #include "cmd.h" 9 | #include "usart.h" 10 | #include "printf.h" 11 | #include "systick.h" 12 | #include "r820t2.h" 13 | 14 | #define MAX_ARGS 4 15 | 16 | /* locals we use here */ 17 | char cmd_buffer[80]; 18 | char *cmd_wptr; 19 | const char *cmd_commands[] = 20 | { 21 | "help", 22 | "read", 23 | "write", 24 | "dump", 25 | "freq", 26 | "lna_gain", 27 | "mixer_gain", 28 | "vga_gain", 29 | "lna_agc_ena", 30 | "mixer_agc_ena", 31 | "bandwidth", 32 | "init", 33 | "" 34 | }; 35 | 36 | /* reset buffer & display the prompt */ 37 | void cmd_prompt(void) 38 | { 39 | /* reset input buffer */ 40 | cmd_wptr = &cmd_buffer[0]; 41 | 42 | /* prompt user */ 43 | printf("\rCommand>"); 44 | } 45 | 46 | /* process command line after */ 47 | void cmd_proc(void) 48 | { 49 | char *token, *argv[MAX_ARGS]; 50 | int argc, cmd, reg; 51 | unsigned long data, i; 52 | 53 | /* parse out three tokens: cmd arg arg */ 54 | argc = 0; 55 | token = strtok(cmd_buffer, " "); 56 | while(token != NULL && argc < MAX_ARGS) 57 | { 58 | argv[argc++] = token; 59 | token = strtok(NULL, " "); 60 | } 61 | 62 | /* figure out which command it is */ 63 | if(argc > 0) 64 | { 65 | cmd = 0; 66 | while(cmd_commands[cmd] != '\0') 67 | { 68 | if(strcmp(argv[0], cmd_commands[cmd])==0) 69 | break; 70 | cmd++; 71 | } 72 | 73 | /* Can we handle this? */ 74 | if(cmd_commands[cmd] != '\0') 75 | { 76 | printf("\r\n"); 77 | 78 | /* Handle commands */ 79 | switch(cmd) 80 | { 81 | case 0: /* Help */ 82 | printf("help - this message\r\n"); 83 | printf("read - ead reg\r\n"); 84 | printf("write - write reg, data\r\n"); 85 | printf("dump - dump all regs\r\n"); 86 | printf("freq - Set freq in Hz\r\n"); 87 | printf("lna_gain - Set gain of LNA [0 - 15]\r\n"); 88 | printf("mixer_gain - Set gain Mixer [0 - 15]\r\n"); 89 | printf("vga_gain - Set gain VGA [0 - 15]\r\n"); 90 | printf("lna_agc_ena - Enable LNA AGC [0 / 1]\r\n"); 91 | printf("mixer_agc_ena - Enable Mixer AGC [0 / 1]\r\n"); 92 | printf("bandwidth - Set IF bandwidth [0 - 15]\r\n"); 93 | printf("init - run initialization\n\r"); 94 | break; 95 | 96 | case 1: /* read */ 97 | if(argc < 2) 98 | printf("read - missing arg(s)\r\n"); 99 | else 100 | { 101 | reg = (int)strtoul(argv[1], NULL, 0) & 0x3f; 102 | data = R820T2_i2c_read_reg_uncached(reg); 103 | printf("read: 0x%02X = 0x%02lX\r\n", reg, data); 104 | } 105 | break; 106 | 107 | case 2: /* write */ 108 | if(argc < 3) 109 | printf("write - missing arg(s)\r\n"); 110 | else 111 | { 112 | reg = (int)strtoul(argv[1], NULL, 0) & 0x3f; 113 | data = strtoul(argv[2], NULL, 0); 114 | R820T2_i2c_write_reg(reg, data); 115 | printf("write: 0x%02X 0x%02lX\r\n", reg, data); 116 | } 117 | break; 118 | 119 | case 3: /* dump */ 120 | printf("dump:\n\r"); 121 | for(i=0;i<0x20;i++) 122 | { 123 | reg = R820T2_i2c_read_reg_uncached(i); 124 | printf("%3d : 0x%02X\n\r", i, reg&0xff); 125 | systick_delayms(5); 126 | } 127 | break; 128 | 129 | case 4: /* freq */ 130 | if(argc < 2) 131 | printf("freq - missing arg(s)\r\n"); 132 | else 133 | { 134 | data = (int)strtoul(argv[1], NULL, 0); 135 | R820T2_set_freq(data);; 136 | printf("freq: %ld\r\n", data); 137 | } 138 | break; 139 | 140 | case 5: /* lna gain */ 141 | if(argc < 2) 142 | printf("lna_gain - missing arg(s)\r\n"); 143 | else 144 | { 145 | data = (int)strtoul(argv[1], NULL, 0) & 0x0f; 146 | R820T2_set_lna_gain(data);; 147 | printf("lna_gain: %ld\r\n", data); 148 | } 149 | break; 150 | 151 | case 6: /* mixer gain */ 152 | if(argc < 2) 153 | printf("mixer_gain - missing arg(s)\r\n"); 154 | else 155 | { 156 | data = (int)strtoul(argv[1], NULL, 0) & 0x0f; 157 | R820T2_set_mixer_gain(data);; 158 | printf("mixer_gain: %ld\r\n", data); 159 | } 160 | break; 161 | 162 | case 7: /* vga gain */ 163 | if(argc < 2) 164 | printf("vga_gain - missing arg(s)\r\n"); 165 | else 166 | { 167 | data = (int)strtoul(argv[1], NULL, 0) & 0x0f; 168 | R820T2_set_vga_gain(data);; 169 | printf("vga_gain: %ld\r\n", data); 170 | } 171 | break; 172 | 173 | case 8: /* lna agc enable */ 174 | if(argc < 2) 175 | printf("lna_agc_ena - missing arg(s)\r\n"); 176 | else 177 | { 178 | data = (int)strtoul(argv[1], NULL, 0) & 0x01; 179 | R820T2_set_lna_agc(data);; 180 | printf("lna_agc_ena: %ld\r\n", data); 181 | } 182 | break; 183 | 184 | case 9: /* mixer agc enable */ 185 | if(argc < 2) 186 | printf("lna_agc_ena - missing arg(s)\r\n"); 187 | else 188 | { 189 | data = (int)strtoul(argv[1], NULL, 0) & 0x01; 190 | R820T2_set_mixer_agc(data);; 191 | printf("mixer_agc_ena: %ld\r\n", data); 192 | } 193 | break; 194 | 195 | case 10: /* IF Bandwidth */ 196 | if(argc < 2) 197 | printf("bandwidth - missing arg(s)\r\n"); 198 | else 199 | { 200 | data = (int)strtoul(argv[1], NULL, 0) & 0x0f; 201 | R820T2_set_if_bandwidth(data);; 202 | printf("bandwidth: %ld\r\n", data); 203 | } 204 | break; 205 | 206 | case 11: /* init */ 207 | printf("init\n\r"); 208 | R820T2_init(); 209 | break; 210 | 211 | default: /* shouldn't get here */ 212 | break; 213 | } 214 | } 215 | else 216 | printf("Unknown command\r\n"); 217 | } 218 | } 219 | void R820T2_set_if_bandwidth(uint8_t bw); 220 | 221 | void init_cmd(void) 222 | { 223 | /* prompt */ 224 | cmd_prompt(); 225 | } 226 | 227 | void cmd_parse(char ch) 228 | { 229 | /* accumulate chars until cr, handle backspace */ 230 | if(ch == '\b') 231 | { 232 | /* check for buffer underflow */ 233 | if(cmd_wptr - &cmd_buffer[0] > 0) 234 | { 235 | printf("\b \b"); /* Erase & backspace */ 236 | cmd_wptr--; /* remove previous char */ 237 | } 238 | } 239 | else if(ch == '\r') 240 | { 241 | *cmd_wptr = '\0'; /* null terminate, no inc */ 242 | cmd_proc(); 243 | cmd_prompt(); 244 | } 245 | else 246 | { 247 | /* check for buffer full (leave room for null) */ 248 | if(cmd_wptr - &cmd_buffer[0] < 254) 249 | { 250 | *cmd_wptr++ = ch; /* store to buffer */ 251 | usart_putc(NULL, ch); /* echo */ 252 | } 253 | } 254 | } 255 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_pwr.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_PWR_H 31 | #define __STM32F0XX_PWR_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup PWR 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /* Exported constants --------------------------------------------------------*/ 51 | 52 | /** @defgroup PWR_Exported_Constants 53 | * @{ 54 | */ 55 | 56 | /** @defgroup PWR_PVD_detection_level 57 | * @brief This parameters are only applicable for STM32F051 and STM32F072 devices 58 | * @{ 59 | */ 60 | 61 | #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 62 | #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 63 | #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 64 | #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 65 | #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 66 | #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 67 | #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 68 | #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 69 | 70 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ 71 | ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ 72 | ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ 73 | ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) 74 | /** 75 | * @} 76 | */ 77 | 78 | /** @defgroup PWR_WakeUp_Pins 79 | * @{ 80 | */ 81 | 82 | #define PWR_WakeUpPin_1 PWR_CSR_EWUP1 83 | #define PWR_WakeUpPin_2 PWR_CSR_EWUP2 84 | #define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */ 85 | #define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */ 86 | #define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */ 87 | #define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */ 88 | #define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */ 89 | #define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */ 90 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \ 91 | ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \ 92 | ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \ 93 | ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8)) 94 | /** 95 | * @} 96 | */ 97 | 98 | 99 | /** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode 100 | * @{ 101 | */ 102 | 103 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 104 | #define PWR_Regulator_LowPower PWR_CR_LPSDSR 105 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ 106 | ((REGULATOR) == PWR_Regulator_LowPower)) 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @defgroup PWR_SLEEP_mode_entry 112 | * @{ 113 | */ 114 | 115 | #define PWR_SLEEPEntry_WFI ((uint8_t)0x01) 116 | #define PWR_SLEEPEntry_WFE ((uint8_t)0x02) 117 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @defgroup PWR_STOP_mode_entry 124 | * @{ 125 | */ 126 | 127 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 128 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 129 | #define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03) 130 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\ 131 | ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT)) 132 | 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup PWR_Flag 138 | * @{ 139 | */ 140 | 141 | #define PWR_FLAG_WU PWR_CSR_WUF 142 | #define PWR_FLAG_SB PWR_CSR_SBF 143 | #define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */ 144 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF 145 | 146 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 147 | ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY)) 148 | 149 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) 150 | /** 151 | * @} 152 | */ 153 | 154 | /** 155 | * @} 156 | */ 157 | 158 | /* Exported macro ------------------------------------------------------------*/ 159 | /* Exported functions ------------------------------------------------------- */ 160 | 161 | /* Function used to set the PWR configuration to the default reset state ******/ 162 | void PWR_DeInit(void); 163 | 164 | /* Backup Domain Access function **********************************************/ 165 | void PWR_BackupAccessCmd(FunctionalState NewState); 166 | 167 | /* PVD configuration functions ************************************************/ 168 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */ 169 | void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */ 170 | 171 | /* WakeUp pins configuration functions ****************************************/ 172 | void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); 173 | 174 | /* Low Power modes configuration functions ************************************/ 175 | void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry); 176 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 177 | void PWR_EnterSTANDBYMode(void); 178 | 179 | /* Flags management functions *************************************************/ 180 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 181 | void PWR_ClearFlag(uint32_t PWR_FLAG); 182 | 183 | #ifdef __cplusplus 184 | } 185 | #endif 186 | 187 | #endif /* __STM32F0XX_PWR_H */ 188 | 189 | /** 190 | * @} 191 | */ 192 | 193 | /** 194 | * @} 195 | */ 196 | 197 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 198 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_dbgmcu.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the Debug MCU (DBGMCU) peripheral: 9 | * + Device and Revision ID management 10 | * + Peripherals Configuration 11 | * @verbatim 12 | * @endverbatim 13 | * 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | *

© COPYRIGHT 2014 STMicroelectronics

18 | * 19 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 20 | * You may not use this file except in compliance with the License. 21 | * You may obtain a copy of the License at: 22 | * 23 | * http://www.st.com/software_license_agreement_liberty_v2 24 | * 25 | * Unless required by applicable law or agreed to in writing, software 26 | * distributed under the License is distributed on an "AS IS" BASIS, 27 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 | * See the License for the specific language governing permissions and 29 | * limitations under the License. 30 | * 31 | ****************************************************************************** 32 | */ 33 | 34 | /* Includes ------------------------------------------------------------------*/ 35 | #include "stm32f0xx_dbgmcu.h" 36 | 37 | /** @addtogroup STM32F0xx_StdPeriph_Driver 38 | * @{ 39 | */ 40 | 41 | /** @defgroup DBGMCU 42 | * @brief DBGMCU driver modules 43 | * @{ 44 | */ 45 | 46 | /* Private typedef -----------------------------------------------------------*/ 47 | /* Private define ------------------------------------------------------------*/ 48 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) 49 | 50 | /* Private macro -------------------------------------------------------------*/ 51 | /* Private variables ---------------------------------------------------------*/ 52 | /* Private function prototypes -----------------------------------------------*/ 53 | /* Private functions ---------------------------------------------------------*/ 54 | 55 | /** @defgroup DBGMCU_Private_Functions 56 | * @{ 57 | */ 58 | 59 | 60 | /** @defgroup DBGMCU_Group1 Device and Revision ID management functions 61 | * @brief Device and Revision ID management functions 62 | * 63 | @verbatim 64 | ============================================================================== 65 | ##### Device and Revision ID management functions ##### 66 | ============================================================================== 67 | 68 | @endverbatim 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @brief Returns the device revision identifier. 74 | * @param None 75 | * @retval Device revision identifier 76 | */ 77 | uint32_t DBGMCU_GetREVID(void) 78 | { 79 | return(DBGMCU->IDCODE >> 16); 80 | } 81 | 82 | /** 83 | * @brief Returns the device identifier. 84 | * @param None 85 | * @retval Device identifier 86 | */ 87 | uint32_t DBGMCU_GetDEVID(void) 88 | { 89 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); 90 | } 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /** @defgroup DBGMCU_Group2 Peripherals Configuration functions 97 | * @brief Peripherals Configuration 98 | * 99 | @verbatim 100 | ============================================================================== 101 | ##### Peripherals Configuration functions ##### 102 | ============================================================================== 103 | 104 | @endverbatim 105 | * @{ 106 | */ 107 | 108 | /** 109 | * @brief Configures low power mode behavior when the MCU is in Debug mode. 110 | * @param DBGMCU_Periph: specifies the low power mode. 111 | * This parameter can be any combination of the following values: 112 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode 113 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode 114 | * @param NewState: new state of the specified low power mode in Debug mode. 115 | * This parameter can be: ENABLE or DISABLE. 116 | * @retval None 117 | */ 118 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 119 | { 120 | /* Check the parameters */ 121 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); 122 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 123 | 124 | if (NewState != DISABLE) 125 | { 126 | DBGMCU->CR |= DBGMCU_Periph; 127 | } 128 | else 129 | { 130 | DBGMCU->CR &= ~DBGMCU_Periph; 131 | } 132 | } 133 | 134 | 135 | /** 136 | * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. 137 | * @param DBGMCU_Periph: specifies the APB1 peripheral. 138 | * This parameter can be any combination of the following values: 139 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted, 140 | * not applicable for STM32F030 devices 141 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted 142 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted 143 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted, 144 | * applicable only for STM32F072 devices 145 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 146 | * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped 147 | * when Core is halted. 148 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted 149 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted 150 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped 151 | * when Core is halted 152 | * @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted, 153 | * applicable only for STM32F042 and STM32F072 devices 154 | * @param NewState: new state of the specified APB1 peripheral in Debug mode. 155 | * This parameter can be: ENABLE or DISABLE. 156 | * @retval None 157 | */ 158 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) 159 | { 160 | /* Check the parameters */ 161 | assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); 162 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 163 | 164 | if (NewState != DISABLE) 165 | { 166 | DBGMCU->APB1FZ |= DBGMCU_Periph; 167 | } 168 | else 169 | { 170 | DBGMCU->APB1FZ &= ~DBGMCU_Periph; 171 | } 172 | } 173 | 174 | /** 175 | * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. 176 | * @param DBGMCU_Periph: specifies the APB2 peripheral. 177 | * This parameter can be any combination of the following values: 178 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted 179 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted 180 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted 181 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted 182 | * @param NewState: new state of the specified APB2 peripheral in Debug mode. 183 | * This parameter can be: ENABLE or DISABLE. 184 | * @retval None 185 | */ 186 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) 187 | { 188 | /* Check the parameters */ 189 | assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); 190 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 191 | 192 | if (NewState != DISABLE) 193 | { 194 | DBGMCU->APB2FZ |= DBGMCU_Periph; 195 | } 196 | else 197 | { 198 | DBGMCU->APB2FZ &= ~DBGMCU_Periph; 199 | } 200 | } 201 | 202 | /** 203 | * @} 204 | */ 205 | 206 | /** 207 | * @} 208 | */ 209 | 210 | /** 211 | * @} 212 | */ 213 | 214 | /** 215 | * @} 216 | */ 217 | 218 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 219 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_crs.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_crs.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the CRS firmware 8 | * library, applicable only for STM32F042 and STM32F072 devices. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_CRS_H 31 | #define __STM32F0XX_CRS_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /*!< Includes ----------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CRS 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup CRS_Interrupt_Sources 52 | * @{ 53 | */ 54 | #define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ 55 | #define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ 56 | #define CRS_IT_ERR CRS_ISR_ERRF /*!< error */ 57 | #define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ 58 | #define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 59 | #define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 60 | #define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 61 | 62 | #define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ 63 | ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC)) 64 | 65 | #define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ 66 | ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \ 67 | ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \ 68 | ((IT) == CRS_IT_SYNCMISS)) 69 | 70 | #define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00) 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup CRS_Flags 77 | * @{ 78 | */ 79 | #define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ 80 | #define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ 81 | #define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */ 82 | #define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ 83 | #define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 84 | #define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 85 | #define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 86 | 87 | #define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \ 88 | ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \ 89 | ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \ 90 | ((FLAG) == CRS_FLAG_SYNCMISS)) 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /** @defgroup CRS_Synchro_Source 97 | * @{ 98 | */ 99 | #define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ 100 | #define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 101 | #define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */ 102 | 103 | #define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \ 104 | ((SOURCE) == CRS_SYNCSource_LSE) ||\ 105 | ((SOURCE) == CRS_SYNCSource_USB)) 106 | /** 107 | * @} 108 | */ 109 | 110 | /** @defgroup CRS_SynchroDivider 111 | * @{ 112 | */ 113 | #define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */ 114 | #define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 115 | #define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 116 | #define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 117 | #define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 118 | #define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 119 | #define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 120 | #define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 121 | 122 | #define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\ 123 | ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \ 124 | ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \ 125 | ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128)) 126 | /** 127 | * @} 128 | */ 129 | 130 | /** @defgroup CRS_SynchroPolarity 131 | * @{ 132 | */ 133 | #define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */ 134 | #define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 135 | 136 | #define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \ 137 | ((POLARITY) == CRS_SYNCPolarity_Falling)) 138 | /** 139 | * @} 140 | */ 141 | 142 | 143 | 144 | /* Exported macro ------------------------------------------------------------*/ 145 | /* Exported functions ------------------------------------------------------- */ 146 | /* Configuration of the CRS **********************************/ 147 | void CRS_DeInit(void); 148 | void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue); 149 | void CRS_FrequencyErrorCounterCmd(FunctionalState NewState); 150 | void CRS_AutomaticCalibrationCmd(FunctionalState NewState); 151 | void CRS_SoftwareSynchronizationGenerate(void); 152 | void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue); 153 | void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue); 154 | void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler); 155 | void CRS_SynchronizationSourceConfig(uint32_t CRS_Source); 156 | void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity); 157 | uint32_t CRS_GetReloadValue(void); 158 | uint32_t CRS_GetHSI48CalibrationValue(void); 159 | uint32_t CRS_GetFrequencyErrorValue(void); 160 | uint32_t CRS_GetFrequencyErrorDirection(void); 161 | 162 | /* Interrupts and flags management functions **********************************/ 163 | void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState); 164 | FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG); 165 | void CRS_ClearFlag(uint32_t CRS_FLAG); 166 | ITStatus CRS_GetITStatus(uint32_t CRS_IT); 167 | void CRS_ClearITPendingBit(uint32_t CRS_IT); 168 | 169 | #ifdef __cplusplus 170 | } 171 | #endif 172 | 173 | #endif /* __STM32F0XX_CRS_H */ 174 | 175 | /** 176 | * @} 177 | */ 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 184 | -------------------------------------------------------------------------------- /r820t2_breakout/r820t2_breakout-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | # 4 | # +3V3 5 | # 6 | DEF +3V3 #PWR 0 0 Y Y 1 F P 7 | F0 "#PWR" 0 -150 50 H I C CNN 8 | F1 "+3V3" 0 140 50 H V C CNN 9 | F2 "" 0 0 50 H V C CNN 10 | F3 "" 0 0 50 H V C CNN 11 | ALIAS +3.3V 12 | DRAW 13 | P 2 0 1 0 -30 50 0 100 N 14 | P 2 0 1 0 0 0 0 100 N 15 | P 2 0 1 0 0 100 30 50 N 16 | X +3V3 1 0 0 0 U 50 50 1 1 W N 17 | ENDDRAW 18 | ENDDEF 19 | # 20 | # +5V 21 | # 22 | DEF +5V #PWR 0 0 Y Y 1 F P 23 | F0 "#PWR" 0 -150 50 H I C CNN 24 | F1 "+5V" 0 140 50 H V C CNN 25 | F2 "" 0 0 50 H V C CNN 26 | F3 "" 0 0 50 H V C CNN 27 | DRAW 28 | P 2 0 1 0 -30 50 0 100 N 29 | P 2 0 1 0 0 0 0 100 N 30 | P 2 0 1 0 0 100 30 50 N 31 | X +5V 1 0 0 0 U 50 50 1 1 W N 32 | ENDDRAW 33 | ENDDEF 34 | # 35 | # BNC 36 | # 37 | DEF BNC P 0 40 Y N 1 F N 38 | F0 "P" 10 120 50 H V C CNN 39 | F1 "BNC" 110 -60 50 V V C CNN 40 | F2 "" 0 0 50 H V C CNN 41 | F3 "" 0 0 50 H V C CNN 42 | $FPLIST 43 | BNC_* 44 | bnc 45 | bnc-* 46 | $ENDFPLIST 47 | DRAW 48 | C 0 0 20 0 1 8 N 49 | C 0 0 70 0 1 12 N 50 | X In 1 -150 0 130 R 40 40 1 1 P 51 | X Ext 2 0 -200 130 U 40 40 1 1 P 52 | ENDDRAW 53 | ENDDEF 54 | # 55 | # C 56 | # 57 | DEF C C 0 10 N Y 1 F N 58 | F0 "C" 25 100 50 H V L CNN 59 | F1 "C" 25 -100 50 H V L CNN 60 | F2 "" 38 -150 50 H V C CNN 61 | F3 "" 0 0 50 H V C CNN 62 | $FPLIST 63 | C? 64 | C_????_* 65 | C_???? 66 | SMD*_c 67 | Capacitor* 68 | $ENDFPLIST 69 | DRAW 70 | P 2 0 1 20 -80 -30 80 -30 N 71 | P 2 0 1 20 -80 30 80 30 N 72 | X ~ 1 0 150 110 D 40 40 1 1 P 73 | X ~ 2 0 -150 110 U 40 40 1 1 P 74 | ENDDRAW 75 | ENDDEF 76 | # 77 | # CONN_01X01 78 | # 79 | DEF CONN_01X01 P 0 40 Y N 1 F N 80 | F0 "P" 0 100 50 H V C CNN 81 | F1 "CONN_01X01" 100 0 50 V V C CNN 82 | F2 "" 0 0 50 H V C CNN 83 | F3 "" 0 0 50 H V C CNN 84 | $FPLIST 85 | Pin_Header_Straight_1X01 86 | Pin_Header_Angled_1X01 87 | Socket_Strip_Straight_1X01 88 | Socket_Strip_Angled_1X01 89 | $ENDFPLIST 90 | DRAW 91 | S -50 5 10 -5 0 1 0 N 92 | S -50 50 50 -50 0 1 0 N 93 | X P1 1 -200 0 150 R 50 50 1 1 P 94 | ENDDRAW 95 | ENDDEF 96 | # 97 | # CONN_01X04 98 | # 99 | DEF CONN_01X04 P 0 40 Y N 1 F N 100 | F0 "P" 0 250 50 H V C CNN 101 | F1 "CONN_01X04" 100 0 50 V V C CNN 102 | F2 "" 0 0 50 H V C CNN 103 | F3 "" 0 0 50 H V C CNN 104 | $FPLIST 105 | Pin_Header_Straight_1X04 106 | Pin_Header_Angled_1X04 107 | Socket_Strip_Straight_1X04 108 | Socket_Strip_Angled_1X04 109 | $ENDFPLIST 110 | DRAW 111 | S -50 -145 10 -155 0 1 0 N 112 | S -50 -45 10 -55 0 1 0 N 113 | S -50 55 10 45 0 1 0 N 114 | S -50 155 10 145 0 1 0 N 115 | S -50 200 50 -200 0 1 0 N 116 | X P1 1 -200 150 150 R 50 50 1 1 P 117 | X P2 2 -200 50 150 R 50 50 1 1 P 118 | X P3 3 -200 -50 150 R 50 50 1 1 P 119 | X P4 4 -200 -150 150 R 50 50 1 1 P 120 | ENDDRAW 121 | ENDDEF 122 | # 123 | # Crystal_Small 124 | # 125 | DEF Crystal_Small Y 0 40 N N 1 F N 126 | F0 "Y" 0 100 50 H V C CNN 127 | F1 "Crystal_Small" 0 -100 50 H V C CNN 128 | F2 "" 0 0 50 H V C CNN 129 | F3 "" 0 0 50 H V C CNN 130 | $FPLIST 131 | Crystal_ 132 | $ENDFPLIST 133 | DRAW 134 | S -30 -60 30 60 0 1 0 N 135 | P 2 0 1 0 -50 -30 -50 30 N 136 | P 2 0 1 0 50 -30 50 30 N 137 | X 1 1 -100 0 50 R 40 40 1 1 P 138 | X 2 2 100 0 50 L 40 40 1 1 P 139 | ENDDRAW 140 | ENDDEF 141 | # 142 | # D_Schottky_x2_Serial_AKC 143 | # 144 | DEF D_Schottky_x2_Serial_AKC D 0 30 Y N 1 F N 145 | F0 "D" 50 -100 50 H V C CNN 146 | F1 "D_Schottky_x2_Serial_AKC" 0 100 50 H V C CNN 147 | F2 "" 0 0 50 H V C CNN 148 | F3 "" 0 0 50 H V C CNN 149 | DRAW 150 | P 2 0 1 0 0 0 0 -100 N 151 | P 2 0 1 0 250 0 300 0 N 152 | P 3 0 1 10 -50 -50 -50 50 -50 50 N 153 | P 3 0 1 10 -50 0 50 0 50 0 N 154 | P 3 0 1 10 150 50 150 -50 150 -50 N 155 | P 4 0 1 10 -50 -50 -30 -50 -30 -40 -30 -40 N 156 | P 4 0 1 10 150 -50 170 -50 170 -40 170 -40 N 157 | P 4 0 1 10 150 50 130 50 130 40 130 40 N 158 | P 5 0 1 10 -70 40 -70 50 -50 50 -50 50 -50 50 N 159 | P 6 0 1 10 -150 50 -50 0 -150 -50 -150 50 -150 50 -150 50 N 160 | P 6 0 1 10 50 50 150 0 50 -50 50 50 50 50 50 50 N 161 | X A 1 -300 0 150 R 50 50 0 1 P 162 | X K 2 300 0 150 L 50 50 0 1 P 163 | X common 3 0 -200 100 U 50 50 0 1 P 164 | ENDDRAW 165 | ENDDEF 166 | # 167 | # GND 168 | # 169 | DEF GND #PWR 0 0 Y Y 1 F P 170 | F0 "#PWR" 0 -250 50 H I C CNN 171 | F1 "GND" 0 -150 50 H V C CNN 172 | F2 "" 0 0 50 H V C CNN 173 | F3 "" 0 0 50 H V C CNN 174 | DRAW 175 | P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N 176 | X GND 1 0 0 0 D 50 50 1 1 W N 177 | ENDDRAW 178 | ENDDEF 179 | # 180 | # INDUCTOR_SMALL 181 | # 182 | DEF INDUCTOR_SMALL L 0 0 N N 1 F N 183 | F0 "L" 0 100 50 H V C CNN 184 | F1 "INDUCTOR_SMALL" 0 -50 50 H V C CNN 185 | F2 "" 0 0 50 H V C CNN 186 | F3 "" 0 0 50 H V C CNN 187 | DRAW 188 | A -150 0 50 1 1799 0 1 0 N -100 0 -200 0 189 | A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 190 | A 50 0 50 1 1799 0 1 0 N 100 0 0 0 191 | A 150 0 50 1 1799 0 1 0 N 200 0 100 0 192 | X 1 1 -250 0 50 R 30 30 1 1 I 193 | X 2 2 250 0 50 L 30 30 1 1 I 194 | ENDDRAW 195 | ENDDEF 196 | # 197 | # LD1117_tab 198 | # 199 | DEF LD1117_tab U 0 30 Y Y 1 F N 200 | F0 "U" 0 250 50 H V C CNN 201 | F1 "LD1117_tab" 0 200 50 H V C CNN 202 | F2 "SOT-223" 0 100 50 H V C CNN 203 | F3 "" 0 0 50 H V C CNN 204 | $FPLIST 205 | SOT223 206 | $ENDFPLIST 207 | DRAW 208 | S -250 -150 250 150 0 1 10 f 209 | X GND 1 0 -250 100 U 40 40 1 1 W 210 | X VO 2 400 50 150 L 40 40 1 1 w 211 | X VI 3 -400 50 150 R 40 40 1 1 W 212 | X tab 4 400 -50 150 L 50 50 1 1 I 213 | ENDDRAW 214 | ENDDEF 215 | # 216 | # PWR_FLAG 217 | # 218 | DEF PWR_FLAG #FLG 0 0 N N 1 F P 219 | F0 "#FLG" 0 95 50 H I C CNN 220 | F1 "PWR_FLAG" 0 180 50 H V C CNN 221 | F2 "" 0 0 50 H V C CNN 222 | F3 "" 0 0 50 H V C CNN 223 | DRAW 224 | X pwr 1 0 0 0 U 20 20 0 0 w 225 | P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N 226 | ENDDRAW 227 | ENDDEF 228 | # 229 | # R 230 | # 231 | DEF R R 0 0 N Y 1 F N 232 | F0 "R" 80 0 50 V V C CNN 233 | F1 "R" 0 0 50 V V C CNN 234 | F2 "" -70 0 50 V V C CNN 235 | F3 "" 0 0 50 H V C CNN 236 | $FPLIST 237 | R_* 238 | Resistor_* 239 | $ENDFPLIST 240 | DRAW 241 | S -40 -100 40 100 0 1 10 N 242 | X ~ 1 0 150 50 D 50 50 1 1 P 243 | X ~ 2 0 -150 50 U 50 50 1 1 P 244 | ENDDRAW 245 | ENDDEF 246 | # 247 | # R820T2 248 | # 249 | DEF R820T2 U 0 40 Y Y 1 F N 250 | F0 "U" -50 200 60 H V C CNN 251 | F1 "R820T2" 0 0 60 H V C CNN 252 | F2 "" 0 0 60 H V C CNN 253 | F3 "" 0 0 60 H V C CNN 254 | DRAW 255 | S -550 550 550 -550 0 1 0 f 256 | X NC 1 -750 250 200 R 50 50 1 1 N 257 | X VCC 2 -750 150 200 R 50 50 1 1 W 258 | X LT 3 -750 50 200 R 50 50 1 1 O 259 | X DET1 4 -750 -50 200 R 50 50 1 1 P 260 | X DET2 5 -750 -150 200 R 50 50 1 1 P 261 | X SCL 6 -750 -250 200 R 50 50 1 1 I 262 | X SDA 7 -250 -750 200 U 50 50 1 1 B 263 | X XTAL_I 8 -150 -750 200 U 50 50 1 1 I 264 | X XTAL_O 9 -50 -750 200 U 50 50 1 1 O 265 | X CLK_OUT 10 50 -750 200 U 50 50 1 1 O 266 | X TF2P 20 150 750 200 D 50 50 1 1 P 267 | X VCC 11 150 -750 200 U 50 50 1 1 W 268 | X TF1N 21 50 750 200 D 50 50 1 1 P 269 | X IF_N 12 250 -750 200 U 50 50 1 1 O 270 | X TF1P 22 -50 750 200 D 50 50 1 1 P 271 | X IF_P 13 750 -250 200 L 50 50 1 1 O 272 | X VCC 23 -150 750 200 D 50 50 1 1 W 273 | X IF_AGC 14 750 -150 200 L 50 50 1 1 I 274 | X RFIN 24 -250 750 200 D 50 50 1 1 I 275 | X CP 15 750 -50 200 L 50 50 1 1 P 276 | X GND 25 750 -400 200 L 50 50 1 1 W 277 | X GND 16 750 50 200 L 50 50 1 1 W 278 | X VDD_PLL 17 750 150 200 L 50 50 1 1 P 279 | X VCC 18 750 250 200 L 50 50 1 1 W 280 | X TF2N 19 250 750 200 D 50 50 1 1 P 281 | ENDDRAW 282 | ENDDEF 283 | # 284 | # TCXO 285 | # 286 | DEF TCXO U 0 40 Y Y 1 F N 287 | F0 "U" -250 300 60 H V C CNN 288 | F1 "TCXO" 0 0 60 H V C CNN 289 | F2 "" 0 0 60 H V C CNN 290 | F3 "" 0 0 60 H V C CNN 291 | DRAW 292 | S -300 250 300 -250 0 1 0 f 293 | X nc 1 -500 0 200 R 50 50 1 1 I 294 | X gnd 2 0 -450 200 U 50 50 1 1 I 295 | X out 3 500 0 200 L 50 50 1 1 I 296 | X vdd 4 0 450 200 D 50 50 1 1 I 297 | ENDDRAW 298 | ENDDEF 299 | # 300 | # TRANSFO4 301 | # 302 | DEF TRANSFO4 T 0 40 Y N 1 F N 303 | F0 "T" 0 250 50 H V C CNN 304 | F1 "TRANSFO4" 0 -300 50 H V C CNN 305 | F2 "" 0 0 50 H V C CNN 306 | F3 "" 0 0 50 H V C CNN 307 | DRAW 308 | A -100 -150 50 899 1 0 1 0 N -100 -100 -50 -150 309 | A -100 -150 50 -1 -899 0 1 0 N -50 -150 -100 -199 310 | A -100 -50 50 899 1 0 1 0 N -100 0 -50 -50 311 | A -100 -50 50 -1 -899 0 1 0 N -50 -50 -100 -99 312 | A -100 50 50 899 1 0 1 0 N -100 100 -50 50 313 | A -100 50 50 -1 -899 0 1 0 N -50 50 -100 1 314 | A -100 150 50 899 1 0 1 0 N -100 200 -50 150 315 | A -100 150 50 -1 -899 0 1 0 N -50 150 -100 101 316 | A 100 -50 50 899 -1799 0 1 0 N 100 0 51 -50 317 | A 100 -50 50 1799 -899 0 1 0 N 51 -50 100 -99 318 | A 100 50 50 899 -1799 0 1 0 N 100 100 51 50 319 | A 100 50 50 1799 -899 0 1 0 N 51 50 100 1 320 | A 100 150 50 899 -1799 0 1 0 N 100 200 51 150 321 | A 100 150 50 1799 -899 0 1 0 N 51 150 100 101 322 | A 101 -150 50 910 -1799 0 1 0 N 101 -100 52 -150 323 | A 101 -150 50 -912 -1799 0 1 0 N 101 -199 52 -150 324 | P 2 0 1 0 -25 200 -25 -200 N 325 | P 2 0 1 0 25 -200 25 200 N 326 | X PR1 1 -400 200 300 R 50 50 1 1 P 327 | X PM 2 -400 0 300 R 50 50 1 1 P 328 | X PR2 3 -400 -200 300 R 50 50 1 1 P 329 | X S1 4 400 -200 300 L 50 50 1 1 P 330 | X S2 5 400 200 300 L 50 50 1 1 P 331 | ENDDRAW 332 | ENDDEF 333 | # 334 | #End Library 335 | -------------------------------------------------------------------------------- /f030_r820t2/CMSIS/startup_stm32f030.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f030.s 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief STM32F030 Devices vector table for Atollic toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the system clock 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M0 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | *

© COPYRIGHT 2014 STMicroelectronics

21 | * 22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 23 | * You may not use this file except in compliance with the License. 24 | * You may obtain a copy of the License at: 25 | * 26 | * http://www.st.com/software_license_agreement_liberty_v2 27 | * 28 | * Unless required by applicable law or agreed to in writing, software 29 | * distributed under the License is distributed on an "AS IS" BASIS, 30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | * See the License for the specific language governing permissions and 32 | * limitations under the License. 33 | * 34 | ****************************************************************************** 35 | */ 36 | 37 | .syntax unified 38 | .cpu cortex-m0 39 | .fpu softvfp 40 | .thumb 41 | 42 | .global g_pfnVectors 43 | .global Default_Handler 44 | 45 | /* start address for the initialization values of the .data section. 46 | defined in linker script */ 47 | .word _sidata 48 | /* start address for the .data section. defined in linker script */ 49 | .word _sdata 50 | /* end address for the .data section. defined in linker script */ 51 | .word _edata 52 | /* start address for the .bss section. defined in linker script */ 53 | .word _sbss 54 | /* end address for the .bss section. defined in linker script */ 55 | .word _ebss 56 | 57 | .section .text.Reset_Handler 58 | .weak Reset_Handler 59 | .type Reset_Handler, %function 60 | Reset_Handler: 61 | ldr r0, =_estack 62 | mov sp, r0 /* set stack pointer */ 63 | 64 | /*Check if boot space corresponds to test memory*/ 65 | 66 | LDR R0,=0x00000004 67 | LDR R1, [R0] 68 | LSRS R1, R1, #24 69 | LDR R2,=0x1F 70 | CMP R1, R2 71 | BNE ApplicationStart 72 | 73 | /*SYSCFG clock enable*/ 74 | 75 | LDR R0,=0x40021018 76 | LDR R1,=0x00000001 77 | STR R1, [R0] 78 | 79 | /*Set CFGR1 register with flash memory remap at address 0*/ 80 | LDR R0,=0x40010000 81 | LDR R1,=0x00000000 82 | STR R1, [R0] 83 | 84 | ApplicationStart: 85 | /* Copy the data segment initializers from flash to SRAM */ 86 | movs r1, #0 87 | b LoopCopyDataInit 88 | 89 | CopyDataInit: 90 | ldr r3, =_sidata 91 | ldr r3, [r3, r1] 92 | str r3, [r0, r1] 93 | adds r1, r1, #4 94 | 95 | LoopCopyDataInit: 96 | ldr r0, =_sdata 97 | ldr r3, =_edata 98 | adds r2, r0, r1 99 | cmp r2, r3 100 | bcc CopyDataInit 101 | ldr r2, =_sbss 102 | b LoopFillZerobss 103 | /* Zero fill the bss segment. */ 104 | FillZerobss: 105 | movs r3, #0 106 | str r3, [r2] 107 | adds r2, r2, #4 108 | 109 | 110 | LoopFillZerobss: 111 | ldr r3, = _ebss 112 | cmp r2, r3 113 | bcc FillZerobss 114 | 115 | /* Call the clock system intitialization function.*/ 116 | bl SystemInit 117 | /* Call static constructors */ 118 | /*bl __libc_init_array*/ 119 | /* Call the application's entry point.*/ 120 | bl main 121 | 122 | LoopForever: 123 | b LoopForever 124 | 125 | 126 | .size Reset_Handler, .-Reset_Handler 127 | 128 | /** 129 | * @brief This is the code that gets called when the processor receives an 130 | * unexpected interrupt. This simply enters an infinite loop, preserving 131 | * the system state for examination by a debugger. 132 | * 133 | * @param None 134 | * @retval : None 135 | */ 136 | .section .text.Default_Handler,"ax",%progbits 137 | Default_Handler: 138 | Infinite_Loop: 139 | b Infinite_Loop 140 | .size Default_Handler, .-Default_Handler 141 | /****************************************************************************** 142 | * 143 | * The minimal vector table for a Cortex M0. Note that the proper constructs 144 | * must be placed on this to ensure that it ends up at physical address 145 | * 0x0000.0000. 146 | * 147 | ******************************************************************************/ 148 | .section .isr_vector,"a",%progbits 149 | .type g_pfnVectors, %object 150 | .size g_pfnVectors, .-g_pfnVectors 151 | 152 | g_pfnVectors: 153 | .word _estack 154 | .word Reset_Handler 155 | 156 | .word NMI_Handler 157 | .word HardFault_Handler 158 | .word 0 159 | .word 0 160 | .word 0 161 | .word 0 162 | .word 0 163 | .word 0 164 | .word 0 165 | .word SVC_Handler 166 | .word 0 167 | .word 0 168 | .word PendSV_Handler 169 | .word SysTick_Handler 170 | 171 | 172 | .word WWDG_IRQHandler 173 | .word 0 174 | .word RTC_IRQHandler 175 | .word FLASH_IRQHandler 176 | .word RCC_IRQHandler 177 | .word EXTI0_1_IRQHandler 178 | .word EXTI2_3_IRQHandler 179 | .word EXTI4_15_IRQHandler 180 | .word 0 181 | .word DMA1_Channel1_IRQHandler 182 | .word DMA1_Channel2_3_IRQHandler 183 | .word DMA1_Channel4_5_IRQHandler 184 | .word ADC1_IRQHandler 185 | .word TIM1_BRK_UP_TRG_COM_IRQHandler 186 | .word TIM1_CC_IRQHandler 187 | .word 0 188 | .word TIM3_IRQHandler 189 | .word 0 190 | .word 0 191 | .word TIM14_IRQHandler 192 | .word TIM15_IRQHandler 193 | .word TIM16_IRQHandler 194 | .word TIM17_IRQHandler 195 | .word I2C1_IRQHandler 196 | .word I2C2_IRQHandler 197 | .word SPI1_IRQHandler 198 | .word SPI2_IRQHandler 199 | .word USART1_IRQHandler 200 | .word USART2_IRQHandler 201 | .word 0 202 | .word 0 203 | .word 0 204 | 205 | /******************************************************************************* 206 | * 207 | * Provide weak aliases for each Exception handler to the Default_Handler. 208 | * As they are weak aliases, any function with the same name will override 209 | * this definition. 210 | * 211 | *******************************************************************************/ 212 | 213 | .weak NMI_Handler 214 | .thumb_set NMI_Handler,Default_Handler 215 | 216 | .weak HardFault_Handler 217 | .thumb_set HardFault_Handler,Default_Handler 218 | 219 | .weak SVC_Handler 220 | .thumb_set SVC_Handler,Default_Handler 221 | 222 | .weak PendSV_Handler 223 | .thumb_set PendSV_Handler,Default_Handler 224 | 225 | .weak SysTick_Handler 226 | .thumb_set SysTick_Handler,Default_Handler 227 | 228 | .weak WWDG_IRQHandler 229 | .thumb_set WWDG_IRQHandler,Default_Handler 230 | 231 | .weak RTC_IRQHandler 232 | .thumb_set RTC_IRQHandler,Default_Handler 233 | 234 | .weak FLASH_IRQHandler 235 | .thumb_set FLASH_IRQHandler,Default_Handler 236 | 237 | .weak RCC_IRQHandler 238 | .thumb_set RCC_IRQHandler,Default_Handler 239 | 240 | .weak EXTI0_1_IRQHandler 241 | .thumb_set EXTI0_1_IRQHandler,Default_Handler 242 | 243 | .weak EXTI2_3_IRQHandler 244 | .thumb_set EXTI2_3_IRQHandler,Default_Handler 245 | 246 | .weak EXTI4_15_IRQHandler 247 | .thumb_set EXTI4_15_IRQHandler,Default_Handler 248 | 249 | .weak DMA1_Channel1_IRQHandler 250 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 251 | 252 | .weak DMA1_Channel2_3_IRQHandler 253 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler 254 | 255 | .weak DMA1_Channel4_5_IRQHandler 256 | .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler 257 | 258 | .weak ADC1_IRQHandler 259 | .thumb_set ADC1_IRQHandler,Default_Handler 260 | 261 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler 262 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 263 | 264 | .weak TIM1_CC_IRQHandler 265 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 266 | 267 | .weak TIM3_IRQHandler 268 | .thumb_set TIM3_IRQHandler,Default_Handler 269 | 270 | .weak TIM14_IRQHandler 271 | .thumb_set TIM14_IRQHandler,Default_Handler 272 | 273 | .weak TIM15_IRQHandler 274 | .thumb_set TIM15_IRQHandler,Default_Handler 275 | 276 | .weak TIM16_IRQHandler 277 | .thumb_set TIM16_IRQHandler,Default_Handler 278 | 279 | .weak TIM17_IRQHandler 280 | .thumb_set TIM17_IRQHandler,Default_Handler 281 | 282 | .weak I2C1_IRQHandler 283 | .thumb_set I2C1_IRQHandler,Default_Handler 284 | 285 | .weak I2C2_IRQHandler 286 | .thumb_set I2C2_IRQHandler,Default_Handler 287 | 288 | .weak SPI1_IRQHandler 289 | .thumb_set SPI1_IRQHandler,Default_Handler 290 | 291 | .weak SPI2_IRQHandler 292 | .thumb_set SPI2_IRQHandler,Default_Handler 293 | 294 | .weak USART1_IRQHandler 295 | .thumb_set USART1_IRQHandler,Default_Handler 296 | 297 | .weak USART2_IRQHandler 298 | .thumb_set USART2_IRQHandler,Default_Handler 299 | 300 | 301 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 302 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_wwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_wwdg.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the Window watchdog (WWDG) peripheral: 9 | * + Prescaler, Refresh window and Counter configuration 10 | * + WWDG activation 11 | * + Interrupts and flags management 12 | * 13 | * @verbatim 14 | * 15 | ============================================================================== 16 | ##### WWDG features ##### 17 | ============================================================================== 18 | [..] Once enabled the WWDG generates a system reset on expiry of a programmed 19 | time period, unless the program refreshes the counter (downcounter) 20 | before to reach 0x3F value (i.e. a reset is generated when the counter 21 | value rolls over from 0x40 to 0x3F). 22 | [..] An MCU reset is also generated if the counter value is refreshed 23 | before the counter has reached the refresh window value. This 24 | implies that the counter must be refreshed in a limited window. 25 | 26 | [..] Once enabled the WWDG cannot be disabled except by a system reset. 27 | 28 | [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG 29 | reset occurs. 30 | 31 | [..] The WWDG counter input clock is derived from the APB clock divided 32 | by a programmable prescaler. 33 | 34 | [..] WWDG counter clock = PCLK1 / Prescaler. 35 | [..] WWDG timeout = (WWDG counter clock) * (counter value). 36 | 37 | [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms. 38 | 39 | ##### How to use this driver ##### 40 | ============================================================================== 41 | [..] 42 | (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) 43 | function. 44 | 45 | (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function. 46 | 47 | (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function. 48 | 49 | (#) Set the WWDG counter value and start it using WWDG_Enable() function. 50 | When the WWDG is enabled the counter value should be configured to 51 | a value greater than 0x40 to prevent generating an immediate reset. 52 | 53 | (#) Optionally you can enable the Early wakeup interrupt which is 54 | generated when the counter reach 0x40. 55 | Once enabled this interrupt cannot be disabled except by a system reset. 56 | 57 | (#) Then the application program must refresh the WWDG counter at regular 58 | intervals during normal operation to prevent an MCU reset, using 59 | WWDG_SetCounter() function. This operation must occur only when 60 | the counter value is lower than the refresh window value, 61 | programmed using WWDG_SetWindowValue(). 62 | 63 | * @endverbatim 64 | * 65 | ****************************************************************************** 66 | * @attention 67 | * 68 | *

© COPYRIGHT 2014 STMicroelectronics

69 | * 70 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 71 | * You may not use this file except in compliance with the License. 72 | * You may obtain a copy of the License at: 73 | * 74 | * http://www.st.com/software_license_agreement_liberty_v2 75 | * 76 | * Unless required by applicable law or agreed to in writing, software 77 | * distributed under the License is distributed on an "AS IS" BASIS, 78 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 79 | * See the License for the specific language governing permissions and 80 | * limitations under the License. 81 | * 82 | ****************************************************************************** 83 | */ 84 | 85 | /* Includes ------------------------------------------------------------------*/ 86 | #include "stm32f0xx_wwdg.h" 87 | #include "stm32f0xx_rcc.h" 88 | 89 | /** @addtogroup STM32F0xx_StdPeriph_Driver 90 | * @{ 91 | */ 92 | 93 | /** @defgroup WWDG 94 | * @brief WWDG driver modules 95 | * @{ 96 | */ 97 | 98 | /* Private typedef -----------------------------------------------------------*/ 99 | /* Private define ------------------------------------------------------------*/ 100 | /* --------------------- WWDG registers bit mask ---------------------------- */ 101 | /* CFR register bit mask */ 102 | #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) 103 | #define CFR_W_MASK ((uint32_t)0xFFFFFF80) 104 | #define BIT_MASK ((uint8_t)0x7F) 105 | 106 | /* Private macro -------------------------------------------------------------*/ 107 | /* Private variables ---------------------------------------------------------*/ 108 | /* Private function prototypes -----------------------------------------------*/ 109 | /* Private functions ---------------------------------------------------------*/ 110 | 111 | /** @defgroup WWDG_Private_Functions 112 | * @{ 113 | */ 114 | 115 | /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions 116 | * @brief Prescaler, Refresh window and Counter configuration functions 117 | * 118 | @verbatim 119 | ============================================================================== 120 | ##### Prescaler, Refresh window and Counter configuration functions ##### 121 | ============================================================================== 122 | 123 | @endverbatim 124 | * @{ 125 | */ 126 | 127 | /** 128 | * @brief Deinitializes the WWDG peripheral registers to their default reset values. 129 | * @param None 130 | * @retval None 131 | */ 132 | void WWDG_DeInit(void) 133 | { 134 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 135 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 136 | } 137 | 138 | /** 139 | * @brief Sets the WWDG Prescaler. 140 | * @param WWDG_Prescaler: specifies the WWDG Prescaler. 141 | * This parameter can be one of the following values: 142 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 143 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 144 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 145 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 146 | * @retval None 147 | */ 148 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 149 | { 150 | uint32_t tmpreg = 0; 151 | /* Check the parameters */ 152 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); 153 | /* Clear WDGTB[1:0] bits */ 154 | tmpreg = WWDG->CFR & CFR_WDGTB_MASK; 155 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ 156 | tmpreg |= WWDG_Prescaler; 157 | /* Store the new value */ 158 | WWDG->CFR = tmpreg; 159 | } 160 | 161 | /** 162 | * @brief Sets the WWDG window value. 163 | * @param WindowValue: specifies the window value to be compared to the downcounter. 164 | * This parameter value must be lower than 0x80. 165 | * @retval None 166 | */ 167 | void WWDG_SetWindowValue(uint8_t WindowValue) 168 | { 169 | __IO uint32_t tmpreg = 0; 170 | 171 | /* Check the parameters */ 172 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); 173 | /* Clear W[6:0] bits */ 174 | 175 | tmpreg = WWDG->CFR & CFR_W_MASK; 176 | 177 | /* Set W[6:0] bits according to WindowValue value */ 178 | tmpreg |= WindowValue & (uint32_t) BIT_MASK; 179 | 180 | /* Store the new value */ 181 | WWDG->CFR = tmpreg; 182 | } 183 | 184 | /** 185 | * @brief Enables the WWDG Early Wakeup interrupt(EWI). 186 | * @note Once enabled this interrupt cannot be disabled except by a system reset. 187 | * @param None 188 | * @retval None 189 | */ 190 | void WWDG_EnableIT(void) 191 | { 192 | WWDG->CFR |= WWDG_CFR_EWI; 193 | } 194 | 195 | /** 196 | * @brief Sets the WWDG counter value. 197 | * @param Counter: specifies the watchdog counter value. 198 | * This parameter must be a number between 0x40 and 0x7F (to prevent 199 | * generating an immediate reset). 200 | * @retval None 201 | */ 202 | void WWDG_SetCounter(uint8_t Counter) 203 | { 204 | /* Check the parameters */ 205 | assert_param(IS_WWDG_COUNTER(Counter)); 206 | /* Write to T[6:0] bits to configure the counter value, no need to do 207 | a read-modify-write; writing a 0 to WDGA bit does nothing */ 208 | WWDG->CR = Counter & BIT_MASK; 209 | } 210 | 211 | /** 212 | * @} 213 | */ 214 | 215 | /** @defgroup WWDG_Group2 WWDG activation functions 216 | * @brief WWDG activation functions 217 | * 218 | @verbatim 219 | ============================================================================== 220 | ##### WWDG activation function ##### 221 | ============================================================================== 222 | 223 | @endverbatim 224 | * @{ 225 | */ 226 | 227 | /** 228 | * @brief Enables WWDG and load the counter value. 229 | * @param Counter: specifies the watchdog counter value. 230 | * This parameter must be a number between 0x40 and 0x7F (to prevent 231 | * generating an immediate reset). 232 | * @retval None 233 | */ 234 | void WWDG_Enable(uint8_t Counter) 235 | { 236 | /* Check the parameters */ 237 | assert_param(IS_WWDG_COUNTER(Counter)); 238 | WWDG->CR = WWDG_CR_WDGA | Counter; 239 | } 240 | 241 | /** 242 | * @} 243 | */ 244 | 245 | /** @defgroup WWDG_Group3 Interrupts and flags management functions 246 | * @brief Interrupts and flags management functions 247 | * 248 | @verbatim 249 | ============================================================================== 250 | ##### Interrupts and flags management functions ##### 251 | ============================================================================== 252 | 253 | @endverbatim 254 | * @{ 255 | */ 256 | 257 | /** 258 | * @brief Checks whether the Early Wakeup interrupt flag is set or not. 259 | * @param None 260 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). 261 | */ 262 | FlagStatus WWDG_GetFlagStatus(void) 263 | { 264 | FlagStatus bitstatus = RESET; 265 | 266 | if ((WWDG->SR) != (uint32_t)RESET) 267 | { 268 | bitstatus = SET; 269 | } 270 | else 271 | { 272 | bitstatus = RESET; 273 | } 274 | return bitstatus; 275 | } 276 | 277 | /** 278 | * @brief Clears Early Wakeup interrupt flag. 279 | * @param None 280 | * @retval None 281 | */ 282 | void WWDG_ClearFlag(void) 283 | { 284 | WWDG->SR = (uint32_t)RESET; 285 | } 286 | 287 | /** 288 | * @} 289 | */ 290 | 291 | /** 292 | * @} 293 | */ 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 304 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_exti.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the EXTI 8 | * firmware library 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_EXTI_H 31 | #define __STM32F0XX_EXTI_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup EXTI 45 | * @{ 46 | */ 47 | /* Exported types ------------------------------------------------------------*/ 48 | 49 | /** 50 | * @brief EXTI mode enumeration 51 | */ 52 | 53 | typedef enum 54 | { 55 | EXTI_Mode_Interrupt = 0x00, 56 | EXTI_Mode_Event = 0x04 57 | }EXTIMode_TypeDef; 58 | 59 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) 60 | 61 | /** 62 | * @brief EXTI Trigger enumeration 63 | */ 64 | 65 | typedef enum 66 | { 67 | EXTI_Trigger_Rising = 0x08, 68 | EXTI_Trigger_Falling = 0x0C, 69 | EXTI_Trigger_Rising_Falling = 0x10 70 | }EXTITrigger_TypeDef; 71 | 72 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ 73 | ((TRIGGER) == EXTI_Trigger_Falling) || \ 74 | ((TRIGGER) == EXTI_Trigger_Rising_Falling)) 75 | /** 76 | * @brief EXTI Init Structure definition 77 | */ 78 | 79 | typedef struct 80 | { 81 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. 82 | This parameter can be any combination of @ref EXTI_Lines */ 83 | 84 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. 85 | This parameter can be a value of @ref EXTIMode_TypeDef */ 86 | 87 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. 88 | This parameter can be a value of @ref EXTIMode_TypeDef */ 89 | 90 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. 91 | This parameter can be set either to ENABLE or DISABLE */ 92 | }EXTI_InitTypeDef; 93 | 94 | /* Exported constants --------------------------------------------------------*/ 95 | 96 | /** @defgroup EXTI_Exported_Constants 97 | * @{ 98 | */ 99 | /** @defgroup EXTI_Lines 100 | * @{ 101 | */ 102 | 103 | #define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ 104 | #define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ 105 | #define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ 106 | #define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ 107 | #define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ 108 | #define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ 109 | #define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ 110 | #define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ 111 | #define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ 112 | #define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ 113 | #define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ 114 | #define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ 115 | #define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ 116 | #define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ 117 | #define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ 118 | #define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ 119 | #define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 120 | Connected to the PVD Output, 121 | not applicable for STM32F030 devices */ 122 | #define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17 123 | Connected to the RTC Alarm 124 | event */ 125 | #define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18 126 | Connected to the USB 127 | event, only applicable for 128 | STM32F072 devices */ 129 | #define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19 130 | Connected to the RTC Tamper 131 | and Time Stamp events */ 132 | #define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20 133 | Connected to the RTC wakeup 134 | event, only applicable for 135 | STM32F072 devices */ 136 | #define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21 137 | Connected to the Comparator 1 138 | event, only applicable for STM32F051 139 | ans STM32F072 devices */ 140 | #define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22 141 | Connected to the Comparator 2 142 | event, only applicable for STM32F051 143 | and STM32F072 devices */ 144 | #define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23 145 | Connected to the I2C1 wakeup 146 | event, not applicable for STM32F030 devices */ 147 | #define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25 148 | Connected to the USART1 wakeup 149 | event, not applicable for STM32F030 devices */ 150 | #define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26 151 | Connected to the USART2 wakeup 152 | event, applicable only for 153 | STM32F072 devices */ 154 | #define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27 155 | Connected to the CEC wakeup 156 | event, applicable only for STM32F051 157 | and STM32F072 devices */ 158 | #define EXTI_Line31 ((uint32_t)0x80000000) /*!< Internal interrupt line 31 159 | Connected to the VDD USB monitor 160 | event, applicable only for 161 | STM32F072 devices */ 162 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00)) 163 | 164 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ 165 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ 166 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ 167 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ 168 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ 169 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ 170 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ 171 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ 172 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ 173 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ 174 | ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ 175 | ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \ 176 | ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \ 177 | ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31)) 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /** 184 | * @} 185 | */ 186 | 187 | /* Exported macro ------------------------------------------------------------*/ 188 | /* Exported functions ------------------------------------------------------- */ 189 | /* Function used to set the EXTI configuration to the default reset state *****/ 190 | void EXTI_DeInit(void); 191 | 192 | /* Initialization and Configuration functions *********************************/ 193 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 194 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 195 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 196 | 197 | /* Interrupts and flags management functions **********************************/ 198 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 199 | void EXTI_ClearFlag(uint32_t EXTI_Line); 200 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 201 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 202 | 203 | #ifdef __cplusplus 204 | } 205 | #endif 206 | 207 | #endif /* __STM32F0XX_EXTI_H */ 208 | /** 209 | * @} 210 | */ 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 217 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_comp.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_comp.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the COMP firmware 8 | * library, applicable only for STM32F051 and STM32F072 devices. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_COMP_H 31 | #define __STM32F0XX_COMP_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup COMP 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /** 51 | * @brief COMP Init structure definition 52 | */ 53 | 54 | typedef struct 55 | { 56 | 57 | uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator. 58 | This parameter can be a value of @ref COMP_InvertingInput */ 59 | 60 | uint32_t COMP_Output; /*!< Selects the output redirection of the comparator. 61 | This parameter can be a value of @ref COMP_Output */ 62 | 63 | uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator. 64 | This parameter can be a value of @ref COMP_OutputPolarity */ 65 | 66 | uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator. 67 | This parameter can be a value of @ref COMP_Hysteresis */ 68 | 69 | uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator 70 | and allows to adjust the speed/consumption. 71 | This parameter can be a value of @ref COMP_Mode */ 72 | 73 | }COMP_InitTypeDef; 74 | 75 | /* Exported constants --------------------------------------------------------*/ 76 | 77 | /** @defgroup COMP_Exported_Constants 78 | * @{ 79 | */ 80 | 81 | /** @defgroup COMP_Selection 82 | * @{ 83 | */ 84 | 85 | #define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */ 86 | #define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */ 87 | 88 | #define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ 89 | ((PERIPH) == COMP_Selection_COMP2)) 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup COMP_InvertingInput 96 | * @{ 97 | */ 98 | 99 | #define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ 100 | #define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ 101 | #define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ 102 | #define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */ 103 | #define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT (PA4) connected to comparator inverting input */ 104 | #define COMP_InvertingInput_DAC2 ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input, applicable only for STM32F072 devices */ 105 | #define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */ 106 | 107 | #define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ 108 | ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \ 109 | ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \ 110 | ((INPUT) == COMP_InvertingInput_VREFINT) || \ 111 | ((INPUT) == COMP_InvertingInput_DAC1) || \ 112 | ((INPUT) == COMP_InvertingInput_DAC2) || \ 113 | ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ 114 | ((INPUT) == COMP_InvertingInput_IO)) 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @defgroup COMP_Output 120 | * @{ 121 | */ 122 | 123 | #define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */ 124 | #define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */ 125 | #define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */ 126 | #define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */ 127 | #define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */ 128 | #define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */ 129 | #define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */ 130 | #define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */ 131 | 132 | 133 | #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \ 134 | ((OUTPUT) == COMP_Output_TIM1BKIN) || \ 135 | ((OUTPUT) == COMP_Output_TIM1IC1) || \ 136 | ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \ 137 | ((OUTPUT) == COMP_Output_TIM2IC4) || \ 138 | ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \ 139 | ((OUTPUT) == COMP_Output_TIM3IC1) || \ 140 | ((OUTPUT) == COMP_Output_TIM3OCREFCLR)) 141 | /** 142 | * @} 143 | */ 144 | 145 | /** @defgroup COMP_OutputPolarity 146 | * @{ 147 | */ 148 | #define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ 149 | #define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */ 150 | 151 | #define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \ 152 | ((POL) == COMP_OutputPol_Inverted)) 153 | 154 | /** 155 | * @} 156 | */ 157 | 158 | /** @defgroup COMP_Hysteresis 159 | * @{ 160 | */ 161 | /* Please refer to the electrical characteristics in the device datasheet for 162 | the hysteresis level */ 163 | #define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */ 164 | #define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */ 165 | #define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */ 166 | #define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */ 167 | 168 | #define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \ 169 | ((HYSTERESIS) == COMP_Hysteresis_Low) || \ 170 | ((HYSTERESIS) == COMP_Hysteresis_Medium) || \ 171 | ((HYSTERESIS) == COMP_Hysteresis_High)) 172 | /** 173 | * @} 174 | */ 175 | 176 | /** @defgroup COMP_Mode 177 | * @{ 178 | */ 179 | /* Please refer to the electrical characteristics in the device datasheet for 180 | the power consumption values */ 181 | #define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */ 182 | #define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */ 183 | #define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */ 184 | #define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */ 185 | 186 | #define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \ 187 | ((MODE) == COMP_Mode_LowPower) || \ 188 | ((MODE) == COMP_Mode_MediumSpeed) || \ 189 | ((MODE) == COMP_Mode_HighSpeed)) 190 | /** 191 | * @} 192 | */ 193 | 194 | /** @defgroup COMP_OutputLevel 195 | * @{ 196 | */ 197 | /* When output polarity is not inverted, comparator output is high when 198 | the non-inverting input is at a higher voltage than the inverting input */ 199 | #define COMP_OutputLevel_High COMP_CSR_COMP1OUT 200 | /* When output polarity is not inverted, comparator output is low when 201 | the non-inverting input is at a lower voltage than the inverting input*/ 202 | #define COMP_OutputLevel_Low ((uint32_t)0x00000000) 203 | 204 | /** 205 | * @} 206 | */ 207 | 208 | /** 209 | * @} 210 | */ 211 | 212 | /* Exported macro ------------------------------------------------------------*/ 213 | /* Exported functions ------------------------------------------------------- */ 214 | 215 | /* Function used to set the COMP configuration to the default reset state ****/ 216 | void COMP_DeInit(void); 217 | 218 | /* Initialization and Configuration functions *********************************/ 219 | void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct); 220 | void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct); 221 | void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState); 222 | void COMP_SwitchCmd(FunctionalState NewState); 223 | uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection); 224 | 225 | /* Window mode control function ***********************************************/ 226 | void COMP_WindowCmd(FunctionalState NewState); 227 | 228 | /* COMP configuration locking function ****************************************/ 229 | void COMP_LockConfig(uint32_t COMP_Selection); 230 | 231 | #ifdef __cplusplus 232 | } 233 | #endif 234 | 235 | #endif /*__STM32F0XX_COMP_H */ 236 | 237 | /** 238 | * @} 239 | */ 240 | 241 | /** 242 | * @} 243 | */ 244 | 245 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 246 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_exti.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_exti.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the EXTI peripheral: 9 | * + Initialization and Configuration 10 | * + Interrupts and flags management 11 | * 12 | * @verbatim 13 | ============================================================================== 14 | ##### EXTI features ##### 15 | ============================================================================== 16 | [..] External interrupt/event lines are mapped as following: 17 | (#) All available GPIO pins are connected to the 16 external 18 | interrupt/event lines from EXTI0 to EXTI15. 19 | (#) EXTI line 16 is connected to the PVD output, not applicable for STM32F030 devices. 20 | (#) EXTI line 17 is connected to the RTC Alarm event. 21 | (#) EXTI line 18 is connected to the RTC Alarm event, applicable only for STM32F072 devices. 22 | (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events. 23 | (#) EXTI line 20 is connected to the RTC wakeup event, applicable only for STM32F072 devices. 24 | (#) EXTI line 21 is connected to the Comparator 1 wakeup event, applicable only for STM32F051 and STM32F072 devices. 25 | (#) EXTI line 22 is connected to the Comparator 2 wakeup event, applicable only for STM32F051 and STM32F072 devices. 26 | (#) EXTI line 23 is connected to the I2C1 wakeup event, not applicable for STM32F030 devices. 27 | (#) EXTI line 25 is connected to the USART1 wakeup event, not applicable for STM32F030 devices. 28 | (#) EXTI line 26 is connected to the USART2 wakeup event, applicable only for STM32F072 devices. 29 | (#) EXTI line 27 is connected to the CEC wakeup event, applicable only for STM32F051 and STM32F072 devices. 30 | (#) EXTI line 31 is connected to the VDD USB monitor event, applicable only for STM32F072 devices. 31 | 32 | ##### How to use this driver ##### 33 | ============================================================================== 34 | [..] In order to use an I/O pin as an external interrupt source, follow 35 | steps below: 36 | (#) Configure the I/O in input mode using GPIO_Init() 37 | (#) Select the input source pin for the EXTI line using 38 | SYSCFG_EXTILineConfig(). 39 | (#) Select the mode(interrupt, event) and configure the trigger selection 40 | (Rising, falling or both) using EXTI_Init(). For the internal interrupt, 41 | the trigger selection is not needed( the active edge is always the rising one). 42 | (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init(). 43 | (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt(). 44 | [..] 45 | (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx 46 | registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); 47 | @endverbatim 48 | * 49 | ****************************************************************************** 50 | * @attention 51 | * 52 | *

© COPYRIGHT 2014 STMicroelectronics

53 | * 54 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 55 | * You may not use this file except in compliance with the License. 56 | * You may obtain a copy of the License at: 57 | * 58 | * http://www.st.com/software_license_agreement_liberty_v2 59 | * 60 | * Unless required by applicable law or agreed to in writing, software 61 | * distributed under the License is distributed on an "AS IS" BASIS, 62 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 63 | * See the License for the specific language governing permissions and 64 | * limitations under the License. 65 | * 66 | ****************************************************************************** 67 | */ 68 | 69 | /* Includes ------------------------------------------------------------------*/ 70 | #include "stm32f0xx_exti.h" 71 | 72 | /** @addtogroup STM32F0xx_StdPeriph_Driver 73 | * @{ 74 | */ 75 | 76 | /** @defgroup EXTI 77 | * @brief EXTI driver modules 78 | * @{ 79 | */ 80 | 81 | /* Private typedef -----------------------------------------------------------*/ 82 | /* Private define ------------------------------------------------------------*/ 83 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ 84 | 85 | /* Private macro -------------------------------------------------------------*/ 86 | /* Private variables ---------------------------------------------------------*/ 87 | /* Private function prototypes -----------------------------------------------*/ 88 | /* Private functions ---------------------------------------------------------*/ 89 | 90 | /** @defgroup EXTI_Private_Functions 91 | * @{ 92 | */ 93 | 94 | /** @defgroup EXTI_Group1 Initialization and Configuration functions 95 | * @brief Initialization and Configuration functions 96 | * 97 | @verbatim 98 | ============================================================================== 99 | ##### Initialization and Configuration functions ##### 100 | ============================================================================== 101 | 102 | @endverbatim 103 | * @{ 104 | */ 105 | 106 | /** 107 | * @brief Deinitializes the EXTI peripheral registers to their default reset 108 | * values. 109 | * @param None 110 | * @retval None 111 | */ 112 | void EXTI_DeInit(void) 113 | { 114 | EXTI->IMR = 0x0F940000; 115 | EXTI->EMR = 0x00000000; 116 | EXTI->RTSR = 0x00000000; 117 | EXTI->FTSR = 0x00000000; 118 | EXTI->PR = 0x006BFFFF; 119 | } 120 | 121 | /** 122 | * @brief Initializes the EXTI peripheral according to the specified 123 | * parameters in the EXTI_InitStruct. 124 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that 125 | * contains the configuration information for the EXTI peripheral. 126 | * @retval None 127 | */ 128 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) 129 | { 130 | uint32_t tmp = 0; 131 | 132 | /* Check the parameters */ 133 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); 134 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); 135 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); 136 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); 137 | 138 | tmp = (uint32_t)EXTI_BASE; 139 | 140 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) 141 | { 142 | /* Clear EXTI line configuration */ 143 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; 144 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; 145 | 146 | tmp += EXTI_InitStruct->EXTI_Mode; 147 | 148 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 149 | 150 | /* Clear Rising Falling edge configuration */ 151 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; 152 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; 153 | 154 | /* Select the trigger for the selected interrupts */ 155 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 156 | { 157 | /* Rising Falling edge */ 158 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; 159 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; 160 | } 161 | else 162 | { 163 | tmp = (uint32_t)EXTI_BASE; 164 | tmp += EXTI_InitStruct->EXTI_Trigger; 165 | 166 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 167 | } 168 | } 169 | else 170 | { 171 | tmp += EXTI_InitStruct->EXTI_Mode; 172 | 173 | /* Disable the selected external lines */ 174 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; 175 | } 176 | } 177 | 178 | /** 179 | * @brief Fills each EXTI_InitStruct member with its reset value. 180 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will 181 | * be initialized. 182 | * @retval None 183 | */ 184 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) 185 | { 186 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 187 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 188 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 189 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 190 | } 191 | 192 | /** 193 | * @brief Generates a Software interrupt on selected EXTI line. 194 | * @param EXTI_Line: specifies the EXTI line on which the software interrupt 195 | * will be generated. 196 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 197 | * @retval None 198 | */ 199 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 200 | { 201 | /* Check the parameters */ 202 | assert_param(IS_EXTI_LINE(EXTI_Line)); 203 | 204 | EXTI->SWIER |= EXTI_Line; 205 | } 206 | 207 | /** 208 | * @} 209 | */ 210 | 211 | /** @defgroup EXTI_Group2 Interrupts and flags management functions 212 | * @brief Interrupts and flags management functions 213 | * 214 | @verbatim 215 | ============================================================================== 216 | ##### Interrupts and flags management functions ##### 217 | ============================================================================== 218 | 219 | @endverbatim 220 | * @{ 221 | */ 222 | 223 | /** 224 | * @brief Checks whether the specified EXTI line flag is set or not. 225 | * @param EXTI_Line: specifies the EXTI line flag to check. 226 | * This parameter can be EXTI_Linex where x can be (0..27). 227 | * @retval The new state of EXTI_Line (SET or RESET). 228 | */ 229 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 230 | { 231 | FlagStatus bitstatus = RESET; 232 | /* Check the parameters */ 233 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 234 | 235 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 236 | { 237 | bitstatus = SET; 238 | } 239 | else 240 | { 241 | bitstatus = RESET; 242 | } 243 | return bitstatus; 244 | } 245 | 246 | /** 247 | * @brief Clears the EXTI's line pending flags. 248 | * @param EXTI_Line: specifies the EXTI lines flags to clear. 249 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 250 | * @retval None 251 | */ 252 | void EXTI_ClearFlag(uint32_t EXTI_Line) 253 | { 254 | /* Check the parameters */ 255 | assert_param(IS_EXTI_LINE(EXTI_Line)); 256 | 257 | EXTI->PR = EXTI_Line; 258 | } 259 | 260 | /** 261 | * @brief Checks whether the specified EXTI line is asserted or not. 262 | * @param EXTI_Line: specifies the EXTI line to check. 263 | * This parameter can be EXTI_Linex where x can be (0..27). 264 | * @retval The new state of EXTI_Line (SET or RESET). 265 | */ 266 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 267 | { 268 | ITStatus bitstatus = RESET; 269 | 270 | /* Check the parameters */ 271 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 272 | 273 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 274 | { 275 | bitstatus = SET; 276 | } 277 | else 278 | { 279 | bitstatus = RESET; 280 | } 281 | return bitstatus; 282 | } 283 | 284 | /** 285 | * @brief Clears the EXTI's line pending bits. 286 | * @param EXTI_Line: specifies the EXTI lines to clear. 287 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 288 | * @retval None 289 | */ 290 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 291 | { 292 | /* Check the parameters */ 293 | assert_param(IS_EXTI_LINE(EXTI_Line)); 294 | 295 | EXTI->PR = EXTI_Line; 296 | } 297 | 298 | /** 299 | * @} 300 | */ 301 | 302 | /** 303 | * @} 304 | */ 305 | 306 | /** 307 | * @} 308 | */ 309 | 310 | /** 311 | * @} 312 | */ 313 | 314 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 315 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_iwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_iwdg.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the Independent watchdog (IWDG) peripheral: 9 | * + Prescaler and Counter configuration 10 | * + IWDG activation 11 | * + Flag management 12 | * 13 | * @verbatim 14 | * 15 | ============================================================================== 16 | ##### IWDG features ##### 17 | ============================================================================== 18 | [..] The IWDG can be started by either software or hardware (configurable 19 | through option byte). 20 | 21 | [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and 22 | thus stays active even if the main clock fails. 23 | Once the IWDG is started, the LSI is forced ON and cannot be disabled 24 | (LSI cannot be disabled too), and the counter starts counting down from 25 | the reset value of 0xFFF. When it reaches the end of count value (0x000) 26 | a system reset is generated. 27 | The IWDG counter should be reloaded at regular intervals to prevent 28 | an MCU reset. 29 | 30 | [..] The IWDG is implemented in the VDD voltage domain that is still functional 31 | in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). 32 | 33 | [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG 34 | reset occurs. 35 | 36 | [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s 37 | The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx 38 | devices provide the capability to measure the LSI frequency (LSI clock 39 | should be seleted as RTC clock which is internally connected to TIM10 CH1 40 | input capture). The measured value can be used to have an IWDG timeout with 41 | an acceptable accuracy. 42 | For more information, please refer to the STM32F0xx Reference manual. 43 | 44 | ##### How to use this driver ##### 45 | ============================================================================== 46 | [..] This driver allows to use IWDG peripheral with either window option enabled 47 | or disabled. To do so follow one of the two procedures below. 48 | (#) Window option is enabled: 49 | (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used 50 | in software mode (no need to enable the LSI, it will be enabled 51 | by hardware). 52 | (++) Enable write access to IWDG_PR and IWDG_RLR registers using 53 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. 54 | (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. 55 | (++) Configure the IWDG counter value using IWDG_SetReload() function. 56 | This value will be loaded in the IWDG counter each time the counter 57 | is reloaded, then the IWDG will start counting down from this value. 58 | (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. 59 | (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function. 60 | 61 | (#) Window option is disabled: 62 | (++) Enable write access to IWDG_PR and IWDG_RLR registers using 63 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. 64 | (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. 65 | (++) Configure the IWDG counter value using IWDG_SetReload() function. 66 | This value will be loaded in the IWDG counter each time the counter 67 | is reloaded, then the IWDG will start counting down from this value. 68 | (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. 69 | (++) reload the IWDG counter at regular intervals during normal operation 70 | to prevent an MCU reset, using IWDG_ReloadCounter() function. 71 | (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used 72 | in software mode (no need to enable the LSI, it will be enabled 73 | by hardware). 74 | 75 | @endverbatim 76 | * 77 | ****************************************************************************** 78 | * @attention 79 | * 80 | *

© COPYRIGHT 2014 STMicroelectronics

81 | * 82 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 83 | * You may not use this file except in compliance with the License. 84 | * You may obtain a copy of the License at: 85 | * 86 | * http://www.st.com/software_license_agreement_liberty_v2 87 | * 88 | * Unless required by applicable law or agreed to in writing, software 89 | * distributed under the License is distributed on an "AS IS" BASIS, 90 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 91 | * See the License for the specific language governing permissions and 92 | * limitations under the License. 93 | * 94 | ****************************************************************************** 95 | */ 96 | 97 | /* Includes ------------------------------------------------------------------*/ 98 | #include "stm32f0xx_iwdg.h" 99 | 100 | /** @addtogroup STM32F0xx_StdPeriph_Driver 101 | * @{ 102 | */ 103 | 104 | /** @defgroup IWDG 105 | * @brief IWDG driver modules 106 | * @{ 107 | */ 108 | 109 | /* Private typedef -----------------------------------------------------------*/ 110 | /* Private define ------------------------------------------------------------*/ 111 | /* ---------------------- IWDG registers bit mask ----------------------------*/ 112 | /* KR register bit mask */ 113 | #define KR_KEY_RELOAD ((uint16_t)0xAAAA) 114 | #define KR_KEY_ENABLE ((uint16_t)0xCCCC) 115 | 116 | /* Private macro -------------------------------------------------------------*/ 117 | /* Private variables ---------------------------------------------------------*/ 118 | /* Private function prototypes -----------------------------------------------*/ 119 | /* Private functions ---------------------------------------------------------*/ 120 | 121 | /** @defgroup IWDG_Private_Functions 122 | * @{ 123 | */ 124 | 125 | /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions 126 | * @brief Prescaler and Counter configuration functions 127 | * 128 | @verbatim 129 | ============================================================================== 130 | ##### Prescaler and Counter configuration functions ##### 131 | ============================================================================== 132 | 133 | @endverbatim 134 | * @{ 135 | */ 136 | 137 | /** 138 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. 139 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. 140 | * This parameter can be one of the following values: 141 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers 142 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers 143 | * @retval None 144 | */ 145 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 146 | { 147 | /* Check the parameters */ 148 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); 149 | IWDG->KR = IWDG_WriteAccess; 150 | } 151 | 152 | /** 153 | * @brief Sets IWDG Prescaler value. 154 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value. 155 | * This parameter can be one of the following values: 156 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 157 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 158 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 159 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 160 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 161 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 162 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 163 | * @retval None 164 | */ 165 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 166 | { 167 | /* Check the parameters */ 168 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); 169 | IWDG->PR = IWDG_Prescaler; 170 | } 171 | 172 | /** 173 | * @brief Sets IWDG Reload value. 174 | * @param Reload: specifies the IWDG Reload value. 175 | * This parameter must be a number between 0 and 0x0FFF. 176 | * @retval None 177 | */ 178 | void IWDG_SetReload(uint16_t Reload) 179 | { 180 | /* Check the parameters */ 181 | assert_param(IS_IWDG_RELOAD(Reload)); 182 | IWDG->RLR = Reload; 183 | } 184 | 185 | /** 186 | * @brief Reloads IWDG counter with value defined in the reload register 187 | * (write access to IWDG_PR and IWDG_RLR registers disabled). 188 | * @param None 189 | * @retval None 190 | */ 191 | void IWDG_ReloadCounter(void) 192 | { 193 | IWDG->KR = KR_KEY_RELOAD; 194 | } 195 | 196 | 197 | /** 198 | * @brief Sets the IWDG window value. 199 | * @param WindowValue: specifies the window value to be compared to the downcounter. 200 | * @retval None 201 | */ 202 | void IWDG_SetWindowValue(uint16_t WindowValue) 203 | { 204 | /* Check the parameters */ 205 | assert_param(IS_IWDG_WINDOW_VALUE(WindowValue)); 206 | IWDG->WINR = WindowValue; 207 | } 208 | 209 | /** 210 | * @} 211 | */ 212 | 213 | /** @defgroup IWDG_Group2 IWDG activation function 214 | * @brief IWDG activation function 215 | * 216 | @verbatim 217 | ============================================================================== 218 | ##### IWDG activation function ##### 219 | ============================================================================== 220 | 221 | @endverbatim 222 | * @{ 223 | */ 224 | 225 | /** 226 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). 227 | * @param None 228 | * @retval None 229 | */ 230 | void IWDG_Enable(void) 231 | { 232 | IWDG->KR = KR_KEY_ENABLE; 233 | } 234 | 235 | /** 236 | * @} 237 | */ 238 | 239 | /** @defgroup IWDG_Group3 Flag management function 240 | * @brief Flag management function 241 | * 242 | @verbatim 243 | =============================================================================== 244 | ##### Flag management function ##### 245 | =============================================================================== 246 | 247 | @endverbatim 248 | * @{ 249 | */ 250 | 251 | /** 252 | * @brief Checks whether the specified IWDG flag is set or not. 253 | * @param IWDG_FLAG: specifies the flag to check. 254 | * This parameter can be one of the following values: 255 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going 256 | * @arg IWDG_FLAG_RVU: Reload Value Update on going 257 | * @arg IWDG_FLAG_WVU: Counter Window Value Update on going 258 | * @retval The new state of IWDG_FLAG (SET or RESET). 259 | */ 260 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 261 | { 262 | FlagStatus bitstatus = RESET; 263 | /* Check the parameters */ 264 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); 265 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) 266 | { 267 | bitstatus = SET; 268 | } 269 | else 270 | { 271 | bitstatus = RESET; 272 | } 273 | /* Return the flag status */ 274 | return bitstatus; 275 | } 276 | 277 | /** 278 | * @} 279 | */ 280 | 281 | /** 282 | * @} 283 | */ 284 | 285 | /** 286 | * @} 287 | */ 288 | 289 | /** 290 | * @} 291 | */ 292 | 293 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 294 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_crc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_crc.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of CRC computation unit peripheral: 9 | * + Configuration of the CRC computation unit 10 | * + CRC computation of one/many 32-bit data 11 | * + CRC Independent register (IDR) access 12 | * 13 | * @verbatim 14 | =============================================================================== 15 | ##### How to use this driver ##### 16 | =============================================================================== 17 | [..] 18 | 19 | (+) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE) 20 | function 21 | (+) If required, select the reverse operation on input data 22 | using CRC_ReverseInputDataSelect() 23 | (+) If required, enable the reverse operation on output data 24 | using CRC_ReverseOutputDataCmd(Enable) 25 | (+) use CRC_CalcCRC() function to compute the CRC of a 32-bit data 26 | or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit 27 | data buffer 28 | (@) To compute the CRC of a new data use CRC_ResetDR() to reset 29 | the CRC computation unit before starting the computation 30 | otherwise you can get wrong CRC values. 31 | 32 | @endverbatim 33 | * 34 | ****************************************************************************** 35 | * @attention 36 | * 37 | *

© COPYRIGHT 2014 STMicroelectronics

38 | * 39 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 40 | * You may not use this file except in compliance with the License. 41 | * You may obtain a copy of the License at: 42 | * 43 | * http://www.st.com/software_license_agreement_liberty_v2 44 | * 45 | * Unless required by applicable law or agreed to in writing, software 46 | * distributed under the License is distributed on an "AS IS" BASIS, 47 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 48 | * See the License for the specific language governing permissions and 49 | * limitations under the License. 50 | * 51 | ****************************************************************************** 52 | */ 53 | 54 | /* Includes ------------------------------------------------------------------*/ 55 | #include "stm32f0xx_crc.h" 56 | 57 | /** @addtogroup STM32F0xx_StdPeriph_Driver 58 | * @{ 59 | */ 60 | 61 | /** @defgroup CRC 62 | * @brief CRC driver modules 63 | * @{ 64 | */ 65 | 66 | /* Private typedef -----------------------------------------------------------*/ 67 | /* Private define ------------------------------------------------------------*/ 68 | /* Private macro -------------------------------------------------------------*/ 69 | /* Private variables ---------------------------------------------------------*/ 70 | /* Private function prototypes -----------------------------------------------*/ 71 | /* Private functions ---------------------------------------------------------*/ 72 | 73 | /** @defgroup CRC_Private_Functions 74 | * @{ 75 | */ 76 | 77 | /** @defgroup CRC_Group1 Configuration of the CRC computation unit functions 78 | * @brief Configuration of the CRC computation unit functions 79 | * 80 | @verbatim 81 | =============================================================================== 82 | ##### CRC configuration functions ##### 83 | =============================================================================== 84 | 85 | @endverbatim 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @brief Deinitializes CRC peripheral registers to their default reset values. 91 | * @param None 92 | * @retval None 93 | */ 94 | void CRC_DeInit(void) 95 | { 96 | /* Set DR register to reset value */ 97 | CRC->DR = 0xFFFFFFFF; 98 | 99 | /* Set the POL register to the reset value: 0x04C11DB7 */ 100 | CRC->POL = 0x04C11DB7; 101 | 102 | /* Reset IDR register */ 103 | CRC->IDR = 0x00; 104 | 105 | /* Set INIT register to reset value */ 106 | CRC->INIT = 0xFFFFFFFF; 107 | 108 | /* Reset the CRC calculation unit */ 109 | CRC->CR = CRC_CR_RESET; 110 | } 111 | 112 | /** 113 | * @brief Resets the CRC calculation unit and sets INIT register content in DR register. 114 | * @param None 115 | * @retval None 116 | */ 117 | void CRC_ResetDR(void) 118 | { 119 | /* Reset CRC generator */ 120 | CRC->CR |= CRC_CR_RESET; 121 | } 122 | 123 | /** 124 | * @brief Selects the polynomial size. This function is only applicable for 125 | * STM32F072 devices. 126 | * @param CRC_PolSize: Specifies the polynomial size. 127 | * This parameter can be: 128 | * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation 129 | * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation 130 | * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation 131 | * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation 132 | * @retval None 133 | */ 134 | void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize) 135 | { 136 | uint32_t tmpcr = 0; 137 | 138 | /* Check the parameter */ 139 | assert_param(IS_CRC_POL_SIZE(CRC_PolSize)); 140 | 141 | /* Get CR register value */ 142 | tmpcr = CRC->CR; 143 | 144 | /* Reset POL_SIZE bits */ 145 | tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE); 146 | /* Set the polynomial size */ 147 | tmpcr |= (uint32_t)CRC_PolSize; 148 | 149 | /* Write to CR register */ 150 | CRC->CR = (uint32_t)tmpcr; 151 | } 152 | 153 | /** 154 | * @brief Selects the reverse operation to be performed on input data. 155 | * @param CRC_ReverseInputData: Specifies the reverse operation on input data. 156 | * This parameter can be: 157 | * @arg CRC_ReverseInputData_No: No reverse operation is performed 158 | * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits 159 | * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits 160 | * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits 161 | * @retval None 162 | */ 163 | void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData) 164 | { 165 | uint32_t tmpcr = 0; 166 | 167 | /* Check the parameter */ 168 | assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData)); 169 | 170 | /* Get CR register value */ 171 | tmpcr = CRC->CR; 172 | 173 | /* Reset REV_IN bits */ 174 | tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN); 175 | /* Set the reverse operation */ 176 | tmpcr |= (uint32_t)CRC_ReverseInputData; 177 | 178 | /* Write to CR register */ 179 | CRC->CR = (uint32_t)tmpcr; 180 | } 181 | 182 | /** 183 | * @brief Enables or disable the reverse operation on output data. 184 | * The reverse operation on output data is performed on 32-bit. 185 | * @param NewState: new state of the reverse operation on output data. 186 | * This parameter can be: ENABLE or DISABLE. 187 | * @retval None 188 | */ 189 | void CRC_ReverseOutputDataCmd(FunctionalState NewState) 190 | { 191 | /* Check the parameters */ 192 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 193 | 194 | if (NewState != DISABLE) 195 | { 196 | /* Enable reverse operation on output data */ 197 | CRC->CR |= CRC_CR_REV_OUT; 198 | } 199 | else 200 | { 201 | /* Disable reverse operation on output data */ 202 | CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT); 203 | } 204 | } 205 | 206 | /** 207 | * @brief Initializes the INIT register. 208 | * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register 209 | * @param CRC_InitValue: Programmable initial CRC value 210 | * @retval None 211 | */ 212 | void CRC_SetInitRegister(uint32_t CRC_InitValue) 213 | { 214 | CRC->INIT = CRC_InitValue; 215 | } 216 | 217 | /** 218 | * @brief Initializes the polynomail coefficients. This function is only 219 | * applicable for STM32F072 devices. 220 | * @param CRC_Pol: Polynomial to be used for CRC calculation. 221 | * @retval None 222 | */ 223 | void CRC_SetPolynomial(uint32_t CRC_Pol) 224 | { 225 | CRC->POL = CRC_Pol; 226 | } 227 | 228 | /** 229 | * @} 230 | */ 231 | 232 | /** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions 233 | * @brief CRC computation of one/many 32-bit data functions 234 | * 235 | @verbatim 236 | =============================================================================== 237 | ##### CRC computation functions ##### 238 | =============================================================================== 239 | 240 | @endverbatim 241 | * @{ 242 | */ 243 | 244 | /** 245 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 246 | * @param CRC_Data: data word(32-bit) to compute its CRC 247 | * @retval 32-bit CRC 248 | */ 249 | uint32_t CRC_CalcCRC(uint32_t CRC_Data) 250 | { 251 | CRC->DR = CRC_Data; 252 | 253 | return (CRC->DR); 254 | } 255 | 256 | /** 257 | * @brief Computes the 16-bit CRC of a given 16-bit data. This function is only 258 | * applicable for STM32F072 devices. 259 | * @param CRC_Data: data half-word(16-bit) to compute its CRC 260 | * @retval 16-bit CRC 261 | */ 262 | uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data) 263 | { 264 | *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data; 265 | 266 | return (CRC->DR); 267 | } 268 | 269 | /** 270 | * @brief Computes the 8-bit CRC of a given 8-bit data. This function is only 271 | * applicable for STM32F072 devices. 272 | * @param CRC_Data: 8-bit data to compute its CRC 273 | * @retval 8-bit CRC 274 | */ 275 | uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data) 276 | { 277 | *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data; 278 | 279 | return (CRC->DR); 280 | } 281 | 282 | /** 283 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 284 | * @param pBuffer: pointer to the buffer containing the data to be computed 285 | * @param BufferLength: length of the buffer to be computed 286 | * @retval 32-bit CRC 287 | */ 288 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 289 | { 290 | uint32_t index = 0; 291 | 292 | for(index = 0; index < BufferLength; index++) 293 | { 294 | CRC->DR = pBuffer[index]; 295 | } 296 | return (CRC->DR); 297 | } 298 | 299 | /** 300 | * @brief Returns the current CRC value. 301 | * @param None 302 | * @retval 32-bit CRC 303 | */ 304 | uint32_t CRC_GetCRC(void) 305 | { 306 | return (CRC->DR); 307 | } 308 | 309 | /** 310 | * @} 311 | */ 312 | 313 | /** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions 314 | * @brief CRC Independent Register (IDR) access (write/read) functions 315 | * 316 | @verbatim 317 | =============================================================================== 318 | ##### CRC Independent Register (IDR) access functions ##### 319 | =============================================================================== 320 | 321 | @endverbatim 322 | * @{ 323 | */ 324 | 325 | /** 326 | * @brief Stores an 8-bit data in the Independent Data(ID) register. 327 | * @param CRC_IDValue: 8-bit value to be stored in the ID register 328 | * @retval None 329 | */ 330 | void CRC_SetIDRegister(uint8_t CRC_IDValue) 331 | { 332 | CRC->IDR = CRC_IDValue; 333 | } 334 | 335 | /** 336 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register 337 | * @param None 338 | * @retval 8-bit value of the ID register 339 | */ 340 | uint8_t CRC_GetIDRegister(void) 341 | { 342 | return (CRC->IDR); 343 | } 344 | 345 | /** 346 | * @} 347 | */ 348 | 349 | /** 350 | * @} 351 | */ 352 | 353 | /** 354 | * @} 355 | */ 356 | 357 | /** 358 | * @} 359 | */ 360 | 361 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 362 | -------------------------------------------------------------------------------- /f030_r820t2/StdPeriph/stm32f0xx_cec.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_cec.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the CEC firmware 8 | * library, applicable only for STM32F051, STM32F042 and STM32F072 devices. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_CEC_H 31 | #define __STM32F0XX_CEC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CEC 45 | * @{ 46 | */ 47 | /* Exported types ------------------------------------------------------------*/ 48 | 49 | /** 50 | * @brief CEC Init structure definition 51 | */ 52 | typedef struct 53 | { 54 | uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration. 55 | This parameter can be a value of @ref CEC_Signal_Free_Time */ 56 | uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance. 57 | This parameter can be a value of @ref CEC_RxTolerance */ 58 | uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception. 59 | This parameter can be a value of @ref CEC_Stop_Reception */ 60 | uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation. 61 | This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */ 62 | uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation. 63 | This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */ 64 | uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation. 65 | This parameter can be a value of @ref CEC_BDR_No_Gen */ 66 | uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option. 67 | This parameter can be a value of @ref CEC_SFT_Option */ 68 | 69 | }CEC_InitTypeDef; 70 | 71 | /* Exported constants --------------------------------------------------------*/ 72 | 73 | /** @defgroup CEC_Exported_Constants 74 | * @{ 75 | */ 76 | 77 | /** @defgroup CEC_Signal_Free_Time 78 | * @{ 79 | */ 80 | #define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */ 81 | #define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */ 82 | #define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */ 83 | #define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */ 84 | #define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */ 85 | #define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */ 86 | #define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */ 87 | #define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */ 88 | 89 | #define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \ 90 | ((TIME) == CEC_SignalFreeTime_1T)|| \ 91 | ((TIME) == CEC_SignalFreeTime_2T)|| \ 92 | ((TIME) == CEC_SignalFreeTime_3T)|| \ 93 | ((TIME) == CEC_SignalFreeTime_4T)|| \ 94 | ((TIME) == CEC_SignalFreeTime_5T)|| \ 95 | ((TIME) == CEC_SignalFreeTime_6T)|| \ 96 | ((TIME) == CEC_SignalFreeTime_7T)) 97 | /** 98 | * @} 99 | */ 100 | 101 | /** @defgroup CEC_RxTolerance 102 | * @{ 103 | */ 104 | #define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */ 105 | #define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */ 106 | 107 | #define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \ 108 | ((TOLERANCE) == CEC_RxTolerance_Extended)) 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @defgroup CEC_Stop_Reception 114 | * @{ 115 | */ 116 | #define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */ 117 | #define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */ 118 | 119 | #define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \ 120 | ((RECEPTION) == CEC_StopReception_Off)) 121 | /** 122 | * @} 123 | */ 124 | 125 | /** @defgroup CEC_Bit_Rising_Error_Generation 126 | * @{ 127 | */ 128 | #define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */ 129 | #define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */ 130 | 131 | #define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \ 132 | ((ERROR) == CEC_BitRisingError_On)) 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup CEC_Long_Bit_Error_Generation 138 | * @{ 139 | */ 140 | #define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */ 141 | #define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */ 142 | 143 | #define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \ 144 | ((ERROR) == CEC_LongBitPeriodError_On)) 145 | /** 146 | * @} 147 | */ 148 | 149 | /** @defgroup CEC_BDR_No_Gen 150 | * @{ 151 | */ 152 | 153 | #define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */ 154 | #define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */ 155 | 156 | #define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \ 157 | ((ERROR) == CEC_BRDNoGen_On)) 158 | /** 159 | * @} 160 | */ 161 | 162 | /** @defgroup CEC_SFT_Option 163 | * @{ 164 | */ 165 | #define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */ 166 | #define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */ 167 | 168 | #define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \ 169 | ((OPTION) == CEC_SFTOption_On)) 170 | /** 171 | * @} 172 | */ 173 | 174 | /** @defgroup CEC_Own_Address 175 | * @{ 176 | */ 177 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /** @defgroup CEC_Interrupt_Configuration_definition 184 | * @{ 185 | */ 186 | #define CEC_IT_TXACKE CEC_IER_TXACKEIE 187 | #define CEC_IT_TXERR CEC_IER_TXERRIE 188 | #define CEC_IT_TXUDR CEC_IER_TXUDRIE 189 | #define CEC_IT_TXEND CEC_IER_TXENDIE 190 | #define CEC_IT_TXBR CEC_IER_TXBRIE 191 | #define CEC_IT_ARBLST CEC_IER_ARBLSTIE 192 | #define CEC_IT_RXACKE CEC_IER_RXACKEIE 193 | #define CEC_IT_LBPE CEC_IER_LBPEIE 194 | #define CEC_IT_SBPE CEC_IER_SBPEIE 195 | #define CEC_IT_BRE CEC_IER_BREIEIE 196 | #define CEC_IT_RXOVR CEC_IER_RXOVRIE 197 | #define CEC_IT_RXEND CEC_IER_RXENDIE 198 | #define CEC_IT_RXBR CEC_IER_RXBRIE 199 | 200 | #define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00)) 201 | 202 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \ 203 | ((IT) == CEC_IT_TXERR)|| \ 204 | ((IT) == CEC_IT_TXUDR)|| \ 205 | ((IT) == CEC_IT_TXEND)|| \ 206 | ((IT) == CEC_IT_TXBR)|| \ 207 | ((IT) == CEC_IT_ARBLST)|| \ 208 | ((IT) == CEC_IT_RXACKE)|| \ 209 | ((IT) == CEC_IT_LBPE)|| \ 210 | ((IT) == CEC_IT_SBPE)|| \ 211 | ((IT) == CEC_IT_BRE)|| \ 212 | ((IT) == CEC_IT_RXOVR)|| \ 213 | ((IT) == CEC_IT_RXEND)|| \ 214 | ((IT) == CEC_IT_RXBR)) 215 | /** 216 | * @} 217 | */ 218 | 219 | /** @defgroup CEC_ISR_register_flags_definition 220 | * @{ 221 | */ 222 | #define CEC_FLAG_TXACKE CEC_ISR_TXACKE 223 | #define CEC_FLAG_TXERR CEC_ISR_TXERR 224 | #define CEC_FLAG_TXUDR CEC_ISR_TXUDR 225 | #define CEC_FLAG_TXEND CEC_ISR_TXEND 226 | #define CEC_FLAG_TXBR CEC_ISR_TXBR 227 | #define CEC_FLAG_ARBLST CEC_ISR_ARBLST 228 | #define CEC_FLAG_RXACKE CEC_ISR_RXACKE 229 | #define CEC_FLAG_LBPE CEC_ISR_LBPE 230 | #define CEC_FLAG_SBPE CEC_ISR_SBPE 231 | #define CEC_FLAG_BRE CEC_ISR_BRE 232 | #define CEC_FLAG_RXOVR CEC_ISR_RXOVR 233 | #define CEC_FLAG_RXEND CEC_ISR_RXEND 234 | #define CEC_FLAG_RXBR CEC_ISR_RXBR 235 | 236 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00)) 237 | 238 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \ 239 | ((FLAG) == CEC_FLAG_TXERR)|| \ 240 | ((FLAG) == CEC_FLAG_TXUDR)|| \ 241 | ((FLAG) == CEC_FLAG_TXEND)|| \ 242 | ((FLAG) == CEC_FLAG_TXBR)|| \ 243 | ((FLAG) == CEC_FLAG_ARBLST)|| \ 244 | ((FLAG) == CEC_FLAG_RXACKE)|| \ 245 | ((FLAG) == CEC_FLAG_LBPE)|| \ 246 | ((FLAG) == CEC_FLAG_SBPE)|| \ 247 | ((FLAG) == CEC_FLAG_BRE)|| \ 248 | ((FLAG) == CEC_FLAG_RXOVR)|| \ 249 | ((FLAG) == CEC_FLAG_RXEND)|| \ 250 | ((FLAG) == CEC_FLAG_RXBR)) 251 | /** 252 | * @} 253 | */ 254 | 255 | /** 256 | * @} 257 | */ 258 | 259 | /* Exported macro ------------------------------------------------------------*/ 260 | /* Exported functions ------------------------------------------------------- */ 261 | 262 | /* Function used to set the CEC configuration to the default reset state *****/ 263 | void CEC_DeInit(void); 264 | 265 | /* CEC_Initialization and Configuration functions *****************************/ 266 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); 267 | void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct); 268 | void CEC_Cmd(FunctionalState NewState); 269 | void CEC_ListenModeCmd(FunctionalState NewState); 270 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); 271 | void CEC_OwnAddressClear(void); 272 | 273 | /* CEC_Data transfers functions ***********************************************/ 274 | void CEC_SendData(uint8_t Data); 275 | uint8_t CEC_ReceiveData(void); 276 | void CEC_StartOfMessage(void); 277 | void CEC_EndOfMessage(void); 278 | 279 | /* CEC_Interrupts and flags management functions ******************************/ 280 | void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState); 281 | FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG); 282 | void CEC_ClearFlag(uint32_t CEC_FLAG); 283 | ITStatus CEC_GetITStatus(uint16_t CEC_IT); 284 | void CEC_ClearITPendingBit(uint16_t CEC_IT); 285 | 286 | #ifdef __cplusplus 287 | } 288 | #endif 289 | 290 | #endif /* __STM32F0XX_CEC_H */ 291 | 292 | /** 293 | * @} 294 | */ 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 301 | -------------------------------------------------------------------------------- /f030_r820t2/CMSIS/system_stm32f0xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f0xx.c 4 | * @author MCD Application Team 5 | * @version V1.4.0 6 | * @date 05-December-2014 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. 8 | * This file contains the system clock configuration for STM32F0xx devices, 9 | * and is generated by the clock configuration tool 10 | * STM32F0xx_Clock_Configuration_V1.0.0.xls 11 | * 12 | * 1. This file provides two functions and one global variable to be called from 13 | * user application: 14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 15 | * and Divider factors, AHB/APBx prescalers and Flash settings), 16 | * depending on the configuration made in the clock xls tool. 17 | * This function is called at startup just after reset and 18 | * before branch to main program. This call is made inside 19 | * the "startup_stm32f0xx.s" file. 20 | * 21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 22 | * by the user application to setup the SysTick 23 | * timer or configure other parameters. 24 | * 25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 26 | * be called whenever the core clock is changed 27 | * during program execution. 28 | * 29 | * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. 30 | * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to 31 | * configure the system clock before to branch to main program. 32 | * 33 | * 3. If the system clock source selected by user fails to startup, the SystemInit() 34 | * function will do nothing and HSI still used as system clock source. User can 35 | * add some code to deal with this issue inside the SetSysClock() function. 36 | * 37 | * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define 38 | * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or 39 | * through PLL, and you are using different crystal you have to adapt the HSE 40 | * value to your own configuration. 41 | * 42 | * 5. This file configures the system clock as follows: 43 | *============================================================================= 44 | * System Clock Configuration 45 | *============================================================================= 46 | * System Clock source | PLL(HSE or HSI) 47 | *----------------------------------------------------------------------------- 48 | * SYSCLK | 48000000 Hz 49 | *----------------------------------------------------------------------------- 50 | * HCLK | 48000000 Hz 51 | *----------------------------------------------------------------------------- 52 | * AHB Prescaler | 1 53 | *----------------------------------------------------------------------------- 54 | * APB1 Prescaler | 1 55 | *----------------------------------------------------------------------------- 56 | * APB2 Prescaler | 1 57 | *----------------------------------------------------------------------------- 58 | * HSE Frequency | 8000000 Hz 59 | *----------------------------------------------------------------------------- 60 | * PLL MUL | 6 61 | *----------------------------------------------------------------------------- 62 | * VDD | 3.3 V 63 | *----------------------------------------------------------------------------- 64 | * Flash Latency | 1 WS 65 | *----------------------------------------------------------------------------- 66 | *============================================================================= 67 | ****************************************************************************** 68 | * @attention 69 | * 70 | *

© COPYRIGHT 2014 STMicroelectronics

71 | * 72 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 73 | * You may not use this file except in compliance with the License. 74 | * You may obtain a copy of the License at: 75 | * 76 | * http://www.st.com/software_license_agreement_liberty_v2 77 | * 78 | * Unless required by applicable law or agreed to in writing, software 79 | * distributed under the License is distributed on an "AS IS" BASIS, 80 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 81 | * See the License for the specific language governing permissions and 82 | * limitations under the License. 83 | * 84 | ****************************************************************************** 85 | */ 86 | 87 | /** @addtogroup CMSIS 88 | * @{ 89 | */ 90 | 91 | /** @addtogroup stm32f0xx_system 92 | * @{ 93 | */ 94 | 95 | /** @addtogroup STM32F0xx_System_Private_Includes 96 | * @{ 97 | */ 98 | 99 | #include "stm32f0xx.h" 100 | 101 | /** 102 | * @} 103 | */ 104 | 105 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions 106 | * @{ 107 | */ 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @addtogroup STM32F0xx_System_Private_Defines 114 | * @{ 115 | */ 116 | /** 117 | * @} 118 | */ 119 | 120 | /** @addtogroup STM32F0xx_System_Private_Macros 121 | * @{ 122 | */ 123 | 124 | /** 125 | * @} 126 | */ 127 | 128 | /** @addtogroup STM32F0xx_System_Private_Variables 129 | * @{ 130 | */ 131 | uint32_t SystemCoreClock = 48000000; 132 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 133 | 134 | /** 135 | * @} 136 | */ 137 | 138 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes 139 | * @{ 140 | */ 141 | 142 | static void SetSysClock(void); 143 | 144 | /** 145 | * @} 146 | */ 147 | 148 | /** @addtogroup STM32F0xx_System_Private_Functions 149 | * @{ 150 | */ 151 | 152 | /** 153 | * @brief Setup the microcontroller system. 154 | * Initialize the Embedded Flash Interface, the PLL and update the 155 | * SystemCoreClock variable. 156 | * @param None 157 | * @retval None 158 | */ 159 | void SystemInit (void) 160 | { 161 | /* Set HSION bit */ 162 | RCC->CR |= (uint32_t)0x00000001; 163 | 164 | #if defined(STM32F051) 165 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ 166 | RCC->CFGR &= (uint32_t)0xF8FFB80C; 167 | #else 168 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ 169 | RCC->CFGR &= (uint32_t)0x08FFB80C; 170 | #endif /* STM32F051 */ 171 | 172 | /* Reset HSEON, CSSON and PLLON bits */ 173 | RCC->CR &= (uint32_t)0xFEF6FFFF; 174 | 175 | /* Reset HSEBYP bit */ 176 | RCC->CR &= (uint32_t)0xFFFBFFFF; 177 | 178 | /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ 179 | RCC->CFGR &= (uint32_t)0xFFC0FFFF; 180 | 181 | /* Reset PREDIV1[3:0] bits */ 182 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; 183 | 184 | /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ 185 | RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; 186 | 187 | /* Reset HSI14 bit */ 188 | RCC->CR2 &= (uint32_t)0xFFFFFFFE; 189 | 190 | /* Disable all interrupts */ 191 | RCC->CIR = 0x00000000; 192 | 193 | /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ 194 | SetSysClock(); 195 | } 196 | 197 | /** 198 | * @brief Update SystemCoreClock according to Clock Register Values 199 | * The SystemCoreClock variable contains the core clock (HCLK), it can 200 | * be used by the user application to setup the SysTick timer or configure 201 | * other parameters. 202 | * 203 | * @note Each time the core clock (HCLK) changes, this function must be called 204 | * to update SystemCoreClock variable value. Otherwise, any configuration 205 | * based on this variable will be incorrect. 206 | * 207 | * @note - The system frequency computed by this function is not the real 208 | * frequency in the chip. It is calculated based on the predefined 209 | * constant and the selected clock source: 210 | * 211 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 212 | * 213 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 214 | * 215 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 216 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 217 | * 218 | * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value 219 | * 8 MHz) but the real value may vary depending on the variations 220 | * in voltage and temperature. 221 | * 222 | * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value 223 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real 224 | * frequency of the crystal used. Otherwise, this function may 225 | * have wrong result. 226 | * 227 | * - The result of this function could be not correct when using fractional 228 | * value for HSE crystal. 229 | * @param None 230 | * @retval None 231 | */ 232 | void SystemCoreClockUpdate (void) 233 | { 234 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; 235 | 236 | /* Get SYSCLK source -------------------------------------------------------*/ 237 | tmp = RCC->CFGR & RCC_CFGR_SWS; 238 | 239 | switch (tmp) 240 | { 241 | case 0x00: /* HSI used as system clock */ 242 | SystemCoreClock = HSI_VALUE; 243 | break; 244 | case 0x04: /* HSE used as system clock */ 245 | SystemCoreClock = HSE_VALUE; 246 | break; 247 | case 0x08: /* PLL used as system clock */ 248 | /* Get PLL clock source and multiplication factor ----------------------*/ 249 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 250 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 251 | pllmull = ( pllmull >> 18) + 2; 252 | 253 | if (pllsource == 0x00) 254 | { 255 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 256 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 257 | } 258 | else 259 | { 260 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 261 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 262 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 263 | } 264 | break; 265 | default: /* HSI used as system clock */ 266 | SystemCoreClock = HSI_VALUE; 267 | break; 268 | } 269 | /* Compute HCLK clock frequency ----------------*/ 270 | /* Get HCLK prescaler */ 271 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 272 | /* HCLK clock frequency */ 273 | SystemCoreClock >>= tmp; 274 | } 275 | 276 | /** 277 | * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash 278 | * settings. 279 | * @note This function should be called only once the RCC clock configuration 280 | * is reset to the default reset state (done in SystemInit() function). 281 | * @param None 282 | * @retval None 283 | */ 284 | static void SetSysClock(void) 285 | { 286 | /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ 287 | 288 | #if 1 289 | /* Enable HSE */ 290 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 291 | 292 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 293 | 294 | /* Wait till HSE is ready and if Time out is reached exit */ 295 | do 296 | { 297 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 298 | StartUpCounter++; 299 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 300 | 301 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 302 | { 303 | HSEStatus = (uint32_t)0x01; 304 | } 305 | else 306 | { 307 | HSEStatus = (uint32_t)0x00; 308 | } 309 | 310 | if (HSEStatus == (uint32_t)0x01) 311 | { 312 | /* Enable Prefetch Buffer and set Flash Latency */ 313 | FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; 314 | 315 | /* HCLK = SYSCLK */ 316 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 317 | 318 | /* PCLK = HCLK */ 319 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; 320 | 321 | /* PLL configuration = HSE * 6 = 48 MHz */ 322 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 323 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); 324 | 325 | /* Enable PLL */ 326 | RCC->CR |= RCC_CR_PLLON; 327 | 328 | /* Wait till PLL is ready */ 329 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 330 | { 331 | } 332 | 333 | /* Select PLL as system clock source */ 334 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 335 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 336 | 337 | /* Wait till PLL is used as system clock source */ 338 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) 339 | { 340 | } 341 | } 342 | else 343 | { /* If HSE fails to start-up, the application will have wrong clock 344 | configuration. User can add here some code to deal with this error */ 345 | } 346 | #else 347 | /* Use HSI */ 348 | 349 | /* Enable Prefetch Buffer and set Flash Latency */ 350 | FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; 351 | 352 | /* HCLK = SYSCLK */ 353 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 354 | 355 | /* PCLK = HCLK */ 356 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; 357 | 358 | /* PLL configuration = HSI * 6 = 48 MHz */ 359 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 360 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLMULL12); 361 | 362 | /* Enable PLL */ 363 | RCC->CR |= RCC_CR_PLLON; 364 | 365 | /* Wait till PLL is ready */ 366 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 367 | { 368 | } 369 | 370 | /* Select PLL as system clock source */ 371 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 372 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 373 | 374 | /* Wait till PLL is used as system clock source */ 375 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) 376 | { 377 | } 378 | #endif 379 | } 380 | 381 | /** 382 | * @} 383 | */ 384 | 385 | /** 386 | * @} 387 | */ 388 | 389 | /** 390 | * @} 391 | */ 392 | 393 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 394 | --------------------------------------------------------------------------------