├── Project ├── airfield_control_system.v ├── airfield_control_system_tb.v └── project.pdf ├── README.md ├── lab2 ├── lab2.v ├── lab2_tb.v └── question.png ├── lab3 ├── lab3.v ├── lab3_tb.v ├── question.png ├── schematic.png └── simulation.png ├── lab4 ├── lab4.v ├── lab4_1.v ├── lab4_tb.v └── question.png ├── lab4_2 ├── lab4_2.v ├── lab4_2_1.v ├── lab4_2_tb.v ├── main_schematic.png ├── question .png └── rlt_schematic.png ├── lab5_1 ├── Full Adder Circuit.png ├── full_adder.v ├── half_adder.v ├── module_adder.v ├── module_adder_tb.v └── question.png ├── lab5_2 ├── Full Adder Circuit.png ├── Half Adder Circuit.png ├── full_adder.v ├── half_adder.v ├── module_adder.v ├── module_adder_tb.v └── question.png ├── lab6_1 ├── comparator.png ├── comparator.v ├── comparator_tb.v └── question.png ├── lab6_2 ├── comparator.png ├── comparator2.v ├── comparator2_tb.v ├── question.png └── simulation.png ├── lab7 ├── SR_Latch.png ├── SR_latch.v ├── SR_latch_control.v ├── SR_latch_control_tb.v └── question.png └── lab8 ├── frequency_divider.v ├── frequency_divider_tb.v └── question.png /Project/airfield_control_system.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module airfield_control_system(clk,passengers,weather,airfield,led1,led2); 4 | 5 | input clk; 6 | input weather; // weather conditions are favorable or unsuitable. 0 means bad weather 7 | // The weather condition will act as a control input. 8 | input [5:0] passengers; // capacity could be max 60 9 | input airfield; // airfield availability , "is there a plane or not" 0 means available 10 | 11 | output reg[2:0] led1; // led1 is the right led in the photo. 12 | output reg[2:0] led2; //led2 is the left led in the photo. 13 | 14 | //Led1 has 2 color , led2 has 3 color. 15 | // led[0] --> green (keep moving) 16 | // led[1] --> red (wait) 17 | // led[2] --> yellow ( keep moving but be careful) 18 | 19 | initial begin 20 | 21 | led1[0] = 0; // In the first case, the airfield is not available and the led turns red. 22 | led1[1] = 1; 23 | led1[2] = 0; 24 | led2[0] = 0; // If led1 is red, led2 should light up red. 25 | led2[1] = 1; 26 | led2[2] = 0; 27 | end 28 | always @ (posedge clk) 29 | begin 30 | if (airfield == 0) // runway available 31 | begin 32 | if ( weather == 1 ) 33 | begin 34 | if ( passengers < 60) //its not emergency and 35 | begin //could be only 1 plane 36 | led1[0] <= 1; 37 | led1[1] <= 0 ; // We turned our LED1 on green 38 | led2[2] <= 0; // and LED2 on red. 39 | led2[0] <= 0; 40 | led2[1] <= 1; 41 | led2[2] <= 0; 42 | end 43 | else // if passengers > 60) // The waiting area is crowded, 44 | begin //so an emergency is declared. 45 | led1[0] <= 1; 46 | led1[1] <= 0; //Since there was no aircraft at the airport before, 47 | led1[2] <= 0; //although LED1 was green, LED2 turns yellow. 48 | led2[0] <= 0; 49 | led2[1] <= 0; 50 | led2[2] <= 1; 51 | end 52 | end 53 | end 54 | if (airfield == 0) 55 | begin //If the weather conditions are not suitable, 56 | if (weather == 0 ) //take-off and landing are not allowed. 57 | begin 58 | led1[0] <= 0; 59 | led1[1] <= 1; 60 | led1[2] <= 0; 61 | led2[0] <= 0; 62 | led2[1] <= 1; 63 | led2[2] <= 0; 64 | end 65 | end 66 | if (airfield == 1) //there is plane at runway 67 | begin 68 | if (weather == 1) 69 | begin 70 | if (passengers > 60) 71 | begin 72 | led1[0] <= 0; 73 | led1[1] <= 0; 74 | led1[2] <= 1; 75 | led2[0] <= 0; 76 | led2[1] <= 1; 77 | led2[2] <= 0; 78 | end 79 | else //if passengers < 60) 80 | begin 81 | led1[0] <= 0; 82 | led1[1] <= 1; 83 | led1[2] <= 0; 84 | led2[0] <= 0; 85 | led2[1] <= 1; 86 | led2[2] <= 0; 87 | end 88 | end 89 | end 90 | if (airfield == 1) 91 | begin 92 | if (weather == 0) 93 | begin 94 | led1[0] <= 0; 95 | led1[1] <= 1; 96 | led1[2] <= 0; 97 | led2[0] <= 0; 98 | led2[1] <= 1; 99 | led2[2] <= 0; 100 | end 101 | end 102 | end 103 | endmodule 104 | -------------------------------------------------------------------------------- /Project/airfield_control_system_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module airfield_control_system_tb(); 3 | reg clk , weather , airfield; 4 | reg [5:0] passengers; 5 | wire [2:0] led1 , led2; 6 | 7 | airfield_control_system UUT(.clk(clk),.weather(weather), 8 | .passengers(passengers), 9 | .airfield(airfield),.led1(led1),.led2(led2) 10 | ); 11 | initial begin 12 | clk = 0; 13 | passengers = 6'b0; 14 | #10; 15 | 16 | airfield = 0; 17 | weather = 1; 18 | passengers = 6'b001111; 19 | #20; 20 | 21 | airfield = 0; 22 | weather = 1; 23 | passengers = 6'b111110; 24 | #20; 25 | 26 | airfield = 1; 27 | weather = 1; 28 | passengers = 6'b001111; 29 | #20; 30 | 31 | airfield = 1; 32 | weather = 1; 33 | passengers = 6'b111101; 34 | #20; 35 | 36 | airfield = 1; 37 | weather = 0; 38 | passengers = 6'b111110; 39 | #20; 40 | end 41 | 42 | always 43 | begin 44 | #10; 45 | clk =~ clk; 46 | end 47 | endmodule 48 | -------------------------------------------------------------------------------- /Project/project.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/Project/project.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPGA - Verilog 2 | ![fpga](https://user-images.githubusercontent.com/87760380/197897931-8453605b-3ab2-403e-9266-8d18bd092480.png) 3 | -------------------------------------------------------------------------------- /lab2/lab2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lab2(in1,in2,out1); 4 | 5 | input [7:0] in1,in2; 6 | output [7:0] out1; 7 | 8 | assign out1 = in1 - in2; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /lab2/lab2_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lab2_tb(); 4 | 5 | reg [7:0] inp1,inp2; 6 | wire [7:0] outp1; 7 | 8 | lab2 UUT( 9 | 10 | .in1(inp1), 11 | .in2(inp2), 12 | .out1(outp1) 13 | 14 | ); 15 | 16 | inital begin 17 | 18 | inp1 = 8'b00011001; 19 | inp2 = 8'b11011001; 20 | 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /lab2/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab2/question.png -------------------------------------------------------------------------------- /lab3/lab3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //num1= 11011011 3 | //num2 10101110 4 | 5 | module lab3(num1,num2,out1); 6 | 7 | input [7:0] num1; 8 | input [7:0] num2; 9 | output [5:0] out1; 10 | 11 | wire [1:0] a_result ; 12 | wire [3:0] b_result; 13 | wire [2:0] c_result; 14 | wire [3:0] d_result; 15 | wire [10:0] e_result; 16 | parameter coef =6'b110010; 17 | 18 | assign a_result = num1[6:5]; 19 | assign b_result = {2{a_result}}; 20 | assign c_result = num1[2:0] ; 21 | assign d_result = num2[3:0]; 22 | assign e_result = {d_result,c_result,b_result}; 23 | assign out1 = e_result / coef; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /lab3/lab3_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab3/lab3_tb.v -------------------------------------------------------------------------------- /lab3/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab3/question.png -------------------------------------------------------------------------------- /lab3/schematic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab3/schematic.png -------------------------------------------------------------------------------- /lab3/simulation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab3/simulation.png -------------------------------------------------------------------------------- /lab4/lab4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lab4(in1,in2,s1,out1); 4 | 5 | input[7:0] in1,in2; 6 | input s1; 7 | output[7:0] out1; 8 | 9 | 10 | assign out1 = s1 ? in2:in1; 11 | //ya da assign out1 = (~s1 && in1 ) || (s1 && in2); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /lab4/lab4_1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lab4_1(inp1,inp2,inp3,inp4,s1,s2,outp1); 4 | 5 | input [7:0] inp1,inp2,inp3,inp4; 6 | input s1,s2; 7 | output [7:0] outp1; 8 | 9 | wire [7:0] w1,w2; 10 | 11 | lab4 mux1(inp1,inp2,s1,w1); 12 | lab4 mux2(inp3,inp4,s1,w2); 13 | lab4 mux3(w1,w2,s2,outp1); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /lab4/lab4_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | 4 | module lab4_tb(); 5 | 6 | reg [7:0] inp1_tb,inp2_tb,inp3_tb,inp4_tb; 7 | reg s1_tb,s2_tb; 8 | wire[7:0] outp1_tb; 9 | 10 | lab4_1 UUT( 11 | .inp1(inp1_tb), 12 | .inp2(inp2_tb), 13 | .inp3(inp3_tb), 14 | .inp4(inp4_tb), 15 | .s1(s1_tb), 16 | .s2(s2_tb), 17 | .outp1(outp1_tb) 18 | ); 19 | 20 | initial begin 21 | s1_tb=0; 22 | s2_tb=1; 23 | 24 | inp1_tb = 8'ha5; 25 | inp2_tb = 8'hb8; 26 | inp3_tb = 8'hc7; 27 | inp4_tb = 8'hd2; 28 | 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /lab4/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab4/question.png -------------------------------------------------------------------------------- /lab4_2/lab4_2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lab4_2(in1,in2,s1,out1); 4 | 5 | input [7:0] in1,in2; 6 | input s1; 7 | output[7:0] out1; 8 | 9 | assign out1 = (s1) ? in2:in1; 10 | endmodule 11 | -------------------------------------------------------------------------------- /lab4_2/lab4_2_1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lab4_2_1(inp1,inp2,inp3,inp4,inp5,inp6,inp7,inp8,s1,s2,s3,w_out); 4 | 5 | input [7:0] inp1,inp2,inp3,inp4,inp5,inp6,inp7,inp8; 6 | input s1,s2,s3; 7 | output [7:0] w_out; 8 | 9 | wire [7:0] w1,w2,w3,w4,w5,w6; 10 | 11 | lab6 u1(inp1,inp2,s1,w1); 12 | lab6 u2(inp3,inp4,s1,w2); 13 | lab6 u3(inp5,inp6,s1,w3); 14 | lab6 u4(inp7,inp8,s1,w4); 15 | 16 | lab6 u5(w1,w2,s2,w5); 17 | lab6 u6(w3,w4,s2,w6); 18 | lab6 u7(w5,w6,s3,w_out); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /lab4_2/lab4_2_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lab4_2_tb(); 4 | 5 | reg [7:0] inp1_tb,inp2_tb,inp3_tb,inp4_tb,inp5_tb,inp6_tb,inp7_tb,inp8_tb; 6 | reg s1_tb,s2_tb,s3_tb; 7 | wire [7:0] w_out_tb; 8 | 9 | lab6_1 UUT( 10 | .inp1(inp1_tb), 11 | .inp2(inp2_tb), 12 | .inp3(inp3_tb), 13 | .inp4(inp4_tb), 14 | .inp5(inp5_tb), 15 | .inp6(inp6_tb), 16 | .inp7(inp7_tb), 17 | .inp8(inp8_tb), 18 | .s1(s1_tb), 19 | .s2(s2_tb), 20 | .s3(s3_tb), 21 | .w_out(w_out_tb) 22 | ); 23 | 24 | initial begin 25 | 26 | s1_tb=0; 27 | s2_tb=1; 28 | s3_tb=0; 29 | inp1_tb = 8'hAA; 30 | inp2_tb = 8'hBA; 31 | inp3_tb = 8'hBB; 32 | inp4_tb = 8'hCB; 33 | inp5_tb = 8'hCC; 34 | inp6_tb = 8'hDC; 35 | inp7_tb = 8'hDD; 36 | inp8_tb = 8'hFF; 37 | 38 | 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /lab4_2/main_schematic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab4_2/main_schematic.png -------------------------------------------------------------------------------- /lab4_2/question .png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab4_2/question .png -------------------------------------------------------------------------------- /lab4_2/rlt_schematic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab4_2/rlt_schematic.png -------------------------------------------------------------------------------- /lab5_1/Full Adder Circuit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab5_1/Full Adder Circuit.png -------------------------------------------------------------------------------- /lab5_1/full_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module full_adder(x,y,ci,s,co); 4 | 5 | input x,y,ci; 6 | output s,co; 7 | 8 | assign s = x ^ y ^ ci; 9 | assign co = (x & y) | (ci & (x ^ y)); 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /lab5_1/half_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module half_adder(x,y,s,co); 4 | input x,y; 5 | output s,co; 6 | 7 | assign s = x ^ y; 8 | assign co = x & y; 9 | 10 | endmodule 11 | 12 | -------------------------------------------------------------------------------- /lab5_1/module_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module module_adder(x,y,sum); 5 | 6 | input [2:0] x,y; 7 | output [3:0] sum; 8 | 9 | wire c1,c2,c3; 10 | 11 | full_adder islem1(x[0],y[0],0,sum[0],c1); 12 | full_adder islem2(x[1],y[1],c1,sum[1],c2); 13 | full_adder islem3(x[2],y[2],c2,sum[2],sum[3]); 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /lab5_1/module_adder_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module module_adder_tb(); 4 | 5 | reg [2:0] x,y; 6 | wire [3:0] sum; 7 | 8 | module_adder UUT(.x(x),.y(y),.sum(sum)); 9 | 10 | initial begin 11 | 12 | x = 3'b101; 13 | y = 3'b011; 14 | 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /lab5_1/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab5_1/question.png -------------------------------------------------------------------------------- /lab5_2/Full Adder Circuit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab5_2/Full Adder Circuit.png -------------------------------------------------------------------------------- /lab5_2/Half Adder Circuit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab5_2/Half Adder Circuit.png -------------------------------------------------------------------------------- /lab5_2/full_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module full_adder(x,y,ci,s,co); 4 | 5 | input x,y,ci; 6 | output s,co; 7 | 8 | assign s = x ^ y ^ ci; 9 | assign co = (x & y) | (ci & (x ^ y)); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /lab5_2/half_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module half_adder(x,y,s,co); 4 | input x,y; 5 | output s,co; 6 | 7 | assign s = x ^ y; 8 | assign co = x & y; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /lab5_2/module_adder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module module_adder(x,y,sum); 5 | 6 | input [3:0] x,y; 7 | output [4:0] sum; 8 | 9 | wire c1,c2,c3; 10 | 11 | half_adder islem1(x[0],y[0],sum[0],c1); 12 | full_adder islem2(x[1],y[1],c1,sum[1],c2); 13 | full_adder islem3(x[2],y[2],c2,sum[2],c3); 14 | full_adder islem4(x[3],y[3],c3,sum[3],sum[4]); 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /lab5_2/module_adder_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | 5 | module module_adder_tb(); 6 | 7 | reg [3:0] x,y; 8 | wire [4:0] sum; 9 | 10 | module_adder UUT(.x(x),.y(y),.sum(sum)); 11 | 12 | initial begin 13 | 14 | x = 4'b1010; 15 | y = 4'b1100; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /lab5_2/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab5_2/question.png -------------------------------------------------------------------------------- /lab6_1/comparator.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab6_1/comparator.png -------------------------------------------------------------------------------- /lab6_1/comparator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module comparator (x,y,z,out); 4 | 5 | input [7:0] x,y,z; 6 | output reg [7:0] out; 7 | 8 | initial begin 9 | out = 8'b0; 10 | end 11 | 12 | always @ (x,y,z) 13 | begin 14 | if ((x > y) & (x > z)) 15 | out = x; 16 | 17 | else if ((y > x) & (y > z)) 18 | out = y; 19 | 20 | else if ((z > x) & (z > y)) 21 | out = z; 22 | 23 | else 24 | out = 8'b0; 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /lab6_1/comparator_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module comparator_tb(); 4 | 5 | reg [7:0] x,y,z; 6 | wire [7:0] out; 7 | 8 | comparator UUT( 9 | .x(x), 10 | .y(y), 11 | .z(z), 12 | .out(out) 13 | ); 14 | 15 | initial begin 16 | x = 8'hA4; 17 | y = 8'h2C; 18 | z = 8'h6F; 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /lab6_1/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab6_1/question.png -------------------------------------------------------------------------------- /lab6_2/comparator.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab6_2/comparator.png -------------------------------------------------------------------------------- /lab6_2/comparator2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module comparator2(x,y,z,out); 5 | input [7:0] x,y,z; 6 | output reg [7:0] out; 7 | wire [7:0] x1,y1,z1; 8 | 9 | initial begin 10 | out = 8'h00; 11 | end 12 | 13 | assign x1 = ~(x - 8'b00000001); 14 | assign y1 = ~(y - 8'b00000001); 15 | assign z1 = ~(z - 8'b00000001); 16 | 17 | 18 | always @ (x,y,z) 19 | begin 20 | if ((x1 > y1) & (x1 > z1)) 21 | out = x; 22 | else if ((y1 > x1) & (y1 > z1)) 23 | out = y; 24 | else 25 | out = z; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /lab6_2/comparator2_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module comparator2_tb(); 5 | 6 | reg [7:0] x,y,z; 7 | wire [7:0] out; 8 | 9 | comparator2 UUT( 10 | .x(x), 11 | .y(y), 12 | .z(z), 13 | .out(out) 14 | ); 15 | 16 | initial begin 17 | x = 8'hA5; 18 | y = 8'hCF; 19 | z = 8'hF1; 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /lab6_2/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab6_2/question.png -------------------------------------------------------------------------------- /lab6_2/simulation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab6_2/simulation.png -------------------------------------------------------------------------------- /lab7/SR_Latch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab7/SR_Latch.png -------------------------------------------------------------------------------- /lab7/SR_latch.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module SR_latch(s,r,c,q,qn); 4 | 5 | input s,r,c; 6 | 7 | output reg q; 8 | output reg qn; 9 | 10 | always @ (s,r,c) 11 | 12 | if (c & s) 13 | {q,qn} <= 2'b10; 14 | 15 | else if (c & r) 16 | {q,qn} <= 2'b01; 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /lab7/SR_latch_control.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module SR_latch_control(s,r,c,q,qn); 4 | 5 | input c; 6 | input [3:0] s,r; 7 | 8 | output [3:0] q,qn; 9 | 10 | SR_latch islem1(s[0],r[0],c,q[0],qn[0]); 11 | SR_latch islem2(s[1],r[1],c,q[1],qn[1]); 12 | SR_latch islem3(s[2],r[2],c,q[2],qn[2]); 13 | SR_latch islem4(s[3],r[3],c,q[3],qn[3]); 14 | 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /lab7/SR_latch_control_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module SR_latch_control_tb(); 4 | 5 | reg [3:0] s,r; 6 | reg c; 7 | 8 | wire [3:0] q,qn; 9 | 10 | SR_latch_control uut( 11 | 12 | .s(s), 13 | .r(r), 14 | .c(c), 15 | .q(q), 16 | .qn(qn) 17 | ); 18 | 19 | initial begin 20 | 21 | c = 1'b0; 22 | s = 4'h0; 23 | r = 4'h0; 24 | #10; 25 | 26 | c = 1'b0; 27 | s = 4'hF; 28 | r = 4'h0; 29 | #10; 30 | 31 | c = 1'b1; 32 | s = 4'h0; 33 | r = 4'h0; 34 | #10; 35 | 36 | c = 1'b1; 37 | s = 4'hA; 38 | r = 4'h5; 39 | #10; 40 | 41 | c = 1'b1; 42 | s = 4'h0; 43 | r = 4'h0; 44 | #10; 45 | 46 | c = 1'b1; 47 | s = 4'hF; 48 | r = 4'hA; 49 | #10; 50 | 51 | c = 1'b1; 52 | s = 4'h0; 53 | r = 4'h5; 54 | #10; 55 | 56 | c = 1'b1; 57 | s = 4'h0; 58 | r = 4'h0; 59 | #10; 60 | 61 | end 62 | 63 | endmodule 64 | 65 | -------------------------------------------------------------------------------- /lab7/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab7/question.png -------------------------------------------------------------------------------- /lab8/frequency_divider.v: -------------------------------------------------------------------------------- 1 | module frequency_divider(clk ,out); 2 | 3 | input clk; 4 | output reg [1:0] out; 5 | 6 | initial out = 0; 7 | integer count1,count2; 8 | initial count1 = 0; 9 | initial count2 = 0; 10 | 11 | always @ (posedge clk) 12 | begin 13 | count1 = count1 + 1; 14 | count2 = count2 + 1; 15 | 16 | if (count1 == 4) // 6/2 + 1 , T = 120 17 | begin 18 | out[0] =~ out[0]; 19 | count1 = 1; 20 | end 21 | 22 | if (count2 == 6) // 10/2 + 1 , T = 200; 23 | begin 24 | out[1] =~ out[1]; 25 | count2 = 1; 26 | end 27 | 28 | end 29 | 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /lab8/frequency_divider_tb.v: -------------------------------------------------------------------------------- 1 | module frequency_divider_tb(); 2 | 3 | reg clk; 4 | wire[1:0] out; 5 | 6 | frequency_divider uut( 7 | .clk(clk), 8 | .out(out) 9 | ); 10 | 11 | initial begin 12 | clk = 0; 13 | 14 | forever 15 | #10 clk = ~clk; // T = 20 16 | end 17 | 18 | endmodule -------------------------------------------------------------------------------- /lab8/question.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/emrealci/FPGA-Verilog/c14d6d820bd8dcd95e1d996482bb44aa029b33b6/lab8/question.png --------------------------------------------------------------------------------