├── .github └── workflows │ └── ci.yml ├── .gitignore ├── CHANGES.md ├── CONTRIBUTORS ├── LICENSE ├── MANIFEST.in ├── README.md ├── doc ├── bios_screenshot.png ├── litex-hub.png ├── litex-hub.svg ├── litex.png ├── litex.svg └── socdoc.md ├── litex ├── __init__.py ├── build │ ├── __init__.py │ ├── altera │ │ ├── __init__.py │ │ ├── common.py │ │ ├── platform.py │ │ ├── programmer.py │ │ └── quartus.py │ ├── anlogic │ │ ├── __init__.py │ │ ├── anlogic.py │ │ ├── common.py │ │ ├── platform.py │ │ └── programmer.py │ ├── colognechip │ │ ├── __init__.py │ │ ├── colognechip.py │ │ ├── common.py │ │ ├── peppercorn.py │ │ └── platform.py │ ├── dfu.py │ ├── efinix │ │ ├── __init__.py │ │ ├── common.py │ │ ├── dbparser.py │ │ ├── efinity.py │ │ ├── ifacewriter.py │ │ ├── ipmwriter.py │ │ ├── platform.py │ │ └── programmer.py │ ├── generic_platform.py │ ├── generic_programmer.py │ ├── generic_toolchain.py │ ├── gowin │ │ ├── __init__.py │ │ ├── apicula.py │ │ ├── common.py │ │ ├── gowin.py │ │ ├── platform.py │ │ └── programmer.py │ ├── io.py │ ├── lattice │ │ ├── __init__.py │ │ ├── bit_to_svf.py │ │ ├── common.py │ │ ├── diamond.py │ │ ├── icestorm.py │ │ ├── oxide.py │ │ ├── platform.py │ │ ├── programmer.py │ │ ├── radiant.py │ │ └── trellis.py │ ├── microsemi │ │ ├── __init__.py │ │ ├── common.py │ │ ├── libero_soc.py │ │ └── platform.py │ ├── nextpnr_wrapper.py │ ├── openfpgaloader.py │ ├── openocd.py │ ├── parser.py │ ├── quicklogic │ │ ├── __init__.py │ │ ├── common.py │ │ ├── f4pga.py │ │ └── platform.py │ ├── sim │ │ ├── README │ │ ├── __init__.py │ │ ├── common.py │ │ ├── config.py │ │ ├── core │ │ │ ├── Makefile │ │ │ ├── error.h │ │ │ ├── libdylib.c │ │ │ ├── libdylib.h │ │ │ ├── modules.c │ │ │ ├── modules.h │ │ │ ├── modules │ │ │ │ ├── Makefile │ │ │ │ ├── clocker │ │ │ │ │ ├── Makefile │ │ │ │ │ └── clocker.c │ │ │ │ ├── ethernet │ │ │ │ │ ├── Makefile │ │ │ │ │ └── ethernet.c │ │ │ │ ├── gmii_ethernet │ │ │ │ │ ├── Makefile │ │ │ │ │ └── gmii_ethernet.c │ │ │ │ ├── jtagremote │ │ │ │ │ ├── Makefile │ │ │ │ │ └── jtagremote.c │ │ │ │ ├── rules.mak │ │ │ │ ├── serial2console │ │ │ │ │ ├── Makefile │ │ │ │ │ └── serial2console.c │ │ │ │ ├── serial2tcp │ │ │ │ │ ├── Makefile │ │ │ │ │ └── serial2tcp.c │ │ │ │ ├── spdeeprom │ │ │ │ │ ├── Makefile │ │ │ │ │ └── spdeeprom.c │ │ │ │ ├── video │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── sim_fb.c │ │ │ │ │ ├── sim_fb.h │ │ │ │ │ └── video.c │ │ │ │ └── xgmii_ethernet │ │ │ │ │ ├── Makefile │ │ │ │ │ └── xgmii_ethernet.c │ │ │ ├── pads.c │ │ │ ├── pads.h │ │ │ ├── parse.c │ │ │ ├── sim.c │ │ │ ├── tinydir.h │ │ │ ├── veril.cpp │ │ │ └── veril.h │ │ ├── gtkwave.py │ │ ├── platform.py │ │ ├── verilator.py │ │ └── verilog │ │ │ ├── iddr_verilog.v │ │ │ └── oddr_verilog.v │ ├── tools.py │ ├── vhd2v_converter.py │ ├── xilinx │ │ ├── __init__.py │ │ ├── common.py │ │ ├── f4pga.py │ │ ├── ise.py │ │ ├── platform.py │ │ ├── programmer.py │ │ ├── vivado.py │ │ └── yosys_nextpnr.py │ ├── yosys_nextpnr_toolchain.py │ └── yosys_wrapper.py ├── compat │ ├── __init__.py │ ├── soc_core.py │ └── stream_sim.py ├── gen │ ├── __init__.py │ ├── common.py │ ├── context.py │ ├── fhdl │ │ ├── __init__.py │ │ ├── expression.py │ │ ├── hierarchy.py │ │ ├── instance.py │ │ ├── memory.py │ │ ├── module.py │ │ ├── namer.py │ │ └── verilog.py │ ├── genlib │ │ ├── __init__.py │ │ ├── cdc.py │ │ └── misc.py │ ├── reduce.py │ ├── signal.py │ └── sim │ │ ├── __init__.py │ │ ├── core.py │ │ └── vcd.py ├── soc │ ├── __init__.py │ ├── cores │ │ ├── __init__.py │ │ ├── bitbang.py │ │ ├── can │ │ │ ├── __init__.py │ │ │ ├── ctu_can_fd.py │ │ │ └── rtl_lst.txt │ │ ├── clock │ │ │ ├── __init__.py │ │ │ ├── colognechip.py │ │ │ ├── common.py │ │ │ ├── efinix.py │ │ │ ├── gowin_gw1n.py │ │ │ ├── gowin_gw2a.py │ │ │ ├── gowin_gw5a.py │ │ │ ├── intel_common.py │ │ │ ├── intel_cyclone10.py │ │ │ ├── intel_cyclone4.py │ │ │ ├── intel_cyclone5.py │ │ │ ├── intel_max10.py │ │ │ ├── intel_stratix5.py │ │ │ ├── lattice_ecp5.py │ │ │ ├── lattice_ice40.py │ │ │ ├── lattice_nx.py │ │ │ ├── xilinx_common.py │ │ │ ├── xilinx_s6.py │ │ │ ├── xilinx_s7.py │ │ │ ├── xilinx_us.py │ │ │ └── xilinx_usp.py │ │ ├── code_8b10b.py │ │ ├── code_tmds.py │ │ ├── cpu │ │ │ ├── __init__.py │ │ │ ├── blackparrot │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── coreblocks │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── cortex_m1 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.c │ │ │ │ ├── core.py │ │ │ │ ├── crt0.c │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── cortex_m3 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.c │ │ │ │ ├── core.py │ │ │ │ ├── crt0.c │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── cv32e40p │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── cv32e41p │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── cva5 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── cva6 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── cva6_wrapper │ │ │ │ │ ├── Flist.cva6_wrapper │ │ │ │ │ ├── ariane_pkg.sv │ │ │ │ │ ├── cva6_defines.sv │ │ │ │ │ ├── cva6_wrapper.sv │ │ │ │ │ └── cva6_wrapper_pkg.sv │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── eos_s3 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.c │ │ │ │ ├── core.py │ │ │ │ ├── crt0.c │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── fazyrv │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── femtorv │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── firev │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── gowin_ae350 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── gowin_emcu │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.c │ │ │ │ ├── core.py │ │ │ │ ├── crt0.c │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── ibex │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── kianv │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── lm32 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ ├── system.h │ │ │ │ └── verilog │ │ │ │ │ ├── config │ │ │ │ │ └── lm32_config.v │ │ │ │ │ ├── config_lite │ │ │ │ │ └── lm32_config.v │ │ │ │ │ └── config_minimal │ │ │ │ │ └── lm32_config.v │ │ │ ├── marocchino │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ ├── spr-defs.h │ │ │ │ └── system.h │ │ │ ├── microwatt │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ ├── microwatt_wrapper.vhdl │ │ │ │ ├── system.h │ │ │ │ └── xics_wrapper.vhdl │ │ │ ├── minerva │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ ├── minerva-pep-723.py │ │ │ │ └── system.h │ │ │ ├── mor1kx │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ ├── spr-defs.h │ │ │ │ └── system.h │ │ │ ├── naxriscv │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── neorv32 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── openc906 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── picorv32 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── extraops.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── rocket │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── sentinel │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ ├── sentinel-pep-723.py │ │ │ │ └── system.h │ │ │ ├── serv │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── urv │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── vexiiriscv │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── vexriscv │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── vexriscv_smp │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.S │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── csr-defs.h │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ ├── zynq7000 │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.c │ │ │ │ ├── core.py │ │ │ │ ├── crt0.S │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ │ └── zynqmp │ │ │ │ ├── __init__.py │ │ │ │ ├── boot-helper.c │ │ │ │ ├── core.py │ │ │ │ ├── crt0.c │ │ │ │ ├── irq.h │ │ │ │ └── system.h │ │ ├── dma.py │ │ ├── dna.py │ │ ├── ecc.py │ │ ├── emif.py │ │ ├── esc.py │ │ ├── freqmeter.py │ │ ├── gpio.py │ │ ├── hyperbus.py │ │ ├── i2c.py │ │ ├── i2s.py │ │ ├── icap.py │ │ ├── identifier.py │ │ ├── jtag.py │ │ ├── led.py │ │ ├── prbs.py │ │ ├── pwm.py │ │ ├── ram │ │ │ ├── __init__.py │ │ │ ├── efinix_hyperram.py │ │ │ ├── lattice_ice40.py │ │ │ ├── lattice_nx.py │ │ │ ├── xilinx_fifo_sync_macro.py │ │ │ └── xilinx_usp_hbm2.py │ │ ├── spi │ │ │ ├── __init__.py │ │ │ ├── spi_bone.py │ │ │ ├── spi_master.py │ │ │ ├── spi_mmap.py │ │ │ └── spi_slave.py │ │ ├── spi_flash.py │ │ ├── spi_opi.py │ │ ├── timer.py │ │ ├── uart.py │ │ ├── usb_fifo.py │ │ ├── usb_ohci.py │ │ ├── video.py │ │ ├── watchdog.py │ │ └── xadc.py │ ├── doc │ │ ├── __init__.py │ │ ├── csr.py │ │ ├── module.py │ │ ├── rst.py │ │ └── static │ │ │ ├── WaveDrom.js │ │ │ └── default.js │ ├── integration │ │ ├── __init__.py │ │ ├── builder.py │ │ ├── common.py │ │ ├── doc.py │ │ ├── export.py │ │ ├── soc.py │ │ └── soc_core.py │ ├── interconnect │ │ ├── __init__.py │ │ ├── ahb.py │ │ ├── avalon │ │ │ ├── __init__.py │ │ │ ├── avalon_mm.py │ │ │ ├── avalon_mm_to_wishbone.py │ │ │ └── avalon_st.py │ │ ├── axi │ │ │ ├── __init__.py │ │ │ ├── axi_common.py │ │ │ ├── axi_full.py │ │ │ ├── axi_full_to_axi_lite.py │ │ │ ├── axi_full_to_wishbone.py │ │ │ ├── axi_lite.py │ │ │ ├── axi_lite_to_csr.py │ │ │ ├── axi_lite_to_wishbone.py │ │ │ └── axi_stream.py │ │ ├── csr.py │ │ ├── csr_bus.py │ │ ├── csr_eventmanager.py │ │ ├── packet.py │ │ ├── stream.py │ │ └── wishbone.py │ └── software │ │ ├── bios │ │ ├── Makefile │ │ ├── boot.c │ │ ├── boot.h │ │ ├── cmds │ │ │ ├── cmd_bios.c │ │ │ ├── cmd_boot.c │ │ │ ├── cmd_i2c.c │ │ │ ├── cmd_litedram.c │ │ │ ├── cmd_liteeth.c │ │ │ ├── cmd_litesata.c │ │ │ ├── cmd_litesdcard.c │ │ │ ├── cmd_mem.c │ │ │ └── cmd_spiflash.c │ │ ├── command.h │ │ ├── complete.c │ │ ├── complete.h │ │ ├── helpers.c │ │ ├── helpers.h │ │ ├── init.h │ │ ├── linker-zynq.ld │ │ ├── linker-zynqmp.ld │ │ ├── linker.ld │ │ ├── main.c │ │ ├── readline.c │ │ ├── readline.h │ │ ├── readline_simple.c │ │ ├── sfl.h │ │ ├── sim_debug.c │ │ └── sim_debug.h │ │ ├── common.mak │ │ ├── crcfbigen.py │ │ ├── demo │ │ ├── Makefile │ │ ├── README.md │ │ ├── __init__.py │ │ ├── demo.py │ │ ├── donut.c │ │ ├── helloc.c │ │ ├── hellocpp.cpp │ │ ├── linker.ld │ │ └── main.c │ │ ├── include │ │ ├── hw │ │ │ └── common.h │ │ └── irq.h │ │ ├── libbase │ │ ├── Makefile │ │ ├── console.c │ │ ├── console.h │ │ ├── crc.h │ │ ├── crc16.c │ │ ├── crc32.c │ │ ├── hyperram.c │ │ ├── hyperram.h │ │ ├── i2c.c │ │ ├── i2c.h │ │ ├── isr.c │ │ ├── jsmn.h │ │ ├── lfsr.h │ │ ├── memtest.c │ │ ├── memtest.h │ │ ├── progress.c │ │ ├── progress.h │ │ ├── spiflash.c │ │ ├── spiflash.h │ │ ├── system.c │ │ ├── uart.c │ │ └── uart.h │ │ ├── libc │ │ ├── Makefile │ │ ├── arm │ │ │ └── meson.build │ │ ├── lm32 │ │ │ └── meson.build │ │ ├── missing.c │ │ ├── or1k │ │ │ ├── exception.c │ │ │ └── meson.build │ │ └── stdio.c │ │ ├── libcompiler_rt │ │ ├── Makefile │ │ └── mulsi3.c │ │ ├── libfatfs │ │ ├── Makefile │ │ ├── diskio.h │ │ ├── ff.c │ │ ├── ff.h │ │ ├── ffconf.h │ │ └── ffunicode.c │ │ ├── liblitedram │ │ ├── Makefile │ │ ├── accessors.c │ │ ├── accessors.h │ │ ├── bist.c │ │ ├── bist.h │ │ ├── sdram.c │ │ ├── sdram.h │ │ ├── sdram_dbg.c │ │ ├── sdram_dbg.h │ │ ├── sdram_spd.c │ │ ├── sdram_spd.h │ │ ├── utils.c │ │ └── utils.h │ │ ├── libliteeth │ │ ├── Makefile │ │ ├── inet.h │ │ ├── mdio.c │ │ ├── mdio.h │ │ ├── tftp.c │ │ ├── tftp.h │ │ ├── udp.c │ │ └── udp.h │ │ ├── liblitesata │ │ ├── Makefile │ │ ├── sata.c │ │ └── sata.h │ │ ├── liblitesdcard │ │ ├── Makefile │ │ ├── sdcard.c │ │ ├── sdcard.h │ │ ├── spisdcard.c │ │ └── spisdcard.h │ │ ├── liblitespi │ │ ├── Makefile │ │ ├── spiflash.c │ │ ├── spiflash.h │ │ ├── spiram.c │ │ └── spiram.h │ │ ├── libxil │ │ └── Makefile │ │ └── memusage.py └── tools │ ├── __init__.py │ ├── litex_client.py │ ├── litex_contributors.py │ ├── litex_json2dts_linux.py │ ├── litex_json2dts_zephyr.py │ ├── litex_json2renode.py │ ├── litex_periph_gen.py │ ├── litex_read_verilog.py │ ├── litex_server.py │ ├── litex_sim.py │ ├── litex_soc_gen.py │ ├── litex_term.py │ └── remote │ ├── __init__.py │ ├── comm_pcie.py │ ├── comm_uart.py │ ├── comm_udp.py │ ├── comm_usb.py │ ├── csr_builder.py │ └── etherbone.py ├── litex_setup.py ├── setup.py └── test ├── __init__.py ├── test_avalon_mm.py ├── test_axi.py ├── test_axi_lite.py ├── test_axi_stream.py ├── test_bitbang.py ├── test_clock.py ├── test_code_8b10b.py ├── test_csr.py ├── test_ecc.py ├── test_emif.py ├── test_fifosyncmacro.py ├── test_gearbox.py ├── test_hyperbus.py ├── test_i2c.py ├── test_i2s.py ├── test_icap.py ├── test_integration.py ├── test_led.py ├── test_packet.py ├── test_prbs.py ├── test_reduce.py ├── test_spi.py ├── test_spi_mmap.py ├── test_spi_opi.py ├── test_stream.py ├── test_timer.py └── test_wishbone.py /.gitignore: -------------------------------------------------------------------------------- 1 | # Byte-compiled / optimized / DLL files 2 | __pycache__/ 3 | *.py[cod] 4 | *$py.class 5 | 6 | # Tilde files 7 | *~ 8 | 9 | # C extensions 10 | *.so 11 | 12 | # Distribution / packaging 13 | .Python 14 | env/ 15 | build/ 16 | !litex/build 17 | develop-eggs/ 18 | dist/ 19 | downloads/ 20 | eggs/ 21 | .eggs/ 22 | lib/ 23 | lib64/ 24 | parts/ 25 | sdist/ 26 | var/ 27 | *.egg-info/ 28 | .installed.cfg 29 | *.egg 30 | 31 | # PyInstaller 32 | # Usually these files are written by a python script from a template 33 | # before PyInstaller builds the exe, so as to inject date/other infos into it. 34 | *.manifest 35 | *.spec 36 | 37 | # Installer logs 38 | pip-log.txt 39 | pip-delete-this-directory.txt 40 | 41 | # Unit test / coverage reports 42 | htmlcov/ 43 | .tox/ 44 | .coverage 45 | .coverage.* 46 | .cache 47 | nosetests.xml 48 | coverage.xml 49 | *,cover 50 | .hypothesis/ 51 | 52 | # Translations 53 | *.mo 54 | *.pot 55 | 56 | # Django stuff: 57 | *.log 58 | local_settings.py 59 | 60 | # Flask stuff: 61 | instance/ 62 | .webassets-cache 63 | 64 | # Scrapy stuff: 65 | .scrapy 66 | 67 | # Sphinx documentation 68 | docs/_build/ 69 | 70 | # PyBuilder 71 | target/ 72 | 73 | # IPython Notebook 74 | .ipynb_checkpoints 75 | 76 | # pyenv 77 | .python-version 78 | 79 | # celery beat schedule file 80 | celerybeat-schedule 81 | 82 | # dotenv 83 | .env 84 | 85 | # virtualenv 86 | venv/ 87 | ENV/ 88 | 89 | # Spyder project settings 90 | .spyderproject 91 | 92 | # Rope project settings 93 | .ropeproject 94 | 95 | # VS Code settings 96 | .vscode 97 | -------------------------------------------------------------------------------- /MANIFEST.in: -------------------------------------------------------------------------------- 1 | graft litex 2 | include CHANGES.md 3 | include CONTRIBUTORS 4 | graft doc 5 | 6 | exclude litex_setup.py 7 | 8 | prune test 9 | 10 | -------------------------------------------------------------------------------- /doc/bios_screenshot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/doc/bios_screenshot.png -------------------------------------------------------------------------------- /doc/litex-hub.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/doc/litex-hub.png -------------------------------------------------------------------------------- /doc/litex.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/doc/litex.png -------------------------------------------------------------------------------- /litex/__init__.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | from litex.tools.litex_client import RemoteClient 4 | 5 | # Python-Data Import Helper ------------------------------------------------------------------------ 6 | 7 | def get_data_mod(data_type, data_name): 8 | """Get the pythondata-{}-{} module or raise a useful error message.""" 9 | imp = "import pythondata_{}_{} as dm".format(data_type, data_name) 10 | try: 11 | l = {} 12 | exec(imp, {}, l) 13 | dm = l['dm'] 14 | return dm 15 | except ImportError as e: 16 | raise ImportError("""\ 17 | pythondata-{dt}-{dn} module not installed! Unable to use {dn} {dt}. 18 | {e} 19 | 20 | You can install this by running; 21 | pip3 install git+https://github.com/litex-hub/pythondata-{dt}-{dn}.git 22 | """.format(dt=data_type, dn=data_name, e=e)) from None 23 | -------------------------------------------------------------------------------- /litex/build/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/build/__init__.py -------------------------------------------------------------------------------- /litex/build/altera/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.build.altera.platform import AlteraPlatform 2 | from litex.build.altera.programmer import USBBlaster 3 | -------------------------------------------------------------------------------- /litex/build/altera/programmer.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2015-2018 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from litex.build.generic_programmer import GenericProgrammer 8 | 9 | # USBBlaster --------------------------------------------------------------------------------------- 10 | 11 | class USBBlaster(GenericProgrammer): 12 | needs_bitreverse = False 13 | 14 | def __init__(self, cable_name="USB-Blaster", device_id=1): 15 | self.cable_name = cable_name 16 | self.device_id = device_id 17 | 18 | def load_bitstream(self, bitstream_file, cable_suffix=""): 19 | self.call(["quartus_pgm", 20 | "-m", "jtag", 21 | "-c", "{}{}".format(self.cable_name, cable_suffix), 22 | "-o", "p;{}@{}".format(bitstream_file, self.device_id) 23 | ]) 24 | -------------------------------------------------------------------------------- /litex/build/anlogic/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/build/anlogic/__init__.py -------------------------------------------------------------------------------- /litex/build/anlogic/common.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2021 Miodrag Milanovic 5 | # Copyright (c) 2015-2021 Florent Kermarrec 6 | # SPDX-License-Identifier: BSD-2-Clause 7 | 8 | from migen.fhdl.module import Module 9 | from migen.genlib.resetsync import AsyncResetSynchronizer 10 | 11 | from litex.build.io import * 12 | 13 | # Anlogic AsyncResetSynchronizer ------------------------------------------------------------------- 14 | 15 | class AnlogicAsyncResetSynchronizerImpl(Module): 16 | def __init__(self, cd, async_reset): 17 | rst1 = Signal() 18 | self.specials += [ 19 | Instance("AL_MAP_SEQ", 20 | p_DFFMODE = "FF", 21 | p_REGSET = "SET", 22 | p_SRMUX = "SR", 23 | p_SRMODE = "ASYNC", 24 | i_ce = 1, 25 | i_d = 0, 26 | i_sr = async_reset, 27 | i_clk = cd.clk, 28 | o_q = rst1 29 | ), 30 | Instance("AL_MAP_SEQ", 31 | p_DFFMODE = "FF", 32 | p_REGSET = "SET", 33 | p_SRMUX = "SR", 34 | p_SRMODE = "ASYNC", 35 | i_ce = 1, 36 | i_d = rst1, 37 | i_sr = async_reset, 38 | i_clk = cd.clk, 39 | o_q = cd.rst 40 | ) 41 | ] 42 | 43 | class AnlogicAsyncResetSynchronizer: 44 | @staticmethod 45 | def lower(dr): 46 | return AnlogicAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) 47 | 48 | # Anlogic Special Overrides ------------------------------------------------------------------------ 49 | 50 | anlogic_special_overrides = { 51 | AsyncResetSynchronizer: AnlogicAsyncResetSynchronizer, 52 | } 53 | -------------------------------------------------------------------------------- /litex/build/anlogic/platform.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2021 Miodrag Milanovic 5 | # Copyright (c) 2015-2021 Florent Kermarrec 6 | # SPDX-License-Identifier: BSD-2-Clause 7 | 8 | import os 9 | 10 | from litex.build.generic_platform import GenericPlatform 11 | from litex.build.anlogic import common, anlogic 12 | 13 | # AnlogicPlatform ---------------------------------------------------------------------------------- 14 | 15 | class AnlogicPlatform(GenericPlatform): 16 | _bitstream_ext = ".bit" 17 | _jtag_support = False 18 | 19 | _supported_toolchains = ["td"] 20 | 21 | def __init__(self, device, *args, toolchain="td", **kwargs): 22 | GenericPlatform.__init__(self, device, *args, **kwargs) 23 | if toolchain == "td": 24 | self.toolchain = anlogic.TangDynastyToolchain() 25 | else: 26 | raise ValueError(f"Unknown toolchain {toolchain}") 27 | 28 | def get_verilog(self, *args, special_overrides=dict(), **kwargs): 29 | so = dict(common.anlogic_special_overrides) 30 | so.update(special_overrides) 31 | return GenericPlatform.get_verilog(self, *args, 32 | special_overrides = so, 33 | attr_translate = self.toolchain.attr_translate, 34 | **kwargs 35 | ) 36 | 37 | def build(self, *args, **kwargs): 38 | return self.toolchain.build(self, *args, **kwargs) 39 | -------------------------------------------------------------------------------- /litex/build/anlogic/programmer.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2015-2025 Florent Kermarrec 5 | # Copyright (c) 2025 Junhui Liu 6 | # SPDX-License-Identifier: BSD-2-Clause 7 | 8 | import subprocess 9 | from shutil import which 10 | 11 | from litex.build.generic_programmer import GenericProgrammer 12 | 13 | def _run_td(cmds): 14 | if which("td") is None: 15 | msg = "Unable to find Tang Dinasty toolchain, please:\n" 16 | msg += "- Add Tang Dinasty toolchain to your $PATH." 17 | raise OSError(msg) 18 | 19 | with subprocess.Popen("td", stdin=subprocess.PIPE, shell=True) as process: 20 | process.stdin.write(cmds.encode("ASCII")) 21 | process.communicate() 22 | 23 | class TangDynastyProgrammer(GenericProgrammer): 24 | def __init__(self): 25 | GenericProgrammer.__init__(self) 26 | 27 | def load_bitstream(self, bitstream_file): 28 | cmds = """download -bit {bitstream} -mode jtag -spd 7 -sec 64 -cable 0 29 | exit 30 | """.format(bitstream=bitstream_file) 31 | _run_td(cmds) 32 | -------------------------------------------------------------------------------- /litex/build/colognechip/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.build.colognechip.platform import CologneChipPlatform 2 | -------------------------------------------------------------------------------- /litex/build/dfu.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2020 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | import subprocess 8 | 9 | from litex.build.tools import write_to_file 10 | from litex.build.generic_programmer import GenericProgrammer 11 | 12 | # DFUProg ------------------------------------------------------------------------------------------ 13 | 14 | class DFUProg(GenericProgrammer): 15 | needs_bitreverse = False 16 | 17 | def __init__(self, vid, pid, alt=None): 18 | self.vid = vid 19 | self.pid = pid 20 | self.alt = alt 21 | 22 | def load_bitstream(self, bitstream_file, reset=True): 23 | subprocess.call(["cp", bitstream_file, bitstream_file + ".dfu"]) 24 | subprocess.call(["dfu-suffix", "-v", self.vid, "-p", self.pid, "-a", bitstream_file + ".dfu"]) 25 | 26 | flash_cmd = ["dfu-util", "--download", bitstream_file + ".dfu"] 27 | if reset: 28 | flash_cmd.append("-R") 29 | if self.alt is not None: 30 | flash_cmd.extend(["-a", str(self.alt)]) 31 | subprocess.call(flash_cmd) 32 | -------------------------------------------------------------------------------- /litex/build/efinix/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.build.efinix.programmer import EfinixProgrammer 2 | from litex.build.efinix.dbparser import EfinixDbParser 3 | from litex.build.efinix.ifacewriter import InterfaceWriter, InterfaceWriterBlock, InterfaceWriterXMLBlock 4 | from litex.build.efinix.ipmwriter import IPMWriter, IPMWriterBlock, IPMWriterXMLBlock 5 | from litex.build.efinix.platform import EfinixPlatform -------------------------------------------------------------------------------- /litex/build/gowin/__init__.py: -------------------------------------------------------------------------------- 1 | # Platforms. 2 | from litex.build.gowin.platform import GowinPlatform 3 | 4 | # Programmers. 5 | from litex.build.gowin.programmer import GowinProgrammer 6 | -------------------------------------------------------------------------------- /litex/build/lattice/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.build.lattice.platform import LatticePlatform, LatticeiCE40Platform, LatticeECP5Platform, LatticeNexusPlatform 2 | from litex.build.lattice.programmer import LatticeProgrammer 3 | -------------------------------------------------------------------------------- /litex/build/microsemi/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.build.microsemi.platform import MicrosemiPlatform 2 | -------------------------------------------------------------------------------- /litex/build/microsemi/common.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2018-2019 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | from migen.genlib.resetsync import AsyncResetSynchronizer 9 | 10 | # AsyncResetSynchronizer --------------------------------------------------------------------------- 11 | 12 | class MicrosemiPolarfireAsyncResetSynchronizerImpl(Module): 13 | def __init__(self, cd, async_reset): 14 | rst1 = Signal() 15 | self.specials += [ 16 | Instance("DFN1P0", 17 | i_CLK = cd.clk, 18 | i_PRE = ~async_reset, 19 | i_D = 0, 20 | o_Q = rst1 21 | ), 22 | Instance("DFN1P0", 23 | i_CLK = cd.clk, 24 | i_PRE = ~async_reset, 25 | i_D = rst1, 26 | o_Q = cd.rst 27 | ) 28 | ] 29 | 30 | 31 | class MicrosemiPolarfireAsyncResetSynchronizer: 32 | @staticmethod 33 | def lower(dr): 34 | return MicrosemiPolarfireAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) 35 | 36 | # Special Overrides -------------------------------------------------------------------------------- 37 | 38 | microsemi_polarfire_special_overrides = { 39 | AsyncResetSynchronizer: MicrosemiPolarfireAsyncResetSynchronizer, 40 | } 41 | -------------------------------------------------------------------------------- /litex/build/microsemi/platform.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2018-2019 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from litex.build.generic_platform import GenericPlatform 8 | from litex.build.microsemi import common, libero_soc 9 | 10 | # MicrosemiPlatform -------------------------------------------------------------------------------- 11 | 12 | class MicrosemiPlatform(GenericPlatform): 13 | _bitstream_ext = ".bit" 14 | _jtag_support = False 15 | 16 | _supported_toolchains = ["libero_soc_polarfire"] 17 | 18 | def __init__(self, *args, toolchain="libero_soc_polarfire", **kwargs): 19 | GenericPlatform.__init__(self, *args, **kwargs) 20 | if toolchain == "libero_soc_polarfire": 21 | self.toolchain = libero_soc.MicrosemiLiberoSoCPolarfireToolchain() 22 | else: 23 | raise ValueError(f"Unknown toolchain {toolchain}") 24 | 25 | def get_verilog(self, *args, special_overrides=dict(), **kwargs): 26 | so = dict() 27 | so.update(self.toolchain.special_overrides) 28 | so.update(special_overrides) 29 | return GenericPlatform.get_verilog(self, *args, 30 | special_overrides = so, 31 | attr_translate = self.toolchain.attr_translate, 32 | **kwargs 33 | ) 34 | 35 | def build(self, *args, **kwargs): 36 | return self.toolchain.build(self, *args, **kwargs) 37 | 38 | def add_false_path_constraint(self, from_, to): 39 | if hasattr(from_, "p"): 40 | from_ = from_.p 41 | if hasattr(to, "p"): 42 | to = to.p 43 | from_.attr.add("keep") 44 | to.attr.add("keep") 45 | self.toolchain.add_false_path_constraint(self, from_, to) 46 | -------------------------------------------------------------------------------- /litex/build/quicklogic/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.build.quicklogic.platform import QuickLogicPlatform 2 | -------------------------------------------------------------------------------- /litex/build/quicklogic/common.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2021 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | # QuickLogic Special Overrides --------------------------------------------------------------------- 8 | 9 | quicklogic_special_overrides = {} 10 | -------------------------------------------------------------------------------- /litex/build/quicklogic/platform.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2021 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | import os 8 | 9 | from litex.build.generic_platform import GenericPlatform 10 | from litex.build.quicklogic import common, f4pga 11 | 12 | # QuickLogicPlatform ------------------------------------------------------------------------------- 13 | 14 | class QuickLogicPlatform(GenericPlatform): 15 | _bitstream_ext = ".bit" 16 | _jtag_support = False 17 | 18 | _supported_toolchains = ["f4pga"] 19 | 20 | def __init__(self, *args, toolchain="f4pga", **kwargs): 21 | GenericPlatform.__init__(self, *args, **kwargs) 22 | if isinstance(toolchain, str): 23 | if toolchain == "symbiflow" or toolchain == "f4pga": 24 | self.toolchain = f4pga.F4PGAToolchain() 25 | else: 26 | raise ValueError(f"Unknown toolchain {toolchain}") 27 | else: 28 | self.toolchain = toolchain 29 | 30 | def get_verilog(self, *args, special_overrides=dict(), **kwargs): 31 | so = dict(common.quicklogic_special_overrides) 32 | so.update(special_overrides) 33 | return GenericPlatform.get_verilog(self, *args, 34 | special_overrides = so, 35 | attr_translate = self.toolchain.attr_translate, 36 | **kwargs) 37 | 38 | def build(self, *args, **kwargs): 39 | return self.toolchain.build(self, *args, **kwargs) 40 | -------------------------------------------------------------------------------- /litex/build/sim/README: -------------------------------------------------------------------------------- 1 | LiteX Sim is a contribution from LambdaConcept and provides 2 | a modular SoC simulation environment. 3 | 4 | The contribution from LambdaConcept is a major rework/refactoring 5 | of the original simulation environnment PoC that was hacky and not 6 | modular. 7 | 8 | LiteX Sim is Copyright (c) 2017 Pierre-Olivier Vauboin 9 | 2017 Ramtin Amin 10 | 11 | Original PoC is Copyright (c) 2015-2016 Florent Kermarrec -------------------------------------------------------------------------------- /litex/build/sim/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.build.sim.platform import SimPlatform 2 | -------------------------------------------------------------------------------- /litex/build/sim/core/error.h: -------------------------------------------------------------------------------- 1 | /* Copyright (C) 2017 LambdaConcept */ 2 | 3 | #ifndef __ERROR_H_ 4 | #define __ERROR_H_ 5 | 6 | #define RC_OK 0 7 | #define RC_ERROR -1 8 | #define RC_INVARG -2 9 | #define RC_NOENMEM -3 10 | #define RC_JSERROR -4 11 | 12 | #define eprintf(format, ...) fprintf (stderr, "%s:%d "format, __FILE__, __LINE__, ##__VA_ARGS__) 13 | 14 | #endif 15 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/Makefile: -------------------------------------------------------------------------------- 1 | include ../variables.mak 2 | MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker spdeeprom gmii_ethernet jtagremote $(if $(VIDEO), video) 3 | 4 | .PHONY: $(MODULES) $(EXTRA_MOD_LIST) 5 | all: $(MODULES) $(EXTRA_MOD_LIST) 6 | 7 | $(MODULES): %: 8 | mkdir -p $@ 9 | $(MAKE) MOD=$@ -C $@ -f $(SRC_DIR)/modules/$@/Makefile 10 | cp $@/$@.so $@.so 11 | 12 | $(EXTRA_MOD_LIST): %: 13 | mkdir -p $@ 14 | $(MAKE) MOD=$@ -C $@ -f $(EXTRA_MOD_BASE_DIR)/$@/Makefile 15 | cp $@/$@.so $@.so 16 | 17 | .PHONY: clean 18 | clean: 19 | for module in $(MODULES); do \ 20 | $(MAKE) -C $$module $@; \ 21 | done 22 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/clocker/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | include $(SRC_DIR)/modules/rules.mak 3 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/ethernet/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | UNAME_S := $(shell uname -s) 3 | 4 | include $(SRC_DIR)/modules/rules.mak 5 | 6 | CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include 7 | OBJS = $(MOD).o tapcfg.o taplog.o 8 | 9 | $(MOD).so: $(OBJS) 10 | ifeq ($(UNAME_S),Darwin) 11 | $(CC) $(LDFLAGS) -o $@ $^ 12 | else 13 | $(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^ 14 | endif 15 | 16 | tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c 17 | $(CC) $(CFLAGS) -c -o $@ $< 18 | 19 | taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c 20 | $(CC) $(CFLAGS) -c -o $@ $< 21 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/gmii_ethernet/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | UNAME_S := $(shell uname -s) 3 | 4 | include $(SRC_DIR)/modules/rules.mak 5 | 6 | CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include 7 | LDFLAGS += -lz 8 | OBJS = $(MOD).o tapcfg.o taplog.o 9 | 10 | $(MOD).so: $(OBJS) 11 | ifeq ($(UNAME_S),Darwin) 12 | $(CC) $(LDFLAGS) -o $@ $^ 13 | else 14 | $(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^ 15 | endif 16 | 17 | tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c 18 | $(CC) $(CFLAGS) -c -o $@ $< 19 | 20 | taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c 21 | $(CC) $(CFLAGS) -c -o $@ $< 22 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/jtagremote/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | include $(SRC_DIR)/modules/rules.mak 3 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/rules.mak: -------------------------------------------------------------------------------- 1 | CC ?= gcc 2 | UNAME_S := $(shell uname -s) 3 | UNAME_M := $(shell uname -m) 4 | 5 | ifeq ($(UNAME_S),Darwin) 6 | ifeq ($(UNAME_M),x86_64) 7 | CFLAGS += -I/usr/local/include 8 | LDFLAGS += -L/usr/local/lib 9 | else 10 | CFLAGS += -I/opt/homebrew/include 11 | LDFLAGS += -L/opt/homebrew/lib 12 | endif 13 | LDFLAGS += -ljson-c 14 | CFLAGS += -Wall -O3 -ggdb -fPIC 15 | else 16 | CFLAGS += -Wall -O3 -ggdb -fPIC -Werror 17 | endif 18 | LDFLAGS += -levent -shared -fPIC 19 | 20 | MOD_SRC_DIR=$(SRC_DIR)/modules/$(MOD) 21 | EXTRA_MOD_SRC_DIR=$(EXTRA_MOD_BASE_DIR)/$(MOD) 22 | 23 | all: $(MOD).so 24 | 25 | %.o: $(MOD_SRC_DIR)/%.c 26 | $(CC) -c $(CFLAGS) -I$(MOD_SRC_DIR)/../.. -o $@ $< 27 | 28 | %.o: $(EXTRA_MOD_SRC_DIR)/%.c 29 | $(CC) -c $(CFLAGS) -I$(SRC_DIR) -o $@ $< 30 | 31 | %.so: %.o 32 | ifeq ($(UNAME_S),Darwin) 33 | $(CC) $(LDFLAGS) -o $@ $^ 34 | else 35 | $(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $< 36 | endif 37 | 38 | .PHONY: clean 39 | clean: 40 | rm -f *.o *.so 41 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/serial2console/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | include $(SRC_DIR)/modules/rules.mak 3 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/serial2tcp/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | include $(SRC_DIR)/modules/rules.mak 3 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/spdeeprom/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | include $(SRC_DIR)/modules/rules.mak 3 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/video/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | include $(SRC_DIR)/modules/rules.mak 3 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/video/sim_fb.h: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022 Victor Suarez Rovere 2 | 3 | #ifndef __SIM_FB_H__ 4 | #define __SIM_FB_H__ 5 | 6 | struct SDL_Window; 7 | struct SDL_Renderer; 8 | struct SDL_Texture; 9 | 10 | typedef struct 11 | { 12 | SDL_Window* win; 13 | SDL_Renderer* renderer; 14 | SDL_Texture* texture; 15 | } fb_handle_t; 16 | 17 | bool fb_init(unsigned width, unsigned height, bool vsync, fb_handle_t *handle); 18 | void fb_update(fb_handle_t *handle, const void *buf, size_t stride_bytes); 19 | void fb_deinit(fb_handle_t *handle); 20 | bool fb_should_quit(void); 21 | 22 | #ifdef __cplusplus 23 | extern "C" { 24 | #endif 25 | uint64_t SDL_GetPerformanceCounter(void); 26 | uint64_t SDL_GetPerformanceFrequency(void); 27 | #ifdef __cplusplus 28 | } 29 | #endif 30 | 31 | inline uint64_t higres_ticks() { return SDL_GetPerformanceCounter(); } 32 | inline uint64_t higres_ticks_freq() { return SDL_GetPerformanceFrequency(); } 33 | 34 | #endif //__SIM_FB_H__ 35 | -------------------------------------------------------------------------------- /litex/build/sim/core/modules/xgmii_ethernet/Makefile: -------------------------------------------------------------------------------- 1 | include ../../variables.mak 2 | UNAME_S := $(shell uname -s) 3 | 4 | include $(SRC_DIR)/modules/rules.mak 5 | 6 | CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include 7 | LDFLAGS += -lz 8 | OBJS = $(MOD).o tapcfg.o taplog.o 9 | 10 | $(MOD).so: $(OBJS) 11 | ifeq ($(UNAME_S),Darwin) 12 | $(CC) $(LDFLAGS) -o $@ $^ 13 | else 14 | $(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^ 15 | endif 16 | 17 | tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c 18 | $(CC) $(CFLAGS) -c -o $@ $< 19 | 20 | taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c 21 | $(CC) $(CFLAGS) -c -o $@ $< 22 | -------------------------------------------------------------------------------- /litex/build/sim/core/pads.c: -------------------------------------------------------------------------------- 1 | /* Copyright (C) 2017 LambdaConcept */ 2 | 3 | #include 4 | #include 5 | #include 6 | #include "error.h" 7 | #include "pads.h" 8 | 9 | static struct pad_list_s *padlist=NULL; 10 | 11 | int litex_sim_register_pads(struct pad_s *pads, char *interface_name, int index) 12 | { 13 | int ret = RC_OK; 14 | 15 | struct pad_list_s *pl=NULL; 16 | if(!pads || !interface_name) 17 | { 18 | ret = RC_INVARG; 19 | eprintf("Invalid argument\n"); 20 | goto out; 21 | } 22 | 23 | pl = (struct pad_list_s *)malloc(sizeof(struct pad_list_s)); 24 | if(NULL == pl) 25 | { 26 | ret = RC_NOENMEM; 27 | eprintf("Not enough mem\n"); 28 | goto out; 29 | } 30 | 31 | memset(pl, 0, sizeof(struct pad_list_s)); 32 | 33 | pl->index = index; /* Do we really need it ?*/ 34 | pl->name = strdup(interface_name); 35 | pl->pads = pads; 36 | 37 | pl->next = padlist; 38 | padlist = pl; 39 | 40 | out: 41 | return ret; 42 | } 43 | 44 | int litex_sim_pads_get_list(struct pad_list_s **plist) 45 | { 46 | int ret=RC_OK; 47 | 48 | 49 | if(!plist) 50 | { 51 | ret = RC_INVARG; 52 | eprintf("Invalid argument\n"); 53 | goto out; 54 | } 55 | 56 | *plist = padlist; 57 | out: 58 | return ret; 59 | } 60 | 61 | int litex_sim_pads_find(struct pad_list_s *first, char *name, int index, struct pad_list_s **found) 62 | { 63 | struct pad_list_s *list = NULL; 64 | int ret=RC_OK; 65 | if(!first || !name || !found) 66 | { 67 | ret = RC_INVARG; 68 | eprintf("Invalid arg\n"); 69 | goto out; 70 | } 71 | 72 | for(list = first; list; list=list->next) 73 | { 74 | if(!strcmp(name, list->name) && (list->index == index)) 75 | break; 76 | } 77 | out: 78 | *found = list; 79 | return ret; 80 | } 81 | -------------------------------------------------------------------------------- /litex/build/sim/core/pads.h: -------------------------------------------------------------------------------- 1 | /* Copyright (C) 2017 LambdaConcept */ 2 | 3 | #ifndef __PADS_H_ 4 | #define __PADS_H_ 5 | 6 | struct pad_s { 7 | char *name; 8 | size_t len; 9 | void *signal; 10 | }; 11 | 12 | struct pad_list_s { 13 | char *name; 14 | struct pad_s *pads; 15 | int index; 16 | struct pad_list_s *next; 17 | }; 18 | 19 | int litex_sim_pads_get_list(struct pad_list_s **plist); 20 | int litex_sim_pads_find(struct pad_list_s *first, char *name, int index, struct pad_list_s **found); 21 | 22 | #ifdef __cplusplus 23 | extern "C" int litex_sim_register_pads(struct pad_s *pads, char *interface_name, int index); 24 | #else 25 | int litex_sim_register_pads(struct pad_s *pads, char *interface_name, int index); 26 | #endif 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /litex/build/sim/core/veril.h: -------------------------------------------------------------------------------- 1 | /* Copyright (C) 2017 LambdaConcept */ 2 | 3 | #ifndef __VERIL_H_ 4 | #define __VERIL_H_ 5 | 6 | #include 7 | 8 | #ifdef __cplusplus 9 | extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]); 10 | extern "C" void litex_sim_eval(void *vsim, uint64_t time_ps); 11 | extern "C" void litex_sim_init_tracer(void *vsim, long start, long end); 12 | extern "C" void litex_sim_tracer_dump(); 13 | extern "C" int litex_sim_got_finish(); 14 | #if VM_COVERAGE 15 | extern "C" void litex_sim_coverage_dump(); 16 | #endif 17 | #else 18 | void litex_sim_eval(void *vsim, uint64_t time_ps); 19 | void litex_sim_init_tracer(void *vsim); 20 | void litex_sim_tracer_dump(); 21 | int litex_sim_got_finish(); 22 | void litex_sim_init_cmdargs(int argc, char *argv[]); 23 | #if VM_COVERAGE 24 | void litex_sim_coverage_dump(); 25 | #endif 26 | #endif 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /litex/build/sim/verilog/iddr_verilog.v: -------------------------------------------------------------------------------- 1 | module DDR_INPUT( 2 | output reg o1, 3 | output reg o2, 4 | input i, 5 | input clk); 6 | 7 | reg _o1, _o2; 8 | 9 | always @ (posedge clk) 10 | begin 11 | o1 = _o1; 12 | o2 = _o2; 13 | end 14 | 15 | always @ (posedge clk) 16 | begin 17 | _o1 = i; 18 | end 19 | 20 | always @ (negedge clk) 21 | begin 22 | _o2 = i; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /litex/build/sim/verilog/oddr_verilog.v: -------------------------------------------------------------------------------- 1 | module DDR_OUTPUT( 2 | input i1, 3 | input i2, 4 | output o, 5 | input clk); 6 | 7 | wire _o; 8 | reg _i1, _i2; 9 | 10 | assign o = _o; 11 | assign _o = (clk) ? _i1 : _i2; 12 | 13 | always @ (posedge clk) 14 | begin 15 | _i1 = i1; 16 | _i2 = i2; 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /litex/build/xilinx/__init__.py: -------------------------------------------------------------------------------- 1 | # Platforms. 2 | from litex.build.xilinx.platform import XilinxPlatform 3 | from litex.build.xilinx.platform import XilinxSpartan6Platform 4 | from litex.build.xilinx.platform import Xilinx7SeriesPlatform 5 | from litex.build.xilinx.platform import XilinxUSPlatform 6 | from litex.build.xilinx.platform import XilinxUSPPlatform 7 | 8 | # Programmers. 9 | from litex.build.xilinx.programmer import UrJTAG 10 | from litex.build.xilinx.programmer import XC3SProg 11 | from litex.build.xilinx.programmer import FpgaProg 12 | from litex.build.xilinx.programmer import VivadoProgrammer 13 | from litex.build.xilinx.programmer import iMPACT 14 | from litex.build.xilinx.programmer import Adept 15 | -------------------------------------------------------------------------------- /litex/compat/__init__.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import time 3 | 4 | # Compatibility Layer ------------------------------------------------------------------------------ 5 | 6 | def compat_notice(name, date, info=""): 7 | from litex.gen import colorer 8 | print("Compat: {name} is {deprecated} since {date} and will soon no longer work, please {update}. {info}".format( 9 | name = colorer(name), 10 | deprecated = colorer("deprecated", color="red"), 11 | date = colorer(date), 12 | update = colorer("update", color="red"), 13 | info = info, 14 | ), end="") 15 | # Annoy user to force update :) 16 | for i in range(10): 17 | time.sleep(0.2) 18 | print(".", end="") 19 | sys.stdout.flush() 20 | print("thanks :)") 21 | 22 | def add_compat(location): 23 | # Integration. 24 | if location == "litex.soc.integration": 25 | pass 26 | # Interconnect. 27 | if location == "litex.soc.interconnect": 28 | class compat_stream_sim: 29 | noticed = False 30 | def __getattr__(self, name): 31 | if not self.noticed: 32 | compat_notice("stream_sim", date="2020-03-24", info="Code will not be replaced, copy it in your project to continue using it.") 33 | self.noticed = True 34 | from litex.compat import stream_sim 35 | return getattr(stream_sim, name) 36 | sys.modules["litex.soc.interconnect.stream_sim"] = compat_stream_sim() 37 | 38 | # Cores. 39 | if location == "litex.soc.cores": 40 | pass 41 | -------------------------------------------------------------------------------- /litex/gen/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.gen.sim import * 2 | 3 | from litex.gen.common import * 4 | from litex.gen.signal import * 5 | from litex.gen.reduce import * 6 | from litex.gen.context import * 7 | 8 | from litex.gen.fhdl.module import * 9 | -------------------------------------------------------------------------------- /litex/gen/common.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # This file is Copyright (c) 2018-2022 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | # Coloring Helpers --------------------------------------------------------------------------------- 10 | 11 | def colorer(s, color="bright", enable=True): 12 | """Apply ANSI colors to a string.""" 13 | header = { 14 | "bright": "\x1b[1m", 15 | "green": "\x1b[32m", 16 | "cyan": "\x1b[36m", 17 | "red": "\x1b[31m", 18 | "yellow": "\x1b[33m", 19 | "underline": "\x1b[4m"}[color] 20 | trailer = "\x1b[0m" 21 | return (header + str(s) + trailer) if enable else str(s) 22 | 23 | # Byte Size Definitions ---------------------------------------------------------------------------- 24 | 25 | # Short. 26 | KB = 1024 27 | MB = KB * 1024 28 | GB = MB * 1024 29 | 30 | # Long. 31 | KILOBYTE = 1024 32 | MEGABYTE = KILOBYTE * 1024 33 | GIGABYTE = MEGABYTE * 1024 34 | 35 | # Bit/Bytes Reversing ------------------------------------------------------------------------------ 36 | 37 | def reverse_bits(s): 38 | """Return a signal with reversed bit order.""" 39 | return s[::-1] 40 | 41 | def reverse_bytes(s): 42 | """Return a signal with reversed byte order.""" 43 | n = (len(s) + 7)//8 44 | return Cat(*[s[i*8:min((i + 1)*8, len(s))] 45 | for i in reversed(range(n))]) 46 | -------------------------------------------------------------------------------- /litex/gen/context.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # This file is Copyright (c) 2023 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | # LiteX Context ------------------------------------------------------------------------------------ 10 | 11 | class LiteXContext: 12 | """ 13 | A context for LiteX-related settings. 14 | 15 | This class serves as a container for the platform, toolchain, device, 16 | and system-on-a-chip (SoC) information for a given LiteX project. 17 | 18 | Attributes: 19 | platform : The FPGA Platform of the project. 20 | toolchain : The FPGA Toolchain to be used for synthesis and place-and-route. 21 | device : The FPGA Device of the LiteX project. 22 | top : The FPGA Top-Level Module of the LiteX project. 23 | """ 24 | platform = None 25 | toolchain = None 26 | device = None 27 | top = None 28 | -------------------------------------------------------------------------------- /litex/gen/fhdl/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/gen/fhdl/__init__.py -------------------------------------------------------------------------------- /litex/gen/genlib/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/gen/genlib/__init__.py -------------------------------------------------------------------------------- /litex/gen/reduce.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # This file is Copyright (c) 2022 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | from functools import reduce 10 | from operator import and_, or_, not_, xor, add 11 | 12 | # Reduction ---------------------------------------------------------------------------------------- 13 | 14 | def Reduce(operator, value): 15 | # List of supported Operators. 16 | operators = { 17 | "AND" : and_, 18 | "OR" : or_, 19 | "NOR" : not_, 20 | "XOR" : xor, 21 | "ADD" : add, 22 | } 23 | 24 | # Switch to upper-case. 25 | operator = operator.upper() 26 | 27 | # Check if provided operator is supported. 28 | if operator not in operators.keys(): 29 | supported = ", ".join(operators.keys()) 30 | raise ValueError(f"Reduce does not support {operator} operator; supported: {supported}.") 31 | 32 | # Return Python's reduction. 33 | return reduce(operators[operator], value) 34 | -------------------------------------------------------------------------------- /litex/gen/signal.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # This file is Copyright (c) 2022 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | # Signals ------------------------------------------------------------------------------------------ 10 | 11 | class Open(Signal): 12 | """A base Signal class, representing an open signal.""" 13 | pass 14 | 15 | class Unsigned(Signal): 16 | """ 17 | A Signal subclass for unsigned signals. 18 | 19 | Args: 20 | bits (int): Number of bits of the signal. Defaults to 1. 21 | """ 22 | def __init__(self, bits=1, *args, **kwargs): 23 | assert isinstance(bits, int) 24 | Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs) 25 | 26 | class Signed(Signal): 27 | """ 28 | A Signal subclass for signed signals. 29 | 30 | Args: 31 | bits (int): Number of bits of the signal. Defaults to 1. 32 | """ 33 | def __init__(self, bits=1, *args, **kwargs): 34 | assert isinstance(bits, int) 35 | Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs) 36 | -------------------------------------------------------------------------------- /litex/gen/sim/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.gen.sim.core import Simulator, run_simulation, passive 2 | -------------------------------------------------------------------------------- /litex/soc/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/soc/__init__.py -------------------------------------------------------------------------------- /litex/soc/cores/__init__.py: -------------------------------------------------------------------------------- 1 | import sys 2 | from litex.compat import add_compat 3 | add_compat(__name__) 4 | -------------------------------------------------------------------------------- /litex/soc/cores/can/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/soc/cores/can/__init__.py -------------------------------------------------------------------------------- /litex/soc/cores/clock/__init__.py: -------------------------------------------------------------------------------- 1 | # Xilinx 2 | from litex.soc.cores.clock.xilinx_s6 import S6PLL, S6DCM 3 | from litex.soc.cores.clock.xilinx_s7 import S7PLL, S7MMCM, S7IDELAYCTRL 4 | from litex.soc.cores.clock.xilinx_us import USPLL, USMMCM, USIDELAYCTRL 5 | from litex.soc.cores.clock.xilinx_usp import USPPLL, USPMMCM, USPIDELAYCTRL 6 | 7 | # Intel 8 | from litex.soc.cores.clock.intel_max10 import Max10PLL 9 | from litex.soc.cores.clock.intel_cyclone4 import CycloneIVPLL 10 | from litex.soc.cores.clock.intel_cyclone5 import CycloneVPLL 11 | from litex.soc.cores.clock.intel_cyclone10 import Cyclone10LPPLL 12 | 13 | # Lattice 14 | from litex.soc.cores.clock.lattice_ice40 import iCE40PLL 15 | from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL, ECP5DynamicDelay 16 | from litex.soc.cores.clock.lattice_nx import NXOSCA, NXPLL 17 | 18 | # Efinix 19 | from litex.soc.cores.clock.efinix import TRIONPLL, TITANIUMPLL 20 | -------------------------------------------------------------------------------- /litex/soc/cores/clock/gowin_gw2a.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2022 Icenowy Zheng 5 | # Copyright (c) 2022 Florent Kermarrec 6 | # SPDX-License-Identifier: BSD-2-Clause 7 | 8 | from migen import * 9 | 10 | from litex.soc.cores.clock.gowin_gw1n import GW1NPLL 11 | 12 | # GoWin / GW2APLL ---------------------------------------------------------------------------------- 13 | 14 | class GW2APLL(GW1NPLL): 15 | # GW2A has the same PLL primitive than GW1N but vco/pfd_freq_range are specific to device. 16 | 17 | @staticmethod 18 | def get_vco_freq_range(device): 19 | vco_freq_range = None 20 | if device.startswith('GW2A-') or device.startswith('GW2AR-'): 21 | vco_freq_range = (500e6, 1250e6) # datasheet values 22 | if vco_freq_range is None: 23 | raise ValueError(f"Unsupported device {device}.") 24 | return vco_freq_range 25 | 26 | @staticmethod 27 | def get_pfd_freq_range(device): 28 | pfd_freq_range = None 29 | if device.startswith('GW2A-') or device.startswith('GW2AR-'): 30 | pfd_freq_range = (3e6, 500e6) # datasheet values 31 | if pfd_freq_range is None: 32 | raise ValueError(f"Unsupported device {device}.") 33 | return pfd_freq_range 34 | -------------------------------------------------------------------------------- /litex/soc/cores/clock/intel_cyclone10.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2018-2020 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | from litex.soc.cores.clock.common import * 10 | from litex.soc.cores.clock.intel_common import * 11 | 12 | # Intel / Cyclone10LP ------------------------------------------------------------------------------ 13 | 14 | class Cyclone10LPPLL(IntelClocking): 15 | nclkouts_max = 5 16 | n_div_range = (1, 512+1) 17 | m_div_range = (1, 512+1) 18 | c_div_range = (1, 512+1) 19 | clkin_pfd_freq_range = (5e6, 325e6) 20 | vco_freq_range = (600e6, 1300e6) 21 | def __init__(self, speedgrade="-C6"): 22 | self.logger = logging.getLogger("Cyclone10LPPLL") 23 | self.logger.info("Creating Cyclone10LPPLL, {}.".format(colorer("speedgrade {}".format(speedgrade)))) 24 | IntelClocking.__init__(self) 25 | self.clkin_freq_range = { 26 | "-C6" : (5e6, 472.5e6), 27 | "-C8" : (5e6, 472.5e6), 28 | "-I7" : (5e6, 472.5e6), 29 | "-A7" : (5e6, 472.5e6), 30 | "-I8" : (5e6, 362e6), 31 | }[speedgrade] 32 | self.clko_freq_range = { 33 | "-C6" : (0e6, 472.5e6), 34 | "-C8" : (0e6, 402.5e6), 35 | "-I7" : (0e6, 450e6), 36 | "-A7" : (0e6, 450e6), 37 | "-I8" : (0e6, 362e6), 38 | }[speedgrade] 39 | -------------------------------------------------------------------------------- /litex/soc/cores/clock/intel_cyclone4.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2018-2020 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | from litex.soc.cores.clock.common import * 10 | from litex.soc.cores.clock.intel_common import * 11 | 12 | # Intel / CycloneIV ------------------------------------------------------------------------------- 13 | 14 | class CycloneIVPLL(IntelClocking): 15 | nclkouts_max = 5 16 | n_div_range = (1, 512+1) 17 | m_div_range = (1, 512+1) 18 | c_div_range = (1, 512+1) 19 | clkin_pfd_freq_range = (5e6, 325e6) 20 | vco_freq_range = (600e6, 1300e6) 21 | def __init__(self, speedgrade="-6"): 22 | self.logger = logging.getLogger("CycloneIVPLL") 23 | self.logger.info("Creating CycloneIVPLL, {}.".format(colorer("speedgrade {}".format(speedgrade)))) 24 | IntelClocking.__init__(self) 25 | self.clkin_freq_range = { 26 | "-6" : (5e6, 472.5e6), 27 | "-7" : (5e6, 472.5e6), 28 | "-8" : (5e6, 472.5e6), 29 | "-8L": (5e6, 362e6), 30 | "-9L": (5e6, 256e6), 31 | }[speedgrade] 32 | self.clko_freq_range = { 33 | "-6" : (0e6, 472.5e6), 34 | "-7" : (0e6, 450e6), 35 | "-8" : (0e6, 402.5e6), 36 | "-8L": (0e6, 362e6), 37 | "-9L": (0e6, 265e6), 38 | }[speedgrade] 39 | -------------------------------------------------------------------------------- /litex/soc/cores/clock/intel_cyclone5.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2018-2020 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | from litex.soc.cores.clock.common import * 10 | from litex.soc.cores.clock.intel_common import * 11 | 12 | # Intel / CycloneV -------------------------------------------------------------------------------- 13 | 14 | class CycloneVPLL(IntelClocking): 15 | nclkouts_max = 5 16 | n_div_range = (1, 512+1) 17 | m_div_range = (1, 512+1) 18 | c_div_range = (1, 512+1) 19 | clkin_pfd_freq_range = (5e6, 325e6) 20 | def __init__(self, speedgrade="-C6"): 21 | self.logger = logging.getLogger("CycloneVPLL") 22 | self.logger.info("Creating CycloneVPLL, {}.".format(colorer("speedgrade {}".format(speedgrade)))) 23 | IntelClocking.__init__(self) 24 | self.clkin_freq_range = { 25 | "-C6" : (5e6, 670e6), 26 | "-C7" : (5e6, 622e6), 27 | "-I7" : (5e6, 622e6), 28 | "-C8" : (5e6, 622e6), 29 | "-A7" : (5e6, 500e6), 30 | }[speedgrade] 31 | self.vco_freq_range = { 32 | "-C6" : (600e6, 1600e6), 33 | "-C7" : (600e6, 1600e6), 34 | "-I7" : (600e6, 1600e6), 35 | "-C8" : (600e6, 1300e6), 36 | "-A7" : (600e6, 1300e6), 37 | }[speedgrade] 38 | self.clko_freq_range = { 39 | "-C6" : (0e6, 550e6), 40 | "-C7" : (0e6, 550e6), 41 | "-I7" : (0e6, 550e6), 42 | "-C8" : (0e6, 460e6), 43 | "-A7" : (0e6, 460e6), 44 | }[speedgrade] 45 | -------------------------------------------------------------------------------- /litex/soc/cores/clock/intel_max10.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2018-2020 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | from litex.soc.cores.clock.common import * 10 | from litex.soc.cores.clock.intel_common import * 11 | 12 | # Intel / Max10 ------------------------------------------------------------------------------------ 13 | 14 | class Max10PLL(IntelClocking): 15 | nclkouts_max = 5 16 | n_div_range = (1, 512+1) 17 | m_div_range = (1, 512+1) 18 | c_div_range = (1, 512+1) 19 | clkin_freq_range = (5e6, 472.5e6) 20 | clkin_pfd_freq_range = (5e6, 325e6) # FIXME: use 21 | vco_freq_range = (600e6, 1300e6) 22 | def __init__(self, speedgrade="-6"): 23 | self.logger = logging.getLogger("Max10PLL") 24 | self.logger.info("Creating Max10PLL, {}.".format(colorer("speedgrade {}".format(speedgrade)))) 25 | IntelClocking.__init__(self) 26 | self.clko_freq_range = { 27 | "-6" : (0e6, 472.5e6), 28 | "-7" : (0e6, 450e6), 29 | "-8" : (0e6, 402.5e6), 30 | }[speedgrade] 31 | -------------------------------------------------------------------------------- /litex/soc/cores/clock/intel_stratix5.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2023 stone3311 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | from litex.soc.cores.clock.common import * 10 | from litex.soc.cores.clock.intel_common import * 11 | 12 | # Intel / StratixV -------------------------------------------------------------------------------- 13 | 14 | class StratixVPLL(IntelClocking): 15 | nclkouts_max = 18 16 | n_div_range = (1, 512+1) 17 | m_div_range = (1, 512+1) 18 | c_div_range = (1, 512+1) 19 | clkin_pfd_freq_range = (5e6, 325e6) 20 | def __init__(self, speedgrade="-C4"): 21 | self.logger = logging.getLogger("StratixVPLL") 22 | self.logger.info("Creating StratixVPLL, {}.".format(colorer("speedgrade {}".format(speedgrade)))) 23 | IntelClocking.__init__(self) 24 | 25 | if speedgrade == "-C4" or speedgrade == "-I4": 26 | self.clkin_freq_range = (5e6, 650e6) 27 | self.vco_freq_range = (600e6, 1300e6) 28 | else: 29 | self.clkin_freq_range = (5e6, 800e6) 30 | self.vco_freq_range = (600e6, 1600e6) 31 | 32 | self.clko_freq_range = { 33 | "-C1" : (5e6, 717e6), 34 | "-C2" : (5e6, 717e6), 35 | "-C2L" : (5e6, 717e6), 36 | "-I2" : (5e6, 717e6), 37 | "-I2L" : (5e6, 717e6), 38 | "-C3" : (5e6, 650e6), 39 | "-I3" : (5e6, 650e6), 40 | "-I3L" : (5e6, 650e6), 41 | "-C4" : (5e6, 580e6), 42 | "-I4" : (5e6, 580e6), 43 | }[speedgrade] 44 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/blackparrot/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.blackparrot.core import BlackParrot 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/blackparrot/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/blackparrot/crt0.S: -------------------------------------------------------------------------------- 1 | .global main 2 | .global isr 3 | .global _start 4 | 5 | _start: 6 | j crt_init 7 | nop 8 | nop 9 | nop 10 | nop 11 | nop 12 | nop 13 | nop 14 | 15 | trap_entry: 16 | sd x1, - 1*8(sp) 17 | sd x5, - 2*8(sp) 18 | sd x6, - 3*8(sp) 19 | sd x7, - 4*8(sp) 20 | sd x10, - 5*8(sp) 21 | sd x11, - 6*8(sp) 22 | sd x12, - 7*8(sp) 23 | sd x13, - 8*8(sp) 24 | sd x14, - 9*8(sp) 25 | sd x15, -10*8(sp) 26 | sd x16, -11*8(sp) 27 | sd x17, -12*8(sp) 28 | sd x28, -13*8(sp) 29 | sd x29, -14*8(sp) 30 | sd x30, -15*8(sp) 31 | sd x31, -16*8(sp) 32 | addi sp,sp,-16*8 33 | call isr 34 | ld x1 , 15*8(sp) 35 | ld x5, 14*8(sp) 36 | ld x6, 13*8(sp) 37 | ld x7, 12*8(sp) 38 | ld x10, 11*8(sp) 39 | ld x11, 10*8(sp) 40 | ld x12, 9*8(sp) 41 | ld x13, 8*8(sp) 42 | ld x14, 7*8(sp) 43 | ld x15, 6*8(sp) 44 | ld x16, 5*8(sp) 45 | ld x17, 4*8(sp) 46 | ld x28, 3*8(sp) 47 | ld x29, 2*8(sp) 48 | ld x30, 1*8(sp) 49 | ld x31, 0*8(sp) 50 | addi sp,sp,16*8 51 | mret 52 | .text 53 | 54 | 55 | crt_init: 56 | la sp, _fstack 57 | la a0, trap_entry 58 | csrw mtvec, a0 59 | 60 | data_init: 61 | la a0, _fdata 62 | la a1, _edata 63 | la a2, _fdata_rom 64 | data_loop: 65 | beq a0,a1,data_done 66 | ld a3,0(a2) 67 | sd a3,0(a0) 68 | add a0,a0,8 69 | add a2,a2,8 70 | j data_loop 71 | data_done: 72 | 73 | bss_init: 74 | la a0, _fbss 75 | la a1, _ebss 76 | bss_loop: 77 | beq a0,a1,bss_done 78 | sd zero,0(a0) 79 | add a0,a0,8 80 | j bss_loop 81 | bss_done: 82 | 83 | // call plic_init // initialize external interrupt controller 84 | li a0, 0x800 // external interrupt sources only (using LiteX timer); 85 | // NOTE: must still enable mstatus.MIE! 86 | csrw mie,a0 87 | 88 | call main 89 | inf_loop: 90 | j inf_loop 91 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/blackparrot/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_DCACHE_INFO 0xCC0 7 | 8 | #endif /* CSR_DEFS__H */ 9 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/blackparrot/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | // The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which 13 | // is programmed and queried via a set of MMIO registers. 14 | // TODO: How about Blackparrot? Should be probably included in linux version 15 | 16 | #define PLIC_BASE 0x0c000000L // Base address and per-pin priority array 17 | #define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins 18 | #define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask 19 | #define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger 20 | #define PLIC_CLAIM 0x0c200004L // Claim & completion register address 21 | 22 | static inline unsigned int irq_getie(void) 23 | { 24 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; /* FIXME */ 25 | } 26 | 27 | static inline void irq_setie(unsigned int ie) 28 | { 29 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); /* FIXME */ 30 | } 31 | 32 | static inline unsigned int irq_getmask(void) 33 | { 34 | return 0; /* FIXME */ 35 | } 36 | 37 | static inline void irq_setmask(unsigned int mask) 38 | { 39 | /* FIXME */ 40 | } 41 | 42 | static inline unsigned int irq_pending(void) 43 | { 44 | return csr_readl(PLIC_PENDING) >> 1; /* FIXME */ 45 | } 46 | 47 | #ifdef __cplusplus 48 | } 49 | #endif 50 | 51 | #endif /* __IRQ_H */ 52 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/blackparrot/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ 10 | void flush_l2_cache(void); 11 | void busy_wait(unsigned int ms); 12 | void busy_wait_us(unsigned int us); 13 | 14 | #include 15 | 16 | #define csrr(reg) ({ unsigned long __tmp; \ 17 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 18 | __tmp; }) 19 | 20 | #define csrw(reg, val) ({ \ 21 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 22 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 23 | else \ 24 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 25 | 26 | #define csrs(reg, bit) ({ \ 27 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 28 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 29 | else \ 30 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 31 | 32 | #define csrc(reg, bit) ({ \ 33 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 34 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 35 | else \ 36 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 37 | 38 | #ifdef __cplusplus 39 | } 40 | #endif 41 | 42 | #endif /* __SYSTEM_H */ 43 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/coreblocks/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.coreblocks.core import Coreblocks 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/coreblocks/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/coreblocks/crt0.S: -------------------------------------------------------------------------------- 1 | .global _start 2 | _start: 3 | j reset_vector 4 | 5 | reset_vector: 6 | la sp, _fstack 7 | la t0, trap_vector 8 | csrw mtvec, t0 9 | 10 | // initialize .data 11 | la t0, _fdata 12 | la t1, _edata 13 | la t2, _fdata_rom 14 | 1: beq t0, t1, 2f 15 | lw t3, 0(t2) 16 | sw t3, 0(t0) 17 | addi t0, t0, 4 18 | addi t2, t2, 4 19 | j 1b 20 | 2: 21 | 22 | // initialize .bss 23 | la t0, _fbss 24 | la t1, _ebss 25 | 1: beq t0, t1, 3f 26 | sw zero, 0(t0) 27 | addi t0, t0, 4 28 | j 1b 29 | 3: 30 | 31 | call main 32 | 33 | 1: j 1b 34 | 35 | trap_vector: 36 | addi sp, sp, -16*4 37 | sw ra, 0*4(sp) 38 | sw t0, 1*4(sp) 39 | sw t1, 2*4(sp) 40 | sw t2, 3*4(sp) 41 | sw a0, 4*4(sp) 42 | sw a1, 5*4(sp) 43 | sw a2, 6*4(sp) 44 | sw a3, 7*4(sp) 45 | sw a4, 8*4(sp) 46 | sw a5, 9*4(sp) 47 | sw a6, 10*4(sp) 48 | sw a7, 11*4(sp) 49 | sw t3, 12*4(sp) 50 | sw t4, 13*4(sp) 51 | sw t5, 14*4(sp) 52 | sw t6, 15*4(sp) 53 | call isr 54 | lw ra, 0*4(sp) 55 | lw t0, 1*4(sp) 56 | lw t1, 2*4(sp) 57 | lw t2, 3*4(sp) 58 | lw a0, 4*4(sp) 59 | lw a1, 5*4(sp) 60 | lw a2, 6*4(sp) 61 | lw a3, 7*4(sp) 62 | lw a4, 8*4(sp) 63 | lw a5, 9*4(sp) 64 | lw a6, 10*4(sp) 65 | lw a7, 11*4(sp) 66 | lw t3, 12*4(sp) 67 | lw t4, 13*4(sp) 68 | lw t5, 14*4(sp) 69 | lw t6, 15*4(sp) 70 | addi sp, sp, 16*4 71 | mret 72 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/coreblocks/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | // mie 7 | #define CSR_IRQ_MASK 0x304 8 | 9 | // mip 10 | #define CSR_IRQ_PENDING 0x344 11 | 12 | // first platform irq - enables offset in internal software 13 | #define FIRQ_OFFSET 16 14 | 15 | #endif /* CSR_DEFS__H */ 16 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/coreblocks/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include "csr-defs.h" 13 | 14 | static inline unsigned int irq_getie(void) 15 | { 16 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 17 | } 18 | 19 | static inline void irq_setie(unsigned int ie) 20 | { 21 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 22 | } 23 | 24 | static inline unsigned int irq_getmask(void) 25 | { 26 | unsigned int mask; 27 | asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); 28 | return (mask>>FIRQ_OFFSET); 29 | } 30 | 31 | static inline void irq_setmask(unsigned int mask) 32 | { 33 | asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask<> FIRQ_OFFSET); 41 | } 42 | 43 | #ifdef __cplusplus 44 | } 45 | #endif 46 | 47 | #endif /* __IRQ_H */ 48 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/coreblocks/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void) { 9 | asm volatile ("fence.i"); 10 | }; 11 | 12 | __attribute__((unused)) static void flush_cpu_dcache(void){}; // currently no dcache 13 | 14 | void flush_l2_cache(void); 15 | void busy_wait(unsigned int ms); 16 | void busy_wait_us(unsigned int us); 17 | 18 | #include 19 | 20 | #define csrr(reg) ({ unsigned long __tmp; \ 21 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 22 | __tmp; }) 23 | 24 | #define csrw(reg, val) ({ \ 25 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 26 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 27 | else \ 28 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 29 | 30 | #define csrs(reg, bit) ({ \ 31 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 32 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 33 | else \ 34 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 35 | 36 | #define csrc(reg, bit) ({ \ 37 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 38 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 39 | else \ 40 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 41 | 42 | #ifdef __cplusplus 43 | } 44 | #endif 45 | 46 | #endif /* __SYSTEM_H */ 47 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cortex_m1/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.cortex_m1.core import CortexM1 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cortex_m1/boot-helper.c: -------------------------------------------------------------------------------- 1 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); 2 | 3 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) { 4 | goto *(void*)addr; 5 | } 6 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cortex_m1/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #include 5 | #include "system.h" 6 | #include "generated/soc.h" 7 | 8 | 9 | #ifdef __cplusplus 10 | extern "C" { 11 | #endif 12 | 13 | extern volatile unsigned int irqs_enabled; 14 | 15 | static inline unsigned int irq_getie(void) 16 | { 17 | return irqs_enabled; /* FIXME */ 18 | } 19 | 20 | static inline void irq_setie(unsigned int ie) 21 | { 22 | if (ie) 23 | __asm__ volatile ("cpsie i" : : : "memory"); 24 | else 25 | __asm__ volatile ("cpsid i" : : : "memory"); 26 | irqs_enabled = ie; 27 | } 28 | 29 | static inline unsigned int irq_getmask(void) 30 | { 31 | return (1 << UART_INTERRUPT); // FIXME 32 | } 33 | 34 | static inline void irq_setmask(unsigned int mask) 35 | { 36 | /* TODO */ 37 | } 38 | 39 | static inline unsigned int irq_pending(void) 40 | { 41 | /* TODO */ 42 | return 0; 43 | } 44 | 45 | 46 | #ifdef __cplusplus 47 | } 48 | #endif 49 | 50 | #endif /* __IRQ_H */ 51 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cortex_m1/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cortex_m3/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.cortex_m3.core import CortexM3 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cortex_m3/boot-helper.c: -------------------------------------------------------------------------------- 1 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); 2 | 3 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) { 4 | goto *(void*)addr; 5 | } 6 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cortex_m3/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #include 5 | #include "system.h" 6 | #include "generated/soc.h" 7 | 8 | 9 | #ifdef __cplusplus 10 | extern "C" { 11 | #endif 12 | 13 | extern volatile unsigned int irqs_enabled; 14 | 15 | static inline unsigned int irq_getie(void) 16 | { 17 | return irqs_enabled; /* FIXME */ 18 | } 19 | 20 | static inline void irq_setie(unsigned int ie) 21 | { 22 | if (ie) 23 | __asm__ volatile ("cpsie i" : : : "memory"); 24 | else 25 | __asm__ volatile ("cpsid i" : : : "memory"); 26 | irqs_enabled = ie; 27 | } 28 | 29 | static inline unsigned int irq_getmask(void) 30 | { 31 | return (1 << UART_INTERRUPT); // FIXME 32 | } 33 | 34 | static inline void irq_setmask(unsigned int mask) 35 | { 36 | /* TODO */ 37 | } 38 | 39 | static inline unsigned int irq_pending(void) 40 | { 41 | /* TODO */ 42 | return 0; 43 | } 44 | 45 | 46 | #ifdef __cplusplus 47 | } 48 | #endif 49 | 50 | #endif /* __IRQ_H */ 51 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cortex_m3/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e40p/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.cv32e40p.core import CV32E40P 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e40p/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e40p/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | /*Reference : https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/control_status_registers.html */ 5 | 6 | #define CSR_MSTATUS_MIE 0x8 7 | 8 | #define CSR_IRQ_MASK 0x304 9 | #define CSR_IRQ_PENDING 0x344 10 | #define FIRQ_OFFSET 16 11 | #define CSR_DCACHE_INFO 0xCC0 12 | 13 | 14 | #endif /* CSR_DEFS__H */ 15 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e40p/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | 11 | static inline unsigned int irq_getie(void) 12 | { 13 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 14 | } 15 | 16 | static inline void irq_setie(unsigned int ie) 17 | { 18 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 19 | } 20 | 21 | static inline unsigned int irq_getmask(void) 22 | { 23 | unsigned int mask; 24 | asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); 25 | return (mask >> FIRQ_OFFSET); 26 | } 27 | 28 | static inline void irq_setmask(unsigned int mask) 29 | { 30 | asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask << FIRQ_OFFSET)); 31 | } 32 | 33 | static inline unsigned int irq_pending(void) 34 | { 35 | unsigned int pending; 36 | asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); 37 | return (pending >> FIRQ_OFFSET); 38 | } 39 | 40 | #ifdef __cplusplus 41 | } 42 | #endif 43 | 44 | #endif /* __IRQ_H */ 45 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e40p/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 11 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 12 | 13 | void flush_l2_cache(void); 14 | 15 | void busy_wait(unsigned int ms); 16 | void busy_wait_us(unsigned int us); 17 | 18 | #define csrr(reg) ({ unsigned long __tmp; \ 19 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 20 | __tmp; }) 21 | 22 | #define csrw(reg, val) ({ \ 23 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 24 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 25 | else \ 26 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 27 | 28 | #define csrs(reg, bit) ({ \ 29 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 30 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 31 | else \ 32 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 33 | 34 | #define csrc(reg, bit) ({ \ 35 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 36 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 37 | else \ 38 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 39 | 40 | #ifdef __cplusplus 41 | } 42 | #endif 43 | 44 | #endif /* __SYSTEM_H */ 45 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e41p/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.cv32e41p.core import CV32E41P 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e41p/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e41p/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | 5 | #define CSR_MSTATUS_MIE 0x8 6 | 7 | #define CSR_IRQ_MASK 0x304 8 | #define CSR_IRQ_PENDING 0x344 9 | #define FIRQ_OFFSET 16 10 | #define CSR_DCACHE_INFO 0xCC0 11 | 12 | #endif /* CSR_DEFS__H */ 13 | 14 | 15 | /* 16 | For CV32E41P from https://docs.openhwgroup.org/projects/cv32e41p-user-manual/control_status_registers.html 17 | Machine Interrupt Pending Register (mip): CSR_IRQ_PENDING: 0x344 18 | Machine Interrupt Enable Register (mie): CSR_IRQ_MASK: 0x304 19 | */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e41p/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | 11 | static inline unsigned int irq_getie(void) 12 | { 13 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 14 | } 15 | 16 | static inline void irq_setie(unsigned int ie) 17 | { 18 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 19 | } 20 | 21 | static inline unsigned int irq_getmask(void) 22 | { 23 | unsigned int mask; 24 | asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); 25 | return (mask >> FIRQ_OFFSET); 26 | } 27 | 28 | static inline void irq_setmask(unsigned int mask) 29 | { 30 | asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask << FIRQ_OFFSET)); 31 | } 32 | 33 | static inline unsigned int irq_pending(void) 34 | { 35 | unsigned int pending; 36 | asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); 37 | return (pending >> FIRQ_OFFSET); 38 | } 39 | 40 | #ifdef __cplusplus 41 | } 42 | #endif 43 | 44 | #endif /* __IRQ_H */ 45 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cv32e41p/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | __attribute__((unused)) static void flush_cpu_icache(void) 11 | { 12 | // FIXME 13 | asm volatile("nop"); 14 | } 15 | 16 | __attribute__((unused)) static void flush_cpu_dcache(void) 17 | { 18 | // FIXME 19 | asm volatile("nop"); 20 | } 21 | 22 | void flush_l2_cache(void); 23 | 24 | void busy_wait(unsigned int ms); 25 | void busy_wait_us(unsigned int us); 26 | 27 | #define csrr(reg) ({ unsigned long __tmp; \ 28 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 29 | __tmp; }) 30 | 31 | #define csrw(reg, val) ({ \ 32 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 33 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 34 | else \ 35 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 36 | 37 | #define csrs(reg, bit) ({ \ 38 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 39 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 40 | else \ 41 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 42 | 43 | #define csrc(reg, bit) ({ \ 44 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 45 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 46 | else \ 47 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 48 | 49 | #ifdef __cplusplus 50 | } 51 | #endif 52 | 53 | #endif /* __SYSTEM_H */ 54 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva5/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.cva5.core import CVA5 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva5/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | .global smp_lottery_target 4 | .global smp_lottery_lock 5 | .global smp_lottery_args 6 | 7 | boot_helper: 8 | sw x10, smp_lottery_args , x14 9 | sw x11, smp_lottery_args+4, x14 10 | sw x12, smp_lottery_args+8, x14 11 | sw x13, smp_lottery_target, x14 12 | fence w, w 13 | li x15, 1 14 | sw x15, smp_lottery_lock, x14 15 | jr x13 -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva5/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_IRQ_EXTERNAL_OFFSET 0xB 7 | 8 | #endif /* CSR_DEFS__H */ 9 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva6/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.cva6.core import CVA6 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva6/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | .global smp_ap_args 4 | .global smp_ap_target 5 | .global smp_ap_ready 6 | 7 | #if __riscv_xlen == 32 8 | 9 | boot_helper: 10 | // boot core saves args and jump target for ap cores: 11 | sw a0, smp_ap_args, t1 12 | sw a1, smp_ap_args+4, t1 13 | sw a2, smp_ap_args+8, t1 14 | sw a3, smp_ap_target, t1 15 | fence w, w 16 | // notify application cores to proceed with boot: 17 | li t0, 1 18 | sw t0, smp_ap_ready, t1 19 | // boot core now also ready to boot: 20 | jr a3 21 | 22 | #else 23 | 24 | boot_helper: 25 | // boot core saves args and jump target for ap cores: 26 | sd a0, smp_ap_args, t1 27 | sd a1, smp_ap_args+8, t1 28 | sd a2, smp_ap_args+16, t1 29 | sd a3, smp_ap_target, t1 30 | fence w, w 31 | // notify application cores to proceed with boot: 32 | li t0, 1 33 | sd t0, smp_ap_ready, t1 34 | // boot core now also ready to boot: 35 | jr a3 36 | 37 | #endif 38 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva6/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_DCACHE_INFO 0xCC0 7 | 8 | #endif /* CSR_DEFS__H */ 9 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva6/cva6_wrapper/cva6_defines.sv: -------------------------------------------------------------------------------- 1 | `define WT_DCACHE 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva6/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | // The CVA6 uses a Platform-Level Interrupt Controller (PLIC) which 13 | // is programmed and queried via a set of MMIO registers. 14 | 15 | #define PLIC_BASE 0x0c000000L // Base address and per-pin priority array 16 | #define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins 17 | #define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask 18 | #define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger 19 | #define PLIC_CLAIM 0x0c200004L // Claim & completion register address 20 | 21 | #define PLIC_EXT_IRQ_BASE 1 22 | 23 | static inline unsigned int irq_getie(void) 24 | { 25 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 26 | } 27 | 28 | static inline void irq_setie(unsigned int ie) 29 | { 30 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 31 | } 32 | 33 | static inline unsigned int irq_getmask(void) 34 | { 35 | return *((unsigned int *)PLIC_ENABLED) >> 1; 36 | } 37 | 38 | static inline void irq_setmask(unsigned int mask) 39 | { 40 | *((unsigned int *)PLIC_ENABLED) = mask << 1; 41 | } 42 | 43 | static inline unsigned int irq_pending(void) 44 | { 45 | return *((unsigned int *)PLIC_PENDING) >> 1; 46 | } 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* __IRQ_H */ 53 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/cva6/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){} /* FIXME: do something useful here! */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #include 16 | 17 | #define csrr(reg) ({ unsigned long __tmp; \ 18 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 19 | __tmp; }) 20 | 21 | #define csrw(reg, val) ({ \ 22 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 23 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 24 | else \ 25 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 26 | 27 | #define csrs(reg, bit) ({ \ 28 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 29 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 30 | else \ 31 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 32 | 33 | #define csrc(reg, bit) ({ \ 34 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 35 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 36 | else \ 37 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 38 | 39 | #ifdef __cplusplus 40 | } 41 | #endif 42 | 43 | #endif /* __SYSTEM_H */ 44 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/eos_s3/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.eos_s3.core import EOS_S3 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/eos_s3/boot-helper.c: -------------------------------------------------------------------------------- 1 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); 2 | 3 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) { 4 | goto *(void*)addr; 5 | } 6 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/eos_s3/crt0.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | extern uint32_t _fdata_rom, _fdata, _edata, _fbss, _ebss; 4 | 5 | void SystemInit(void); 6 | void Reset_Handler(void); 7 | void _start(void); 8 | 9 | void _start(void) { 10 | Reset_Handler(); 11 | } 12 | 13 | void Reset_Handler(void) { 14 | uint32_t *y = &_fdata_rom; 15 | for (uint32_t *x = &_fdata; x < &_edata; x ++) 16 | *x = *y ++; 17 | 18 | for (uint32_t *x = &_fbss; x < &_ebss; x ++) 19 | *x = 0; 20 | 21 | #ifndef __NO_SYSTEM_INIT 22 | SystemInit(); 23 | #endif 24 | 25 | // just in case - for now EOS CPU support relies on QORC SDK 26 | // and main() is launched inside SystemInit() as FreeRTOS task 27 | // so this call is not reached 28 | __asm__("bl main"); 29 | } 30 | 31 | __attribute__((weak)) uint32_t __semihost_call(uint32_t r0, uint32_t r1); 32 | 33 | __attribute__((weak)) uint32_t __semihost_call(uint32_t r0, uint32_t r1) { 34 | return 0; 35 | } 36 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/eos_s3/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | static inline unsigned int irq_getie(void) 9 | { 10 | return 0; /* FIXME */ 11 | } 12 | 13 | static inline void irq_setie(unsigned int ie) 14 | { 15 | /* FIXME */ 16 | } 17 | 18 | static inline unsigned int irq_getmask(void) 19 | { 20 | return 0; /* FIXME */ 21 | } 22 | 23 | static inline void irq_setmask(unsigned int mask) 24 | { 25 | /* FIXME */ 26 | } 27 | 28 | static inline unsigned int irq_pending(void) 29 | { 30 | return 0; /* FIXME */ 31 | } 32 | 33 | #ifdef __cplusplus 34 | } 35 | #endif 36 | 37 | #endif /* __IRQ_H */ 38 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/eos_s3/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | 10 | __attribute__((unused)) static void flush_cpu_icache(void){}; 11 | __attribute__((unused)) static void flush_cpu_dcache(void){}; 12 | void flush_l2_cache(void); 13 | 14 | void busy_wait(unsigned int ms); 15 | void busy_wait_us(unsigned int us); 16 | 17 | #define CSR_UART_BASE 18 | #define UART_POLLING 19 | #define UART_ID_HW 1 // hard UART on the S3 20 | #define UART_ID UART_ID_HW 21 | 22 | void uart_tx(int uartid, int c); 23 | int uart_rx(int uartid); 24 | int uart_rx_available(int uartid); 25 | int uart_tx_is_fifo_full(int uart_id); 26 | 27 | static inline void uart_rxtx_write(char c) { 28 | uart_tx(UART_ID, c); 29 | } 30 | 31 | static inline uint8_t uart_rxtx_read(void) { 32 | return uart_rx(UART_ID); 33 | } 34 | 35 | static inline uint8_t uart_txfull_read(void) { 36 | return uart_tx_is_fifo_full(UART_ID); 37 | } 38 | 39 | static inline uint8_t uart_rxempty_read(void) { 40 | return uart_rx_available(UART_ID); 41 | } 42 | 43 | static inline void uart_ev_pending_write(uint8_t x) {} 44 | 45 | static inline uint8_t uart_ev_pending_read(void) { 46 | return 0; 47 | } 48 | 49 | static inline void uart_ev_enable_write(uint8_t x) {} 50 | 51 | 52 | #ifdef __cplusplus 53 | } 54 | #endif 55 | 56 | #endif /* __SYSTEM_H */ 57 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/fazyrv/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.fazyrv.core import FazyRV 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/fazyrv/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/fazyrv/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/fazyrv/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #endif /* __IRQ_H */ 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/fazyrv/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/femtorv/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.femtorv.core import FemtoRV 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/femtorv/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/femtorv/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/femtorv/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #endif /* __IRQ_H */ 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/femtorv/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/firev/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.firev.core import FireV 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/firev/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/firev/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/firev/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #endif /* __IRQ_H */ 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/firev/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_ae350/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.gowin_ae350.core import GowinAE350 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_ae350/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_ae350/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_ae350/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #endif /* __IRQ_H */ 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_ae350/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_emcu/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.gowin_emcu.core import GowinEMCU 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_emcu/boot-helper.c: -------------------------------------------------------------------------------- 1 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); 2 | 3 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) { 4 | goto *(void*)addr; 5 | } 6 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_emcu/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | static inline unsigned int irq_getie(void) 9 | { 10 | return 0; /* FIXME */ 11 | } 12 | 13 | static inline void irq_setie(unsigned int ie) 14 | { 15 | /* FIXME */ 16 | } 17 | 18 | static inline unsigned int irq_getmask(void) 19 | { 20 | return 0; /* FIXME */ 21 | } 22 | 23 | static inline void irq_setmask(unsigned int mask) 24 | { 25 | /* FIXME */ 26 | } 27 | 28 | static inline unsigned int irq_pending(void) 29 | { 30 | return 0; /* FIXME */ 31 | } 32 | 33 | #ifdef __cplusplus 34 | } 35 | #endif 36 | 37 | #endif /* __IRQ_H */ 38 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/gowin_emcu/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/ibex/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.ibex.core import Ibex 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/ibex/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/ibex/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | /*Reference : https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html# */ 5 | 6 | #define CSR_MSTATUS_MIE 0x8 7 | 8 | #define CSR_IRQ_MASK 0x304 9 | #define CSR_IRQ_PENDING 0x344 10 | #define FIRQ_OFFSET 16 11 | #define CSR_DCACHE_INFO 0xCC0 12 | 13 | 14 | #endif /* CSR_DEFS__H */ 15 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/ibex/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | 11 | static inline unsigned int irq_getie(void) 12 | { 13 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 14 | } 15 | 16 | static inline void irq_setie(unsigned int ie) 17 | { 18 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 19 | } 20 | 21 | static inline unsigned int irq_getmask(void) 22 | { 23 | unsigned int mask; 24 | asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); 25 | return (mask >> FIRQ_OFFSET); 26 | } 27 | 28 | static inline void irq_setmask(unsigned int mask) 29 | { 30 | asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask << FIRQ_OFFSET)); 31 | } 32 | 33 | static inline unsigned int irq_pending(void) 34 | { 35 | unsigned int pending; 36 | asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); 37 | return (pending >> FIRQ_OFFSET); 38 | } 39 | 40 | #ifdef __cplusplus 41 | } 42 | #endif 43 | 44 | #endif /* __IRQ_H */ 45 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/ibex/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | __attribute__((unused)) static void flush_cpu_icache(void) 11 | { 12 | asm volatile( 13 | "fence.i\n" 14 | ); 15 | } 16 | 17 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 18 | void flush_l2_cache(void); 19 | 20 | void busy_wait(unsigned int ms); 21 | void busy_wait_us(unsigned int us); 22 | 23 | #define csrr(reg) ({ unsigned long __tmp; \ 24 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 25 | __tmp; }) 26 | 27 | #define csrw(reg, val) ({ \ 28 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 29 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 30 | else \ 31 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 32 | 33 | #define csrs(reg, bit) ({ \ 34 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 35 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 36 | else \ 37 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 38 | 39 | #define csrc(reg, bit) ({ \ 40 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 41 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 42 | else \ 43 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 44 | 45 | #ifdef __cplusplus 46 | } 47 | #endif 48 | 49 | #endif /* __SYSTEM_H */ 50 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/kianv/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.kianv.core import KianV 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/kianv/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/kianv/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/kianv/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #endif /* __IRQ_H */ 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/kianv/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/lm32/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.lm32.core import LM32 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/lm32/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | call r4 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/lm32/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | static inline unsigned int irq_getie(void) 13 | { 14 | unsigned int ie; 15 | __asm__ __volatile__("rcsr %0, IE" : "=r" (ie)); 16 | return ie; 17 | } 18 | 19 | static inline void irq_setie(unsigned int ie) 20 | { 21 | __asm__ __volatile__("wcsr IE, %0" : : "r" (ie)); 22 | } 23 | 24 | static inline unsigned int irq_getmask(void) 25 | { 26 | unsigned int mask; 27 | __asm__ __volatile__("rcsr %0, IM" : "=r" (mask)); 28 | return mask; 29 | } 30 | 31 | static inline void irq_setmask(unsigned int mask) 32 | { 33 | __asm__ __volatile__("wcsr IM, %0" : : "r" (mask)); 34 | } 35 | 36 | static inline unsigned int irq_pending(void) 37 | { 38 | unsigned int pending; 39 | __asm__ __volatile__("rcsr %0, IP" : "=r" (pending)); 40 | return pending; 41 | } 42 | 43 | #ifdef __cplusplus 44 | } 45 | #endif 46 | 47 | #endif /* __IRQ_H */ 48 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/lm32/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void) 9 | { 10 | asm volatile( 11 | "wcsr ICC, r0\n" 12 | "nop\n" 13 | "nop\n" 14 | "nop\n" 15 | "nop\n" 16 | ); 17 | } 18 | 19 | __attribute__((unused)) static void flush_cpu_dcache(void) 20 | { 21 | asm volatile( 22 | "wcsr DCC, r0\n" 23 | "nop\n" 24 | ); 25 | } 26 | 27 | void flush_l2_cache(void); 28 | 29 | void busy_wait(unsigned int ms); 30 | void busy_wait_us(unsigned int us); 31 | 32 | #ifdef __cplusplus 33 | } 34 | #endif 35 | 36 | #endif /* __SYSTEM_H */ 37 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/marocchino/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.marocchino.core import Marocchino 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/marocchino/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | l.jr r6 5 | l.nop 6 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/marocchino/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | static inline unsigned int irq_getie(void) 13 | { 14 | return !!(mfspr(SPR_SR) & SPR_SR_IEE); 15 | } 16 | 17 | static inline void irq_setie(unsigned int ie) 18 | { 19 | if (ie & 0x1) 20 | mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); 21 | else 22 | mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE); 23 | } 24 | 25 | static inline unsigned int irq_getmask(void) 26 | { 27 | return mfspr(SPR_PICMR); 28 | } 29 | 30 | static inline void irq_setmask(unsigned int mask) 31 | { 32 | mtspr(SPR_PICMR, mask); 33 | } 34 | 35 | static inline unsigned int irq_pending(void) 36 | { 37 | return mfspr(SPR_PICSR); 38 | } 39 | 40 | #ifdef __cplusplus 41 | } 42 | #endif 43 | 44 | #endif /* __IRQ_H */ 45 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/microwatt/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.microwatt.core import Microwatt 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/microwatt/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | // void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) 4 | boot_helper: 5 | mtctr %r6, 6 | bctrl 7 | ba 0 8 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/microwatt/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | static inline void flush_cpu_icache(void) 9 | { 10 | __asm__ volatile ("icbi 0,0; isync" : : : "memory"); 11 | } 12 | static inline void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ 13 | void flush_l2_cache(void); 14 | 15 | void busy_wait(unsigned int ms); 16 | void busy_wait_us(unsigned int us); 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | 22 | #endif /* __SYSTEM_H */ 23 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/minerva/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.minerva.core import Minerva 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/minerva/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/minerva/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/minerva/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_MIE 0x304 7 | #define CSR_MIP 0x344 8 | #define FIRQ_OFFSET 16 9 | 10 | #define CSR_DCACHE_INFO 0xCC0 11 | 12 | #endif /* CSR_DEFS__H */ 13 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/minerva/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | static inline unsigned int irq_getie(void) 13 | { 14 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 15 | } 16 | 17 | static inline void irq_setie(unsigned int ie) 18 | { 19 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 20 | } 21 | 22 | static inline unsigned int irq_getmask(void) 23 | { 24 | unsigned int mask; 25 | asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_MIE)); 26 | return (mask >> FIRQ_OFFSET); 27 | } 28 | 29 | static inline void irq_setmask(unsigned int mask) 30 | { 31 | asm volatile ("csrw %0, %1" :: "i"(CSR_MIE), "r"(mask << FIRQ_OFFSET)); 32 | } 33 | 34 | static inline unsigned int irq_pending(void) 35 | { 36 | unsigned int pending; 37 | asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_MIP)); 38 | return (pending >> FIRQ_OFFSET); 39 | } 40 | 41 | #ifdef __cplusplus 42 | } 43 | #endif 44 | 45 | #endif /* __IRQ_H */ 46 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/minerva/minerva-pep-723.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2025 William D. Jones 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | """PEP-723-aware script for installing Minerva.""" 8 | 9 | # Deps must be kept in sync with Minerva's pyproject.toml. 10 | # /// script 11 | # requires-python = "~=3.8" 12 | # dependencies = [ 13 | # "amaranth[builtin-yosys]<0.6,>=0.5", 14 | # "amaranth_soc @ git+https://github.com/amaranth-lang/amaranth-soc", 15 | # "yowasp-yosys", 16 | # ] 17 | # /// 18 | 19 | import os 20 | import sys 21 | from pathlib import Path 22 | 23 | # Must be run from Minerva's source root. 24 | sys.path += [str(Path(os.getcwd())), str(Path(os.getcwd()) / "minerva")] 25 | 26 | import cli # noqa: E402 27 | 28 | if __name__ == "__main__": 29 | cli.main() 30 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/minerva/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ 10 | void flush_l2_cache(void); 11 | void busy_wait(unsigned int ms); 12 | void busy_wait_us(unsigned int us); 13 | 14 | #include 15 | 16 | #define csrr(reg) ({ unsigned long __tmp; \ 17 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 18 | __tmp; }) 19 | 20 | #define csrw(reg, val) ({ \ 21 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 22 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 23 | else \ 24 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 25 | 26 | #define csrs(reg, bit) ({ \ 27 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 28 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 29 | else \ 30 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 31 | 32 | #define csrc(reg, bit) ({ \ 33 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 34 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 35 | else \ 36 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 37 | 38 | #ifdef __cplusplus 39 | } 40 | #endif 41 | 42 | #endif /* __SYSTEM_H */ 43 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/mor1kx/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.mor1kx.core import MOR1KX 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/mor1kx/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | l.jr r6 5 | l.nop 6 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/mor1kx/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | static inline unsigned int irq_getie(void) 13 | { 14 | return !!(mfspr(SPR_SR) & SPR_SR_IEE); 15 | } 16 | 17 | static inline void irq_setie(unsigned int ie) 18 | { 19 | if (ie & 0x1) 20 | mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); 21 | else 22 | mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE); 23 | } 24 | 25 | static inline unsigned int irq_getmask(void) 26 | { 27 | return mfspr(SPR_PICMR); 28 | } 29 | 30 | static inline void irq_setmask(unsigned int mask) 31 | { 32 | mtspr(SPR_PICMR, mask); 33 | } 34 | 35 | static inline unsigned int irq_pending(void) 36 | { 37 | return mfspr(SPR_PICSR); 38 | } 39 | 40 | #ifdef __cplusplus 41 | } 42 | #endif 43 | 44 | #endif /* __IRQ_H */ 45 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/naxriscv/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.naxriscv.core import NaxRiscv 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/naxriscv/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | .global smp_lottery_target 4 | .global smp_lottery_lock 5 | .global smp_lottery_args 6 | 7 | boot_helper: 8 | sw x10, smp_lottery_args , x14 9 | sw x11, smp_lottery_args+4, x14 10 | sw x12, smp_lottery_args+8, x14 11 | sw x13, smp_lottery_target, x14 12 | fence w, w 13 | li x15, 1 14 | sw x15, smp_lottery_lock, x14 15 | jr x13 16 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/naxriscv/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_IRQ_MASK 0xBC0 7 | #define CSR_IRQ_PENDING 0xFC0 8 | 9 | #endif /* CSR_DEFS__H */ 10 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/naxriscv/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | // NaxRiscv uses a Platform-Level Interrupt Controller (PLIC) which 13 | // is programmed and queried via a set of MMIO registerss 14 | 15 | #define PLIC_BASE 0xf0c00000L // Base address and per-pin priority array 16 | #define PLIC_PENDING 0xf0c01000L // Bit field matching currently pending pins 17 | #define PLIC_ENABLED 0xf0c02000L // Bit field corresponding to the current mask 18 | #define PLIC_THRSHLD 0xf0e00000L // Per-pin priority must be >= this to trigger 19 | #define PLIC_CLAIM 0xf0e00004L // Claim & completion register address 20 | 21 | #define PLIC_EXT_IRQ_BASE 0 22 | 23 | static inline unsigned int irq_getie(void) 24 | { 25 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 26 | } 27 | 28 | static inline void irq_setie(unsigned int ie) 29 | { 30 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 31 | } 32 | 33 | static inline unsigned int irq_getmask(void) 34 | { 35 | return *((unsigned int *)PLIC_ENABLED) >> PLIC_EXT_IRQ_BASE; 36 | } 37 | 38 | static inline void irq_setmask(unsigned int mask) 39 | { 40 | *((unsigned int *)PLIC_ENABLED) = mask << PLIC_EXT_IRQ_BASE; 41 | } 42 | 43 | static inline unsigned int irq_pending(void) 44 | { 45 | return *((unsigned int *)PLIC_PENDING) >> PLIC_EXT_IRQ_BASE; 46 | } 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* __IRQ_H */ 53 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/naxriscv/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | __attribute__((unused)) static void flush_cpu_icache(void) 11 | { 12 | asm volatile( 13 | "fence.i\n" 14 | ); 15 | } 16 | 17 | __attribute__((unused)) static void flush_cpu_dcache(void) 18 | { 19 | asm volatile(".word(0x500F)\n"); 20 | } 21 | 22 | void flush_l2_cache(void); 23 | 24 | void busy_wait(unsigned int ms); 25 | void busy_wait_us(unsigned int us); 26 | 27 | #include 28 | 29 | #define csrr(reg) ({ unsigned long __tmp; \ 30 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 31 | __tmp; }) 32 | 33 | #define csrw(reg, val) ({ \ 34 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 35 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 36 | else \ 37 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 38 | 39 | #define csrs(reg, bit) ({ \ 40 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 41 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 42 | else \ 43 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 44 | 45 | #define csrc(reg, bit) ({ \ 46 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 47 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 48 | else \ 49 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 50 | 51 | #ifdef __cplusplus 52 | } 53 | #endif 54 | 55 | #endif /* __SYSTEM_H */ 56 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/neorv32/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.neorv32.core import NEORV32 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/neorv32/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | .global smp_lottery_target 4 | .global smp_lottery_lock 5 | .global smp_lottery_args 6 | 7 | boot_helper: 8 | sw x10, smp_lottery_args , x14 9 | sw x11, smp_lottery_args+4, x14 10 | sw x12, smp_lottery_args+8, x14 11 | sw x13, smp_lottery_target, x14 12 | fence w, w 13 | fence.i 14 | li x15, 1 15 | sw x15, smp_lottery_lock, x14 16 | jr x13 17 | 18 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/neorv32/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | static inline unsigned int irq_getie(void) { 9 | 10 | unsigned int tmp; 11 | asm volatile ("csrr %0, mstatus" : "=r"(tmp) : ); 12 | 13 | if (tmp & (1<<3)) { /* check mstatus.mie */ 14 | return 1; 15 | } 16 | else { 17 | return 0; 18 | } 19 | } 20 | 21 | static inline void irq_setie(unsigned int ie) { 22 | 23 | if (ie) { 24 | asm volatile ("csrrs zero, mstatus, 1<<3"); /* atomic set mstatus.mie */ 25 | } 26 | else { 27 | asm volatile ("csrrc zero, mstatus, 1<<3"); /* atomic clear mstatus.mie */ 28 | } 29 | } 30 | 31 | static inline unsigned int irq_getmask(void) { 32 | 33 | unsigned int mask; 34 | asm volatile ("csrr %0, mie" : "=r"(mask) : ); 35 | return mask; 36 | } 37 | 38 | static inline void irq_setmask(unsigned int mask) { 39 | 40 | asm volatile ("csrw mie, %0" : : "r"(mask)); 41 | } 42 | 43 | static inline unsigned int irq_pending(void) { 44 | 45 | unsigned int pending; 46 | asm volatile ("csrr %0, mip" : "=r"(pending) : ); 47 | return pending; 48 | } 49 | 50 | #ifdef __cplusplus 51 | } 52 | #endif 53 | 54 | #endif /* __IRQ_H */ 55 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/neorv32/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void) 9 | { 10 | asm volatile ("fence.i"); 11 | } 12 | 13 | __attribute__((unused)) static void flush_cpu_dcache(void) 14 | { 15 | asm volatile ("fence"); /* No data cache yet */ 16 | } 17 | 18 | void flush_l2_cache(void); 19 | 20 | void busy_wait(unsigned int ms); 21 | void busy_wait_us(unsigned int us); 22 | 23 | #ifdef __cplusplus 24 | } 25 | #endif 26 | 27 | #endif /* __SYSTEM_H */ 28 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/openc906/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.openc906.core import OpenC906 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/openc906/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/openc906/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_MXSTATUS 0x7C0 7 | #define CSR_MXSTATUS_THEADISAEE (1 << 22) 8 | #define CSR_MHCR 0x7C1 9 | #define CSR_MHCR_IE (1 << 0) 10 | #define CSR_MHCR_DE (1 << 1) 11 | #define CSR_MHCR_BPE (1 << 5) 12 | #define CSR_MHCR_BTB (1 << 6) 13 | #define CSR_MCOR 0x7C2 14 | #define CSR_MCOR_CACHE_SEL_I (1 << 0) 15 | #define CSR_MCOR_CACHE_SEL_D (1 << 1) 16 | #define CSR_MCOR_INV (1 << 4) 17 | #define CSR_MCOR_CLR (1 << 5) 18 | #define CSR_MCOR_BHT_INV (1 << 16) 19 | #define CSR_MCOR_BTB_INV (1 << 17) 20 | 21 | #endif /* CSR_DEFS__H */ 22 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/openc906/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | // The C906 core uses a Platform-Level Interrupt Controller (PLIC) which 13 | // is programmed and queried via a set of MMIO registers. 14 | 15 | #define PLIC_BASE 0x90000000L // Base address and per-pin priority array 16 | #define PLIC_PENDING 0x90001000L // Bit field matching currently pending pins 17 | #define PLIC_ENABLED 0x90002000L // Bit field corresponding to the current mask 18 | #define PLIC_THRSHLD 0x90200000L // Per-pin priority must be >= this to trigger 19 | #define PLIC_CLAIM 0x90200004L // Claim & completion register address 20 | 21 | #define PLIC_EXT_IRQ_BASE 16 22 | 23 | static inline unsigned int irq_getie(void) 24 | { 25 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 26 | } 27 | 28 | static inline void irq_setie(unsigned int ie) 29 | { 30 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 31 | } 32 | 33 | static inline unsigned int irq_getmask(void) 34 | { 35 | return *((unsigned int *)PLIC_ENABLED) >> 16; 36 | } 37 | 38 | static inline void irq_setmask(unsigned int mask) 39 | { 40 | *((unsigned int *)PLIC_ENABLED) = mask << 16; 41 | } 42 | 43 | static inline unsigned int irq_pending(void) 44 | { 45 | return *((unsigned int *)PLIC_PENDING) >> 16; 46 | } 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* __IRQ_H */ 53 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/openc906/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | void flush_l2_cache(void); 9 | 10 | void busy_wait(unsigned int ms); 11 | void busy_wait_us(unsigned int us); 12 | 13 | #include 14 | 15 | #define csrr(reg) ({ unsigned long __tmp; \ 16 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 17 | __tmp; }) 18 | 19 | #define csrw(reg, val) ({ \ 20 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 21 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 22 | else \ 23 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 24 | 25 | #define csrs(reg, bit) ({ \ 26 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 27 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 28 | else \ 29 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 30 | 31 | #define csrc(reg, bit) ({ \ 32 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 33 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 34 | else \ 35 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 36 | 37 | __attribute__((unused)) static void flush_cpu_icache(void) { 38 | asm volatile (".long 0x0100000b"); /* icache.iall */ 39 | asm volatile (".long 0x01a0000b"); /* sync.i */ 40 | }; 41 | 42 | __attribute__((unused)) static void flush_cpu_dcache(void) { 43 | asm volatile (".long 0x0030000b"); /* dcache.ciall */ 44 | asm volatile (".long 0x01a0000b"); /* sync.i */ 45 | }; 46 | 47 | #ifdef __cplusplus 48 | } 49 | #endif 50 | 51 | #endif /* __SYSTEM_H */ 52 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/picorv32/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.picorv32.core import PicoRV32 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/picorv32/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/picorv32/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/rocket/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.rocket.core import Rocket 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/rocket/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | .global smp_ap_args 4 | .global smp_ap_target 5 | .global smp_ap_ready 6 | 7 | boot_helper: 8 | // boot core saves args and jump target for ap cores: 9 | sd a0, smp_ap_args, t1 10 | sd a1, smp_ap_args+8, t1 11 | sd a2, smp_ap_args+16, t1 12 | sd a3, smp_ap_target, t1 13 | fence w, w 14 | // notify application cores to proceed with boot: 15 | li t0, 1 16 | sd t0, smp_ap_ready, t1 17 | // boot core now also ready to boot: 18 | jr a3 19 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/rocket/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_DCACHE_INFO 0xCC0 7 | 8 | #endif /* CSR_DEFS__H */ 9 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/rocket/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | // The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which 13 | // is programmed and queried via a set of MMIO registers. 14 | 15 | #define PLIC_BASE 0x0c000000L // Base address and per-pin priority array 16 | #define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins 17 | #define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask 18 | #define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger 19 | #define PLIC_CLAIM 0x0c200004L // Claim & completion register address 20 | 21 | #define PLIC_EXT_IRQ_BASE 1 22 | 23 | static inline unsigned int irq_getie(void) 24 | { 25 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 26 | } 27 | 28 | static inline void irq_setie(unsigned int ie) 29 | { 30 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 31 | } 32 | 33 | static inline unsigned int irq_getmask(void) 34 | { 35 | return *((unsigned int *)PLIC_ENABLED) >> 1; 36 | } 37 | 38 | static inline void irq_setmask(unsigned int mask) 39 | { 40 | *((unsigned int *)PLIC_ENABLED) = mask << 1; 41 | } 42 | 43 | static inline unsigned int irq_pending(void) 44 | { 45 | return *((unsigned int *)PLIC_PENDING) >> 1; 46 | } 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* __IRQ_H */ 53 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/rocket/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){} /* FIXME: do something useful here! */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #include 16 | 17 | #define csrr(reg) ({ unsigned long __tmp; \ 18 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 19 | __tmp; }) 20 | 21 | #define csrw(reg, val) ({ \ 22 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 23 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 24 | else \ 25 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 26 | 27 | #define csrs(reg, bit) ({ \ 28 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 29 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 30 | else \ 31 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 32 | 33 | #define csrc(reg, bit) ({ \ 34 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 35 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 36 | else \ 37 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 38 | 39 | #ifdef __cplusplus 40 | } 41 | #endif 42 | 43 | #endif /* __SYSTEM_H */ 44 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/sentinel/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.sentinel.core import Sentinel 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/sentinel/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/sentinel/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/sentinel/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #endif /* CSR_DEFS__H */ 7 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/sentinel/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | /* Custom interrupt I/O registers. The value of IRQ line to Sentinel is: 13 | (irq_pending() & irq_getmask()) != 0. 14 | 15 | Of course, if MIE is clear, no interrupts will be serviced :). */ 16 | #define INTERRUPT_PEND 0x10L 17 | #define INTERRUPT_MASK 0x14L 18 | 19 | static inline unsigned int irq_getie(void) 20 | { 21 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 22 | } 23 | 24 | static inline void irq_setie(unsigned int ie) 25 | { 26 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 27 | } 28 | 29 | static inline unsigned int irq_getmask(void) 30 | { 31 | return *((unsigned int *)INTERRUPT_MASK); 32 | } 33 | 34 | static inline void irq_setmask(unsigned int mask) 35 | { 36 | *((unsigned int *)INTERRUPT_MASK) = mask; 37 | } 38 | 39 | static inline unsigned int irq_pending(void) { 40 | 41 | return *((unsigned int *)INTERRUPT_PEND); 42 | } 43 | 44 | #ifdef __cplusplus 45 | } 46 | #endif 47 | 48 | #endif /* __IRQ_H */ 49 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/sentinel/sentinel-pep-723.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2025 William D. Jones 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | """PEP-723-aware script for installing Sentinel.""" 8 | 9 | # Deps must be kept in sync with Sentinel's pyproject.toml. 10 | # /// script 11 | # requires-python = ">=3.11" 12 | # dependencies = [ 13 | # "m5meta>=1.0.4", 14 | # "m5pre>=1.0.3", 15 | # "amaranth[builtin-yosys]>=0.5.4", 16 | # "amaranth-soc @ git+https://github.com/amaranth-lang/amaranth-soc", 17 | # ] 18 | # /// 19 | 20 | import os 21 | import sys 22 | from pathlib import Path 23 | 24 | sys.path += [str(Path(os.getcwd()) / "src")] 25 | 26 | import sentinel.gen # noqa: E402 27 | 28 | if __name__ == "__main__": 29 | sentinel.gen._main() 30 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/sentinel/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ 10 | void flush_l2_cache(void); 11 | void busy_wait(unsigned int ms); 12 | void busy_wait_us(unsigned int us); 13 | 14 | #include 15 | 16 | #define csrr(reg) ({ unsigned long __tmp; \ 17 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 18 | __tmp; }) 19 | 20 | #define csrw(reg, val) ({ \ 21 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 22 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 23 | else \ 24 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 25 | 26 | #define csrs(reg, bit) ({ \ 27 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 28 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 29 | else \ 30 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 31 | 32 | #define csrc(reg, bit) ({ \ 33 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 34 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 35 | else \ 36 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 37 | 38 | #ifdef __cplusplus 39 | } 40 | #endif 41 | 42 | #endif /* __SYSTEM_H */ 43 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/serv/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.serv.core import SERV 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/serv/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/serv/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/serv/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #endif /* __IRQ_H */ 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/serv/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/urv/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.urv.core import uRV 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/urv/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/urv/crt0.S: -------------------------------------------------------------------------------- 1 | #define MIE_MEIE 0x800 2 | 3 | .global _start 4 | _start: 5 | j reset_vector 6 | 7 | reset_vector: 8 | la sp, _fstack 9 | la t0, trap_vector 10 | csrw mtvec, t0 11 | 12 | // initialize .data 13 | la t0, _fdata 14 | la t1, _edata 15 | la t2, _fdata_rom 16 | 1: beq t0, t1, 2f 17 | lw t3, 0(t2) 18 | sw t3, 0(t0) 19 | addi t0, t0, 4 20 | addi t2, t2, 4 21 | j 1b 22 | 2: 23 | 24 | // initialize .bss 25 | la t0, _fbss 26 | la t1, _ebss 27 | 1: beq t0, t1, 3f 28 | sw zero, 0(t0) 29 | addi t0, t0, 4 30 | j 1b 31 | 3: 32 | // enable external interrupts 33 | li t0, MIE_MEIE 34 | csrs mie, t0 35 | 36 | call main 37 | 1: j 1b 38 | 39 | trap_vector: 40 | addi sp, sp, -16*4 41 | sw ra, 0*4(sp) 42 | sw t0, 1*4(sp) 43 | sw t1, 2*4(sp) 44 | sw t2, 3*4(sp) 45 | sw a0, 4*4(sp) 46 | sw a1, 5*4(sp) 47 | sw a2, 6*4(sp) 48 | sw a3, 7*4(sp) 49 | sw a4, 8*4(sp) 50 | sw a5, 9*4(sp) 51 | sw a6, 10*4(sp) 52 | sw a7, 11*4(sp) 53 | sw t3, 12*4(sp) 54 | sw t4, 13*4(sp) 55 | sw t5, 14*4(sp) 56 | sw t6, 15*4(sp) 57 | call isr 58 | lw ra, 0*4(sp) 59 | lw t0, 1*4(sp) 60 | lw t1, 2*4(sp) 61 | lw t2, 3*4(sp) 62 | lw a0, 4*4(sp) 63 | lw a1, 5*4(sp) 64 | lw a2, 6*4(sp) 65 | lw a3, 7*4(sp) 66 | lw a4, 8*4(sp) 67 | lw a5, 9*4(sp) 68 | lw a6, 10*4(sp) 69 | lw a7, 11*4(sp) 70 | lw t3, 12*4(sp) 71 | lw t4, 13*4(sp) 72 | lw t5, 14*4(sp) 73 | lw t6, 15*4(sp) 74 | addi sp, sp, 16*4 75 | mret 76 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/urv/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #endif /* __IRQ_H */ 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/urv/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | __attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ 9 | __attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ 10 | void flush_l2_cache(void); 11 | 12 | void busy_wait(unsigned int ms); 13 | void busy_wait_us(unsigned int us); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __SYSTEM_H */ 20 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexiiriscv/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.vexiiriscv.core import VexiiRiscv 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexiiriscv/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | .global smp_lottery_target 4 | .global smp_lottery_lock 5 | .global smp_lottery_args 6 | 7 | boot_helper: 8 | sw x10, smp_lottery_args , x14 9 | sw x11, smp_lottery_args+4, x14 10 | sw x12, smp_lottery_args+8, x14 11 | sw x13, smp_lottery_target, x14 12 | fence w, w 13 | li x15, 1 14 | sw x15, smp_lottery_lock, x14 15 | jr x13 16 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexiiriscv/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_IRQ_MASK 0xBC0 7 | #define CSR_IRQ_PENDING 0xFC0 8 | 9 | #endif /* CSR_DEFS__H */ 10 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexiiriscv/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | // VexiiRiscv uses a Platform-Level Interrupt Controller (PLIC) which 13 | // is programmed and queried via a set of MMIO registerss 14 | 15 | #define PLIC_BASE 0xf0c00000L // Base address and per-pin priority array 16 | #define PLIC_PENDING 0xf0c01000L // Bit field matching currently pending pins 17 | #define PLIC_ENABLED 0xf0c02000L // Bit field corresponding to the current mask 18 | #define PLIC_THRSHLD 0xf0e00000L // Per-pin priority must be >= this to trigger 19 | #define PLIC_CLAIM 0xf0e00004L // Claim & completion register address 20 | 21 | #define PLIC_EXT_IRQ_BASE 0 22 | 23 | static inline unsigned int irq_getie(void) 24 | { 25 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 26 | } 27 | 28 | static inline void irq_setie(unsigned int ie) 29 | { 30 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 31 | } 32 | 33 | static inline unsigned int irq_getmask(void) 34 | { 35 | return *((unsigned int *)PLIC_ENABLED) >> PLIC_EXT_IRQ_BASE; 36 | } 37 | 38 | static inline void irq_setmask(unsigned int mask) 39 | { 40 | *((unsigned int *)PLIC_ENABLED) = mask << PLIC_EXT_IRQ_BASE; 41 | } 42 | 43 | static inline unsigned int irq_pending(void) 44 | { 45 | return *((unsigned int *)PLIC_PENDING) >> PLIC_EXT_IRQ_BASE; 46 | } 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* __IRQ_H */ 53 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexiiriscv/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | __attribute__((unused)) static void flush_cpu_icache(void) 11 | { 12 | asm volatile( 13 | "fence.i\n" 14 | ); 15 | } 16 | 17 | __attribute__((unused)) static void flush_cpu_dcache(void) 18 | { 19 | //asm volatile(".word(0x500F)\n"); 20 | } 21 | 22 | void flush_l2_cache(void); 23 | 24 | void busy_wait(unsigned int ms); 25 | void busy_wait_us(unsigned int us); 26 | 27 | #include 28 | 29 | #define csrr(reg) ({ unsigned long __tmp; \ 30 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 31 | __tmp; }) 32 | 33 | #define csrw(reg, val) ({ \ 34 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 35 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 36 | else \ 37 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 38 | 39 | #define csrs(reg, bit) ({ \ 40 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 41 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 42 | else \ 43 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 44 | 45 | #define csrc(reg, bit) ({ \ 46 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 47 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 48 | else \ 49 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 50 | 51 | #ifdef __cplusplus 52 | } 53 | #endif 54 | 55 | #endif /* __SYSTEM_H */ 56 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.vexriscv.core import VexRiscv 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | boot_helper: 4 | jr x13 5 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv/crt0.S: -------------------------------------------------------------------------------- 1 | .global main 2 | .global isr 3 | .global _start 4 | 5 | _start: 6 | j crt_init 7 | nop 8 | nop 9 | nop 10 | nop 11 | nop 12 | nop 13 | nop 14 | 15 | .global trap_entry 16 | trap_entry: 17 | sw x1, - 1*4(sp) 18 | sw x5, - 2*4(sp) 19 | sw x6, - 3*4(sp) 20 | sw x7, - 4*4(sp) 21 | sw x10, - 5*4(sp) 22 | sw x11, - 6*4(sp) 23 | sw x12, - 7*4(sp) 24 | sw x13, - 8*4(sp) 25 | sw x14, - 9*4(sp) 26 | sw x15, -10*4(sp) 27 | sw x16, -11*4(sp) 28 | sw x17, -12*4(sp) 29 | sw x28, -13*4(sp) 30 | sw x29, -14*4(sp) 31 | sw x30, -15*4(sp) 32 | sw x31, -16*4(sp) 33 | addi sp,sp,-16*4 34 | call isr 35 | lw x1 , 15*4(sp) 36 | lw x5, 14*4(sp) 37 | lw x6, 13*4(sp) 38 | lw x7, 12*4(sp) 39 | lw x10, 11*4(sp) 40 | lw x11, 10*4(sp) 41 | lw x12, 9*4(sp) 42 | lw x13, 8*4(sp) 43 | lw x14, 7*4(sp) 44 | lw x15, 6*4(sp) 45 | lw x16, 5*4(sp) 46 | lw x17, 4*4(sp) 47 | lw x28, 3*4(sp) 48 | lw x29, 2*4(sp) 49 | lw x30, 1*4(sp) 50 | lw x31, 0*4(sp) 51 | addi sp,sp,16*4 52 | mret 53 | .text 54 | 55 | 56 | crt_init: 57 | la sp, _fstack 58 | la a0, trap_entry 59 | csrw mtvec, a0 60 | 61 | data_init: 62 | la a0, _fdata 63 | la a1, _edata 64 | la a2, _fdata_rom 65 | data_loop: 66 | beq a0,a1,data_done 67 | lw a3,0(a2) 68 | sw a3,0(a0) 69 | add a0,a0,4 70 | add a2,a2,4 71 | j data_loop 72 | data_done: 73 | 74 | bss_init: 75 | la a0, _fbss 76 | la a1, _ebss 77 | bss_loop: 78 | beq a0,a1,bss_done 79 | sw zero,0(a0) 80 | add a0,a0,4 81 | j bss_loop 82 | bss_done: 83 | 84 | li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt) 85 | csrw mie,a0 86 | 87 | call main 88 | infinit_loop: 89 | j infinit_loop 90 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_IRQ_MASK 0xBC0 7 | #define CSR_IRQ_PENDING 0xFC0 8 | 9 | #define CSR_DCACHE_INFO 0xCC0 10 | 11 | #endif /* CSR_DEFS__H */ 12 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | static inline unsigned int irq_getie(void) 13 | { 14 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 15 | } 16 | 17 | static inline void irq_setie(unsigned int ie) 18 | { 19 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 20 | } 21 | 22 | static inline unsigned int irq_getmask(void) 23 | { 24 | unsigned int mask; 25 | asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); 26 | return mask; 27 | } 28 | 29 | static inline void irq_setmask(unsigned int mask) 30 | { 31 | asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); 32 | } 33 | 34 | static inline unsigned int irq_pending(void) 35 | { 36 | unsigned int pending; 37 | asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); 38 | return pending; 39 | } 40 | 41 | #ifdef __cplusplus 42 | } 43 | #endif 44 | 45 | #endif /* __IRQ_H */ 46 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #include 5 | 6 | #include 7 | 8 | #ifdef __cplusplus 9 | extern "C" { 10 | #endif 11 | 12 | __attribute__((unused)) static void flush_cpu_icache(void) 13 | { 14 | #if defined(CONFIG_CPU_HAS_ICACHE) 15 | asm volatile( 16 | ".word(0x100F)\n" 17 | "nop\n" 18 | "nop\n" 19 | "nop\n" 20 | "nop\n" 21 | "nop\n" 22 | ); 23 | #endif 24 | } 25 | 26 | __attribute__((unused)) static void flush_cpu_dcache(void) 27 | { 28 | #if defined(CONFIG_CPU_HAS_DCACHE) 29 | asm volatile(".word(0x500F)\n"); 30 | #endif 31 | } 32 | 33 | void flush_l2_cache(void); 34 | 35 | void busy_wait(unsigned int ms); 36 | void busy_wait_us(unsigned int us); 37 | 38 | #define csrr(reg) ({ unsigned long __tmp; \ 39 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 40 | __tmp; }) 41 | 42 | #define csrw(reg, val) ({ \ 43 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 44 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 45 | else \ 46 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 47 | 48 | #define csrs(reg, bit) ({ \ 49 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 50 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 51 | else \ 52 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 53 | 54 | #define csrc(reg, bit) ({ \ 55 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 56 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 57 | else \ 58 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* __SYSTEM_H */ 65 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv_smp/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.vexriscv_smp.core import VexRiscvSMP 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv_smp/boot-helper.S: -------------------------------------------------------------------------------- 1 | .section .text, "ax", @progbits 2 | .global boot_helper 3 | .global smp_lottery_target 4 | .global smp_lottery_lock 5 | .global smp_lottery_args 6 | 7 | boot_helper: 8 | sw x10, smp_lottery_args , x14 9 | sw x11, smp_lottery_args+4, x14 10 | sw x12, smp_lottery_args+8, x14 11 | sw x13, smp_lottery_target, x14 12 | fence w, w 13 | li x15, 1 14 | sw x15, smp_lottery_lock, x14 15 | jr x13 16 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv_smp/csr-defs.h: -------------------------------------------------------------------------------- 1 | #ifndef CSR_DEFS__H 2 | #define CSR_DEFS__H 3 | 4 | #define CSR_MSTATUS_MIE 0x8 5 | 6 | #define CSR_IRQ_MASK 0xBC0 7 | #define CSR_IRQ_PENDING 0xFC0 8 | 9 | #define CSR_DCACHE_INFO 0xCC0 10 | 11 | #endif /* CSR_DEFS__H */ 12 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv_smp/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | // VexRiscv-SMP uses a Platform-Level Interrupt Controller (PLIC) which 13 | // is programmed and queried via a set of MMIO registerss 14 | 15 | #define PLIC_BASE 0xf0c00000L // Base address and per-pin priority array 16 | #define PLIC_PENDING 0xf0c01000L // Bit field matching currently pending pins 17 | #define PLIC_ENABLED 0xf0c02000L // Bit field corresponding to the current mask 18 | #define PLIC_THRSHLD 0xf0e00000L // Per-pin priority must be >= this to trigger 19 | #define PLIC_CLAIM 0xf0e00004L // Claim & completion register address 20 | 21 | #define PLIC_EXT_IRQ_BASE 0 22 | 23 | static inline unsigned int irq_getie(void) 24 | { 25 | return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; 26 | } 27 | 28 | static inline void irq_setie(unsigned int ie) 29 | { 30 | if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); 31 | } 32 | 33 | static inline unsigned int irq_getmask(void) 34 | { 35 | return *((unsigned int *)PLIC_ENABLED) >> PLIC_EXT_IRQ_BASE; 36 | } 37 | 38 | static inline void irq_setmask(unsigned int mask) 39 | { 40 | *((unsigned int *)PLIC_ENABLED) = mask << PLIC_EXT_IRQ_BASE; 41 | } 42 | 43 | static inline unsigned int irq_pending(void) 44 | { 45 | return *((unsigned int *)PLIC_PENDING) >> PLIC_EXT_IRQ_BASE; 46 | } 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* __IRQ_H */ 53 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/vexriscv_smp/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | __attribute__((unused)) static void flush_cpu_icache(void) 11 | { 12 | asm volatile( 13 | ".word(0x100F)\n" 14 | "nop\n" 15 | "nop\n" 16 | "nop\n" 17 | "nop\n" 18 | "nop\n" 19 | ); 20 | } 21 | 22 | __attribute__((unused)) static void flush_cpu_dcache(void) 23 | { 24 | asm volatile(".word(0x500F)\n"); 25 | } 26 | 27 | void flush_l2_cache(void); 28 | 29 | void busy_wait(unsigned int ms); 30 | void busy_wait_us(unsigned int us); 31 | 32 | #include 33 | 34 | #define csrr(reg) ({ unsigned long __tmp; \ 35 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 36 | __tmp; }) 37 | 38 | #define csrw(reg, val) ({ \ 39 | if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 40 | asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 41 | else \ 42 | asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 43 | 44 | #define csrs(reg, bit) ({ \ 45 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 46 | asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ 47 | else \ 48 | asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) 49 | 50 | #define csrc(reg, bit) ({ \ 51 | if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 52 | asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ 53 | else \ 54 | asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) 55 | 56 | #ifdef __cplusplus 57 | } 58 | #endif 59 | 60 | #endif /* __SYSTEM_H */ 61 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynq7000/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.zynq7000.core import Zynq7000 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynq7000/boot-helper.c: -------------------------------------------------------------------------------- 1 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); 2 | 3 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) { 4 | goto *(void*)addr; 5 | } 6 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynq7000/crt0.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/soc/cores/cpu/zynq7000/crt0.S -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynq7000/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | static inline unsigned int irq_getie(void) 9 | { 10 | return 0; /* FIXME */ 11 | } 12 | 13 | static inline void irq_setie(unsigned int ie) 14 | { 15 | /* FIXME */ 16 | } 17 | 18 | static inline unsigned int irq_getmask(void) 19 | { 20 | return 0; /* FIXME */ 21 | } 22 | 23 | static inline void irq_setmask(unsigned int mask) 24 | { 25 | /* FIXME */ 26 | } 27 | 28 | static inline unsigned int irq_pending(void) 29 | { 30 | return 0; /* FIXME */ 31 | } 32 | 33 | #ifdef __cplusplus 34 | } 35 | #endif 36 | 37 | #endif /* __IRQ_H */ 38 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynq7000/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include "xuartps_hw.h" 9 | #include "xil_cache.h" 10 | 11 | __attribute__((unused)) static void flush_cpu_icache(void){}; 12 | 13 | __attribute__((unused)) static void flush_cpu_dcache(void) { 14 | Xil_DCacheFlush(); 15 | }; 16 | 17 | void flush_l2_cache(void); // TODO: use Xil_L2CacheFlush(); ! 18 | 19 | void busy_wait(unsigned int ms); 20 | void busy_wait_us(unsigned int us); 21 | 22 | #define CSR_UART_BASE 23 | #define UART_POLLING 24 | 25 | static inline void uart_rxtx_write(char c) { 26 | XUartPs_WriteReg(STDOUT_BASEADDRESS, XUARTPS_FIFO_OFFSET, (uint32_t) c); 27 | } 28 | 29 | static inline uint8_t uart_rxtx_read(void) { 30 | return XUartPs_ReadReg(STDOUT_BASEADDRESS, XUARTPS_FIFO_OFFSET); 31 | } 32 | 33 | static inline uint8_t uart_txfull_read(void) { 34 | return XUartPs_IsTransmitFull(STDOUT_BASEADDRESS); 35 | } 36 | 37 | static inline uint8_t uart_rxempty_read(void) { 38 | return !XUartPs_IsReceiveData(STDOUT_BASEADDRESS); 39 | } 40 | 41 | static inline void uart_ev_pending_write(uint8_t x) {} 42 | 43 | static inline uint8_t uart_ev_pending_read(void) { 44 | return 0; 45 | } 46 | 47 | static inline void uart_ev_enable_write(uint8_t x) {} 48 | 49 | #ifdef __cplusplus 50 | } 51 | #endif 52 | 53 | #endif /* __SYSTEM_H */ 54 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynqmp/__init__.py: -------------------------------------------------------------------------------- 1 | from litex.soc.cores.cpu.zynqmp.core import ZynqMP 2 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynqmp/boot-helper.c: -------------------------------------------------------------------------------- 1 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); 2 | 3 | void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) { 4 | goto *(void*)addr; 5 | } 6 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynqmp/crt0.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/soc/cores/cpu/zynqmp/crt0.c -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynqmp/irq.h: -------------------------------------------------------------------------------- 1 | #ifndef __IRQ_H 2 | #define __IRQ_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | static inline unsigned int irq_getie(void) 9 | { 10 | return 0; /* FIXME */ 11 | } 12 | 13 | static inline void irq_setie(unsigned int ie) 14 | { 15 | /* FIXME */ 16 | } 17 | 18 | static inline unsigned int irq_getmask(void) 19 | { 20 | return 0; /* FIXME */ 21 | } 22 | 23 | static inline void irq_setmask(unsigned int mask) 24 | { 25 | /* FIXME */ 26 | } 27 | 28 | static inline unsigned int irq_pending(void) 29 | { 30 | return 0; /* FIXME */ 31 | } 32 | 33 | #ifdef __cplusplus 34 | } 35 | #endif 36 | 37 | #endif /* __IRQ_H */ 38 | -------------------------------------------------------------------------------- /litex/soc/cores/cpu/zynqmp/system.h: -------------------------------------------------------------------------------- 1 | #ifndef __SYSTEM_H 2 | #define __SYSTEM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include "xuartps_hw.h" 9 | #include "xil_cache.h" 10 | 11 | __attribute__((unused)) static void flush_cpu_icache(void){}; 12 | 13 | __attribute__((unused)) static void flush_cpu_dcache(void) { 14 | Xil_DCacheFlush(); 15 | }; 16 | 17 | void flush_l2_cache(void); // TODO: use Xil_L2CacheFlush(); ! 18 | 19 | void busy_wait(unsigned int ms); 20 | void busy_wait_us(unsigned int us); 21 | 22 | #define CSR_UART_BASE 23 | #define UART_POLLING 24 | 25 | static inline void uart_rxtx_write(char c) { 26 | XUartPs_WriteReg(STDOUT_BASEADDRESS, XUARTPS_FIFO_OFFSET, (uint32_t) c); 27 | } 28 | 29 | static inline uint8_t uart_rxtx_read(void) { 30 | return XUartPs_ReadReg(STDOUT_BASEADDRESS, XUARTPS_FIFO_OFFSET); 31 | } 32 | 33 | static inline uint8_t uart_txfull_read(void) { 34 | return XUartPs_IsTransmitFull(STDOUT_BASEADDRESS); 35 | } 36 | 37 | static inline uint8_t uart_rxempty_read(void) { 38 | return !XUartPs_IsReceiveData(STDOUT_BASEADDRESS); 39 | } 40 | 41 | static inline void uart_ev_pending_write(uint8_t x) {} 42 | 43 | static inline uint8_t uart_ev_pending_read(void) { 44 | return 0; 45 | } 46 | 47 | static inline void uart_ev_enable_write(uint8_t x) {} 48 | 49 | #ifdef __cplusplus 50 | } 51 | #endif 52 | 53 | #endif /* __SYSTEM_H */ 54 | -------------------------------------------------------------------------------- /litex/soc/cores/identifier.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2013-2015 Sebastien Bourdeauducq 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | from migen import * 8 | 9 | from litex.gen import * 10 | 11 | # Identifier --------------------------------------------------------------------------------------- 12 | 13 | class Identifier(LiteXModule): 14 | def __init__(self, ident): 15 | if "," in ident: 16 | raise ValueError("Identifier string must not contain commas") 17 | contents = list(ident.encode()) 18 | l = len(contents) 19 | if l > 255: 20 | raise ValueError("Identifier string must be 255 characters or less") 21 | contents.append(0) 22 | self.mem = Memory(8, len(contents), init=contents) 23 | 24 | def get_memories(self): 25 | return [(True, self.mem)] 26 | -------------------------------------------------------------------------------- /litex/soc/cores/ram/__init__.py: -------------------------------------------------------------------------------- 1 | # Xilinx 2 | 3 | # Intel 4 | 5 | # Lattice 6 | from litex.soc.cores.ram.lattice_ice40 import Up5kSPRAM 7 | from litex.soc.cores.ram.lattice_nx import NXLRAM 8 | -------------------------------------------------------------------------------- /litex/soc/cores/spi/__init__.py: -------------------------------------------------------------------------------- 1 | # SPI-Master/Slave. 2 | from litex.soc.cores.spi.spi_master import SPIMaster 3 | from litex.soc.cores.spi.spi_slave import SPISlave 4 | 5 | # SPI-Bone. 6 | from litex.soc.cores.spi.spi_bone import SPIBone 7 | -------------------------------------------------------------------------------- /litex/soc/integration/__init__.py: -------------------------------------------------------------------------------- 1 | import sys 2 | from litex.compat import add_compat 3 | add_compat(__name__) 4 | -------------------------------------------------------------------------------- /litex/soc/interconnect/__init__.py: -------------------------------------------------------------------------------- 1 | import sys 2 | from litex.compat import add_compat 3 | add_compat(__name__) 4 | -------------------------------------------------------------------------------- /litex/soc/interconnect/avalon/__init__.py: -------------------------------------------------------------------------------- 1 | # Avalon MM. 2 | from litex.soc.interconnect.avalon.avalon_mm import AvalonMMInterface 3 | from litex.soc.interconnect.avalon.avalon_mm_to_wishbone import AvalonMM2Wishbone 4 | 5 | # Avalon ST. 6 | from litex.soc.interconnect.avalon.avalon_st import Native2AvalonST, AvalonST2Native -------------------------------------------------------------------------------- /litex/soc/interconnect/axi/__init__.py: -------------------------------------------------------------------------------- 1 | # Common. 2 | from litex.soc.interconnect.axi.axi_common import * 3 | 4 | # AXI-Stream. 5 | from litex.soc.interconnect.axi.axi_stream import * 6 | 7 | # AXI-Lite. 8 | from litex.soc.interconnect.axi.axi_lite import * 9 | from litex.soc.interconnect.axi.axi_lite_to_csr import * 10 | from litex.soc.interconnect.axi.axi_lite_to_wishbone import * 11 | 12 | # AXI-Full. 13 | from litex.soc.interconnect.axi.axi_full import * 14 | from litex.soc.interconnect.axi.axi_full_to_axi_lite import * 15 | from litex.soc.interconnect.axi.axi_full_to_wishbone import * 16 | -------------------------------------------------------------------------------- /litex/soc/interconnect/axi/axi_full_to_wishbone.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2018-2023 Florent Kermarrec 5 | # Copyright (c) 2020 Antmicro 6 | # SPDX-License-Identifier: BSD-2-Clause 7 | 8 | """AXI4-Full/Lite support for LiteX""" 9 | 10 | from migen import * 11 | 12 | from litex.gen import * 13 | 14 | from litex.soc.interconnect.axi.axi_common import * 15 | from litex.soc.interconnect.axi.axi_lite import * 16 | from litex.soc.interconnect.axi.axi_full_to_axi_lite import * 17 | from litex.soc.interconnect.axi.axi_lite_to_wishbone import * 18 | 19 | # AXI to Wishbone ---------------------------------------------------------------------------------- 20 | 21 | class AXI2Wishbone(LiteXModule): 22 | def __init__(self, axi, wishbone, base_address=0x00000000): 23 | axi_lite = AXILiteInterface(axi.data_width, axi.address_width) 24 | axi2axi_lite = AXI2AXILite(axi, axi_lite) 25 | axi_lite2wishbone = AXILite2Wishbone(axi_lite, wishbone, base_address) 26 | self.submodules += axi2axi_lite, axi_lite2wishbone 27 | 28 | # Wishbone to AXI ---------------------------------------------------------------------------------- 29 | 30 | class Wishbone2AXI(LiteXModule): 31 | def __init__(self, wishbone, axi, base_address=0x00000000): 32 | axi_lite = AXILiteInterface(axi.data_width, axi.address_width) 33 | wishbone2axi_lite = Wishbone2AXILite(wishbone, axi_lite, base_address) 34 | axi_lite2axi = AXILite2AXI(axi_lite, axi) 35 | self.submodules += wishbone2axi_lite, axi_lite2axi 36 | -------------------------------------------------------------------------------- /litex/soc/interconnect/axi/axi_lite_to_csr.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2018-2022 Florent Kermarrec 5 | # Copyright (c) 2020 Antmicro 6 | # SPDX-License-Identifier: BSD-2-Clause 7 | 8 | """AXI4-Full/Lite support for LiteX""" 9 | 10 | from migen import * 11 | 12 | from litex.gen import * 13 | 14 | from litex.build.generic_platform import * 15 | 16 | from litex.soc.interconnect.axi.axi_common import * 17 | from litex.soc.interconnect.axi.axi_lite import * 18 | 19 | # AXI-Lite to CSR ---------------------------------------------------------------------------------- 20 | 21 | class AXILite2CSR(LiteXModule): 22 | def __init__(self, axi_lite=None, bus_csr=None, register=False): 23 | # TODO: unused register argument 24 | if axi_lite is None: 25 | axi_lite = AXILiteInterface() 26 | if bus_csr is None: 27 | bus_csr = csr_bus.Interface() 28 | 29 | self.axi_lite = axi_lite 30 | self.csr = bus_csr 31 | 32 | assert axi_lite.data_width == bus_csr.data_width 33 | 34 | fsm, comb = axi_lite_to_simple( 35 | axi_lite = self.axi_lite, 36 | port_adr = self.csr.adr, 37 | port_re = self.csr.re, 38 | port_dat_r = self.csr.dat_r, 39 | port_dat_w = self.csr.dat_w, 40 | port_we = self.csr.we) 41 | self.fsm = fsm 42 | self.comb += comb 43 | -------------------------------------------------------------------------------- /litex/soc/software/bios/boot.h: -------------------------------------------------------------------------------- 1 | #ifndef __BOOT_H 2 | #define __BOOT_H 3 | 4 | void set_local_ip(const char * ip_address); 5 | void set_remote_ip(const char * ip_address); 6 | void set_mac_addr(const char * mac_address); 7 | 8 | void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); 9 | int serialboot(void); 10 | void netboot(int nb_params, char **params); 11 | void flashboot(void); 12 | void romboot(void); 13 | void sdcardboot(void); 14 | void sataboot(void); 15 | 16 | #endif /* __BOOT_H */ 17 | -------------------------------------------------------------------------------- /litex/soc/software/bios/command.h: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2020 Franck Jullien 2 | 3 | // SPDX-License-Identifier: BSD-Source-Code 4 | 5 | #ifndef __COMMAND_H__ 6 | #define __COMMAND_H__ 7 | 8 | #define MAX_PARAM 8 9 | 10 | #define HIST_DEPTH 10 /* Used in string list, complete.c */ 11 | 12 | #define SYSTEM_CMDS 0 13 | #define BOOT_CMDS 1 14 | #define MEM_CMDS 2 15 | #define SPIFLASH_CMDS 3 16 | #define I2C_CMDS 4 17 | #define LITEDRAM_CMDS 5 18 | #define LITEETH_CMDS 6 19 | #define LITESDCARD_CMDS 7 20 | #define LITESATA_CMDS 8 21 | #define NB_OF_GROUPS 9 22 | 23 | typedef void (*cmd_handler)(int nb_params, char **params); 24 | 25 | struct command_struct { 26 | void (*func)(int nb_params, char **params); 27 | const char *name; 28 | const char *help; 29 | int group; 30 | }; 31 | 32 | extern struct command_struct *const __bios_cmd_start[]; 33 | extern struct command_struct *const __bios_cmd_end[]; 34 | 35 | #ifdef BIOS_CONSOLE_BIOS_CONSOLE_DISABLE 36 | #define define_command(cmd_name, handler, help_txt, group_id) 37 | #else 38 | #define define_command(cmd_name, handler, help_txt, group_id) \ 39 | struct command_struct s_##cmd_name = { \ 40 | .func = (cmd_handler)handler, \ 41 | .name = #cmd_name, \ 42 | .help = help_txt, \ 43 | .group = group_id, \ 44 | }; \ 45 | const struct command_struct *__bios_cmd_##cmd_name __attribute__((__used__)) \ 46 | __attribute__((__section__(".bios_cmd"))) = &s_##cmd_name 47 | 48 | struct command_struct *command_dispatcher(char *command, int nb_params, char **params); 49 | 50 | #endif 51 | #endif -------------------------------------------------------------------------------- /litex/soc/software/bios/complete.h: -------------------------------------------------------------------------------- 1 | #ifndef __COMPLETE_H__ 2 | #define __COMPLETE_H__ 3 | 4 | int complete(char *instr, char **outstr); 5 | 6 | #endif 7 | -------------------------------------------------------------------------------- /litex/soc/software/bios/helpers.h: -------------------------------------------------------------------------------- 1 | #ifndef __HELPERS_H__ 2 | #define __HELPERS_H__ 3 | 4 | void dump_bytes(unsigned int *ptr, int count, unsigned long addr); 5 | void crcbios(void); 6 | int get_param(char *buf, char **cmd, char **params); 7 | struct command_struct *command_dispatcher(char *command, int nb_params, char **params); 8 | void init_dispatcher(void); 9 | 10 | #endif 11 | -------------------------------------------------------------------------------- /litex/soc/software/bios/init.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | 3 | typedef void (*init_func)(void); 4 | 5 | extern init_func const __bios_init_start[]; 6 | extern init_func const __bios_init_end[]; 7 | 8 | #define define_init_func(f) \ 9 | const init_func __bios_init_##f __attribute__((__used__)) \ 10 | __attribute__((__section__(".bios_init"))) = f 11 | -------------------------------------------------------------------------------- /litex/soc/software/bios/readline_simple.c: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq 2 | // This file is Copyright (c) 2014-2019 Florent Kermarrec 3 | 4 | // SPDX-License-Identifier: BSD-Source-Code 5 | 6 | #include 7 | #include 8 | #include 9 | #include 10 | 11 | #include "readline.h" 12 | 13 | int readline(char *s, int size) 14 | { 15 | static char skip = 0; 16 | char c[2]; 17 | int ptr; 18 | 19 | c[1] = 0; 20 | ptr = 0; 21 | while(1) { 22 | c[0] = getchar(); 23 | if (c[0] == skip) 24 | continue; 25 | skip = 0; 26 | switch(c[0]) { 27 | case 0x7f: 28 | case 0x08: 29 | if(ptr > 0) { 30 | ptr--; 31 | fputs("\x08 \x08", stdout); 32 | } 33 | break; 34 | case 0x07: 35 | break; 36 | case '\r': 37 | skip = '\n'; 38 | s[ptr] = 0x00; 39 | fputs("\n", stdout); 40 | return 0; 41 | case '\n': 42 | skip = '\r'; 43 | s[ptr] = 0x00; 44 | fputs("\n", stdout); 45 | return 0; 46 | default: 47 | fputs(c, stdout); 48 | s[ptr] = c[0]; 49 | ptr++; 50 | break; 51 | } 52 | } 53 | 54 | return 0; 55 | } 56 | 57 | -------------------------------------------------------------------------------- /litex/soc/software/bios/sfl.h: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2012-2015 Sebastien Bourdeauducq 2 | // License: BSD 3 | 4 | #ifndef __SFL_H 5 | #define __SFL_H 6 | 7 | #define SFL_MAGIC_LEN 14 8 | #define SFL_MAGIC_REQ "sL5DdSMmkekro\n" 9 | #define SFL_MAGIC_ACK "z6IHG7cYDID6o\n" 10 | 11 | struct sfl_frame { 12 | unsigned char payload_length; 13 | unsigned char crc[2]; 14 | unsigned char cmd; 15 | unsigned char payload[255]; 16 | } __attribute__((packed)); 17 | 18 | /* General commands */ 19 | #define SFL_CMD_ABORT 0x00 20 | #define SFL_CMD_LOAD 0x01 21 | #define SFL_CMD_JUMP 0x02 22 | 23 | /* Replies */ 24 | #define SFL_ACK_SUCCESS 'K' 25 | #define SFL_ACK_CRCERROR 'C' 26 | #define SFL_ACK_UNKNOWN 'U' 27 | #define SFL_ACK_ERROR 'E' 28 | 29 | #endif /* __SFL_H */ 30 | -------------------------------------------------------------------------------- /litex/soc/software/bios/sim_debug.c: -------------------------------------------------------------------------------- 1 | #include "sim_debug.h" 2 | 3 | #include 4 | #include 5 | 6 | // 0 is used as no marker 7 | #define MAX_N_MARKERS (255 - 1) 8 | 9 | #ifdef CSR_SIM_MARKER_BASE 10 | static int n_markers = 0; 11 | static const char *markers[MAX_N_MARKERS] = {0}; 12 | #endif 13 | 14 | void sim_mark(const char *text) { 15 | #ifdef CSR_SIM_MARKER_BASE 16 | if (text == NULL) { 17 | text = "NO COMMENT"; 18 | } 19 | // 0 is not used 20 | int marker_num = n_markers + 1; 21 | markers[n_markers++] = text; 22 | sim_marker_marker_write(marker_num); 23 | if (n_markers >= MAX_N_MARKERS) { 24 | printf("Max number of markers reached\n"); 25 | n_markers = 0; 26 | } 27 | #else 28 | printf("No sim_marker CSR\n"); 29 | #endif 30 | } 31 | 32 | void sim_markers_summary(void) { 33 | #ifdef CSR_SIM_MARKER_BASE 34 | printf("\nMarkers:\n"); 35 | for (int i = 0; i < n_markers; ++i) { 36 | printf(" %3d: %s\n", i + 1, markers[i]); 37 | } 38 | printf("\n"); 39 | #else 40 | printf("No sim_marker CSR\n"); 41 | #endif 42 | } 43 | 44 | void sim_trace(int on) { 45 | #ifdef CSR_SIM_TRACE_BASE 46 | sim_trace_enable_write(on); 47 | #else 48 | printf("No sim_trace CSR\n"); 49 | #endif 50 | } 51 | 52 | int sim_trace_on(void) { 53 | #ifdef CSR_SIM_TRACE_BASE 54 | return sim_trace_enable_read(); 55 | #else 56 | printf("No sim_trace CSR\n"); 57 | return 0; 58 | #endif 59 | } 60 | 61 | void sim_finish(void) { 62 | #ifdef CSR_SIM_FINISH_BASE 63 | sim_trace(0); 64 | if (n_markers > 0) { 65 | sim_markers_summary(); 66 | } 67 | sim_finish_finish_write(1); 68 | #else 69 | printf("No sim_finish CSR\n"); 70 | #endif 71 | } 72 | -------------------------------------------------------------------------------- /litex/soc/software/bios/sim_debug.h: -------------------------------------------------------------------------------- 1 | #ifndef __SIM_DEBUG_H 2 | #define __SIM_DEBUG_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | // add next marker with given comment 9 | void sim_mark(const char *comment); 10 | #define sim_mark_func() sim_mark(__func__) 11 | // print the summary of markers mapping (number -> comment) 12 | void sim_markers_summary(void); 13 | // enable simulation trace dump 14 | void sim_trace(int on); 15 | // check if trace is on 16 | int sim_trace_on(void); 17 | // finish simulation 18 | void sim_finish(void); 19 | 20 | #ifdef __cplusplus 21 | } 22 | #endif 23 | 24 | #endif 25 | 26 | -------------------------------------------------------------------------------- /litex/soc/software/crcfbigen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # This file is Copyright (c) 2015 Sebastien Bourdeauducq 4 | # This file is Copyright (c) 2018 Dolu1990 5 | # License: BSD 6 | 7 | import argparse 8 | import binascii 9 | 10 | 11 | def insert_crc(i_filename, fbi_mode=False, o_filename=None, little_endian=False): 12 | endian = "little" if little_endian else "big" 13 | 14 | if o_filename is None: 15 | o_filename = i_filename 16 | 17 | with open(i_filename, "rb") as f: 18 | fdata = f.read() 19 | fcrc = binascii.crc32(fdata).to_bytes(4, byteorder=endian) 20 | flength = len(fdata).to_bytes(4, byteorder=endian) 21 | 22 | with open(o_filename, "wb") as f: 23 | if fbi_mode: 24 | f.write(flength) 25 | f.write(fcrc) 26 | f.write(fdata) 27 | else: 28 | f.write(fdata) 29 | f.write(fcrc) 30 | 31 | 32 | def main(): 33 | parser = argparse.ArgumentParser(description="CRC32/Flash Boot Image generator.") 34 | parser.add_argument("input", help="Input file.") 35 | parser.add_argument("-o", "--output", default=None, help="Output file (if not specified, use input file).") 36 | parser.add_argument("-f", "--fbi", default=False, action="store_true", help="Build Flash Boot Image (FBI) file.") 37 | parser.add_argument("-l", "--little", default=False, action="store_true", help="Use little endian to write the CRC32.") 38 | args = parser.parse_args() 39 | insert_crc(args.input, args.fbi, args.output, args.little) 40 | 41 | 42 | if __name__ == "__main__": 43 | main() 44 | -------------------------------------------------------------------------------- /litex/soc/software/demo/Makefile: -------------------------------------------------------------------------------- 1 | BUILD_DIR?=../build/ 2 | 3 | include $(BUILD_DIR)/software/include/generated/variables.mak 4 | include $(SOC_DIRECTORY)/software/common.mak 5 | 6 | OBJECTS = donut.o helloc.o crt0.o main.o 7 | ifdef WITH_CXX 8 | OBJECTS += hellocpp.o 9 | CFLAGS += -DWITH_CXX 10 | endif 11 | 12 | 13 | all: demo.bin 14 | 15 | 16 | %.bin: %.elf 17 | $(OBJCOPY) -O binary $< $@ 18 | ifneq ($(OS),Windows_NT) 19 | chmod -x $@ 20 | endif 21 | 22 | vpath %.a $(PACKAGES:%=../%) 23 | 24 | demo.elf: $(OBJECTS) 25 | $(CC) $(LDFLAGS) -T linker.ld -N -o $@ \ 26 | $(OBJECTS) \ 27 | $(PACKAGES:%=-L$(BUILD_DIR)/software/%) \ 28 | -Wl,--whole-archive \ 29 | -Wl,--gc-sections \ 30 | -Wl,-Map,$@.map \ 31 | $(LIBS:lib%=-l%) 32 | 33 | ifneq ($(OS),Windows_NT) 34 | chmod -x $@ 35 | endif 36 | 37 | # pull in dependency info for *existing* .o files 38 | -include $(OBJECTS:.o=.d) 39 | 40 | donut.o: CFLAGS += -w 41 | 42 | VPATH = $(BIOS_DIRECTORY):$(BIOS_DIRECTORY)/cmds:$(CPU_DIRECTORY) 43 | 44 | 45 | %.o: %.cpp 46 | $(compilexx) 47 | 48 | %.o: %.c 49 | $(compile) 50 | 51 | %.o: %.S 52 | $(assemble) 53 | 54 | clean: 55 | $(RM) $(OBJECTS) demo.elf demo.bin .*~ *~ 56 | 57 | .PHONY: all clean 58 | -------------------------------------------------------------------------------- /litex/soc/software/demo/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/soc/software/demo/__init__.py -------------------------------------------------------------------------------- /litex/soc/software/demo/demo.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # 4 | # This file is part of LiteX. 5 | # 6 | # Copyright (c) 2020-2022 Florent Kermarrec 7 | # SPDX-License-Identifier: BSD-2-Clause 8 | 9 | import os 10 | import sys 11 | import argparse 12 | 13 | from litex.build.tools import replace_in_file 14 | 15 | def main(): 16 | parser = argparse.ArgumentParser(description="LiteX Bare Metal Demo App.") 17 | parser.add_argument("--build-path", help="Target's build path (ex build/board_name).", required=True) 18 | parser.add_argument("--with-cxx", action="store_true", help="Enable CXX support.") 19 | parser.add_argument("--mem", default="main_ram", help="Memory Region where code will be loaded/executed.") 20 | args = parser.parse_args() 21 | 22 | # Create demo directory 23 | os.makedirs("demo", exist_ok=True) 24 | 25 | # Copy contents to demo directory 26 | os.system(f"cp {os.path.abspath(os.path.dirname(__file__))}/* demo") 27 | os.system("chmod -R u+w demo") # Nix specific: Allow linker script to be modified. 28 | 29 | # Update memory region. 30 | replace_in_file("demo/linker.ld", "main_ram", args.mem) 31 | 32 | # Compile demo 33 | build_path = args.build_path if os.path.isabs(args.build_path) else os.path.join("..", args.build_path) 34 | os.system(f"export BUILD_DIR={build_path} && {'export WITH_CXX=1 &&' if args.with_cxx else ''} cd demo && make") 35 | 36 | # Copy demo.bin 37 | os.system("cp demo/demo.bin ./") 38 | 39 | # Prepare flash boot image. 40 | python3 = sys.executable or "python3" # Nix specific: Reuse current Python executable if available. 41 | os.system(f"{python3} -m litex.soc.software.crcfbigen demo.bin -o demo.fbi --fbi --little") # FIXME: Endianness. 42 | 43 | if __name__ == "__main__": 44 | main() 45 | 46 | -------------------------------------------------------------------------------- /litex/soc/software/demo/helloc.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | void helloc(void); 4 | void helloc(void) { 5 | printf("C: Hello, world!\n"); 6 | } -------------------------------------------------------------------------------- /litex/soc/software/demo/hellocpp.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | extern "C" void hellocpp(void); 4 | void hellocpp(void) 5 | { 6 | printf("C++: Hello, world!\n"); 7 | } -------------------------------------------------------------------------------- /litex/soc/software/demo/linker.ld: -------------------------------------------------------------------------------- 1 | INCLUDE generated/output_format.ld 2 | ENTRY(_start) 3 | 4 | __DYNAMIC = 0; 5 | 6 | INCLUDE generated/regions.ld 7 | 8 | SECTIONS 9 | { 10 | .text : 11 | { 12 | _ftext = .; 13 | /* Make sure crt0 files come first, and they, and the isr */ 14 | /* don't get disposed of by greedy optimisation */ 15 | *crt0*(.text) 16 | KEEP(*crt0*(.text)) 17 | KEEP(*(.text.isr)) 18 | 19 | *(.text .stub .text.* .gnu.linkonce.t.*) 20 | _etext = .; 21 | } > main_ram 22 | 23 | .rodata : 24 | { 25 | . = ALIGN(8); 26 | _frodata = .; 27 | *(.rodata .rodata.* .gnu.linkonce.r.*) 28 | *(.rodata1) 29 | *(.got .got.*) 30 | *(.toc .toc.*) 31 | . = ALIGN(8); 32 | _erodata = .; 33 | } > main_ram 34 | 35 | .data : 36 | { 37 | . = ALIGN(8); 38 | _fdata = .; 39 | *(.data .data.* .gnu.linkonce.d.*) 40 | *(.data1) 41 | _gp = ALIGN(16); 42 | *(.sdata .sdata.* .gnu.linkonce.s.*) 43 | . = ALIGN(8); 44 | _edata = .; 45 | } > sram AT > main_ram 46 | 47 | .bss : 48 | { 49 | . = ALIGN(8); 50 | _fbss = .; 51 | *(.dynsbss) 52 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 53 | *(.scommon) 54 | *(.dynbss) 55 | *(.bss .bss.* .gnu.linkonce.b.*) 56 | *(COMMON) 57 | . = ALIGN(8); 58 | _ebss = .; 59 | _end = .; 60 | } > sram 61 | } 62 | 63 | PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram)); 64 | 65 | PROVIDE(_fdata_rom = LOADADDR(.data)); 66 | PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data)); 67 | -------------------------------------------------------------------------------- /litex/soc/software/include/irq.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include_next 3 | 4 | typedef void (*isr_t)(void); 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | extern int irq_attach(unsigned int irq, isr_t isr) __attribute__((weak)); 11 | extern int irq_detach(unsigned int irq) __attribute__((weak)); 12 | 13 | #ifdef __cplusplus 14 | } 15 | #endif 16 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | OBJECTS = \ 5 | crc16.o \ 6 | crc32.o \ 7 | console.o \ 8 | system.o \ 9 | progress.o \ 10 | memtest.o \ 11 | uart.o \ 12 | spiflash.o \ 13 | i2c.o \ 14 | isr.o \ 15 | hyperram.o 16 | 17 | all: libbase.a 18 | 19 | libbase.a: $(OBJECTS) 20 | $(AR) crs libbase.a $(OBJECTS) 21 | 22 | # pull in dependency info for *existing* .o files 23 | -include $(OBJECTS:.o=.d) 24 | 25 | %.o: $(LIBBASE_DIRECTORY)/%.c 26 | $(compile) 27 | 28 | .PHONY: all clean 29 | 30 | clean: 31 | $(RM) $(OBJECTS) 32 | $(RM) libbase.a .*~ *~ 33 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/console.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include 5 | 6 | int readchar_nonblock(void) 7 | { 8 | #ifdef CSR_UART_BASE 9 | return uart_read_nonblock(); 10 | #else 11 | return 1; 12 | #endif 13 | } 14 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/console.h: -------------------------------------------------------------------------------- 1 | #ifndef __CONSOLE_H 2 | #define __CONSOLE_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #define readchar getchar 9 | #define putsnonl(X) fputs(X, stdout) 10 | 11 | int readchar_nonblock(void); 12 | 13 | #ifdef __cplusplus 14 | } 15 | #endif 16 | 17 | #endif /* __CONSOLE_H */ 18 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/crc.h: -------------------------------------------------------------------------------- 1 | #ifndef __CRC_H 2 | #define __CRC_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | unsigned short crc16(const unsigned char *buffer, int len); 9 | unsigned int crc32(const unsigned char *buffer, unsigned int len); 10 | 11 | #ifdef __cplusplus 12 | } 13 | #endif 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/i2c.h: -------------------------------------------------------------------------------- 1 | #ifndef __I2C_H 2 | #define __I2C_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | #include 10 | 11 | typedef void (*i2c_write_t)(uint32_t v); 12 | typedef uint32_t (*i2c_read_t)(void); 13 | 14 | struct i2c_ops { 15 | i2c_write_t write; 16 | i2c_read_t read; 17 | int w_scl_offset; 18 | int w_sda_offset; 19 | int w_oe_offset; 20 | }; 21 | 22 | struct i2c_dev { 23 | char *name; 24 | struct i2c_ops ops; 25 | }; 26 | 27 | /* I2C frequency defaults to a safe value in range 10-100 kHz to be compatible with SMBus */ 28 | #ifndef I2C_FREQ_HZ 29 | #define I2C_FREQ_HZ 50000 30 | #endif 31 | 32 | #define I2C_ADDR_WR(addr) ((addr) << 1) 33 | #define I2C_ADDR_RD(addr) (((addr) << 1) | 1u) 34 | 35 | void i2c_reset(void); 36 | bool i2c_write(unsigned char slave_addr, unsigned int addr, const unsigned char *data, unsigned int len, unsigned int addr_size); 37 | bool i2c_read(unsigned char slave_addr, unsigned int addr, unsigned char *data, unsigned int len, bool send_stop, unsigned int addr_size); 38 | bool i2c_poll(unsigned char slave_addr); 39 | int i2c_send_init_cmds(void); 40 | struct i2c_dev *get_i2c_devs(void); 41 | int get_i2c_devs_count(void); 42 | void set_i2c_active_dev(int dev); 43 | int get_i2c_active_dev(void); 44 | 45 | #ifdef __cplusplus 46 | } 47 | #endif 48 | 49 | #endif /* __I2C_H */ 50 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/memtest.h: -------------------------------------------------------------------------------- 1 | #ifndef __MEMTEST_H 2 | #define __MEMTEST_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | 10 | #include 11 | #include 12 | 13 | #ifndef MEMTEST_DATA_SIZE 14 | #define MEMTEST_DATA_SIZE (2*1024*1024) 15 | #endif 16 | 17 | // Called when an error is encountered. Can return non-zero to stop the memtest. 18 | // `arg` can be used to pass arbitrary data to the callback via `memtest_config.arg`. 19 | typedef int (*on_error_callback)(unsigned int addr, unsigned int rdata, unsigned int refdata, void *arg); 20 | 21 | // Optional memtest configuration. If NULL, then we default to progress=1, read_only=0. 22 | struct memtest_config { 23 | int show_progress; 24 | int read_only; 25 | on_error_callback on_error; 26 | void *arg; 27 | }; 28 | 29 | int memtest_access(unsigned int *addr); 30 | int memtest_bus(unsigned int *addr, unsigned long size); 31 | int memtest_addr(unsigned int *addr, unsigned long size, int random); 32 | int memtest_data(unsigned int *addr, unsigned long size, int random, struct memtest_config *config); 33 | 34 | void memspeed(unsigned int *addr, unsigned long size, bool read_only, bool random); 35 | int memtest(unsigned int *addr, unsigned long maxsize); 36 | 37 | #ifdef __cplusplus 38 | } 39 | #endif 40 | 41 | #endif /* __MEMTEST_H */ 42 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/progress.c: -------------------------------------------------------------------------------- 1 | /* 2 | * show_progress.c - simple progress bar functions 3 | * 4 | * Copyright (c) 2010 Sascha Hauer , Pengutronix 5 | * 6 | * See file CREDITS for list of people who contributed to this 7 | * project. 8 | * 9 | * This program is free software; you can redistribute it and/or modify 10 | * it under the terms of the GNU General Public License version 2 11 | * as published by the Free Software Foundation. 12 | * 13 | * This program is distributed in the hope that it will be useful, 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | * GNU General Public License for more details. 17 | * 18 | */ 19 | 20 | #include 21 | #include 22 | #include 23 | 24 | #include "progress.h" 25 | 26 | #define FILESIZE_MAX 100000000 27 | #define HASHES_PER_LINE 40 28 | 29 | static int printed; 30 | static int progress_max; 31 | static int spin; 32 | 33 | void show_progress(int now) 34 | { 35 | char spinchr[] = "\\|/-"; 36 | 37 | if (now < 0) { 38 | printf("%c\b", spinchr[spin++ % (sizeof(spinchr) - 1)]); 39 | return; 40 | } 41 | 42 | if (progress_max && progress_max != FILESIZE_MAX) { 43 | uint64_t tmp = (int64_t)now * HASHES_PER_LINE; 44 | now = lldiv(tmp, progress_max).quot; 45 | } 46 | 47 | while (printed < now) { 48 | if (!(printed % HASHES_PER_LINE) && printed) 49 | printf("\n"); 50 | printf("#"); 51 | printed++; 52 | } 53 | } 54 | 55 | void init_progression_bar(int max) 56 | { 57 | printed = 0; 58 | progress_max = max; 59 | spin = 0; 60 | if (progress_max && progress_max != FILESIZE_MAX) 61 | printf("[%*s]\r[", HASHES_PER_LINE, ""); 62 | } 63 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/progress.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | #ifndef __PROGRSS_H 3 | #define __PROGRSS_H 4 | 5 | #ifdef __cplusplus 6 | extern "C" { 7 | #endif 8 | 9 | /* Initialize a progress bar. If max > 0 a one line progress 10 | * bar is printed where 'max' corresponds to 100%. If max == 0 11 | * a multi line progress bar is printed. 12 | */ 13 | void init_progression_bar(int max); 14 | 15 | /* update a progress bar to a new value. If now < 0 then a 16 | * spinner is printed. 17 | */ 18 | void show_progress(int now); 19 | 20 | #ifdef __cplusplus 21 | } 22 | #endif 23 | 24 | #endif /* __PROGRSS_H */ 25 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/spiflash.h: -------------------------------------------------------------------------------- 1 | #ifndef __SPIFLASH_H 2 | #define __SPIFLASH_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | void write_to_flash_page(unsigned int addr, const unsigned char *c, unsigned int len); 9 | void erase_flash_sector(unsigned int addr); 10 | void erase_flash(void); 11 | void write_to_flash(unsigned int addr, const unsigned char *c, unsigned int len); 12 | 13 | #ifdef __cplusplus 14 | } 15 | #endif 16 | 17 | #endif /* __SPIFLASH_H */ 18 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/system.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | void flush_l2_cache(void) 8 | { 9 | #ifdef CONFIG_L2_SIZE 10 | unsigned int i; 11 | for(i=0;i<2*CONFIG_L2_SIZE/4;i++) { 12 | ((volatile unsigned int *) MAIN_RAM_BASE)[i]; 13 | } 14 | #endif 15 | } 16 | 17 | void busy_wait(unsigned int ms) 18 | { 19 | timer0_en_write(0); 20 | timer0_reload_write(0); 21 | timer0_load_write(CONFIG_CLOCK_FREQUENCY/1000*ms); 22 | timer0_en_write(1); 23 | timer0_update_value_write(1); 24 | while(timer0_value_read()) timer0_update_value_write(1); 25 | } 26 | 27 | void busy_wait_us(unsigned int us) 28 | { 29 | timer0_en_write(0); 30 | timer0_reload_write(0); 31 | timer0_load_write(CONFIG_CLOCK_FREQUENCY/1000000*us); 32 | timer0_en_write(1); 33 | timer0_update_value_write(1); 34 | while(timer0_value_read()) timer0_update_value_write(1); 35 | } 36 | -------------------------------------------------------------------------------- /litex/soc/software/libbase/uart.h: -------------------------------------------------------------------------------- 1 | #ifndef __UART_H 2 | #define __UART_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #define UART_EV_TX 0x1 9 | #define UART_EV_RX 0x2 10 | 11 | void uart_init(void); 12 | void uart_isr(void); 13 | void uart_sync(void); 14 | 15 | void uart_write(char c); 16 | char uart_read(void); 17 | int uart_read_nonblock(void); 18 | 19 | #ifdef __cplusplus 20 | } 21 | #endif 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /litex/soc/software/libc/arm/meson.build: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/soc/software/libc/arm/meson.build -------------------------------------------------------------------------------- /litex/soc/software/libc/missing.c: -------------------------------------------------------------------------------- 1 | /* This file contains functions that were missing 2 | * during picolibc compilation. They are only stubs 3 | * and should be probably replaced with more 4 | * meaningful versions. 5 | */ 6 | 7 | #include 8 | #include 9 | 10 | int getentropy(void *v, size_t s) { 11 | return -1; 12 | } 13 | 14 | int getpid(void) { 15 | return 1; 16 | } 17 | 18 | void _exit(int code) { 19 | while (1); 20 | } 21 | 22 | int kill(int pid, int name) { 23 | _exit(0); 24 | return 0; 25 | } 26 | 27 | void *_impure_ptr; 28 | -------------------------------------------------------------------------------- /litex/soc/software/libc/stdio.c: -------------------------------------------------------------------------------- 1 | /* 2 | * LiteX stdio support for Picolibc. 3 | * 4 | * More info: picolibc/doc/os.md 5 | */ 6 | 7 | #include 8 | 9 | #include 10 | #include 11 | 12 | #include 13 | 14 | static int 15 | litex_putc(char c, FILE *file) 16 | { 17 | (void) file; /* Not used in this function */ 18 | #ifdef CSR_UART_BASE 19 | uart_write(c); 20 | if (c == '\n') 21 | litex_putc('\r', NULL); 22 | #endif 23 | return c; 24 | } 25 | 26 | static int 27 | litex_getc(FILE *file) 28 | { 29 | (void) file; /* Not used in this function */ 30 | while(1) { 31 | #ifdef CSR_UART_BASE 32 | if(uart_read_nonblock()) 33 | return uart_read(); 34 | #endif 35 | } 36 | return -1; 37 | } 38 | 39 | static FILE __stdio = FDEV_SETUP_STREAM(litex_putc, litex_getc, NULL, _FDEV_SETUP_RW); 40 | 41 | FILE *const stdout = &__stdio; 42 | FILE *const stderr = &__stdio; 43 | FILE *const stdin = &__stdio; 44 | -------------------------------------------------------------------------------- /litex/soc/software/libcompiler_rt/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | CFLAGS += -Wno-missing-prototypes 5 | 6 | ifeq ($(CPUENDIANNESS),big) 7 | CFLAGS+=-D_YUGA_LITTLE_ENDIAN=0 -D_YUGA_BIG_ENDIAN=1 8 | else 9 | CFLAGS+=-D_YUGA_LITTLE_ENDIAN=1 -D_YUGA_BIG_ENDIAN=0 10 | endif 11 | 12 | OBJECTS=umodsi3.o udivsi3.o divsi3.o modsi3.o comparesf2.o comparedf2.o negsf2.o negdf2.o addsf3.o subsf3.o mulsf3.o divsf3.o lshrdi3.o muldi3.o divdi3.o ashldi3.o ashrdi3.o udivmoddi4.o \ 13 | floatsisf.o floatunsisf.o fixsfsi.o fixdfdi.o fixunssfsi.o fixunsdfdi.o adddf3.o subdf3.o muldf3.o divdf3.o floatsidf.o floatunsidf.o floatdidf.o fixdfsi.o fixunsdfsi.o \ 14 | clzsi2.o ctzsi2.o udivdi3.o umoddi3.o moddi3.o ucmpdi2.o 15 | 16 | ifeq ($(CPUFAMILY), arm) 17 | OBJECTS += aeabi_uidivmod.o aeabi_idivmod.o udivmodsi4.o divmodsi4.o divmoddi4.o 18 | ifneq ($(CPU), cortex_m1) 19 | OBJECTS += aeabi_div0.o aeabi_uldivmod.o aeabi_ldivmod.o 20 | endif 21 | endif 22 | 23 | all: libcompiler_rt.a 24 | 25 | libcompiler_rt.a: $(OBJECTS) mulsi3.o 26 | $(AR) crs libcompiler_rt.a $(OBJECTS) mulsi3.o 27 | 28 | # pull in dependency info for *existing* .o files 29 | -include $(OBJECTS:.o=.d) 30 | 31 | VPATH = $(SOC_DIRECTORY)/software/libcompiler_rt:$(COMPILER_RT_DIRECTORY)/lib/builtins 32 | 33 | ifeq ($(CPUFAMILY), arm) 34 | VPATH += $(COMPILER_RT_DIRECTORY)/lib/builtins/arm 35 | endif 36 | 37 | %.o: %.c 38 | $(call compile,-fno-lto) 39 | 40 | %.o: %.S 41 | $(call compile,-fno-lto) 42 | 43 | .PHONY: all clean 44 | 45 | clean: 46 | $(RM) $(OBJECTS) $(OBJECTS:.o=.ts) $(OBJECTS:.o=.d) libcompiler_rt.a .*~ *~ 47 | -------------------------------------------------------------------------------- /litex/soc/software/libcompiler_rt/mulsi3.c: -------------------------------------------------------------------------------- 1 | 2 | long 3 | __mulsi3(unsigned long a, unsigned long b) 4 | { 5 | long res = 0; 6 | while (a) 7 | { 8 | if (a & 1) 9 | { 10 | res += b; 11 | } 12 | b <<= 1; 13 | a >>=1; 14 | } 15 | return res; 16 | } -------------------------------------------------------------------------------- /litex/soc/software/libfatfs/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | OBJECTS=ffunicode.o ff.o 5 | 6 | all: libfatfs.a 7 | 8 | libfatfs.a: $(OBJECTS) 9 | $(AR) crs libfatfs.a $(OBJECTS) 10 | 11 | # pull in dependency info for *existing* .o files 12 | -include $(OBJECTS:.o=.d) 13 | 14 | %.o: $(LIBFATFS_DIRECTORY)/%.c 15 | $(compile) 16 | 17 | %.o: %.S 18 | $(assemble) 19 | 20 | .PHONY: all clean 21 | 22 | clean: 23 | $(RM) $(OBJECTS) libfatfs.a .*~ *~ 24 | -------------------------------------------------------------------------------- /litex/soc/software/liblitedram/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | OBJECTS = sdram.o bist.o sdram_dbg.o sdram_spd.o utils.o accessors.o 5 | 6 | all: liblitedram.a 7 | 8 | liblitedram.a: $(OBJECTS) 9 | $(AR) crs liblitedram.a $(OBJECTS) 10 | 11 | # pull in dependency info for *existing* .o files 12 | -include $(OBJECTS:.o=.d) 13 | 14 | %.o: $(LIBLITEDRAM_DIRECTORY)/%.c 15 | $(compile) 16 | 17 | %.o: %.S 18 | $(assemble) 19 | 20 | .PHONY: all clean 21 | 22 | clean: 23 | $(RM) $(OBJECTS) liblitedram.a .*~ *~ 24 | -------------------------------------------------------------------------------- /litex/soc/software/liblitedram/bist.h: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2018-2020 Florent Kermarrec 2 | // License: BSD 3 | 4 | #ifndef __SDRAM_BIST_H 5 | #define __SDRAM_BIST_H 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | 13 | void sdram_bist(uint32_t burst_length, uint32_t random); 14 | int sdram_hw_test(uint64_t origin, uint64_t size, uint64_t burst_length); 15 | 16 | #ifdef __cplusplus 17 | } 18 | #endif 19 | 20 | #endif /* __SDRAM_BIST_H */ 21 | -------------------------------------------------------------------------------- /litex/soc/software/liblitedram/sdram_spd.c: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2023 Antmicro 2 | // License: BSD 3 | 4 | #include 5 | 6 | #if defined(CSR_SDRAM_BASE) && defined(CONFIG_HAS_I2C) 7 | 8 | #if defined(SDRAM_PHY_DDR4) 9 | /* 10 | * In DDR4, addresses 0x36 (SPA0) and 0x37 (SPA1) are used to switch between two 256 byte pages. 11 | */ 12 | static bool sdram_select_spd_page(uint8_t page) { 13 | uint8_t i2c_addr; 14 | 15 | if (page == 0) { 16 | i2c_addr = 0x36; 17 | } else if (page == 1) { 18 | i2c_addr = 0x37; 19 | } else { 20 | return false; 21 | } 22 | 23 | return i2c_poll(i2c_addr); 24 | } 25 | #else 26 | static bool sdram_select_spd_page(uint8_t page) { 27 | return true; 28 | } 29 | #endif 30 | 31 | bool sdram_read_spd(uint8_t spd, uint16_t addr, uint8_t *buf, uint16_t len) { 32 | uint8_t page; 33 | uint16_t offset; 34 | uint16_t temp_len, read_bytes = 0; 35 | 36 | bool ok = true; 37 | 38 | while (addr < SDRAM_SPD_SIZE && len > 0) { 39 | page = addr / SDRAM_SPD_PAGE_SIZE; 40 | ok &= sdram_select_spd_page(page); 41 | 42 | offset = addr % SDRAM_SPD_PAGE_SIZE; 43 | 44 | temp_len = SDRAM_SPD_PAGE_SIZE - offset; 45 | if (temp_len > len) 46 | temp_len = len; 47 | 48 | ok &= i2c_read(SPD_RW_ADDR(spd), offset, &buf[read_bytes], temp_len, false, 1); 49 | len -= temp_len; 50 | read_bytes += temp_len; 51 | addr += temp_len; 52 | } 53 | 54 | return ok; 55 | } 56 | #else /* no CSR_SDRAM_BASE && CONFIG_HAS_I2C */ 57 | bool sdram_read_spd(uint8_t spd, uint16_t addr, uint8_t *buf, uint16_t len) { 58 | return false; 59 | } 60 | #endif /* CSR_SDRAM_BASE && CONFIG_HAS_I2C */ 61 | -------------------------------------------------------------------------------- /litex/soc/software/liblitedram/sdram_spd.h: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2023 Antmicro 2 | // License: BSD 3 | 4 | #ifndef __SDRAM_SPD_H 5 | #define __SDRAM_SPD_H 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | #include 16 | 17 | #if defined(CSR_SDRAM_BASE) && defined(CONFIG_HAS_I2C) 18 | 19 | #include 20 | 21 | #define SPD_RW_PREAMBLE 0b1010 22 | #define SPD_RW_ADDR(a210) ((SPD_RW_PREAMBLE << 3) | ((a210) & 0b111)) 23 | 24 | #if defined(SDRAM_PHY_DDR4) 25 | #define SDRAM_SPD_PAGES 2 26 | #define SDRAM_SPD_PAGE_SIZE 256 27 | #elif defined(SDRAM_PHY_DDR3) 28 | #define SDRAM_SPD_PAGES 1 29 | #define SDRAM_SPD_PAGE_SIZE 256 30 | #else 31 | #define SDRAM_SPD_PAGES 1 32 | #define SDRAM_SPD_PAGE_SIZE 128 33 | #endif 34 | 35 | #define SDRAM_SPD_SIZE (SDRAM_SPD_PAGES * SDRAM_SPD_PAGE_SIZE) 36 | 37 | #endif /* CSR_SDRAM_BASE && CONFIG_HAS_I2C */ 38 | 39 | bool sdram_read_spd(uint8_t spd, uint16_t addr, uint8_t *buf, uint16_t len); 40 | 41 | #ifdef __cplusplus 42 | } 43 | #endif 44 | 45 | #endif /* __SDRAM_SPD_H */ 46 | -------------------------------------------------------------------------------- /litex/soc/software/liblitedram/utils.c: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2023 Antmicro 2 | // License: BSD 3 | 4 | #include 5 | 6 | #include 7 | #include 8 | 9 | #include 10 | 11 | #define KIB 1024 12 | #define MIB (KIB*1024) 13 | #define GIB (MIB*1024) 14 | 15 | void print_size(uint64_t size) { 16 | if (size < KIB) 17 | printf("%" PRIu64 "B", size); 18 | else if (size < MIB) 19 | printf("%" PRIu64 ".%" PRIu64 "KiB", size/KIB, (size/1 - KIB*(size/KIB))/(KIB/10)); 20 | else if (size < GIB) 21 | printf("%" PRIu64 ".%" PRIu64 "MiB", size/MIB, (size/KIB - KIB*(size/MIB))/(KIB/10)); 22 | else 23 | printf("%" PRIu64 ".%" PRIu64 "GiB", size/GIB, (size/MIB - KIB*(size/GIB))/(KIB/10)); 24 | } 25 | 26 | void print_progress(const char * header, uint64_t origin, uint64_t size) 27 | { 28 | printf("%s 0x%" PRIx64 "-0x%" PRIx64 " ", header, origin, origin + size); 29 | print_size(size); 30 | printf(" \r"); 31 | } 32 | 33 | #ifdef CSR_SDRAM_BASE 34 | 35 | #include 36 | 37 | uint64_t sdram_get_supported_memory(void) { 38 | #ifdef CONFIG_HAS_I2C 39 | 40 | #if defined(SDRAM_PHY_DDR3) || defined(SDRAM_PHY_DDR4) 41 | uint8_t buf; 42 | 43 | if (!sdram_read_spd(0x0, 4, &buf, 1)) { 44 | printf("Couldn't read SDRAM size from the SPD, defaulting to 256 MB.\n"); 45 | return 256 << 20; 46 | } 47 | 48 | /* minimal supported is 256 Mb */ 49 | uint64_t single_die_capacity = 256 << 20; 50 | single_die_capacity <<= buf & 0x7; 51 | 52 | /* convert from bits to bytes (divide by 8) */ 53 | single_die_capacity >>= 3; 54 | 55 | return SDRAM_PHY_MODULES * single_die_capacity; 56 | #else 57 | return SDRAM_PHY_SUPPORTED_MEMORY; 58 | #endif 59 | 60 | #else /* no CONFIG_HAS_I2C */ 61 | return SDRAM_PHY_SUPPORTED_MEMORY; 62 | #endif /* CONFIG_HAS_I2C */ 63 | } 64 | 65 | #endif 66 | -------------------------------------------------------------------------------- /litex/soc/software/liblitedram/utils.h: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2023 Antmicro 2 | // License: BSD 3 | 4 | #ifndef __SDRAM_UTILS_H 5 | #define __SDRAM_UTILS_H 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | 13 | void print_size(uint64_t size); 14 | void print_progress(const char * header, uint64_t origin, uint64_t size); 15 | 16 | uint64_t sdram_get_supported_memory(void); 17 | 18 | #ifdef __cplusplus 19 | } 20 | #endif 21 | 22 | #endif /* __SDRAM_UTILS_H */ 23 | -------------------------------------------------------------------------------- /litex/soc/software/libliteeth/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | OBJECTS=udp.o tftp.o mdio.o 5 | 6 | all: libliteeth.a 7 | 8 | libliteeth.a: $(OBJECTS) 9 | $(AR) crs libliteeth.a $(OBJECTS) 10 | 11 | # pull in dependency info for *existing* .o files 12 | -include $(OBJECTS:.o=.d) 13 | 14 | %.o: $(LIBLITEETH_DIRECTORY)/%.c 15 | $(compile) 16 | 17 | %.o: %.S 18 | $(assemble) 19 | 20 | .PHONY: all clean 21 | 22 | clean: 23 | $(RM) $(OBJECTS) libliteeth.a .*~ *~ 24 | -------------------------------------------------------------------------------- /litex/soc/software/libliteeth/mdio.h: -------------------------------------------------------------------------------- 1 | #ifndef __MDIO_H 2 | #define __MDIO_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #define MDIO_CLK 0x01 9 | #define MDIO_OE 0x02 10 | #define MDIO_DO 0x04 11 | 12 | #define MDIO_DI 0x01 13 | 14 | #define MDIO_PREAMBLE 0xffffffff 15 | #define MDIO_START 0x1 16 | #define MDIO_READ 0x2 17 | #define MDIO_WRITE 0x1 18 | #define MDIO_TURN_AROUND 0x2 19 | 20 | void mdio_write(int phyadr, int reg, int val); 21 | int mdio_read(int phyadr, int reg); 22 | 23 | #ifdef __cplusplus 24 | } 25 | #endif 26 | 27 | #endif /* __MDIO_H */ 28 | -------------------------------------------------------------------------------- /litex/soc/software/libliteeth/tftp.h: -------------------------------------------------------------------------------- 1 | #ifndef __TFTP_H 2 | #define __TFTP_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #include 9 | 10 | int tftp_get(uint32_t ip, uint16_t server_port, const char *filename, 11 | void *buffer); 12 | int tftp_put(uint32_t ip, uint16_t server_port, const char *filename, 13 | const void *buffer, int size); 14 | 15 | #ifdef __cplusplus 16 | } 17 | #endif 18 | 19 | #endif /* __TFTP_H */ 20 | 21 | -------------------------------------------------------------------------------- /litex/soc/software/libliteeth/udp.h: -------------------------------------------------------------------------------- 1 | #ifndef __UDP_H 2 | #define __UDP_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #define ETHMAC_EV_SRAM_WRITER 0x1 9 | #define ETHMAC_EV_SRAM_READER 0x1 10 | 11 | #define IPTOINT(a, b, c, d) ((a << 24)|(b << 16)|(c << 8)|d) 12 | 13 | #define UDP_BUFSIZE (5*1532) 14 | 15 | typedef void (*udp_callback)(uint32_t src_ip, uint16_t src_port, uint16_t dst_port, void *data, uint32_t length); 16 | 17 | void udp_set_ip(uint32_t ip); 18 | void udp_set_mac(const uint8_t *macaddr); 19 | void udp_start(const uint8_t *macaddr, uint32_t ip); 20 | int udp_arp_resolve(uint32_t ip); 21 | void *udp_get_tx_buffer(void); 22 | int udp_send(uint16_t src_port, uint16_t dst_port, uint32_t length); 23 | void udp_set_callback(udp_callback callback); 24 | void udp_service(void); 25 | 26 | void eth_init(void); 27 | void eth_mode(void); 28 | 29 | #ifdef __cplusplus 30 | } 31 | #endif 32 | 33 | #endif /* __UDP_H */ 34 | -------------------------------------------------------------------------------- /litex/soc/software/liblitesata/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | OBJECTS=sata.o 5 | 6 | all: liblitesata.a 7 | 8 | liblitesata.a: $(OBJECTS) 9 | $(AR) crs liblitesata.a $(OBJECTS) 10 | 11 | # pull in dependency info for *existing* .o files 12 | -include $(OBJECTS:.o=.d) 13 | 14 | %.o: $(LIBLITESATA_DIRECTORY)/%.c 15 | $(compile) 16 | 17 | %.o: %.S 18 | $(assemble) 19 | 20 | .PHONY: all clean 21 | 22 | clean: 23 | $(RM) $(OBJECTS) liblitesata.a .*~ *~ 24 | -------------------------------------------------------------------------------- /litex/soc/software/liblitesata/sata.h: -------------------------------------------------------------------------------- 1 | // This file is Copyright (c) 2020 Florent Kermarrec 2 | // License: BSD 3 | 4 | #ifndef __SATA_H 5 | #define __SATA_H 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | 13 | /*-----------------------------------------------------------------------*/ 14 | /* SATA user functions */ 15 | /*-----------------------------------------------------------------------*/ 16 | 17 | #ifdef CSR_SATA_PHY_BASE 18 | 19 | int sata_init(int show); 20 | void fatfs_set_ops_sata(void); 21 | 22 | #endif 23 | 24 | #ifdef CSR_SATA_SECTOR2MEM_BASE 25 | 26 | void sata_read(uint32_t sector, uint32_t count, uint8_t* buf); 27 | 28 | #endif 29 | 30 | #ifdef CSR_SATA_MEM2SECTOR_BASE 31 | 32 | void sata_write(uint32_t sector, uint32_t count, uint8_t* buf); 33 | 34 | #endif 35 | 36 | #ifdef __cplusplus 37 | } 38 | #endif 39 | 40 | #endif /* __SATA_H */ 41 | -------------------------------------------------------------------------------- /litex/soc/software/liblitesdcard/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | OBJECTS=sdcard.o spisdcard.o 5 | 6 | all: liblitesdcard.a 7 | 8 | liblitesdcard.a: $(OBJECTS) 9 | $(AR) crs liblitesdcard.a $(OBJECTS) 10 | 11 | # pull in dependency info for *existing* .o files 12 | -include $(OBJECTS:.o=.d) 13 | 14 | %.o: $(LIBLITESDCARD_DIRECTORY)/%.c 15 | $(compile) 16 | 17 | %.o: %.S 18 | $(assemble) 19 | 20 | .PHONY: all clean 21 | 22 | clean: 23 | $(RM) $(OBJECTS) liblitesdcard.a .*~ *~ 24 | -------------------------------------------------------------------------------- /litex/soc/software/liblitespi/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | OBJECTS=spiflash.o spiram.o 5 | 6 | all: liblitespi.a 7 | 8 | liblitespi.a: $(OBJECTS) 9 | $(AR) crs liblitespi.a $(OBJECTS) 10 | 11 | # pull in dependency info for *existing* .o files 12 | -include $(OBJECTS:.o=.d) 13 | 14 | %.o: $(LIBLITESPI_DIRECTORY)/%.c 15 | $(compile) 16 | 17 | %.o: %.S 18 | $(assemble) 19 | 20 | .PHONY: all clean 21 | 22 | clean: 23 | $(RM) $(OBJECTS) liblitespi.a .*~ *~ 24 | -------------------------------------------------------------------------------- /litex/soc/software/liblitespi/spiflash.h: -------------------------------------------------------------------------------- 1 | #ifndef __LITESPI_FLASH_H 2 | #define __LITESPI_FLASH_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | #define SPI_FLASH_BLOCK_SIZE 256 9 | #define CRC32_ERASED_FLASH 0xFEA8A821 10 | 11 | int spiflash_freq_init(void); 12 | void spiflash_dummy_bits_setup(unsigned int dummy_bits); 13 | void spiflash_memspeed(void); 14 | void spiflash_init(void); 15 | int spiflash_write_stream(uint32_t addr, uint8_t *stream, uint32_t len); 16 | void spiflash_erase_range(uint32_t addr, uint32_t len); 17 | void spiflash_erase_4k_sector(uint32_t addr); 18 | 19 | #ifdef __cplusplus 20 | } 21 | #endif 22 | 23 | #endif /* __LITESPI_FLASH_H */ 24 | -------------------------------------------------------------------------------- /litex/soc/software/liblitespi/spiram.h: -------------------------------------------------------------------------------- 1 | #ifndef __LITESPI_SPIRAM_H 2 | #define __LITESPI_SPIRAM_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | int spiram_freq_init(void); 9 | void spiram_dummy_bits_setup(unsigned int dummy_bits); 10 | void spiram_memspeed(void); 11 | void spiram_init(void); 12 | 13 | #ifdef __cplusplus 14 | } 15 | #endif 16 | 17 | #endif /* __LITESPI_SPIRAM_H */ 18 | -------------------------------------------------------------------------------- /litex/soc/software/libxil/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | all: libxil.a 5 | 6 | CFLAGS += -nostartfiles 7 | 8 | OBJECTS = xil_cache.o \ 9 | xil_exception.o \ 10 | asm_vectors.o \ 11 | boot.o \ 12 | translation_table.o \ 13 | xil-crt0.o \ 14 | vectors.o \ 15 | xtime_l.o 16 | 17 | %.o: embeddedsw/lib/bsp/standalone/src/arm/common/%.c 18 | $(compile) 19 | 20 | ifeq ($(CPU), zynqmp) 21 | %.o: embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit/%.c 22 | $(compile) 23 | %.o: embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit/gcc/%.S 24 | $(assemble) 25 | %.o: embeddedsw/lib/bsp/standalone/src/arm/ARMv8/64bit/platform/ZynqMP/gcc/%.S 26 | $(assemble) 27 | 28 | else ifeq ($(CPU), zynq7000) 29 | 30 | OBJECTS += cpu_init.o 31 | 32 | %.o: embeddedsw/lib/bsp/standalone/src/arm/cortexa9/%.c 33 | $(compile) 34 | %.o: embeddedsw/lib/bsp/standalone/src/arm/cortexa9/gcc/%.S 35 | $(assemble) 36 | 37 | endif 38 | 39 | libxil.a: $(OBJECTS) 40 | $(AR) crs $@ $^ 41 | 42 | clean: 43 | $(RM) $(OBJECTS) libxil.a 44 | -------------------------------------------------------------------------------- /litex/tools/__init__.py: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /litex/tools/remote/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/litex/tools/remote/__init__.py -------------------------------------------------------------------------------- /test/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/enjoy-digital/litex/0ee94439ab7776e64bc42fa0b96f4fe069cae434/test/__init__.py -------------------------------------------------------------------------------- /test/test_axi_stream.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2020-2022 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | import unittest 8 | 9 | from migen import * 10 | 11 | from litex.soc.interconnect.axi import AXIStreamInterface 12 | 13 | class TestAXIStream(unittest.TestCase): 14 | def test_axi_stream_syntax(self): 15 | axis = AXIStreamInterface(data_width=32) 16 | axis = AXIStreamInterface(data_width=32, keep_width=4) 17 | axis = AXIStreamInterface(data_width=32, keep_width=4, id_width=4) 18 | axis = AXIStreamInterface(data_width=32, keep_width=4, id_width=4, dest_width=4) 19 | axis = AXIStreamInterface(data_width=32, keep_width=4, id_width=4, dest_width=4, user_width=4) 20 | 21 | def test_axi_stream_get_ios(self): 22 | axis = AXIStreamInterface(data_width=32, keep_width=4, id_width=4, dest_width=4, user_width=4) 23 | pads = axis.get_ios() 24 | -------------------------------------------------------------------------------- /test/test_bitbang.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2019 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | import unittest 8 | 9 | from migen import * 10 | 11 | from litex.soc.cores.bitbang import I2CMaster, SPIMaster 12 | 13 | class TestBitBang(unittest.TestCase): 14 | def test_i2c_master_syntax(self): 15 | i2c_master = I2CMaster() 16 | self.assertEqual(hasattr(i2c_master, "pads"), 1) 17 | i2c_master = I2CMaster(Record(I2CMaster.pads_layout)) 18 | self.assertEqual(hasattr(i2c_master, "pads"), 1) 19 | 20 | def test_spi_master_syntax(self): 21 | spi_master = SPIMaster() 22 | self.assertEqual(hasattr(spi_master, "pads"), 1) 23 | spi_master = SPIMaster(Record(SPIMaster.pads_layout)) 24 | self.assertEqual(hasattr(spi_master, "pads"), 1) 25 | -------------------------------------------------------------------------------- /test/test_i2s.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2020 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | import unittest 8 | 9 | from migen import * 10 | 11 | from litex.soc.cores.i2s import S7I2S 12 | 13 | 14 | class TestI2S(unittest.TestCase): 15 | def test_s7i2sslave_syntax(self): 16 | i2s_pads = Record([("rx", 1), ("tx", 1), ("sync", 1), ("clk", 1)]) 17 | i2s = S7I2S(pads=i2s_pads, fifo_depth=256) 18 | 19 | -------------------------------------------------------------------------------- /test/test_spi_opi.py: -------------------------------------------------------------------------------- 1 | # 2 | # This file is part of LiteX. 3 | # 4 | # Copyright (c) 2020 Florent Kermarrec 5 | # SPDX-License-Identifier: BSD-2-Clause 6 | 7 | import unittest 8 | 9 | from migen import * 10 | 11 | from litex.soc.cores.spi_opi import S7SPIOPI 12 | 13 | 14 | class TestI2S(unittest.TestCase): 15 | def test_s7spiopi_syntax(self): 16 | spi_opi_pads = Record([("dqs", 1), ("dq", 8), ("sclk", 1), ("cs_n", 1), ("ecs_n", 1)]) 17 | spi_opi = S7SPIOPI(pads=spi_opi_pads) 18 | 19 | --------------------------------------------------------------------------------