├── LICENSE
├── README.md
├── demo
├── Drivers
│ ├── CMSIS
│ │ ├── Device
│ │ │ └── ST
│ │ │ │ └── STM32F1xx
│ │ │ │ └── Include
│ │ │ │ ├── stm32f103xb.h
│ │ │ │ ├── stm32f1xx.h
│ │ │ │ └── system_stm32f1xx.h
│ │ └── Include
│ │ │ ├── cmsis_armcc.h
│ │ │ ├── cmsis_armclang.h
│ │ │ ├── cmsis_compiler.h
│ │ │ ├── cmsis_gcc.h
│ │ │ ├── cmsis_iccarm.h
│ │ │ ├── cmsis_version.h
│ │ │ ├── core_armv8mbl.h
│ │ │ ├── core_armv8mml.h
│ │ │ ├── core_cm0.h
│ │ │ ├── core_cm0plus.h
│ │ │ ├── core_cm1.h
│ │ │ ├── core_cm23.h
│ │ │ ├── core_cm3.h
│ │ │ ├── core_cm33.h
│ │ │ ├── core_cm4.h
│ │ │ ├── core_cm7.h
│ │ │ ├── core_sc000.h
│ │ │ ├── core_sc300.h
│ │ │ ├── mpu_armv7.h
│ │ │ ├── mpu_armv8.h
│ │ │ └── tz_context.h
│ └── STM32F1xx_HAL_Driver
│ │ ├── Inc
│ │ ├── Legacy
│ │ │ └── stm32_hal_legacy.h
│ │ ├── stm32f1xx_hal.h
│ │ ├── stm32f1xx_hal_cortex.h
│ │ ├── stm32f1xx_hal_def.h
│ │ ├── stm32f1xx_hal_dma.h
│ │ ├── stm32f1xx_hal_dma_ex.h
│ │ ├── stm32f1xx_hal_exti.h
│ │ ├── stm32f1xx_hal_flash.h
│ │ ├── stm32f1xx_hal_flash_ex.h
│ │ ├── stm32f1xx_hal_gpio.h
│ │ ├── stm32f1xx_hal_gpio_ex.h
│ │ ├── stm32f1xx_hal_pwr.h
│ │ ├── stm32f1xx_hal_rcc.h
│ │ ├── stm32f1xx_hal_rcc_ex.h
│ │ ├── stm32f1xx_hal_tim.h
│ │ ├── stm32f1xx_hal_tim_ex.h
│ │ └── stm32f1xx_hal_uart.h
│ │ └── Src
│ │ ├── stm32f1xx_hal.c
│ │ ├── stm32f1xx_hal_cortex.c
│ │ ├── stm32f1xx_hal_dma.c
│ │ ├── stm32f1xx_hal_exti.c
│ │ ├── stm32f1xx_hal_flash.c
│ │ ├── stm32f1xx_hal_flash_ex.c
│ │ ├── stm32f1xx_hal_gpio.c
│ │ ├── stm32f1xx_hal_gpio_ex.c
│ │ ├── stm32f1xx_hal_pwr.c
│ │ ├── stm32f1xx_hal_rcc.c
│ │ ├── stm32f1xx_hal_rcc_ex.c
│ │ ├── stm32f1xx_hal_tim.c
│ │ ├── stm32f1xx_hal_tim_ex.c
│ │ └── stm32f1xx_hal_uart.c
├── Inc
│ ├── main.h
│ ├── stm32f1xx_hal_conf.h
│ └── stm32f1xx_it.h
├── MDK-ARM
│ ├── eeprom_test.uvprojx
│ └── startup_stm32f103xb.s
├── Src
│ ├── main.c
│ ├── stm32f1xx_hal_msp.c
│ ├── stm32f1xx_it.c
│ └── system_stm32f1xx.c
└── eeprom_test.ioc
├── eeprom_in_flash.c
├── eeprom_in_flash.h
└── eeprom_port
├── eeprom_port_ch32v1.c
├── eeprom_port_gd32f1.c
└── eeprom_port_stm32f1.c
/LICENSE:
--------------------------------------------------------------------------------
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/README.md:
--------------------------------------------------------------------------------
1 | # eeprom in flash
2 |
3 | #### 介绍
4 | 本代码实现了简易的flash模拟eeprom功能，只需实现底层的flash操作接口，就可以在顶层调用eeprom接口使用。适合存储eeprom数据量较少的项目使用
5 |
6 | #### 原理
7 | 将提供给eeprom使用的flash空间分为两个分区，每个分区可包含多个擦除页，擦除时统一擦除。当前使用哪一个分区由开始的USED_MARK决定，实际数据和eeprom虚拟地址共同组成一个编程单元，写入时新数据依次往后写入，读取时以最后一个值为有效值。当一个分区写满时会复制数据到另一个分区。
8 |
9 | #### 移植说明
10 | 1. 将eeprom_in_flash.c和eeprom_in_flash.h复制到工程
11 | 2. 实现EE_ErasePart，EE_ProgramWord，EE_ReadWord底层调用接口，可参考eeprom_port示例
12 | 3. 修改eeprom_in_flash.h中的宏定义，配置flash地址大小等相关参数
13 | - EEPROM_NUM_MAX：eeprom数据的最大数量，单位为16bit数据的个数。可选范围受最小分区大小的限制，要小于(EEPROM_PART_SIZE_min/4-1)
14 | - EEPROM_PART0_SIZE/EEPROM_PART1_SIZE：两个分区的大小，可以是不同大小，每个分区可包含多个擦除页，为最小擦除页的整数倍
15 | - EEPROM_START_ADDRESS：用于模拟eeprom的flash起始地址
16 |
17 | #### 使用说明
18 | ```c
19 | //参数：eeprom初始化值，NULL则无初始值
20 | int EEPROM_Init(void *default_data);
21 | int EEPROM_Format(void *default_data);
22 |
23 | //参数Address：eeprom的地址，一个地址保存16bit数据，范围0 - (EEPROM_NUM_MAX-1)
24 | //参数length：读写buf的长度，为16bit数据的个数
25 | uint16_t EEPROM_Read(uint16_t Address);
26 | int EEPROM_Write(uint16_t Address, uint16_t Data);
27 | int EEPROM_Read_Buf(uint16_t Address, uint16_t *buf, uint16_t length);
28 | int EEPROM_Write_Buf(uint16_t Address, uint16_t *buf, uint16_t length);
29 |
30 | //参数addr：eeprom存储空间的地址，单位byte，与上面eeprom的参数呈2倍关系，地址空间不可重复，必须2字节对齐，范围0 - (EEPROM_NUM_MAX-1)*2
31 | //参数length：读写buf的长度，单位字节长度，必须2字节对齐
32 | int Config_Read_Buf(uint16_t addr, void *buf, uint16_t length);
33 | int Config_Write_Buf(uint16_t addr, void *buf, uint16_t length);
34 | ```
35 |
36 | #### 使用限制
37 |
38 | 1. 最小编程单元为32bit及以下
39 | 2. 至少有两个可擦除页供eeprom使用
40 | 3. 储存的eeprom最大数据量小于可用flash空间的四分之一
41 | 4. 擦除后的清空值为0xff
42 |
43 | #### 特点
44 |
45 | 1. 资源占有率极低，适合小型单片机项目
46 | 2. 支持flash擦除编程 **磨损平衡**
47 | 3. 支持 **任意时间安全掉电** ，可靠性高
48 | 4. 全部数据在内存缓冲，读写速率快
49 | 5. 更新程序不影响储存的内容，可 **增量更新** ，也可以选择不使用老数据
50 | 6. 支持日志打印接口，方便调试
51 | 7. 支持8位单片机
52 | 8. 不支持数据正确性校验
53 |
54 | #### 注意事项
55 | 1. 调用eeprom读写接口要注意地址和长度范围，不要出现不同数据地址范围覆盖的情况
56 | 2. flash地址编程接口EE_ProgramWord，若不能32位写入原子操作，则要先写低16位后写高16位
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/demo/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h:
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/demo/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h:
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/demo/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h:
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1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f10x.h
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /** @addtogroup CMSIS
21 | * @{
22 | */
23 |
24 | /** @addtogroup stm32f10x_system
25 | * @{
26 | */
27 |
28 | /**
29 | * @brief Define to prevent recursive inclusion
30 | */
31 | #ifndef __SYSTEM_STM32F10X_H
32 | #define __SYSTEM_STM32F10X_H
33 |
34 | #ifdef __cplusplus
35 | extern "C" {
36 | #endif
37 |
38 | /** @addtogroup STM32F10x_System_Includes
39 | * @{
40 | */
41 |
42 | /**
43 | * @}
44 | */
45 |
46 |
47 | /** @addtogroup STM32F10x_System_Exported_types
48 | * @{
49 | */
50 |
51 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
52 | extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
53 | extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /** @addtogroup STM32F10x_System_Exported_Constants
60 | * @{
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @addtogroup STM32F10x_System_Exported_Macros
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @addtogroup STM32F10x_System_Exported_Functions
76 | * @{
77 | */
78 |
79 | extern void SystemInit(void);
80 | extern void SystemCoreClockUpdate(void);
81 | /**
82 | * @}
83 | */
84 |
85 | #ifdef __cplusplus
86 | }
87 | #endif
88 |
89 | #endif /*__SYSTEM_STM32F10X_H */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
99 |
--------------------------------------------------------------------------------
/demo/Drivers/CMSIS/Include/cmsis_compiler.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_compiler.h
3 | * @brief CMSIS compiler generic header file
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #ifndef __CMSIS_COMPILER_H
26 | #define __CMSIS_COMPILER_H
27 |
28 | #include
29 |
30 | /*
31 | * Arm Compiler 4/5
32 | */
33 | #if defined ( __CC_ARM )
34 | #include "cmsis_armcc.h"
35 |
36 |
37 | /*
38 | * Arm Compiler 6 (armclang)
39 | */
40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
41 | #include "cmsis_armclang.h"
42 |
43 |
44 | /*
45 | * GNU Compiler
46 | */
47 | #elif defined ( __GNUC__ )
48 | #include "cmsis_gcc.h"
49 |
50 |
51 | /*
52 | * IAR Compiler
53 | */
54 | #elif defined ( __ICCARM__ )
55 | #include
56 |
57 |
58 | /*
59 | * TI Arm Compiler
60 | */
61 | #elif defined ( __TI_ARM__ )
62 | #include
63 |
64 | #ifndef __ASM
65 | #define __ASM __asm
66 | #endif
67 | #ifndef __INLINE
68 | #define __INLINE inline
69 | #endif
70 | #ifndef __STATIC_INLINE
71 | #define __STATIC_INLINE static inline
72 | #endif
73 | #ifndef __STATIC_FORCEINLINE
74 | #define __STATIC_FORCEINLINE __STATIC_INLINE
75 | #endif
76 | #ifndef __NO_RETURN
77 | #define __NO_RETURN __attribute__((noreturn))
78 | #endif
79 | #ifndef __USED
80 | #define __USED __attribute__((used))
81 | #endif
82 | #ifndef __WEAK
83 | #define __WEAK __attribute__((weak))
84 | #endif
85 | #ifndef __PACKED
86 | #define __PACKED __attribute__((packed))
87 | #endif
88 | #ifndef __PACKED_STRUCT
89 | #define __PACKED_STRUCT struct __attribute__((packed))
90 | #endif
91 | #ifndef __PACKED_UNION
92 | #define __PACKED_UNION union __attribute__((packed))
93 | #endif
94 | #ifndef __UNALIGNED_UINT32 /* deprecated */
95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; };
96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
97 | #endif
98 | #ifndef __UNALIGNED_UINT16_WRITE
99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
101 | #endif
102 | #ifndef __UNALIGNED_UINT16_READ
103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
105 | #endif
106 | #ifndef __UNALIGNED_UINT32_WRITE
107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
109 | #endif
110 | #ifndef __UNALIGNED_UINT32_READ
111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
113 | #endif
114 | #ifndef __ALIGNED
115 | #define __ALIGNED(x) __attribute__((aligned(x)))
116 | #endif
117 | #ifndef __RESTRICT
118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
119 | #define __RESTRICT
120 | #endif
121 |
122 |
123 | /*
124 | * TASKING Compiler
125 | */
126 | #elif defined ( __TASKING__ )
127 | /*
128 | * The CMSIS functions have been implemented as intrinsics in the compiler.
129 | * Please use "carm -?i" to get an up to date list of all intrinsics,
130 | * Including the CMSIS ones.
131 | */
132 |
133 | #ifndef __ASM
134 | #define __ASM __asm
135 | #endif
136 | #ifndef __INLINE
137 | #define __INLINE inline
138 | #endif
139 | #ifndef __STATIC_INLINE
140 | #define __STATIC_INLINE static inline
141 | #endif
142 | #ifndef __STATIC_FORCEINLINE
143 | #define __STATIC_FORCEINLINE __STATIC_INLINE
144 | #endif
145 | #ifndef __NO_RETURN
146 | #define __NO_RETURN __attribute__((noreturn))
147 | #endif
148 | #ifndef __USED
149 | #define __USED __attribute__((used))
150 | #endif
151 | #ifndef __WEAK
152 | #define __WEAK __attribute__((weak))
153 | #endif
154 | #ifndef __PACKED
155 | #define __PACKED __packed__
156 | #endif
157 | #ifndef __PACKED_STRUCT
158 | #define __PACKED_STRUCT struct __packed__
159 | #endif
160 | #ifndef __PACKED_UNION
161 | #define __PACKED_UNION union __packed__
162 | #endif
163 | #ifndef __UNALIGNED_UINT32 /* deprecated */
164 | struct __packed__ T_UINT32 { uint32_t v; };
165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
166 | #endif
167 | #ifndef __UNALIGNED_UINT16_WRITE
168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
170 | #endif
171 | #ifndef __UNALIGNED_UINT16_READ
172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
174 | #endif
175 | #ifndef __UNALIGNED_UINT32_WRITE
176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
178 | #endif
179 | #ifndef __UNALIGNED_UINT32_READ
180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
182 | #endif
183 | #ifndef __ALIGNED
184 | #define __ALIGNED(x) __align(x)
185 | #endif
186 | #ifndef __RESTRICT
187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
188 | #define __RESTRICT
189 | #endif
190 |
191 |
192 | /*
193 | * COSMIC Compiler
194 | */
195 | #elif defined ( __CSMC__ )
196 | #include
197 |
198 | #ifndef __ASM
199 | #define __ASM _asm
200 | #endif
201 | #ifndef __INLINE
202 | #define __INLINE inline
203 | #endif
204 | #ifndef __STATIC_INLINE
205 | #define __STATIC_INLINE static inline
206 | #endif
207 | #ifndef __STATIC_FORCEINLINE
208 | #define __STATIC_FORCEINLINE __STATIC_INLINE
209 | #endif
210 | #ifndef __NO_RETURN
211 | // NO RETURN is automatically detected hence no warning here
212 | #define __NO_RETURN
213 | #endif
214 | #ifndef __USED
215 | #warning No compiler specific solution for __USED. __USED is ignored.
216 | #define __USED
217 | #endif
218 | #ifndef __WEAK
219 | #define __WEAK __weak
220 | #endif
221 | #ifndef __PACKED
222 | #define __PACKED @packed
223 | #endif
224 | #ifndef __PACKED_STRUCT
225 | #define __PACKED_STRUCT @packed struct
226 | #endif
227 | #ifndef __PACKED_UNION
228 | #define __PACKED_UNION @packed union
229 | #endif
230 | #ifndef __UNALIGNED_UINT32 /* deprecated */
231 | @packed struct T_UINT32 { uint32_t v; };
232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
233 | #endif
234 | #ifndef __UNALIGNED_UINT16_WRITE
235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
237 | #endif
238 | #ifndef __UNALIGNED_UINT16_READ
239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
241 | #endif
242 | #ifndef __UNALIGNED_UINT32_WRITE
243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
245 | #endif
246 | #ifndef __UNALIGNED_UINT32_READ
247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
249 | #endif
250 | #ifndef __ALIGNED
251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
252 | #define __ALIGNED(x)
253 | #endif
254 | #ifndef __RESTRICT
255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
256 | #define __RESTRICT
257 | #endif
258 |
259 |
260 | #else
261 | #error Unknown compiler.
262 | #endif
263 |
264 |
265 | #endif /* __CMSIS_COMPILER_H */
266 |
267 |
--------------------------------------------------------------------------------
/demo/Drivers/CMSIS/Include/cmsis_version.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_version.h
3 | * @brief CMSIS Core(M) Version definitions
4 | * @version V5.0.2
5 | * @date 19. April 2017
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef __CMSIS_VERSION_H
32 | #define __CMSIS_VERSION_H
33 |
34 | /* CMSIS Version definitions */
35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
39 | #endif
40 |
--------------------------------------------------------------------------------
/demo/Drivers/CMSIS/Include/mpu_armv7.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv7.h
3 | * @brief CMSIS MPU API for Armv7-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV7_H
32 | #define ARM_MPU_ARMV7_H
33 |
34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62 |
63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69 |
70 | /** MPU Region Base Address Register Value
71 | *
72 | * \param Region The region to be configured, number 0 to 15.
73 | * \param BaseAddress The base address for the region.
74 | */
75 | #define ARM_MPU_RBAR(Region, BaseAddress) \
76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 | ((Region) & MPU_RBAR_REGION_Msk) | \
78 | (MPU_RBAR_VALID_Msk))
79 |
80 | /**
81 | * MPU Memory Access Attributes
82 | *
83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 | * \param IsShareable Region is shareable between multiple bus masters.
85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 | */
88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93 |
94 | /**
95 | * MPU Region Attribute and Size Register Value
96 | *
97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 | * \param SubRegionDisable Sub-region disable field.
101 | * \param Size Region size of the region to be configured, for example 4K, 8K.
102 | */
103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107 |
108 | /**
109 | * MPU Region Attribute and Size Register Value
110 | *
111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
114 | * \param IsShareable Region is shareable between multiple bus masters.
115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
117 | * \param SubRegionDisable Sub-region disable field.
118 | * \param Size Region size of the region to be configured, for example 4K, 8K.
119 | */
120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122 |
123 | /**
124 | * MPU Memory Access Attribute for strongly ordered memory.
125 | * - TEX: 000b
126 | * - Shareable
127 | * - Non-cacheable
128 | * - Non-bufferable
129 | */
130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131 |
132 | /**
133 | * MPU Memory Access Attribute for device memory.
134 | * - TEX: 000b (if non-shareable) or 010b (if shareable)
135 | * - Shareable or non-shareable
136 | * - Non-cacheable
137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable)
138 | *
139 | * \param IsShareable Configures the device memory as shareable or non-shareable.
140 | */
141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142 |
143 | /**
144 | * MPU Memory Access Attribute for normal memory.
145 | * - TEX: 1BBb (reflecting outer cacheability rules)
146 | * - Shareable or non-shareable
147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules)
148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules)
149 | *
150 | * \param OuterCp Configures the outer cache policy.
151 | * \param InnerCp Configures the inner cache policy.
152 | * \param IsShareable Configures the memory as shareable or non-shareable.
153 | */
154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155 |
156 | /**
157 | * MPU Memory Access Attribute non-cacheable policy.
158 | */
159 | #define ARM_MPU_CACHEP_NOCACHE 0U
160 |
161 | /**
162 | * MPU Memory Access Attribute write-back, write and read allocate policy.
163 | */
164 | #define ARM_MPU_CACHEP_WB_WRA 1U
165 |
166 | /**
167 | * MPU Memory Access Attribute write-through, no write allocate policy.
168 | */
169 | #define ARM_MPU_CACHEP_WT_NWA 2U
170 |
171 | /**
172 | * MPU Memory Access Attribute write-back, no write allocate policy.
173 | */
174 | #define ARM_MPU_CACHEP_WB_NWA 3U
175 |
176 |
177 | /**
178 | * Struct for a single MPU Region
179 | */
180 | typedef struct {
181 | uint32_t RBAR; //!< The region base address register value (RBAR)
182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
183 | } ARM_MPU_Region_t;
184 |
185 | /** Enable the MPU.
186 | * \param MPU_Control Default access permissions for unconfigured regions.
187 | */
188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 | {
190 | __DSB();
191 | __ISB();
192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 | #endif
196 | }
197 |
198 | /** Disable the MPU.
199 | */
200 | __STATIC_INLINE void ARM_MPU_Disable(void)
201 | {
202 | __DSB();
203 | __ISB();
204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 | #endif
207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 | }
209 |
210 | /** Clear and disable the given MPU region.
211 | * \param rnr Region number to be cleared.
212 | */
213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
214 | {
215 | MPU->RNR = rnr;
216 | MPU->RASR = 0U;
217 | }
218 |
219 | /** Configure an MPU region.
220 | * \param rbar Value for RBAR register.
221 | * \param rsar Value for RSAR register.
222 | */
223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 | {
225 | MPU->RBAR = rbar;
226 | MPU->RASR = rasr;
227 | }
228 |
229 | /** Configure the given MPU region.
230 | * \param rnr Region number to be configured.
231 | * \param rbar Value for RBAR register.
232 | * \param rsar Value for RSAR register.
233 | */
234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 | {
236 | MPU->RNR = rnr;
237 | MPU->RBAR = rbar;
238 | MPU->RASR = rasr;
239 | }
240 |
241 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
242 | * \param dst Destination data is copied to.
243 | * \param src Source data is copied from.
244 | * \param len Amount of data words to be copied.
245 | */
246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 | {
248 | uint32_t i;
249 | for (i = 0U; i < len; ++i)
250 | {
251 | dst[i] = src[i];
252 | }
253 | }
254 |
255 | /** Load the given number of MPU regions from a table.
256 | * \param table Pointer to the MPU configuration table.
257 | * \param cnt Amount of regions to be configured.
258 | */
259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 | {
261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262 | while (cnt > MPU_TYPE_RALIASES) {
263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 | table += MPU_TYPE_RALIASES;
265 | cnt -= MPU_TYPE_RALIASES;
266 | }
267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 | }
269 |
270 | #endif
271 |
--------------------------------------------------------------------------------
/demo/Drivers/CMSIS/Include/mpu_armv8.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv8.h
3 | * @brief CMSIS MPU API for Armv8-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV8_H
32 | #define ARM_MPU_ARMV8_H
33 |
34 | /** \brief Attribute for device memory (outer only) */
35 | #define ARM_MPU_ATTR_DEVICE ( 0U )
36 |
37 | /** \brief Attribute for non-cacheable, normal memory */
38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39 |
40 | /** \brief Attribute for normal memory (outer and inner)
41 | * \param NT Non-Transient: Set to 1 for non-transient data.
42 | * \param WB Write-Back: Set to 1 to use write-back update policy.
43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
45 | */
46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
48 |
49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51 |
52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54 |
55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57 |
58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60 |
61 | /** \brief Memory Attribute
62 | * \param O Outer memory attributes
63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
64 | */
65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
66 |
67 | /** \brief Normal memory non-shareable */
68 | #define ARM_MPU_SH_NON (0U)
69 |
70 | /** \brief Normal memory outer shareable */
71 | #define ARM_MPU_SH_OUTER (2U)
72 |
73 | /** \brief Normal memory inner shareable */
74 | #define ARM_MPU_SH_INNER (3U)
75 |
76 | /** \brief Memory access permissions
77 | * \param RO Read-Only: Set to 1 for read-only memory.
78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory.
79 | */
80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
81 |
82 | /** \brief Region Base Address Register value
83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
84 | * \param SH Defines the Shareability domain for this memory region.
85 | * \param RO Read-Only: Set to 1 for a read-only memory region.
86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
88 | */
89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90 | ((BASE & MPU_RBAR_BASE_Msk) | \
91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94 |
95 | /** \brief Region Limit Address Register value
96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
97 | * \param IDX The attribute index to be associated with this memory region.
98 | */
99 | #define ARM_MPU_RLAR(LIMIT, IDX) \
100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102 | (MPU_RLAR_EN_Msk))
103 |
104 | /**
105 | * Struct for a single MPU Region
106 | */
107 | typedef struct {
108 | uint32_t RBAR; /*!< Region Base Address Register value */
109 | uint32_t RLAR; /*!< Region Limit Address Register value */
110 | } ARM_MPU_Region_t;
111 |
112 | /** Enable the MPU.
113 | * \param MPU_Control Default access permissions for unconfigured regions.
114 | */
115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
116 | {
117 | __DSB();
118 | __ISB();
119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
122 | #endif
123 | }
124 |
125 | /** Disable the MPU.
126 | */
127 | __STATIC_INLINE void ARM_MPU_Disable(void)
128 | {
129 | __DSB();
130 | __ISB();
131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
133 | #endif
134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
135 | }
136 |
137 | #ifdef MPU_NS
138 | /** Enable the Non-secure MPU.
139 | * \param MPU_Control Default access permissions for unconfigured regions.
140 | */
141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
142 | {
143 | __DSB();
144 | __ISB();
145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
148 | #endif
149 | }
150 |
151 | /** Disable the Non-secure MPU.
152 | */
153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void)
154 | {
155 | __DSB();
156 | __ISB();
157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
159 | #endif
160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
161 | }
162 | #endif
163 |
164 | /** Set the memory attribute encoding to the given MPU.
165 | * \param mpu Pointer to the MPU to be configured.
166 | * \param idx The attribute index to be set [0-7]
167 | * \param attr The attribute value to be set.
168 | */
169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
170 | {
171 | const uint8_t reg = idx / 4U;
172 | const uint32_t pos = ((idx % 4U) * 8U);
173 | const uint32_t mask = 0xFFU << pos;
174 |
175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
176 | return; // invalid index
177 | }
178 |
179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
180 | }
181 |
182 | /** Set the memory attribute encoding.
183 | * \param idx The attribute index to be set [0-7]
184 | * \param attr The attribute value to be set.
185 | */
186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
187 | {
188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr);
189 | }
190 |
191 | #ifdef MPU_NS
192 | /** Set the memory attribute encoding to the Non-secure MPU.
193 | * \param idx The attribute index to be set [0-7]
194 | * \param attr The attribute value to be set.
195 | */
196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
197 | {
198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
199 | }
200 | #endif
201 |
202 | /** Clear and disable the given MPU region of the given MPU.
203 | * \param mpu Pointer to MPU to be used.
204 | * \param rnr Region number to be cleared.
205 | */
206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
207 | {
208 | mpu->RNR = rnr;
209 | mpu->RLAR = 0U;
210 | }
211 |
212 | /** Clear and disable the given MPU region.
213 | * \param rnr Region number to be cleared.
214 | */
215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
216 | {
217 | ARM_MPU_ClrRegionEx(MPU, rnr);
218 | }
219 |
220 | #ifdef MPU_NS
221 | /** Clear and disable the given Non-secure MPU region.
222 | * \param rnr Region number to be cleared.
223 | */
224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
225 | {
226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr);
227 | }
228 | #endif
229 |
230 | /** Configure the given MPU region of the given MPU.
231 | * \param mpu Pointer to MPU to be used.
232 | * \param rnr Region number to be configured.
233 | * \param rbar Value for RBAR register.
234 | * \param rlar Value for RLAR register.
235 | */
236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
237 | {
238 | mpu->RNR = rnr;
239 | mpu->RBAR = rbar;
240 | mpu->RLAR = rlar;
241 | }
242 |
243 | /** Configure the given MPU region.
244 | * \param rnr Region number to be configured.
245 | * \param rbar Value for RBAR register.
246 | * \param rlar Value for RLAR register.
247 | */
248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
249 | {
250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
251 | }
252 |
253 | #ifdef MPU_NS
254 | /** Configure the given Non-secure MPU region.
255 | * \param rnr Region number to be configured.
256 | * \param rbar Value for RBAR register.
257 | * \param rlar Value for RLAR register.
258 | */
259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
260 | {
261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
262 | }
263 | #endif
264 |
265 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
266 | * \param dst Destination data is copied to.
267 | * \param src Source data is copied from.
268 | * \param len Amount of data words to be copied.
269 | */
270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
271 | {
272 | uint32_t i;
273 | for (i = 0U; i < len; ++i)
274 | {
275 | dst[i] = src[i];
276 | }
277 | }
278 |
279 | /** Load the given number of MPU regions from a table to the given MPU.
280 | * \param mpu Pointer to the MPU registers to be used.
281 | * \param rnr First region number to be configured.
282 | * \param table Pointer to the MPU configuration table.
283 | * \param cnt Amount of regions to be configured.
284 | */
285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
286 | {
287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
288 | if (cnt == 1U) {
289 | mpu->RNR = rnr;
290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
291 | } else {
292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
294 |
295 | mpu->RNR = rnrBase;
296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
299 | table += c;
300 | cnt -= c;
301 | rnrOffset = 0U;
302 | rnrBase += MPU_TYPE_RALIASES;
303 | mpu->RNR = rnrBase;
304 | }
305 |
306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
307 | }
308 | }
309 |
310 | /** Load the given number of MPU regions from a table.
311 | * \param rnr First region number to be configured.
312 | * \param table Pointer to the MPU configuration table.
313 | * \param cnt Amount of regions to be configured.
314 | */
315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
316 | {
317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt);
318 | }
319 |
320 | #ifdef MPU_NS
321 | /** Load the given number of MPU regions from a table to the Non-secure MPU.
322 | * \param rnr First region number to be configured.
323 | * \param table Pointer to the MPU configuration table.
324 | * \param cnt Amount of regions to be configured.
325 | */
326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
327 | {
328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
329 | }
330 | #endif
331 |
332 | #endif
333 |
334 |
--------------------------------------------------------------------------------
/demo/Drivers/CMSIS/Include/tz_context.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file tz_context.h
3 | * @brief Context Management for Armv8-M TrustZone
4 | * @version V1.0.1
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef TZ_CONTEXT_H
32 | #define TZ_CONTEXT_H
33 |
34 | #include
35 |
36 | #ifndef TZ_MODULEID_T
37 | #define TZ_MODULEID_T
38 | /// \details Data type that identifies secure software modules called by a process.
39 | typedef uint32_t TZ_ModuleId_t;
40 | #endif
41 |
42 | /// \details TZ Memory ID identifies an allocated memory slot.
43 | typedef uint32_t TZ_MemoryId_t;
44 |
45 | /// Initialize secure context memory system
46 | /// \return execution status (1: success, 0: error)
47 | uint32_t TZ_InitContextSystem_S (void);
48 |
49 | /// Allocate context memory for calling secure software modules in TrustZone
50 | /// \param[in] module identifies software modules called from non-secure mode
51 | /// \return value != 0 id TrustZone memory slot identifier
52 | /// \return value 0 no memory available or internal error
53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
54 |
55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
56 | /// \param[in] id TrustZone memory slot identifier
57 | /// \return execution status (1: success, 0: error)
58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
59 |
60 | /// Load secure context (called on RTOS thread context switch)
61 | /// \param[in] id TrustZone memory slot identifier
62 | /// \return execution status (1: success, 0: error)
63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
64 |
65 | /// Store secure context (called on RTOS thread context switch)
66 | /// \param[in] id TrustZone memory slot identifier
67 | /// \return execution status (1: success, 0: error)
68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
69 |
70 | #endif // TZ_CONTEXT_H
71 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal.h
4 | * @author MCD Application Team
5 | * @brief This file contains all the functions prototypes for the HAL
6 | * module driver.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F1xx_HAL_H
23 | #define __STM32F1xx_HAL_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f1xx_hal_conf.h"
31 |
32 | /** @addtogroup STM32F1xx_HAL_Driver
33 | * @{
34 | */
35 |
36 | /** @addtogroup HAL
37 | * @{
38 | */
39 |
40 | /* Exported constants --------------------------------------------------------*/
41 |
42 | /** @defgroup HAL_Exported_Constants HAL Exported Constants
43 | * @{
44 | */
45 |
46 | /** @defgroup HAL_TICK_FREQ Tick Frequency
47 | * @{
48 | */
49 | typedef enum
50 | {
51 | HAL_TICK_FREQ_10HZ = 100U,
52 | HAL_TICK_FREQ_100HZ = 10U,
53 | HAL_TICK_FREQ_1KHZ = 1U,
54 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
55 | } HAL_TickFreqTypeDef;
56 | /**
57 | * @}
58 | */
59 | /* Exported types ------------------------------------------------------------*/
60 | extern __IO uint32_t uwTick;
61 | extern uint32_t uwTickPrio;
62 | extern HAL_TickFreqTypeDef uwTickFreq;
63 |
64 | /**
65 | * @}
66 | */
67 | /* Exported macro ------------------------------------------------------------*/
68 | /** @defgroup HAL_Exported_Macros HAL Exported Macros
69 | * @{
70 | */
71 |
72 | /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
73 | * @brief Freeze/Unfreeze Peripherals in Debug mode
74 | * Note: On devices STM32F10xx8 and STM32F10xxB,
75 | * STM32F101xC/D/E and STM32F103xC/D/E,
76 | * STM32F101xF/G and STM32F103xF/G
77 | * STM32F10xx4 and STM32F10xx6
78 | * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
79 | * debug mode (not accessible by the user software in normal mode).
80 | * Refer to errata sheet of these devices for more details.
81 | * @{
82 | */
83 |
84 | /* Peripherals on APB1 */
85 | /**
86 | * @brief TIM2 Peripherals Debug mode
87 | */
88 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
89 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
90 |
91 | /**
92 | * @brief TIM3 Peripherals Debug mode
93 | */
94 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
95 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
96 |
97 | #if defined (DBGMCU_CR_DBG_TIM4_STOP)
98 | /**
99 | * @brief TIM4 Peripherals Debug mode
100 | */
101 | #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
102 | #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
103 | #endif
104 |
105 | #if defined (DBGMCU_CR_DBG_TIM5_STOP)
106 | /**
107 | * @brief TIM5 Peripherals Debug mode
108 | */
109 | #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
110 | #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
111 | #endif
112 |
113 | #if defined (DBGMCU_CR_DBG_TIM6_STOP)
114 | /**
115 | * @brief TIM6 Peripherals Debug mode
116 | */
117 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
118 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
119 | #endif
120 |
121 | #if defined (DBGMCU_CR_DBG_TIM7_STOP)
122 | /**
123 | * @brief TIM7 Peripherals Debug mode
124 | */
125 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
126 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
127 | #endif
128 |
129 | #if defined (DBGMCU_CR_DBG_TIM12_STOP)
130 | /**
131 | * @brief TIM12 Peripherals Debug mode
132 | */
133 | #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
134 | #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
135 | #endif
136 |
137 | #if defined (DBGMCU_CR_DBG_TIM13_STOP)
138 | /**
139 | * @brief TIM13 Peripherals Debug mode
140 | */
141 | #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
142 | #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
143 | #endif
144 |
145 | #if defined (DBGMCU_CR_DBG_TIM14_STOP)
146 | /**
147 | * @brief TIM14 Peripherals Debug mode
148 | */
149 | #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
150 | #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
151 | #endif
152 |
153 | /**
154 | * @brief WWDG Peripherals Debug mode
155 | */
156 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
157 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
158 |
159 | /**
160 | * @brief IWDG Peripherals Debug mode
161 | */
162 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
163 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
164 |
165 | /**
166 | * @brief I2C1 Peripherals Debug mode
167 | */
168 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
169 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
170 |
171 | #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
172 | /**
173 | * @brief I2C2 Peripherals Debug mode
174 | */
175 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
176 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
177 | #endif
178 |
179 | #if defined (DBGMCU_CR_DBG_CAN1_STOP)
180 | /**
181 | * @brief CAN1 Peripherals Debug mode
182 | */
183 | #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
184 | #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
185 | #endif
186 |
187 | #if defined (DBGMCU_CR_DBG_CAN2_STOP)
188 | /**
189 | * @brief CAN2 Peripherals Debug mode
190 | */
191 | #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
192 | #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
193 | #endif
194 |
195 | /* Peripherals on APB2 */
196 | #if defined (DBGMCU_CR_DBG_TIM1_STOP)
197 | /**
198 | * @brief TIM1 Peripherals Debug mode
199 | */
200 | #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
201 | #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
202 | #endif
203 |
204 | #if defined (DBGMCU_CR_DBG_TIM8_STOP)
205 | /**
206 | * @brief TIM8 Peripherals Debug mode
207 | */
208 | #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
209 | #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
210 | #endif
211 |
212 | #if defined (DBGMCU_CR_DBG_TIM9_STOP)
213 | /**
214 | * @brief TIM9 Peripherals Debug mode
215 | */
216 | #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
217 | #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
218 | #endif
219 |
220 | #if defined (DBGMCU_CR_DBG_TIM10_STOP)
221 | /**
222 | * @brief TIM10 Peripherals Debug mode
223 | */
224 | #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
225 | #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
226 | #endif
227 |
228 | #if defined (DBGMCU_CR_DBG_TIM11_STOP)
229 | /**
230 | * @brief TIM11 Peripherals Debug mode
231 | */
232 | #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
233 | #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
234 | #endif
235 |
236 |
237 | #if defined (DBGMCU_CR_DBG_TIM15_STOP)
238 | /**
239 | * @brief TIM15 Peripherals Debug mode
240 | */
241 | #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
242 | #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
243 | #endif
244 |
245 | #if defined (DBGMCU_CR_DBG_TIM16_STOP)
246 | /**
247 | * @brief TIM16 Peripherals Debug mode
248 | */
249 | #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
250 | #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
251 | #endif
252 |
253 | #if defined (DBGMCU_CR_DBG_TIM17_STOP)
254 | /**
255 | * @brief TIM17 Peripherals Debug mode
256 | */
257 | #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
258 | #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
259 | #endif
260 |
261 | /**
262 | * @}
263 | */
264 |
265 | /** @defgroup HAL_Private_Macros HAL Private Macros
266 | * @{
267 | */
268 | #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
269 | ((FREQ) == HAL_TICK_FREQ_100HZ) || \
270 | ((FREQ) == HAL_TICK_FREQ_1KHZ))
271 | /**
272 | * @}
273 | */
274 |
275 | /* Exported functions --------------------------------------------------------*/
276 | /** @addtogroup HAL_Exported_Functions
277 | * @{
278 | */
279 | /** @addtogroup HAL_Exported_Functions_Group1
280 | * @{
281 | */
282 | /* Initialization and de-initialization functions ******************************/
283 | HAL_StatusTypeDef HAL_Init(void);
284 | HAL_StatusTypeDef HAL_DeInit(void);
285 | void HAL_MspInit(void);
286 | void HAL_MspDeInit(void);
287 | HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
288 | /**
289 | * @}
290 | */
291 |
292 | /** @addtogroup HAL_Exported_Functions_Group2
293 | * @{
294 | */
295 | /* Peripheral Control functions ************************************************/
296 | void HAL_IncTick(void);
297 | void HAL_Delay(uint32_t Delay);
298 | uint32_t HAL_GetTick(void);
299 | uint32_t HAL_GetTickPrio(void);
300 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
301 | HAL_TickFreqTypeDef HAL_GetTickFreq(void);
302 | void HAL_SuspendTick(void);
303 | void HAL_ResumeTick(void);
304 | uint32_t HAL_GetHalVersion(void);
305 | uint32_t HAL_GetREVID(void);
306 | uint32_t HAL_GetDEVID(void);
307 | uint32_t HAL_GetUIDw0(void);
308 | uint32_t HAL_GetUIDw1(void);
309 | uint32_t HAL_GetUIDw2(void);
310 | void HAL_DBGMCU_EnableDBGSleepMode(void);
311 | void HAL_DBGMCU_DisableDBGSleepMode(void);
312 | void HAL_DBGMCU_EnableDBGStopMode(void);
313 | void HAL_DBGMCU_DisableDBGStopMode(void);
314 | void HAL_DBGMCU_EnableDBGStandbyMode(void);
315 | void HAL_DBGMCU_DisableDBGStandbyMode(void);
316 | /**
317 | * @}
318 | */
319 |
320 | /**
321 | * @}
322 | */
323 |
324 | /**
325 | * @}
326 | */
327 | /* Private types -------------------------------------------------------------*/
328 | /* Private variables ---------------------------------------------------------*/
329 | /** @defgroup HAL_Private_Variables HAL Private Variables
330 | * @{
331 | */
332 | /**
333 | * @}
334 | */
335 | /* Private constants ---------------------------------------------------------*/
336 | /** @defgroup HAL_Private_Constants HAL Private Constants
337 | * @{
338 | */
339 | /**
340 | * @}
341 | */
342 | /* Private macros ------------------------------------------------------------*/
343 | /* Private functions ---------------------------------------------------------*/
344 | /**
345 | * @}
346 | */
347 |
348 | /**
349 | * @}
350 | */
351 |
352 | #ifdef __cplusplus
353 | }
354 | #endif
355 |
356 | #endif /* __STM32F1xx_HAL_H */
357 |
358 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
359 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_def.h
4 | * @author MCD Application Team
5 | * @brief This file contains HAL common defines, enumeration, macros and
6 | * structures definitions.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F1xx_HAL_DEF
23 | #define __STM32F1xx_HAL_DEF
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f1xx.h"
31 | #include "Legacy/stm32_hal_legacy.h"
32 | #include
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 |
36 | /**
37 | * @brief HAL Status structures definition
38 | */
39 | typedef enum
40 | {
41 | HAL_OK = 0x00U,
42 | HAL_ERROR = 0x01U,
43 | HAL_BUSY = 0x02U,
44 | HAL_TIMEOUT = 0x03U
45 | } HAL_StatusTypeDef;
46 |
47 | /**
48 | * @brief HAL Lock structures definition
49 | */
50 | typedef enum
51 | {
52 | HAL_UNLOCKED = 0x00U,
53 | HAL_LOCKED = 0x01U
54 | } HAL_LockTypeDef;
55 |
56 | /* Exported macro ------------------------------------------------------------*/
57 | #define HAL_MAX_DELAY 0xFFFFFFFFU
58 |
59 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
60 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
61 |
62 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
63 | do{ \
64 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
65 | (__DMA_HANDLE__).Parent = (__HANDLE__); \
66 | } while(0U)
67 |
68 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
69 |
70 | /** @brief Reset the Handle's State field.
71 | * @param __HANDLE__ specifies the Peripheral Handle.
72 | * @note This macro can be used for the following purpose:
73 | * - When the Handle is declared as local variable; before passing it as parameter
74 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
75 | * to set to 0 the Handle's "State" field.
76 | * Otherwise, "State" field may have any random value and the first time the function
77 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed
78 | * (i.e. HAL_PPP_MspInit() will not be executed).
79 | * - When there is a need to reconfigure the low level hardware: instead of calling
80 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
81 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function
82 | * HAL_PPP_MspInit() which will reconfigure the low level hardware.
83 | * @retval None
84 | */
85 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
86 |
87 | #if (USE_RTOS == 1U)
88 | /* Reserved for future use */
89 | #error "USE_RTOS should be 0 in the current HAL release"
90 | #else
91 | #define __HAL_LOCK(__HANDLE__) \
92 | do{ \
93 | if((__HANDLE__)->Lock == HAL_LOCKED) \
94 | { \
95 | return HAL_BUSY; \
96 | } \
97 | else \
98 | { \
99 | (__HANDLE__)->Lock = HAL_LOCKED; \
100 | } \
101 | }while (0U)
102 |
103 | #define __HAL_UNLOCK(__HANDLE__) \
104 | do{ \
105 | (__HANDLE__)->Lock = HAL_UNLOCKED; \
106 | }while (0U)
107 | #endif /* USE_RTOS */
108 |
109 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
110 | #ifndef __weak
111 | #define __weak __attribute__((weak))
112 | #endif
113 | #ifndef __packed
114 | #define __packed __attribute__((packed))
115 | #endif
116 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
117 | #ifndef __weak
118 | #define __weak __attribute__((weak))
119 | #endif /* __weak */
120 | #ifndef __packed
121 | #define __packed __attribute__((__packed__))
122 | #endif /* __packed */
123 | #endif /* __GNUC__ */
124 |
125 |
126 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
127 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
128 | #ifndef __ALIGN_BEGIN
129 | #define __ALIGN_BEGIN
130 | #endif
131 | #ifndef __ALIGN_END
132 | #define __ALIGN_END __attribute__ ((aligned (4)))
133 | #endif
134 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
135 | #ifndef __ALIGN_END
136 | #define __ALIGN_END __attribute__ ((aligned (4)))
137 | #endif /* __ALIGN_END */
138 | #ifndef __ALIGN_BEGIN
139 | #define __ALIGN_BEGIN
140 | #endif /* __ALIGN_BEGIN */
141 | #else
142 | #ifndef __ALIGN_END
143 | #define __ALIGN_END
144 | #endif /* __ALIGN_END */
145 | #ifndef __ALIGN_BEGIN
146 | #if defined (__CC_ARM) /* ARM Compiler V5*/
147 | #define __ALIGN_BEGIN __align(4)
148 | #elif defined (__ICCARM__) /* IAR Compiler */
149 | #define __ALIGN_BEGIN
150 | #endif /* __CC_ARM */
151 | #endif /* __ALIGN_BEGIN */
152 | #endif /* __GNUC__ */
153 |
154 |
155 | /**
156 | * @brief __RAM_FUNC definition
157 | */
158 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
159 | /* ARM Compiler V4/V5 and V6
160 | --------------------------
161 | RAM functions are defined using the toolchain options.
162 | Functions that are executed in RAM should reside in a separate source module.
163 | Using the 'Options for File' dialog you can simply change the 'Code / Const'
164 | area of a module to a memory space in physical RAM.
165 | Available memory areas are declared in the 'Target' tab of the 'Options for Target'
166 | dialog.
167 | */
168 | #define __RAM_FUNC
169 |
170 | #elif defined ( __ICCARM__ )
171 | /* ICCARM Compiler
172 | ---------------
173 | RAM functions are defined using a specific toolchain keyword "__ramfunc".
174 | */
175 | #define __RAM_FUNC __ramfunc
176 |
177 | #elif defined ( __GNUC__ )
178 | /* GNU Compiler
179 | ------------
180 | RAM functions are defined using a specific toolchain attribute
181 | "__attribute__((section(".RamFunc")))".
182 | */
183 | #define __RAM_FUNC __attribute__((section(".RamFunc")))
184 |
185 | #endif
186 |
187 | /**
188 | * @brief __NOINLINE definition
189 | */
190 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
191 | /* ARM V4/V5 and V6 & GNU Compiler
192 | -------------------------------
193 | */
194 | #define __NOINLINE __attribute__ ( (noinline) )
195 |
196 | #elif defined ( __ICCARM__ )
197 | /* ICCARM Compiler
198 | ---------------
199 | */
200 | #define __NOINLINE _Pragma("optimize = no_inline")
201 |
202 | #endif
203 |
204 | #ifdef __cplusplus
205 | }
206 | #endif
207 |
208 | #endif /* ___STM32F1xx_HAL_DEF */
209 |
210 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
211 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_dma_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of DMA HAL extension module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F1xx_HAL_DMA_EX_H
22 | #define __STM32F1xx_HAL_DMA_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f1xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F1xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @defgroup DMAEx DMAEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /* Exported macro ------------------------------------------------------------*/
42 | /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
43 | * @{
44 | */
45 | /* Interrupt & Flag management */
46 | #if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
47 | defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
48 | /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
49 | * @{
50 | */
51 |
52 | /**
53 | * @brief Returns the current DMA Channel transfer complete flag.
54 | * @param __HANDLE__: DMA handle
55 | * @retval The specified transfer complete flag index.
56 | */
57 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
58 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
59 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
60 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
61 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
62 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
63 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
64 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
65 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
66 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
67 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
68 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
69 | DMA_FLAG_TC5)
70 |
71 | /**
72 | * @brief Returns the current DMA Channel half transfer complete flag.
73 | * @param __HANDLE__: DMA handle
74 | * @retval The specified half transfer complete flag index.
75 | */
76 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
77 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
78 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
79 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
80 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
81 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
82 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
83 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
84 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
85 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
86 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
87 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
88 | DMA_FLAG_HT5)
89 |
90 | /**
91 | * @brief Returns the current DMA Channel transfer error flag.
92 | * @param __HANDLE__: DMA handle
93 | * @retval The specified transfer error flag index.
94 | */
95 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
96 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
97 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
98 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
99 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
100 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
101 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
102 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
103 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
104 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
105 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
106 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
107 | DMA_FLAG_TE5)
108 |
109 | /**
110 | * @brief Return the current DMA Channel Global interrupt flag.
111 | * @param __HANDLE__: DMA handle
112 | * @retval The specified transfer error flag index.
113 | */
114 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
115 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
116 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
117 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
118 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
119 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
120 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
121 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
122 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
123 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
124 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
125 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
126 | DMA_FLAG_GL5)
127 |
128 | /**
129 | * @brief Get the DMA Channel pending flags.
130 | * @param __HANDLE__: DMA handle
131 | * @param __FLAG__: Get the specified flag.
132 | * This parameter can be any combination of the following values:
133 | * @arg DMA_FLAG_TCx: Transfer complete flag
134 | * @arg DMA_FLAG_HTx: Half transfer complete flag
135 | * @arg DMA_FLAG_TEx: Transfer error flag
136 | * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
137 | * @retval The state of FLAG (SET or RESET).
138 | */
139 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
140 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
141 | (DMA1->ISR & (__FLAG__)))
142 |
143 | /**
144 | * @brief Clears the DMA Channel pending flags.
145 | * @param __HANDLE__: DMA handle
146 | * @param __FLAG__: specifies the flag to clear.
147 | * This parameter can be any combination of the following values:
148 | * @arg DMA_FLAG_TCx: Transfer complete flag
149 | * @arg DMA_FLAG_HTx: Half transfer complete flag
150 | * @arg DMA_FLAG_TEx: Transfer error flag
151 | * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
152 | * @retval None
153 | */
154 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
155 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
156 | (DMA1->IFCR = (__FLAG__)))
157 |
158 | /**
159 | * @}
160 | */
161 |
162 | #else
163 | /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
164 | * @{
165 | */
166 |
167 | /**
168 | * @brief Returns the current DMA Channel transfer complete flag.
169 | * @param __HANDLE__: DMA handle
170 | * @retval The specified transfer complete flag index.
171 | */
172 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
173 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
174 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
175 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
176 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
177 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
178 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
179 | DMA_FLAG_TC7)
180 |
181 | /**
182 | * @brief Return the current DMA Channel half transfer complete flag.
183 | * @param __HANDLE__: DMA handle
184 | * @retval The specified half transfer complete flag index.
185 | */
186 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
187 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
188 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
189 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
190 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
191 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
192 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
193 | DMA_FLAG_HT7)
194 |
195 | /**
196 | * @brief Return the current DMA Channel transfer error flag.
197 | * @param __HANDLE__: DMA handle
198 | * @retval The specified transfer error flag index.
199 | */
200 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
201 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
202 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
203 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
204 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
205 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
206 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
207 | DMA_FLAG_TE7)
208 |
209 | /**
210 | * @brief Return the current DMA Channel Global interrupt flag.
211 | * @param __HANDLE__: DMA handle
212 | * @retval The specified transfer error flag index.
213 | */
214 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
215 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
216 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
217 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
218 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
219 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
220 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
221 | DMA_FLAG_GL7)
222 |
223 | /**
224 | * @brief Get the DMA Channel pending flags.
225 | * @param __HANDLE__: DMA handle
226 | * @param __FLAG__: Get the specified flag.
227 | * This parameter can be any combination of the following values:
228 | * @arg DMA_FLAG_TCx: Transfer complete flag
229 | * @arg DMA_FLAG_HTx: Half transfer complete flag
230 | * @arg DMA_FLAG_TEx: Transfer error flag
231 | * @arg DMA_FLAG_GLx: Global interrupt flag
232 | * Where x can be 1_7 to select the DMA Channel flag.
233 | * @retval The state of FLAG (SET or RESET).
234 | */
235 |
236 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
237 |
238 | /**
239 | * @brief Clear the DMA Channel pending flags.
240 | * @param __HANDLE__: DMA handle
241 | * @param __FLAG__: specifies the flag to clear.
242 | * This parameter can be any combination of the following values:
243 | * @arg DMA_FLAG_TCx: Transfer complete flag
244 | * @arg DMA_FLAG_HTx: Half transfer complete flag
245 | * @arg DMA_FLAG_TEx: Transfer error flag
246 | * @arg DMA_FLAG_GLx: Global interrupt flag
247 | * Where x can be 1_7 to select the DMA Channel flag.
248 | * @retval None
249 | */
250 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
251 |
252 | /**
253 | * @}
254 | */
255 |
256 | #endif
257 |
258 | /**
259 | * @}
260 | */
261 |
262 | /**
263 | * @}
264 | */
265 |
266 | /**
267 | * @}
268 | */
269 |
270 | #ifdef __cplusplus
271 | }
272 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
273 | /* STM32F103xG || STM32F105xC || STM32F107xC */
274 |
275 | #endif /* __STM32F1xx_HAL_DMA_H */
276 |
277 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
278 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_exti.h
4 | * @author MCD Application Team
5 | * @brief Header file of EXTI HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32F1xx_HAL_EXTI_H
22 | #define STM32F1xx_HAL_EXTI_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f1xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F1xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @defgroup EXTI EXTI
36 | * @brief EXTI HAL module driver
37 | * @{
38 | */
39 |
40 | /* Exported types ------------------------------------------------------------*/
41 |
42 | /** @defgroup EXTI_Exported_Types EXTI Exported Types
43 | * @{
44 | */
45 |
46 | /**
47 | * @brief HAL EXTI common Callback ID enumeration definition
48 | */
49 | typedef enum
50 | {
51 | HAL_EXTI_COMMON_CB_ID = 0x00U
52 | } EXTI_CallbackIDTypeDef;
53 |
54 | /**
55 | * @brief EXTI Handle structure definition
56 | */
57 | typedef struct
58 | {
59 | uint32_t Line; /*!< Exti line number */
60 | void (* PendingCallback)(void); /*!< Exti pending callback */
61 | } EXTI_HandleTypeDef;
62 |
63 | /**
64 | * @brief EXTI Configuration structure definition
65 | */
66 | typedef struct
67 | {
68 | uint32_t Line; /*!< The Exti line to be configured. This parameter
69 | can be a value of @ref EXTI_Line */
70 | uint32_t Mode; /*!< The Exit Mode to be configured for a core.
71 | This parameter can be a combination of @ref EXTI_Mode */
72 | uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
73 | can be a value of @ref EXTI_Trigger */
74 | uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
75 | This parameter is only possible for line 0 to 15. It
76 | can be a value of @ref EXTI_GPIOSel */
77 | } EXTI_ConfigTypeDef;
78 |
79 | /**
80 | * @}
81 | */
82 |
83 | /* Exported constants --------------------------------------------------------*/
84 | /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
85 | * @{
86 | */
87 |
88 | /** @defgroup EXTI_Line EXTI Line
89 | * @{
90 | */
91 | #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
92 | #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
93 | #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
94 | #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
95 | #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
96 | #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
97 | #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
98 | #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
99 | #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
100 | #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
101 | #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
102 | #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
103 | #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
104 | #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
105 | #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
106 | #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
107 | #define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
108 | #define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
109 | #if defined(EXTI_IMR_IM18)
110 | #define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */
111 | #endif /* EXTI_IMR_IM18 */
112 | #if defined(EXTI_IMR_IM19)
113 | #define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
114 | #endif /* EXTI_IMR_IM19 */
115 |
116 | /**
117 | * @}
118 | */
119 |
120 | /** @defgroup EXTI_Mode EXTI Mode
121 | * @{
122 | */
123 | #define EXTI_MODE_NONE 0x00000000u
124 | #define EXTI_MODE_INTERRUPT 0x00000001u
125 | #define EXTI_MODE_EVENT 0x00000002u
126 | /**
127 | * @}
128 | */
129 |
130 | /** @defgroup EXTI_Trigger EXTI Trigger
131 | * @{
132 | */
133 | #define EXTI_TRIGGER_NONE 0x00000000u
134 | #define EXTI_TRIGGER_RISING 0x00000001u
135 | #define EXTI_TRIGGER_FALLING 0x00000002u
136 | #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
137 | /**
138 | * @}
139 | */
140 |
141 | /** @defgroup EXTI_GPIOSel EXTI GPIOSel
142 | * @brief
143 | * @{
144 | */
145 | #define EXTI_GPIOA 0x00000000u
146 | #define EXTI_GPIOB 0x00000001u
147 | #define EXTI_GPIOC 0x00000002u
148 | #define EXTI_GPIOD 0x00000003u
149 | #if defined (GPIOE)
150 | #define EXTI_GPIOE 0x00000004u
151 | #endif /* GPIOE */
152 | #if defined (GPIOF)
153 | #define EXTI_GPIOF 0x00000005u
154 | #endif /* GPIOF */
155 | #if defined (GPIOG)
156 | #define EXTI_GPIOG 0x00000006u
157 | #endif /* GPIOG */
158 | /**
159 | * @}
160 | */
161 |
162 | /**
163 | * @}
164 | */
165 |
166 | /* Exported macro ------------------------------------------------------------*/
167 | /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
168 | * @{
169 | */
170 |
171 | /**
172 | * @}
173 | */
174 |
175 | /* Private constants --------------------------------------------------------*/
176 | /** @defgroup EXTI_Private_Constants EXTI Private Constants
177 | * @{
178 | */
179 | /**
180 | * @brief EXTI Line property definition
181 | */
182 | #define EXTI_PROPERTY_SHIFT 24u
183 | #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
184 | #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
185 | #define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
186 |
187 | /**
188 | * @brief EXTI bit usage
189 | */
190 | #define EXTI_PIN_MASK 0x0000001Fu
191 |
192 | /**
193 | * @brief EXTI Mask for interrupt & event mode
194 | */
195 | #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
196 |
197 | /**
198 | * @brief EXTI Mask for trigger possibilities
199 | */
200 | #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
201 |
202 | /**
203 | * @brief EXTI Line number
204 | */
205 | #if defined(EXTI_IMR_IM19)
206 | #define EXTI_LINE_NB 20UL
207 | #elif defined(EXTI_IMR_IM18)
208 | #define EXTI_LINE_NB 19UL
209 | #else /* EXTI_IMR_IM17 */
210 | #define EXTI_LINE_NB 18UL
211 | #endif /* EXTI_IMR_IM19 */
212 | /**
213 | * @}
214 | */
215 |
216 | /* Private macros ------------------------------------------------------------*/
217 | /** @defgroup EXTI_Private_Macros EXTI Private Macros
218 | * @{
219 | */
220 | #define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
221 | ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
222 | (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
223 | (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
224 |
225 | #define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
226 | (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
227 |
228 | #define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
229 |
230 | #define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
231 |
232 | #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
233 |
234 | #if defined (GPIOG)
235 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
236 | ((__PORT__) == EXTI_GPIOB) || \
237 | ((__PORT__) == EXTI_GPIOC) || \
238 | ((__PORT__) == EXTI_GPIOD) || \
239 | ((__PORT__) == EXTI_GPIOE) || \
240 | ((__PORT__) == EXTI_GPIOF) || \
241 | ((__PORT__) == EXTI_GPIOG))
242 | #elif defined (GPIOF)
243 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
244 | ((__PORT__) == EXTI_GPIOB) || \
245 | ((__PORT__) == EXTI_GPIOC) || \
246 | ((__PORT__) == EXTI_GPIOD) || \
247 | ((__PORT__) == EXTI_GPIOE) || \
248 | ((__PORT__) == EXTI_GPIOF))
249 | #elif defined (GPIOE)
250 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
251 | ((__PORT__) == EXTI_GPIOB) || \
252 | ((__PORT__) == EXTI_GPIOC) || \
253 | ((__PORT__) == EXTI_GPIOD) || \
254 | ((__PORT__) == EXTI_GPIOE))
255 | #else
256 | #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
257 | ((__PORT__) == EXTI_GPIOB) || \
258 | ((__PORT__) == EXTI_GPIOC) || \
259 | ((__PORT__) == EXTI_GPIOD))
260 | #endif /* GPIOG */
261 |
262 | #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
263 |
264 | /**
265 | * @}
266 | */
267 |
268 | /* Exported functions --------------------------------------------------------*/
269 | /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
270 | * @brief EXTI Exported Functions
271 | * @{
272 | */
273 |
274 | /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
275 | * @brief Configuration functions
276 | * @{
277 | */
278 | /* Configuration functions ****************************************************/
279 | HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
280 | HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
281 | HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
282 | HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
283 | HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
284 | /**
285 | * @}
286 | */
287 |
288 | /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
289 | * @brief IO operation functions
290 | * @{
291 | */
292 | /* IO operation functions *****************************************************/
293 | void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
294 | uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
295 | void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
296 | void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
297 |
298 | /**
299 | * @}
300 | */
301 |
302 | /**
303 | * @}
304 | */
305 |
306 | /**
307 | * @}
308 | */
309 |
310 | /**
311 | * @}
312 | */
313 |
314 | #ifdef __cplusplus
315 | }
316 | #endif
317 |
318 | #endif /* STM32F1xx_HAL_EXTI_H */
319 |
320 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
321 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_flash.h
4 | * @author MCD Application Team
5 | * @brief Header file of Flash HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F1xx_HAL_FLASH_H
22 | #define __STM32F1xx_HAL_FLASH_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f1xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F1xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup FLASH
36 | * @{
37 | */
38 |
39 | /** @addtogroup FLASH_Private_Constants
40 | * @{
41 | */
42 | #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
43 | /**
44 | * @}
45 | */
46 |
47 | /** @addtogroup FLASH_Private_Macros
48 | * @{
49 | */
50 |
51 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
52 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
53 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
54 |
55 | #if defined(FLASH_ACR_LATENCY)
56 | #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
57 | ((__LATENCY__) == FLASH_LATENCY_1) || \
58 | ((__LATENCY__) == FLASH_LATENCY_2))
59 |
60 | #else
61 | #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
62 | #endif /* FLASH_ACR_LATENCY */
63 | /**
64 | * @}
65 | */
66 |
67 | /* Exported types ------------------------------------------------------------*/
68 | /** @defgroup FLASH_Exported_Types FLASH Exported Types
69 | * @{
70 | */
71 |
72 | /**
73 | * @brief FLASH Procedure structure definition
74 | */
75 | typedef enum
76 | {
77 | FLASH_PROC_NONE = 0U,
78 | FLASH_PROC_PAGEERASE = 1U,
79 | FLASH_PROC_MASSERASE = 2U,
80 | FLASH_PROC_PROGRAMHALFWORD = 3U,
81 | FLASH_PROC_PROGRAMWORD = 4U,
82 | FLASH_PROC_PROGRAMDOUBLEWORD = 5U
83 | } FLASH_ProcedureTypeDef;
84 |
85 | /**
86 | * @brief FLASH handle Structure definition
87 | */
88 | typedef struct
89 | {
90 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
91 |
92 | __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
93 |
94 | __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
95 |
96 | __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
97 |
98 | HAL_LockTypeDef Lock; /*!< FLASH locking object */
99 |
100 | __IO uint32_t ErrorCode; /*!< FLASH error code
101 | This parameter can be a value of @ref FLASH_Error_Codes */
102 | } FLASH_ProcessTypeDef;
103 |
104 | /**
105 | * @}
106 | */
107 |
108 | /* Exported constants --------------------------------------------------------*/
109 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
110 | * @{
111 | */
112 |
113 | /** @defgroup FLASH_Error_Codes FLASH Error Codes
114 | * @{
115 | */
116 |
117 | #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
118 | #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
119 | #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
120 | #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
121 |
122 | /**
123 | * @}
124 | */
125 |
126 | /** @defgroup FLASH_Type_Program FLASH Type Program
127 | * @{
128 | */
129 | #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA)
183 |
184 | /**
185 | * @brief Disable the FLASH half cycle access.
186 | * @note half cycle access can only be used with a low-frequency clock of less than
187 | 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
188 | * @retval None
189 | */
190 | #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
191 |
192 | /**
193 | * @}
194 | */
195 |
196 | #if defined(FLASH_ACR_LATENCY)
197 | /** @defgroup FLASH_EM_Latency FLASH Latency
198 | * @brief macros to handle FLASH Latency
199 | * @{
200 | */
201 |
202 | /**
203 | * @brief Set the FLASH Latency.
204 | * @param __LATENCY__ FLASH Latency
205 | * The value of this parameter depend on device used within the same series
206 | * @retval None
207 | */
208 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
209 |
210 |
211 | /**
212 | * @brief Get the FLASH Latency.
213 | * @retval FLASH Latency
214 | * The value of this parameter depend on device used within the same series
215 | */
216 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
217 |
218 | /**
219 | * @}
220 | */
221 |
222 | #endif /* FLASH_ACR_LATENCY */
223 | /** @defgroup FLASH_Prefetch FLASH Prefetch
224 | * @brief macros to handle FLASH Prefetch buffer
225 | * @{
226 | */
227 | /**
228 | * @brief Enable the FLASH prefetch buffer.
229 | * @retval None
230 | */
231 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
232 |
233 | /**
234 | * @brief Disable the FLASH prefetch buffer.
235 | * @retval None
236 | */
237 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
238 |
239 | /**
240 | * @}
241 | */
242 |
243 | /**
244 | * @}
245 | */
246 |
247 | /* Include FLASH HAL Extended module */
248 | #include "stm32f1xx_hal_flash_ex.h"
249 |
250 | /* Exported functions --------------------------------------------------------*/
251 | /** @addtogroup FLASH_Exported_Functions
252 | * @{
253 | */
254 |
255 | /** @addtogroup FLASH_Exported_Functions_Group1
256 | * @{
257 | */
258 | /* IO operation functions *****************************************************/
259 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
260 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
261 |
262 | /* FLASH IRQ handler function */
263 | void HAL_FLASH_IRQHandler(void);
264 | /* Callbacks in non blocking modes */
265 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
266 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
267 |
268 | /**
269 | * @}
270 | */
271 |
272 | /** @addtogroup FLASH_Exported_Functions_Group2
273 | * @{
274 | */
275 | /* Peripheral Control functions ***********************************************/
276 | HAL_StatusTypeDef HAL_FLASH_Unlock(void);
277 | HAL_StatusTypeDef HAL_FLASH_Lock(void);
278 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
279 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
280 | void HAL_FLASH_OB_Launch(void);
281 |
282 | /**
283 | * @}
284 | */
285 |
286 | /** @addtogroup FLASH_Exported_Functions_Group3
287 | * @{
288 | */
289 | /* Peripheral State and Error functions ***************************************/
290 | uint32_t HAL_FLASH_GetError(void);
291 |
292 | /**
293 | * @}
294 | */
295 |
296 | /**
297 | * @}
298 | */
299 |
300 | /* Private function -------------------------------------------------*/
301 | /** @addtogroup FLASH_Private_Functions
302 | * @{
303 | */
304 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
305 | #if defined(FLASH_BANK2_END)
306 | HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
307 | #endif /* FLASH_BANK2_END */
308 |
309 | /**
310 | * @}
311 | */
312 |
313 | /**
314 | * @}
315 | */
316 |
317 | /**
318 | * @}
319 | */
320 |
321 | #ifdef __cplusplus
322 | }
323 | #endif
324 |
325 | #endif /* __STM32F1xx_HAL_FLASH_H */
326 |
327 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
328 |
329 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_gpio.h
4 | * @author MCD Application Team
5 | * @brief Header file of GPIO HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32F1xx_HAL_GPIO_H
22 | #define STM32F1xx_HAL_GPIO_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f1xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F1xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup GPIO
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup GPIO_Exported_Types GPIO Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief GPIO Init structure definition
46 | */
47 | typedef struct
48 | {
49 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
50 | This parameter can be any value of @ref GPIO_pins_define */
51 |
52 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
53 | This parameter can be a value of @ref GPIO_mode_define */
54 |
55 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
56 | This parameter can be a value of @ref GPIO_pull_define */
57 |
58 | uint32_t Speed; /*!< Specifies the speed for the selected pins.
59 | This parameter can be a value of @ref GPIO_speed_define */
60 | } GPIO_InitTypeDef;
61 |
62 | /**
63 | * @brief GPIO Bit SET and Bit RESET enumeration
64 | */
65 | typedef enum
66 | {
67 | GPIO_PIN_RESET = 0u,
68 | GPIO_PIN_SET
69 | } GPIO_PinState;
70 | /**
71 | * @}
72 | */
73 |
74 | /* Exported constants --------------------------------------------------------*/
75 |
76 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
77 | * @{
78 | */
79 |
80 | /** @defgroup GPIO_pins_define GPIO pins define
81 | * @{
82 | */
83 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
84 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
85 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
86 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
87 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
88 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
89 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
90 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
91 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
92 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
93 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
94 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
95 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
96 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
97 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
98 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
99 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
100 |
101 | #define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */
102 | /**
103 | * @}
104 | */
105 |
106 | /** @defgroup GPIO_mode_define GPIO mode define
107 | * @brief GPIO Configuration Mode
108 | * Elements values convention: 0xX0yz00YZ
109 | * - X : GPIO mode or EXTI Mode
110 | * - y : External IT or Event trigger detection
111 | * - z : IO configuration on External IT or Event
112 | * - Y : Output type (Push Pull or Open Drain)
113 | * - Z : IO Direction mode (Input, Output, Alternate or Analog)
114 | * @{
115 | */
116 | #define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */
117 | #define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */
118 | #define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */
119 | #define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */
120 | #define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */
121 | #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
122 |
123 | #define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */
124 |
125 | #define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */
126 | #define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */
127 | #define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
128 |
129 | #define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */
130 | #define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */
131 | #define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */
132 |
133 | /**
134 | * @}
135 | */
136 |
137 | /** @defgroup GPIO_speed_define GPIO speed define
138 | * @brief GPIO Output Maximum frequency
139 | * @{
140 | */
141 | #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
142 | #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
143 | #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
144 |
145 | /**
146 | * @}
147 | */
148 |
149 | /** @defgroup GPIO_pull_define GPIO pull define
150 | * @brief GPIO Pull-Up or Pull-Down Activation
151 | * @{
152 | */
153 | #define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
154 | #define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
155 | #define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
156 | /**
157 | * @}
158 | */
159 |
160 | /**
161 | * @}
162 | */
163 |
164 | /* Exported macro ------------------------------------------------------------*/
165 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
166 | * @{
167 | */
168 |
169 | /**
170 | * @brief Checks whether the specified EXTI line flag is set or not.
171 | * @param __EXTI_LINE__: specifies the EXTI line flag to check.
172 | * This parameter can be GPIO_PIN_x where x can be(0..15)
173 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
174 | */
175 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
176 |
177 | /**
178 | * @brief Clears the EXTI's line pending flags.
179 | * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
180 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
181 | * @retval None
182 | */
183 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
184 |
185 | /**
186 | * @brief Checks whether the specified EXTI line is asserted or not.
187 | * @param __EXTI_LINE__: specifies the EXTI line to check.
188 | * This parameter can be GPIO_PIN_x where x can be(0..15)
189 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
190 | */
191 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
192 |
193 | /**
194 | * @brief Clears the EXTI's line pending bits.
195 | * @param __EXTI_LINE__: specifies the EXTI lines to clear.
196 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
197 | * @retval None
198 | */
199 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
200 |
201 | /**
202 | * @brief Generates a Software interrupt on selected EXTI line.
203 | * @param __EXTI_LINE__: specifies the EXTI line to check.
204 | * This parameter can be GPIO_PIN_x where x can be(0..15)
205 | * @retval None
206 | */
207 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
208 | /**
209 | * @}
210 | */
211 |
212 | /* Include GPIO HAL Extension module */
213 | #include "stm32f1xx_hal_gpio_ex.h"
214 |
215 | /* Exported functions --------------------------------------------------------*/
216 | /** @addtogroup GPIO_Exported_Functions
217 | * @{
218 | */
219 |
220 | /** @addtogroup GPIO_Exported_Functions_Group1
221 | * @{
222 | */
223 | /* Initialization and de-initialization functions *****************************/
224 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
225 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
226 | /**
227 | * @}
228 | */
229 |
230 | /** @addtogroup GPIO_Exported_Functions_Group2
231 | * @{
232 | */
233 | /* IO operation functions *****************************************************/
234 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
235 | void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
236 | void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
237 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
238 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
239 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
240 |
241 | /**
242 | * @}
243 | */
244 |
245 | /**
246 | * @}
247 | */
248 | /* Private types -------------------------------------------------------------*/
249 | /* Private variables ---------------------------------------------------------*/
250 | /* Private constants ---------------------------------------------------------*/
251 | /** @defgroup GPIO_Private_Constants GPIO Private Constants
252 | * @{
253 | */
254 |
255 | /**
256 | * @}
257 | */
258 |
259 | /* Private macros ------------------------------------------------------------*/
260 | /** @defgroup GPIO_Private_Macros GPIO Private Macros
261 | * @{
262 | */
263 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
264 | #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u))
265 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
266 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
267 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
268 | ((MODE) == GPIO_MODE_AF_PP) ||\
269 | ((MODE) == GPIO_MODE_AF_OD) ||\
270 | ((MODE) == GPIO_MODE_IT_RISING) ||\
271 | ((MODE) == GPIO_MODE_IT_FALLING) ||\
272 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
273 | ((MODE) == GPIO_MODE_EVT_RISING) ||\
274 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\
275 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
276 | ((MODE) == GPIO_MODE_ANALOG))
277 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
278 | ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
279 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
280 | ((PULL) == GPIO_PULLDOWN))
281 | /**
282 | * @}
283 | */
284 |
285 | /* Private functions ---------------------------------------------------------*/
286 | /** @defgroup GPIO_Private_Functions GPIO Private Functions
287 | * @{
288 | */
289 |
290 | /**
291 | * @}
292 | */
293 |
294 | /**
295 | * @}
296 | */
297 |
298 | /**
299 | * @}
300 | */
301 |
302 | #ifdef __cplusplus
303 | }
304 | #endif
305 |
306 | #endif /* STM32F1xx_HAL_GPIO_H */
307 |
308 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
309 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_pwr.h
4 | * @author MCD Application Team
5 | * @brief Header file of PWR HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F1xx_HAL_PWR_H
22 | #define __STM32F1xx_HAL_PWR_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f1xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F1xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup PWR
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 |
41 | /** @defgroup PWR_Exported_Types PWR Exported Types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief PWR PVD configuration structure definition
47 | */
48 | typedef struct
49 | {
50 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
51 | This parameter can be a value of @ref PWR_PVD_detection_level */
52 |
53 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
54 | This parameter can be a value of @ref PWR_PVD_Mode */
55 | }PWR_PVDTypeDef;
56 |
57 |
58 | /**
59 | * @}
60 | */
61 |
62 |
63 | /* Internal constants --------------------------------------------------------*/
64 |
65 | /** @addtogroup PWR_Private_Constants
66 | * @{
67 | */
68 |
69 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 |
76 | /* Exported constants --------------------------------------------------------*/
77 |
78 | /** @defgroup PWR_Exported_Constants PWR Exported Constants
79 | * @{
80 | */
81 |
82 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level
83 | * @{
84 | */
85 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
86 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
87 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
88 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
89 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
90 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
91 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
92 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /** @defgroup PWR_PVD_Mode PWR PVD Mode
99 | * @{
100 | */
101 | #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
102 | #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
103 | #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
104 | #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
105 | #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
106 | #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
107 | #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
108 |
109 | /**
110 | * @}
111 | */
112 |
113 |
114 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
115 | * @{
116 | */
117 |
118 | #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
119 |
120 | /**
121 | * @}
122 | */
123 |
124 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
125 | * @{
126 | */
127 | #define PWR_MAINREGULATOR_ON 0x00000000U
128 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
129 |
130 | /**
131 | * @}
132 | */
133 |
134 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
135 | * @{
136 | */
137 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
138 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
139 |
140 | /**
141 | * @}
142 | */
143 |
144 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
145 | * @{
146 | */
147 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
148 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /** @defgroup PWR_Flag PWR Flag
155 | * @{
156 | */
157 | #define PWR_FLAG_WU PWR_CSR_WUF
158 | #define PWR_FLAG_SB PWR_CSR_SBF
159 | #define PWR_FLAG_PVDO PWR_CSR_PVDO
160 |
161 |
162 | /**
163 | * @}
164 | */
165 |
166 | /**
167 | * @}
168 | */
169 |
170 | /* Exported macro ------------------------------------------------------------*/
171 | /** @defgroup PWR_Exported_Macros PWR Exported Macros
172 | * @{
173 | */
174 |
175 | /** @brief Check PWR flag is set or not.
176 | * @param __FLAG__: specifies the flag to check.
177 | * This parameter can be one of the following values:
178 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
179 | * was received from the WKUP pin or from the RTC alarm
180 | * An additional wakeup event is detected if the WKUP pin is enabled
181 | * (by setting the EWUP bit) when the WKUP pin level is already high.
182 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
183 | * resumed from StandBy mode.
184 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
185 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
186 | * For this reason, this bit is equal to 0 after Standby or reset
187 | * until the PVDE bit is set.
188 | * @retval The new state of __FLAG__ (TRUE or FALSE).
189 | */
190 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
191 |
192 | /** @brief Clear the PWR's pending flags.
193 | * @param __FLAG__: specifies the flag to clear.
194 | * This parameter can be one of the following values:
195 | * @arg PWR_FLAG_WU: Wake Up flag
196 | * @arg PWR_FLAG_SB: StandBy flag
197 | */
198 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
199 |
200 | /**
201 | * @brief Enable interrupt on PVD Exti Line 16.
202 | * @retval None.
203 | */
204 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
205 |
206 | /**
207 | * @brief Disable interrupt on PVD Exti Line 16.
208 | * @retval None.
209 | */
210 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
211 |
212 | /**
213 | * @brief Enable event on PVD Exti Line 16.
214 | * @retval None.
215 | */
216 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
217 |
218 | /**
219 | * @brief Disable event on PVD Exti Line 16.
220 | * @retval None.
221 | */
222 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
223 |
224 |
225 | /**
226 | * @brief PVD EXTI line configuration: set falling edge trigger.
227 | * @retval None.
228 | */
229 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
230 |
231 |
232 | /**
233 | * @brief Disable the PVD Extended Interrupt Falling Trigger.
234 | * @retval None.
235 | */
236 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
237 |
238 |
239 | /**
240 | * @brief PVD EXTI line configuration: set rising edge trigger.
241 | * @retval None.
242 | */
243 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
244 |
245 | /**
246 | * @brief Disable the PVD Extended Interrupt Rising Trigger.
247 | * This parameter can be:
248 | * @retval None.
249 | */
250 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
251 |
252 | /**
253 | * @brief PVD EXTI line configuration: set rising & falling edge trigger.
254 | * @retval None.
255 | */
256 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
257 |
258 | /**
259 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
260 | * This parameter can be:
261 | * @retval None.
262 | */
263 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
264 |
265 |
266 |
267 | /**
268 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
269 | * @retval EXTI PVD Line Status.
270 | */
271 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
272 |
273 | /**
274 | * @brief Clear the PVD EXTI flag.
275 | * @retval None.
276 | */
277 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
278 |
279 | /**
280 | * @brief Generate a Software interrupt on selected EXTI line.
281 | * @retval None.
282 | */
283 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
284 | /**
285 | * @}
286 | */
287 |
288 | /* Private macro -------------------------------------------------------------*/
289 | /** @defgroup PWR_Private_Macros PWR Private Macros
290 | * @{
291 | */
292 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
293 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
294 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
295 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
296 |
297 |
298 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
299 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
300 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
301 | ((MODE) == PWR_PVD_MODE_NORMAL))
302 |
303 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
304 |
305 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
306 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
307 |
308 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
309 |
310 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
311 |
312 | /**
313 | * @}
314 | */
315 |
316 |
317 |
318 | /* Exported functions --------------------------------------------------------*/
319 |
320 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions
321 | * @{
322 | */
323 |
324 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
325 | * @{
326 | */
327 |
328 | /* Initialization and de-initialization functions *******************************/
329 | void HAL_PWR_DeInit(void);
330 | void HAL_PWR_EnableBkUpAccess(void);
331 | void HAL_PWR_DisableBkUpAccess(void);
332 |
333 | /**
334 | * @}
335 | */
336 |
337 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
338 | * @{
339 | */
340 |
341 | /* Peripheral Control functions ************************************************/
342 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
343 | /* #define HAL_PWR_ConfigPVD 12*/
344 | void HAL_PWR_EnablePVD(void);
345 | void HAL_PWR_DisablePVD(void);
346 |
347 | /* WakeUp pins configuration functions ****************************************/
348 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
349 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
350 |
351 | /* Low Power modes configuration functions ************************************/
352 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
353 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
354 | void HAL_PWR_EnterSTANDBYMode(void);
355 |
356 | void HAL_PWR_EnableSleepOnExit(void);
357 | void HAL_PWR_DisableSleepOnExit(void);
358 | void HAL_PWR_EnableSEVOnPend(void);
359 | void HAL_PWR_DisableSEVOnPend(void);
360 |
361 |
362 |
363 | void HAL_PWR_PVD_IRQHandler(void);
364 | void HAL_PWR_PVDCallback(void);
365 | /**
366 | * @}
367 | */
368 |
369 | /**
370 | * @}
371 | */
372 |
373 | /**
374 | * @}
375 | */
376 |
377 | /**
378 | * @}
379 | */
380 |
381 | #ifdef __cplusplus
382 | }
383 | #endif
384 |
385 |
386 | #endif /* __STM32F1xx_HAL_PWR_H */
387 |
388 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
389 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_tim_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of TIM HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2016 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32F1xx_HAL_TIM_EX_H
22 | #define STM32F1xx_HAL_TIM_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f1xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F1xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup TIMEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief TIM Hall sensor Configuration Structure definition
46 | */
47 |
48 | typedef struct
49 | {
50 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
51 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */
52 |
53 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
54 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
55 |
56 | uint32_t IC1Filter; /*!< Specifies the input capture filter.
57 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
58 |
59 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
60 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
61 | } TIM_HallSensor_InitTypeDef;
62 | /**
63 | * @}
64 | */
65 | /* End of exported types -----------------------------------------------------*/
66 |
67 | /* Exported constants --------------------------------------------------------*/
68 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
69 | * @{
70 | */
71 |
72 | /** @defgroup TIMEx_Remap TIM Extended Remapping
73 | * @{
74 | */
75 | /**
76 | * @}
77 | */
78 |
79 | /**
80 | * @}
81 | */
82 | /* End of exported constants -------------------------------------------------*/
83 |
84 | /* Exported macro ------------------------------------------------------------*/
85 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
86 | * @{
87 | */
88 |
89 | /**
90 | * @}
91 | */
92 | /* End of exported macro -----------------------------------------------------*/
93 |
94 | /* Private macro -------------------------------------------------------------*/
95 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
96 | * @{
97 | */
98 |
99 | /**
100 | * @}
101 | */
102 | /* End of private macro ------------------------------------------------------*/
103 |
104 | /* Exported functions --------------------------------------------------------*/
105 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
106 | * @{
107 | */
108 |
109 | /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
110 | * @brief Timer Hall Sensor functions
111 | * @{
112 | */
113 | /* Timer Hall Sensor functions **********************************************/
114 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
115 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
116 |
117 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
118 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
119 |
120 | /* Blocking mode: Polling */
121 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
122 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
123 | /* Non-Blocking mode: Interrupt */
124 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
125 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
126 | /* Non-Blocking mode: DMA */
127 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
128 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
129 | /**
130 | * @}
131 | */
132 |
133 | /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
134 | * @brief Timer Complementary Output Compare functions
135 | * @{
136 | */
137 | /* Timer Complementary Output Compare functions *****************************/
138 | /* Blocking mode: Polling */
139 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
140 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
141 |
142 | /* Non-Blocking mode: Interrupt */
143 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
144 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
145 |
146 | /* Non-Blocking mode: DMA */
147 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
148 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
149 | /**
150 | * @}
151 | */
152 |
153 | /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
154 | * @brief Timer Complementary PWM functions
155 | * @{
156 | */
157 | /* Timer Complementary PWM functions ****************************************/
158 | /* Blocking mode: Polling */
159 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
160 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
161 |
162 | /* Non-Blocking mode: Interrupt */
163 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
164 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
165 | /* Non-Blocking mode: DMA */
166 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
167 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
168 | /**
169 | * @}
170 | */
171 |
172 | /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
173 | * @brief Timer Complementary One Pulse functions
174 | * @{
175 | */
176 | /* Timer Complementary One Pulse functions **********************************/
177 | /* Blocking mode: Polling */
178 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
179 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
180 |
181 | /* Non-Blocking mode: Interrupt */
182 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
183 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
184 | /**
185 | * @}
186 | */
187 |
188 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
189 | * @brief Peripheral Control functions
190 | * @{
191 | */
192 | /* Extended Control functions ************************************************/
193 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
194 | uint32_t CommutationSource);
195 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
196 | uint32_t CommutationSource);
197 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
198 | uint32_t CommutationSource);
199 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
200 | TIM_MasterConfigTypeDef *sMasterConfig);
201 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
202 | TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
203 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
204 | /**
205 | * @}
206 | */
207 |
208 | /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
209 | * @brief Extended Callbacks functions
210 | * @{
211 | */
212 | /* Extended Callback **********************************************************/
213 | void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
214 | void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
215 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
216 | /**
217 | * @}
218 | */
219 |
220 | /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
221 | * @brief Extended Peripheral State functions
222 | * @{
223 | */
224 | /* Extended Peripheral State functions ***************************************/
225 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
226 | HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
227 | /**
228 | * @}
229 | */
230 |
231 | /**
232 | * @}
233 | */
234 | /* End of exported functions -------------------------------------------------*/
235 |
236 | /* Private functions----------------------------------------------------------*/
237 | /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
238 | * @{
239 | */
240 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
241 | void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
242 | /**
243 | * @}
244 | */
245 | /* End of private functions --------------------------------------------------*/
246 |
247 | /**
248 | * @}
249 | */
250 |
251 | /**
252 | * @}
253 | */
254 |
255 | #ifdef __cplusplus
256 | }
257 | #endif
258 |
259 |
260 | #endif /* STM32F1xx_HAL_TIM_EX_H */
261 |
262 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
263 |
--------------------------------------------------------------------------------
/demo/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_hal_gpio_ex.c
4 | * @author MCD Application Team
5 | * @brief GPIO Extension HAL module driver.
6 | * This file provides firmware functions to manage the following
7 | * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
8 | * + Extended features functions
9 | *
10 | @verbatim
11 | ==============================================================================
12 | ##### GPIO Peripheral extension features #####
13 | ==============================================================================
14 | [..] GPIO module on STM32F1 family, manage also the AFIO register:
15 | (+) Possibility to use the EVENTOUT Cortex feature
16 |
17 | ##### How to use this driver #####
18 | ==============================================================================
19 | [..] This driver provides functions to use EVENTOUT Cortex feature
20 | (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
21 | (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
22 | (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
23 |
24 | @endverbatim
25 | ******************************************************************************
26 | * @attention
27 | *
28 | * © Copyright (c) 2016 STMicroelectronics.
29 | * All rights reserved.
30 | *
31 | * This software component is licensed by ST under BSD 3-Clause license,
32 | * the "License"; You may not use this file except in compliance with the
33 | * License. You may obtain a copy of the License at:
34 | * opensource.org/licenses/BSD-3-Clause
35 | *
36 | ******************************************************************************
37 | */
38 |
39 | /* Includes ------------------------------------------------------------------*/
40 | #include "stm32f1xx_hal.h"
41 |
42 | /** @addtogroup STM32F1xx_HAL_Driver
43 | * @{
44 | */
45 |
46 | /** @defgroup GPIOEx GPIOEx
47 | * @brief GPIO HAL module driver
48 | * @{
49 | */
50 |
51 | #ifdef HAL_GPIO_MODULE_ENABLED
52 |
53 | /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
54 | * @{
55 | */
56 |
57 | /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
58 | * @brief Extended features functions
59 | *
60 | @verbatim
61 | ==============================================================================
62 | ##### Extended features functions #####
63 | ==============================================================================
64 | [..] This section provides functions allowing to:
65 | (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
66 | (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
67 | (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
68 |
69 | @endverbatim
70 | * @{
71 | */
72 |
73 | /**
74 | * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
75 | * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
76 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
77 | * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
78 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
79 | * @retval None
80 | */
81 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
82 | {
83 | /* Verify the parameters */
84 | assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
85 | assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
86 |
87 | /* Apply the new configuration */
88 | MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));
89 | }
90 |
91 | /**
92 | * @brief Enables the Event Output.
93 | * @retval None
94 | */
95 | void HAL_GPIOEx_EnableEventout(void)
96 | {
97 | SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
98 | }
99 |
100 | /**
101 | * @brief Disables the Event Output.
102 | * @retval None
103 | */
104 | void HAL_GPIOEx_DisableEventout(void)
105 | {
106 | CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
107 | }
108 |
109 | /**
110 | * @}
111 | */
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | #endif /* HAL_GPIO_MODULE_ENABLED */
118 |
119 | /**
120 | * @}
121 | */
122 |
123 | /**
124 | * @}
125 | */
126 |
127 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
128 |
--------------------------------------------------------------------------------
/demo/Inc/main.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * Copyright (c) 2021 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software is licensed under terms that can be found in the LICENSE file
14 | * in the root directory of this software component.
15 | * If no LICENSE file comes with this software, it is provided AS-IS.
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __MAIN_H
23 | #define __MAIN_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f1xx_hal.h"
31 |
32 | /* Private includes ----------------------------------------------------------*/
33 | /* USER CODE BEGIN Includes */
34 |
35 | /* USER CODE END Includes */
36 |
37 | /* Exported types ------------------------------------------------------------*/
38 | /* USER CODE BEGIN ET */
39 |
40 | /* USER CODE END ET */
41 |
42 | /* Exported constants --------------------------------------------------------*/
43 | /* USER CODE BEGIN EC */
44 |
45 | /* USER CODE END EC */
46 |
47 | /* Exported macro ------------------------------------------------------------*/
48 | /* USER CODE BEGIN EM */
49 |
50 | /* USER CODE END EM */
51 |
52 | /* Exported functions prototypes ---------------------------------------------*/
53 | void Error_Handler(void);
54 |
55 | /* USER CODE BEGIN EFP */
56 |
57 | /* USER CODE END EFP */
58 |
59 | /* Private defines -----------------------------------------------------------*/
60 | /* USER CODE BEGIN Private defines */
61 |
62 | /* USER CODE END Private defines */
63 |
64 | #ifdef __cplusplus
65 | }
66 | #endif
67 |
68 | #endif /* __MAIN_H */
69 |
--------------------------------------------------------------------------------
/demo/Inc/stm32f1xx_it.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f1xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file
13 | * in the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 | /* USER CODE END Header */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F1xx_IT_H
22 | #define __STM32F1xx_IT_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Private includes ----------------------------------------------------------*/
29 | /* USER CODE BEGIN Includes */
30 |
31 | /* USER CODE END Includes */
32 |
33 | /* Exported types ------------------------------------------------------------*/
34 | /* USER CODE BEGIN ET */
35 |
36 | /* USER CODE END ET */
37 |
38 | /* Exported constants --------------------------------------------------------*/
39 | /* USER CODE BEGIN EC */
40 |
41 | /* USER CODE END EC */
42 |
43 | /* Exported macro ------------------------------------------------------------*/
44 | /* USER CODE BEGIN EM */
45 |
46 | /* USER CODE END EM */
47 |
48 | /* Exported functions prototypes ---------------------------------------------*/
49 | void NMI_Handler(void);
50 | void HardFault_Handler(void);
51 | void MemManage_Handler(void);
52 | void BusFault_Handler(void);
53 | void UsageFault_Handler(void);
54 | void SVC_Handler(void);
55 | void DebugMon_Handler(void);
56 | void PendSV_Handler(void);
57 | void SysTick_Handler(void);
58 | /* USER CODE BEGIN EFP */
59 |
60 | /* USER CODE END EFP */
61 |
62 | #ifdef __cplusplus
63 | }
64 | #endif
65 |
66 | #endif /* __STM32F1xx_IT_H */
67 |
--------------------------------------------------------------------------------
/demo/MDK-ARM/startup_stm32f103xb.s:
--------------------------------------------------------------------------------
1 | ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
2 | ;* File Name : startup_stm32f103xb.s
3 | ;* Author : MCD Application Team
4 | ;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
5 | ;* This module performs:
6 | ;* - Set the initial SP
7 | ;* - Set the initial PC == Reset_Handler
8 | ;* - Set the vector table entries with the exceptions ISR address
9 | ;* - Configure the clock system
10 | ;* - Branches to __main in the C library (which eventually
11 | ;* calls main()).
12 | ;* After Reset the Cortex-M3 processor is in Thread mode,
13 | ;* priority is Privileged, and the Stack is set to Main.
14 | ;******************************************************************************
15 | ;* @attention
16 | ;*
17 | ;* Copyright (c) 2017 STMicroelectronics.
18 | ;* All rights reserved.
19 | ;*
20 | ;* This software component is licensed by ST under BSD 3-Clause license,
21 | ;* the "License"; You may not use this file except in compliance with the
22 | ;* License. You may obtain a copy of the License at:
23 | ;* opensource.org/licenses/BSD-3-Clause
24 | ;*
25 | ;******************************************************************************
26 |
27 | ; Amount of memory (in bytes) allocated for Stack
28 | ; Tailor this value to your application needs
29 | ; Stack Configuration
30 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31 | ;
32 |
33 | Stack_Size EQU 0x400
34 |
35 | AREA STACK, NOINIT, READWRITE, ALIGN=3
36 | Stack_Mem SPACE Stack_Size
37 | __initial_sp
38 |
39 |
40 | ; Heap Configuration
41 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
42 | ;
43 |
44 | Heap_Size EQU 0x200
45 |
46 | AREA HEAP, NOINIT, READWRITE, ALIGN=3
47 | __heap_base
48 | Heap_Mem SPACE Heap_Size
49 | __heap_limit
50 |
51 | PRESERVE8
52 | THUMB
53 |
54 |
55 | ; Vector Table Mapped to Address 0 at Reset
56 | AREA RESET, DATA, READONLY
57 | EXPORT __Vectors
58 | EXPORT __Vectors_End
59 | EXPORT __Vectors_Size
60 |
61 | __Vectors DCD __initial_sp ; Top of Stack
62 | DCD Reset_Handler ; Reset Handler
63 | DCD NMI_Handler ; NMI Handler
64 | DCD HardFault_Handler ; Hard Fault Handler
65 | DCD MemManage_Handler ; MPU Fault Handler
66 | DCD BusFault_Handler ; Bus Fault Handler
67 | DCD UsageFault_Handler ; Usage Fault Handler
68 | DCD 0 ; Reserved
69 | DCD 0 ; Reserved
70 | DCD 0 ; Reserved
71 | DCD 0 ; Reserved
72 | DCD SVC_Handler ; SVCall Handler
73 | DCD DebugMon_Handler ; Debug Monitor Handler
74 | DCD 0 ; Reserved
75 | DCD PendSV_Handler ; PendSV Handler
76 | DCD SysTick_Handler ; SysTick Handler
77 |
78 | ; External Interrupts
79 | DCD WWDG_IRQHandler ; Window Watchdog
80 | DCD PVD_IRQHandler ; PVD through EXTI Line detect
81 | DCD TAMPER_IRQHandler ; Tamper
82 | DCD RTC_IRQHandler ; RTC
83 | DCD FLASH_IRQHandler ; Flash
84 | DCD RCC_IRQHandler ; RCC
85 | DCD EXTI0_IRQHandler ; EXTI Line 0
86 | DCD EXTI1_IRQHandler ; EXTI Line 1
87 | DCD EXTI2_IRQHandler ; EXTI Line 2
88 | DCD EXTI3_IRQHandler ; EXTI Line 3
89 | DCD EXTI4_IRQHandler ; EXTI Line 4
90 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
91 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
92 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
93 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
94 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
95 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
96 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
97 | DCD ADC1_2_IRQHandler ; ADC1_2
98 | DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
99 | DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
100 | DCD CAN1_RX1_IRQHandler ; CAN1 RX1
101 | DCD CAN1_SCE_IRQHandler ; CAN1 SCE
102 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
103 | DCD TIM1_BRK_IRQHandler ; TIM1 Break
104 | DCD TIM1_UP_IRQHandler ; TIM1 Update
105 | DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
106 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
107 | DCD TIM2_IRQHandler ; TIM2
108 | DCD TIM3_IRQHandler ; TIM3
109 | DCD TIM4_IRQHandler ; TIM4
110 | DCD I2C1_EV_IRQHandler ; I2C1 Event
111 | DCD I2C1_ER_IRQHandler ; I2C1 Error
112 | DCD I2C2_EV_IRQHandler ; I2C2 Event
113 | DCD I2C2_ER_IRQHandler ; I2C2 Error
114 | DCD SPI1_IRQHandler ; SPI1
115 | DCD SPI2_IRQHandler ; SPI2
116 | DCD USART1_IRQHandler ; USART1
117 | DCD USART2_IRQHandler ; USART2
118 | DCD USART3_IRQHandler ; USART3
119 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
120 | DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
121 | DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
122 | __Vectors_End
123 |
124 | __Vectors_Size EQU __Vectors_End - __Vectors
125 |
126 | AREA |.text|, CODE, READONLY
127 |
128 | ; Reset handler
129 | Reset_Handler PROC
130 | EXPORT Reset_Handler [WEAK]
131 | IMPORT __main
132 | IMPORT SystemInit
133 | LDR R0, =SystemInit
134 | BLX R0
135 | LDR R0, =__main
136 | BX R0
137 | ENDP
138 |
139 | ; Dummy Exception Handlers (infinite loops which can be modified)
140 |
141 | NMI_Handler PROC
142 | EXPORT NMI_Handler [WEAK]
143 | B .
144 | ENDP
145 | HardFault_Handler\
146 | PROC
147 | EXPORT HardFault_Handler [WEAK]
148 | B .
149 | ENDP
150 | MemManage_Handler\
151 | PROC
152 | EXPORT MemManage_Handler [WEAK]
153 | B .
154 | ENDP
155 | BusFault_Handler\
156 | PROC
157 | EXPORT BusFault_Handler [WEAK]
158 | B .
159 | ENDP
160 | UsageFault_Handler\
161 | PROC
162 | EXPORT UsageFault_Handler [WEAK]
163 | B .
164 | ENDP
165 | SVC_Handler PROC
166 | EXPORT SVC_Handler [WEAK]
167 | B .
168 | ENDP
169 | DebugMon_Handler\
170 | PROC
171 | EXPORT DebugMon_Handler [WEAK]
172 | B .
173 | ENDP
174 | PendSV_Handler PROC
175 | EXPORT PendSV_Handler [WEAK]
176 | B .
177 | ENDP
178 | SysTick_Handler PROC
179 | EXPORT SysTick_Handler [WEAK]
180 | B .
181 | ENDP
182 |
183 | Default_Handler PROC
184 |
185 | EXPORT WWDG_IRQHandler [WEAK]
186 | EXPORT PVD_IRQHandler [WEAK]
187 | EXPORT TAMPER_IRQHandler [WEAK]
188 | EXPORT RTC_IRQHandler [WEAK]
189 | EXPORT FLASH_IRQHandler [WEAK]
190 | EXPORT RCC_IRQHandler [WEAK]
191 | EXPORT EXTI0_IRQHandler [WEAK]
192 | EXPORT EXTI1_IRQHandler [WEAK]
193 | EXPORT EXTI2_IRQHandler [WEAK]
194 | EXPORT EXTI3_IRQHandler [WEAK]
195 | EXPORT EXTI4_IRQHandler [WEAK]
196 | EXPORT DMA1_Channel1_IRQHandler [WEAK]
197 | EXPORT DMA1_Channel2_IRQHandler [WEAK]
198 | EXPORT DMA1_Channel3_IRQHandler [WEAK]
199 | EXPORT DMA1_Channel4_IRQHandler [WEAK]
200 | EXPORT DMA1_Channel5_IRQHandler [WEAK]
201 | EXPORT DMA1_Channel6_IRQHandler [WEAK]
202 | EXPORT DMA1_Channel7_IRQHandler [WEAK]
203 | EXPORT ADC1_2_IRQHandler [WEAK]
204 | EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
205 | EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
206 | EXPORT CAN1_RX1_IRQHandler [WEAK]
207 | EXPORT CAN1_SCE_IRQHandler [WEAK]
208 | EXPORT EXTI9_5_IRQHandler [WEAK]
209 | EXPORT TIM1_BRK_IRQHandler [WEAK]
210 | EXPORT TIM1_UP_IRQHandler [WEAK]
211 | EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
212 | EXPORT TIM1_CC_IRQHandler [WEAK]
213 | EXPORT TIM2_IRQHandler [WEAK]
214 | EXPORT TIM3_IRQHandler [WEAK]
215 | EXPORT TIM4_IRQHandler [WEAK]
216 | EXPORT I2C1_EV_IRQHandler [WEAK]
217 | EXPORT I2C1_ER_IRQHandler [WEAK]
218 | EXPORT I2C2_EV_IRQHandler [WEAK]
219 | EXPORT I2C2_ER_IRQHandler [WEAK]
220 | EXPORT SPI1_IRQHandler [WEAK]
221 | EXPORT SPI2_IRQHandler [WEAK]
222 | EXPORT USART1_IRQHandler [WEAK]
223 | EXPORT USART2_IRQHandler [WEAK]
224 | EXPORT USART3_IRQHandler [WEAK]
225 | EXPORT EXTI15_10_IRQHandler [WEAK]
226 | EXPORT RTC_Alarm_IRQHandler [WEAK]
227 | EXPORT USBWakeUp_IRQHandler [WEAK]
228 |
229 | WWDG_IRQHandler
230 | PVD_IRQHandler
231 | TAMPER_IRQHandler
232 | RTC_IRQHandler
233 | FLASH_IRQHandler
234 | RCC_IRQHandler
235 | EXTI0_IRQHandler
236 | EXTI1_IRQHandler
237 | EXTI2_IRQHandler
238 | EXTI3_IRQHandler
239 | EXTI4_IRQHandler
240 | DMA1_Channel1_IRQHandler
241 | DMA1_Channel2_IRQHandler
242 | DMA1_Channel3_IRQHandler
243 | DMA1_Channel4_IRQHandler
244 | DMA1_Channel5_IRQHandler
245 | DMA1_Channel6_IRQHandler
246 | DMA1_Channel7_IRQHandler
247 | ADC1_2_IRQHandler
248 | USB_HP_CAN1_TX_IRQHandler
249 | USB_LP_CAN1_RX0_IRQHandler
250 | CAN1_RX1_IRQHandler
251 | CAN1_SCE_IRQHandler
252 | EXTI9_5_IRQHandler
253 | TIM1_BRK_IRQHandler
254 | TIM1_UP_IRQHandler
255 | TIM1_TRG_COM_IRQHandler
256 | TIM1_CC_IRQHandler
257 | TIM2_IRQHandler
258 | TIM3_IRQHandler
259 | TIM4_IRQHandler
260 | I2C1_EV_IRQHandler
261 | I2C1_ER_IRQHandler
262 | I2C2_EV_IRQHandler
263 | I2C2_ER_IRQHandler
264 | SPI1_IRQHandler
265 | SPI2_IRQHandler
266 | USART1_IRQHandler
267 | USART2_IRQHandler
268 | USART3_IRQHandler
269 | EXTI15_10_IRQHandler
270 | RTC_Alarm_IRQHandler
271 | USBWakeUp_IRQHandler
272 |
273 | B .
274 |
275 | ENDP
276 |
277 | ALIGN
278 |
279 | ;*******************************************************************************
280 | ; User Stack and Heap initialization
281 | ;*******************************************************************************
282 | IF :DEF:__MICROLIB
283 |
284 | EXPORT __initial_sp
285 | EXPORT __heap_base
286 | EXPORT __heap_limit
287 |
288 | ELSE
289 |
290 | IMPORT __use_two_region_memory
291 | EXPORT __user_initial_stackheap
292 |
293 | __user_initial_stackheap
294 |
295 | LDR R0, = Heap_Mem
296 | LDR R1, =(Stack_Mem + Stack_Size)
297 | LDR R2, = (Heap_Mem + Heap_Size)
298 | LDR R3, = Stack_Mem
299 | BX LR
300 |
301 | ALIGN
302 |
303 | ENDIF
304 |
305 | END
306 |
307 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
308 |
--------------------------------------------------------------------------------
/demo/Src/main.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.c
5 | * @brief : Main program body
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file
13 | * in the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 | /* USER CODE END Header */
19 | /* Includes ------------------------------------------------------------------*/
20 | #include "main.h"
21 |
22 | /* Private includes ----------------------------------------------------------*/
23 | /* USER CODE BEGIN Includes */
24 | #include "eeprom_in_flash.h"
25 | /* USER CODE END Includes */
26 |
27 | /* Private typedef -----------------------------------------------------------*/
28 | /* USER CODE BEGIN PTD */
29 | #pragma pack(1)
30 | typedef struct
31 | {
32 | uint32_t boot_count; //0
33 | uint16_t modbus_addr; //4
34 |
35 | int32_t Voltage_offset; //6
36 | int32_t Current_offset; //10
37 | }Config_type;
38 | #pragma pack()
39 | /* USER CODE END PTD */
40 |
41 | /* Private define ------------------------------------------------------------*/
42 | /* USER CODE BEGIN PD */
43 | int fputc(int ch, FILE *f)
44 | {
45 | while((USART1->SR&0X40)==0){}
46 | USART1->DR = (uint8_t) ch;
47 | return ch;
48 | }
49 | /* USER CODE END PD */
50 |
51 | /* Private macro -------------------------------------------------------------*/
52 | /* USER CODE BEGIN PM */
53 |
54 | /* USER CODE END PM */
55 |
56 | /* Private variables ---------------------------------------------------------*/
57 | UART_HandleTypeDef huart1;
58 |
59 | /* USER CODE BEGIN PV */
60 | const Config_type Config_default = {
61 | .boot_count = 0,
62 | .modbus_addr = 1,
63 | .Voltage_offset = 3000,
64 | .Current_offset = -2000,
65 | };
66 | /* USER CODE END PV */
67 |
68 | /* Private function prototypes -----------------------------------------------*/
69 | void SystemClock_Config(void);
70 | static void MX_GPIO_Init(void);
71 | static void MX_USART1_UART_Init(void);
72 | /* USER CODE BEGIN PFP */
73 |
74 | /* USER CODE END PFP */
75 |
76 | /* Private user code ---------------------------------------------------------*/
77 | /* USER CODE BEGIN 0 */
78 |
79 | /* USER CODE END 0 */
80 |
81 | /**
82 | * @brief The application entry point.
83 | * @retval int
84 | */
85 | int main(void)
86 | {
87 | /* USER CODE BEGIN 1 */
88 |
89 | /* USER CODE END 1 */
90 |
91 | /* MCU Configuration--------------------------------------------------------*/
92 |
93 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
94 | HAL_Init();
95 |
96 | /* USER CODE BEGIN Init */
97 |
98 | /* USER CODE END Init */
99 |
100 | /* Configure the system clock */
101 | SystemClock_Config();
102 |
103 | /* USER CODE BEGIN SysInit */
104 |
105 | /* USER CODE END SysInit */
106 |
107 | /* Initialize all configured peripherals */
108 | MX_GPIO_Init();
109 | MX_USART1_UART_Init();
110 | /* USER CODE BEGIN 2 */
111 | log_printf(LOG_Assert, "system start!\r\n");
112 |
113 | EEPROM_Init((void *)&Config_default);
114 |
115 | uint32_t boot_count = 0;
116 | Config_Read_Buf(0, &boot_count, sizeof(boot_count));
117 | boot_count++;
118 | Config_Write_Buf(0, &boot_count, sizeof(boot_count));
119 | log_printf(LOG_Info, "----------> system boot count: %d\r\n\r\n", boot_count);
120 |
121 | /* USER CODE END 2 */
122 |
123 | /* Infinite loop */
124 | /* USER CODE BEGIN WHILE */
125 | uint32_t Voltage;
126 | Config_Read_Buf(6, &Voltage, sizeof(Voltage));
127 | while (1)
128 | {
129 | HAL_Delay(2000);
130 |
131 | Config_Read_Buf(6, &Voltage, sizeof(Voltage));
132 | log_printf(LOG_Debug, "----------> Read Voltage_offset is %d\r\n", Voltage);
133 |
134 | HAL_Delay(500);
135 |
136 | log_printf(LOG_Debug, "----------> change Voltage %d to %d\r\n", Voltage, Voltage+20);
137 | Voltage += 20;
138 | Config_Write_Buf(6, &Voltage, sizeof(Voltage));
139 |
140 | if(Voltage > 3400)
141 | {
142 | log_printf(LOG_Debug, "----------> Format eeprom with default data\r\n");
143 | EEPROM_Format((void *)&Config_default);
144 | }
145 | /* USER CODE END WHILE */
146 |
147 | /* USER CODE BEGIN 3 */
148 | }
149 | /* USER CODE END 3 */
150 | }
151 |
152 | /**
153 | * @brief System Clock Configuration
154 | * @retval None
155 | */
156 | void SystemClock_Config(void)
157 | {
158 | RCC_OscInitTypeDef RCC_OscInitStruct = {0};
159 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
160 |
161 | /** Initializes the RCC Oscillators according to the specified parameters
162 | * in the RCC_OscInitTypeDef structure.
163 | */
164 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
165 | RCC_OscInitStruct.HSIState = RCC_HSI_ON;
166 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
167 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
168 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
169 | {
170 | Error_Handler();
171 | }
172 | /** Initializes the CPU, AHB and APB buses clocks
173 | */
174 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
175 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
176 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
177 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
178 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
179 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
180 |
181 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
182 | {
183 | Error_Handler();
184 | }
185 | }
186 |
187 | /**
188 | * @brief USART1 Initialization Function
189 | * @param None
190 | * @retval None
191 | */
192 | static void MX_USART1_UART_Init(void)
193 | {
194 |
195 | /* USER CODE BEGIN USART1_Init 0 */
196 |
197 | /* USER CODE END USART1_Init 0 */
198 |
199 | /* USER CODE BEGIN USART1_Init 1 */
200 |
201 | /* USER CODE END USART1_Init 1 */
202 | huart1.Instance = USART1;
203 | huart1.Init.BaudRate = 115200;
204 | huart1.Init.WordLength = UART_WORDLENGTH_8B;
205 | huart1.Init.StopBits = UART_STOPBITS_1;
206 | huart1.Init.Parity = UART_PARITY_NONE;
207 | huart1.Init.Mode = UART_MODE_TX_RX;
208 | huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
209 | huart1.Init.OverSampling = UART_OVERSAMPLING_16;
210 | if (HAL_UART_Init(&huart1) != HAL_OK)
211 | {
212 | Error_Handler();
213 | }
214 | /* USER CODE BEGIN USART1_Init 2 */
215 |
216 | /* USER CODE END USART1_Init 2 */
217 |
218 | }
219 |
220 | /**
221 | * @brief GPIO Initialization Function
222 | * @param None
223 | * @retval None
224 | */
225 | static void MX_GPIO_Init(void)
226 | {
227 |
228 | /* GPIO Ports Clock Enable */
229 | __HAL_RCC_GPIOA_CLK_ENABLE();
230 |
231 | }
232 |
233 | /* USER CODE BEGIN 4 */
234 |
235 | /* USER CODE END 4 */
236 |
237 | /**
238 | * @brief This function is executed in case of error occurrence.
239 | * @retval None
240 | */
241 | void Error_Handler(void)
242 | {
243 | /* USER CODE BEGIN Error_Handler_Debug */
244 | /* User can add his own implementation to report the HAL error return state */
245 | __disable_irq();
246 | while (1)
247 | {
248 | }
249 | /* USER CODE END Error_Handler_Debug */
250 | }
251 |
252 | #ifdef USE_FULL_ASSERT
253 | /**
254 | * @brief Reports the name of the source file and the source line number
255 | * where the assert_param error has occurred.
256 | * @param file: pointer to the source file name
257 | * @param line: assert_param error line source number
258 | * @retval None
259 | */
260 | void assert_failed(uint8_t *file, uint32_t line)
261 | {
262 | /* USER CODE BEGIN 6 */
263 | /* User can add his own implementation to report the file name and line number,
264 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
265 | /* USER CODE END 6 */
266 | }
267 | #endif /* USE_FULL_ASSERT */
268 |
269 |
--------------------------------------------------------------------------------
/demo/Src/stm32f1xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f1xx_hal_msp.c
5 | * @brief This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * Copyright (c) 2021 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software is licensed under terms that can be found in the LICENSE file
14 | * in the root directory of this software component.
15 | * If no LICENSE file comes with this software, it is provided AS-IS.
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | /* USER CODE BEGIN Includes */
24 |
25 | /* USER CODE END Includes */
26 |
27 | /* Private typedef -----------------------------------------------------------*/
28 | /* USER CODE BEGIN TD */
29 |
30 | /* USER CODE END TD */
31 |
32 | /* Private define ------------------------------------------------------------*/
33 | /* USER CODE BEGIN Define */
34 |
35 | /* USER CODE END Define */
36 |
37 | /* Private macro -------------------------------------------------------------*/
38 | /* USER CODE BEGIN Macro */
39 |
40 | /* USER CODE END Macro */
41 |
42 | /* Private variables ---------------------------------------------------------*/
43 | /* USER CODE BEGIN PV */
44 |
45 | /* USER CODE END PV */
46 |
47 | /* Private function prototypes -----------------------------------------------*/
48 | /* USER CODE BEGIN PFP */
49 |
50 | /* USER CODE END PFP */
51 |
52 | /* External functions --------------------------------------------------------*/
53 | /* USER CODE BEGIN ExternalFunctions */
54 |
55 | /* USER CODE END ExternalFunctions */
56 |
57 | /* USER CODE BEGIN 0 */
58 |
59 | /* USER CODE END 0 */
60 | /**
61 | * Initializes the Global MSP.
62 | */
63 | void HAL_MspInit(void)
64 | {
65 | /* USER CODE BEGIN MspInit 0 */
66 |
67 | /* USER CODE END MspInit 0 */
68 |
69 | __HAL_RCC_AFIO_CLK_ENABLE();
70 | __HAL_RCC_PWR_CLK_ENABLE();
71 |
72 | /* System interrupt init*/
73 |
74 | /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
75 | */
76 | __HAL_AFIO_REMAP_SWJ_NOJTAG();
77 |
78 | /* USER CODE BEGIN MspInit 1 */
79 |
80 | /* USER CODE END MspInit 1 */
81 | }
82 |
83 | /**
84 | * @brief UART MSP Initialization
85 | * This function configures the hardware resources used in this example
86 | * @param huart: UART handle pointer
87 | * @retval None
88 | */
89 | void HAL_UART_MspInit(UART_HandleTypeDef* huart)
90 | {
91 | GPIO_InitTypeDef GPIO_InitStruct = {0};
92 | if(huart->Instance==USART1)
93 | {
94 | /* USER CODE BEGIN USART1_MspInit 0 */
95 |
96 | /* USER CODE END USART1_MspInit 0 */
97 | /* Peripheral clock enable */
98 | __HAL_RCC_USART1_CLK_ENABLE();
99 |
100 | __HAL_RCC_GPIOA_CLK_ENABLE();
101 | /**USART1 GPIO Configuration
102 | PA9 ------> USART1_TX
103 | PA10 ------> USART1_RX
104 | */
105 | GPIO_InitStruct.Pin = GPIO_PIN_9;
106 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
107 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
108 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
109 |
110 | GPIO_InitStruct.Pin = GPIO_PIN_10;
111 | GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
112 | GPIO_InitStruct.Pull = GPIO_NOPULL;
113 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
114 |
115 | /* USER CODE BEGIN USART1_MspInit 1 */
116 |
117 | /* USER CODE END USART1_MspInit 1 */
118 | }
119 |
120 | }
121 |
122 | /**
123 | * @brief UART MSP De-Initialization
124 | * This function freeze the hardware resources used in this example
125 | * @param huart: UART handle pointer
126 | * @retval None
127 | */
128 | void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
129 | {
130 | if(huart->Instance==USART1)
131 | {
132 | /* USER CODE BEGIN USART1_MspDeInit 0 */
133 |
134 | /* USER CODE END USART1_MspDeInit 0 */
135 | /* Peripheral clock disable */
136 | __HAL_RCC_USART1_CLK_DISABLE();
137 |
138 | /**USART1 GPIO Configuration
139 | PA9 ------> USART1_TX
140 | PA10 ------> USART1_RX
141 | */
142 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
143 |
144 | /* USER CODE BEGIN USART1_MspDeInit 1 */
145 |
146 | /* USER CODE END USART1_MspDeInit 1 */
147 | }
148 |
149 | }
150 |
151 | /* USER CODE BEGIN 1 */
152 |
153 | /* USER CODE END 1 */
154 |
155 |
--------------------------------------------------------------------------------
/demo/Src/stm32f1xx_it.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f1xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * Copyright (c) 2021 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software is licensed under terms that can be found in the LICENSE file
13 | * in the root directory of this software component.
14 | * If no LICENSE file comes with this software, it is provided AS-IS.
15 | *
16 | ******************************************************************************
17 | */
18 | /* USER CODE END Header */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "main.h"
22 | #include "stm32f1xx_it.h"
23 | /* Private includes ----------------------------------------------------------*/
24 | /* USER CODE BEGIN Includes */
25 | /* USER CODE END Includes */
26 |
27 | /* Private typedef -----------------------------------------------------------*/
28 | /* USER CODE BEGIN TD */
29 |
30 | /* USER CODE END TD */
31 |
32 | /* Private define ------------------------------------------------------------*/
33 | /* USER CODE BEGIN PD */
34 |
35 | /* USER CODE END PD */
36 |
37 | /* Private macro -------------------------------------------------------------*/
38 | /* USER CODE BEGIN PM */
39 |
40 | /* USER CODE END PM */
41 |
42 | /* Private variables ---------------------------------------------------------*/
43 | /* USER CODE BEGIN PV */
44 |
45 | /* USER CODE END PV */
46 |
47 | /* Private function prototypes -----------------------------------------------*/
48 | /* USER CODE BEGIN PFP */
49 |
50 | /* USER CODE END PFP */
51 |
52 | /* Private user code ---------------------------------------------------------*/
53 | /* USER CODE BEGIN 0 */
54 |
55 | /* USER CODE END 0 */
56 |
57 | /* External variables --------------------------------------------------------*/
58 |
59 | /* USER CODE BEGIN EV */
60 |
61 | /* USER CODE END EV */
62 |
63 | /******************************************************************************/
64 | /* Cortex-M3 Processor Interruption and Exception Handlers */
65 | /******************************************************************************/
66 | /**
67 | * @brief This function handles Non maskable interrupt.
68 | */
69 | void NMI_Handler(void)
70 | {
71 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
72 |
73 | /* USER CODE END NonMaskableInt_IRQn 0 */
74 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
75 | while (1)
76 | {
77 | }
78 | /* USER CODE END NonMaskableInt_IRQn 1 */
79 | }
80 |
81 | /**
82 | * @brief This function handles Hard fault interrupt.
83 | */
84 | void HardFault_Handler(void)
85 | {
86 | /* USER CODE BEGIN HardFault_IRQn 0 */
87 |
88 | /* USER CODE END HardFault_IRQn 0 */
89 | while (1)
90 | {
91 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
92 | /* USER CODE END W1_HardFault_IRQn 0 */
93 | }
94 | }
95 |
96 | /**
97 | * @brief This function handles Memory management fault.
98 | */
99 | void MemManage_Handler(void)
100 | {
101 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */
102 |
103 | /* USER CODE END MemoryManagement_IRQn 0 */
104 | while (1)
105 | {
106 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
107 | /* USER CODE END W1_MemoryManagement_IRQn 0 */
108 | }
109 | }
110 |
111 | /**
112 | * @brief This function handles Prefetch fault, memory access fault.
113 | */
114 | void BusFault_Handler(void)
115 | {
116 | /* USER CODE BEGIN BusFault_IRQn 0 */
117 |
118 | /* USER CODE END BusFault_IRQn 0 */
119 | while (1)
120 | {
121 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */
122 | /* USER CODE END W1_BusFault_IRQn 0 */
123 | }
124 | }
125 |
126 | /**
127 | * @brief This function handles Undefined instruction or illegal state.
128 | */
129 | void UsageFault_Handler(void)
130 | {
131 | /* USER CODE BEGIN UsageFault_IRQn 0 */
132 |
133 | /* USER CODE END UsageFault_IRQn 0 */
134 | while (1)
135 | {
136 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
137 | /* USER CODE END W1_UsageFault_IRQn 0 */
138 | }
139 | }
140 |
141 | /**
142 | * @brief This function handles System service call via SWI instruction.
143 | */
144 | void SVC_Handler(void)
145 | {
146 | /* USER CODE BEGIN SVCall_IRQn 0 */
147 |
148 | /* USER CODE END SVCall_IRQn 0 */
149 | /* USER CODE BEGIN SVCall_IRQn 1 */
150 |
151 | /* USER CODE END SVCall_IRQn 1 */
152 | }
153 |
154 | /**
155 | * @brief This function handles Debug monitor.
156 | */
157 | void DebugMon_Handler(void)
158 | {
159 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */
160 |
161 | /* USER CODE END DebugMonitor_IRQn 0 */
162 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */
163 |
164 | /* USER CODE END DebugMonitor_IRQn 1 */
165 | }
166 |
167 | /**
168 | * @brief This function handles Pendable request for system service.
169 | */
170 | void PendSV_Handler(void)
171 | {
172 | /* USER CODE BEGIN PendSV_IRQn 0 */
173 |
174 | /* USER CODE END PendSV_IRQn 0 */
175 | /* USER CODE BEGIN PendSV_IRQn 1 */
176 |
177 | /* USER CODE END PendSV_IRQn 1 */
178 | }
179 |
180 | /**
181 | * @brief This function handles System tick timer.
182 | */
183 | void SysTick_Handler(void)
184 | {
185 | /* USER CODE BEGIN SysTick_IRQn 0 */
186 |
187 | /* USER CODE END SysTick_IRQn 0 */
188 | HAL_IncTick();
189 | /* USER CODE BEGIN SysTick_IRQn 1 */
190 |
191 | /* USER CODE END SysTick_IRQn 1 */
192 | }
193 |
194 | /******************************************************************************/
195 | /* STM32F1xx Peripheral Interrupt Handlers */
196 | /* Add here the Interrupt Handlers for the used peripherals. */
197 | /* For the available peripheral interrupt handler names, */
198 | /* please refer to the startup file (startup_stm32f1xx.s). */
199 | /******************************************************************************/
200 |
201 | /* USER CODE BEGIN 1 */
202 |
203 | /* USER CODE END 1 */
204 |
205 |
--------------------------------------------------------------------------------
/demo/Src/system_stm32f1xx.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f1xx.c
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6 | *
7 | * 1. This file provides two functions and one global variable to be called from
8 | * user application:
9 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
10 | * factors, AHB/APBx prescalers and Flash settings).
11 | * This function is called at startup just after reset and
12 | * before branch to main program. This call is made inside
13 | * the "startup_stm32f1xx_xx.s" file.
14 | *
15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 | * by the user application to setup the SysTick
17 | * timer or configure other parameters.
18 | *
19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 | * be called whenever the core clock is changed
21 | * during program execution.
22 | *
23 | * 2. After each device reset the HSI (8 MHz) is used as system clock source.
24 | * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
25 | * configure the system clock before to branch to main program.
26 | *
27 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
28 | * the product used), refer to "HSE_VALUE".
29 | * When HSE is used as system clock source, directly or through PLL, and you
30 | * are using different crystal you have to adapt the HSE value to your own
31 | * configuration.
32 | *
33 | ******************************************************************************
34 | * @attention
35 | *
36 | * © Copyright (c) 2017 STMicroelectronics.
37 | * All rights reserved.
38 | *
39 | * This software component is licensed by ST under BSD 3-Clause license,
40 | * the "License"; You may not use this file except in compliance with the
41 | * License. You may obtain a copy of the License at:
42 | * opensource.org/licenses/BSD-3-Clause
43 | *
44 | ******************************************************************************
45 | */
46 |
47 | /** @addtogroup CMSIS
48 | * @{
49 | */
50 |
51 | /** @addtogroup stm32f1xx_system
52 | * @{
53 | */
54 |
55 | /** @addtogroup STM32F1xx_System_Private_Includes
56 | * @{
57 | */
58 |
59 | #include "stm32f1xx.h"
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
66 | * @{
67 | */
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /** @addtogroup STM32F1xx_System_Private_Defines
74 | * @{
75 | */
76 |
77 | #if !defined (HSE_VALUE)
78 | #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
79 | This value can be provided and adapted by the user application. */
80 | #endif /* HSE_VALUE */
81 |
82 | #if !defined (HSI_VALUE)
83 | #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
84 | This value can be provided and adapted by the user application. */
85 | #endif /* HSI_VALUE */
86 |
87 | /*!< Uncomment the following line if you need to use external SRAM */
88 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
89 | /* #define DATA_IN_ExtSRAM */
90 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
91 |
92 | /* Note: Following vector table addresses must be defined in line with linker
93 | configuration. */
94 | /*!< Uncomment the following line if you need to relocate the vector table
95 | anywhere in Flash or Sram, else the vector table is kept at the automatic
96 | remap of boot address selected */
97 | /* #define USER_VECT_TAB_ADDRESS */
98 |
99 | #if defined(USER_VECT_TAB_ADDRESS)
100 | /*!< Uncomment the following line if you need to relocate your vector Table
101 | in Sram else user remap will be done in Flash. */
102 | /* #define VECT_TAB_SRAM */
103 | #if defined(VECT_TAB_SRAM)
104 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
105 | This value must be a multiple of 0x200. */
106 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
107 | This value must be a multiple of 0x200. */
108 | #else
109 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
110 | This value must be a multiple of 0x200. */
111 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
112 | This value must be a multiple of 0x200. */
113 | #endif /* VECT_TAB_SRAM */
114 | #endif /* USER_VECT_TAB_ADDRESS */
115 |
116 | /******************************************************************************/
117 |
118 | /**
119 | * @}
120 | */
121 |
122 | /** @addtogroup STM32F1xx_System_Private_Macros
123 | * @{
124 | */
125 |
126 | /**
127 | * @}
128 | */
129 |
130 | /** @addtogroup STM32F1xx_System_Private_Variables
131 | * @{
132 | */
133 |
134 | /* This variable is updated in three ways:
135 | 1) by calling CMSIS function SystemCoreClockUpdate()
136 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
137 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
138 | Note: If you use this function to configure the system clock; then there
139 | is no need to call the 2 first functions listed above, since SystemCoreClock
140 | variable is updated automatically.
141 | */
142 | uint32_t SystemCoreClock = 16000000;
143 | const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
144 | const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
145 |
146 | /**
147 | * @}
148 | */
149 |
150 | /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
151 | * @{
152 | */
153 |
154 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
155 | #ifdef DATA_IN_ExtSRAM
156 | static void SystemInit_ExtMemCtl(void);
157 | #endif /* DATA_IN_ExtSRAM */
158 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
159 |
160 | /**
161 | * @}
162 | */
163 |
164 | /** @addtogroup STM32F1xx_System_Private_Functions
165 | * @{
166 | */
167 |
168 | /**
169 | * @brief Setup the microcontroller system
170 | * Initialize the Embedded Flash Interface, the PLL and update the
171 | * SystemCoreClock variable.
172 | * @note This function should be used only after reset.
173 | * @param None
174 | * @retval None
175 | */
176 | void SystemInit (void)
177 | {
178 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
179 | #ifdef DATA_IN_ExtSRAM
180 | SystemInit_ExtMemCtl();
181 | #endif /* DATA_IN_ExtSRAM */
182 | #endif
183 |
184 | /* Configure the Vector Table location -------------------------------------*/
185 | #if defined(USER_VECT_TAB_ADDRESS)
186 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
187 | #endif /* USER_VECT_TAB_ADDRESS */
188 | }
189 |
190 | /**
191 | * @brief Update SystemCoreClock variable according to Clock Register Values.
192 | * The SystemCoreClock variable contains the core clock (HCLK), it can
193 | * be used by the user application to setup the SysTick timer or configure
194 | * other parameters.
195 | *
196 | * @note Each time the core clock (HCLK) changes, this function must be called
197 | * to update SystemCoreClock variable value. Otherwise, any configuration
198 | * based on this variable will be incorrect.
199 | *
200 | * @note - The system frequency computed by this function is not the real
201 | * frequency in the chip. It is calculated based on the predefined
202 | * constant and the selected clock source:
203 | *
204 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
205 | *
206 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
207 | *
208 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
209 | * or HSI_VALUE(*) multiplied by the PLL factors.
210 | *
211 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
212 | * 8 MHz) but the real value may vary depending on the variations
213 | * in voltage and temperature.
214 | *
215 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
216 | * 8 MHz or 25 MHz, depending on the product used), user has to ensure
217 | * that HSE_VALUE is same as the real frequency of the crystal used.
218 | * Otherwise, this function may have wrong result.
219 | *
220 | * - The result of this function could be not correct when using fractional
221 | * value for HSE crystal.
222 | * @param None
223 | * @retval None
224 | */
225 | void SystemCoreClockUpdate (void)
226 | {
227 | uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
228 |
229 | #if defined(STM32F105xC) || defined(STM32F107xC)
230 | uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
231 | #endif /* STM32F105xC */
232 |
233 | #if defined(STM32F100xB) || defined(STM32F100xE)
234 | uint32_t prediv1factor = 0U;
235 | #endif /* STM32F100xB or STM32F100xE */
236 |
237 | /* Get SYSCLK source -------------------------------------------------------*/
238 | tmp = RCC->CFGR & RCC_CFGR_SWS;
239 |
240 | switch (tmp)
241 | {
242 | case 0x00U: /* HSI used as system clock */
243 | SystemCoreClock = HSI_VALUE;
244 | break;
245 | case 0x04U: /* HSE used as system clock */
246 | SystemCoreClock = HSE_VALUE;
247 | break;
248 | case 0x08U: /* PLL used as system clock */
249 |
250 | /* Get PLL clock source and multiplication factor ----------------------*/
251 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
252 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
253 |
254 | #if !defined(STM32F105xC) && !defined(STM32F107xC)
255 | pllmull = ( pllmull >> 18U) + 2U;
256 |
257 | if (pllsource == 0x00U)
258 | {
259 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
260 | SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
261 | }
262 | else
263 | {
264 | #if defined(STM32F100xB) || defined(STM32F100xE)
265 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
266 | /* HSE oscillator clock selected as PREDIV1 clock entry */
267 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
268 | #else
269 | /* HSE selected as PLL clock entry */
270 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
271 | {/* HSE oscillator clock divided by 2 */
272 | SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
273 | }
274 | else
275 | {
276 | SystemCoreClock = HSE_VALUE * pllmull;
277 | }
278 | #endif
279 | }
280 | #else
281 | pllmull = pllmull >> 18U;
282 |
283 | if (pllmull != 0x0DU)
284 | {
285 | pllmull += 2U;
286 | }
287 | else
288 | { /* PLL multiplication factor = PLL input clock * 6.5 */
289 | pllmull = 13U / 2U;
290 | }
291 |
292 | if (pllsource == 0x00U)
293 | {
294 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
295 | SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
296 | }
297 | else
298 | {/* PREDIV1 selected as PLL clock entry */
299 |
300 | /* Get PREDIV1 clock source and division factor */
301 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
302 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
303 |
304 | if (prediv1source == 0U)
305 | {
306 | /* HSE oscillator clock selected as PREDIV1 clock entry */
307 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
308 | }
309 | else
310 | {/* PLL2 clock selected as PREDIV1 clock entry */
311 |
312 | /* Get PREDIV2 division factor and PLL2 multiplication factor */
313 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
314 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
315 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
316 | }
317 | }
318 | #endif /* STM32F105xC */
319 | break;
320 |
321 | default:
322 | SystemCoreClock = HSI_VALUE;
323 | break;
324 | }
325 |
326 | /* Compute HCLK clock frequency ----------------*/
327 | /* Get HCLK prescaler */
328 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
329 | /* HCLK clock frequency */
330 | SystemCoreClock >>= tmp;
331 | }
332 |
333 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
334 | /**
335 | * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
336 | * before jump to __main
337 | * @param None
338 | * @retval None
339 | */
340 | #ifdef DATA_IN_ExtSRAM
341 | /**
342 | * @brief Setup the external memory controller.
343 | * Called in startup_stm32f1xx_xx.s/.c before jump to main.
344 | * This function configures the external SRAM mounted on STM3210E-EVAL
345 | * board (STM32 High density devices). This SRAM will be used as program
346 | * data memory (including heap and stack).
347 | * @param None
348 | * @retval None
349 | */
350 | void SystemInit_ExtMemCtl(void)
351 | {
352 | __IO uint32_t tmpreg;
353 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
354 | required, then adjust the Register Addresses */
355 |
356 | /* Enable FSMC clock */
357 | RCC->AHBENR = 0x00000114U;
358 |
359 | /* Delay after an RCC peripheral clock enabling */
360 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
361 |
362 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
363 | RCC->APB2ENR = 0x000001E0U;
364 |
365 | /* Delay after an RCC peripheral clock enabling */
366 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
367 |
368 | (void)(tmpreg);
369 |
370 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
371 | /*---------------- SRAM Address lines configuration -------------------------*/
372 | /*---------------- NOE and NWE configuration --------------------------------*/
373 | /*---------------- NE3 configuration ----------------------------------------*/
374 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/
375 |
376 | GPIOD->CRL = 0x44BB44BBU;
377 | GPIOD->CRH = 0xBBBBBBBBU;
378 |
379 | GPIOE->CRL = 0xB44444BBU;
380 | GPIOE->CRH = 0xBBBBBBBBU;
381 |
382 | GPIOF->CRL = 0x44BBBBBBU;
383 | GPIOF->CRH = 0xBBBB4444U;
384 |
385 | GPIOG->CRL = 0x44BBBBBBU;
386 | GPIOG->CRH = 0x444B4B44U;
387 |
388 | /*---------------- FSMC Configuration ---------------------------------------*/
389 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
390 |
391 | FSMC_Bank1->BTCR[4U] = 0x00001091U;
392 | FSMC_Bank1->BTCR[5U] = 0x00110212U;
393 | }
394 | #endif /* DATA_IN_ExtSRAM */
395 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
396 |
397 | /**
398 | * @}
399 | */
400 |
401 | /**
402 | * @}
403 | */
404 |
405 | /**
406 | * @}
407 | */
408 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
409 |
--------------------------------------------------------------------------------
/demo/eeprom_test.ioc:
--------------------------------------------------------------------------------
1 | #MicroXplorer Configuration settings - do not modify
2 | File.Version=6
3 | GPIO.groupedBy=
4 | KeepUserPlacement=false
5 | Mcu.Family=STM32F1
6 | Mcu.IP0=NVIC
7 | Mcu.IP1=RCC
8 | Mcu.IP2=SYS
9 | Mcu.IP3=USART1
10 | Mcu.IPNb=4
11 | Mcu.Name=STM32F103C(8-B)Tx
12 | Mcu.Package=LQFP48
13 | Mcu.Pin0=PA9
14 | Mcu.Pin1=PA10
15 | Mcu.Pin2=PA13
16 | Mcu.Pin3=PA14
17 | Mcu.Pin4=VP_SYS_VS_Systick
18 | Mcu.PinsNb=5
19 | Mcu.ThirdPartyNb=0
20 | Mcu.UserConstants=
21 | Mcu.UserName=STM32F103C8Tx
22 | MxCube.Version=6.4.0
23 | MxDb.Version=DB.6.0.40
24 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
25 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
26 | NVIC.ForceEnableDMAVector=true
27 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
28 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
29 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
30 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
31 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
32 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
33 | NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true
34 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
35 | PA10.Mode=Asynchronous
36 | PA10.Signal=USART1_RX
37 | PA13.Mode=Serial_Wire
38 | PA13.Signal=SYS_JTMS-SWDIO
39 | PA14.Mode=Serial_Wire
40 | PA14.Signal=SYS_JTCK-SWCLK
41 | PA9.Mode=Asynchronous
42 | PA9.Signal=USART1_TX
43 | PinOutPanel.RotationAngle=0
44 | ProjectManager.AskForMigrate=true
45 | ProjectManager.BackupPrevious=false
46 | ProjectManager.CompilerOptimize=6
47 | ProjectManager.ComputerToolchain=false
48 | ProjectManager.CoupleFile=false
49 | ProjectManager.CustomerFirmwarePackage=
50 | ProjectManager.DefaultFWLocation=true
51 | ProjectManager.DeletePrevious=true
52 | ProjectManager.DeviceId=STM32F103C8Tx
53 | ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.4
54 | ProjectManager.FreePins=false
55 | ProjectManager.HalAssertFull=false
56 | ProjectManager.HeapSize=0x200
57 | ProjectManager.KeepUserCode=true
58 | ProjectManager.LastFirmware=true
59 | ProjectManager.LibraryCopy=1
60 | ProjectManager.MainLocation=Src
61 | ProjectManager.NoMain=false
62 | ProjectManager.PreviousToolchain=
63 | ProjectManager.ProjectBuild=false
64 | ProjectManager.ProjectFileName=eeprom_test.ioc
65 | ProjectManager.ProjectName=eeprom_test
66 | ProjectManager.RegisterCallBack=
67 | ProjectManager.StackSize=0x400
68 | ProjectManager.TargetToolchain=MDK-ARM V5.32
69 | ProjectManager.ToolChainLocation=
70 | ProjectManager.UnderRoot=false
71 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true
72 | RCC.APB1Freq_Value=8000000
73 | RCC.APB2Freq_Value=8000000
74 | RCC.FamilyName=M
75 | RCC.IPParameters=APB1Freq_Value,APB2Freq_Value,FamilyName,PLLCLKFreq_Value,PLLMCOFreq_Value,TimSysFreq_Value
76 | RCC.PLLCLKFreq_Value=8000000
77 | RCC.PLLMCOFreq_Value=4000000
78 | RCC.TimSysFreq_Value=8000000
79 | USART1.IPParameters=VirtualMode
80 | USART1.VirtualMode=VM_ASYNC
81 | VP_SYS_VS_Systick.Mode=SysTick
82 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
83 | board=custom
84 |
--------------------------------------------------------------------------------
/eeprom_in_flash.c:
--------------------------------------------------------------------------------
1 | /* eeprom in flash
2 | * Copyright (c) 2021-2022 epoko
3 | *
4 | * Licensed under the Apache License, Version 2.0 (the "License");
5 | * you may not use this file except in compliance with the License.
6 | * You may obtain a copy of the License at
7 | *
8 | * http://www.apache.org/licenses/LICENSE-2.0
9 | *
10 | * Unless required by applicable law or agreed to in writing, software
11 | * distributed under the License is distributed on an "AS IS" BASIS,
12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 | * See the License for the specific language governing permissions and
14 | * limitations under the License.
15 | */
16 | #include "eeprom_in_flash.h"
17 |
18 | static uint16_t EEPROM_data[EEPROM_NUM_MAX] = {0};
19 | static int EEPROM_PART_USE = -1;
20 |
21 | static int EE_Init(void);
22 | static int EE_ReadVariable(uint32_t VirtAddress, uint16_t *Data);
23 | static int EE_WriteVariable(uint32_t VirtAddress, uint16_t Data);
24 | static int EE_Format(int part);
25 |
26 | int EEPROM_Init(void *default_data)
27 | {
28 | uint32_t time_use = HAL_GetTick();
29 |
30 | if (default_data)
31 | memcpy(EEPROM_data, default_data, sizeof(EEPROM_data));
32 |
33 | if (EE_Init() != HAL_OK)
34 | {
35 | log_printf(LOG_Error, "EEPROM Init error\r\n");
36 | return HAL_ERROR;
37 | }
38 |
39 | for (int i = 0; i < EEPROM_NUM_MAX; i++)
40 | EE_ReadVariable(i, &EEPROM_data[i]);
41 |
42 | log_printf(LOG_Verbose, "EEPROM_Init use %dms\r\n", HAL_GetTick() - time_use);
43 | return HAL_OK;
44 | }
45 |
46 | uint16_t EEPROM_Read(uint16_t Address)
47 | {
48 | if (Address >= EEPROM_NUM_MAX)
49 | return 0;
50 |
51 | return EEPROM_data[Address];
52 | }
53 |
54 | int EEPROM_Write(uint16_t Address, uint16_t Data)
55 | {
56 | if (EEPROM_PART_USE == -1 || Address >= EEPROM_NUM_MAX)
57 | return HAL_ERROR;
58 |
59 | if (EEPROM_data[Address] == Data)
60 | return HAL_OK;
61 |
62 | if (EE_WriteVariable(Address, Data) != HAL_OK)
63 | {
64 | // EEPROM_data[Address] = Data;
65 | log_printf(LOG_Error, "EEPROM write error\r\n");
66 | return HAL_ERROR;
67 | }
68 |
69 | return HAL_OK;
70 | }
71 |
72 | int EEPROM_Read_Buf(uint16_t Address, uint16_t *buf, uint16_t length)
73 | {
74 | if (Address + length >= EEPROM_NUM_MAX)
75 | return HAL_ERROR;
76 |
77 | memcpy(buf, EEPROM_data + Address, length << 1);
78 | return HAL_OK;
79 | }
80 |
81 | int EEPROM_Write_Buf(uint16_t Address, uint16_t *buf, uint16_t length)
82 | {
83 | if (EEPROM_PART_USE == -1 || Address + length >= EEPROM_NUM_MAX)
84 | return HAL_ERROR;
85 |
86 | while (length--)
87 | {
88 | if (EEPROM_data[Address] != *buf)
89 | {
90 | if (EE_WriteVariable(Address, *buf) != HAL_OK)
91 | {
92 | // EEPROM_data[Address] = *buf;
93 | log_printf(LOG_Error, "EEPROM write buf error\r\n");
94 | return HAL_ERROR;
95 | }
96 | }
97 |
98 | buf++;
99 | Address++;
100 | }
101 | return HAL_OK;
102 | }
103 |
104 | int EEPROM_Format(void *default_data)
105 | {
106 | if (default_data)
107 | memcpy(EEPROM_data, default_data, sizeof(EEPROM_data));
108 | else
109 | memset(EEPROM_data, 0, sizeof(EEPROM_data));
110 |
111 | if (EE_Format(0) != HAL_OK)
112 | {
113 | log_printf(LOG_Error, "EEPROM Format error\r\n");
114 | return HAL_ERROR;
115 | }
116 |
117 | EEPROM_PART_USE = 0;
118 |
119 | if (EE_ErasePart(1) != HAL_OK)
120 | return HAL_ERROR;
121 | return HAL_OK;
122 | }
123 |
124 | /* -------------- EE Private function -------------- */
125 | static int EE_Init(void)
126 | {
127 | if (EE_ReadWord(PART0_BASE_ADDRESS) == PART_USED_MARK)
128 | {
129 | EEPROM_PART_USE = 0;
130 | }
131 | else
132 | {
133 | if (EE_ReadWord(PART1_BASE_ADDRESS) == PART_USED_MARK)
134 | {
135 | EEPROM_PART_USE = 1;
136 | }
137 | else
138 | {
139 | if (EE_Format(0) != HAL_OK)
140 | return HAL_ERROR;
141 | EEPROM_PART_USE = 0;
142 | }
143 | }
144 |
145 | return HAL_OK;
146 | }
147 |
148 | static int EE_ReadVariable(uint32_t VirtAddress, uint16_t *Data)
149 | {
150 | uint32_t time_use = HAL_GetTick();
151 | uint32_t PartStartAddress = EEPROM_PART_USE == 0 ? PART0_BASE_ADDRESS : PART1_BASE_ADDRESS;
152 | uint32_t Address = (EEPROM_PART_USE == 0 ? PART0_END_ADDRESS : PART1_END_ADDRESS) - 4;
153 | uint32_t temp;
154 |
155 | VirtAddress <<= 16;
156 | for (; Address > PartStartAddress; Address -= 4)
157 | {
158 | temp = EE_ReadWord(Address);
159 | if ((temp & 0xffff0000) == VirtAddress)
160 | {
161 | *Data = temp & 0xffff;
162 | log_printf(LOG_Verbose, "EE_ReadVariable use %dms\r\n", HAL_GetTick() - time_use);
163 | return HAL_OK;
164 | }
165 | }
166 | log_printf(LOG_Warn, "EE_ReadVariable failed, use %dms\r\n", HAL_GetTick() - time_use);
167 | return HAL_ERROR;
168 | }
169 |
170 | static int EE_WriteVariable(uint32_t VirtAddress, uint16_t Data)
171 | {
172 | uint32_t time_use = HAL_GetTick();
173 | uint32_t PartStartAddress = EEPROM_PART_USE == 0 ? PART0_BASE_ADDRESS : PART1_BASE_ADDRESS;
174 | uint32_t Address = (EEPROM_PART_USE == 0 ? PART0_END_ADDRESS : PART1_END_ADDRESS) - 4;
175 |
176 | if (EE_ReadWord(Address) != 0xffffffff)
177 | {
178 | EEPROM_data[VirtAddress] = Data;
179 | if (EE_Format(EEPROM_PART_USE == 0 ? 1 : 0) != HAL_OK)
180 | return HAL_ERROR;
181 |
182 | EEPROM_PART_USE = EEPROM_PART_USE == 0 ? 1 : 0;
183 |
184 | #if PART0_BASE_ADDRESS != PART1_BASE_ADDRESS
185 | if (EE_ErasePart(EEPROM_PART_USE == 0 ? 1 : 0) != HAL_OK)
186 | return HAL_ERROR;
187 | #endif
188 |
189 | return HAL_OK;
190 | }
191 | else
192 | {
193 | for (Address -= 4; Address > PartStartAddress; Address -= 4)
194 | {
195 | if (EE_ReadWord(Address) != 0xffffffff)
196 | break;
197 | }
198 |
199 | if (EE_ProgramWord(Address + 4, (VirtAddress << 16) | Data) != HAL_OK)
200 | return HAL_ERROR;
201 |
202 | EEPROM_data[VirtAddress] = Data;
203 | log_printf(LOG_Verbose, "EE_WriteVariable use %dms\r\n", HAL_GetTick() - time_use);
204 |
205 | return HAL_OK;
206 | }
207 | }
208 |
209 | static int EE_Format(int part)
210 | {
211 | uint32_t i;
212 | uint32_t Part_Addr;
213 | uint32_t Address;
214 |
215 | if (part == 0)
216 | Part_Addr = PART0_BASE_ADDRESS;
217 | else if (part == 1)
218 | Part_Addr = PART1_BASE_ADDRESS;
219 | else
220 | return HAL_ERROR;
221 |
222 | if (EE_ErasePart(part) != HAL_OK)
223 | return HAL_ERROR;
224 |
225 | log_printf(LOG_Info, "EEPROM move data to partiton %d\r\n", part);
226 | Address = Part_Addr + 4;
227 | for (i = 0; i < EEPROM_NUM_MAX; i++)
228 | {
229 | if (EE_ProgramWord(Address, (i << 16) | EEPROM_data[i]) != HAL_OK)
230 | return HAL_ERROR;
231 |
232 | Address += 4;
233 | }
234 |
235 | if (EE_ProgramWord(Part_Addr, PART_USED_MARK) != HAL_OK)
236 | return HAL_ERROR;
237 |
238 | return HAL_OK;
239 | }
240 |
--------------------------------------------------------------------------------
/eeprom_in_flash.h:
--------------------------------------------------------------------------------
1 | /* eeprom in flash
2 | * Copyright (c) 2021-2022 epoko
3 | *
4 | * Licensed under the Apache License, Version 2.0 (the "License");
5 | * you may not use this file except in compliance with the License.
6 | * You may obtain a copy of the License at
7 | *
8 | * http://www.apache.org/licenses/LICENSE-2.0
9 | *
10 | * Unless required by applicable law or agreed to in writing, software
11 | * distributed under the License is distributed on an "AS IS" BASIS,
12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 | * See the License for the specific language governing permissions and
14 | * limitations under the License.
15 | */
16 | #ifndef _EEPROM_IN_FLASH_H_
17 | #define _EEPROM_IN_FLASH_H_
18 | #include "main.h"
19 | #include "stdint.h"
20 | #include "string.h"
21 | #include "stdio.h"
22 |
23 | /* eeprom storage data num max, 1-65535, unit halfword.
24 | Must be smaller than (EEPROM_PART_SIZE/4)-2 */
25 | #define EEPROM_NUM_MAX 7 //*2byte
26 |
27 | /* EEPROM Use two partitions, each partition size is
28 | an integer multiple of the erased page */
29 | #define EEPROM_PART0_SIZE (2048) //eeprom part size 2K, total size 4K
30 | #define EEPROM_PART1_SIZE (EEPROM_PART0_SIZE)
31 |
32 | /* EEPROM start address in Flash */
33 | #define EEPROM_START_ADDRESS (0x0800F000U) //use flash 0x0800F000 - 0x08010000, for 64k flash mcu
34 | #define EEPROM_END_ADDRESS (0x0800F000U + EEPROM_PART0_SIZE + EEPROM_PART1_SIZE)
35 |
36 |
37 | /* Pages 0 and 1 base and end addresses */
38 | #define PART0_BASE_ADDRESS (EEPROM_START_ADDRESS)
39 | #define PART0_END_ADDRESS ((PART0_BASE_ADDRESS + EEPROM_PART0_SIZE))
40 |
41 | #define PART1_BASE_ADDRESS (PART0_END_ADDRESS)
42 | #define PART1_END_ADDRESS ((PART1_BASE_ADDRESS + EEPROM_PART1_SIZE))
43 |
44 | /* PAGE is marked to record data */
45 | #define PART_USED_MARK (0xEAE5D135 + EEPROM_NUM_MAX) //Different number, use new data
46 | //#define PART_USED_MARK (0xEAE5D135) //Different number, use old data
47 |
48 | #ifndef log_printf
49 | #define LOG_Assert "[A] "
50 | #define LOG_Error "[E] "
51 | #define LOG_Warn "[W] "
52 | #define LOG_Info "[I] "
53 | #define LOG_Debug "[D] "
54 | #define LOG_Verbose "[V] "
55 | #define log_printf(level, format, ...) printf(level format, ##__VA_ARGS__)
56 | #endif
57 |
58 | #ifndef USE_HAL_DRIVER
59 | #define HAL_GetTick() 0
60 | #define HAL_Delay(ms)
61 | typedef enum
62 | {
63 | HAL_OK = 0x00U,
64 | HAL_ERROR = 0x01U,
65 | HAL_BUSY = 0x02U,
66 | HAL_TIMEOUT = 0x03U
67 | } HAL_StatusTypeDef;
68 | #endif
69 |
70 | int EEPROM_Init(void *default_data);
71 | int EEPROM_Format(void *default_data);
72 | uint16_t EEPROM_Read(uint16_t Address);
73 | int EEPROM_Write(uint16_t Address, uint16_t Data);
74 | int EEPROM_Read_Buf(uint16_t Address, uint16_t *buf, uint16_t length);
75 | int EEPROM_Write_Buf(uint16_t Address, uint16_t *buf, uint16_t length);
76 | #define Config_Read_Buf(addr, buf, length) EEPROM_Read_Buf((addr)/2, (uint16_t *)(buf), (length)/2)
77 | #define Config_Write_Buf(addr, buf, length) EEPROM_Write_Buf((addr)/2, (uint16_t *)(buf), (length)/2)
78 |
79 | /* flash read program erase callback function */
80 | int EE_ErasePart(int part);
81 | int EE_ProgramWord(uint32_t Address, uint32_t Data);
82 | #define EE_ReadWord(Addr) (*(volatile uint32_t*)Addr)
83 |
84 | #endif
85 |
--------------------------------------------------------------------------------
/eeprom_port/eeprom_port_ch32v1.c:
--------------------------------------------------------------------------------
1 | #include "eeprom_in_flash.h"
2 |
3 | #define PAGE_SIZE 1024
4 |
5 | //EEPROM_PART0 0x0800F000 - 0x0800F800 size 2048
6 | //EEPROM_PART1 0x0800F800 - 0x08001000 size 2048
7 |
8 | /* Erase from PART_BASE_ADDRESS, size EEPROM_PART_SIZE */
9 | int EE_ErasePart(int part)
10 | {
11 | uint32_t time_use=HAL_GetTick();
12 | int ret;
13 | uint32_t erase_address = part == 0 ? PART0_BASE_ADDRESS : PART1_BASE_ADDRESS;
14 | uint32_t erase_size = part == 0 ? EEPROM_PART0_SIZE : EEPROM_PART1_SIZE;
15 |
16 | if (erase_address < PART0_BASE_ADDRESS || erase_address >= PART1_END_ADDRESS)
17 | return HAL_ERROR;
18 |
19 | log_printf(LOG_Debug, "FLASHE Erase 0x%08x size %#x\r\n", erase_address, erase_size);
20 |
21 | FLASH_Unlock();
22 |
23 | ret = FLASH_ErasePage(erase_address);
24 | if(ret != FLASH_COMPLETE)
25 | {
26 | FLASH_Lock();
27 | log_printf(LOG_Error, "FLASHE Erase error %d\r\n", ret);
28 | return HAL_ERROR;
29 | }
30 | ret = FLASH_ErasePage(erase_address + PAGE_SIZE);
31 | if(ret != FLASH_COMPLETE)
32 | {
33 | FLASH_Lock();
34 | log_printf(LOG_Error, "FLASHE Erase error %d\r\n", ret);
35 | return HAL_ERROR;
36 | }
37 |
38 | FLASH_Lock();
39 | log_printf(LOG_Verbose, "FLASHE Erase over, use %dms\r\n", HAL_GetTick()-time_use);
40 | return HAL_OK;
41 | }
42 |
43 | /* If the write operation is not a 32-bit atomic operation,
44 | Write the low 16-bit first, then write the high 16-bit */
45 | int EE_ProgramWord(uint32_t Address, uint32_t Data)
46 | {
47 | int ret;
48 |
49 | if(Address=PART1_END_ADDRESS)
50 | return HAL_ERROR;
51 |
52 | log_printf(LOG_Debug, "FLASHE Program 0x%08x 0x%08x\r\n", Address, Data);
53 |
54 | FLASH_Unlock();
55 |
56 | ret=FLASH_ProgramHalfWord(Address, Data);
57 | if(ret != FLASH_COMPLETE)
58 | {
59 | FLASH_Lock();
60 | log_printf(LOG_Error, "FLASHE Program error %d\r\n", ret);
61 | return HAL_ERROR;
62 | }
63 | ret=FLASH_ProgramHalfWord(Address+2, Data>>16);
64 | if(ret != FLASH_COMPLETE)
65 | {
66 | FLASH_Lock();
67 | log_printf(LOG_Error, "FLASHE Program error %d\r\n", ret);
68 | return HAL_ERROR;
69 | }
70 |
71 | FLASH_Lock();
72 | return HAL_OK;
73 | }
74 |
--------------------------------------------------------------------------------
/eeprom_port/eeprom_port_gd32f1.c:
--------------------------------------------------------------------------------
1 | #include "eeprom_in_flash.h"
2 |
3 | #define FMC_PAGE_SIZE ((uint16_t)0x400U)
4 |
5 | //EEPROM_PART0 0x0800F000 - 0x0800F800 size 2048
6 | //EEPROM_PART1 0x0800F800 - 0x08001000 size 2048
7 |
8 | /* Erase from PART_BASE_ADDRESS, size EEPROM_PART_SIZE */
9 | int EE_ErasePart(int part)
10 | {
11 | uint32_t time_use = HAL_GetTick();
12 | int ret;
13 | uint32_t erase_address = part == 0 ? PART0_BASE_ADDRESS : PART1_BASE_ADDRESS;
14 | uint32_t erase_size = part == 0 ? EEPROM_PART0_SIZE : EEPROM_PART1_SIZE;
15 |
16 | if (erase_address < PART0_BASE_ADDRESS || erase_address >= PART1_END_ADDRESS)
17 | return HAL_ERROR;
18 |
19 | log_printf(LOG_Debug, "FLASHE Erase 0x%08x size %#x\r\n", erase_address, erase_size);
20 |
21 | fmc_unlock();
22 |
23 | fmc_flag_clear(FMC_FLAG_BANK0_END);
24 | fmc_flag_clear(FMC_FLAG_BANK0_WPERR);
25 | fmc_flag_clear(FMC_FLAG_BANK0_PGERR);
26 |
27 | ret = fmc_page_erase(erase_address);
28 | fmc_flag_clear(FMC_FLAG_BANK0_END);
29 | fmc_flag_clear(FMC_FLAG_BANK0_WPERR);
30 | fmc_flag_clear(FMC_FLAG_BANK0_PGERR);
31 | if(ret != FMC_READY)
32 | {
33 | fmc_lock();
34 | log_printf(LOG_Error, "FLASHE Erase error %d at %#x\r\n", ret, erase_address);
35 | return HAL_ERROR;
36 | }
37 |
38 | ret = fmc_page_erase(erase_address + FMC_PAGE_SIZE);
39 | fmc_flag_clear(FMC_FLAG_BANK0_END);
40 | fmc_flag_clear(FMC_FLAG_BANK0_WPERR);
41 | fmc_flag_clear(FMC_FLAG_BANK0_PGERR);
42 | if(ret != FMC_READY)
43 | {
44 | fmc_lock();
45 | log_printf(LOG_Error, "FLASHE Erase error %d at %#x\r\n", ret, erase_address + FMC_PAGE_SIZE);
46 | return HAL_ERROR;
47 | }
48 |
49 | fmc_lock();
50 | log_printf(LOG_Verbose, "FLASHE Erase over, use %dms\r\n", HAL_GetTick() - time_use);
51 | return HAL_OK;
52 | }
53 |
54 | /* If the write operation is not a 32-bit atomic operation,
55 | Write the low 16-bit first, then write the high 16-bit */
56 | int EE_ProgramWord(uint32_t Address, uint32_t Data)
57 | {
58 | int ret;
59 |
60 | if (Address < PART0_BASE_ADDRESS || Address >= PART1_END_ADDRESS)
61 | return HAL_ERROR;
62 |
63 | log_printf(LOG_Debug, "FLASHE Program 0x%08x 0x%08x\r\n", Address, Data);
64 |
65 | fmc_unlock();
66 |
67 | ret = fmc_halfword_program(address, data0);
68 | fmc_flag_clear(FMC_FLAG_BANK0_END);
69 | fmc_flag_clear(FMC_FLAG_BANK0_WPERR);
70 | fmc_flag_clear(FMC_FLAG_BANK0_PGERR);
71 | if (ret != FMC_READY)
72 | {
73 | fmc_lock();
74 | log_printf(LOG_Error, "FLASHE Program error %d\r\n", ret);
75 | return HAL_ERROR;
76 | }
77 | ret = fmc_halfword_program(Address + 2, Data >> 16);
78 | fmc_flag_clear(FMC_FLAG_BANK0_END);
79 | fmc_flag_clear(FMC_FLAG_BANK0_WPERR);
80 | fmc_flag_clear(FMC_FLAG_BANK0_PGERR);
81 | if (ret != FMC_READY)
82 | {
83 | fmc_lock();
84 | log_printf(LOG_Error, "FLASHE Program error %d\r\n", ret);
85 | return HAL_ERROR;
86 | }
87 |
88 | fmc_lock();
89 | return HAL_OK;
90 | }
91 |
--------------------------------------------------------------------------------
/eeprom_port/eeprom_port_stm32f1.c:
--------------------------------------------------------------------------------
1 | #include "eeprom_in_flash.h"
2 |
3 | #if defined(STM32F103xE)
4 | #define PAGE_SIZE 2048
5 | #else
6 | #define PAGE_SIZE 1024
7 | #endif
8 |
9 | //EEPROM_PART0 0x0800F000 - 0x0800F800 size 2048
10 | //EEPROM_PART1 0x0800F800 - 0x08001000 size 2048
11 |
12 | /* Erase from PART_BASE_ADDRESS, size EEPROM_PART_SIZE */
13 | int EE_ErasePart(int part)
14 | {
15 | uint32_t PageError = 0;
16 | uint32_t time_use = HAL_GetTick();
17 | int ret;
18 | uint32_t erase_address = part == 0 ? PART0_BASE_ADDRESS : PART1_BASE_ADDRESS;
19 | uint32_t erase_size = part == 0 ? EEPROM_PART0_SIZE : EEPROM_PART1_SIZE;
20 |
21 | if (erase_address < PART0_BASE_ADDRESS || erase_address >= PART1_END_ADDRESS)
22 | return HAL_ERROR;
23 |
24 | log_printf(LOG_Debug, "FLASHE Erase 0x%08x size %#x\r\n", erase_address, erase_size);
25 |
26 | HAL_FLASH_Unlock();
27 |
28 | FLASH_EraseInitTypeDef EraseInitStruct;
29 | EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
30 | EraseInitStruct.NbPages = erase_size / PAGE_SIZE;
31 | EraseInitStruct.PageAddress = erase_address;
32 |
33 | ret = HAL_FLASHEx_Erase(&EraseInitStruct, &PageError);
34 | if (ret != HAL_OK)
35 | {
36 | HAL_FLASH_Lock();
37 | log_printf(LOG_Error, "FLASHE Erase error %d at %#x\r\n", ret, PageError);
38 | return HAL_ERROR;
39 | }
40 |
41 | HAL_FLASH_Lock();
42 | log_printf(LOG_Verbose, "FLASHE Erase over, use %dms\r\n", HAL_GetTick() - time_use);
43 | return HAL_OK;
44 | }
45 |
46 | /* If the write operation is not a 32-bit atomic operation,
47 | Write the low 16-bit first, then write the high 16-bit */
48 | int EE_ProgramWord(uint32_t Address, uint32_t Data)
49 | {
50 | int ret;
51 |
52 | if (Address < PART0_BASE_ADDRESS || Address >= PART1_END_ADDRESS)
53 | return HAL_ERROR;
54 |
55 | log_printf(LOG_Debug, "FLASHE Program 0x%08x 0x%08x\r\n", Address, Data);
56 |
57 | HAL_FLASH_Unlock();
58 |
59 | ret = HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, Address, Data);
60 | if (ret != HAL_OK)
61 | {
62 | HAL_FLASH_Lock();
63 | log_printf(LOG_Error, "FLASHE Program error %d\r\n", ret);
64 | return HAL_ERROR;
65 | }
66 | ret = HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, Address + 2, Data >> 16);
67 | if (ret != HAL_OK)
68 | {
69 | HAL_FLASH_Lock();
70 | log_printf(LOG_Error, "FLASHE Program error %d\r\n", ret);
71 | return HAL_ERROR;
72 | }
73 |
74 | HAL_FLASH_Lock();
75 | return HAL_OK;
76 | }
77 |
--------------------------------------------------------------------------------