├── dist ├── Assets │ └── donkeykong │ │ ├── common │ │ └── .keep │ │ └── ericlewis.donkeykong │ │ ├── Donkey Kong (US set 2).json │ │ ├── Donkey Kong (US, Set 1).json │ │ ├── Donkey Kong Junior.json │ │ ├── Donkey Kong (Japan set 1).json │ │ ├── Donkey Kong (Japan set 2).json │ │ ├── Donkey Kong (Japan set 3).json │ │ ├── Donkey Kong (hard kit).json │ │ ├── Donkey Kong Foundry (hack).json │ │ ├── Naked Donkey Kong - HBMame.json │ │ ├── Donkey Kong (2 marios) - HBMame.json │ │ ├── Donkey Kong (patched) - HBMame.json │ │ ├── Donkey Kong Foundry - HBMame.json │ │ ├── Rainbow Donkey Kong - HBMame.json │ │ ├── Donkey Kong (2600 graphics) - HBMame.json │ │ ├── Donkey Kong Remix demo 1.8 - HBMame.json │ │ ├── Donkey Kong (Pacman graphics) - HBMame.json │ │ ├── Donkey Kong Pauline Edition Rev 5 (2013-04-22).json │ │ └── Donkey Kong (US set 1 with barrel control coloring) - HBMame.json ├── Cores │ └── ericlewis.DonkeyKong │ │ ├── audio.json │ │ ├── icon.bin │ │ ├── input.json │ │ ├── variants.json │ │ ├── bitstream.rbf_r │ │ ├── video.json │ │ ├── interact.json │ │ ├── data.json │ │ └── core.json └── Platforms │ ├── _images │ └── donkeykong.bin │ └── donkeykong.json ├── src └── fpga │ ├── output_files │ ├── .gitignore │ ├── ap_core.rbf │ ├── ap_core.sof │ ├── bitstream.rbf_r │ ├── reverse_bits.exe │ ├── run.bat │ └── ap_core.jdi │ ├── core │ ├── mf_pllbase_sim.f │ ├── mf_pllbase_sim │ │ ├── cadence │ │ │ ├── hdl.var │ │ │ └── cds.lib │ │ └── synopsys │ │ │ └── vcsmx │ │ │ └── synopsys_sim.setup │ ├── rtl │ │ ├── t48 │ │ │ ├── README │ │ │ ├── clock_ctrl-c.vhd │ │ │ ├── timer-c.vhd │ │ │ ├── p1-c.vhd │ │ │ ├── p2-c.vhd │ │ │ ├── psw-c.vhd │ │ │ ├── int-c.vhd │ │ │ ├── pmem_ctrl-c.vhd │ │ │ ├── system │ │ │ │ ├── wb_master-c.vhd │ │ │ │ ├── generic_ram_ena-c.vhd │ │ │ │ ├── t48_rom-struct-c.vhd │ │ │ │ ├── t49_rom-struct-c.vhd │ │ │ │ ├── t8039-c.vhd │ │ │ │ ├── t8048-c.vhd │ │ │ │ ├── t8039_notri-c.vhd │ │ │ │ ├── t8048_notri-c.vhd │ │ │ │ ├── t8050_wb-c.vhd │ │ │ │ ├── t48_rom-e.vhd │ │ │ │ ├── t49_rom-e.vhd │ │ │ │ ├── t48_rom-struct-a.vhd │ │ │ │ ├── t49_rom-struct-a.vhd │ │ │ │ └── generic_ram_ena.vhd │ │ │ ├── db_bus-c.vhd │ │ │ ├── bus_mux-c.vhd │ │ │ ├── opc_table-c.vhd │ │ │ ├── alu-c.vhd │ │ │ ├── dmem_ctrl-c.vhd │ │ │ ├── cond_branch-c.vhd │ │ │ ├── t48_tb_pack-p.vhd │ │ │ ├── opc_decoder-c.vhd │ │ │ ├── decoder-c.vhd │ │ │ ├── pmem_ctrl_pack-p.vhd │ │ │ ├── dmem_ctrl_pack-p.vhd │ │ │ ├── cond_branch_pack-p.vhd │ │ │ ├── alu_pack-p.vhd │ │ │ ├── t48_core-c.vhd │ │ │ ├── T48.qip │ │ │ ├── t48_pack-p.vhd │ │ │ ├── syn_ram-e.vhd │ │ │ ├── decoder_pack-p.vhd │ │ │ ├── t48_core_comp_pack-p.vhd │ │ │ ├── bus_mux.vhd │ │ │ ├── p1.vhd │ │ │ └── db_bus.vhd │ │ ├── mister-discrete │ │ │ ├── LFSR.sv │ │ │ ├── rate_of_change_limiter.sv │ │ │ ├── natural_log.sv │ │ │ ├── resistor_capacitor_low_pass_filter.sv │ │ │ ├── resistive_two_way_mixer.sv │ │ │ ├── resistor_capacitor_high_pass_filter.sv │ │ │ ├── invertor_square_wave_oscilator.sv │ │ │ ├── Log2highacc.sv │ │ │ ├── astable_555_vco.sv │ │ │ └── dk_walk.sv │ │ ├── T80 │ │ │ ├── T80.qip │ │ │ ├── README │ │ │ ├── Z80.vhd │ │ │ ├── T80_Reg.vhd │ │ │ └── T80sed.vhd │ │ ├── dkong_dma.v │ │ ├── dpram.vhd │ │ ├── i8035ip.v │ │ ├── dkong_col_pal.v │ │ ├── dkong_logic.v │ │ ├── dkong_sound.v │ │ ├── dkong_soundboard.sv │ │ ├── radarscp_stars.v │ │ ├── dkong_hv_count.v │ │ ├── dkong_wav_sound.v │ │ ├── pause.v │ │ └── dkong_bram.v │ ├── mf_pllbase.spd │ ├── mf_pllbase │ │ ├── mf_pllbase_0002.qip │ │ └── mf_pllbase_0002.v │ ├── pin_ddio_clk.qip │ ├── pin_ddio_clk.ppf │ ├── mf_pllbase.sip │ ├── core_constraints.sdc │ ├── mf_pllbase.ppf │ ├── sync_fifo.sv │ ├── pin_ddio_clk.v │ ├── mf_pllbase.bsf │ └── sound_i2s.sv │ ├── apf │ ├── build_id.mif │ ├── mf_datatable.qip │ ├── mf_ddio_bidir_12.qip │ ├── apf_constraints.sdc │ ├── apf.qip │ ├── mf_ddio_bidir_12.ppf │ └── mf_ddio_bidir_12.v │ ├── .gitignore │ └── ap_core.qpf └── README.md /dist/Assets/donkeykong/common/.keep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/fpga/output_files/.gitignore: -------------------------------------------------------------------------------- 1 | !*.sof 2 | !*.rbf -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim.f: -------------------------------------------------------------------------------- 1 | mf_pllbase_sim/mf_pllbase.vo 2 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/audio.json: -------------------------------------------------------------------------------- 1 | { 2 | "audio": { 3 | "magic": "APF_VER_1" 4 | } 5 | } -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ericlewis/openFPGA-DonkeyKong/HEAD/src/fpga/core/rtl/t48/README -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.rbf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ericlewis/openFPGA-DonkeyKong/HEAD/src/fpga/output_files/ap_core.rbf -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ericlewis/openFPGA-DonkeyKong/HEAD/src/fpga/output_files/ap_core.sof -------------------------------------------------------------------------------- /dist/Platforms/_images/donkeykong.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ericlewis/openFPGA-DonkeyKong/HEAD/dist/Platforms/_images/donkeykong.bin -------------------------------------------------------------------------------- /src/fpga/output_files/bitstream.rbf_r: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ericlewis/openFPGA-DonkeyKong/HEAD/src/fpga/output_files/bitstream.rbf_r -------------------------------------------------------------------------------- /src/fpga/output_files/reverse_bits.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ericlewis/openFPGA-DonkeyKong/HEAD/src/fpga/output_files/reverse_bits.exe -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/icon.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ericlewis/openFPGA-DonkeyKong/HEAD/dist/Cores/ericlewis.DonkeyKong/icon.bin -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/input.json: -------------------------------------------------------------------------------- 1 | { 2 | "input": { 3 | "magic": "APF_VER_1", 4 | "controllers": [] 5 | } 6 | } -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/variants.json: -------------------------------------------------------------------------------- 1 | { 2 | "variants": { 3 | "magic": "APF_VER_1", 4 | "variant_list": [] 5 | } 6 | } -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/bitstream.rbf_r: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ericlewis/openFPGA-DonkeyKong/HEAD/dist/Cores/ericlewis.DonkeyKong/bitstream.rbf_r -------------------------------------------------------------------------------- /dist/Platforms/donkeykong.json: -------------------------------------------------------------------------------- 1 | { 2 | "platform": { 3 | "category": "Arcade", 4 | "name": "Donkey Kong", 5 | "year": 1981, 6 | "manufacturer": "Nintendo" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/fpga/output_files/run.bat: -------------------------------------------------------------------------------- 1 | reverse_bits.exe ap_core.rbf bitstream.rbf_r 2 | copy /y bitstream.rbf_r "E:\Cores\ericlewis.DonkeyKong\bitstream.rbf_r" 3 | copy /y bitstream.rbf_r "..\..\..\dist\Cores\ericlewis.DonkeyKong\bitstream.rbf_r" -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/fpga/output_files/ap_core.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/fpga/apf/build_id.mif: -------------------------------------------------------------------------------- 1 | -- Build ID Memory Initialization File 2 | -- 3 | 4 | DEPTH = 256; 5 | WIDTH = 32; 6 | ADDRESS_RADIX = HEX; 7 | DATA_RADIX = HEX; 8 | 9 | CONTENT 10 | BEGIN 11 | 12 | 0E0 : 20221014; 13 | 0E1 : 00200918; 14 | 0E2 : df5e8f08; 15 | 16 | END; 17 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_datatable.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "21.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_datatable.v"] 5 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase/mf_pllbase_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/video.json: -------------------------------------------------------------------------------- 1 | { 2 | "video": { 3 | "magic": "APF_VER_1", 4 | "scaler_modes": [ 5 | { 6 | "width": 256, 7 | "height": 224, 8 | "aspect_w": 8, 9 | "aspect_h": 7, 10 | "rotation": 90, 11 | "mirror": 0 12 | } 13 | ] 14 | } 15 | } -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" 2 | set_global_assignment -name IP_TOOL_VERSION "21.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.ppf"] 6 | -------------------------------------------------------------------------------- /src/fpga/.gitignore: -------------------------------------------------------------------------------- 1 | */db/ 2 | */incremental_db/ 3 | */simulation/ 4 | */greybox_tmp/ 5 | incremental_db/ 6 | db/ 7 | PLLJ_PLLSPE_INFO.txt 8 | c5_pin_model_dump.txt 9 | cr_ie_info.json 10 | *.pin 11 | *.pof 12 | *.ptf.* 13 | *.qar 14 | *.qarlog 15 | *.qws 16 | *.rpt 17 | *.smsg 18 | *.sof 19 | *.sopc_builder 20 | *.summary 21 | *.txt 22 | *.bak 23 | *.cmp 24 | *.done 25 | *.xml 26 | *.sld 27 | *.cdf 28 | 29 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/clock_ctrl-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: clock_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- The clock control unit. 6 | -- 7 | ------------------------------------------------------------------------------- 8 | 9 | configuration t48_clock_ctrl_rtl_c0 of t48_clock_ctrl is 10 | 11 | for rtl 12 | end for; 13 | 14 | end t48_clock_ctrl_rtl_c0; 15 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/timer-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Timer/Counter unit. 4 | -- 5 | -- $Id: timer-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | configuration t48_timer_rtl_c0 of t48_timer is 12 | 13 | for rtl 14 | end for; 15 | 16 | end t48_timer_rtl_c0; 17 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/p1-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Port 1 unit. 4 | -- Implements the Port 1 logic. 5 | -- 6 | -- $Id: p1-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_p1_rtl_c0 of t48_p1 is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_p1_rtl_c0; 18 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/p2-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Port 2 unit. 4 | -- Implements the Port 2 logic. 5 | -- 6 | -- $Id: p2-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_p2_rtl_c0 of t48_p2 is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_p2_rtl_c0; 18 | -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pin_ddio_clk.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pin_ddio_clk_inst.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pin_ddio_clk.ppf"] 7 | -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (US set 2).json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongo.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (US, Set 1).json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkong.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong Junior.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongjr.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (Japan set 1).json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongj.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (Japan set 2).json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongjo.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (Japan set 3).json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongjo1.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (hard kit).json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkonghrd.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong Foundry (hack).json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongf.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Naked Donkey Kong - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "nadkong.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/psw-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Program Status Word (PSW). 4 | -- Implements the PSW with its special bits. 5 | -- 6 | -- $Id: psw-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_psw_rtl_c0 of t48_psw is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_psw_rtl_c0; 18 | -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (2 marios) - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkong2m.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (patched) - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongp.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong Foundry - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongex.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Rainbow Donkey Kong - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkraibow.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (2600 graphics) - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "kong2600.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong Remix demo 1.8 - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkrdemo.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/int-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Interrupt Controller. 4 | -- It collects the interrupt sources and notifies the decoder. 5 | -- 6 | -- $Id: int-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_int_rtl_c0 of t48_int is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_int_rtl_c0; 18 | -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (Pacman graphics) - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongpac.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong Pauline Edition Rev 5 (2013-04-22).json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongpe.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /dist/Assets/donkeykong/ericlewis.donkeykong/Donkey Kong (US set 1 with barrel control coloring) - HBMame.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance":{ 3 | "magic": "APF_VER_1", 4 | "variant_select": { 5 | "id": 0, 6 | "select": false 7 | }, 8 | "data_path": "", 9 | "data_slots": [ 10 | { 11 | "id": 1, 12 | "filename": "dkongbcc.rom" 13 | } 14 | ], 15 | "memory_writes": [ 16 | { 17 | "address": "0xf9000000", 18 | "data": "0x0" 19 | }, 20 | { 21 | "address": "0xfa000000", 22 | "data": "0x" 23 | } 24 | ] 25 | } 26 | } -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_VERSION "21.1" 3 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_mf_pllbase" -name SPD_FILE [file join $::quartus(sip_path) "mf_pllbase.spd"] 5 | 6 | set_global_assignment -library "lib_mf_pllbase" -name MISC_FILE [file join $::quartus(sip_path) "mf_pllbase_sim/mf_pllbase.vo"] 7 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/pmem_ctrl-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Program Memory control unit. 4 | -- All operations related to the Program Memory are managed here. 5 | -- 6 | -- $Id: pmem_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- All rights reserved 9 | -- 10 | ------------------------------------------------------------------------------- 11 | 12 | configuration t48_pmem_ctrl_rtl_c0 of t48_pmem_ctrl is 13 | 14 | for rtl 15 | end for; 16 | 17 | end t48_pmem_ctrl_rtl_c0; 18 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/wb_master-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Wishbone master module. 4 | -- 5 | -- $Id: wb_master-c.vhd,v 1.2 2005/06/11 10:16:05 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t48_wb_master_rtl_c0 of t48_wb_master is 14 | 15 | for rtl 16 | end for; 17 | 18 | end t48_wb_master_rtl_c0; 19 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/db_bus-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The BUS unit. 4 | -- Implements the BUS port logic. 5 | -- 6 | -- $Id: db_bus-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_db_bus_rtl_c0 of t48_db_bus is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_db_bus_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/core_constraints.sdc: -------------------------------------------------------------------------------- 1 | # 2 | # user core constraints 3 | # 4 | # put your clock groups in here as well as any net assignments 5 | # 6 | 7 | set_clock_groups -asynchronous \ 8 | -group { bridge_spiclk } \ 9 | -group { clk_74a } \ 10 | -group { clk_74b } \ 11 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ 12 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ 13 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } 14 | 15 | derive_clock_uncertainty -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/bus_mux-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The T48 Bus Connector. 4 | -- Multiplexes all drivers of the T48 bus. 5 | -- 6 | -- $Id: bus_mux-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_bus_mux_rtl_c0 of t48_bus_mux is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_bus_mux_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/opc_table-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Opcode Decoder Table. 4 | -- Decodes the given opcode to instruction mnemonics. 5 | -- Also derives the multicycle information. 6 | -- 7 | -- $Id: opc_table-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t48_opc_table_rtl_c0 of t48_opc_table is 14 | 15 | for rtl 16 | end for; 17 | 18 | end t48_opc_table_rtl_c0; 19 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/generic_ram_ena-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- Parametrizable, generic RAM with enable. 4 | -- 5 | -- $Id: generic_ram_ena-c.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration generic_ram_ena_rtl_c0 of generic_ram_ena is 14 | 15 | for rtl 16 | end for; 17 | 18 | end generic_ram_ena_rtl_c0; 19 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/alu-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Arithmetic Logic Unit (ALU). 4 | -- It contains the ALU core plus the Accumulator and the Temp Reg. 5 | -- 6 | -- $Id: alu-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_alu_rtl_c0 of t48_alu is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_alu_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/dmem_ctrl-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Data Memory control unit. 4 | -- All accesses to the Data Memory are managed here. 5 | -- 6 | -- $Id: dmem_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_dmem_ctrl_rtl_c0 of t48_dmem_ctrl is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_dmem_ctrl_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/LFSR.sv: -------------------------------------------------------------------------------- 1 | module LFSR( 2 | input clk, 3 | input audio_clk_en, 4 | input I_RSTn, 5 | output reg [7:0] LFSR = 255 // put here the initial value 6 | ); 7 | 8 | wire feedback = LFSR[7]; 9 | 10 | always @(posedge clk) begin 11 | if(!I_RSTn)begin 12 | LFSR <= 255; 13 | end else if(audio_clk_en) begin 14 | LFSR[0] <= feedback; 15 | LFSR[1] <= LFSR[0]; 16 | LFSR[2] <= LFSR[1] ^ feedback; 17 | LFSR[3] <= LFSR[2] ^ feedback; 18 | LFSR[4] <= LFSR[3] ^ feedback; 19 | LFSR[5] <= LFSR[4]; 20 | LFSR[6] <= LFSR[5]; 21 | LFSR[7] <= LFSR[6]; 22 | end 23 | end 24 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/fpga/apf/apf_constraints.sdc: -------------------------------------------------------------------------------- 1 | # 2 | # APF constraints 3 | # Do not edit this file. 4 | # 5 | # Add your own constraints in the \core_constraints.sdc in the core directory, which will also be loaded. 6 | 7 | create_clock -name clk_74a -period 13.468 [get_ports clk_74a] 8 | create_clock -name clk_74b -period 13.468 [get_ports clk_74b] 9 | create_clock -name bridge_spiclk -period 13.468 [get_ports bridge_spiclk] 10 | 11 | # autogenerate PLL clock names for use down below 12 | derive_pll_clocks 13 | 14 | 15 | # io constraints go here 16 | # 17 | 18 | 19 | # load in user constraints 20 | read_sdc "core/core_constraints.sdc" -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/cond_branch-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Conditional Branch Logic unit. 4 | -- Decisions whether to take a jump or not are made here. 5 | -- 6 | -- $Id: cond_branch-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_cond_branch_rtl_c0 of t48_cond_branch is 15 | 16 | for rtl 17 | end for; 18 | 19 | end t48_cond_branch_rtl_c0; 20 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t48_rom-struct-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x48 ROM 4 | -- 5 | -- $Id: t48_rom-struct-c.vhd,v 1.1.1.1 2006/11/26 10:07:52 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t48_rom_struct_c0 of t48_rom is 14 | 15 | for struct 16 | 17 | for rom_b: rom_t48 18 | use configuration work.rom_t48_rtl_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t48_rom_struct_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t49_rom-struct-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x49 ROM 4 | -- 5 | -- $Id: t49_rom-struct-c.vhd,v 1.1.1.1 2006/11/26 10:07:52 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t49_rom_struct_c0 of t49_rom is 14 | 15 | for struct 16 | 17 | for rom_b: rom_t49 18 | use configuration work.rom_t49_rtl_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t49_rom_struct_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/apf/apf.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "apf_top.v"] 2 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "common.v"] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_bridge_peripheral.v"] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_pad_controller.v"] 5 | set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "apf_constraints.sdc"] 6 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.qip"] 7 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_datatable.qip"] 8 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8039-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8039 Microcontroller System 4 | -- 5 | -- $Id: t8039-c.vhd,v 1.2 2004/12/03 19:43:12 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t8039_struct_c0 of t8039 is 14 | 15 | for struct 16 | 17 | for t8039_notri_b : t8039_notri 18 | use configuration work.t8039_notri_struct_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t8039_struct_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8048-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8048 Microcontroller System 4 | -- 5 | -- $Id: t8048-c.vhd,v 1.2 2004/12/01 23:09:47 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t8048_struct_c0 of t8048 is 14 | 15 | for struct 16 | 17 | for t8048_notri_b : t8048_notri 18 | use configuration work.t8048_notri_struct_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t8048_struct_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/t48_tb_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: t48_tb_pack-p.vhd,v 1.2 2004/04/14 20:53:54 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | package t48_tb_pack is 15 | 16 | -- Instruction strobe visibility 17 | signal tb_istrobe_s : std_logic; 18 | 19 | -- Accumulator visibilty 20 | signal tb_accu_s : std_logic_vector(7 downto 0); 21 | 22 | end t48_tb_pack; 23 | -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/interact.json: -------------------------------------------------------------------------------- 1 | { 2 | "interact": { 3 | "magic": "APF_VER_1", 4 | "variables": [ 5 | { 6 | "type": "default", 7 | "mappings": [ 8 | { 9 | "id": 1, 10 | "name": "Insert coin", 11 | "key": "pad_btn_select" 12 | }, 13 | { 14 | "id": 2, 15 | "name": "Start Game", 16 | "key": "pad_btn_start" 17 | } 18 | ] 19 | } 20 | ], 21 | "messages": [] 22 | } 23 | } -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/opc_decoder-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Opcode Decoder. 4 | -- Derives instruction mnemonics and multicycle information 5 | -- using the OPC table unit. 6 | -- 7 | -- $Id: opc_decoder-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t48_opc_decoder_rtl_c0 of t48_opc_decoder is 14 | 15 | for rtl 16 | 17 | for opc_table_b: t48_opc_table 18 | use configuration work.t48_opc_table_rtl_c0; 19 | end for; 20 | 21 | end for; 22 | 23 | end t48_opc_decoder_rtl_c0; 24 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera_ver: ./libraries/altera_ver/ 6 | lpm_ver: ./libraries/lpm_ver/ 7 | sgate_ver: ./libraries/sgate_ver/ 8 | altera_mf_ver: ./libraries/altera_mf_ver/ 9 | altera_lnsim_ver: ./libraries/altera_lnsim_ver/ 10 | cyclonev_ver: ./libraries/cyclonev_ver/ 11 | cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/ 12 | cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/ 13 | LIBRARY_SCAN = TRUE 14 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/decoder-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Decoder unit. 4 | -- It decodes the instruction opcodes and executes them. 5 | -- 6 | -- $Id: decoder-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t48_decoder_rtl_c0 of t48_decoder is 15 | 16 | for rtl 17 | 18 | for opc_decoder_b: t48_opc_decoder 19 | use configuration work.t48_opc_decoder_rtl_c0; 20 | end for; 21 | 22 | for int_b: t48_int 23 | use configuration work.t48_int_rtl_c0; 24 | end for; 25 | 26 | end for; 27 | 28 | end t48_decoder_rtl_c0; 29 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8039_notri-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8039 Microcontroller System 4 | -- 8039 toplevel without tri-states 5 | -- 6 | -- $Id: t8039_notri-c.vhd,v 1.2 2006/06/21 01:02:35 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | ------------------------------------------------------------------------------- 13 | 14 | configuration t8039_notri_struct_c0 of t8039_notri is 15 | 16 | for struct 17 | 18 | for ram_128_b : generic_ram_ena 19 | use configuration work.generic_ram_ena_rtl_c0; 20 | end for; 21 | 22 | for t48_core_b : t48_core 23 | use configuration work.t48_core_struct_c0; 24 | end for; 25 | 26 | end for; 27 | 28 | end t8039_notri_struct_c0; 29 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8048_notri-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8048 Microcontroller System 4 | -- 5 | -- $Id: t8048_notri-c.vhd,v 1.2 2006/06/21 01:02:16 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t8048_notri_struct_c0 of t8048_notri is 14 | 15 | for struct 16 | 17 | for rom_1k_b : t48_rom 18 | use configuration work.t48_rom_lpm_c0; 19 | end for; 20 | 21 | for ram_64_b : generic_ram_ena 22 | use configuration work.generic_ram_ena_rtl_c0; 23 | end for; 24 | 25 | for t48_core_b : t48_core 26 | use configuration work.t48_core_struct_c0; 27 | end for; 28 | 29 | end for; 30 | 31 | end t8048_notri_struct_c0; 32 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t8050_wb-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8048 Microcontroller System 4 | -- 5 | -- $Id: t8050_wb-c.vhd,v 1.2 2005/06/11 10:19:14 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | ------------------------------------------------------------------------------- 12 | 13 | configuration t8050_wb_struct_c0 of t8050_wb is 14 | 15 | for struct 16 | 17 | for rom_4k_b : syn_rom 18 | use configuration work.syn_rom_lpm_c0; 19 | end for; 20 | 21 | for ram_256_b : syn_ram 22 | use configuration work.syn_ram_lpm_c0; 23 | end for; 24 | 25 | for wb_master_b : t48_wb_master 26 | use configuration work.t48_wb_master_rtl_c0; 27 | end for; 28 | 29 | for t48_core_b : t48_core 30 | use configuration work.t48_core_struct_c0; 31 | end for; 32 | 33 | end for; 34 | 35 | end t8050_wb_struct_c0; 36 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Donkey Kong 2 | 3 | Analogue Pocket port of Donkey Kong. 4 | 5 | ## Known Issues 6 | 7 | * High Score saving doesn't work. 8 | * No dips. 9 | * Doesn't support Pest Place or Radar Scope. 10 | * Or Donkey Kong, Jr. 11 | 12 | ## Attribution 13 | 14 | ``` 15 | --------------------------------------------------------------------------------- 16 | -- 17 | -- Arcade: Donkey Kong port to MiSTer by Sorgelig 18 | -- 18 April 2018 19 | -- 20 | --------------------------------------------------------------------------------- 21 | -- 22 | -- dkong Copyright (c) 2003 - 2004 Katsumi Degawa 23 | -- T80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) All rights reserved 24 | -- T48 Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) All rights reserved 25 | -- 26 | ``` 27 | 28 | ## ROM Instructions 29 | 30 | ROM files are not included, you must use [mra-tools-c](https://github.com/sebdel/mra-tools-c/) to convert to a singular `dkong.rom` file, then place the ROM file in `/Assets/donkeykong/common`. 31 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/rate_of_change_limiter.sv: -------------------------------------------------------------------------------- 1 | module rate_of_change_limiter #( 2 | parameter VCC = 12, 3 | parameter SAMPLE_RATE = 48000, 4 | parameter MAX_CHANGE_RATE = 1000 //10 V/s 5 | ) ( 6 | input clk, 7 | input I_RSTn, 8 | input audio_clk_en, 9 | input signed[15:0] in, 10 | output reg signed[15:0] out = 0 11 | ); 12 | localparam longint MAX_CHANGE_PER_SAMPLE = (MAX_CHANGE_RATE << 14) / VCC / SAMPLE_RATE; 13 | 14 | wire signed[16:0] difference; 15 | assign difference = in - out; 16 | always@(posedge clk, negedge I_RSTn) begin 17 | if(!I_RSTn)begin 18 | out <= 0; 19 | end else if(audio_clk_en) begin 20 | if(difference < -MAX_CHANGE_PER_SAMPLE)begin 21 | out <= out - MAX_CHANGE_PER_SAMPLE; 22 | end else if(difference > MAX_CHANGE_PER_SAMPLE) begin 23 | out <= out + MAX_CHANGE_PER_SAMPLE; 24 | end else begin 25 | out <= in; 26 | end 27 | end 28 | end 29 | endmodule -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/data.json: -------------------------------------------------------------------------------- 1 | { 2 | "data": { 3 | "magic": "APF_VER_1", 4 | "data_slots": [ 5 | { 6 | "name": "Arcade Game", 7 | "id": 0, 8 | "required": true, 9 | "parameters": "0x113", 10 | "extensions": [ 11 | "json" 12 | ], 13 | "address": "" 14 | }, 15 | { 16 | "name": "ROM", 17 | "id": 1, 18 | "required": true, 19 | "parameters": "0x109", 20 | "extensions": [ 21 | "rom" 22 | ], 23 | "address": "0x10000000" 24 | }, 25 | { 26 | "id": 10, 27 | "name": "HISCORE", 28 | "required": false, 29 | "nonvolatile": true, 30 | "parameters": "0x84", 31 | "extensions": ["sav"], 32 | "address": "0x20000000" 33 | } 34 | ] 35 | } 36 | } -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/T80.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) GBse.vhd ] 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80se.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80a.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80as.vhd ] 7 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80sed.vhd ] 8 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T8080se.vhd ] 9 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ] 10 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ] 11 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ] 12 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ] 13 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Pack.vhd ] -------------------------------------------------------------------------------- /dist/Cores/ericlewis.DonkeyKong/core.json: -------------------------------------------------------------------------------- 1 | { 2 | "core": { 3 | "magic": "APF_VER_1", 4 | "metadata": { 5 | "platform_ids": ["donkeykong"], 6 | "shortname": "DonkeyKong", 7 | "description": "Nintendo's Donkey Kong released in 1981.", 8 | "author": "ericlewis", 9 | "url": "https://github.com/ericlewis/openFPGA-DonkeyKong", 10 | "version": "0.0.1", 11 | "date_release": "2022-10-12" 12 | }, 13 | "framework": { 14 | "target_product": "Analogue Pocket", 15 | "version_required": "1.1", 16 | "sleep_supported": false, 17 | "dock": { 18 | "supported": true, 19 | "analog_output": false 20 | }, 21 | "hardware": { 22 | "link_port": false, 23 | "cartridge_adapter": -1 24 | } 25 | }, 26 | "cores": [ 27 | { 28 | "name": "default", 29 | "id": 0, 30 | "filename": "bitstream.rbf_r" 31 | } 32 | ] 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/natural_log.sv: -------------------------------------------------------------------------------- 1 | /********************************************************************************\ 2 | * 3 | * MiSTer Discrete natural log core 4 | * 5 | * Copyright 2022 by Jegor van Opdorp. 6 | * This program is free software under the terms of the GPLv3, see LICENCSE.txt 7 | * 8 | ********************************************************************************/ 9 | module natural_log(input clk, input[23:0] in_8_shifted, input I_RSTn, output reg[11:0] out_8_shifted); 10 | 11 | localparam RATIO_16_SHIFTED = 45426; // 1 / log2(e) 12 | 13 | wire[11:0] log2_x; 14 | 15 | // TODO: use more precise implementation of log2 16 | Log2highacc log2( 17 | .DIN_8_shifted(in_8_shifted < 24'h104 ? 24'h104 : in_8_shifted), //This implementation of log2 doesn't support input 1 or smaller 18 | .clk(clk), 19 | .DOUT_8_shifted(log2_x) 20 | ); 21 | 22 | always_ff @( posedge clk, negedge I_RSTn ) begin : blockName 23 | if(!I_RSTn)begin 24 | out_8_shifted <= 0; 25 | end else if(log2_x)begin 26 | out_8_shifted <= RATIO_16_SHIFTED * log2_x >> 16; 27 | end 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/pmem_ctrl_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: pmem_ctrl_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | package t48_pmem_ctrl_pack is 12 | 13 | ----------------------------------------------------------------------------- 14 | -- Address Type Identifier 15 | ----------------------------------------------------------------------------- 16 | type pmem_addr_ident_t is (PM_PC, 17 | PM_PAGE, 18 | PM_PAGE3); 19 | 20 | end t48_pmem_ctrl_pack; 21 | 22 | 23 | ------------------------------------------------------------------------------- 24 | -- File History: 25 | -- 26 | -- $Log: pmem_ctrl_pack-p.vhd,v $ 27 | -- Revision 1.2 2005/06/11 10:08:43 arniml 28 | -- introduce prefix 't48_' for all packages, entities and configurations 29 | -- 30 | -- Revision 1.1 2004/03/23 21:31:53 arniml 31 | -- initial check-in 32 | -- 33 | ------------------------------------------------------------------------------- 34 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/dmem_ctrl_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: dmem_ctrl_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | package t48_dmem_ctrl_pack is 12 | 13 | ----------------------------------------------------------------------------- 14 | -- Address Type Identifier 15 | ----------------------------------------------------------------------------- 16 | type dmem_addr_ident_t is (DM_PLAIN, 17 | DM_REG, 18 | DM_STACK, 19 | DM_STACK_HIGH); 20 | 21 | end t48_dmem_ctrl_pack; 22 | 23 | 24 | ------------------------------------------------------------------------------- 25 | -- File History: 26 | -- 27 | -- $Log: dmem_ctrl_pack-p.vhd,v $ 28 | -- Revision 1.2 2005/06/11 10:08:43 arniml 29 | -- introduce prefix 't48_' for all packages, entities and configurations 30 | -- 31 | -- Revision 1.1 2004/03/23 21:31:52 arniml 32 | -- initial check-in 33 | -- 34 | ------------------------------------------------------------------------------- 35 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera_ver ./libraries/altera_ver/ 13 | DEFINE lpm_ver ./libraries/lpm_ver/ 14 | DEFINE sgate_ver ./libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/ 20 | -------------------------------------------------------------------------------- /src/fpga/ap_core.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2019 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition 22 | # Date created = 21:31:36 January 22, 2020 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "18.1" 27 | DATE = "21:31:36 January 22, 2020" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "ap_core" 32 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/resistor_capacitor_low_pass_filter.sv: -------------------------------------------------------------------------------- 1 | /********************************************************************************\ 2 | * 3 | * MiSTer Discrete resistor_capacitor_low_pass filter 4 | * 5 | * Copyright 2022 by Jegor van Opdorp. 6 | * This program is free software under the terms of the GPLv3, see LICENCSE.txt 7 | * 8 | * based on https://en.wikipedia.org/wiki/Low-pass_filter 9 | * and https://zipcpu.com/dsp/2017/08/19/simple-filter.html 10 | * 11 | ********************************************************************************/ 12 | module resistor_capacitor_low_pass_filter #( 13 | parameter SAMPLE_RATE = 48000, 14 | parameter R = 47000, 15 | parameter C_35_SHIFTED = 1615 // 0.000000047 farads <<< 35 16 | ) ( 17 | input clk, 18 | input I_RSTn, 19 | input audio_clk_en, 20 | input signed[15:0] in, 21 | output reg signed[15:0] out = 0 22 | ); 23 | localparam longint DELTA_T_32_SHIFTED = (1 <<< 32) / SAMPLE_RATE; 24 | localparam longint R_C_32_SHIFTED = R * C_35_SHIFTED >>> 3; 25 | localparam longint SMOOTHING_FACTOR_ALPHA_16_SHIFTED = (DELTA_T_32_SHIFTED <<< 16) / (R_C_32_SHIFTED + DELTA_T_32_SHIFTED); 26 | 27 | always@(posedge clk, negedge I_RSTn) begin 28 | if(!I_RSTn)begin 29 | out <= 0; 30 | end else if(audio_clk_en)begin 31 | out <= out + (SMOOTHING_FACTOR_ALPHA_16_SHIFTED * (in - out) >>> 16); 32 | end 33 | end 34 | 35 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/cond_branch_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: cond_branch_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | package t48_cond_branch_pack is 15 | 16 | ----------------------------------------------------------------------------- 17 | -- The branch conditions. 18 | ----------------------------------------------------------------------------- 19 | type branch_conditions_t is (COND_ON_BIT, COND_Z, 20 | COND_C, 21 | COND_F0, COND_F1, 22 | COND_INT, 23 | COND_T0, COND_T1, 24 | COND_TF); 25 | 26 | subtype comp_value_t is std_logic_vector(2 downto 0); 27 | 28 | end t48_cond_branch_pack; 29 | 30 | 31 | ------------------------------------------------------------------------------- 32 | -- File History: 33 | -- 34 | -- $Log: cond_branch_pack-p.vhd,v $ 35 | -- Revision 1.2 2005/06/11 10:08:43 arniml 36 | -- introduce prefix 't48_' for all packages, entities and configurations 37 | -- 38 | -- Revision 1.1 2004/03/23 21:31:52 arniml 39 | -- initial check-in 40 | -- 41 | ------------------------------------------------------------------------------- 42 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/resistive_two_way_mixer.sv: -------------------------------------------------------------------------------- 1 | /********************************************************************************\ 2 | * 3 | * MiSTer Discrete resistive two way mixer 4 | * 5 | * Copyright 2022 by Jegor van Opdorp. 6 | * This program is free software under the terms of the GPLv3, see LICENCSE.txt 7 | * 8 | * inputs[0] inputs[1] 9 | * V V 10 | * | | 11 | * | | 12 | * Z Z 13 | * R0 Z Z R1 14 | * Z Z 15 | * | | 16 | * '----,----' 17 | * | 18 | * | 19 | * V 20 | * out 21 | * 22 | ********************************************************************************/ 23 | module resistive_two_way_mixer #( 24 | parameter longint R0 = 10000, 25 | parameter longint R1 = 10000 26 | ) ( 27 | input clk, 28 | input I_RSTn, 29 | input audio_clk_en, 30 | input[15:0] inputs[1:0], 31 | output reg[15:0] out = 0 32 | ); 33 | localparam integer R0_RATIO_16_SHIFTED = ((R1 <<< 16) / R0); 34 | localparam integer R1_RATIO_16_SHIFTED = ((R0 <<< 16) / R1); 35 | localparam longint NORMALIZATION_RATIO_16_SHIFTED = (1 <<< 32)/(R0_RATIO_16_SHIFTED+R1_RATIO_16_SHIFTED); 36 | 37 | always@(posedge clk, negedge I_RSTn) begin 38 | if(!I_RSTn)begin 39 | out <= 0; 40 | end else if(audio_clk_en)begin 41 | out <= (R0_RATIO_16_SHIFTED * inputs[0] + R1_RATIO_16_SHIFTED * inputs[1]) * NORMALIZATION_RATIO_16_SHIFTED >>> 32; 42 | end 43 | end 44 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/resistor_capacitor_high_pass_filter.sv: -------------------------------------------------------------------------------- 1 | /********************************************************************************\ 2 | * 3 | * MiSTer Discrete resistor_capacitor_low_pass filter 4 | * 5 | * Copyright 2022 by Jegor van Opdorp. 6 | * This program is free software under the terms of the GPLv3, see LICENCSE.txt 7 | * 8 | * based on https://en.wikipedia.org/wiki/Low-pass_filter 9 | * 10 | ********************************************************************************/ 11 | module resistor_capacitor_high_pass_filter #( 12 | parameter SAMPLE_RATE = 48000, 13 | parameter R = 47000, 14 | parameter C_35_SHIFTED = 1615 // 0.000000047 farads <<< 35 15 | ) ( 16 | input clk, 17 | input I_RSTn, 18 | input audio_clk_en, 19 | input signed[15:0] in, 20 | output reg signed[15:0] out = 0 21 | ); 22 | localparam longint DELTA_T_32_SHIFTED = (1 <<< 32) / SAMPLE_RATE; 23 | localparam longint R_C_32_SHIFTED = R * C_35_SHIFTED >>> 3; 24 | localparam longint SMOOTHING_FACTOR_ALPHA_16_SHIFTED = (R_C_32_SHIFTED <<< 16) / (R_C_32_SHIFTED + DELTA_T_32_SHIFTED); 25 | 26 | wire[7:0] random_number; 27 | 28 | LFSR lfsr( 29 | .clk(clk), 30 | .audio_clk_en(audio_clk_en), 31 | .I_RSTn(I_RSTn), 32 | .LFSR(random_number) 33 | ); 34 | 35 | reg signed[15:0] last_in = 0; 36 | always@(posedge clk, negedge I_RSTn) begin 37 | if(!I_RSTn)begin 38 | out <= 0; 39 | last_in <= 0; 40 | end else if(audio_clk_en)begin 41 | out <= SMOOTHING_FACTOR_ALPHA_16_SHIFTED * (out + in - last_in) >> 16; 42 | last_in <= in + ((random_number >>> 6) - 2); // add noise to help convergence to 0 43 | end 44 | end 45 | 46 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/alu_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: alu_pack-p.vhd,v 1.3 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | use work.t48_pack.word_width_c; 15 | 16 | package t48_alu_pack is 17 | 18 | ----------------------------------------------------------------------------- 19 | -- The ALU operations 20 | ----------------------------------------------------------------------------- 21 | type alu_op_t is (ALU_AND, ALU_OR, ALU_XOR, 22 | ALU_CPL, ALU_CLR, 23 | ALU_RL, ALU_RR, 24 | ALU_SWAP, 25 | ALU_DEC, ALU_INC, 26 | ALU_ADD, 27 | ALU_CONCAT, 28 | ALU_NOP); 29 | 30 | ----------------------------------------------------------------------------- 31 | -- The dedicated ALU arithmetic types. 32 | ----------------------------------------------------------------------------- 33 | subtype alu_operand_t is std_logic_vector(word_width_c downto 0); 34 | 35 | end t48_alu_pack; 36 | 37 | 38 | ------------------------------------------------------------------------------- 39 | -- File History: 40 | -- 41 | -- $Log: alu_pack-p.vhd,v $ 42 | -- Revision 1.3 2005/06/11 10:08:43 arniml 43 | -- introduce prefix 't48_' for all packages, entities and configurations 44 | -- 45 | -- Revision 1.2 2004/04/04 14:18:53 arniml 46 | -- add measures to implement XCHD 47 | -- 48 | -- Revision 1.1 2004/03/23 21:31:52 arniml 49 | -- initial check-in 50 | -- 51 | ------------------------------------------------------------------------------- 52 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/t48_core-c.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T48 Microcontroller Core 4 | -- 5 | -- $Id: t48_core-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 6 | -- 7 | ------------------------------------------------------------------------------- 8 | 9 | configuration t48_core_struct_c0 of t48_core is 10 | 11 | for struct 12 | 13 | for alu_b : t48_alu 14 | use configuration work.t48_alu_rtl_c0; 15 | end for; 16 | 17 | for bus_mux_b : t48_bus_mux 18 | use configuration work.t48_bus_mux_rtl_c0; 19 | end for; 20 | 21 | for clock_ctrl_b : t48_clock_ctrl 22 | use configuration work.t48_clock_ctrl_rtl_c0; 23 | end for; 24 | 25 | for cond_branch_b : t48_cond_branch 26 | use configuration work.t48_cond_branch_rtl_c0; 27 | end for; 28 | 29 | for use_db_bus 30 | for db_bus_b : t48_db_bus 31 | use configuration work.t48_db_bus_rtl_c0; 32 | end for; 33 | end for; 34 | 35 | for decoder_b : t48_decoder 36 | use configuration work.t48_decoder_rtl_c0; 37 | end for; 38 | 39 | for dmem_ctrl_b : t48_dmem_ctrl 40 | use configuration work.t48_dmem_ctrl_rtl_c0; 41 | end for; 42 | 43 | for use_timer 44 | for timer_b : t48_timer 45 | use configuration work.t48_timer_rtl_c0; 46 | end for; 47 | end for; 48 | 49 | for use_p1 50 | for p1_b : t48_p1 51 | use configuration work.t48_p1_rtl_c0; 52 | end for; 53 | end for; 54 | 55 | for use_p2 56 | for p2_b : t48_p2 57 | use configuration work.t48_p2_rtl_c0; 58 | end for; 59 | end for; 60 | 61 | for pmem_ctrl_b : t48_pmem_ctrl 62 | use configuration work.t48_pmem_ctrl_rtl_c0; 63 | end for; 64 | 65 | for psw_b : t48_psw 66 | use configuration work.t48_psw_rtl_c0; 67 | end for; 68 | 69 | end for; 70 | 71 | end t48_core_struct_c0; 72 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong_dma.v: -------------------------------------------------------------------------------- 1 | //============================================================================ 2 | // Sprite DMA. 3 | // 4 | // Author: gaz68 (https://github.com/gaz68) 5 | // October 2019 6 | // 7 | // Simplified sprite DMA. To Do: Implement full 8257 DMA controller. 8 | // Added HRQ/HLDA - slingshot 9 | //============================================================================ 10 | 11 | module dkong_dma 12 | ( 13 | input I_CLK, 14 | input I_CLK_EN, 15 | input I_RSTn, 16 | input I_DMA_TRIG, 17 | input [7:0]I_DMA_DS, 18 | input I_HLDA, 19 | 20 | output reg O_HRQ, 21 | output [9:0]O_DMA_AS, 22 | output [9:0]O_DMA_AD, 23 | output [7:0]O_DMA_DD, 24 | output O_DMA_CES, 25 | output O_DMA_CED 26 | ); 27 | 28 | parameter dma_cnt_end = 10'h17F; 29 | 30 | reg W_DMA_EN = 1'b0; 31 | reg [10:0]W_DMA_CNT; 32 | reg [7:0]W_DMA_DATA; 33 | reg [9:0]DMA_ASr; 34 | reg [9:0]DMA_ADr; 35 | reg [7:0]DMA_DDr; 36 | reg DMA_CESr, DMA_CEDr; 37 | 38 | always @(posedge I_CLK) 39 | if (I_CLK_EN) begin 40 | reg old_trig; 41 | 42 | old_trig <= I_DMA_TRIG; 43 | 44 | if(~old_trig & I_DMA_TRIG) 45 | begin 46 | DMA_ASr <= 10'h100; 47 | DMA_ADr <= 0; 48 | W_DMA_CNT <= 0; 49 | W_DMA_EN <= 1'b1; 50 | DMA_CESr <= 1'b1; 51 | DMA_CEDr <= 1'b1; 52 | O_HRQ <= 1'b1; 53 | end 54 | else if(W_DMA_EN) begin 55 | if (I_HLDA) begin 56 | case(W_DMA_CNT[1:0]) 57 | 1: DMA_DDr <= I_DMA_DS; 58 | 2: DMA_ASr <= DMA_ASr + 1'd1; 59 | 3: DMA_ADr <= DMA_ADr + 1'd1; 60 | default:; 61 | endcase 62 | W_DMA_CNT <= W_DMA_CNT + 1'd1; 63 | W_DMA_EN <= W_DMA_CNT==dma_cnt_end*4 ? 1'b0 : 1'b1; 64 | end 65 | end else 66 | begin 67 | O_HRQ <= 1'b0; 68 | DMA_CESr <= 1'b0; 69 | DMA_CEDr <= 1'b0; 70 | end 71 | end 72 | 73 | assign O_DMA_AS = DMA_ASr; 74 | assign O_DMA_AD = DMA_ADr; 75 | assign O_DMA_DD = DMA_DDr; 76 | assign O_DMA_CES = DMA_CESr; 77 | assign O_DMA_CED = DMA_CEDr; 78 | 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/T48.qip: -------------------------------------------------------------------------------- 1 | 2 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) timer.vhd ] 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_pack-p.vhd ] 4 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_core_comp_pack-p.vhd ] 5 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_core.vhd ] 6 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_comp_pack-p.vhd ] 7 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) syn_ram-e.vhd ] 8 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) psw.vhd ] 9 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pmem_ctrl_pack-p.vhd ] 10 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pmem_ctrl.vhd ] 11 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) p2.vhd ] 12 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) p1.vhd ] 13 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) opc_table.vhd ] 14 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) opc_decoder.vhd ] 15 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) int.vhd ] 16 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dmem_ctrl_pack-p.vhd ] 17 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dmem_ctrl.vhd ] 18 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) decoder_pack-p.vhd ] 19 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) decoder.vhd ] 20 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) db_bus.vhd ] 21 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cond_branch_pack-p.vhd ] 22 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cond_branch.vhd ] 23 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) clock_ctrl.vhd ] 24 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) bus_mux.vhd ] 25 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) alu_pack-p.vhd ] 26 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) alu.vhd ] 27 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dpram.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | 4 | LIBRARY altera_mf; 5 | USE altera_mf.altera_mf_components.all; 6 | 7 | entity dpram is 8 | generic ( 9 | addr_width_g : integer := 8; 10 | data_width_g : integer := 8 11 | ); 12 | PORT 13 | ( 14 | address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); 15 | address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); 16 | clock_a : IN STD_LOGIC := '1'; 17 | clock_b : IN STD_LOGIC ; 18 | data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); 19 | data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); 20 | enable_a : IN STD_LOGIC := '1'; 21 | enable_b : IN STD_LOGIC := '1'; 22 | wren_a : IN STD_LOGIC := '0'; 23 | wren_b : IN STD_LOGIC := '0'; 24 | q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); 25 | q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) 26 | ); 27 | END dpram; 28 | 29 | 30 | ARCHITECTURE SYN OF dpram IS 31 | BEGIN 32 | altsyncram_component : altsyncram 33 | GENERIC MAP ( 34 | address_reg_b => "CLOCK1", 35 | clock_enable_input_a => "NORMAL", 36 | clock_enable_input_b => "NORMAL", 37 | clock_enable_output_a => "BYPASS", 38 | clock_enable_output_b => "BYPASS", 39 | indata_reg_b => "CLOCK1", 40 | intended_device_family => "Cyclone V", 41 | lpm_type => "altsyncram", 42 | numwords_a => 2**addr_width_g, 43 | numwords_b => 2**addr_width_g, 44 | operation_mode => "BIDIR_DUAL_PORT", 45 | outdata_aclr_a => "NONE", 46 | outdata_aclr_b => "NONE", 47 | outdata_reg_a => "UNREGISTERED", 48 | outdata_reg_b => "UNREGISTERED", 49 | power_up_uninitialized => "FALSE", 50 | read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", 51 | read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", 52 | widthad_a => addr_width_g, 53 | widthad_b => addr_width_g, 54 | width_a => data_width_g, 55 | width_b => data_width_g, 56 | width_byteena_a => 1, 57 | width_byteena_b => 1, 58 | wrcontrol_wraddress_reg_b => "CLOCK1" 59 | ) 60 | PORT MAP ( 61 | address_a => address_a, 62 | address_b => address_b, 63 | clock0 => clock_a, 64 | clock1 => clock_b, 65 | clocken0 => enable_a, 66 | clocken1 => enable_b, 67 | data_a => data_a, 68 | data_b => data_b, 69 | wren_a => wren_a, 70 | wren_b => wren_b, 71 | q_a => q_a, 72 | q_b => q_b 73 | ); 74 | 75 | END SYN; 76 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase/mf_pllbase_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module mf_pllbase_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'outclk1' 14 | output wire outclk_1, 15 | 16 | // interface 'outclk2' 17 | output wire outclk_2, 18 | 19 | // interface 'locked' 20 | output wire locked 21 | ); 22 | 23 | altera_pll #( 24 | .fractional_vco_multiplier("false"), 25 | .reference_clock_frequency("74.25 MHz"), 26 | .operation_mode("direct"), 27 | .number_of_clocks(3), 28 | .output_clock_frequency0("6.143617 MHz"), 29 | .phase_shift0("0 ps"), 30 | .duty_cycle0(50), 31 | .output_clock_frequency1("6.143617 MHz"), 32 | .phase_shift1("40693 ps"), 33 | .duty_cycle1(50), 34 | .output_clock_frequency2("24.574218 MHz"), 35 | .phase_shift2("0 ps"), 36 | .duty_cycle2(50), 37 | .output_clock_frequency3("0 MHz"), 38 | .phase_shift3("0 ps"), 39 | .duty_cycle3(50), 40 | .output_clock_frequency4("0 MHz"), 41 | .phase_shift4("0 ps"), 42 | .duty_cycle4(50), 43 | .output_clock_frequency5("0 MHz"), 44 | .phase_shift5("0 ps"), 45 | .duty_cycle5(50), 46 | .output_clock_frequency6("0 MHz"), 47 | .phase_shift6("0 ps"), 48 | .duty_cycle6(50), 49 | .output_clock_frequency7("0 MHz"), 50 | .phase_shift7("0 ps"), 51 | .duty_cycle7(50), 52 | .output_clock_frequency8("0 MHz"), 53 | .phase_shift8("0 ps"), 54 | .duty_cycle8(50), 55 | .output_clock_frequency9("0 MHz"), 56 | .phase_shift9("0 ps"), 57 | .duty_cycle9(50), 58 | .output_clock_frequency10("0 MHz"), 59 | .phase_shift10("0 ps"), 60 | .duty_cycle10(50), 61 | .output_clock_frequency11("0 MHz"), 62 | .phase_shift11("0 ps"), 63 | .duty_cycle11(50), 64 | .output_clock_frequency12("0 MHz"), 65 | .phase_shift12("0 ps"), 66 | .duty_cycle12(50), 67 | .output_clock_frequency13("0 MHz"), 68 | .phase_shift13("0 ps"), 69 | .duty_cycle13(50), 70 | .output_clock_frequency14("0 MHz"), 71 | .phase_shift14("0 ps"), 72 | .duty_cycle14(50), 73 | .output_clock_frequency15("0 MHz"), 74 | .phase_shift15("0 ps"), 75 | .duty_cycle15(50), 76 | .output_clock_frequency16("0 MHz"), 77 | .phase_shift16("0 ps"), 78 | .duty_cycle16(50), 79 | .output_clock_frequency17("0 MHz"), 80 | .phase_shift17("0 ps"), 81 | .duty_cycle17(50), 82 | .pll_type("General"), 83 | .pll_subtype("General") 84 | ) altera_pll_i ( 85 | .rst (rst), 86 | .outclk ({outclk_2, outclk_1, outclk_0}), 87 | .locked (locked), 88 | .fboutclk ( ), 89 | .fbclk (1'b0), 90 | .refclk (refclk) 91 | ); 92 | endmodule 93 | 94 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/README: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- **** 3 | -- T80(c) core. Attempt to finish all undocumented features and provide 4 | -- accurate timings. 5 | -- 6 | -- Version 351. 7 | -- Merged Gameboy fixes from Bruno Duarte Gouveia (brNX) 8 | -- Passes Blargg's test ROMs 9 | -- 10 | -- Version 350. 11 | -- Copyright (c) 2018 Sorgelig 12 | -- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr 13 | -- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as 14 | -- correct implementation is still unclear. 15 | -- 16 | -- **** 17 | -- T80(b) core. In an effort to merge and maintain bug fixes .... 18 | -- 19 | -- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 20 | -- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle 21 | -- Ver 300 started tidyup. 22 | -- 23 | -- MikeJ March 2005 24 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) 25 | -- 26 | -- **** 27 | -- Z80 compatible microprocessor core 28 | -- 29 | -- Version : 0250 30 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 31 | -- All rights reserved 32 | -- 33 | -- Redistribution and use in source and synthezised forms, with or without 34 | -- modification, are permitted provided that the following conditions are met: 35 | -- 36 | -- Redistributions of source code must retain the above copyright notice, 37 | -- this list of conditions and the following disclaimer. 38 | -- 39 | -- Redistributions in synthesized form must reproduce the above copyright 40 | -- notice, this list of conditions and the following disclaimer in the 41 | -- documentation and/or other materials provided with the distribution. 42 | -- 43 | -- Neither the name of the author nor the names of other contributors may 44 | -- be used to endorse or promote products derived from this software without 45 | -- specific prior written permission. 46 | -- 47 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 48 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 49 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 50 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 51 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 52 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 53 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 54 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 55 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 56 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 57 | -- POSSIBILITY OF SUCH DAMAGE. 58 | -- 59 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/t48_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: t48_pack-p.vhd,v 1.1 2004/03/23 21:31:53 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | package t48_pack is 15 | 16 | ----------------------------------------------------------------------------- 17 | -- Global constants 18 | ----------------------------------------------------------------------------- 19 | 20 | -- clock active level 21 | constant clk_active_c : std_logic := '1'; 22 | -- reset active level 23 | constant res_active_c : std_logic := '0'; 24 | -- idle level on internal data bus 25 | constant bus_idle_level_c : std_logic := '1'; 26 | 27 | -- global data word width 28 | constant word_width_c : natural := 8; 29 | 30 | -- data memory address width 31 | constant dmem_addr_width_c : natural := 8; 32 | -- program memory address width 33 | constant pmem_addr_width_c : natural := 12; 34 | 35 | 36 | ----------------------------------------------------------------------------- 37 | -- Global data types 38 | ----------------------------------------------------------------------------- 39 | 40 | -- the global data word width type 41 | subtype word_t is std_logic_vector(word_width_c-1 downto 0); 42 | subtype nibble_t is std_logic_vector(word_width_c/2-1 downto 0); 43 | -- the global data memory address type 44 | subtype dmem_addr_t is std_logic_vector(dmem_addr_width_c-1 downto 0); 45 | -- the global program memory address type 46 | subtype pmem_addr_t is std_logic_vector(pmem_addr_width_c-1 downto 0); 47 | subtype page_t is std_logic_vector(pmem_addr_width_c-1 downto word_width_c); 48 | 49 | -- the machine states 50 | type mstate_t is (MSTATE1, MSTATE2, MSTATE3, MSTATE4, MSTATE5); 51 | 52 | 53 | ----------------------------------------------------------------------------- 54 | -- Global functions 55 | ----------------------------------------------------------------------------- 56 | 57 | function to_stdLogic(input: boolean) return std_logic; 58 | function to_boolean(input: std_logic) return boolean; 59 | 60 | end t48_pack; 61 | 62 | package body t48_pack is 63 | 64 | function to_stdLogic(input: boolean) return std_logic is 65 | begin 66 | if input then 67 | return '1'; 68 | else 69 | return '0'; 70 | end if; 71 | end to_stdLogic; 72 | 73 | function to_boolean(input: std_logic) return boolean is 74 | begin 75 | if input = '1' then 76 | return true; 77 | else 78 | return false; 79 | end if; 80 | end to_boolean; 81 | 82 | end t48_pack; 83 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/i8035ip.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG T8035 I/F 3 | // 4 | // Version : 1.01 5 | // 6 | // Copyright(c) 2004 Katsumi Degawa , All rights reserved 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | // 2004- 9- 2 T48-IP(beta3) was include. K.Degawa 15 | // 2004- 9- 2 T48 Bug Fix K.Degawa 16 | // 2004- 9-14 T48-IP was changed to beta4. K.Degawa 17 | // 2005- 2- 9 It cleaned. 18 | //================================================================================ 19 | 20 | 21 | module I8035IP( 22 | 23 | I_CLK, 24 | I_CLK_EN, 25 | I_RSTn, 26 | I_INTn, 27 | I_EA, 28 | O_PSENn, 29 | O_RDn, 30 | O_WRn, 31 | O_ALE, 32 | O_PROGn, 33 | I_T0, 34 | O_T0, 35 | I_T1, 36 | I_DB, 37 | O_DB, 38 | I_P1, 39 | O_P1, 40 | I_P2, 41 | O_P2 42 | 43 | ); 44 | 45 | input I_CLK; 46 | input I_CLK_EN; 47 | input I_RSTn; 48 | input I_INTn; 49 | input I_EA; 50 | output O_PSENn; 51 | output O_RDn; 52 | output O_WRn; 53 | output O_ALE; 54 | output O_PROGn; 55 | input I_T0; 56 | output O_T0; 57 | input I_T1; 58 | input [7:0]I_DB; 59 | output [7:0]O_DB; 60 | input [7:0]I_P1; 61 | output [7:0]O_P1; 62 | input [7:0]I_P2; 63 | output [7:0]O_P2; 64 | 65 | wire W_PSENn; 66 | assign O_PSENn = W_PSENn ; 67 | 68 | // 64 Byte RAM ------------------------------------------ 69 | wire [7:0]t48_ram_a; 70 | wire t48_ram_we; 71 | wire [7:0]t48_ram_do; 72 | wire [7:0]t48_ram_di; 73 | 74 | ram_64_8 t48_ram( 75 | 76 | .I_CLK(I_CLK), 77 | .I_ADDR(t48_ram_a[5:0]), 78 | .I_D(t48_ram_di), 79 | .I_CE(1'b1), 80 | .I_WE(t48_ram_we), 81 | .O_D(t48_ram_do) 82 | 83 | ); 84 | 85 | //---------------------------------------------------------- 86 | 87 | wire xtal3_s; 88 | 89 | t48_core t48_core( 90 | 91 | .xtal_i(I_CLK), 92 | .xtal_en_i(I_CLK_EN), 93 | .reset_i(I_RSTn), 94 | .t0_i(I_T0), 95 | .t0_o(O_T0), 96 | .t0_dir_o(), 97 | .int_n_i(I_INTn), 98 | .ea_i(I_EA), 99 | .rd_n_o(O_RDn), 100 | .psen_n_o(W_PSENn), 101 | .wr_n_o(O_WRn), 102 | .ale_o(O_ALE), 103 | .db_i(I_DB), 104 | .db_o(O_DB), 105 | .db_dir_o(), 106 | .t1_i(I_T1), 107 | .p2_i(I_P2), 108 | .p2_o(O_P2), 109 | .p2_low_imp_o(), 110 | .p1_i(I_P1), 111 | .p1_o(O_P1), 112 | .p1_low_imp_o(), 113 | .prog_n_o(O_PROGn), 114 | .clk_i(I_CLK), 115 | .en_clk_i(xtal3_s), 116 | .xtal3_o(xtal3_s), 117 | .dmem_addr_o(t48_ram_a), 118 | .dmem_we_o(t48_ram_we), 119 | .dmem_data_i(t48_ram_do), 120 | .dmem_data_o(t48_ram_di), 121 | .pmem_addr_o(), 122 | .pmem_data_i(8'h00) 123 | 124 | ); 125 | 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong_col_pal.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG COLOR_PALETE(XILINX EDITION) 3 | // 4 | // Version : 3.00 5 | // 6 | // Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | // 2005- 2- 9 The description of the ROM was changed. 15 | // Data on the ROM are initialized at the time of the start. 16 | //================================================================================ 17 | module dkong_col_pal( 18 | input CLK_24M, 19 | input CLK_6M_EN, 20 | input I_DK3B, 21 | input I_PESTPLCE, 22 | input I_PALBNK, 23 | input [5:0]I_VRAM_D, 24 | input [5:0]I_OBJ_D, 25 | input I_CMPBLKn, 26 | input I_5H_Q6, 27 | input I_5H_Q7, 28 | output [3:0]O_R, 29 | output [3:0]O_G, 30 | output [3:0]O_B, 31 | 32 | input [15:0] DL_ADDR, 33 | input DL_WR, 34 | input [7:0] DL_DATA 35 | ); 36 | 37 | 38 | //------- PARTS 3ML ------------------------------------ 39 | wire [5:0]W_3ML_Y = (~(I_OBJ_D[0]|I_OBJ_D[1])) ? I_VRAM_D: I_OBJ_D; 40 | 41 | //------- PARTS 1EF ------------------------------------ 42 | wire [9:0]W_1EF_D = {I_5H_Q7,I_5H_Q6,W_3ML_Y[5:0],W_3ML_Y[0]|W_3ML_Y[1],I_CMPBLKn}; 43 | reg [9:0]W_1EF_Q; 44 | wire W_1EF_RST = I_CMPBLKn|W_1EF_Q[0]; 45 | 46 | always@(posedge CLK_24M or negedge W_1EF_RST) 47 | begin 48 | if(W_1EF_RST == 1'b0) W_1EF_Q <= 1'b0; 49 | else if(CLK_6M_EN) W_1EF_Q <= W_1EF_D; 50 | end 51 | 52 | //------- PARTS 2EF ------------------------------------ 53 | wire [7:0]W_2E_DO,W_2F_DO; 54 | /* 55 | col1 rom2j( 56 | .clk(CLK_24M), 57 | .addr(W_1EF_Q[9:2]), 58 | .data(W_2F_DO) 59 | ); 60 | */ 61 | dpram #(9,8) col1 ( 62 | .clock_a(CLK_24M), 63 | .address_a(W_1EF_Q[9:2]), 64 | .q_a(W_2F_DO), 65 | 66 | .clock_b(CLK_24M), 67 | .address_b(DL_ADDR[7:0]), 68 | .wren_b(DL_WR && DL_ADDR[15:9] == {4'hF, 3'b001}), 69 | .data_b(DL_DATA) 70 | ); 71 | /* 72 | col2 rom2k( 73 | .clk(CLK_24M), 74 | .addr(W_1EF_Q[9:2]), 75 | .data(W_2E_DO) 76 | ); 77 | */ 78 | dpram #(9,8) col2 ( 79 | .clock_a(CLK_24M), 80 | .address_a(W_1EF_Q[9:2]), 81 | .q_a(W_2E_DO), 82 | 83 | .clock_b(CLK_24M), 84 | .address_b(DL_ADDR[7:0]), 85 | .wren_b(DL_WR && DL_ADDR[15:9] == {4'hF, 3'b000}), 86 | .data_b(DL_DATA) 87 | ); 88 | 89 | //assign {O_R, O_G, O_B} = I_DK3B ? {W_2F_DO, W_2E_DO} : ~{W_2F_DO[3:1], W_2F_DO[3], ~W_2E_DO}; 90 | assign O_R = I_DK3B ? W_2F_DO[7:4] : {4{I_PESTPLCE}} ^ ~{W_2F_DO[3:1], W_2F_DO[3]}; 91 | assign O_G = I_DK3B ? W_2F_DO[3:0] : {4{I_PESTPLCE}} ^ ~{W_2F_DO[0], W_2E_DO[3:2], W_2F_DO[0]}; 92 | assign O_B = I_DK3B ? W_2E_DO[3:0] : {4{I_PESTPLCE}} ^ ~{W_2E_DO[1:0], W_2E_DO[1:0]}; 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t48_rom-e.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x48 ROM 4 | -- 5 | -- $Id: t48_rom-e.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | library ieee; 47 | use ieee.std_logic_1164.all; 48 | 49 | entity t48_rom is 50 | 51 | port ( 52 | clk_i : in std_logic; 53 | rom_addr_i : in std_logic_vector(9 downto 0); 54 | rom_data_o : out std_logic_vector(7 downto 0) 55 | ); 56 | 57 | end t48_rom; 58 | 59 | 60 | ------------------------------------------------------------------------------- 61 | -- File History: 62 | -- 63 | -- $Log: t48_rom-e.vhd,v $ 64 | -- Revision 1.1.1.1 2006/11/25 22:15:41 arnim 65 | -- copied from opencores.org repository release 1.0 66 | -- 67 | -- Revision 1.1 2006/06/21 00:59:15 arniml 68 | -- initial check-in 69 | -- 70 | ------------------------------------------------------------------------------- 71 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t49_rom-e.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x49 ROM 4 | -- 5 | -- $Id: t49_rom-e.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | library ieee; 47 | use ieee.std_logic_1164.all; 48 | 49 | entity t49_rom is 50 | 51 | port ( 52 | clk_i : in std_logic; 53 | rom_addr_i : in std_logic_vector(10 downto 0); 54 | rom_data_o : out std_logic_vector( 7 downto 0) 55 | ); 56 | 57 | end t49_rom; 58 | 59 | 60 | ------------------------------------------------------------------------------- 61 | -- File History: 62 | -- 63 | -- $Log: t49_rom-e.vhd,v $ 64 | -- Revision 1.1.1.1 2006/11/25 22:15:41 arnim 65 | -- copied from opencores.org repository release 1.0 66 | -- 67 | -- Revision 1.1 2006/06/21 00:59:15 arniml 68 | -- initial check-in 69 | -- 70 | ------------------------------------------------------------------------------- 71 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/syn_ram-e.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- A synchronous parametrizable RAM. 4 | -- 5 | -- $Id: syn_ram-e.vhd,v 1.1 2004/03/24 21:32:27 arniml Exp $ 6 | -- 7 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | library ieee; 47 | use ieee.std_logic_1164.all; 48 | 49 | entity syn_ram is 50 | 51 | generic ( 52 | address_width_g : positive := 8 53 | ); 54 | port ( 55 | clk_i : in std_logic; 56 | res_i : in std_logic; 57 | ram_addr_i : in std_logic_vector(address_width_g-1 downto 0); 58 | ram_data_i : in std_logic_vector(7 downto 0); 59 | ram_we_i : in std_logic; 60 | ram_data_o : out std_logic_vector(7 downto 0) 61 | ); 62 | 63 | end syn_ram; 64 | 65 | 66 | ------------------------------------------------------------------------------- 67 | -- File History: 68 | -- 69 | -- $Log: syn_ram-e.vhd,v $ 70 | -- Revision 1.1 2004/03/24 21:32:27 arniml 71 | -- initial check-in 72 | -- 73 | ------------------------------------------------------------------------------- 74 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong_logic.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG used LOGIC IP 3 | // 4 | // Version : 1.00 5 | // 6 | // Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | //================================================================================ 15 | 16 | //================================================ 17 | // 74xx109 18 | // JK FLIP-FLOPS with PRESET & RST 19 | // PRESET NO USE 20 | //================================================ 21 | 22 | module logic_74xx109( 23 | 24 | CLK, 25 | RST, 26 | I_J, 27 | I_K, 28 | O_Q 29 | 30 | ); 31 | 32 | input CLK,RST; 33 | input I_J,I_K; 34 | output O_Q; 35 | 36 | reg Q; 37 | 38 | assign O_Q = Q; 39 | 40 | always@(posedge CLK or negedge RST) 41 | begin 42 | if(RST == 1'b0) Q <= 1'b0; 43 | else begin 44 | case({I_J,I_K}) 45 | 2'b00: Q <= 1'b0; 46 | 2'b01: Q <= Q; 47 | 2'b10: Q <= ~Q; 48 | 2'b11: Q <= 1'b1; 49 | endcase 50 | end 51 | end 52 | 53 | endmodule 54 | 55 | //================================================ 56 | // 74xx138 57 | // 3-to-8 line decoder 58 | //================================================ 59 | 60 | module logic_74xx138( 61 | 62 | I_G1, 63 | I_G2a, 64 | I_G2b, 65 | I_Sel, 66 | O_Q 67 | 68 | ); 69 | 70 | input I_G1,I_G2a,I_G2b; 71 | input [2:0]I_Sel; 72 | output [7:0]O_Q; 73 | 74 | reg [7:0]O_Q; 75 | wire [2:0]I_G = {I_G1,I_G2a,I_G2b}; 76 | always@(I_G or I_Sel or O_Q) 77 | begin 78 | if(I_G == 3'b100 )begin 79 | case(I_Sel) 80 | 3'b000: O_Q = 8'b11111110; 81 | 3'b001: O_Q = 8'b11111101; 82 | 3'b010: O_Q = 8'b11111011; 83 | 3'b011: O_Q = 8'b11110111; 84 | 3'b100: O_Q = 8'b11101111; 85 | 3'b101: O_Q = 8'b11011111; 86 | 3'b110: O_Q = 8'b10111111; 87 | 3'b111: O_Q = 8'b01111111; 88 | endcase 89 | end 90 | else begin 91 | O_Q = 8'b11111111; 92 | end 93 | end 94 | endmodule 95 | 96 | //================================================ 97 | // 74xx139 98 | // 2-to-4 line decoder 99 | //================================================ 100 | 101 | module logic_74xx139( 102 | 103 | I_G, 104 | I_Sel, 105 | O_Q 106 | 107 | ); 108 | 109 | input I_G; 110 | input [1:0]I_Sel; 111 | output [3:0]O_Q; 112 | 113 | reg [3:0]O_Q; 114 | always@(I_G or I_Sel or O_Q) 115 | begin 116 | if(I_G == 1'b0 )begin 117 | case(I_Sel) 118 | 2'b00: O_Q = 4'b1110; 119 | 2'b01: O_Q = 4'b1101; 120 | 2'b10: O_Q = 4'b1011; 121 | 2'b11: O_Q = 4'b0111; 122 | endcase 123 | end 124 | else begin 125 | O_Q = 4'b1111; 126 | end 127 | end 128 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/invertor_square_wave_oscilator.sv: -------------------------------------------------------------------------------- 1 | /*********************************************************************************\ 2 | * 3 | * MiSTer Discrete invertor square wave oscilator 4 | * 5 | * Copyright 2022 by Jegor van Opdorp. 6 | * This program is free software under the terms of the GPLv3, see LICENCSE.txt 7 | * 8 | * 9 | * Simplified model of the below circuit. 10 | * This model does not take the transfer functions of the invertors 11 | * into account: 12 | * 13 | * f = 1 / 2.2 R1C1 14 | * This equation was found on: 15 | * https://www.gadgetronicx.com/square-wave-generator-logic-gates/ 16 | * 17 | * The equation didn't coincide with the circuit simulated version. 18 | * It looks like the above formula is to obtain the SWITCHING feequency. 19 | * The actualy frequency is twice lower. 20 | * 21 | * 22 | * |\ |\ 23 | * | \ | \ 24 | * +--| >o--+--|-->o--+-------> out 25 | * | | / | | / | 26 | * | |/ | |/ | 27 | * Z Z | 28 | * Z Z R1 --- C 29 | * Z Z --- 30 | * | | | 31 | * '---------+---------' 32 | * 33 | * Drawing based on a drawing from MAME discrete 34 | * 35 | *********************************************************************************/ 36 | module invertor_square_wave_oscilator#( 37 | parameter longint CLOCK_RATE = 50000000, 38 | parameter SAMPLE_RATE = 48000, 39 | parameter R1 = 4300, 40 | parameter C_MICROFARADS_16_SHIFTED = 655360 // 10 microfarad 41 | ) ( 42 | input clk, 43 | input I_RSTn, 44 | input audio_clk_en, 45 | output signed[15:0] out 46 | ); 47 | localparam longint R1_K_OHM_16_SHIFTED = R1 * 16777 >> 8; // 1/1000 <<< 24 = 16777 48 | localparam CONSTANT_RATIO_16_SHIFTED = 14895; // 1/2.2/2 * 2 ^ 16 49 | localparam longint FREQUENCY_16_SHIFTED = CONSTANT_RATIO_16_SHIFTED * (R1_K_OHM_16_SHIFTED * C_MICROFARADS_16_SHIFTED) >> 32; 50 | localparam longint WAVE_LENGTH = (CLOCK_RATE <<< 16) / FREQUENCY_16_SHIFTED; 51 | localparam HALF_WAVE_LENGTH = WAVE_LENGTH >> 1; 52 | 53 | reg [63:0] wave_length_counter = 0; 54 | 55 | reg signed[15:0] unfiltered_out = 0; 56 | 57 | // filter to simulate transfer rate of invertors 58 | rate_of_change_limiter #( 59 | .SAMPLE_RATE(SAMPLE_RATE) 60 | ) slew_rate ( 61 | .clk(clk), 62 | .I_RSTn(I_RSTn), 63 | .audio_clk_en(audio_clk_en), 64 | .in(unfiltered_out), 65 | .out(out) 66 | ); 67 | 68 | always@(posedge clk, negedge I_RSTn) begin 69 | if(!I_RSTn)begin 70 | wave_length_counter <= 0; 71 | unfiltered_out <= 0; 72 | end else begin 73 | if(wave_length_counter < WAVE_LENGTH)begin 74 | wave_length_counter <= wave_length_counter + 1; 75 | end else begin 76 | wave_length_counter <= 0; 77 | end 78 | 79 | if (audio_clk_en) begin 80 | unfiltered_out <= wave_length_counter < HALF_WAVE_LENGTH ? 16384 : 0; 81 | end 82 | end 83 | end 84 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/sync_fifo.sv: -------------------------------------------------------------------------------- 1 | // MIT License 2 | 3 | // Copyright (c) 2022 Adam Gastineau 4 | 5 | // Permission is hereby granted, free of charge, to any person obtaining a copy 6 | // of this software and associated documentation files (the "Software"), to deal 7 | // in the Software without restriction, including without limitation the rights 8 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | // copies of the Software, and to permit persons to whom the Software is 10 | // furnished to do so, subject to the following conditions: 11 | 12 | // The above copyright notice and this permission notice shall be included in all 13 | // copies or substantial portions of the Software. 14 | 15 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | // SOFTWARE. 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | // An easily reusable method for synchronizing multiple bits across clock domains 26 | // Uses a shallow depth (4 entries) FIFO, so make sure to empty it quickly 27 | module sync_fifo #( 28 | parameter WIDTH = 2 29 | ) ( 30 | input wire clk_write, 31 | input wire clk_read, 32 | 33 | input wire write_en, 34 | input wire [WIDTH - 1:0] data_in, 35 | output reg [WIDTH - 1:0] data_out = 0 36 | ); 37 | 38 | reg read_req = 0; 39 | wire empty; 40 | 41 | wire [WIDTH - 1:0] fifo_out; 42 | 43 | dcfifo dcfifo_component ( 44 | .data(data_in), 45 | .rdclk(clk_read), 46 | .rdreq(read_req), 47 | .wrclk(clk_write), 48 | .wrreq(write_en), 49 | .q(fifo_out), 50 | .rdempty(empty), 51 | .aclr(), 52 | .eccstatus(), 53 | .rdfull(), 54 | .rdusedw(), 55 | .wrempty(), 56 | .wrfull(), 57 | .wrusedw() 58 | ); 59 | defparam dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 4, 60 | dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo", 61 | dcfifo_component.lpm_width = 32, dcfifo_component.lpm_widthu = 2, 62 | dcfifo_component.overflow_checking = "ON", dcfifo_component.rdsync_delaypipe = 5, 63 | dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON", 64 | dcfifo_component.wrsync_delaypipe = 5; 65 | 66 | reg [1:0] read_state = 0; 67 | 68 | localparam READ_DELAY = 1; 69 | localparam READ_WRITE = 2; 70 | 71 | always @(posedge clk_read) begin 72 | read_req <= 0; 73 | 74 | if (~empty) begin 75 | read_state <= READ_DELAY; 76 | read_req <= 1; 77 | end 78 | 79 | case (read_state) 80 | READ_DELAY: begin 81 | read_state <= READ_WRITE; 82 | end 83 | READ_WRITE: begin 84 | read_state <= 0; 85 | 86 | data_out <= fifo_out; 87 | end 88 | endcase 89 | end 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/decoder_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: decoder_pack-p.vhd,v 1.3 2005/06/11 10:08:43 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | package t48_decoder_pack is 12 | 13 | ----------------------------------------------------------------------------- 14 | -- The Mnemonics. 15 | ----------------------------------------------------------------------------- 16 | type mnemonic_t is (MN_ADD, 17 | MN_ADD_A_DATA, 18 | MN_ANL, 19 | MN_ANL_A_DATA, 20 | MN_ANL_EXT, 21 | MN_CALL, 22 | MN_CLR_A, 23 | MN_CLR_C, 24 | MN_CLR_F, 25 | MN_CPL_A, 26 | MN_CPL_C, 27 | MN_CPL_F, 28 | MN_DA, 29 | MN_DEC, 30 | MN_DIS_EN_I, 31 | MN_DIS_EN_TCNTI, 32 | MN_DJNZ, 33 | MN_ENT0_CLK, 34 | MN_IN, 35 | MN_INC, 36 | MN_INS, 37 | MN_JBB, 38 | MN_JC, 39 | MN_JF, 40 | MN_JMP, 41 | MN_JMPP, 42 | MN_JNI, 43 | MN_JT, 44 | MN_JTF, 45 | MN_JZ, 46 | MN_MOV_A_DATA, 47 | MN_MOV_A_PSW, 48 | MN_MOV_A_RR, 49 | MN_MOV_PSW_A, 50 | MN_MOV_RR, 51 | MN_MOV_RR_DATA, 52 | MN_MOV_T, 53 | MN_MOVD_A_PP, 54 | MN_MOVP, 55 | MN_MOVX, 56 | MN_NOP, 57 | MN_ORL, 58 | MN_ORL_A_DATA, 59 | MN_ORL_EXT, 60 | MN_OUTD_PP_A, 61 | MN_OUTL_EXT, 62 | MN_RET, 63 | MN_RL, 64 | MN_RR, 65 | MN_SEL_MB, 66 | MN_SEL_RB, 67 | MN_STOP_TCNT, 68 | MN_STRT, 69 | MN_SWAP, 70 | MN_XCH, 71 | MN_XRL, 72 | MN_XRL_A_DATA); 73 | 74 | end t48_decoder_pack; 75 | 76 | 77 | ------------------------------------------------------------------------------- 78 | -- File History: 79 | -- 80 | -- $Log: decoder_pack-p.vhd,v $ 81 | -- Revision 1.3 2005/06/11 10:08:43 arniml 82 | -- introduce prefix 't48_' for all packages, entities and configurations 83 | -- 84 | -- Revision 1.2 2004/03/28 13:09:53 arniml 85 | -- merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A 86 | -- 87 | -- Revision 1.1 2004/03/23 21:31:52 arniml 88 | -- initial check-in 89 | -- 90 | ------------------------------------------------------------------------------- 91 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t48_rom-struct-a.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x48 ROM 4 | -- 5 | -- $Id: t48_rom-struct-a.vhd,v 1.1.1.3 2006/11/26 10:07:52 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | architecture struct of t48_rom is 47 | 48 | component rom_t48 49 | port( 50 | Clk : in std_logic; 51 | A : in std_logic_vector(9 downto 0); 52 | D : out std_logic_vector(7 downto 0) 53 | ); 54 | end component; 55 | 56 | begin 57 | 58 | rom_b : rom_t48 59 | port map ( 60 | Clk => clk_i, 61 | A => rom_addr_i, 62 | D => rom_data_o 63 | ); 64 | 65 | end struct; 66 | 67 | 68 | ------------------------------------------------------------------------------- 69 | -- File History: 70 | -- 71 | -- $Log: t48_rom-struct-a.vhd,v $ 72 | -- Revision 1.1.1.3 2006/11/26 10:07:52 arnim 73 | -- incremental import for release 1.0 74 | -- 75 | -- Revision 1.3 2006/11/26 12:53:28 arniml 76 | -- fix entity port names 77 | -- 78 | -- Revision 1.2 2006/11/26 11:58:28 arniml 79 | -- fix component name 80 | -- 81 | -- Revision 1.1 2006/06/21 00:59:15 arniml 82 | -- initial check-in 83 | -- 84 | ------------------------------------------------------------------------------- 85 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/t49_rom-struct-a.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- T8x49 ROM 4 | -- 5 | -- $Id: t49_rom-struct-a.vhd,v 1.1.1.3 2006/11/26 10:07:52 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | architecture struct of t49_rom is 47 | 48 | component rom_t49 49 | port( 50 | Clk : in std_logic; 51 | A : in std_logic_vector(10 downto 0); 52 | D : out std_logic_vector( 7 downto 0) 53 | ); 54 | end component; 55 | 56 | begin 57 | 58 | rom_b : rom_t49 59 | port map ( 60 | Clk => clk_i, 61 | A => rom_addr_i, 62 | D => rom_data_o 63 | ); 64 | 65 | end struct; 66 | 67 | 68 | ------------------------------------------------------------------------------- 69 | -- File History: 70 | -- 71 | -- $Log: t49_rom-struct-a.vhd,v $ 72 | -- Revision 1.1.1.3 2006/11/26 10:07:52 arnim 73 | -- incremental import for release 1.0 74 | -- 75 | -- Revision 1.3 2006/11/26 12:53:28 arniml 76 | -- fix entity port names 77 | -- 78 | -- Revision 1.2 2006/11/26 11:58:28 arniml 79 | -- fix component name 80 | -- 81 | -- Revision 1.1 2006/06/21 00:59:15 arniml 82 | -- initial check-in 83 | -- 84 | ------------------------------------------------------------------------------- 85 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong_sound.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG SOUND_I/F 3 | // 4 | // Version : 4.00 5 | // 6 | // Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | // 2004- 9- 2 T48-IP(beta3) was include. K.Degawa 15 | // 2004- 9-14 T48-IP was changed to beta4. K.Degawa 16 | // 2005- 2- 9 The description of the ROM was changed. 17 | // Data on the ROM are initialized at the time of the start. 18 | //================================================================================ 19 | 20 | module dkong_sound( 21 | input I_CLK, 22 | input I_RST, 23 | input I_DKJR, 24 | input [7:0]I8035_DBI, 25 | output [7:0]I8035_DBO, 26 | input [7:0]I8035_PAI, 27 | input [7:0]I8035_PBI, 28 | output [7:0]I8035_PBO, 29 | input I8035_ALE, 30 | input I8035_RDn, 31 | input I8035_PSENn, 32 | input [4:0]I_SOUND_DAT, 33 | input [5:0]I_SOUND_CNT, 34 | output I8035_INTn, 35 | output I8035_T0, 36 | output I8035_T1, 37 | output I8035_RSTn, 38 | output [7:0]O_SOUND_DAT, 39 | output [11:0] ROM_A, 40 | input [7:0] ROM_D 41 | ); 42 | 43 | assign I8035_PBO[6] = ~I_SOUND_CNT[5]; 44 | assign I8035_PBO[4] = ~I_SOUND_CNT[4]; 45 | assign I8035_T0 = ~I_SOUND_CNT[3]; 46 | assign I8035_T1 = ~I_SOUND_CNT[2]; 47 | assign I8035_PBO[5] = ~I_SOUND_CNT[1]; 48 | assign I8035_INTn = ~I_SOUND_CNT[0]; 49 | assign I8035_RSTn = I_RST; 50 | 51 | assign I8035_PBO[3:0] = 4'b0000; 52 | assign I8035_PBO[7] = 1'b0; 53 | //---- Parts 4FH ----------------------------- 54 | wire [10:0]S_ROM_A; 55 | reg [7:0]L_ROM_A; 56 | 57 | //always@(negedge I8035_ALE) L_ROM_A <= I8035_DBI ; 58 | reg I8035_ALE_D; 59 | always@(posedge I_CLK) begin 60 | I8035_ALE_D <= I8035_ALE; 61 | if (!I8035_ALE & I8035_ALE_D) L_ROM_A <= I8035_DBI; 62 | end 63 | assign S_ROM_A = {I8035_PBI[2:0],L_ROM_A[7:0]}; 64 | assign ROM_A = {I_DKJR ? I8035_PBI[3] : I8035_PSENn,S_ROM_A}; 65 | 66 | //---- Parts 4C ------------------------------ 67 | reg S_D1_CS; 68 | always@(posedge I_CLK) S_D1_CS <= (I_DKJR | I8035_PBI[6])&(~I8035_RDn); 69 | 70 | wire [7:0]S_D1 = S_D1_CS ? {3'h0,~I_SOUND_DAT[4:0]}: 8'h00 ; 71 | 72 | wire [7:0]S_PROG_DB; 73 | wire [7:0]S_PROG_D = I8035_PSENn ? 8'h00 : S_PROG_DB ; 74 | /* 75 | snd1 snd1 ( 76 | .clk(I_CLK), 77 | .addr(S_ROM_A), 78 | .data(S_PROG_DB) 79 | ); 80 | */ 81 | assign S_PROG_DB = ROM_D; 82 | 83 | //---- DATA ROM 3H --------------------------- 84 | wire S_D2_CS = (~I_DKJR & ~I8035_PBI[6])&(~I8035_RDn); 85 | 86 | wire [7:0]S_DB2; 87 | wire [7:0]S_D2 = S_D2_CS ? S_DB2 : 8'h00 ; 88 | /* 89 | snd2 snd2 ( 90 | .clk(I_CLK), 91 | .addr(S_ROM_A), 92 | .data(S_DB2) 93 | ); 94 | */ 95 | assign S_DB2 = ROM_D; 96 | 97 | //---- I8035_DB IO I/F ----------------------- 98 | wire [7:0]I8035_DO = S_PROG_D | S_D1 | S_D2 ; 99 | 100 | reg [7:0]DO; 101 | always@(posedge I_CLK) DO <= I8035_DO; 102 | assign I8035_DBO = DO; 103 | 104 | //---- DAC I/F ------------------------ 105 | assign O_SOUND_DAT = I8035_PAI; 106 | 107 | 108 | endmodule 109 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/t48_core_comp_pack-p.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- $Id: t48_core_comp_pack-p.vhd,v 1.5 2006/06/21 01:03:28 arniml Exp $ 4 | -- 5 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 6 | -- 7 | -- All rights reserved 8 | -- 9 | ------------------------------------------------------------------------------- 10 | 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | 14 | package t48_core_comp_pack is 15 | 16 | component t48_core 17 | generic ( 18 | xtal_div_3_g : integer := 1; 19 | register_mnemonic_g : integer := 1; 20 | include_port1_g : integer := 1; 21 | include_port2_g : integer := 1; 22 | include_bus_g : integer := 1; 23 | include_timer_g : integer := 1; 24 | sample_t1_state_g : integer := 4 25 | ); 26 | 27 | port ( 28 | xtal_i : in std_logic; 29 | xtal_en_i : in std_logic; 30 | reset_i : in std_logic; 31 | t0_i : in std_logic; 32 | t0_o : out std_logic; 33 | t0_dir_o : out std_logic; 34 | int_n_i : in std_logic; 35 | ea_i : in std_logic; 36 | rd_n_o : out std_logic; 37 | psen_n_o : out std_logic; 38 | wr_n_o : out std_logic; 39 | ale_o : out std_logic; 40 | db_i : in std_logic_vector( 7 downto 0); 41 | db_o : out std_logic_vector( 7 downto 0); 42 | db_dir_o : out std_logic; 43 | t1_i : in std_logic; 44 | p2_i : in std_logic_vector( 7 downto 0); 45 | p2_o : out std_logic_vector( 7 downto 0); 46 | p2l_low_imp_o : out std_logic; 47 | p2h_low_imp_o : out std_logic; 48 | p1_i : in std_logic_vector( 7 downto 0); 49 | p1_o : out std_logic_vector( 7 downto 0); 50 | p1_low_imp_o : out std_logic; 51 | prog_n_o : out std_logic; 52 | clk_i : in std_logic; 53 | en_clk_i : in std_logic; 54 | xtal3_o : out std_logic; 55 | dmem_addr_o : out std_logic_vector( 7 downto 0); 56 | dmem_we_o : out std_logic; 57 | dmem_data_i : in std_logic_vector( 7 downto 0); 58 | dmem_data_o : out std_logic_vector( 7 downto 0); 59 | pmem_addr_o : out std_logic_vector(11 downto 0); 60 | pmem_data_i : in std_logic_vector( 7 downto 0) 61 | ); 62 | end component; 63 | 64 | component generic_ram_ena 65 | generic ( 66 | addr_width_g : integer := 10; 67 | data_width_g : integer := 8 68 | ); 69 | port ( 70 | clk_i : in std_logic; 71 | a_i : in std_logic_vector(addr_width_g-1 downto 0); 72 | we_i : in std_logic; 73 | ena_i : in std_logic; 74 | d_i : in std_logic_vector(data_width_g-1 downto 0); 75 | d_o : out std_logic_vector(data_width_g-1 downto 0) 76 | ); 77 | end component; 78 | 79 | component t48_rom 80 | port ( 81 | clk_i : in std_logic; 82 | rom_addr_i : in std_logic_vector(9 downto 0); 83 | rom_data_o : out std_logic_vector(7 downto 0) 84 | ); 85 | end component; 86 | 87 | component t49_rom 88 | port ( 89 | clk_i : in std_logic; 90 | rom_addr_i : in std_logic_vector(10 downto 0); 91 | rom_data_o : out std_logic_vector( 7 downto 0) 92 | ); 93 | end component; 94 | 95 | end t48_core_comp_pack; 96 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong_soundboard.sv: -------------------------------------------------------------------------------- 1 | module dkong_soundboard( 2 | input W_CLK_24576M, 3 | input W_RESETn, 4 | input I_DKJR, 5 | input W_W0_WE, 6 | input W_W1_WE, 7 | input W_CNF_EN, 8 | input [6:0] W_6H_Q, 9 | input W_5H_Q0, 10 | input [1:0] W_4H_Q, 11 | input [4:0] W_3D_Q, 12 | output [15:0] O_SOUND_DAT, 13 | output O_SACK, 14 | output [11:0] ROM_A, 15 | input [7:0] ROM_D, 16 | output [18:0] WAV_ROM_A, 17 | input [7:0] WAV_ROM_DO 18 | ); 19 | 20 | wire [7:0]W_D_S_DAT; 21 | 22 | wire [7:0]I8035_DBI; 23 | wire [7:0]I8035_DBO; 24 | wire [7:0]I8035_PAI; 25 | wire [7:0]I8035_PBI; 26 | wire [7:0]I8035_PBO; 27 | wire I8035_ALE; 28 | wire I8035_RDn; 29 | wire I8035_PSENn; 30 | reg I8035_CLK_EN; 31 | wire I8035_INTn; 32 | wire I8035_T0; 33 | wire I8035_T1; 34 | wire I8035_RSTn; 35 | 36 | reg [1:0] cnt; 37 | always @(posedge W_CLK_24576M) begin 38 | cnt <= cnt + 1'd1; 39 | I8035_CLK_EN <= cnt == 0; 40 | end 41 | 42 | I8035IP SOUND_CPU 43 | ( 44 | .I_CLK(W_CLK_24576M), 45 | .I_CLK_EN(I8035_CLK_EN), 46 | .I_RSTn(I8035_RSTn), 47 | .I_INTn(I8035_INTn), 48 | .I_EA(1'b1), 49 | .O_PSENn(I8035_PSENn), 50 | .O_RDn(I8035_RDn), 51 | .O_WRn(), 52 | .O_ALE(I8035_ALE), 53 | .O_PROGn(), 54 | .I_T0(I8035_T0), 55 | .O_T0(), 56 | .I_T1(I8035_T1), 57 | .I_DB(I8035_DBO), 58 | .O_DB(I8035_DBI), 59 | .I_P1(8'h00), 60 | .O_P1(I8035_PAI), 61 | .I_P2(I8035_PBO), 62 | .O_P2(I8035_PBI) 63 | ); 64 | assign O_SACK = I8035_PBI[4]; 65 | //------------------------------------------------- 66 | 67 | dkong_sound Digtal_sound 68 | ( 69 | .I_CLK(W_CLK_24576M), 70 | .I_RST(W_RESETn), 71 | .I_DKJR(I_DKJR), 72 | .I8035_DBI(I8035_DBI), 73 | .I8035_DBO(I8035_DBO), 74 | .I8035_PAI(I8035_PAI), 75 | .I8035_PBI(I8035_PBI), 76 | .I8035_PBO(I8035_PBO), 77 | .I8035_ALE(I8035_ALE), 78 | .I8035_RDn(I8035_RDn), 79 | .I8035_PSENn(I8035_PSENn), 80 | .I8035_RSTn(I8035_RSTn), 81 | .I8035_INTn(I8035_INTn), 82 | .I8035_T0(I8035_T0), 83 | .I8035_T1(I8035_T1), 84 | .I_SOUND_DAT(I_DKJR ? ~W_3D_Q : {1'b1, W_3D_Q[3:0]}), 85 | .I_SOUND_CNT(I_DKJR ? {W_4H_Q[1],W_6H_Q[6:3],W_5H_Q0} : {2'b11,W_6H_Q[5:3],W_5H_Q0}), 86 | .O_SOUND_DAT(W_D_S_DAT), 87 | .ROM_A(ROM_A), 88 | .ROM_D(ROM_D) 89 | ); 90 | 91 | dkong_wav_sound Analog_sound 92 | ( 93 | .O_ROM_AB(WAV_ROM_A), 94 | .I_ROM_DB(WAV_ROM_DO), 95 | 96 | .I_CLK(W_CLK_24576M), 97 | .I_RSTn(W_RESETn), 98 | .I_SW(I_DKJR ? 2'b00 : W_6H_Q[2:1]) 99 | ); 100 | 101 | reg[8:0] audio_clk_counter; 102 | wire audio_clk_en; 103 | assign audio_clk_en = audio_clk_counter == 0; 104 | wire signed[15:0] walk_out; 105 | 106 | always@(posedge W_CLK_24576M, negedge W_RESETn) begin 107 | if(!W_RESETn)begin 108 | audio_clk_counter <= 0; 109 | end else begin 110 | audio_clk_counter <= audio_clk_counter + 1; 111 | end 112 | end 113 | 114 | dk_walk #(.CLOCK_RATE(24576000),.SAMPLE_RATE(48000)) walk ( 115 | .clk(W_CLK_24576M), 116 | .I_RSTn(W_RESETn), 117 | .audio_clk_en(audio_clk_en), 118 | .walk_en(~W_6H_Q[0]), 119 | .out(walk_out) 120 | ); 121 | 122 | // SOUND MIXER (WAV + DIG ) ----------------------- 123 | wire[14:0] sound_mix = ({1'b0, I_DKJR ? 15'd0 : WAV_ROM_DO, 6'b0} + {1'b0, (W_D_S_DAT >> 1) + (W_D_S_DAT >> 3), 6'b0}); 124 | wire signed[15:0] sound_mix_16_bit = sound_mix - 2**14 + walk_out; 125 | 126 | assign O_SOUND_DAT = sound_mix_16_bit + 2**15; 127 | 128 | endmodule 129 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/radarscp_stars.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG Radar Scope grid/star generator 3 | // 4 | // Version : 1.00 5 | // 6 | // Copyright(c) 2021 Gyorgy Szombathelyi 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | //================================================================================ 15 | //----------------------------------------------------------------------------------------- 16 | // H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],H_CNT[9] 17 | // 1/2 H 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H 18 | //----------------------------------------------------------------------------------------- 19 | 20 | module radarscp_stars( 21 | input CLK_24M, 22 | input CLK_EN, 23 | input RESETn, 24 | output O_RADARn, 25 | output O_STARn, 26 | output O_NOISE, 27 | output O_DISPLAY, 28 | input I_DISPLAY, 29 | input I_VBLKn, 30 | input [9:0] I_H_CNT, 31 | input I_FLIPn, 32 | input I_SOU2, 33 | 34 | input [15:0] DL_ADDR, 35 | input DL_WR, 36 | input [7:0] DL_DATA 37 | ); 38 | 39 | reg [7:0] RADAR_SHIFT; 40 | reg [19:0] CNT_30HZ; 41 | reg NOISE; 42 | reg [15:0] NOISE_LFSR; 43 | 44 | always @(posedge CLK_24M, negedge RESETn) begin 45 | if (!RESETn) begin 46 | RADAR_SHIFT <= 0; 47 | CNT_30HZ <= 0; 48 | end else begin 49 | CNT_30HZ <= CNT_30HZ + 1'd1; 50 | if (CNT_30HZ == 20'd799999) begin 51 | RADAR_SHIFT <= {RADAR_SHIFT[6:0], ~^RADAR_SHIFT[7:6]}; 52 | CNT_30HZ <= 0; 53 | 54 | NOISE_LFSR <= {NOISE_LFSR[14:0], (NOISE ^ NOISE_LFSR[4])}; 55 | NOISE <= ~NOISE_LFSR[15]; // originally generated on the sound board - used for stars dimming 56 | end 57 | end 58 | end 59 | wire W_RFLIP = (RADAR_SHIFT[5] & I_SOU2) ^ I_FLIPn; // does the radar flipping when destroyed 60 | 61 | assign O_DISPLAY = I_DISPLAY; // TODO: grid slow drawing effect 62 | 63 | reg [10:0] STARS_A; 64 | wire [7:0] STARS_DO; 65 | reg [3:0] W_1E_D; 66 | 67 | assign O_NOISE = NOISE; 68 | assign O_STARn = ~(W_1E_D[2] & W_1E_D[1] & W_1E_D[0]); 69 | assign O_RADARn = ~(~W_1E_D[2] & W_1E_D[1] & W_1E_D[0]); 70 | wire [3:0] W_1E_D_next = { 1'b1, STARS_DO[7], W_1E_D[0], {1'b0, STARS_DO[6:0]} == {I_H_CNT[2], I_H_CNT[9:3]} }; 71 | 72 | `ifdef SIM 73 | always @(posedge I_H_CNT[0]) begin 74 | W_1E_D <= W_1E_D_next; 75 | end 76 | 77 | wire W_1G_2E_CLK = ~&W_1E_D[1:0]; 78 | always @(posedge W_1G_2E_CLK, negedge I_VBLKn) begin 79 | if (!I_VBLKn) 80 | STARS_A <= {W_RFLIP, 10'd0}; 81 | else 82 | STARS_A <= STARS_A + 1'd1; 83 | end 84 | `else 85 | always @(posedge CLK_24M) begin 86 | if (CLK_EN & ~I_H_CNT[0]) 87 | W_1E_D <= W_1E_D_next; 88 | end 89 | 90 | always @(posedge CLK_24M, negedge I_VBLKn) begin 91 | if (!I_VBLKn) 92 | STARS_A <= 0; 93 | else if (CLK_EN) begin 94 | if (&W_1E_D[1:0] & ~&W_1E_D_next[1:0]) STARS_A <= {W_RFLIP, STARS_A[9:0] + 1'd1}; 95 | end 96 | end 97 | `endif 98 | 99 | dpram #(11,8) U_3E ( 100 | .clock_a(CLK_24M), 101 | .address_a(STARS_A), 102 | .q_a(STARS_DO), 103 | 104 | .clock_b(CLK_24M), 105 | .address_b(DL_ADDR[10:0]), 106 | .wren_b(DL_WR && DL_ADDR[15:11] == {4'hF, 1'b1}), 107 | .data_b(DL_DATA) 108 | ); 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/system/generic_ram_ena.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- Parametrizable, generic RAM with enable. 4 | -- 5 | -- $Id: generic_ram_ena.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ 6 | -- 7 | -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) 8 | -- 9 | -- All rights reserved 10 | -- 11 | -- Redistribution and use in source and synthezised forms, with or without 12 | -- modification, are permitted provided that the following conditions are met: 13 | -- 14 | -- Redistributions of source code must retain the above copyright notice, 15 | -- this list of conditions and the following disclaimer. 16 | -- 17 | -- Redistributions in synthesized form must reproduce the above copyright 18 | -- notice, this list of conditions and the following disclaimer in the 19 | -- documentation and/or other materials provided with the distribution. 20 | -- 21 | -- Neither the name of the author nor the names of other contributors may 22 | -- be used to endorse or promote products derived from this software without 23 | -- specific prior written permission. 24 | -- 25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 | -- POSSIBILITY OF SUCH DAMAGE. 36 | -- 37 | -- Please report bugs to the author, but before you do so, please 38 | -- make sure that this is not a derivative work and that 39 | -- you have the latest version of this file. 40 | -- 41 | -- The latest version of this file can be found at: 42 | -- http://www.opencores.org/cvsweb.shtml/t48/ 43 | -- 44 | ------------------------------------------------------------------------------- 45 | 46 | library ieee; 47 | use ieee.std_logic_1164.all; 48 | 49 | entity generic_ram_ena is 50 | 51 | generic ( 52 | addr_width_g : integer := 10; 53 | data_width_g : integer := 8 54 | ); 55 | port ( 56 | clk_i : in std_logic; 57 | a_i : in std_logic_vector(addr_width_g-1 downto 0); 58 | we_i : in std_logic; 59 | ena_i : in std_logic; 60 | d_i : in std_logic_vector(data_width_g-1 downto 0); 61 | d_o : out std_logic_vector(data_width_g-1 downto 0) 62 | ); 63 | 64 | end generic_ram_ena; 65 | 66 | 67 | library ieee; 68 | use ieee.numeric_std.all; 69 | 70 | architecture rtl of generic_ram_ena is 71 | 72 | type mem_t is array (natural range 0 to 2**addr_width_g-1) of 73 | std_logic_vector(d_i'range); 74 | signal mem_q : mem_t 75 | -- pragma translate_off 76 | := (others => (others => '0')) 77 | -- pragma translate_on 78 | ; 79 | signal a_q : std_logic_vector(a_i'range); 80 | 81 | begin 82 | 83 | mem: process (clk_i) 84 | begin 85 | 86 | if clk_i'event and clk_i = '1' then 87 | if ena_i = '1' then 88 | if we_i = '1' then 89 | mem_q(to_integer(unsigned(a_i))) <= d_i; 90 | end if; 91 | 92 | a_q <= a_i; 93 | end if; 94 | 95 | end if; 96 | end process mem; 97 | 98 | d_o <= mem_q(to_integer(unsigned(a_q))); 99 | 100 | end rtl; 101 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong_hv_count.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG H&V COUNTER 3 | // 4 | // Version : 2.00 5 | // 6 | // Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | // 2005- 2- 9 some changed. 15 | //================================================================================ 16 | //----------------------------------------------------------------------------------------- 17 | // H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],H_CNT[9] 18 | // 1/2 H 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H 19 | //----------------------------------------------------------------------------------------- 20 | // V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] 21 | // 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V 22 | //----------------------------------------------------------------------------------------- 23 | // VF_CNT[0],VF_CNT[1],VF_CNT[2],VF_CNT[3],VF_CNT[4],VF_CNT[5],VF_CNT[6],VF_CNT[7] 24 | // 1 VF 2 VF 4 VF 8 VF 16 VF 32 VF 64 VF 128 VF 25 | 26 | 27 | module dkong_hv_count( 28 | input I_CLK, 29 | input RST_n, 30 | input V_FLIP, 31 | input [8:0] H_OFFSET, 32 | input [8:0] V_OFFSET, 33 | 34 | output O_CLK, 35 | output O_CLK_EN, 36 | output [9:0]H_CNT, 37 | output [7:0]V_CNT, 38 | output [7:0]VF_CNT, 39 | output H_BLANKn, 40 | output V_BLANKn, 41 | output C_BLANKn, 42 | output H_SYNCn, 43 | output V_SYNCn 44 | ); 45 | 46 | 47 | 48 | // parameters tuned to work with flip-screen switch modification 49 | parameter H_count = 1536; 50 | parameter H_BL_P = 513; 51 | parameter H_BL_W = 0; 52 | parameter V_CL_P = 575; 53 | parameter V_CL_W = 639; 54 | parameter V_BL_P = 239; 55 | parameter V_BL_W = 15; 56 | 57 | reg [10:0]H_CNT_r = 0; 58 | always@(posedge I_CLK) 59 | begin 60 | H_CNT_r <= (H_CNT_r == H_count - 1'b1)? - 1'b0 : H_CNT_r + 1'b1 ; 61 | end 62 | 63 | assign H_CNT[9:0] = H_CNT_r[10:1]; 64 | assign O_CLK = H_CNT_r[0]; 65 | assign O_CLK_EN = !H_CNT_r[0]; 66 | 67 | reg V_CLK = 1'b0; 68 | wire V_CLK_EN = O_CLK & H_CNT[9:0] == V_CL_P; 69 | reg H_BLANK = 1'b0; 70 | 71 | always@(posedge I_CLK) begin 72 | case(H_CNT[9:0]) 73 | H_BL_P: H_BLANK <= 1; 74 | H_BL_W: H_BLANK <= 0; 75 | V_CL_W + H_OFFSET*2: V_CLK <= 0; 76 | V_CL_P + H_OFFSET*2: V_CLK <= 1; 77 | default:; 78 | endcase 79 | end 80 | 81 | assign H_SYNCn = ~V_CLK; 82 | assign H_BLANKn = ~H_BLANK; 83 | 84 | 85 | reg [8:0]V_CNT_r; 86 | always@(posedge I_CLK or negedge RST_n) 87 | begin 88 | if(RST_n == 1'b0) 89 | V_CNT_r <= 0 ; 90 | else if (V_CLK_EN) 91 | V_CNT_r <= (V_CNT_r == 255)? 9'd504 : V_CNT_r + 1'b1 ; 92 | end 93 | 94 | reg V_BLANK; 95 | always@(posedge I_CLK or negedge RST_n) 96 | begin 97 | if(RST_n == 1'b0)begin 98 | V_BLANK <= 0 ; 99 | end 100 | else if (V_CLK_EN) begin 101 | case(V_CNT_r[8:0]) 102 | V_BL_P: V_BLANK <= 1; 103 | V_BL_W: V_BLANK <= 0; 104 | default:; 105 | endcase 106 | end 107 | end 108 | 109 | assign V_CNT[7:0] = V_CNT_r[7:0]; 110 | assign V_SYNCn = (V_CNT_r > 255 - V_OFFSET) ^ (V_CNT_r < 9'd511 - V_OFFSET); 111 | assign V_BLANKn = ~V_BLANK; 112 | assign C_BLANKn = ~(H_BLANK | V_BLANK); 113 | assign VF_CNT[7:0]= V_CNT ^ {8{V_FLIP}}; 114 | 115 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong_wav_sound.v: -------------------------------------------------------------------------------- 1 | //=============================================================================== 2 | // FPGA DONKEY KONG WAVE SOUND 3 | // 4 | // Version : 4.00 5 | // 6 | // Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved 7 | // 8 | // Important ! 9 | // 10 | // This program is freeware for non-commercial use. 11 | // An author does no guarantee about this program. 12 | // You can use this under your own risk. 13 | // 14 | // 2004- 9 -7 Added Gorilla roar sound. K.degawa 15 | // 2005- 2 -9 removed Gorilla roar sound. K.degawa 16 | // It was optimized to become the smallest. 17 | //================================================================================ 18 | 19 | 20 | module dkong_wav_sound( 21 | 22 | O_ROM_AB, 23 | I_ROM_DB, 24 | 25 | I_CLK, 26 | I_RSTn, 27 | I_SW 28 | 29 | ); 30 | 31 | output [18:0]O_ROM_AB; 32 | input [7:0]I_ROM_DB; 33 | 34 | input I_CLK,I_RSTn; 35 | input [2:1]I_SW; 36 | 37 | parameter Sample_cnt = 2228; 38 | 39 | parameter Wlk1_adr = 16'h0000; // 10000 - 107FF 40 | parameter Wlk1_cnt = 16'h07d0; // 10000 - 107CF 41 | parameter Wlk2_adr = 16'h0800; // 10800 - 10FFF 42 | parameter Wlk2_cnt = 16'h07d0; // 10800 - 10FCF 43 | parameter Wlk3_adr = 16'h4800; // 14800 - 14FFF 44 | parameter Wlk3_cnt = 16'h07d0; // 14800 - 14FCF 45 | parameter Jump_adr = 16'h1000; // 11000 - 12FFF 46 | parameter Jump_cnt = 16'h1e20; // 11000 - 12E1F 47 | parameter Foot_adr = 16'h3000; // 13000 - 14FFF 48 | parameter Foot_cnt = 16'h1750; // 13000 - 1474F 49 | 50 | reg [11:0]sample; 51 | reg sample_pls; 52 | 53 | always@(posedge I_CLK or negedge I_RSTn) 54 | begin 55 | if(! I_RSTn)begin 56 | sample <= 0; 57 | sample_pls <= 0; 58 | end else begin 59 | sample <= (sample == Sample_cnt - 1'b1) ? 12'b0 : sample+1'b1; 60 | sample_pls <= (sample == Sample_cnt - 1'b1)? 1'b1 : 1'b0 ; 61 | end 62 | end 63 | 64 | //----------- WALK SOUND ------------------------------------------ 65 | reg [2:0]status0; 66 | reg [2:0]status1; 67 | reg [15:0]ad_cnt; 68 | reg [15:0]end_cnt; 69 | reg [1:0]steps_cnt; 70 | reg old_foot_rq; 71 | reg old_jump_rq; 72 | wire foot_rq = I_SW[2]; 73 | wire jump_rq = I_SW[1]; 74 | 75 | always@(posedge I_CLK or negedge I_RSTn) 76 | begin 77 | if(! I_RSTn)begin 78 | status0 <= 0; 79 | status1 <= 0; 80 | end_cnt <= Foot_cnt; 81 | ad_cnt <= 0; 82 | steps_cnt <= 2'b01; 83 | end else begin 84 | status0[0] = ~old_foot_rq & foot_rq; 85 | old_foot_rq = foot_rq; 86 | status0[2] <= ~old_jump_rq & jump_rq; 87 | old_jump_rq = jump_rq; 88 | if(status0 > status1)begin 89 | if(status0[2])begin 90 | status1 <= 3'b111; 91 | ad_cnt <= Jump_adr; 92 | end_cnt <= Jump_cnt; 93 | steps_cnt <= 2'b01; 94 | end else if(status0[1])begin 95 | status1 <= 3'b011; 96 | case (steps_cnt) 97 | 2'b01: begin 98 | ad_cnt <= Wlk1_adr; 99 | end_cnt <= Wlk1_cnt; 100 | steps_cnt <= 2'b10; 101 | end 102 | 2'b10: begin 103 | ad_cnt <= Wlk2_adr; 104 | end_cnt <= Wlk2_cnt; 105 | steps_cnt <= 2'b11; 106 | end 107 | 2'b11: begin 108 | ad_cnt <= Wlk3_adr; 109 | end_cnt <= Wlk3_cnt; 110 | steps_cnt <= 2'b01; 111 | end 112 | endcase 113 | end else begin 114 | status1 <= 3'b001; 115 | ad_cnt <= Foot_adr; 116 | end_cnt <= Foot_cnt; 117 | steps_cnt <= 2'b01; 118 | end 119 | end else begin 120 | if(sample_pls)begin 121 | if(!end_cnt)begin 122 | status1 <= 3'b000; 123 | end else begin 124 | end_cnt <= end_cnt-1; 125 | ad_cnt <= ad_cnt+1; 126 | end 127 | end 128 | end 129 | end 130 | end 131 | 132 | assign O_ROM_AB = {3'b001,ad_cnt}; 133 | 134 | 135 | endmodule 136 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/Z80.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | library work; 4 | use work.T80_Pack.all; 5 | 6 | entity Z80 is port 7 | ( 8 | clk : in std_logic; 9 | clk_en : in std_logic; 10 | reset : in std_logic; 11 | 12 | addr : out std_logic_vector(15 downto 0); 13 | datai : in std_logic_vector(7 downto 0); 14 | datao : out std_logic_vector(7 downto 0); 15 | 16 | m1 : out std_logic; 17 | mem_rd : out std_logic; 18 | mem_wr : out std_logic; 19 | io_rd : out std_logic; 20 | io_wr : out std_logic; 21 | 22 | wait_n : in std_logic := '1'; 23 | busrq_n : in std_logic := '1'; 24 | intreq : in std_logic := '0'; 25 | intvec : in std_logic_vector(7 downto 0); 26 | intack : out std_logic; 27 | nmi : in std_logic := '0' 28 | ); 29 | end Z80; 30 | 31 | architecture SYN of Z80 is 32 | 33 | component T80se is 34 | generic 35 | ( 36 | Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB 37 | T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 38 | ); 39 | port 40 | ( 41 | RESET_n : in std_logic; 42 | CLK_n : in std_logic; 43 | CLKEN : in std_logic; 44 | WAIT_n : in std_logic; 45 | INT_n : in std_logic; 46 | NMI_n : in std_logic; 47 | BUSRQ_n : in std_logic; 48 | M1_n : out std_logic; 49 | MREQ_n : out std_logic; 50 | IORQ_n : out std_logic; 51 | RD_n : out std_logic; 52 | WR_n : out std_logic; 53 | RFSH_n : out std_logic; 54 | HALT_n : out std_logic; 55 | BUSAK_n : out std_logic; 56 | A : out std_logic_vector(15 downto 0); 57 | DI : in std_logic_vector(7 downto 0); 58 | DO : out std_logic_vector(7 downto 0) 59 | ); 60 | end component T80se; 61 | 62 | -- Signal Declarations 63 | 64 | signal reset_n : std_logic; 65 | signal int_n : std_logic; 66 | signal nmi_n : std_logic; 67 | 68 | signal z80_m1 : std_logic; 69 | signal z80_memreq : std_logic; 70 | signal z80_ioreq : std_logic; 71 | signal z80_rd : std_logic; 72 | signal z80_wr : std_logic; 73 | signal z80_datai : std_logic_vector(7 downto 0); 74 | 75 | -- derived signals (outputs we need to read) 76 | signal z80_memrd : std_logic; 77 | signal z80_iord : std_logic; 78 | signal fetch : std_logic; 79 | 80 | begin 81 | 82 | -- simple inversions 83 | reset_n <= not reset; 84 | int_n <= not intreq; 85 | nmi_n <= not nmi; 86 | 87 | -- direct-connect (outputs we need to read) 88 | m1 <= z80_m1; 89 | mem_rd <= z80_memrd; 90 | io_rd <= z80_iord; 91 | 92 | -- memory signals 93 | z80_memrd <= z80_memreq nor z80_rd; 94 | mem_wr <= z80_memreq nor z80_wr; 95 | 96 | -- io signals 97 | z80_iord <= z80_ioreq nor z80_rd; 98 | io_wr <= z80_ioreq nor z80_wr; 99 | 100 | -- other signals 101 | fetch <= z80_m1 nor z80_memreq; 102 | intack <= z80_m1 nor z80_ioreq; 103 | 104 | -- data in mux 105 | z80_datai <= intvec when ((z80_memrd or z80_iord) = '0') else 106 | datai; 107 | 108 | Z80_uP : T80se 109 | generic map 110 | ( 111 | Mode => 0 -- Z80 112 | ) 113 | port map 114 | ( 115 | RESET_n => reset_n, 116 | CLK_n => clk, 117 | CLKEN => clk_en, 118 | WAIT_n => wait_n, 119 | INT_n => int_n, 120 | NMI_n => nmi_n, 121 | BUSRQ_n => busrq_n, 122 | M1_n => z80_m1, 123 | MREQ_n => z80_memreq, 124 | IORQ_n => z80_ioreq, 125 | RD_n => z80_rd, 126 | WR_n => z80_wr, 127 | RFSH_n => open, 128 | HALT_n => open, 129 | BUSAK_n => open, 130 | A => addr, 131 | DI => z80_datai, 132 | DO => datao 133 | ); 134 | 135 | end architecture SYN; 136 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/bus_mux.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The T48 Bus Connector. 4 | -- Multiplexes all drivers of the T48 bus. 5 | -- 6 | -- $Id: bus_mux.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t48/ 44 | -- 45 | ------------------------------------------------------------------------------- 46 | 47 | library ieee; 48 | use ieee.std_logic_1164.all; 49 | 50 | use work.t48_pack.word_t; 51 | 52 | entity t48_bus_mux is 53 | 54 | port ( 55 | alu_data_i : in word_t; 56 | bus_data_i : in word_t; 57 | dec_data_i : in word_t; 58 | dm_data_i : in word_t; 59 | pm_data_i : in word_t; 60 | p1_data_i : in word_t; 61 | p2_data_i : in word_t; 62 | psw_data_i : in word_t; 63 | tim_data_i : in word_t; 64 | data_o : out word_t 65 | ); 66 | 67 | end t48_bus_mux; 68 | 69 | 70 | use work.t48_pack.bus_idle_level_c; 71 | 72 | architecture rtl of t48_bus_mux is 73 | 74 | begin 75 | 76 | or_tree: if bus_idle_level_c = '0' generate 77 | data_o <= alu_data_i or 78 | bus_data_i or 79 | dec_data_i or 80 | dm_data_i or 81 | pm_data_i or 82 | p1_data_i or 83 | p2_data_i or 84 | psw_data_i or 85 | tim_data_i; 86 | end generate; 87 | 88 | and_tree: if bus_idle_level_c = '1' generate 89 | data_o <= alu_data_i and 90 | bus_data_i and 91 | dec_data_i and 92 | dm_data_i and 93 | pm_data_i and 94 | p1_data_i and 95 | p2_data_i and 96 | psw_data_i and 97 | tim_data_i; 98 | end generate; 99 | 100 | end rtl; 101 | 102 | 103 | ------------------------------------------------------------------------------- 104 | -- File History: 105 | -- 106 | -- $Log: bus_mux.vhd,v $ 107 | -- Revision 1.2 2005/06/11 10:08:43 arniml 108 | -- introduce prefix 't48_' for all packages, entities and configurations 109 | -- 110 | -- Revision 1.1 2004/03/23 21:31:52 arniml 111 | -- initial check-in 112 | -- 113 | ------------------------------------------------------------------------------- 114 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/pause.v: -------------------------------------------------------------------------------- 1 | //============================================================================ 2 | // Generic pause handling for MiSTer cores. 3 | // 4 | // https://github.com/JimmyStones/Pause_MiSTer 5 | // 6 | // Copyright (c) 2021 Jim Gregory 7 | // 8 | // This program is free software; you can redistribute it and/or modify it 9 | // under the terms of the GNU General Public License as published by the Free 10 | // Software Foundation; either version 3 of the License, or (at your option) 11 | // any later version. 12 | // 13 | // This program is distributed in the hope that it will be useful, but WITHOUT 14 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 | // more details. 17 | // 18 | // You should have received a copy of the GNU General Public License along 19 | // with this program; if not, write to the Free Software Foundation, Inc., 20 | // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 | //============================================================================ 22 | /* 23 | Features: 24 | - Pause can be triggered by user input, hiscore module or OSD opening (optionally controlled by setting in OSD) 25 | - When paused the RGB outputs will be halved after 10 seconds to reduce burn-in (optionally controlled by setting in OSD) 26 | - Reset signal will cancel user triggered pause 27 | 28 | Version history: 29 | 0001 - 2021-03-15 - First marked release 30 | 0002 - 2021-08-28 - Add optional output of dim_video signal (currently used by Galaga) 31 | ============================================================================ 32 | */ 33 | module pause #( 34 | parameter RW=8, // Width of red channel 35 | parameter GW=8, // Width of green channel 36 | parameter BW=8, // Width of blue channel 37 | parameter CLKSPD = 12 // Main clock speed in MHz 38 | ) 39 | ( 40 | input clk_sys, // Core system clock (should match HPS module) 41 | input reset, // CPU reset signal (active-high) 42 | input user_button, // User pause button signal (active-high) 43 | input pause_request, // Pause requested by other code (active-high) 44 | input [1:0] options, // Pause options from OSD 45 | // [0] = pause in OSD (active-high) 46 | // [1] = dim video (active-high) 47 | input OSD_STATUS, // OSD is open (active-high) 48 | input [(RW-1):0] r, // Red channel 49 | input [(GW-1):0] g, // Green channel 50 | input [(BW-1):0] b, // Blue channel 51 | 52 | output pause_cpu, // Pause signal to CPU (active-high) 53 | `ifdef PAUSE_OUTPUT_DIM 54 | output dim_video, // Dim video requested (active-high) 55 | `endif 56 | output [(RW+GW+BW-1):0] rgb_out // RGB output to arcade_video module 57 | 58 | ); 59 | 60 | // Option constants 61 | localparam pause_in_osd = 1'b0; 62 | localparam dim_video_timer= 1'b1; 63 | 64 | reg pause_toggle = 1'b0; // User paused (active-high) 65 | reg [31:0] pause_timer = 1'b0; // Time since pause 66 | reg [31:0] dim_timeout = (CLKSPD*10000000); // Time until video output dim (10 seconds @ CLKSPD Mhz) 67 | `ifndef PAUSE_OUTPUT_DIM 68 | wire dim_video; // Dim video requested (active-high) 69 | `endif 70 | 71 | assign pause_cpu = (pause_request | pause_toggle | (OSD_STATUS & options[pause_in_osd])) & !reset; 72 | assign dim_video = (pause_timer >= dim_timeout); 73 | 74 | always @(posedge clk_sys) begin 75 | 76 | // Track user pause button down 77 | reg user_button_last; 78 | user_button_last <= user_button; 79 | if(!user_button_last & user_button) pause_toggle <= ~pause_toggle; 80 | 81 | // Clear user pause on reset 82 | if(pause_toggle & reset) pause_toggle <= 0; 83 | 84 | if(pause_cpu & options[dim_video_timer]) 85 | begin 86 | // Track pause duration for video dim 87 | if((pause_timer> 1,g >> 1, b >> 1} : {r,g,b}; 99 | 100 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/pin_ddio_clk.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTDDIO_OUT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTDDIO_OUT 5 | 6 | // ============================================================ 7 | // File Name: pin_ddio_clk.v 8 | // Megafunction Name(s): 9 | // ALTDDIO_OUT 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.1 Build 646 04/11/2019 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2019 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module pin_ddio_clk ( 41 | datain_h, 42 | datain_l, 43 | outclock, 44 | dataout); 45 | 46 | input [0:0] datain_h; 47 | input [0:0] datain_l; 48 | input outclock; 49 | output [0:0] dataout; 50 | 51 | wire [0:0] sub_wire0; 52 | wire [0:0] dataout = sub_wire0[0:0]; 53 | 54 | altddio_out ALTDDIO_OUT_component ( 55 | .datain_h (datain_h), 56 | .datain_l (datain_l), 57 | .outclock (outclock), 58 | .dataout (sub_wire0), 59 | .aclr (1'b0), 60 | .aset (1'b0), 61 | .oe (1'b1), 62 | .oe_out (), 63 | .outclocken (1'b1), 64 | .sclr (1'b0), 65 | .sset (1'b0)); 66 | defparam 67 | ALTDDIO_OUT_component.extend_oe_disable = "OFF", 68 | ALTDDIO_OUT_component.intended_device_family = "Cyclone V", 69 | ALTDDIO_OUT_component.invert_output = "OFF", 70 | ALTDDIO_OUT_component.lpm_hint = "UNUSED", 71 | ALTDDIO_OUT_component.lpm_type = "altddio_out", 72 | ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", 73 | ALTDDIO_OUT_component.power_up_high = "OFF", 74 | ALTDDIO_OUT_component.width = 1; 75 | 76 | 77 | endmodule 78 | 79 | // ============================================================ 80 | // CNX file retrieval info 81 | // ============================================================ 82 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 83 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 84 | // Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" 85 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 86 | // Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" 87 | // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" 88 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" 89 | // Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" 90 | // Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" 91 | // Retrieval info: CONSTANT: WIDTH NUMERIC "1" 92 | // Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]" 93 | // Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0 94 | // Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]" 95 | // Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0 96 | // Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" 97 | // Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 98 | // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" 99 | // Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 100 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.v TRUE FALSE 101 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.qip TRUE FALSE 102 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.bsf FALSE TRUE 103 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk_inst.v TRUE TRUE 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk_bb.v FALSE TRUE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.inc FALSE TRUE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.cmp FALSE TRUE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.ppf TRUE FALSE 108 | // Retrieval info: LIB_FILE: altera_mf 109 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2022 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and any partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details, at 20 | https://fpgasoftware.intel.com/eula. 21 | */ 22 | (header "symbol" (version "1.1")) 23 | (symbol 24 | (rect 0 0 160 224) 25 | (text "mf_pllbase" (rect 48 -1 91 11)(font "Arial" (font_size 10))) 26 | (text "inst" (rect 8 208 20 220)(font "Arial" )) 27 | (port 28 | (pt 0 72) 29 | (input) 30 | (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) 31 | (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) 32 | (line (pt 0 72)(pt 48 72)(line_width 1)) 33 | ) 34 | (port 35 | (pt 0 112) 36 | (input) 37 | (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) 38 | (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) 39 | (line (pt 0 112)(pt 48 112)(line_width 1)) 40 | ) 41 | (port 42 | (pt 160 72) 43 | (output) 44 | (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) 45 | (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) 46 | (line (pt 160 72)(pt 112 72)(line_width 1)) 47 | ) 48 | (port 49 | (pt 160 112) 50 | (output) 51 | (text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8))) 52 | (text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8))) 53 | (line (pt 160 112)(pt 112 112)(line_width 1)) 54 | ) 55 | (port 56 | (pt 160 152) 57 | (output) 58 | (text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8))) 59 | (text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8))) 60 | (line (pt 160 152)(pt 112 152)(line_width 1)) 61 | ) 62 | (port 63 | (pt 160 192) 64 | (output) 65 | (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) 66 | (text "locked" (rect 127 181 163 192)(font "Arial" (font_size 8))) 67 | (line (pt 160 192)(pt 112 192)(line_width 1)) 68 | ) 69 | (drawing 70 | (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) 71 | (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) 72 | (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) 73 | (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) 74 | (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) 75 | (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) 76 | (text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9))) 77 | (text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0))) 78 | (text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9))) 79 | (text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0))) 80 | (text "locked" (rect 113 163 262 339)(font "Arial" (color 128 0 0)(font_size 9))) 81 | (text "export" (rect 82 187 200 384)(font "Arial" (color 0 0 0))) 82 | (text " altera_pll " (rect 118 208 308 426)(font "Arial" )) 83 | (line (pt 48 32)(pt 112 32)(line_width 1)) 84 | (line (pt 112 32)(pt 112 208)(line_width 1)) 85 | (line (pt 48 208)(pt 112 208)(line_width 1)) 86 | (line (pt 48 32)(pt 48 208)(line_width 1)) 87 | (line (pt 49 52)(pt 49 76)(line_width 1)) 88 | (line (pt 50 52)(pt 50 76)(line_width 1)) 89 | (line (pt 49 92)(pt 49 116)(line_width 1)) 90 | (line (pt 50 92)(pt 50 116)(line_width 1)) 91 | (line (pt 111 52)(pt 111 76)(line_width 1)) 92 | (line (pt 110 52)(pt 110 76)(line_width 1)) 93 | (line (pt 111 92)(pt 111 116)(line_width 1)) 94 | (line (pt 110 92)(pt 110 116)(line_width 1)) 95 | (line (pt 111 132)(pt 111 156)(line_width 1)) 96 | (line (pt 110 132)(pt 110 156)(line_width 1)) 97 | (line (pt 111 172)(pt 111 196)(line_width 1)) 98 | (line (pt 110 172)(pt 110 196)(line_width 1)) 99 | (line (pt 0 0)(pt 160 0)(line_width 1)) 100 | (line (pt 160 0)(pt 160 224)(line_width 1)) 101 | (line (pt 0 224)(pt 160 224)(line_width 1)) 102 | (line (pt 0 0)(pt 0 224)(line_width 1)) 103 | ) 104 | ) 105 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/Log2highacc.sv: -------------------------------------------------------------------------------- 1 | module Log2highacc 2 | 3 | /* 4 | A fast base-2 logarithm function, 24 bits (22 used) in, 12 bits out. 5 | Designed and coded by: Michael Dunn, http://www.cantares.on.ca/ 6 | (more info at the web site - see "Extras") 7 | Executes every cycle, with a latency of 3. 8 | 9 | Compared to previous versions, this one has a larger, higher resolution 10 | lookup table. This provides a smoother and more accurate output, though 11 | a downside of having higher LUT resolution than the LUT depth fully 12 | supports is that there are missing codes in the output. If this is a problem, 13 | the lower 2 or 3 output bits can be ignored. In most cases, use all the 14 | bits you can! 15 | 16 | Valid input range = 000100 - FFFFFF. In effect, there is a binary point: 17 | xxxx.yy. Logs of inputs below 1.00 are negative, and not handled by this design. 18 | 19 | License: Free to use & modify, but please keep this header intact. 20 | August 2, 2010, Kitchener, Ontario, Canada 21 | */ 22 | 23 | ( 24 | input [23:0] DIN_8_shifted, 25 | input clk, 26 | 27 | output [11:0] DOUT_8_shifted 28 | ); 29 | 30 | 31 | // Comprises 4 main blocks: priority encoder, barrel shifter, LUT, and adder. 32 | 33 | reg [3:0] priencout1; 34 | reg [3:0] priencout2; 35 | reg [3:0] priencout3; 36 | reg [5:0] barrelout; 37 | reg [20:0] barrelin; 38 | reg [7:0] LUTout; 39 | 40 | assign DOUT_8_shifted = {priencout3, LUTout}; // Basic top-level connectivity 41 | 42 | always @(posedge clk) 43 | begin 44 | priencout2 <= priencout1; 45 | priencout3 <= priencout2; 46 | barrelin <= DIN_8_shifted[22:2]; 47 | end 48 | 49 | 50 | wire [20:0] tmp1 = (barrelin << ~priencout1); // Barrel shifter - OMG, it's a primitive in Verilog! 51 | always @(posedge clk) 52 | begin 53 | barrelout <= tmp1[20:15]; 54 | end 55 | 56 | 57 | wire [15:0] priencin = DIN_8_shifted[23:8]; 58 | 59 | always @(posedge clk) // Priority encoder 60 | 61 | casex (priencin) 62 | 63 | 16'b1xxxxxxxxxxxxxxx: priencout1 <= 15; 64 | 16'b01xxxxxxxxxxxxxx: priencout1 <= 14; 65 | 16'b001xxxxxxxxxxxxx: priencout1 <= 13; 66 | 16'b0001xxxxxxxxxxxx: priencout1 <= 12; 67 | 16'b00001xxxxxxxxxxx: priencout1 <= 11; 68 | 16'b000001xxxxxxxxxx: priencout1 <= 10; 69 | 16'b0000001xxxxxxxxx: priencout1 <= 9; 70 | 16'b00000001xxxxxxxx: priencout1 <= 8; 71 | 16'b000000001xxxxxxx: priencout1 <= 7; 72 | 16'b0000000001xxxxxx: priencout1 <= 6; 73 | 16'b00000000001xxxxx: priencout1 <= 5; 74 | 16'b000000000001xxxx: priencout1 <= 4; 75 | 16'b0000000000001xxx: priencout1 <= 3; 76 | 16'b00000000000001xx: priencout1 <= 2; 77 | 16'b000000000000001x: priencout1 <= 1; 78 | 16'b000000000000000x: priencout1 <= 0; 79 | 80 | endcase 81 | 82 | 83 | 84 | /* 85 | LUT for log fraction lookup 86 | - can be done with array or case: 87 | 88 | case (addr) 89 | 0:out=0; 90 | . 91 | 31:out=15; 92 | endcase 93 | 94 | OR 95 | 96 | wire [3:0] lut [0:31]; 97 | assign lut[0] = 0; 98 | . 99 | assign lut[31] = 15; 100 | 101 | Are there any better ways? 102 | */ 103 | 104 | // Let's try "case". 105 | // The equation is: output = log2(1+input/64)*256 106 | // For larger tables, better to generate a separate data file using a program! 107 | 108 | always @(posedge clk) 109 | case (barrelout) 110 | 111 | 0: LUTout <= 0; 112 | 1: LUTout <= 6; 113 | 2: LUTout <= 11; 114 | 3: LUTout <= 17; 115 | 4: LUTout <= 22; 116 | 5: LUTout <= 28; 117 | 6: LUTout <= 33; 118 | 7: LUTout <= 38; 119 | 8: LUTout <= 44; 120 | 9: LUTout <= 49; 121 | 10: LUTout <= 54; 122 | 11: LUTout <= 59; 123 | 12: LUTout <= 63; 124 | 13: LUTout <= 68; 125 | 14: LUTout <= 73; 126 | 15: LUTout <= 78; 127 | 16: LUTout <= 82; 128 | 17: LUTout <= 87; 129 | 18: LUTout <= 92; 130 | 19: LUTout <= 96; 131 | 20: LUTout <= 100; 132 | 21: LUTout <= 105; 133 | 22: LUTout <= 109; 134 | 23: LUTout <= 113; 135 | 24: LUTout <= 118; 136 | 25: LUTout <= 122; 137 | 26: LUTout <= 126; 138 | 27: LUTout <= 130; 139 | 28: LUTout <= 134; 140 | 29: LUTout <= 138; 141 | 30: LUTout <= 142; 142 | 31: LUTout <= 146; 143 | 32: LUTout <= 150; 144 | 33: LUTout <= 154; 145 | 34: LUTout <= 157; 146 | 35: LUTout <= 161; 147 | 36: LUTout <= 165; 148 | 37: LUTout <= 169; 149 | 38: LUTout <= 172; 150 | 39: LUTout <= 176; 151 | 40: LUTout <= 179; 152 | 41: LUTout <= 183; 153 | 42: LUTout <= 186; 154 | 43: LUTout <= 190; 155 | 44: LUTout <= 193; 156 | 45: LUTout <= 197; 157 | 46: LUTout <= 200; 158 | 47: LUTout <= 203; 159 | 48: LUTout <= 207; 160 | 49: LUTout <= 210; 161 | 50: LUTout <= 213; 162 | 51: LUTout <= 216; 163 | 52: LUTout <= 220; 164 | 53: LUTout <= 223; 165 | 54: LUTout <= 226; 166 | 55: LUTout <= 229; 167 | 56: LUTout <= 232; 168 | 57: LUTout <= 235; 169 | 58: LUTout <= 238; 170 | 59: LUTout <= 241; 171 | 60: LUTout <= 244; 172 | 61: LUTout <= 247; 173 | 62: LUTout <= 250; 174 | 63: LUTout <= 253; 175 | 176 | endcase 177 | 178 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/astable_555_vco.sv: -------------------------------------------------------------------------------- 1 | /********************************************************************************\ 2 | * 3 | * MiSTer Discrete invertor square wave oscilator test bench 4 | * 5 | * Copyright 2022 by Jegor van Opdorp. 6 | * This program is free software under the terms of the GPLv3, see LICENCSE.txt 7 | * 8 | * Model taken from the equation on https://electronics.stackexchange.com/questions/101530/what-is-the-equation-for-the-555-timer-control-voltage 9 | * 10 | * th=C⋅(R1+R2)⋅ln(1+v_control/(2*(VCC−v_control))) 11 | * tl=C⋅R2⋅ln(2) 12 | * 13 | * v_pos 14 | * V 15 | * | 16 | * .-----+---+-----------------------------. 17 | * | | | 18 | * | | | 19 | * | | | 20 | * Z |8 | 21 | * R1 Z .---------. | 22 | * | 7| Vcc | | 23 | * +-----|Discharge| | 24 | * | | | | 25 | * Z | 555 |3 | 26 | * R2 Z | Out|---> Output Node | 27 | * | 6| | | 28 | * +-----|Threshold| | 29 | * | | | | 30 | * +-----|Trigger | | 31 | * | 2| |---< Control Voltage | 32 | * | | Reset |5 | 33 | * | '---------' | 34 | * --- 4| | 35 | * C --- +----------------------------' 36 | * | | 37 | * | ^ 38 | * gnd Reset 39 | * 40 | * Drawing based on a drawing from MAME discrete 41 | * 42 | ********************************************************************************/ 43 | module astable_555_vco#( 44 | parameter CLOCK_RATE = 50000000, 45 | parameter longint SAMPLE_RATE = 48000, 46 | parameter R1 = 47000, 47 | parameter R2 = 27000, 48 | parameter C_35_SHIFTED = 1134 // 33 nanofarad 49 | ) ( 50 | input clk, 51 | input I_RSTn, 52 | input audio_clk_en, 53 | input signed[15:0] v_control, 54 | output signed[15:0] out 55 | ); 56 | localparam VCC = 16384; 57 | localparam ln2_16_SHIFTED = 45426; 58 | localparam[63:0] C_R2_ln2_27_SHIFTED = C_35_SHIFTED * R2 * ln2_16_SHIFTED >> 24; 59 | localparam[63:0] C_R1_R2_35_SHIFTED = C_35_SHIFTED * (R1 + R2); 60 | localparam[31:0] CYCLES_LOW = C_R2_ln2_27_SHIFTED * CLOCK_RATE >> 27; 61 | localparam[31:0] CLOCK_RATE_C_R1_R2 = C_R1_R2_35_SHIFTED * CLOCK_RATE >> 35; 62 | 63 | wire signed[15:0] v_control_safe; 64 | 65 | reg[15:0] v_control_divided_two_vcc_minus_vcontrol = 3000; 66 | reg[15:0] two_vcc_minus_vcontrol = 3000; 67 | 68 | wire [11:0] ln_vc_vcc_vc_8_shifted; 69 | reg[23:0] to_log_8_shifted = 1000; 70 | 71 | natural_log natlog( 72 | .in_8_shifted(to_log_8_shifted), 73 | .I_RSTn(I_RSTn), 74 | .clk(clk), 75 | .out_8_shifted(ln_vc_vcc_vc_8_shifted) 76 | ); 77 | 78 | reg[32:0] WAVE_LENGTH; 79 | reg[31:0] CYCLES_HIGH = 1000; 80 | 81 | assign v_control_safe = v_control < 32767 ? v_control : 32766; 82 | 83 | assign WAVE_LENGTH = CYCLES_HIGH + CYCLES_LOW; 84 | 85 | reg[63:0] wave_length_counter = 0; 86 | 87 | reg signed[15:0] unfiltered_out = 0; 88 | 89 | rate_of_change_limiter #( 90 | .SAMPLE_RATE(SAMPLE_RATE), 91 | .MAX_CHANGE_RATE(200000) 92 | ) slew_rate ( 93 | clk, 94 | I_RSTn, 95 | audio_clk_en, 96 | unfiltered_out, 97 | out 98 | ); 99 | 100 | always @(posedge clk, negedge I_RSTn) begin 101 | if(!I_RSTn)begin 102 | unfiltered_out <= 0; 103 | to_log_8_shifted <= 0; 104 | wave_length_counter <= 0; 105 | CYCLES_HIGH <= 1000; 106 | end else begin 107 | v_control_divided_two_vcc_minus_vcontrol <= v_control_safe / (two_vcc_minus_vcontrol >> 8); 108 | two_vcc_minus_vcontrol <= (VCC << 1) - (v_control_safe << 1); 109 | to_log_8_shifted <= (1 << 8) + v_control_divided_two_vcc_minus_vcontrol; 110 | CYCLES_HIGH <= ((CLOCK_RATE_C_R1_R2 >> 4) * ln_vc_vcc_vc_8_shifted) >> 4; // C⋅(R1+R2)⋅ln(1+v_control/(2*(VCC−v_control))) 111 | 112 | if(wave_length_counter < WAVE_LENGTH)begin 113 | wave_length_counter <= wave_length_counter + 1; 114 | end else begin 115 | wave_length_counter <= 0; 116 | end 117 | 118 | if(audio_clk_en)begin 119 | unfiltered_out <= wave_length_counter < CYCLES_HIGH ? 16384 : 0; 120 | end 121 | end 122 | end 123 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/dkong_bram.v: -------------------------------------------------------------------------------- 1 | 2 | module ram_1024_8_8 3 | ( 4 | input I_CLKA,I_CLKB, 5 | input [9:0]I_ADDRA,I_ADDRB, 6 | input [7:0]I_DA,I_DB, 7 | input I_CEA,I_CEB, 8 | input I_WEA,I_WEB, 9 | output [7:0]O_DA,O_DB 10 | ); 11 | 12 | wire [7:0]W_DOA,W_DOB; 13 | assign O_DA = I_CEA ? W_DOA : 8'h00; 14 | assign O_DB = I_CEB ? W_DOB : 8'h00; 15 | 16 | dpram #(10,8) ram_1024_8_8 17 | ( 18 | .clock_a(I_CLKA), 19 | .address_a(I_ADDRA), 20 | .data_a(I_DA), 21 | .enable_a(I_CEA), 22 | .wren_a(I_WEA), 23 | .q_a(W_DOA), 24 | 25 | .clock_b(I_CLKB), 26 | .address_b(I_ADDRB), 27 | .data_b(I_DB), 28 | .enable_b(I_CEB), 29 | .wren_b(I_WEB), 30 | .q_b(W_DOB) 31 | ); 32 | 33 | endmodule 34 | 35 | ///////////////////////////////////////////////////////////////////// 36 | 37 | module ram_1024_8 38 | ( 39 | input I_CLK, 40 | input [9:0]I_ADDR, 41 | input [7:0]I_D, 42 | input I_CE, 43 | input I_WE, 44 | output [7:0]O_D 45 | ); 46 | 47 | wire [7:0]W_DO; 48 | assign O_D = I_CE ? W_DO : 8'h00; 49 | 50 | dpram #(10,8) ram_1024_8 51 | ( 52 | .clock_a(I_CLK), 53 | .address_a(I_ADDR), 54 | .data_a(I_D), 55 | .wren_a(I_WE), 56 | .enable_a(I_CE), 57 | .q_a(W_DO), 58 | 59 | .clock_b(I_CLK) 60 | ); 61 | 62 | endmodule 63 | 64 | ///////////////////////////////////////////////////////////////////// 65 | 66 | module ram_2N 67 | ( 68 | input I_CLK, 69 | input [7:0]I_ADDR, 70 | input [3:0]I_D, 71 | input I_CE, 72 | input I_WE, 73 | output [3:0]O_D 74 | ); 75 | 76 | dpram #(8,4) ram_256_4 77 | ( 78 | .clock_a(I_CLK), 79 | .address_a(I_ADDR), 80 | .data_a(I_D), 81 | .wren_a(I_WE), 82 | .enable_a(I_CE), 83 | .q_a(O_D), 84 | 85 | .clock_b(I_CLK) 86 | ); 87 | 88 | endmodule 89 | 90 | ///////////////////////////////////////////////////////////////////// 91 | 92 | module ram_2EH7M 93 | ( 94 | input I_CLKA,I_CLKB, 95 | input [7:0]I_ADDRA, 96 | input [5:0]I_ADDRB, 97 | input [5:0]I_DA, 98 | input [8:0]I_DB, 99 | input I_CEA,I_CEB, 100 | input I_WEA,I_WEB, 101 | output [5:0]O_DA, 102 | output [8:0]O_DB 103 | ); 104 | 105 | dpram #(8,6) ram_256_6 106 | ( 107 | .clock_a(I_CLKA), 108 | .address_a(I_ADDRA), 109 | .data_a(I_DA), 110 | .enable_a(I_CEA), 111 | .wren_a(I_WEA), 112 | .q_a(O_DA), 113 | 114 | .clock_b(I_CLKA) 115 | ); 116 | 117 | dpram #(6,9) ram_64_9 118 | ( 119 | .clock_a(I_CLKB), 120 | .address_a(I_ADDRB), 121 | .data_a(I_DB), 122 | .enable_a(I_CEB), 123 | .wren_a(I_WEB), 124 | .q_a(O_DB), 125 | 126 | .clock_b(I_CLKB) 127 | ); 128 | 129 | endmodule 130 | 131 | ///////////////////////////////////////////////////////////////////// 132 | 133 | module ram_2EF 134 | ( 135 | input I_CLKA,I_CLKB, 136 | input [7:0]I_ADDRA,I_ADDRB, 137 | input [7:0]I_DA,I_DB, 138 | input I_CEA,I_CEB, 139 | input I_WEA,I_WEB, 140 | output [7:0]O_DA,O_DB 141 | ); 142 | 143 | dpram #(9,8) ram_512_8 144 | ( 145 | .clock_a(I_CLKA), 146 | .address_a({1'b0,I_ADDRA}), 147 | .data_a(I_DA), 148 | .enable_a(I_CEA), 149 | .wren_a(I_WEA), 150 | .q_a(O_DA), 151 | 152 | .clock_b(I_CLKB), 153 | .address_b({1'b1,I_ADDRB}), 154 | .data_b(I_DB), 155 | .enable_b(I_CEB), 156 | .wren_b(I_WEB), 157 | .q_b(O_DB) 158 | ); 159 | 160 | endmodule 161 | 162 | ///////////////////////////////////////////////////////////////////// 163 | 164 | module double_scan 165 | ( 166 | input I_CLKA,I_CLKB, 167 | input [8:0]I_ADDRA,I_ADDRB, 168 | input [7:0]I_DA,I_DB, 169 | input I_CEA,I_CEB, 170 | input I_WEA,I_WEB, 171 | output [7:0]O_DA,O_DB 172 | ); 173 | 174 | dpram #(9,8) ram_512_8 175 | ( 176 | .clock_a(I_CLKA), 177 | .address_a(I_ADDRA), 178 | .data_a(I_DA), 179 | .enable_a(I_CEA), 180 | .wren_a(I_WEA), 181 | .q_a(O_DA), 182 | 183 | .clock_b(I_CLKB), 184 | .address_b(I_ADDRB), 185 | .data_b(I_DB), 186 | .enable_b(I_CEB), 187 | .wren_b(I_WEB), 188 | .q_b(O_DB) 189 | ); 190 | 191 | endmodule 192 | 193 | ///////////////////////////////////////////////////////////////////// 194 | 195 | module ram_64_8 196 | ( 197 | input I_CLK, 198 | input [5:0]I_ADDR, 199 | input [7:0]I_D, 200 | input I_CE, 201 | input I_WE, 202 | output [7:0]O_D 203 | ); 204 | 205 | dpram #(6,8) ram_64_8 206 | ( 207 | .clock_a(I_CLK), 208 | .address_a(I_ADDR), 209 | .data_a(I_D), 210 | .wren_a(I_WE), 211 | .enable_a(I_CE), 212 | .q_a(O_D), 213 | 214 | .clock_b(I_CLK) 215 | ); 216 | 217 | endmodule 218 | 219 | ///////////////////////////////////////////////////////////////////// 220 | 221 | module ram_2048_8 222 | ( 223 | input I_CLK, 224 | input [10:0]I_ADDR, 225 | input [7:0]I_D, 226 | input I_CE, 227 | input I_WE, 228 | output [7:0]O_D 229 | ); 230 | 231 | dpram #(11,8) ram_2048_8 232 | ( 233 | .clock_a(I_CLK), 234 | .address_a(I_ADDR), 235 | .data_a(I_D), 236 | .wren_a(I_WE), 237 | .enable_a(I_CE), 238 | .q_a(O_D), 239 | 240 | .clock_b(I_CLK) 241 | ); 242 | 243 | endmodule 244 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/mister-discrete/dk_walk.sv: -------------------------------------------------------------------------------- 1 | /********************************************************************************\ 2 | * 3 | * MiSTer Discrete example circuit - dk walk 4 | * 5 | * Copyright 2022 by Jegor van Opdorp. 6 | * This program is free software under the terms of the GPLv3, see LICENCSE.txt 7 | * 8 | ********************************************************************************/ 9 | module dk_walk #( 10 | parameter CLOCK_RATE = 1000000, 11 | parameter SAMPLE_RATE = 48000 12 | )( 13 | input clk, 14 | input I_RSTn, 15 | input audio_clk_en, 16 | input walk_en, 17 | output reg signed[15:0] out = 0 18 | ); 19 | wire signed[15:0] square_osc_out; 20 | wire signed[15:0] v_control; 21 | wire signed[15:0] mixer_input[1:0]; 22 | 23 | wire signed[15:0] walk_en_5volts; 24 | wire signed[15:0] walk_en_5volts_filtered; 25 | assign walk_en_5volts = walk_en ? 0 : 'd6826; // 2^14 * 5/12 = 6826 , for 5 volts 26 | 27 | // filter to simulate transfer rate of invertors 28 | rate_of_change_limiter #( 29 | .SAMPLE_RATE(SAMPLE_RATE), 30 | .MAX_CHANGE_RATE(950) 31 | ) slew_rate ( 32 | .clk(clk), 33 | .I_RSTn(I_RSTn), 34 | .audio_clk_en(audio_clk_en), 35 | .in(walk_en_5volts), 36 | .out(walk_en_5volts_filtered) 37 | ); 38 | 39 | assign mixer_input[0] = walk_en_5volts_filtered; 40 | assign mixer_input[1] = square_osc_out; 41 | 42 | localparam SAMPLE_RATE_SHIFT = 3; 43 | localparam INTEGRATOR_SAMPLE_RATE = SAMPLE_RATE >> SAMPLE_RATE_SHIFT; 44 | 45 | wire signed[15:0] walk_en_filtered; 46 | wire signed[15:0] astable_555_out; 47 | 48 | invertor_square_wave_oscilator#( 49 | .CLOCK_RATE(CLOCK_RATE), 50 | .SAMPLE_RATE(SAMPLE_RATE), 51 | .R1(4100),// sligtly slower R, to simulate slower freq due to transfer rate of inverters 52 | .C_MICROFARADS_16_SHIFTED(655360) 53 | ) square ( 54 | .clk(clk), 55 | .I_RSTn(I_RSTn), 56 | .audio_clk_en(audio_clk_en), 57 | .out(square_osc_out) 58 | ); 59 | 60 | resistive_two_way_mixer #( 61 | .R0(10000), 62 | .R1(12000) 63 | ) mixer ( 64 | .clk(clk), 65 | .I_RSTn(I_RSTn), 66 | .audio_clk_en(audio_clk_en), 67 | .inputs(mixer_input), 68 | .out(v_control) 69 | ); 70 | 71 | wire signed[15:0] v_control_filtered; 72 | 73 | resistor_capacitor_low_pass_filter #( 74 | .SAMPLE_RATE(SAMPLE_RATE), 75 | .R(3700), //TODO actual value is 1200, but 3700 a closer response, probably need a better low pass implementation 76 | .C_35_SHIFTED(113387) 77 | ) filter4 ( 78 | .clk(clk), 79 | .I_RSTn(I_RSTn), 80 | .audio_clk_en(audio_clk_en), 81 | .in(v_control), 82 | .out(v_control_filtered) 83 | ); 84 | 85 | //TODO: properly calculate influence of 555 timer on input voltage 86 | astable_555_vco #( 87 | .CLOCK_RATE(CLOCK_RATE), 88 | .SAMPLE_RATE(SAMPLE_RATE), 89 | .R1(47000), 90 | .R2(27000), 91 | .C_35_SHIFTED(1134) 92 | ) vco ( 93 | .clk(clk), 94 | .I_RSTn(I_RSTn), 95 | .audio_clk_en(audio_clk_en), 96 | .v_control((v_control_filtered >>> 1) + 16'd5900), 97 | .out(astable_555_out) 98 | ); 99 | 100 | resistor_capacitor_high_pass_filter #( 101 | .SAMPLE_RATE(SAMPLE_RATE), 102 | .R(9200), // not sure what this should be 103 | .C_35_SHIFTED(113387) 104 | ) filter1 ( 105 | .clk(clk), 106 | .I_RSTn(I_RSTn), 107 | .audio_clk_en(audio_clk_en), 108 | .in(walk_en_5volts_filtered), 109 | .out(walk_en_filtered) 110 | ); 111 | 112 | wire signed[15:0] walk_enveloped; 113 | assign walk_enveloped = astable_555_out > 1000 ? walk_en_filtered : 0; 114 | 115 | wire signed[15:0] walk_enveloped_high_passed; 116 | 117 | resistor_capacitor_high_pass_filter #( 118 | .SAMPLE_RATE(SAMPLE_RATE), 119 | .R(2000), 120 | .C_35_SHIFTED(161491) 121 | ) filter2 ( 122 | .clk(clk), 123 | .I_RSTn(I_RSTn), 124 | .audio_clk_en(audio_clk_en), 125 | .in(walk_enveloped), 126 | .out(walk_enveloped_high_passed) 127 | ); 128 | 129 | wire signed[15:0] walk_enveloped_band_passed; 130 | 131 | resistor_capacitor_low_pass_filter #( 132 | .SAMPLE_RATE(SAMPLE_RATE), 133 | .R(3000), // actually 5.6K 134 | .C_35_SHIFTED(1614) 135 | ) filter3 ( 136 | .clk(clk), 137 | .I_RSTn(I_RSTn), 138 | .audio_clk_en(audio_clk_en), 139 | .in(walk_enveloped_high_passed), 140 | .out(walk_enveloped_band_passed) 141 | ); 142 | 143 | 144 | 145 | always @(posedge clk, negedge I_RSTn) begin 146 | if(!I_RSTn)begin 147 | out <= 0; 148 | end else if(audio_clk_en)begin 149 | if(walk_enveloped_band_passed > 0) begin //TODO: hack to simulate diode connection coming from ground 150 | out <= walk_enveloped_band_passed + (walk_enveloped_band_passed >>> 1); 151 | end else begin 152 | out <= walk_enveloped_band_passed >>> 1 + (walk_enveloped_band_passed >>> 2); 153 | end 154 | end 155 | end 156 | 157 | endmodule -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/T80_Reg.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- **** 3 | -- T80(c) core. Attempt to finish all undocumented features and provide 4 | -- accurate timings. 5 | -- Version 350. 6 | -- Copyright (c) 2018 Sorgelig 7 | -- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr 8 | -- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as 9 | -- correct implementation is still unclear. 10 | -- 11 | -- **** 12 | -- T80(b) core. In an effort to merge and maintain bug fixes .... 13 | -- 14 | -- 15 | -- Ver 300 started tidyup 16 | -- MikeJ March 2005 17 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) 18 | -- 19 | -- **** 20 | -- 21 | -- T80 Registers, technology independent 22 | -- 23 | -- Version : 0244 24 | -- 25 | -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) 26 | -- 27 | -- All rights reserved 28 | -- 29 | -- Redistribution and use in source and synthezised forms, with or without 30 | -- modification, are permitted provided that the following conditions are met: 31 | -- 32 | -- Redistributions of source code must retain the above copyright notice, 33 | -- this list of conditions and the following disclaimer. 34 | -- 35 | -- Redistributions in synthesized form must reproduce the above copyright 36 | -- notice, this list of conditions and the following disclaimer in the 37 | -- documentation and/or other materials provided with the distribution. 38 | -- 39 | -- Neither the name of the author nor the names of other contributors may 40 | -- be used to endorse or promote products derived from this software without 41 | -- specific prior written permission. 42 | -- 43 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 44 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 45 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 47 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 | -- POSSIBILITY OF SUCH DAMAGE. 54 | -- 55 | -- Please report bugs to the author, but before you do so, please 56 | -- make sure that this is not a derivative work and that 57 | -- you have the latest version of this file. 58 | -- 59 | -- The latest version of this file can be found at: 60 | -- http://www.opencores.org/cvsweb.shtml/t51/ 61 | -- 62 | -- Limitations : 63 | -- 64 | -- File history : 65 | -- 66 | -- 0242 : Initial release 67 | -- 68 | -- 0244 : Changed to single register file 69 | -- 70 | 71 | library IEEE; 72 | use IEEE.std_logic_1164.all; 73 | use IEEE.numeric_std.all; 74 | 75 | entity T80_Reg is 76 | port( 77 | Clk : in std_logic; 78 | CEN : in std_logic; 79 | WEH : in std_logic; 80 | WEL : in std_logic; 81 | AddrA : in std_logic_vector(2 downto 0); 82 | AddrB : in std_logic_vector(2 downto 0); 83 | AddrC : in std_logic_vector(2 downto 0); 84 | DIH : in std_logic_vector(7 downto 0); 85 | DIL : in std_logic_vector(7 downto 0); 86 | DOAH : out std_logic_vector(7 downto 0); 87 | DOAL : out std_logic_vector(7 downto 0); 88 | DOBH : out std_logic_vector(7 downto 0); 89 | DOBL : out std_logic_vector(7 downto 0); 90 | DOCH : out std_logic_vector(7 downto 0); 91 | DOCL : out std_logic_vector(7 downto 0); 92 | DOR : out std_logic_vector(127 downto 0); 93 | DIRSet : in std_logic; 94 | DIR : in std_logic_vector(127 downto 0) 95 | ); 96 | end T80_Reg; 97 | 98 | architecture rtl of T80_Reg is 99 | 100 | type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); 101 | signal RegsH : Register_Image(0 to 7); 102 | signal RegsL : Register_Image(0 to 7); 103 | 104 | begin 105 | 106 | process (Clk) 107 | begin 108 | if rising_edge(Clk) then 109 | if DIRSet = '1' then 110 | RegsL(0) <= DIR( 7 downto 0); 111 | RegsH(0) <= DIR( 15 downto 8); 112 | 113 | RegsL(1) <= DIR( 23 downto 16); 114 | RegsH(1) <= DIR( 31 downto 24); 115 | 116 | RegsL(2) <= DIR( 39 downto 32); 117 | RegsH(2) <= DIR( 47 downto 40); 118 | 119 | RegsL(3) <= DIR( 55 downto 48); 120 | RegsH(3) <= DIR( 63 downto 56); 121 | 122 | RegsL(4) <= DIR( 71 downto 64); 123 | RegsH(4) <= DIR( 79 downto 72); 124 | 125 | RegsL(5) <= DIR( 87 downto 80); 126 | RegsH(5) <= DIR( 95 downto 88); 127 | 128 | RegsL(6) <= DIR(103 downto 96); 129 | RegsH(6) <= DIR(111 downto 104); 130 | 131 | RegsL(7) <= DIR(119 downto 112); 132 | RegsH(7) <= DIR(127 downto 120); 133 | elsif CEN = '1' then 134 | if WEH = '1' then 135 | RegsH(to_integer(unsigned(AddrA))) <= DIH; 136 | end if; 137 | if WEL = '1' then 138 | RegsL(to_integer(unsigned(AddrA))) <= DIL; 139 | end if; 140 | end if; 141 | end if; 142 | end process; 143 | 144 | DOAH <= RegsH(to_integer(unsigned(AddrA))); 145 | DOAL <= RegsL(to_integer(unsigned(AddrA))); 146 | DOBH <= RegsH(to_integer(unsigned(AddrB))); 147 | DOBL <= RegsL(to_integer(unsigned(AddrB))); 148 | DOCH <= RegsH(to_integer(unsigned(AddrC))); 149 | DOCL <= RegsL(to_integer(unsigned(AddrC))); 150 | DOR <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0); 151 | 152 | end; 153 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/p1.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The Port 1 unit. 4 | -- Implements the Port 1 logic. 5 | -- 6 | -- $Id: p1.vhd,v 1.5 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t48/ 44 | -- 45 | ------------------------------------------------------------------------------- 46 | 47 | library ieee; 48 | use ieee.std_logic_1164.all; 49 | 50 | use work.t48_pack.word_t; 51 | 52 | entity t48_p1 is 53 | 54 | port ( 55 | -- Global Interface ------------------------------------------------------- 56 | clk_i : in std_logic; 57 | res_i : in std_logic; 58 | en_clk_i : in boolean; 59 | -- T48 Bus Interface ------------------------------------------------------ 60 | data_i : in word_t; 61 | data_o : out word_t; 62 | write_p1_i : in boolean; 63 | read_p1_i : in boolean; 64 | read_reg_i : in boolean; 65 | -- Port 1 Interface ------------------------------------------------------- 66 | p1_i : in word_t; 67 | p1_o : out word_t; 68 | p1_low_imp_o : out std_logic 69 | ); 70 | 71 | end t48_p1; 72 | 73 | 74 | use work.t48_pack.clk_active_c; 75 | use work.t48_pack.res_active_c; 76 | use work.t48_pack.bus_idle_level_c; 77 | 78 | architecture rtl of t48_p1 is 79 | 80 | -- the port output register 81 | signal p1_q : word_t; 82 | 83 | -- the low impedance marker 84 | signal low_imp_q : std_logic; 85 | 86 | begin 87 | 88 | ----------------------------------------------------------------------------- 89 | -- Process p1_reg 90 | -- 91 | -- Purpose: 92 | -- Implements the port output register. 93 | -- 94 | p1_reg: process (res_i, clk_i) 95 | begin 96 | if res_i = res_active_c then 97 | p1_q <= (others => '1'); 98 | low_imp_q <= '0'; 99 | 100 | elsif clk_i'event and clk_i = clk_active_c then 101 | if en_clk_i then 102 | 103 | if write_p1_i then 104 | p1_q <= data_i; 105 | low_imp_q <= '1'; 106 | else 107 | low_imp_q <= '0'; 108 | end if; 109 | 110 | end if; 111 | 112 | end if; 113 | 114 | end process p1_reg; 115 | -- 116 | ----------------------------------------------------------------------------- 117 | 118 | 119 | ----------------------------------------------------------------------------- 120 | -- Process p1_data 121 | -- 122 | -- Purpose: 123 | -- Generates the T48 bus data. 124 | -- 125 | p1_data: process (read_p1_i, 126 | p1_i, 127 | read_reg_i, 128 | p1_q) 129 | begin 130 | data_o <= (others => bus_idle_level_c); 131 | 132 | if read_p1_i then 133 | if read_reg_i then 134 | data_o <= p1_q; 135 | else 136 | data_o <= p1_i; 137 | end if; 138 | end if; 139 | 140 | end process p1_data; 141 | -- 142 | ----------------------------------------------------------------------------- 143 | 144 | 145 | ----------------------------------------------------------------------------- 146 | -- Output Mapping. 147 | ----------------------------------------------------------------------------- 148 | p1_o <= p1_q; 149 | p1_low_imp_o <= low_imp_q; 150 | 151 | end rtl; 152 | 153 | 154 | ------------------------------------------------------------------------------- 155 | -- File History: 156 | -- 157 | -- $Log: p1.vhd,v $ 158 | -- Revision 1.5 2005/06/11 10:08:43 arniml 159 | -- introduce prefix 't48_' for all packages, entities and configurations 160 | -- 161 | -- Revision 1.4 2004/07/11 16:51:33 arniml 162 | -- cleanup copyright notice 163 | -- 164 | -- Revision 1.3 2004/05/17 14:37:53 arniml 165 | -- reorder data_o generation 166 | -- 167 | -- Revision 1.2 2004/03/29 19:39:58 arniml 168 | -- rename pX_limp to pX_low_imp 169 | -- 170 | -- Revision 1.1 2004/03/23 21:31:52 arniml 171 | -- initial check-in 172 | -- 173 | ------------------------------------------------------------------------------- 174 | -------------------------------------------------------------------------------- /src/fpga/core/sound_i2s.sv: -------------------------------------------------------------------------------- 1 | // MIT License 2 | 3 | // Copyright (c) 2022 Adam Gastineau 4 | 5 | // Permission is hereby granted, free of charge, to any person obtaining a copy 6 | // of this software and associated documentation files (the "Software"), to deal 7 | // in the Software without restriction, including without limitation the rights 8 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | // copies of the Software, and to permit persons to whom the Software is 10 | // furnished to do so, subject to the following conditions: 11 | 12 | // The above copyright notice and this permission notice shall be included in all 13 | // copies or substantial portions of the Software. 14 | 15 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | // SOFTWARE. 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | // A very simple audio i2s bridge to APF, based on their example code 26 | module sound_i2s #( 27 | parameter CHANNEL_WIDTH = 15, 28 | parameter SIGNED_INPUT = 0 29 | ) ( 30 | input wire clk_74a, 31 | input wire clk_audio, 32 | 33 | // Left and right audio channels. Can be in an arbitrary clock domain 34 | input wire [CHANNEL_WIDTH - 1:0] audio_l, 35 | input wire [CHANNEL_WIDTH - 1:0] audio_r, 36 | 37 | output reg audio_mclk, 38 | output reg audio_lrck, 39 | output reg audio_dac 40 | ); 41 | // 42 | // audio i2s generator 43 | // 44 | 45 | reg audgen_nextsamp; 46 | 47 | // generate MCLK = 12.288mhz with fractional accumulator 48 | reg [21:0] audgen_accum = 0; 49 | parameter [20:0] CYCLE_48KHZ = 21'd122880 * 2; 50 | always @(posedge clk_74a) begin 51 | audgen_accum <= audgen_accum + CYCLE_48KHZ; 52 | if (audgen_accum >= 21'd742500) begin 53 | audio_mclk <= ~audio_mclk; 54 | audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ; 55 | end 56 | end 57 | 58 | // generate SCLK = 3.072mhz by dividing MCLK by 4 59 | reg [1:0] aud_mclk_divider; 60 | reg prev_audio_mclk; 61 | wire audgen_sclk = aud_mclk_divider[1] /* synthesis keep*/; 62 | 63 | always @(posedge clk_74a) begin 64 | if (audio_mclk && ~prev_audio_mclk) begin 65 | aud_mclk_divider <= aud_mclk_divider + 1'b1; 66 | end 67 | 68 | prev_audio_mclk <= audio_mclk; 69 | end 70 | 71 | // shift out audio data as I2S 72 | // 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits 73 | // 74 | // synchronize audio samples coming from the core 75 | 76 | localparam CHANNEL_LEFT_HIGH = SIGNED_INPUT ? 16 : 15; 77 | localparam CHANNEL_RIGHT_HIGH = 16 + CHANNEL_LEFT_HIGH; 78 | 79 | // Width of channel with signed component 80 | localparam SIGNED_CHANNEL_WIDTH = SIGNED_INPUT ? CHANNEL_WIDTH : CHANNEL_WIDTH + 1; 81 | 82 | wire [31:0] audgen_sampdata; 83 | 84 | assign audgen_sampdata[CHANNEL_LEFT_HIGH-1:CHANNEL_LEFT_HIGH-CHANNEL_WIDTH] = audio_l; 85 | assign audgen_sampdata[CHANNEL_RIGHT_HIGH-1:CHANNEL_RIGHT_HIGH-CHANNEL_WIDTH] = audio_r; 86 | 87 | generate 88 | if (!SIGNED_INPUT) begin 89 | // If not signed, make sure high bit is 0 90 | assign audgen_sampdata[31] = 0; 91 | assign audgen_sampdata[15] = 0; 92 | end 93 | endgenerate 94 | 95 | generate 96 | if (15 - SIGNED_CHANNEL_WIDTH > 0) begin 97 | assign audgen_sampdata[31-SIGNED_CHANNEL_WIDTH:16] = 0; 98 | assign audgen_sampdata[15-SIGNED_CHANNEL_WIDTH:0] = 0; 99 | end 100 | endgenerate 101 | 102 | sync_fifo #( 103 | .WIDTH(32) 104 | ) sync_fifo ( 105 | .clk_write(clk_audio), 106 | .clk_read (clk_74a), 107 | 108 | .write_en(write_en), 109 | .data_in (audgen_sampdata), 110 | .data_out(audgen_sampdata_s) 111 | ); 112 | 113 | reg write_en = 0; 114 | reg [CHANNEL_WIDTH - 1:0] prev_left; 115 | reg [CHANNEL_WIDTH - 1:0] prev_right; 116 | 117 | // Mark write when necessary 118 | always @(posedge clk_audio) begin 119 | prev_left <= audio_l; 120 | prev_right <= audio_r; 121 | 122 | write_en <= 0; 123 | 124 | if (audio_l != prev_left || audio_r != prev_right) begin 125 | write_en <= 1; 126 | end 127 | end 128 | 129 | wire [31:0] audgen_sampdata_s; 130 | 131 | reg [31:0] audgen_sampshift; 132 | reg [4:0] audio_lrck_cnt; 133 | reg prev_audgen_sclk; 134 | always @(posedge clk_74a) begin 135 | if (prev_audgen_sclk && ~audgen_sclk) begin 136 | // output the next bit 137 | audio_dac <= audgen_sampshift[31]; 138 | 139 | // 48khz * 64 140 | audio_lrck_cnt <= audio_lrck_cnt + 1'b1; 141 | if (audio_lrck_cnt == 31) begin 142 | // switch channels 143 | audio_lrck <= ~audio_lrck; 144 | 145 | // Reload sample shifter 146 | if (~audio_lrck) begin 147 | audgen_sampshift <= audgen_sampdata_s; 148 | end 149 | end else if (audio_lrck_cnt < 16) begin 150 | // only shift for 16 clocks per channel 151 | audgen_sampshift <= {audgen_sampshift[30:0], 1'b0}; 152 | end 153 | end 154 | 155 | prev_audgen_sclk <= audgen_sclk; 156 | end 157 | 158 | initial begin 159 | // Verify parameters 160 | if (CHANNEL_WIDTH > 16) begin 161 | $error("CHANNEL_WIDTH must be <= 16. Received %d", CHANNEL_WIDTH); 162 | end 163 | 164 | if (SIGNED_INPUT != 0 && SIGNED_INPUT != 1) begin 165 | $error("SIGNED_INPUT must be 0 or 1. Received %d", SIGNED_INPUT); 166 | end 167 | 168 | if (CHANNEL_WIDTH == 16 && SIGNED_INPUT == 0) begin 169 | $error("Cannot have CHANNEL_WIDTH of 16 and an unsigned input"); 170 | end 171 | end 172 | endmodule 173 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTDDIO_BIDIR% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTDDIO_BIDIR 5 | 6 | // ============================================================ 7 | // File Name: mf_ddio_bidir_12.v 8 | // Megafunction Name(s): 9 | // ALTDDIO_BIDIR 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 21.1.1 Build 850 06/23/2022 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2022 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module mf_ddio_bidir_12 ( 41 | datain_h, 42 | datain_l, 43 | inclock, 44 | oe, 45 | outclock, 46 | dataout_h, 47 | dataout_l, 48 | padio); 49 | 50 | input [11:0] datain_h; 51 | input [11:0] datain_l; 52 | input inclock; 53 | input oe; 54 | input outclock; 55 | output [11:0] dataout_h; 56 | output [11:0] dataout_l; 57 | inout [11:0] padio; 58 | 59 | wire [11:0] sub_wire0; 60 | wire [11:0] sub_wire1; 61 | wire [11:0] dataout_h = sub_wire0[11:0]; 62 | wire [11:0] dataout_l = sub_wire1[11:0]; 63 | 64 | altddio_bidir ALTDDIO_BIDIR_component ( 65 | .datain_h (datain_h), 66 | .datain_l (datain_l), 67 | .inclock (inclock), 68 | .oe (oe), 69 | .outclock (outclock), 70 | .padio (padio), 71 | .dataout_h (sub_wire0), 72 | .dataout_l (sub_wire1), 73 | .aclr (1'b0), 74 | .aset (1'b0), 75 | .combout (), 76 | .dqsundelayedout (), 77 | .inclocken (1'b1), 78 | .oe_out (), 79 | .outclocken (1'b1), 80 | .sclr (1'b0), 81 | .sset (1'b0)); 82 | defparam 83 | ALTDDIO_BIDIR_component.extend_oe_disable = "OFF", 84 | ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF", 85 | ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V", 86 | ALTDDIO_BIDIR_component.invert_output = "OFF", 87 | ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", 88 | ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", 89 | ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED", 90 | ALTDDIO_BIDIR_component.power_up_high = "OFF", 91 | ALTDDIO_BIDIR_component.width = 12; 92 | 93 | 94 | endmodule 95 | 96 | // ============================================================ 97 | // CNX file retrieval info 98 | // ============================================================ 99 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 100 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 101 | // Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" 102 | // Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "OFF" 103 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 104 | // Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" 105 | // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" 106 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" 107 | // Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" 108 | // Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" 109 | // Retrieval info: CONSTANT: WIDTH NUMERIC "12" 110 | // Retrieval info: USED_PORT: datain_h 0 0 12 0 INPUT NODEFVAL "datain_h[11..0]" 111 | // Retrieval info: CONNECT: @datain_h 0 0 12 0 datain_h 0 0 12 0 112 | // Retrieval info: USED_PORT: datain_l 0 0 12 0 INPUT NODEFVAL "datain_l[11..0]" 113 | // Retrieval info: CONNECT: @datain_l 0 0 12 0 datain_l 0 0 12 0 114 | // Retrieval info: USED_PORT: dataout_h 0 0 12 0 OUTPUT NODEFVAL "dataout_h[11..0]" 115 | // Retrieval info: CONNECT: dataout_h 0 0 12 0 @dataout_h 0 0 12 0 116 | // Retrieval info: USED_PORT: dataout_l 0 0 12 0 OUTPUT NODEFVAL "dataout_l[11..0]" 117 | // Retrieval info: CONNECT: dataout_l 0 0 12 0 @dataout_l 0 0 12 0 118 | // Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" 119 | // Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 120 | // Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" 121 | // Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 122 | // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" 123 | // Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 124 | // Retrieval info: USED_PORT: padio 0 0 12 0 BIDIR NODEFVAL "padio[11..0]" 125 | // Retrieval info: CONNECT: padio 0 0 12 0 @padio 0 0 12 0 126 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.v TRUE FALSE 127 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.qip TRUE FALSE 128 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.bsf FALSE TRUE 129 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_inst.v FALSE TRUE 130 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_bb.v FALSE TRUE 131 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.inc FALSE TRUE 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.cmp FALSE TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.ppf TRUE FALSE 134 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/t48/db_bus.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- 3 | -- The BUS unit. 4 | -- Implements the BUS port logic. 5 | -- 6 | -- $Id: db_bus.vhd,v 1.5 2005/06/11 10:08:43 arniml Exp $ 7 | -- 8 | -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) 9 | -- 10 | -- All rights reserved 11 | -- 12 | -- Redistribution and use in source and synthezised forms, with or without 13 | -- modification, are permitted provided that the following conditions are met: 14 | -- 15 | -- Redistributions of source code must retain the above copyright notice, 16 | -- this list of conditions and the following disclaimer. 17 | -- 18 | -- Redistributions in synthesized form must reproduce the above copyright 19 | -- notice, this list of conditions and the following disclaimer in the 20 | -- documentation and/or other materials provided with the distribution. 21 | -- 22 | -- Neither the name of the author nor the names of other contributors may 23 | -- be used to endorse or promote products derived from this software without 24 | -- specific prior written permission. 25 | -- 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | -- POSSIBILITY OF SUCH DAMAGE. 37 | -- 38 | -- Please report bugs to the author, but before you do so, please 39 | -- make sure that this is not a derivative work and that 40 | -- you have the latest version of this file. 41 | -- 42 | -- The latest version of this file can be found at: 43 | -- http://www.opencores.org/cvsweb.shtml/t48/ 44 | -- 45 | ------------------------------------------------------------------------------- 46 | 47 | library ieee; 48 | use ieee.std_logic_1164.all; 49 | 50 | use work.t48_pack.word_t; 51 | 52 | entity t48_db_bus is 53 | 54 | port ( 55 | -- Global Interface ------------------------------------------------------- 56 | clk_i : in std_logic; 57 | res_i : in std_logic; 58 | en_clk_i : in boolean; 59 | ea_i : in std_logic; 60 | -- T48 Bus Interface ------------------------------------------------------ 61 | data_i : in word_t; 62 | data_o : out word_t; 63 | write_bus_i : in boolean; 64 | read_bus_i : in boolean; 65 | -- BUS Interface ---------------------------------------------------------- 66 | output_pcl_i : in boolean; 67 | bidir_bus_i : in boolean; 68 | pcl_i : in word_t; 69 | db_i : in word_t; 70 | db_o : out word_t; 71 | db_dir_o : out std_logic 72 | ); 73 | 74 | end t48_db_bus; 75 | 76 | 77 | use work.t48_pack.clk_active_c; 78 | use work.t48_pack.res_active_c; 79 | use work.t48_pack.bus_idle_level_c; 80 | use work.t48_pack.to_stdLogic; 81 | 82 | architecture rtl of t48_db_bus is 83 | 84 | -- the BUS output register 85 | signal bus_q : word_t; 86 | 87 | -- BUS direction marker 88 | signal db_dir_q, 89 | db_dir_qq : std_logic; 90 | 91 | begin 92 | 93 | ----------------------------------------------------------------------------- 94 | -- Process bus_regs 95 | -- 96 | -- Purpose: 97 | -- Implements the BUS output register. 98 | -- 99 | bus_regs: process (res_i, clk_i) 100 | begin 101 | if res_i = res_active_c then 102 | bus_q <= (others => '0'); 103 | db_dir_q <= '0'; 104 | db_dir_qq <= '0'; 105 | 106 | elsif clk_i'event and clk_i = clk_active_c then 107 | if en_clk_i then 108 | if write_bus_i then 109 | db_dir_qq <= '1'; 110 | else 111 | -- extend bus direction by one machine cycle 112 | db_dir_qq <= db_dir_q; 113 | end if; 114 | 115 | if write_bus_i then 116 | bus_q <= data_i; 117 | 118 | db_dir_q <= '1'; 119 | 120 | elsif ea_i = '1' or bidir_bus_i then 121 | db_dir_q <= '0'; 122 | 123 | end if; 124 | 125 | end if; 126 | 127 | end if; 128 | 129 | end process bus_regs; 130 | -- 131 | ----------------------------------------------------------------------------- 132 | 133 | 134 | ----------------------------------------------------------------------------- 135 | -- Output Mapping. 136 | ----------------------------------------------------------------------------- 137 | db_o <= pcl_i 138 | when output_pcl_i else 139 | bus_q; 140 | db_dir_o <= db_dir_qq or 141 | to_stdLogic(output_pcl_i); 142 | data_o <= (others => bus_idle_level_c) 143 | when not read_bus_i else 144 | db_i; 145 | 146 | end rtl; 147 | 148 | 149 | ------------------------------------------------------------------------------- 150 | -- File History: 151 | -- 152 | -- $Log: db_bus.vhd,v $ 153 | -- Revision 1.5 2005/06/11 10:08:43 arniml 154 | -- introduce prefix 't48_' for all packages, entities and configurations 155 | -- 156 | -- Revision 1.4 2005/06/09 22:16:26 arniml 157 | -- Implement db_dir_o glitch-safe 158 | -- 159 | -- Revision 1.3 2004/10/25 20:30:18 arniml 160 | -- delay db_dir_o by one machine cycle 161 | -- this fixes the timing relation between BUS data and WR' 162 | -- 163 | -- Revision 1.2 2004/04/04 14:15:45 arniml 164 | -- add dump_compare support 165 | -- 166 | -- Revision 1.1 2004/03/23 21:31:52 arniml 167 | -- initial check-in 168 | -- 169 | ------------------------------------------------------------------------------- 170 | -------------------------------------------------------------------------------- /src/fpga/core/rtl/T80/T80sed.vhd: -------------------------------------------------------------------------------- 1 | -- **** 2 | -- T80(b) core. In an effort to merge and maintain bug fixes .... 3 | -- 4 | -- 5 | -- Ver 300 started tidyup 6 | -- MikeJ March 2005 7 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) 8 | -- 9 | -- **** 10 | -- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** 11 | -- 12 | -- Z80 compatible microprocessor core, synchronous top level with clock enable 13 | -- Different timing than the original z80 14 | -- Inputs needs to be synchronous and outputs may glitch 15 | -- 16 | -- Version : 0238 17 | -- 18 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) 19 | -- 20 | -- All rights reserved 21 | -- 22 | -- Redistribution and use in source and synthezised forms, with or without 23 | -- modification, are permitted provided that the following conditions are met: 24 | -- 25 | -- Redistributions of source code must retain the above copyright notice, 26 | -- this list of conditions and the following disclaimer. 27 | -- 28 | -- Redistributions in synthesized form must reproduce the above copyright 29 | -- notice, this list of conditions and the following disclaimer in the 30 | -- documentation and/or other materials provided with the distribution. 31 | -- 32 | -- Neither the name of the author nor the names of other contributors may 33 | -- be used to endorse or promote products derived from this software without 34 | -- specific prior written permission. 35 | -- 36 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 37 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 38 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE 40 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 | -- POSSIBILITY OF SUCH DAMAGE. 47 | -- 48 | -- Please report bugs to the author, but before you do so, please 49 | -- make sure that this is not a derivative work and that 50 | -- you have the latest version of this file. 51 | -- 52 | -- The latest version of this file can be found at: 53 | -- http://www.opencores.org/cvsweb.shtml/t80/ 54 | -- 55 | -- Limitations : 56 | -- 57 | -- File history : 58 | -- 59 | -- 0235 : First release 60 | -- 61 | -- 0236 : Added T2Write generic 62 | -- 63 | -- 0237 : Fixed T2Write with wait state 64 | -- 65 | -- 0238 : Updated for T80 interface change 66 | -- 67 | -- 0242 : Updated for T80 interface change 68 | -- 69 | 70 | library IEEE; 71 | use IEEE.std_logic_1164.all; 72 | use IEEE.numeric_std.all; 73 | use work.T80_Pack.all; 74 | 75 | entity T80sed is 76 | port( 77 | RESET_n : in std_logic; 78 | CLK_n : in std_logic; 79 | CLKEN : in std_logic; 80 | WAIT_n : in std_logic; 81 | INT_n : in std_logic; 82 | NMI_n : in std_logic; 83 | BUSRQ_n : in std_logic; 84 | M1_n : out std_logic; 85 | MREQ_n : out std_logic; 86 | IORQ_n : out std_logic; 87 | RD_n : out std_logic; 88 | WR_n : out std_logic; 89 | RFSH_n : out std_logic; 90 | HALT_n : out std_logic; 91 | BUSAK_n : out std_logic; 92 | A : out std_logic_vector(15 downto 0); 93 | DI : in std_logic_vector(7 downto 0); 94 | DO : out std_logic_vector(7 downto 0) 95 | ); 96 | end T80sed; 97 | 98 | architecture rtl of T80sed is 99 | 100 | signal IntCycle_n : std_logic; 101 | signal NoRead : std_logic; 102 | signal Write : std_logic; 103 | signal IORQ : std_logic; 104 | signal DI_Reg : std_logic_vector(7 downto 0); 105 | signal MCycle : std_logic_vector(2 downto 0); 106 | signal TState : std_logic_vector(2 downto 0); 107 | 108 | begin 109 | 110 | u0 : T80 111 | generic map( 112 | Mode => 0, 113 | IOWait => 1) 114 | port map( 115 | CEN => CLKEN, 116 | M1_n => M1_n, 117 | IORQ => IORQ, 118 | NoRead => NoRead, 119 | Write => Write, 120 | RFSH_n => RFSH_n, 121 | HALT_n => HALT_n, 122 | WAIT_n => Wait_n, 123 | INT_n => INT_n, 124 | NMI_n => NMI_n, 125 | RESET_n => RESET_n, 126 | BUSRQ_n => BUSRQ_n, 127 | BUSAK_n => BUSAK_n, 128 | CLK_n => CLK_n, 129 | A => A, 130 | DInst => DI, 131 | DI => DI_Reg, 132 | DO => DO, 133 | MC => MCycle, 134 | TS => TState, 135 | IntCycle_n => IntCycle_n); 136 | 137 | process (RESET_n, CLK_n) 138 | begin 139 | if RESET_n = '0' then 140 | RD_n <= '1'; 141 | WR_n <= '1'; 142 | IORQ_n <= '1'; 143 | MREQ_n <= '1'; 144 | DI_Reg <= "00000000"; 145 | elsif CLK_n'event and CLK_n = '1' then 146 | if CLKEN = '1' then 147 | RD_n <= '1'; 148 | WR_n <= '1'; 149 | IORQ_n <= '1'; 150 | MREQ_n <= '1'; 151 | if MCycle = "001" then 152 | if TState = "001" or (TState = "010" and Wait_n = '0') then 153 | RD_n <= not IntCycle_n; 154 | MREQ_n <= not IntCycle_n; 155 | IORQ_n <= IntCycle_n; 156 | end if; 157 | if TState = "011" then 158 | MREQ_n <= '0'; 159 | end if; 160 | else 161 | if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then 162 | RD_n <= '0'; 163 | IORQ_n <= not IORQ; 164 | MREQ_n <= IORQ; 165 | end if; 166 | if ((TState = "001") or (TState = "010")) and Write = '1' then 167 | WR_n <= '0'; 168 | IORQ_n <= not IORQ; 169 | MREQ_n <= IORQ; 170 | end if; 171 | end if; 172 | if TState = "010" and Wait_n = '1' then 173 | DI_Reg <= DI; 174 | end if; 175 | end if; 176 | end if; 177 | end process; 178 | 179 | end; 180 | --------------------------------------------------------------------------------