├── .gitignore ├── DE2_115_CAMERA.cdf ├── DE2_115_CAMERA.qpf ├── DE2_115_CAMERA.qsf ├── DE2_115_CAMERA.sof ├── DE2_115_CAMERA.v ├── DE2_115_CAMERA_assignment_defaults.qdf ├── Line_Buffer1.qip ├── Sdram_Control ├── Sdram_Control.v ├── Sdram_Params.h ├── Sdram_RD_FIFO.qip ├── Sdram_RD_FIFO.v ├── Sdram_WR_FIFO.qip ├── Sdram_WR_FIFO.v ├── command.v ├── control_interface.v └── sdr_data_path.v ├── Sdram_RD_FIFO.qip ├── VGA_Param.h ├── stp1.stp └── v ├── CCD_Capture.v ├── I2C_CCD_Config.v ├── I2C_Controller.v ├── Line_Buffer.bsf ├── Line_Buffer.qip ├── Line_Buffer.v ├── Line_Buffer1.bsf ├── Line_Buffer1.qip ├── Line_Buffer1.v ├── MEM_SWITCH.v ├── RAW2RGB.v ├── RGB2GRAY.v ├── Reset_Delay.v ├── SEG7_LUT.v ├── SEG7_LUT_8.v ├── VGA_Controller.v ├── sdram_pll.bsf ├── sdram_pll.ppf ├── sdram_pll.qip ├── sdram_pll.v ├── vga_pll.bsf └── vga_pll.ppf /.gitignore: -------------------------------------------------------------------------------- 1 | # Working with Altera Quartus II (Q2) and do proper versioning is not that easy 2 | # but if you follow some rules it can be accomplished. :) 3 | # This file should be placed into the main directory where the .qpf file is 4 | # found. Generally Q2 throws all entities and so on in the main directory, but 5 | # you can place all stuff also in separate folders. This approach is followed 6 | # here. So when you create a new design create one or more folders where your 7 | # entities will be located and put a .gitignore in there that overrides the 8 | # ignores of this file, e.g. one single rule stating "!*" which allows now all 9 | # type of files. When you add a MegaFunction or another entity to your design, 10 | # simply add it to one of your private folders and Q2 will be happy and manage 11 | # everything quite good. When you want to do versioning of your generated 12 | # SOF/POF files, you can do this by redirecting the generated output to an own 13 | # folder. To do this go to: 14 | # "Assignments" 15 | # -> "Settings 16 | # -> "Compilation Process Settings" 17 | # -> "Save project output files in specified directory" 18 | # Now you can either place a .gitignore in the directory and allow the following 19 | # list of types: 20 | # !*.sof 21 | # !*.pof 22 | # or you create an own submodule in the folder to keep binary files out of your 23 | # design. 24 | 25 | # ignore hdl source files in top level directory 26 | #*.vhd 27 | #*.v 28 | 29 | # ignore Quartus II generated files 30 | *sopc_* 31 | *.jdi 32 | *.ptf.* 33 | #*.sof 34 | #*.pof 35 | *.qws 36 | *.smsg 37 | *_inst.vhd 38 | *_generation_script* 39 | *.done 40 | *.txt 41 | *.qarlog 42 | *.rpt 43 | *.summary 44 | *.qws 45 | *.cmp 46 | *.eqn 47 | *.html 48 | *.jpg 49 | *.bak 50 | *.qar 51 | *.sopc_builder 52 | *example* 53 | *~ 54 | *.sdc 55 | *.tcl 56 | *.pin 57 | *.mif 58 | *.hex 59 | 60 | # ignore Quartus II generated folders 61 | db/ 62 | incremental_db/ 63 | simulation/ 64 | timing/ 65 | testbench/ 66 | *_sim/ -------------------------------------------------------------------------------- /DE2_115_CAMERA.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP4CE115F29) Path("E:/FPGA_Object_Tracking-master/") File("DE2_115_CAMERA.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /DE2_115_CAMERA.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2010 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 20 | # Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version 21 | # Date created = 18:00:44 August 10, 2010 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "9.1" 26 | DATE = "18:00:44 August 10, 2010" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "DE2_115_CAMERA" 31 | -------------------------------------------------------------------------------- /DE2_115_CAMERA.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/erosen/FPGA_Object_Tracking/4b8827eed9239223612c11d7db5ac8f344878a53/DE2_115_CAMERA.sof -------------------------------------------------------------------------------- /DE2_115_CAMERA.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2010 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: DE2_115 D5M+VGA 640*480 800*600 solution 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny FAN Peli Li:| 22/07/2010:| Initial Revision 41 | // -------------------------------------------------------------------- 42 | //======================================================= 43 | // This code is generated by Terasic System Builder 44 | //======================================================= 45 | //to set the VGA solution 46 | `include "VGA_Param.h" 47 | 48 | module DE2_115_CAMERA( 49 | 50 | //////////// CLOCK ////////// 51 | CLOCK_50, 52 | CLOCK2_50, 53 | CLOCK3_50, 54 | 55 | //////////// Sma ////////// 56 | SMA_CLKIN, 57 | SMA_CLKOUT, 58 | 59 | //////////// LED ////////// 60 | LEDG, 61 | LEDR, 62 | 63 | //////////// KEY ////////// 64 | KEY, 65 | 66 | //////////// EJTAG ////////// 67 | EX_IO, 68 | 69 | //////////// SW ////////// 70 | SW, 71 | 72 | //////////// SEG7 ////////// 73 | HEX0, 74 | HEX1, 75 | HEX2, 76 | HEX3, 77 | HEX4, 78 | HEX5, 79 | HEX6, 80 | HEX7, 81 | 82 | //////////// LCD ////////// 83 | LCD_BLON, 84 | LCD_DATA, 85 | LCD_EN, 86 | LCD_ON, 87 | LCD_RS, 88 | LCD_RW, 89 | 90 | //////////// RS232 ////////// 91 | UART_CTS, 92 | UART_RTS, 93 | UART_RXD, 94 | UART_TXD, 95 | 96 | //////////// PS2 for Keyboard and Mouse ////////// 97 | PS2_CLK, 98 | PS2_CLK2, 99 | PS2_DAT, 100 | PS2_DAT2, 101 | 102 | //////////// SDCARD ////////// 103 | SD_CLK, 104 | SD_CMD, 105 | SD_DAT, 106 | SD_WP_N, 107 | 108 | //////////// VGA ////////// 109 | VGA_B, 110 | VGA_BLANK_N, 111 | VGA_CLK, 112 | VGA_G, 113 | VGA_HS, 114 | VGA_R, 115 | VGA_SYNC_N, 116 | VGA_VS, 117 | 118 | //////////// Audio ////////// 119 | AUD_ADCDAT, 120 | AUD_ADCLRCK, 121 | AUD_BCLK, 122 | AUD_DACDAT, 123 | AUD_DACLRCK, 124 | AUD_XCK, 125 | 126 | //////////// I2C for EEPROM ////////// 127 | EEP_I2C_SCLK, 128 | EEP_I2C_SDAT, 129 | 130 | //////////// I2C for Audio Tv-Decoder ////////// 131 | I2C_SCLK, 132 | I2C_SDAT, 133 | 134 | //////////// Ethernet 0 ////////// 135 | ENET0_GTX_CLK, 136 | ENET0_INT_N, 137 | ENET0_LINK100, 138 | ENET0_MDC, 139 | ENET0_MDIO, 140 | ENET0_RST_N, 141 | ENET0_RX_CLK, 142 | ENET0_RX_COL, 143 | ENET0_RX_CRS, 144 | ENET0_RX_DATA, 145 | ENET0_RX_DV, 146 | ENET0_RX_ER, 147 | ENET0_TX_CLK, 148 | ENET0_TX_DATA, 149 | ENET0_TX_EN, 150 | ENET0_TX_ER, 151 | ENETCLK_25, 152 | 153 | //////////// Ethernet 1 ////////// 154 | ENET1_GTX_CLK, 155 | ENET1_INT_N, 156 | ENET1_LINK100, 157 | ENET1_MDC, 158 | ENET1_MDIO, 159 | ENET1_RST_N, 160 | ENET1_RX_CLK, 161 | ENET1_RX_COL, 162 | ENET1_RX_CRS, 163 | ENET1_RX_DATA, 164 | ENET1_RX_DV, 165 | ENET1_RX_ER, 166 | ENET1_TX_CLK, 167 | ENET1_TX_DATA, 168 | ENET1_TX_EN, 169 | ENET1_TX_ER, 170 | 171 | //////////// TV Decoder ////////// 172 | TD_CLK27, 173 | TD_DATA, 174 | TD_HS, 175 | TD_RESET_N, 176 | TD_VS, 177 | 178 | //////////// USB 2.0 OTG ////////// 179 | OTG_ADDR, 180 | OTG_CS_N, 181 | OTG_DACK_N, 182 | OTG_DATA, 183 | OTG_DREQ, 184 | OTG_FSPEED, 185 | OTG_INT, 186 | OTG_LSPEED, 187 | OTG_RD_N, 188 | OTG_RST_N, 189 | OTG_WE_N, 190 | 191 | //////////// IR Receiver ////////// 192 | IRDA_RXD, 193 | 194 | //////////// SDRAM ////////// 195 | DRAM_ADDR, 196 | DRAM_BA, 197 | DRAM_CAS_N, 198 | DRAM_CKE, 199 | DRAM_CLK, 200 | DRAM_CS_N, 201 | DRAM_DQ, 202 | DRAM_DQM, 203 | DRAM_RAS_N, 204 | DRAM_WE_N, 205 | 206 | //////////// SRAM ////////// 207 | SRAM_ADDR, 208 | SRAM_CE_N, 209 | SRAM_DQ, 210 | SRAM_LB_N, 211 | SRAM_OE_N, 212 | SRAM_UB_N, 213 | SRAM_WE_N, 214 | 215 | //////////// Flash ////////// 216 | FL_ADDR, 217 | FL_CE_N, 218 | FL_DQ, 219 | FL_OE_N, 220 | FL_RST_N, 221 | FL_RY, 222 | FL_WE_N, 223 | FL_WP_N, 224 | 225 | //////////// GPIO, GPIO connect to D5M - 5M Pixel Camera ////////// 226 | D5M_D, 227 | D5M_FVAL, 228 | D5M_LVAL, 229 | D5M_PIXLCLK, 230 | D5M_RESET_N, 231 | D5M_SCLK, 232 | D5M_SDATA, 233 | D5M_STROBE, 234 | D5M_TRIGGER, 235 | D5M_XCLKIN 236 | ); 237 | 238 | //======================================================= 239 | // PARAMETER declarations 240 | //======================================================= 241 | 242 | 243 | //======================================================= 244 | // PORT declarations 245 | //======================================================= 246 | 247 | //////////// CLOCK ////////// 248 | input CLOCK_50; 249 | input CLOCK2_50; 250 | input CLOCK3_50; 251 | 252 | //////////// Sma ////////// 253 | input SMA_CLKIN; 254 | output SMA_CLKOUT; 255 | 256 | //////////// LED ////////// 257 | output [8:0] LEDG; 258 | output [17:0] LEDR; 259 | 260 | //////////// KEY ////////// 261 | input [3:0] KEY; 262 | 263 | //////////// EJTAG ////////// 264 | inout [6:0] EX_IO; 265 | 266 | //////////// SW ////////// 267 | input [17:0] SW; 268 | 269 | //////////// SEG7 ////////// 270 | output [6:0] HEX0; 271 | output [6:0] HEX1; 272 | output [6:0] HEX2; 273 | output [6:0] HEX3; 274 | output [6:0] HEX4; 275 | output [6:0] HEX5; 276 | output [6:0] HEX6; 277 | output [6:0] HEX7; 278 | 279 | //////////// LCD ////////// 280 | output LCD_BLON; 281 | inout [7:0] LCD_DATA; 282 | output LCD_EN; 283 | output LCD_ON; 284 | output LCD_RS; 285 | output LCD_RW; 286 | 287 | //////////// RS232 ////////// 288 | output UART_CTS; 289 | input UART_RTS; 290 | input UART_RXD; 291 | output UART_TXD; 292 | 293 | //////////// PS2 for Keyboard and Mouse ////////// 294 | inout PS2_CLK; 295 | inout PS2_CLK2; 296 | inout PS2_DAT; 297 | inout PS2_DAT2; 298 | 299 | //////////// SDCARD ////////// 300 | output SD_CLK; 301 | inout SD_CMD; 302 | inout [3:0] SD_DAT; 303 | input SD_WP_N; 304 | 305 | //////////// VGA ////////// 306 | output [7:0] VGA_B; 307 | output VGA_BLANK_N; 308 | output VGA_CLK; 309 | output [7:0] VGA_G; 310 | output VGA_HS; 311 | output [7:0] VGA_R; 312 | output VGA_SYNC_N; 313 | output VGA_VS; 314 | 315 | //////////// Audio ////////// 316 | input AUD_ADCDAT; 317 | inout AUD_ADCLRCK; 318 | inout AUD_BCLK; 319 | output AUD_DACDAT; 320 | inout AUD_DACLRCK; 321 | output AUD_XCK; 322 | 323 | //////////// I2C for EEPROM ////////// 324 | output EEP_I2C_SCLK; 325 | inout EEP_I2C_SDAT; 326 | 327 | //////////// I2C for Audio Tv-Decoder ////////// 328 | output I2C_SCLK; 329 | inout I2C_SDAT; 330 | 331 | //////////// Ethernet 0 ////////// 332 | output ENET0_GTX_CLK; 333 | input ENET0_INT_N; 334 | input ENET0_LINK100; 335 | output ENET0_MDC; 336 | inout ENET0_MDIO; 337 | output ENET0_RST_N; 338 | input ENET0_RX_CLK; 339 | input ENET0_RX_COL; 340 | input ENET0_RX_CRS; 341 | input [3:0] ENET0_RX_DATA; 342 | input ENET0_RX_DV; 343 | input ENET0_RX_ER; 344 | input ENET0_TX_CLK; 345 | output [3:0] ENET0_TX_DATA; 346 | output ENET0_TX_EN; 347 | output ENET0_TX_ER; 348 | input ENETCLK_25; 349 | 350 | //////////// Ethernet 1 ////////// 351 | output ENET1_GTX_CLK; 352 | input ENET1_INT_N; 353 | input ENET1_LINK100; 354 | output ENET1_MDC; 355 | inout ENET1_MDIO; 356 | output ENET1_RST_N; 357 | input ENET1_RX_CLK; 358 | input ENET1_RX_COL; 359 | input ENET1_RX_CRS; 360 | input [3:0] ENET1_RX_DATA; 361 | input ENET1_RX_DV; 362 | input ENET1_RX_ER; 363 | input ENET1_TX_CLK; 364 | output [3:0] ENET1_TX_DATA; 365 | output ENET1_TX_EN; 366 | output ENET1_TX_ER; 367 | 368 | //////////// TV Decoder ////////// 369 | input TD_CLK27; 370 | input [7:0] TD_DATA; 371 | input TD_HS; 372 | output TD_RESET_N; 373 | input TD_VS; 374 | 375 | //////////// USB 2.0 OTG ////////// 376 | output [1:0] OTG_ADDR; 377 | output OTG_CS_N; 378 | output [1:0] OTG_DACK_N; 379 | inout [15:0] OTG_DATA; 380 | input [1:0] OTG_DREQ; 381 | inout OTG_FSPEED; 382 | input [1:0] OTG_INT; 383 | inout OTG_LSPEED; 384 | output OTG_RD_N; 385 | output OTG_RST_N; 386 | output OTG_WE_N; 387 | 388 | //////////// IR Receiver ////////// 389 | input IRDA_RXD; 390 | 391 | //////////// SDRAM ////////// 392 | output [12:0] DRAM_ADDR; 393 | output [1:0] DRAM_BA; 394 | output DRAM_CAS_N; 395 | output DRAM_CKE; 396 | output DRAM_CLK; 397 | output DRAM_CS_N; 398 | inout [31:0] DRAM_DQ; 399 | output [3:0] DRAM_DQM; 400 | output DRAM_RAS_N; 401 | output DRAM_WE_N; 402 | 403 | //////////// SRAM ////////// 404 | output [19:0] SRAM_ADDR; 405 | output SRAM_CE_N; 406 | inout [15:0] SRAM_DQ; 407 | output SRAM_LB_N; 408 | output SRAM_OE_N; 409 | output SRAM_UB_N; 410 | output SRAM_WE_N; 411 | 412 | //////////// Flash ////////// 413 | output [22:0] FL_ADDR; 414 | output FL_CE_N; 415 | inout [7:0] FL_DQ; 416 | output FL_OE_N; 417 | output FL_RST_N; 418 | input FL_RY; 419 | output FL_WE_N; 420 | output FL_WP_N; 421 | 422 | //////////// GPIO, GPIO connect to D5M - 5M Pixel Camera ////////// 423 | input [11:0] D5M_D; 424 | input D5M_FVAL; 425 | input D5M_LVAL; 426 | input D5M_PIXLCLK; 427 | output D5M_RESET_N; 428 | output D5M_SCLK; 429 | inout D5M_SDATA; 430 | input D5M_STROBE; 431 | output D5M_TRIGGER; 432 | output D5M_XCLKIN; 433 | 434 | 435 | //======================================================= 436 | // REG/WIRE declarations 437 | //======================================================= 438 | wire [15:0] Read_DATA1; 439 | wire [15:0] Read_DATA2; 440 | 441 | wire [11:0] mCCD_DATA; 442 | wire mCCD_DVAL; 443 | wire mCCD_DVAL_d; 444 | wire [15:0] X_Cont; 445 | wire [15:0] Y_Cont; 446 | wire [9:0] X_ADDR; 447 | wire [31:0] Frame_Cont; 448 | wire DLY_RST_0; 449 | wire DLY_RST_1; 450 | wire DLY_RST_2; 451 | wire DLY_RST_3; 452 | wire DLY_RST_4; 453 | wire Read; 454 | reg [11:0] rCCD_DATA; 455 | reg rCCD_LVAL; 456 | reg rCCD_FVAL; 457 | wire [11:0] gCCD_R; 458 | wire [11:0] gCCD_G; 459 | wire [11:0] gCCD_B; 460 | wire xCCD_DVAL; 461 | wire sCCD_DVAL1; 462 | wire sCCD_DVAL2; 463 | 464 | wire [11:0] mCCD_G; 465 | wire [11:0] sCCD_G1; 466 | wire [11:0] sCCD_G2; 467 | 468 | wire sdram_ctrl_clk; 469 | wire [9:0] oVGA_R; // VGA Red[9:0] 470 | wire [9:0] oVGA_G; // VGA Green[9:0] 471 | wire [9:0] oVGA_B; // VGA Blue[9:0] 472 | wire [7:0] ActivityGraph; 473 | 474 | //power on start 475 | wire auto_start; 476 | //======================================================= 477 | // Structural coding 478 | //======================================================= 479 | // D5M 480 | assign D5M_TRIGGER = 1'b1; // tRIGGER 481 | assign D5M_RESET_N = DLY_RST_1; 482 | assign VGA_CTRL_CLK = ~VGA_CLK; 483 | 484 | assign LEDR = SW; 485 | assign LEDG[7:0] = ActivityGraph; 486 | assign LEDG[8] = Y_Cont; 487 | assign UART_TXD = UART_RXD; 488 | 489 | //fetch the high 8 bits 490 | assign VGA_R = oVGA_R[9:2]; 491 | assign VGA_G = oVGA_G[9:2]; 492 | assign VGA_B = oVGA_B[9:2]; 493 | 494 | //D5M read 495 | always@(posedge D5M_PIXLCLK) 496 | begin 497 | rCCD_DATA <= D5M_D; 498 | rCCD_LVAL <= D5M_LVAL; 499 | rCCD_FVAL <= D5M_FVAL; 500 | end 501 | 502 | //auto start when power on 503 | assign auto_start = ((KEY[0])&&(DLY_RST_3)&&(!DLY_RST_4))? 1'b1:1'b0; 504 | //Reset module 505 | Reset_Delay u2 ( .iCLK(CLOCK2_50), 506 | .iRST(KEY[0]), 507 | .oRST_0(DLY_RST_0), 508 | .oRST_1(DLY_RST_1), 509 | .oRST_2(DLY_RST_2), 510 | .oRST_3(DLY_RST_3), 511 | .oRST_4(DLY_RST_4) 512 | ); 513 | //D5M image capture 514 | CCD_Capture u3 ( .oDATA(mCCD_DATA), 515 | .oDVAL(mCCD_DVAL), 516 | .oX_Cont(X_Cont), 517 | .oY_Cont(Y_Cont), 518 | .oFrame_Cont(Frame_Cont), 519 | .iDATA(rCCD_DATA), 520 | .iFVAL(rCCD_FVAL), 521 | .iLVAL(rCCD_LVAL), 522 | .iSTART(!KEY[3]|auto_start), 523 | .iEND(!KEY[2]), 524 | .iCLK(~D5M_PIXLCLK), 525 | .iRST(DLY_RST_2) 526 | ); 527 | //D5M raw data convert to RGB data 528 | RAW2RGB u4 ( .iCLK(D5M_PIXLCLK), 529 | .iRST(DLY_RST_1), 530 | .iDATA(mCCD_DATA), 531 | .iDVAL(mCCD_DVAL), 532 | .oRed(gCCD_R), 533 | .oGreen(gCCD_G), 534 | .oBlue(gCCD_B), 535 | .oDVAL(xCCD_DVAL), 536 | .iX_Cont(X_Cont), 537 | .iY_Cont(Y_Cont) 538 | ); 539 | // Convert RGB data to Grayscale 540 | RGB2GRAY u5 ( .iRed(gCCD_R), 541 | .iGreen(gCCD_G), 542 | .iBlue(gCCD_B), 543 | .oGray(mCCD_G) 544 | ); 545 | 546 | // Memory Multiplexer 547 | MEM_SWITCH u6 (.iGray(mCCD_G), 548 | .iFrameCount(Frame_Cont[0]), 549 | .iDVAL(xCCD_DVAL), 550 | .oGray1(sCCD_G1), 551 | .oGray2(sCCD_G2), 552 | .oDVAL1(sCCD_DVAL1), 553 | .oDVAL2(sCCD_DVAL2) 554 | ); 555 | 556 | //Frame count display 557 | SEG7_LUT_8 u7 ( .oSEG0(HEX0),.oSEG1(HEX1), 558 | .oSEG2(HEX2),.oSEG3(HEX3), 559 | .oSEG4(HEX4),.oSEG5(HEX5), 560 | .oSEG6(HEX6),.oSEG7(HEX7), 561 | .iDIG(Frame_Cont[31:0]) 562 | ); 563 | 564 | sdram_pll u8 ( 565 | .inclk0(CLOCK2_50), 566 | .c0(sdram_ctrl_clk), 567 | .c1(DRAM_CLK), 568 | .c2(D5M_XCLKIN), //25M 569 | `ifdef VGA_640x480p60 570 | .c3(VGA_CLK) //25M 571 | `else 572 | .c4(VGA_CLK) //40M 573 | `endif 574 | ); 575 | 576 | //SDRam Read and Write as Frame Buffer 577 | Sdram_Control u9 ( // HOST Side 578 | .RESET_N(KEY[0]), 579 | .CLK(sdram_ctrl_clk), 580 | 581 | // FIFO Write Side 1 582 | .WR1_DATA({4'b0,sCCD_G1[11:0]}), 583 | .WR1(sCCD_DVAL1), 584 | .WR1_ADDR(0), 585 | .WR1_MAX_ADDR(640*480/2), 586 | .WR1_LENGTH(8'h50), 587 | 588 | .WR1_LOAD(!DLY_RST_0), 589 | .WR1_CLK(D5M_PIXLCLK), 590 | 591 | // FIFO Write Side 2 592 | .WR2_DATA({4'b0,sCCD_G2[11:0]}), 593 | .WR2(sCCD_DVAL2), 594 | .WR2_ADDR(23'h100000), 595 | 596 | .WR2_MAX_ADDR(23'h100000+640*480/2), 597 | .WR2_LENGTH(8'h50), 598 | 599 | .WR2_LOAD(!DLY_RST_0), 600 | .WR2_CLK(D5M_PIXLCLK), 601 | 602 | // FIFO Read Side 1 603 | .RD1_DATA(Read_DATA1), 604 | .RD1(Read), 605 | .RD1_ADDR(0), 606 | 607 | .RD1_MAX_ADDR(640*480/2), 608 | .RD1_LENGTH(8'h50), 609 | 610 | .RD1_LOAD(!DLY_RST_0), 611 | .RD1_CLK(~VGA_CTRL_CLK), 612 | 613 | // FIFO Read Side 2 614 | .RD2_DATA(Read_DATA2), 615 | .RD2(Read), 616 | .RD2_ADDR(23'h100000), 617 | 618 | .RD2_MAX_ADDR(23'h100000+640*480/2), 619 | .RD2_LENGTH(8'h50), 620 | 621 | .RD2_LOAD(!DLY_RST_0), 622 | .RD2_CLK(~VGA_CTRL_CLK), 623 | 624 | // SDRAM Side 625 | .SA(DRAM_ADDR), 626 | .BA(DRAM_BA), 627 | .CS_N(DRAM_CS_N), 628 | .CKE(DRAM_CKE), 629 | .RAS_N(DRAM_RAS_N), 630 | .CAS_N(DRAM_CAS_N), 631 | .WE_N(DRAM_WE_N), 632 | .DQ(DRAM_DQ), 633 | .DQM(DRAM_DQM) 634 | ); 635 | 636 | //D5M I2C control 637 | I2C_CCD_Config u11 ( // Host Side 638 | .iCLK(CLOCK2_50), 639 | .iRST_N(DLY_RST_2), 640 | .iEXPOSURE_ADJ(KEY[1]), 641 | .iEXPOSURE_DEC_p(SW[17]), 642 | .iZOOM_MODE_SW(SW[16]), 643 | // I2C Side 644 | .I2C_SCLK(D5M_SCLK), 645 | .I2C_SDAT(D5M_SDATA) 646 | ); 647 | //VGA DISPLAY 648 | VGA_Controller u1 ( // Host Side 649 | .oRequest(Read), 650 | .iGrayMem1(Read_DATA1[11:2]), 651 | .iGrayMem2(Read_DATA2[11:2]), 652 | .iTrackMode(SW[9:0]), 653 | // VGA Side 654 | .oVGA_R(oVGA_R), 655 | .oVGA_G(oVGA_G), 656 | .oVGA_B(oVGA_B), 657 | .oVGA_H_SYNC(VGA_HS), 658 | .oVGA_V_SYNC(VGA_VS), 659 | .oVGA_SYNC(VGA_SYNC_N), 660 | .oVGA_BLANK(VGA_BLANK_N), 661 | // Control Signal 662 | .iCLK(VGA_CTRL_CLK), 663 | .iRST_N(DLY_RST_2), 664 | .iZOOM_MODE_SW(SW[16]), 665 | .oActivityGraph(ActivityGraph) 666 | ); 667 | 668 | endmodule 669 | -------------------------------------------------------------------------------- /Line_Buffer1.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/erosen/FPGA_Object_Tracking/4b8827eed9239223612c11d7db5ac8f344878a53/Line_Buffer1.qip -------------------------------------------------------------------------------- /Sdram_Control/Sdram_Control.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2010 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: Sdram Control Multi-Port 34 | // 35 | // -------------------------------------------------------------------- 36 | 37 | module Sdram_Control ( 38 | // HOST Side 39 | RESET_N, 40 | CLK, 41 | // FIFO Write Side 1 42 | WR1_DATA, 43 | WR1, 44 | WR1_ADDR, 45 | WR1_MAX_ADDR, 46 | WR1_LENGTH, 47 | WR1_LOAD, 48 | WR1_CLK, 49 | // FIFO Write Side 2 50 | WR2_DATA, 51 | WR2, 52 | WR2_ADDR, 53 | WR2_MAX_ADDR, 54 | WR2_LENGTH, 55 | WR2_LOAD, 56 | WR2_CLK, 57 | // FIFO Read Side 1 58 | RD1_DATA, 59 | RD1, 60 | RD1_ADDR, 61 | RD1_MAX_ADDR, 62 | RD1_LENGTH, 63 | RD1_LOAD, 64 | RD1_CLK, 65 | // FIFO Read Side 2 66 | RD2_DATA, 67 | RD2, 68 | RD2_ADDR, 69 | RD2_MAX_ADDR, 70 | RD2_LENGTH, 71 | RD2_LOAD, 72 | RD2_CLK, 73 | // SDRAM Side 74 | SA, 75 | BA, 76 | CS_N, 77 | CKE, 78 | RAS_N, 79 | CAS_N, 80 | WE_N, 81 | DQ, 82 | DQM 83 | ); 84 | 85 | 86 | //======================================================= 87 | // PARAMETER declarations 88 | //======================================================= 89 | `include "Sdram_Params.h" 90 | 91 | 92 | //======================================================= 93 | // PORT declarations 94 | //======================================================= 95 | // HOST Side 96 | input RESET_N; //System Reset 97 | input CLK; 98 | // FIFO Write Side 1 99 | input [`DIOSIZE-1:0] WR1_DATA; //Data Input 100 | input WR1; //Write Request 101 | input [`ASIZE-1:0] WR1_ADDR; //Write Start Address 102 | input [`ASIZE-1:0] WR1_MAX_ADDR; //Write Max Address 103 | input [7:0] WR1_LENGTH; //Write Length 104 | input WR1_LOAD; //Write FIFO Clear 105 | input WR1_CLK; //Write FIFO Clock 106 | // FIFO Write Side 2 107 | input [`DIOSIZE-1:0] WR2_DATA; //Data Input 108 | input WR2; //Write Request 109 | input [`ASIZE-1:0] WR2_ADDR; //Write Start Address 110 | input [`ASIZE-1:0] WR2_MAX_ADDR; //Write Max Address 111 | input [7:0] WR2_LENGTH; //Write Length 112 | input WR2_LOAD; //Write FIFO Clear 113 | input WR2_CLK; //Write FIFO Clock 114 | // FIFO Read Side 1 115 | output [`DIOSIZE-1:0] RD1_DATA; //Data Output 116 | input RD1; //Read Request 117 | input [`ASIZE-1:0] RD1_ADDR; //Read Start Address 118 | input [`ASIZE-1:0] RD1_MAX_ADDR; //Read Max Address 119 | input [7:0] RD1_LENGTH; //Read Length 120 | input RD1_LOAD; //Read FIFO Clear 121 | input RD1_CLK; //Read FIFO Clock 122 | // FIFO Read Side 2 123 | output [`DIOSIZE-1:0] RD2_DATA; //Data Output 124 | input RD2; //Read Request 125 | input [`ASIZE-1:0] RD2_ADDR; //Read Start Address 126 | input [`ASIZE-1:0] RD2_MAX_ADDR; //Read Max Address 127 | input [7:0] RD2_LENGTH; //Read Length 128 | input RD2_LOAD; //Read FIFO Clear 129 | input RD2_CLK; //Read FIFO Clock 130 | // SDRAM Side 131 | output [11:0] SA; //SDRAM address output 132 | output [1:0] BA; //SDRAM bank address 133 | output [1:0] CS_N; //SDRAM Chip Selects 134 | output CKE; //SDRAM clock enable 135 | output RAS_N; //SDRAM Row address Strobe 136 | output CAS_N; //SDRAM Column address Strobe 137 | output WE_N; //SDRAM write enable 138 | inout [`DSIZE-1:0] DQ; //SDRAM data bus 139 | output [`DSIZE/8-1:0] DQM; //SDRAM data mask lines 140 | 141 | 142 | 143 | //======================================================= 144 | // Signal Declarations 145 | //======================================================= 146 | // Controller 147 | reg [`ASIZE-1:0] mADDR; //Internal address 148 | reg [7:0] mLENGTH; //Internal length 149 | reg [`ASIZE-1:0] rWR1_ADDR; //Register write address 150 | reg [`ASIZE-1:0] rWR1_MAX_ADDR; //Register max write address 151 | reg [7:0] rWR1_LENGTH; //Register write length 152 | reg [`ASIZE-1:0] rWR2_ADDR; //Register write address 153 | reg [`ASIZE-1:0] rWR2_MAX_ADDR; //Register max write address 154 | reg [7:0] rWR2_LENGTH; //Register write length 155 | reg [`ASIZE-1:0] rRD1_ADDR; //Register read address 156 | reg [`ASIZE-1:0] rRD1_MAX_ADDR; //Register max read address 157 | reg [7:0] rRD1_LENGTH; //Register read length 158 | reg [`ASIZE-1:0] rRD2_ADDR; //Register read address 159 | reg [`ASIZE-1:0] rRD2_MAX_ADDR; //Register max read address 160 | reg [7:0] rRD2_LENGTH; //Register read length 161 | reg [1:0] WR_MASK; //Write port active mask 162 | reg [1:0] RD_MASK; //Read port active mask 163 | reg mWR_DONE; //Flag write done, 1 pulse SDR_CLK 164 | reg mRD_DONE; //Flag read done, 1 pulse SDR_CLK 165 | reg mWR,Pre_WR; //Internal WR edge capture 166 | reg mRD,Pre_RD; //Internal RD edge capture 167 | reg [9:0] ST; //Controller status 168 | reg [1:0] CMD; //Controller command 169 | reg PM_STOP; //Flag page mode stop 170 | reg PM_DONE; //Flag page mode done 171 | reg Read; //Flag read active 172 | reg Write; //Flag write active 173 | reg [`DSIZE-1:0] mDATAOUT; //Controller Data output 174 | wire [`DSIZE-1:0] mDATAIN; //Controller Data input 175 | wire [`DSIZE-1:0] mDATAIN1; //Controller Data input 1 176 | wire [`DSIZE-1:0] mDATAIN2; //Controller Data input 2 177 | wire CMDACK; //Controller command acknowledgement 178 | // DRAM Control 179 | reg [`DSIZE/8-1:0] DQM; //SDRAM data mask lines 180 | reg [11:0] SA; //SDRAM address output 181 | reg [1:0] BA; //SDRAM bank address 182 | reg [1:0] CS_N; //SDRAM Chip Selects 183 | reg CKE; //SDRAM clock enable 184 | reg RAS_N; //SDRAM Row address Strobe 185 | reg CAS_N; //SDRAM Column address Strobe 186 | reg WE_N; //SDRAM write enable 187 | wire [`DSIZE-1:0] DQOUT; //SDRAM data out link 188 | wire [`DSIZE/8-1:0] IDQM; //SDRAM data mask lines 189 | wire [11:0] ISA; //SDRAM address output 190 | wire [1:0] IBA; //SDRAM bank address 191 | wire [1:0] ICS_N; //SDRAM Chip Selects 192 | wire ICKE; //SDRAM clock enable 193 | wire IRAS_N; //SDRAM Row address Strobe 194 | wire ICAS_N; //SDRAM Column address Strobe 195 | wire IWE_N; //SDRAM write enable 196 | // FIFO Control 197 | reg OUT_VALID; //Output data request to read side fifo 198 | reg IN_REQ; //Input data request to write side fifo 199 | wire [7:0] write_side_fifo_rusedw1; 200 | wire [7:0] write_side_fifo_rusedw2; 201 | wire [7:0] read_side_fifo_wusedw1; 202 | wire [7:0] read_side_fifo_wusedw2; 203 | // DRAM Internal Control 204 | wire [`ASIZE-1:0] saddr; 205 | wire load_mode; 206 | wire nop; 207 | wire reada; 208 | wire writea; 209 | wire refresh; 210 | wire precharge; 211 | wire oe; 212 | wire ref_ack; 213 | wire ref_req; 214 | wire init_req; 215 | wire cm_ack; 216 | wire active; 217 | 218 | 219 | 220 | //======================================================= 221 | // Sub-module 222 | //======================================================= 223 | control_interface u_control_interface ( 224 | .CLK(CLK), 225 | .RESET_N(RESET_N), 226 | .CMD(CMD), 227 | .ADDR(mADDR), 228 | .REF_ACK(ref_ack), 229 | .CM_ACK(cm_ack), 230 | .NOP(nop), 231 | .READA(reada), 232 | .WRITEA(writea), 233 | .REFRESH(refresh), 234 | .PRECHARGE(precharge), 235 | .LOAD_MODE(load_mode), 236 | .SADDR(saddr), 237 | .REF_REQ(ref_req), 238 | .INIT_REQ(init_req), 239 | .CMD_ACK(CMDACK) ); 240 | 241 | command u_command ( 242 | .CLK(CLK), 243 | .RESET_N(RESET_N), 244 | .SADDR(saddr), 245 | .NOP(nop), 246 | .READA(reada), 247 | .WRITEA(writea), 248 | .REFRESH(refresh), 249 | .LOAD_MODE(load_mode), 250 | .PRECHARGE(precharge), 251 | .REF_REQ(ref_req), 252 | .INIT_REQ(init_req), 253 | .REF_ACK(ref_ack), 254 | .CM_ACK(cm_ack), 255 | .OE(oe), 256 | .PM_STOP(PM_STOP), 257 | .PM_DONE(PM_DONE), 258 | .SA(ISA), 259 | .BA(IBA), 260 | .CS_N(ICS_N), 261 | .CKE(ICKE), 262 | .RAS_N(IRAS_N), 263 | .CAS_N(ICAS_N), 264 | .WE_N(IWE_N) ); 265 | 266 | sdr_data_path u_sdr_data_path ( 267 | .CLK(CLK), 268 | .RESET_N(RESET_N), 269 | .DATAIN(mDATAIN), 270 | .DM(2'b00), 271 | .DQOUT(DQOUT), 272 | .DQM(IDQM) ); 273 | 274 | Sdram_WR_FIFO u_write1_fifo ( 275 | .data(WR1_DATA), 276 | .wrreq(WR1), 277 | .wrclk(WR1_CLK), 278 | .aclr(WR1_LOAD), 279 | .rdreq(IN_REQ&&WR_MASK[0]), 280 | .rdclk(CLK), 281 | .q(mDATAIN1), 282 | .rdusedw(write_side_fifo_rusedw1) ); 283 | 284 | Sdram_WR_FIFO u_write2_fifo ( 285 | .data(WR2_DATA), 286 | .wrreq(WR2), 287 | .wrclk(WR2_CLK), 288 | .aclr(WR2_LOAD), 289 | .rdreq(IN_REQ&&WR_MASK[1]), 290 | .rdclk(CLK), 291 | .q(mDATAIN2), 292 | .rdusedw(write_side_fifo_rusedw2) ); 293 | 294 | Sdram_RD_FIFO u_read1_fifo ( 295 | .data(mDATAOUT), 296 | .wrreq(OUT_VALID&&RD_MASK[0]), 297 | .wrclk(CLK), 298 | .aclr(RD1_LOAD), 299 | .rdreq(RD1), 300 | .rdclk(RD1_CLK), 301 | .q(RD1_DATA), 302 | .wrusedw(read_side_fifo_wusedw1) ); 303 | 304 | Sdram_RD_FIFO u_read2_fifo ( 305 | .data(mDATAOUT), 306 | .wrreq(OUT_VALID&&RD_MASK[1]), 307 | .wrclk(CLK), 308 | .aclr(RD2_LOAD), 309 | .rdreq(RD2), 310 | .rdclk(RD2_CLK), 311 | .q(RD2_DATA), 312 | .wrusedw(read_side_fifo_wusedw2) ); 313 | 314 | 315 | 316 | //======================================================= 317 | // Structural coding 318 | //======================================================= 319 | assign mDATAIN = (WR_MASK[0]) ? mDATAIN1 : mDATAIN2; 320 | assign DQ = oe ? DQOUT : `DSIZE'hzzzz; 321 | assign active = Read | Write; 322 | 323 | 324 | 325 | always @ (posedge CLK) 326 | begin 327 | SA <= (ST==SC_CL+mLENGTH) ? 12'h200 : ISA; 328 | BA <= IBA; 329 | CS_N <= ICS_N; 330 | CKE <= ICKE; 331 | RAS_N <= (ST==SC_CL+mLENGTH) ? 1'b0 : IRAS_N; 332 | CAS_N <= (ST==SC_CL+mLENGTH) ? 1'b1 : ICAS_N; 333 | WE_N <= (ST==SC_CL+mLENGTH) ? 1'b0 : IWE_N; 334 | PM_STOP <= (ST==SC_CL+mLENGTH) ? 1'b1 : 1'b0; 335 | PM_DONE <= (ST==SC_CL+SC_RCD+mLENGTH+2) ? 1'b1 : 1'b0; 336 | DQM <= (active && (ST>=SC_CL) ) ? (((ST==SC_CL+mLENGTH) && Write)? 4'b1111 : 4'b0 ) : 4'b1111; 337 | mDATAOUT<= DQ; 338 | end 339 | 340 | always@(posedge CLK or negedge RESET_N) 341 | begin 342 | if(!RESET_N) 343 | begin 344 | CMD <= 0; 345 | ST <= 0; 346 | Pre_RD <= 0; 347 | Pre_WR <= 0; 348 | Read <= 0; 349 | Write <= 0; 350 | OUT_VALID <= 0; 351 | IN_REQ <= 0; 352 | mWR_DONE <= 0; 353 | mRD_DONE <= 0; 354 | end 355 | else 356 | begin 357 | Pre_RD <= mRD; 358 | Pre_WR <= mWR; 359 | case (ST) 360 | 0: begin 361 | if (!Pre_RD && mRD) 362 | begin 363 | Read <= 1; 364 | Write <= 0; 365 | CMD <= 2'b01; 366 | ST <= 1; 367 | end 368 | else if (!Pre_WR && mWR) 369 | begin 370 | Read <= 0; 371 | Write <= 1; 372 | CMD <= 2'b10; 373 | ST <= 1; 374 | end 375 | end 376 | 1: begin 377 | if (CMDACK) 378 | begin 379 | CMD <= 2'b00; 380 | ST <= 2; 381 | end 382 | end 383 | default: begin 384 | if (ST!=SC_CL+SC_RCD+mLENGTH+1) 385 | ST <= ST+1; 386 | else 387 | ST <= 0; 388 | end 389 | endcase 390 | 391 | if (Read) 392 | begin 393 | if (ST==SC_CL+SC_RCD+1) 394 | OUT_VALID <= 1; 395 | else if (ST==SC_CL+SC_RCD+mLENGTH+1) 396 | begin 397 | OUT_VALID <= 0; 398 | Read <= 0; 399 | mRD_DONE <= 1; 400 | end 401 | end 402 | else 403 | mRD_DONE <= 0; 404 | 405 | if (Write) 406 | begin 407 | if (ST==SC_CL-1) 408 | IN_REQ <= 1; 409 | else if (ST==SC_CL+mLENGTH-1) 410 | IN_REQ <= 0; 411 | else if (ST==SC_CL+SC_RCD+mLENGTH) 412 | begin 413 | Write <= 0; 414 | mWR_DONE<= 1; 415 | end 416 | end 417 | else 418 | mWR_DONE <= 0; 419 | end 420 | end 421 | 422 | // Internal Address & Length Control 423 | always@(posedge CLK or negedge RESET_N) 424 | if (!RESET_N) 425 | begin 426 | rWR1_ADDR <= WR1_ADDR; 427 | rWR2_ADDR <= WR2_ADDR; 428 | rRD1_ADDR <= RD1_ADDR; 429 | rRD2_ADDR <= RD2_ADDR; 430 | rWR1_MAX_ADDR <= WR1_MAX_ADDR; 431 | rWR2_MAX_ADDR <= WR2_MAX_ADDR; 432 | rRD1_MAX_ADDR <= RD1_MAX_ADDR; 433 | rRD2_MAX_ADDR <= RD2_MAX_ADDR; 434 | 435 | rWR1_LENGTH <= WR1_LENGTH; 436 | rWR2_LENGTH <= WR2_LENGTH; 437 | rRD1_LENGTH <= RD1_LENGTH; 438 | rRD2_LENGTH <= RD2_LENGTH; 439 | end 440 | else 441 | begin 442 | // Write Side 1 443 | if (mWR_DONE&&WR_MASK[0]) 444 | begin 445 | if(rWR1_ADDR= rWR1_LENGTH) && (rWR1_LENGTH!=0) ) 496 | begin 497 | mADDR <= rWR1_ADDR; 498 | mLENGTH <= rWR1_LENGTH; 499 | WR_MASK <= 2'b01; 500 | RD_MASK <= 2'b00; 501 | mWR <= 1; 502 | mRD <= 0; 503 | end 504 | // Write Side 2 505 | else if ( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH!=0) ) 506 | begin 507 | mADDR <= rWR2_ADDR; 508 | mLENGTH <= rWR2_LENGTH; 509 | WR_MASK <= 2'b10; 510 | RD_MASK <= 2'b00; 511 | mWR <= 1; 512 | mRD <= 0; 513 | end 514 | // Read Side 1 515 | else if ( (read_side_fifo_wusedw1 < rRD1_LENGTH) ) 516 | begin 517 | mADDR <= rRD1_ADDR; 518 | mLENGTH <= rRD1_LENGTH; 519 | WR_MASK <= 2'b00; 520 | RD_MASK <= 2'b01; 521 | mWR <= 0; 522 | mRD <= 1; 523 | end 524 | // Read Side 2 525 | else if ( (read_side_fifo_wusedw2 < rRD2_LENGTH) ) 526 | begin 527 | mADDR <= rRD2_ADDR; 528 | mLENGTH <= rRD2_LENGTH; 529 | WR_MASK <= 2'b00; 530 | RD_MASK <= 2'b10; 531 | mWR <= 0; 532 | mRD <= 1; 533 | end 534 | end 535 | 536 | if (mWR_DONE) 537 | begin 538 | WR_MASK <= 0; 539 | mWR <= 0; 540 | end 541 | 542 | if (mRD_DONE) 543 | begin 544 | RD_MASK <= 0; 545 | mRD <= 0; 546 | end 547 | end 548 | 549 | 550 | endmodule 551 | -------------------------------------------------------------------------------- /Sdram_Control/Sdram_Params.h: -------------------------------------------------------------------------------- 1 | // Address Space Parameters 2 | 3 | `define ROWSTART 8 4 | `define ROWSIZE 12 5 | `define COLSTART 0 6 | `define COLSIZE 8 7 | `define BANKSTART 20 8 | `define BANKSIZE 2 9 | 10 | // Address and Data Bus Sizes 11 | 12 | `define ASIZE 23 // total address width of the SDRAM 13 | `define DSIZE 32 // Width of data bus to SDRAMS 14 | `define DIOSIZE 16 // Width of data bus in/out SDRAM Controller 15 | 16 | //parameter INIT_PER = 100; // For Simulation 17 | 18 | // Controller Parameter 19 | //////////// 133 MHz /////////////// 20 | /* 21 | parameter INIT_PER = 32000; 22 | parameter REF_PER = 1536; 23 | parameter SC_CL = 3; 24 | parameter SC_RCD = 3; 25 | parameter SC_RRD = 7; 26 | parameter SC_PM = 1; 27 | parameter SC_BL = 1; 28 | */ 29 | /////////////////////////////////////// 30 | //////////// 100 MHz /////////////// 31 | parameter INIT_PER = 24000; 32 | parameter REF_PER = 1024; 33 | parameter SC_CL = 3; 34 | parameter SC_RCD = 3; 35 | parameter SC_RRD = 7; 36 | parameter SC_PM = 1; 37 | parameter SC_BL = 1; 38 | /////////////////////////////////////// 39 | //////////// 50 MHz /////////////// 40 | /* 41 | parameter INIT_PER = 12000; 42 | parameter REF_PER = 512; 43 | parameter SC_CL = 3; 44 | parameter SC_RCD = 3; 45 | parameter SC_RRD = 7; 46 | parameter SC_PM = 1; 47 | parameter SC_BL = 1; 48 | */ 49 | /////////////////////////////////////// 50 | 51 | // SDRAM Parameter 52 | parameter SDR_BL = (SC_PM == 1) ? 3'b111 : 53 | (SC_BL == 1) ? 3'b000 : 54 | (SC_BL == 2) ? 3'b001 : 55 | (SC_BL == 4) ? 3'b010 : 3'b011; 56 | parameter SDR_BT = 1'b0; // 1'b0 : Sequential 1'b1 : Interteave 57 | parameter SDR_CL = (SC_CL == 2) ? 3'b10 : 3'b11; -------------------------------------------------------------------------------- /Sdram_Control/Sdram_RD_FIFO.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_RD_FIFO.v"] 4 | -------------------------------------------------------------------------------- /Sdram_Control/Sdram_RD_FIFO.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo_mixed_widths 5 | 6 | // ============================================================ 7 | // File Name: Sdram_RD_FIFO.v 8 | // Megafunction Name(s): 9 | // dcfifo_mixed_widths 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module Sdram_RD_FIFO ( 40 | aclr, 41 | data, 42 | rdclk, 43 | rdreq, 44 | wrclk, 45 | wrreq, 46 | q, 47 | wrusedw); 48 | 49 | input aclr; 50 | input [31:0] data; 51 | input rdclk; 52 | input rdreq; 53 | input wrclk; 54 | input wrreq; 55 | output [15:0] q; 56 | output [7:0] wrusedw; 57 | `ifndef ALTERA_RESERVED_QIS 58 | // synopsys translate_off 59 | `endif 60 | tri0 aclr; 61 | `ifndef ALTERA_RESERVED_QIS 62 | // synopsys translate_on 63 | `endif 64 | 65 | wire [15:0] sub_wire0; 66 | wire [7:0] sub_wire1; 67 | wire [15:0] q = sub_wire0[15:0]; 68 | wire [7:0] wrusedw = sub_wire1[7:0]; 69 | 70 | dcfifo_mixed_widths dcfifo_mixed_widths_component ( 71 | .aclr (aclr), 72 | .data (data), 73 | .rdclk (rdclk), 74 | .rdreq (rdreq), 75 | .wrclk (wrclk), 76 | .wrreq (wrreq), 77 | .q (sub_wire0), 78 | .wrusedw (sub_wire1), 79 | .rdempty (), 80 | .rdfull (), 81 | .rdusedw (), 82 | .wrempty (), 83 | .wrfull ()); 84 | defparam 85 | dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E", 86 | dcfifo_mixed_widths_component.lpm_numwords = 256, 87 | dcfifo_mixed_widths_component.lpm_showahead = "OFF", 88 | dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths", 89 | dcfifo_mixed_widths_component.lpm_width = 32, 90 | dcfifo_mixed_widths_component.lpm_widthu = 8, 91 | dcfifo_mixed_widths_component.lpm_widthu_r = 9, 92 | dcfifo_mixed_widths_component.lpm_width_r = 16, 93 | dcfifo_mixed_widths_component.overflow_checking = "ON", 94 | dcfifo_mixed_widths_component.rdsync_delaypipe = 4, 95 | dcfifo_mixed_widths_component.read_aclr_synch = "OFF", 96 | dcfifo_mixed_widths_component.underflow_checking = "ON", 97 | dcfifo_mixed_widths_component.use_eab = "ON", 98 | dcfifo_mixed_widths_component.write_aclr_synch = "OFF", 99 | dcfifo_mixed_widths_component.wrsync_delaypipe = 4; 100 | 101 | 102 | endmodule 103 | 104 | // ============================================================ 105 | // CNX file retrieval info 106 | // ============================================================ 107 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 108 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 109 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 110 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 111 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 112 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 113 | // Retrieval info: PRIVATE: Depth NUMERIC "256" 114 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 115 | // Retrieval info: PRIVATE: Full NUMERIC "1" 116 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 117 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 118 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" 119 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 120 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 121 | // Retrieval info: PRIVATE: Optimize NUMERIC "1" 122 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 123 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 124 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 125 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 126 | // Retrieval info: PRIVATE: Width NUMERIC "32" 127 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 128 | // Retrieval info: PRIVATE: diff_widths NUMERIC "1" 129 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 130 | // Retrieval info: PRIVATE: output_width NUMERIC "16" 131 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "0" 132 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 133 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" 134 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 135 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 136 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 137 | // Retrieval info: PRIVATE: wsFull NUMERIC "0" 138 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" 139 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 140 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 141 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256" 142 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" 143 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths" 144 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" 145 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8" 146 | // Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9" 147 | // Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16" 148 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 149 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 150 | // Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" 151 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 152 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 153 | // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" 154 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 155 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" 156 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 157 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 158 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" 159 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 160 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" 161 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 162 | // Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]" 163 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 164 | // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 165 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 166 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 167 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 168 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 169 | // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 170 | // Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.v TRUE 172 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.inc FALSE 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.cmp FALSE 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO.bsf FALSE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_inst.v FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_bb.v FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_waveforms.html FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_RD_FIFO_wave*.jpg FALSE 179 | -------------------------------------------------------------------------------- /Sdram_Control/Sdram_WR_FIFO.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_WR_FIFO.v"] 4 | -------------------------------------------------------------------------------- /Sdram_Control/Sdram_WR_FIFO.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo_mixed_widths 5 | 6 | // ============================================================ 7 | // File Name: Sdram_WR_FIFO.v 8 | // Megafunction Name(s): 9 | // dcfifo_mixed_widths 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 9.1 Build 350 03/24/2010 SP 2 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2010 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module Sdram_WR_FIFO ( 40 | aclr, 41 | data, 42 | rdclk, 43 | rdreq, 44 | wrclk, 45 | wrreq, 46 | q, 47 | rdusedw); 48 | 49 | input aclr; 50 | input [15:0] data; 51 | input rdclk; 52 | input rdreq; 53 | input wrclk; 54 | input wrreq; 55 | output [31:0] q; 56 | output [7:0] rdusedw; 57 | `ifndef ALTERA_RESERVED_QIS 58 | // synopsys translate_off 59 | `endif 60 | tri0 aclr; 61 | `ifndef ALTERA_RESERVED_QIS 62 | // synopsys translate_on 63 | `endif 64 | 65 | wire [31:0] sub_wire0; 66 | wire [7:0] sub_wire1; 67 | wire [31:0] q = sub_wire0[31:0]; 68 | wire [7:0] rdusedw = sub_wire1[7:0]; 69 | 70 | dcfifo_mixed_widths dcfifo_mixed_widths_component ( 71 | .wrclk (wrclk), 72 | .rdreq (rdreq), 73 | .aclr (aclr), 74 | .rdclk (rdclk), 75 | .wrreq (wrreq), 76 | .data (data), 77 | .q (sub_wire0), 78 | .rdusedw (sub_wire1) 79 | // synopsys translate_off 80 | , 81 | .rdempty (), 82 | .rdfull (), 83 | .wrempty (), 84 | .wrfull (), 85 | .wrusedw () 86 | // synopsys translate_on 87 | ); 88 | defparam 89 | dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E", 90 | dcfifo_mixed_widths_component.lpm_numwords = 512, 91 | dcfifo_mixed_widths_component.lpm_showahead = "OFF", 92 | dcfifo_mixed_widths_component.lpm_type = "dcfifo", 93 | dcfifo_mixed_widths_component.lpm_width = 16, 94 | dcfifo_mixed_widths_component.lpm_widthu = 9, 95 | dcfifo_mixed_widths_component.lpm_widthu_r = 8, 96 | dcfifo_mixed_widths_component.lpm_width_r = 32, 97 | dcfifo_mixed_widths_component.overflow_checking = "ON", 98 | dcfifo_mixed_widths_component.rdsync_delaypipe = 4, 99 | dcfifo_mixed_widths_component.underflow_checking = "ON", 100 | dcfifo_mixed_widths_component.use_eab = "ON", 101 | dcfifo_mixed_widths_component.write_aclr_synch = "OFF", 102 | dcfifo_mixed_widths_component.wrsync_delaypipe = 4; 103 | 104 | 105 | endmodule 106 | 107 | // ============================================================ 108 | // CNX file retrieval info 109 | // ============================================================ 110 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 111 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 112 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 113 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 114 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 115 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 116 | // Retrieval info: PRIVATE: Depth NUMERIC "512" 117 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 118 | // Retrieval info: PRIVATE: Full NUMERIC "1" 119 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 120 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 121 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" 122 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 123 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 124 | // Retrieval info: PRIVATE: Optimize NUMERIC "1" 125 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 126 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 127 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 128 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 129 | // Retrieval info: PRIVATE: Width NUMERIC "16" 130 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" 131 | // Retrieval info: PRIVATE: diff_widths NUMERIC "1" 132 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 133 | // Retrieval info: PRIVATE: output_width NUMERIC "32" 134 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "0" 135 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 136 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "1" 137 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 138 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 139 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 140 | // Retrieval info: PRIVATE: wsFull NUMERIC "0" 141 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" 142 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 143 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" 144 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" 145 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 146 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" 147 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" 148 | // Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8" 149 | // Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32" 150 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 151 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 152 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 153 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 154 | // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" 155 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 156 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr 157 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] 158 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] 159 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk 160 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq 161 | // Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0] 162 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk 163 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq 164 | // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 165 | // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 166 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 167 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 168 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 169 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 170 | // Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0 171 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 172 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.v TRUE 174 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.inc FALSE 175 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.cmp FALSE 176 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO.bsf FALSE 177 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_inst.v FALSE 178 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_bb.v FALSE 179 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_waveforms.html FALSE 180 | // Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_WR_FIFO_wave*.jpg FALSE 181 | // Retrieval info: LIB_FILE: altera_mf 182 | -------------------------------------------------------------------------------- /Sdram_Control/command.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2008 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: command 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny Fan :| 08/04/22 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | 43 | module command( 44 | CLK, 45 | RESET_N, 46 | SADDR, 47 | NOP, 48 | READA, 49 | WRITEA, 50 | REFRESH, 51 | PRECHARGE, 52 | LOAD_MODE, 53 | REF_REQ, 54 | INIT_REQ, 55 | PM_STOP, 56 | PM_DONE, 57 | REF_ACK, 58 | CM_ACK, 59 | OE, 60 | SA, 61 | BA, 62 | CS_N, 63 | CKE, 64 | RAS_N, 65 | CAS_N, 66 | WE_N 67 | ); 68 | 69 | `include "Sdram_Params.h" 70 | 71 | input CLK; // System Clock 72 | input RESET_N; // System Reset 73 | input [`ASIZE-1:0] SADDR; // Address 74 | input NOP; // Decoded NOP command 75 | input READA; // Decoded READA command 76 | input WRITEA; // Decoded WRITEA command 77 | input REFRESH; // Decoded REFRESH command 78 | input PRECHARGE; // Decoded PRECHARGE command 79 | input LOAD_MODE; // Decoded LOAD_MODE command 80 | input REF_REQ; // Hidden refresh request 81 | input INIT_REQ; // Hidden initial request 82 | input PM_STOP; // Page mode stop 83 | input PM_DONE; // Page mode done 84 | output REF_ACK; // Refresh request acknowledge 85 | output CM_ACK; // Command acknowledge 86 | output OE; // OE signal for data path module 87 | output [11:0] SA; // SDRAM address 88 | output [1:0] BA; // SDRAM bank address 89 | output [1:0] CS_N; // SDRAM chip selects 90 | output CKE; // SDRAM clock enable 91 | output RAS_N; // SDRAM RAS 92 | output CAS_N; // SDRAM CAS 93 | output WE_N; // SDRAM WE_N 94 | 95 | reg CM_ACK; 96 | reg REF_ACK; 97 | reg OE; 98 | reg [11:0] SA; 99 | reg [1:0] BA; 100 | reg [1:0] CS_N; 101 | reg CKE; 102 | reg RAS_N; 103 | reg CAS_N; 104 | reg WE_N; 105 | 106 | // Internal signals 107 | reg do_reada; 108 | reg do_writea; 109 | reg do_refresh; 110 | reg do_precharge; 111 | reg do_load_mode; 112 | reg do_initial; 113 | reg command_done; 114 | reg [7:0] command_delay; 115 | reg [1:0] rw_shift; 116 | reg do_act; 117 | reg rw_flag; 118 | reg do_rw; 119 | reg [6:0] oe_shift; 120 | reg oe1; 121 | reg oe2; 122 | reg oe3; 123 | reg oe4; 124 | reg [3:0] rp_shift; 125 | reg rp_done; 126 | reg ex_read; 127 | reg ex_write; 128 | 129 | wire [`ROWSIZE - 1:0] rowaddr; 130 | wire [`COLSIZE - 1:0] coladdr; 131 | wire [`BANKSIZE - 1:0] bankaddr; 132 | 133 | assign rowaddr = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART]; // assignment of the row address bits from SADDR 134 | assign coladdr = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART]; // assignment of the column address bits 135 | assign bankaddr = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART]; // assignment of the bank address bits 136 | 137 | // This always block monitors the individual command lines and issues a command 138 | // to the next stage if there currently another command already running. 139 | always @(posedge CLK or negedge RESET_N) 140 | begin 141 | if (RESET_N == 0) 142 | begin 143 | do_reada <= 0; 144 | do_writea <= 0; 145 | do_refresh <= 0; 146 | do_precharge <= 0; 147 | do_load_mode <= 0; 148 | do_initial <= 0; 149 | command_done <= 0; 150 | command_delay <= 0; 151 | rw_flag <= 0; 152 | rp_shift <= 0; 153 | rp_done <= 0; 154 | ex_read <= 0; 155 | ex_write <= 0; 156 | end 157 | 158 | else 159 | begin 160 | 161 | // Issue the appropriate command if the sdram is not currently busy 162 | if( INIT_REQ == 1 ) 163 | begin 164 | do_reada <= 0; 165 | do_writea <= 0; 166 | do_refresh <= 0; 167 | do_precharge <= 0; 168 | do_load_mode <= 0; 169 | do_initial <= 1; 170 | command_done <= 0; 171 | command_delay <= 0; 172 | rw_flag <= 0; 173 | rp_shift <= 0; 174 | rp_done <= 0; 175 | ex_read <= 0; 176 | ex_write <= 0; 177 | end 178 | else 179 | begin 180 | do_initial <= 0; 181 | 182 | if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0 // Refresh 183 | & do_reada == 0 & do_writea == 0) 184 | do_refresh <= 1; 185 | else 186 | do_refresh <= 0; 187 | 188 | if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0)) // READA 189 | begin 190 | do_reada <= 1; 191 | ex_read <= 1; 192 | end 193 | else 194 | do_reada <= 0; 195 | 196 | if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0)) // WRITEA 197 | begin 198 | do_writea <= 1; 199 | ex_write <= 1; 200 | end 201 | else 202 | do_writea <= 0; 203 | 204 | if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0)) // PRECHARGE 205 | do_precharge <= 1; 206 | else 207 | do_precharge <= 0; 208 | 209 | if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0)) // LOADMODE 210 | do_load_mode <= 1; 211 | else 212 | do_load_mode <= 0; 213 | 214 | // set command_delay shift register and command_done flag 215 | // The command delay shift register is a timer that is used to ensure that 216 | // the SDRAM devices have had sufficient time to finish the last command. 217 | 218 | if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1) 219 | | (do_load_mode == 1)) 220 | begin 221 | command_delay <= 8'b11111111; 222 | command_done <= 1; 223 | rw_flag <= do_reada; 224 | end 225 | 226 | else 227 | begin 228 | command_done <= command_delay[0]; // the command_delay shift operation 229 | command_delay <= (command_delay>>1); 230 | end 231 | 232 | 233 | // start additional timer that is used for the refresh, writea, reada commands 234 | if (command_delay[0] == 0 & command_done == 1) 235 | begin 236 | rp_shift <= 4'b1111; 237 | rp_done <= 1; 238 | end 239 | else 240 | begin 241 | if(SC_PM == 0) 242 | begin 243 | rp_shift <= (rp_shift>>1); 244 | rp_done <= rp_shift[0]; 245 | end 246 | else 247 | begin 248 | if( (ex_read == 0) && (ex_write == 0) ) 249 | begin 250 | rp_shift <= (rp_shift>>1); 251 | rp_done <= rp_shift[0]; 252 | end 253 | else 254 | begin 255 | if( PM_STOP==1 ) 256 | begin 257 | rp_shift <= (rp_shift>>1); 258 | rp_done <= rp_shift[0]; 259 | ex_read <= 1'b0; 260 | ex_write <= 1'b0; 261 | end 262 | end 263 | end 264 | end 265 | end 266 | end 267 | end 268 | 269 | 270 | // logic that generates the OE signal for the data path module 271 | // For normal burst write he duration of OE is dependent on the configured burst length. 272 | // For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command 273 | // and is left on until a PRECHARGE(page burst terminate) is detected. 274 | // 275 | always @(posedge CLK or negedge RESET_N) 276 | begin 277 | if (RESET_N == 0) 278 | begin 279 | oe_shift <= 0; 280 | oe1 <= 0; 281 | oe2 <= 0; 282 | OE <= 0; 283 | end 284 | else 285 | begin 286 | if (SC_PM == 0) 287 | begin 288 | if (do_writea == 1) 289 | begin 290 | if (SC_BL == 1) // Set the shift register to the appropriate 291 | oe_shift <= 0; // value based on burst length. 292 | else if (SC_BL == 2) 293 | oe_shift <= 1; 294 | else if (SC_BL == 4) 295 | oe_shift <= 7; 296 | else if (SC_BL == 8) 297 | oe_shift <= 127; 298 | oe1 <= 1; 299 | end 300 | else 301 | begin 302 | oe_shift <= (oe_shift>>1); 303 | oe1 <= oe_shift[0]; 304 | oe2 <= oe1; 305 | oe3 <= oe2; 306 | oe4 <= oe3; 307 | if (SC_RCD == 2) 308 | OE <= oe3; 309 | else 310 | OE <= oe4; 311 | end 312 | end 313 | else 314 | begin 315 | if (do_writea == 1) // OE generation for page mode accesses 316 | oe4 <= 1; 317 | else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 ) 318 | oe4 <= 0; 319 | OE <= oe4; 320 | end 321 | 322 | end 323 | end 324 | 325 | 326 | 327 | 328 | // This always block tracks the time between the activate command and the 329 | // subsequent WRITEA or READA command, RC. The shift register is set using 330 | // the configuration register setting SC_RCD. The shift register is loaded with 331 | // a single '1' with the position within the register dependent on SC_RCD. 332 | // When the '1' is shifted out of the register it sets so_rw which triggers 333 | // a writea or reada command 334 | // 335 | always @(posedge CLK or negedge RESET_N) 336 | begin 337 | if (RESET_N == 0) 338 | begin 339 | rw_shift <= 0; 340 | do_rw <= 0; 341 | end 342 | 343 | else 344 | begin 345 | 346 | if ((do_reada == 1) | (do_writea == 1)) 347 | begin 348 | if (SC_RCD == 1) // Set the shift register 349 | do_rw <= 1; 350 | else if (SC_RCD == 2) 351 | rw_shift <= 1; 352 | else if (SC_RCD == 3) 353 | rw_shift <= 2; 354 | end 355 | else 356 | begin 357 | rw_shift <= (rw_shift>>1); 358 | do_rw <= rw_shift[0]; 359 | end 360 | end 361 | end 362 | 363 | // This always block generates the command acknowledge, CM_ACK, signal. 364 | // It also generates the acknowledge signal, REF_ACK, that acknowledges 365 | // a refresh request that was generated by the internal refresh timer circuit. 366 | always @(posedge CLK or negedge RESET_N) 367 | begin 368 | 369 | if (RESET_N == 0) 370 | begin 371 | CM_ACK <= 0; 372 | REF_ACK <= 0; 373 | end 374 | 375 | else 376 | begin 377 | if (do_refresh == 1 & REF_REQ == 1) // Internal refresh timer refresh request 378 | REF_ACK <= 1; 379 | else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1) // externa commands 380 | | (do_load_mode)) 381 | CM_ACK <= 1; 382 | else 383 | begin 384 | REF_ACK <= 0; 385 | CM_ACK <= 0; 386 | end 387 | end 388 | end 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | // This always block generates the address, cs, cke, and command signals(ras,cas,wen) 397 | // 398 | always @(posedge CLK ) begin 399 | if (RESET_N==0) begin 400 | SA <= 0; 401 | BA <= 0; 402 | CS_N <= 1; 403 | RAS_N <= 1; 404 | CAS_N <= 1; 405 | WE_N <= 1; 406 | CKE <= 0; 407 | end 408 | else begin 409 | CKE <= 1; 410 | 411 | // Generate SA 412 | if (do_writea == 1 | do_reada == 1) // ACTIVATE command is being issued, so present the row address 413 | SA <= rowaddr; 414 | else 415 | SA <= coladdr; // else alway present column address 416 | if ((do_rw==1) | (do_precharge)) 417 | SA[10] <= !SC_PM; // set SA[10] for autoprecharge read/write or for a precharge all command 418 | // don't set it if the controller is in page mode. 419 | if (do_precharge==1 | do_load_mode==1) 420 | BA <= 0; // Set BA=0 if performing a precharge or load_mode command 421 | else 422 | BA <= bankaddr[1:0]; // else set it with the appropriate address bits 423 | 424 | if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1) 425 | CS_N <= 0; // Select both chip selects if performing 426 | else // refresh, precharge(all) or load_mode 427 | begin 428 | CS_N[0] <= SADDR[`ASIZE-1]; // else set the chip selects based off of the 429 | CS_N[1] <= ~SADDR[`ASIZE-1]; // msb address bit 430 | end 431 | 432 | if(do_load_mode==1) 433 | SA <= {2'b00,SDR_CL,SDR_BT,SDR_BL}; 434 | 435 | 436 | //Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N 437 | //depending on the issued command. 438 | // 439 | if ( do_refresh==1 ) begin // Refresh: S=00, RAS=0, CAS=0, WE=1 440 | RAS_N <= 0; 441 | CAS_N <= 0; 442 | WE_N <= 1; 443 | end 444 | else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin // burst terminate if write is active 445 | RAS_N <= 1; 446 | CAS_N <= 1; 447 | WE_N <= 0; 448 | end 449 | else if (do_precharge==1) begin // Precharge All: S=00, RAS=0, CAS=1, WE=0 450 | RAS_N <= 0; 451 | CAS_N <= 1; 452 | WE_N <= 0; 453 | end 454 | else if (do_load_mode==1) begin // Mode Write: S=00, RAS=0, CAS=0, WE=0 455 | RAS_N <= 0; 456 | CAS_N <= 0; 457 | WE_N <= 0; 458 | end 459 | else if (do_reada == 1 | do_writea == 1) begin // Activate: S=01 or 10, RAS=0, CAS=1, WE=1 460 | RAS_N <= 0; 461 | CAS_N <= 1; 462 | WE_N <= 1; 463 | end 464 | else if (do_rw == 1) begin // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1 465 | RAS_N <= 1; 466 | CAS_N <= 0; 467 | WE_N <= rw_flag; 468 | end 469 | else if (do_initial ==1) begin 470 | RAS_N <= 1; 471 | CAS_N <= 1; 472 | WE_N <= 1; 473 | end 474 | else begin // No Operation: RAS=1, CAS=1, WE=1 475 | RAS_N <= 1; 476 | CAS_N <= 1; 477 | WE_N <= 1; 478 | end 479 | end 480 | end 481 | 482 | endmodule 483 | -------------------------------------------------------------------------------- /Sdram_Control/control_interface.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2008 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: control_interface 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny Fan :| 08/04/22 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | 43 | module control_interface( 44 | CLK, 45 | RESET_N, 46 | CMD, 47 | ADDR, 48 | REF_ACK, 49 | INIT_ACK, 50 | CM_ACK, 51 | NOP, 52 | READA, 53 | WRITEA, 54 | REFRESH, 55 | PRECHARGE, 56 | LOAD_MODE, 57 | SADDR, 58 | REF_REQ, 59 | INIT_REQ, 60 | CMD_ACK 61 | ); 62 | 63 | `include "Sdram_Params.h" 64 | 65 | input CLK; // System Clock 66 | input RESET_N; // System Reset 67 | input [2:0] CMD; // Command input 68 | input [`ASIZE-1:0] ADDR; // Address 69 | input REF_ACK; // Refresh request acknowledge 70 | input INIT_ACK; // Initial request acknowledge 71 | input CM_ACK; // Command acknowledge 72 | output NOP; // Decoded NOP command 73 | output READA; // Decoded READA command 74 | output WRITEA; // Decoded WRITEA command 75 | output REFRESH; // Decoded REFRESH command 76 | output PRECHARGE; // Decoded PRECHARGE command 77 | output LOAD_MODE; // Decoded LOAD_MODE command 78 | output [`ASIZE-1:0] SADDR; // Registered version of ADDR 79 | output REF_REQ; // Hidden refresh request 80 | output INIT_REQ; // Hidden initial request 81 | output CMD_ACK; // Command acknowledge 82 | 83 | 84 | 85 | reg NOP; 86 | reg READA; 87 | reg WRITEA; 88 | reg REFRESH; 89 | reg PRECHARGE; 90 | reg LOAD_MODE; 91 | reg [`ASIZE-1:0] SADDR; 92 | reg REF_REQ; 93 | reg INIT_REQ; 94 | reg CMD_ACK; 95 | 96 | // Internal signals 97 | reg [15:0] timer; 98 | reg [15:0] init_timer; 99 | 100 | 101 | 102 | // Command decode and ADDR register 103 | always @(posedge CLK or negedge RESET_N) 104 | begin 105 | if (RESET_N == 0) 106 | begin 107 | NOP <= 0; 108 | READA <= 0; 109 | WRITEA <= 0; 110 | SADDR <= 0; 111 | end 112 | 113 | else 114 | begin 115 | 116 | SADDR <= ADDR; // register the address to keep proper 117 | // alignment with the command 118 | 119 | if (CMD == 3'b000) // NOP command 120 | NOP <= 1; 121 | else 122 | NOP <= 0; 123 | 124 | if (CMD == 3'b001) // READA command 125 | READA <= 1; 126 | else 127 | READA <= 0; 128 | 129 | if (CMD == 3'b010) // WRITEA command 130 | WRITEA <= 1; 131 | else 132 | WRITEA <= 0; 133 | 134 | end 135 | end 136 | 137 | 138 | // Generate CMD_ACK 139 | always @(posedge CLK or negedge RESET_N) 140 | begin 141 | if (RESET_N == 0) 142 | CMD_ACK <= 0; 143 | else 144 | if ((CM_ACK == 1) & (CMD_ACK == 0)) 145 | CMD_ACK <= 1; 146 | else 147 | CMD_ACK <= 0; 148 | end 149 | 150 | 151 | // refresh timer 152 | always @(posedge CLK or negedge RESET_N) begin 153 | if (RESET_N == 0) 154 | begin 155 | timer <= 0; 156 | REF_REQ <= 0; 157 | end 158 | else 159 | begin 160 | if (REF_ACK == 1) 161 | begin 162 | timer <= REF_PER; 163 | REF_REQ <=0; 164 | end 165 | else if (INIT_REQ == 1) 166 | begin 167 | timer <= REF_PER+200; 168 | REF_REQ <=0; 169 | end 170 | else 171 | timer <= timer - 1'b1; 172 | 173 | if (timer==0) 174 | REF_REQ <= 1; 175 | 176 | end 177 | end 178 | 179 | // initial timer 180 | always @(posedge CLK or negedge RESET_N) begin 181 | if (RESET_N == 0) 182 | begin 183 | init_timer <= 0; 184 | REFRESH <= 0; 185 | PRECHARGE <= 0; 186 | LOAD_MODE <= 0; 187 | INIT_REQ <= 0; 188 | end 189 | else 190 | begin 191 | if (init_timer < (INIT_PER+201)) 192 | init_timer <= init_timer+1; 193 | 194 | if (init_timer < INIT_PER) 195 | begin 196 | REFRESH <=0; 197 | PRECHARGE <=0; 198 | LOAD_MODE <=0; 199 | INIT_REQ <=1; 200 | end 201 | else if(init_timer == (INIT_PER+20)) 202 | begin 203 | REFRESH <=0; 204 | PRECHARGE <=1; 205 | LOAD_MODE <=0; 206 | INIT_REQ <=0; 207 | end 208 | else if( (init_timer == (INIT_PER+40)) || 209 | (init_timer == (INIT_PER+60)) || 210 | (init_timer == (INIT_PER+80)) || 211 | (init_timer == (INIT_PER+100)) || 212 | (init_timer == (INIT_PER+120)) || 213 | (init_timer == (INIT_PER+140)) || 214 | (init_timer == (INIT_PER+160)) || 215 | (init_timer == (INIT_PER+180)) ) 216 | begin 217 | REFRESH <=1; 218 | PRECHARGE <=0; 219 | LOAD_MODE <=0; 220 | INIT_REQ <=0; 221 | end 222 | else if(init_timer == (INIT_PER+200)) 223 | begin 224 | REFRESH <=0; 225 | PRECHARGE <=0; 226 | LOAD_MODE <=1; 227 | INIT_REQ <=0; 228 | end 229 | else 230 | begin 231 | REFRESH <=0; 232 | PRECHARGE <=0; 233 | LOAD_MODE <=0; 234 | INIT_REQ <=0; 235 | end 236 | end 237 | end 238 | 239 | endmodule 240 | 241 | -------------------------------------------------------------------------------- /Sdram_Control/sdr_data_path.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2008 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: sdr_data_path 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny Fan :| 08/04/22 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | 43 | module sdr_data_path( 44 | CLK, 45 | RESET_N, 46 | DATAIN, 47 | DM, 48 | DQOUT, 49 | DQM 50 | ); 51 | 52 | `include "Sdram_Params.h" 53 | 54 | input CLK; // System Clock 55 | input RESET_N; // System Reset 56 | input [`DSIZE-1:0] DATAIN; // Data input from the host 57 | input [`DSIZE/8-1:0] DM; // byte data masks 58 | output [`DSIZE-1:0] DQOUT; 59 | output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs 60 | reg [`DSIZE/8-1:0] DQM; 61 | 62 | 63 | 64 | // Allign the input and output data to the SDRAM control path 65 | always @(posedge CLK or negedge RESET_N) 66 | begin 67 | if (RESET_N == 0) 68 | DQM <= `DSIZE/8-1'hF; 69 | else 70 | DQM <= DM; 71 | end 72 | 73 | assign DQOUT = DATAIN; 74 | 75 | endmodule 76 | 77 | -------------------------------------------------------------------------------- /Sdram_RD_FIFO.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/erosen/FPGA_Object_Tracking/4b8827eed9239223612c11d7db5ac8f344878a53/Sdram_RD_FIFO.qip -------------------------------------------------------------------------------- /VGA_Param.h: -------------------------------------------------------------------------------- 1 | //NOTE:you can mask the below macro definition to select the 800*600 solution, unmask it for 640*480 solution 2 | `define VGA_640x480p60 1 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /v/CCD_Capture.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2007 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: D5M CCD_Capture 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | `include "VGA_Param.h" 43 | module CCD_Capture( oDATA, 44 | oDVAL, 45 | oX_Cont, 46 | oY_Cont, 47 | oFrame_Cont, 48 | iDATA, 49 | iFVAL, 50 | iLVAL, 51 | iSTART, 52 | iEND, 53 | iCLK, 54 | iRST 55 | ); 56 | 57 | input [11:0] iDATA; 58 | input iFVAL; 59 | input iLVAL; 60 | input iSTART; 61 | input iEND; 62 | input iCLK; 63 | input iRST; 64 | output [11:0] oDATA; 65 | output [15:0] oX_Cont; 66 | output [15:0] oY_Cont; 67 | output [31:0] oFrame_Cont; 68 | output oDVAL; 69 | reg Pre_FVAL; 70 | reg mCCD_FVAL; 71 | reg mCCD_LVAL; 72 | reg [11:0] mCCD_DATA; 73 | reg [15:0] X_Cont; 74 | reg [15:0] Y_Cont; 75 | reg [31:0] Frame_Cont; 76 | reg mSTART; 77 | 78 | `ifdef VGA_640x480p60 79 | parameter COLUMN_WIDTH = 1280; 80 | `else 81 | parameter COLUMN_WIDTH = 800; 82 | `endif 83 | 84 | assign oX_Cont = X_Cont; 85 | assign oY_Cont = Y_Cont; 86 | assign oFrame_Cont = Frame_Cont; 87 | assign oDATA = mCCD_DATA; 88 | assign oDVAL = mCCD_FVAL&mCCD_LVAL; 89 | 90 | always@(posedge iCLK or negedge iRST) 91 | begin 92 | if(!iRST) 93 | mSTART <= 0; 94 | else 95 | begin 96 | if(iSTART) 97 | mSTART <= 1; 98 | if(iEND) 99 | mSTART <= 0; 100 | end 101 | end 102 | 103 | always@(posedge iCLK or negedge iRST) 104 | begin 105 | if(!iRST) 106 | begin 107 | Pre_FVAL <= 0; 108 | mCCD_FVAL <= 0; 109 | mCCD_LVAL <= 0; 110 | 111 | X_Cont <= 0; 112 | Y_Cont <= 0; 113 | end 114 | else 115 | begin 116 | Pre_FVAL <= iFVAL; 117 | if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART ) 118 | mCCD_FVAL <= 1; 119 | else if({Pre_FVAL,iFVAL}==2'b10) 120 | mCCD_FVAL <= 0; 121 | mCCD_LVAL <= iLVAL; 122 | if(mCCD_FVAL) 123 | begin 124 | if(mCCD_LVAL) 125 | begin 126 | if(X_Cont<(COLUMN_WIDTH-1)) 127 | X_Cont <= X_Cont+1; 128 | else 129 | begin 130 | X_Cont <= 0; 131 | Y_Cont <= Y_Cont+1; 132 | end 133 | end 134 | end 135 | else 136 | begin 137 | X_Cont <= 0; 138 | Y_Cont <= 0; 139 | end 140 | end 141 | end 142 | 143 | always@(posedge iCLK or negedge iRST) 144 | begin 145 | if(!iRST) 146 | Frame_Cont <= 0; 147 | else 148 | begin 149 | if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART ) 150 | Frame_Cont <= Frame_Cont+1; 151 | end 152 | end 153 | 154 | always@(posedge iCLK or negedge iRST) 155 | begin 156 | if(!iRST) 157 | mCCD_DATA <= 0; 158 | else if (iLVAL) 159 | mCCD_DATA <= iDATA; 160 | else 161 | mCCD_DATA <= 0; 162 | end 163 | 164 | reg ifval_dealy; 165 | 166 | wire ifval_fedge; 167 | reg [15:0] y_cnt_d; 168 | 169 | 170 | always@(posedge iCLK or negedge iRST) 171 | begin 172 | if(!iRST) 173 | y_cnt_d <= 0; 174 | else 175 | y_cnt_d <= Y_Cont; 176 | end 177 | 178 | 179 | always@(posedge iCLK or negedge iRST) 180 | begin 181 | if(!iRST) 182 | ifval_dealy <= 0; 183 | else 184 | ifval_dealy <= iFVAL; 185 | end 186 | 187 | assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0; 188 | 189 | endmodule -------------------------------------------------------------------------------- /v/I2C_CCD_Config.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2007 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: I2C_CCD_Config 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | `include "VGA_Param.h" 43 | module I2C_CCD_Config ( // Host Side 44 | iCLK, 45 | iRST_N, 46 | iZOOM_MODE_SW, 47 | iEXPOSURE_ADJ, 48 | iEXPOSURE_DEC_p, 49 | // I2C Side 50 | I2C_SCLK, 51 | I2C_SDAT 52 | ); 53 | 54 | // Host Side 55 | input iCLK; 56 | input iRST_N; 57 | input iZOOM_MODE_SW; 58 | 59 | // I2C Side 60 | output I2C_SCLK; 61 | inout I2C_SDAT; 62 | 63 | // Internal Registers/Wires 64 | reg [15:0] mI2C_CLK_DIV; 65 | reg [31:0] mI2C_DATA; 66 | reg mI2C_CTRL_CLK; 67 | reg mI2C_GO; 68 | wire mI2C_END; 69 | wire mI2C_ACK; 70 | reg [23:0] LUT_DATA; 71 | reg [5:0] LUT_INDEX; 72 | reg [3:0] mSetup_ST; 73 | 74 | 75 | ////////////// CMOS sensor registers setting ////////////////////// 76 | 77 | input iEXPOSURE_ADJ; 78 | input iEXPOSURE_DEC_p; 79 | 80 | parameter default_exposure = 16'h07c0; 81 | parameter exposure_change_value = 16'd200; 82 | 83 | reg [24:0] combo_cnt; 84 | wire combo_pulse; 85 | 86 | reg [1:0] izoom_mode_sw_delay; 87 | 88 | reg [3:0] iexposure_adj_delay; 89 | wire exposure_adj_set; 90 | wire exposure_adj_reset; 91 | reg [15:0] senosr_exposure; 92 | wire [17:0] senosr_exposure_temp; 93 | 94 | wire [23:0] sensor_start_row; 95 | wire [23:0] sensor_start_column; 96 | wire [23:0] sensor_row_size; 97 | wire [23:0] sensor_column_size; 98 | wire [23:0] sensor_row_mode; 99 | wire [23:0] sensor_column_mode; 100 | 101 | assign sensor_start_row = iZOOM_MODE_SW ? 24'h010036 : 24'h010000; 102 | assign sensor_start_column = iZOOM_MODE_SW ? 24'h020010 : 24'h020000; 103 | `ifdef VGA_640x480p60 104 | assign sensor_row_size = iZOOM_MODE_SW ? 24'h0303BF : 24'h03077F; 105 | assign sensor_column_size = iZOOM_MODE_SW ? 24'h0404FF : 24'h0409FF; 106 | `else 107 | assign sensor_row_size = iZOOM_MODE_SW ? 24'h0303BF : 24'h0304AF; //600 108 | assign sensor_column_size = iZOOM_MODE_SW ? 24'h0404FF : 24'h04063F; //800 109 | `endif 110 | assign sensor_row_mode = iZOOM_MODE_SW ? 24'h220000 : 24'h220011; 111 | assign sensor_column_mode = iZOOM_MODE_SW ? 24'h230000 : 24'h230011; 112 | 113 | 114 | always@(posedge iCLK or negedge iRST_N) 115 | begin 116 | if (!iRST_N) 117 | begin 118 | iexposure_adj_delay <= 0; 119 | end 120 | else 121 | begin 122 | iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ}; 123 | end 124 | end 125 | 126 | assign exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ; 127 | assign exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ; 128 | assign senosr_exposure_temp = iEXPOSURE_DEC_p ? (senosr_exposure - exposure_change_value) : (senosr_exposure + exposure_change_value); 129 | 130 | always@(posedge iCLK or negedge iRST_N) 131 | begin 132 | if (!iRST_N) 133 | senosr_exposure <= default_exposure; 134 | else if (exposure_adj_set|combo_pulse) 135 | if (senosr_exposure_temp[17]) 136 | senosr_exposure <= 0; 137 | else if (senosr_exposure_temp[16]) 138 | senosr_exposure <= 16'hffff; 139 | else 140 | senosr_exposure <= senosr_exposure_temp[15:0]; 141 | end 142 | 143 | 144 | always@(posedge iCLK or negedge iRST_N) 145 | begin 146 | if (!iRST_N) 147 | combo_cnt <= 0; 148 | else if (!iexposure_adj_delay[3]) 149 | combo_cnt <= combo_cnt + 1; 150 | else 151 | combo_cnt <= 0; 152 | end 153 | 154 | assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0; 155 | 156 | wire i2c_reset; 157 | 158 | assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ; 159 | 160 | ///////////////////////////////////////////////////////////////////// 161 | 162 | // Clock Setting 163 | parameter CLK_Freq = 50000000; // 50 MHz 164 | parameter I2C_Freq = 20000; // 20 KHz 165 | // LUT Data Number 166 | parameter LUT_SIZE = 25; 167 | 168 | ///////////////////// I2C Control Clock //////////////////////// 169 | always@(posedge iCLK or negedge i2c_reset) 170 | begin 171 | if(!i2c_reset) 172 | begin 173 | mI2C_CTRL_CLK <= 0; 174 | mI2C_CLK_DIV <= 0; 175 | end 176 | else 177 | begin 178 | if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) ) 179 | mI2C_CLK_DIV <= mI2C_CLK_DIV+1; 180 | else 181 | begin 182 | mI2C_CLK_DIV <= 0; 183 | mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK; 184 | end 185 | end 186 | end 187 | //////////////////////////////////////////////////////////////////// 188 | I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock 189 | .I2C_SCLK(I2C_SCLK), // I2C CLOCK 190 | .I2C_SDAT(I2C_SDAT), // I2C DATA 191 | .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA] 192 | .GO(mI2C_GO), // GO transfor 193 | .END(mI2C_END), // END transfor 194 | .ACK(mI2C_ACK), // ACK 195 | .RESET(i2c_reset) 196 | ); 197 | //////////////////////////////////////////////////////////////////// 198 | ////////////////////// Config Control //////////////////////////// 199 | //always@(posedge mI2C_CTRL_CLK or negedge iRST_N) 200 | always@(posedge mI2C_CTRL_CLK or negedge i2c_reset) 201 | begin 202 | if(!i2c_reset) 203 | begin 204 | LUT_INDEX <= 0; 205 | mSetup_ST <= 0; 206 | mI2C_GO <= 0; 207 | 208 | end 209 | 210 | else if(LUT_INDEX= 4) & (SD_COUNTER <=39))? ~CLOCK :0 ); 71 | wire I2C_SDAT=SDO?1'bz:0 ; 72 | 73 | reg ACK1,ACK2,ACK3,ACK4; 74 | wire ACK=ACK1 | ACK2 |ACK3 |ACK4; 75 | 76 | //--I2C COUNTER 77 | always @(negedge RESET or posedge CLOCK ) begin 78 | if (!RESET) SD_COUNTER=6'b111111; 79 | else begin 80 | if (GO==0) 81 | SD_COUNTER=0; 82 | else 83 | if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1; 84 | end 85 | end 86 | //---- 87 | 88 | always @(negedge RESET or posedge CLOCK ) begin 89 | if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end 90 | else 91 | case (SD_COUNTER) 92 | 6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end 93 | //start 94 | 6'd1 : begin SD=I2C_DATA;SDO=0;end 95 | 6'd2 : SCLK=0; 96 | //SLAVE ADDR 97 | 6'd3 : SDO=SD[31]; 98 | 6'd4 : SDO=SD[30]; 99 | 6'd5 : SDO=SD[29]; 100 | 6'd6 : SDO=SD[28]; 101 | 6'd7 : SDO=SD[27]; 102 | 6'd8 : SDO=SD[26]; 103 | 6'd9 : SDO=SD[25]; 104 | 6'd10 : SDO=SD[24]; 105 | 6'd11 : SDO=1'b1;//ACK 106 | 107 | //SUB ADDR 108 | 6'd12 : begin SDO=SD[23]; ACK1=I2C_SDAT; end 109 | 6'd13 : SDO=SD[22]; 110 | 6'd14 : SDO=SD[21]; 111 | 6'd15 : SDO=SD[20]; 112 | 6'd16 : SDO=SD[19]; 113 | 6'd17 : SDO=SD[18]; 114 | 6'd18 : SDO=SD[17]; 115 | 6'd19 : SDO=SD[16]; 116 | 6'd20 : SDO=1'b1;//ACK 117 | 118 | //DATA 119 | 6'd21 : begin SDO=SD[15]; ACK2=I2C_SDAT; end 120 | 6'd22 : SDO=SD[14]; 121 | 6'd23 : SDO=SD[13]; 122 | 6'd24 : SDO=SD[12]; 123 | 6'd25 : SDO=SD[11]; 124 | 6'd26 : SDO=SD[10]; 125 | 6'd27 : SDO=SD[9]; 126 | 6'd28 : SDO=SD[8]; 127 | 6'd29 : SDO=1'b1;//ACK 128 | 129 | //DATA 130 | 6'd30 : begin SDO=SD[7]; ACK3=I2C_SDAT; end 131 | 6'd31 : SDO=SD[6]; 132 | 6'd32 : SDO=SD[5]; 133 | 6'd33 : SDO=SD[4]; 134 | 6'd34 : SDO=SD[3]; 135 | 6'd35 : SDO=SD[2]; 136 | 6'd36 : SDO=SD[1]; 137 | 6'd37 : SDO=SD[0]; 138 | 6'd38 : SDO=1'b1;//ACK 139 | 140 | 141 | //stop 142 | 6'd39 : begin SDO=1'b0; SCLK=1'b0; ACK4=I2C_SDAT; end 143 | 6'd40 : SCLK=1'b1; 144 | 6'd41 : begin SDO=1'b1; END=1; end 145 | 146 | endcase 147 | end 148 | 149 | 150 | 151 | endmodule 152 | -------------------------------------------------------------------------------- /v/Line_Buffer.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2010 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 184 144) 24 | (text "Line_Buffer" (rect 60 1 135 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 128 25 140)(font "Arial" )) 26 | (port 27 | (pt 0 40) 28 | (input) 29 | (text "shiftin[11..0]" (rect 0 0 69 14)(font "Arial" (font_size 8))) 30 | (text "shiftin[11..0]" (rect 20 34 78 47)(font "Arial" (font_size 8))) 31 | (line (pt 0 40)(pt 16 40)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 56) 35 | (input) 36 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 37 | (text "clock" (rect 20 50 43 63)(font "Arial" (font_size 8))) 38 | (line (pt 0 56)(pt 16 56)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 72) 42 | (input) 43 | (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8))) 44 | (text "clken" (rect 20 66 44 79)(font "Arial" (font_size 8))) 45 | (line (pt 0 72)(pt 16 72)(line_width 1)) 46 | ) 47 | (port 48 | (pt 184 40) 49 | (output) 50 | (text "shiftout[11..0]" (rect 0 0 77 14)(font "Arial" (font_size 8))) 51 | (text "shiftout[11..0]" (rect 99 34 163 47)(font "Arial" (font_size 8))) 52 | (line (pt 184 40)(pt 168 40)(line_width 3)) 53 | ) 54 | (port 55 | (pt 184 56) 56 | (output) 57 | (text "taps2x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) 58 | (text "taps2x[11..0]" (rect 102 50 162 63)(font "Arial" (font_size 8))) 59 | (line (pt 184 56)(pt 168 56)(line_width 3)) 60 | ) 61 | (port 62 | (pt 184 72) 63 | (output) 64 | (text "taps1x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) 65 | (text "taps1x[11..0]" (rect 102 66 162 79)(font "Arial" (font_size 8))) 66 | (line (pt 184 72)(pt 168 72)(line_width 3)) 67 | ) 68 | (port 69 | (pt 184 88) 70 | (output) 71 | (text "taps0x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) 72 | (text "taps0x[11..0]" (rect 102 82 162 95)(font "Arial" (font_size 8))) 73 | (line (pt 184 88)(pt 168 88)(line_width 3)) 74 | ) 75 | (drawing 76 | (text "altshift_taps" (rect 63 18 119 31)(font "Arial" (font_size 8))) 77 | (text "Number of taps 3" (rect 19 106 93 118)(font "Arial" )) 78 | (text "Tap distance 800" (rect 19 116 90 128)(font "Arial" )) 79 | (line (pt 16 16)(pt 168 16)(line_width 1)) 80 | (line (pt 168 16)(pt 168 128)(line_width 1)) 81 | (line (pt 168 128)(pt 16 128)(line_width 1)) 82 | (line (pt 16 128)(pt 16 16)(line_width 1)) 83 | ) 84 | ) 85 | -------------------------------------------------------------------------------- /v/Line_Buffer.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "Shift register (RAM-based)" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Line_Buffer.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Line_Buffer.bsf"] 5 | -------------------------------------------------------------------------------- /v/Line_Buffer.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %Shift register (RAM-based)% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altshift_taps 5 | 6 | // ============================================================ 7 | // File Name: Line_Buffer.v 8 | // Megafunction Name(s): 9 | // altshift_taps 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 9.1 Build 350 03/24/2010 SP 2 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2010 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module Line_Buffer ( 40 | clken, 41 | clock, 42 | shiftin, 43 | shiftout, 44 | taps0x, 45 | taps1x, 46 | taps2x); 47 | 48 | input clken; 49 | input clock; 50 | input [11:0] shiftin; 51 | output [11:0] shiftout; 52 | output [11:0] taps0x; 53 | output [11:0] taps1x; 54 | output [11:0] taps2x; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_off 57 | `endif 58 | tri1 clken; 59 | `ifndef ALTERA_RESERVED_QIS 60 | // synopsys translate_on 61 | `endif 62 | 63 | wire [35:0] sub_wire0; 64 | wire [11:0] sub_wire5; 65 | wire [23:12] sub_wire3 = sub_wire0[23:12]; 66 | wire [11:0] sub_wire4 = sub_wire0[11:0]; 67 | wire [35:24] sub_wire2 = sub_wire0[35:24]; 68 | wire [35:24] sub_wire1 = sub_wire2[35:24]; 69 | wire [11:0] taps2x = sub_wire1[35:24]; 70 | wire [11:0] taps1x = sub_wire3[23:12]; 71 | wire [11:0] taps0x = sub_wire4[11:0]; 72 | wire [11:0] shiftout = sub_wire5[11:0]; 73 | 74 | altshift_taps altshift_taps_component ( 75 | .clken (clken), 76 | .clock (clock), 77 | .shiftin (shiftin), 78 | .taps (sub_wire0), 79 | .shiftout (sub_wire5) 80 | // synopsys translate_off 81 | , 82 | .aclr () 83 | // synopsys translate_on 84 | ); 85 | defparam 86 | altshift_taps_component.lpm_hint = "RAM_BLOCK_TYPE=M9K", 87 | altshift_taps_component.lpm_type = "altshift_taps", 88 | altshift_taps_component.number_of_taps = 3, 89 | altshift_taps_component.tap_distance = 800, 90 | altshift_taps_component.width = 12; 91 | 92 | 93 | endmodule 94 | 95 | // ============================================================ 96 | // CNX file retrieval info 97 | // ============================================================ 98 | // Retrieval info: PRIVATE: ACLR NUMERIC "0" 99 | // Retrieval info: PRIVATE: CLKEN NUMERIC "1" 100 | // Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1" 101 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 102 | // Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "3" 103 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1" 104 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 105 | // Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "800" 106 | // Retrieval info: PRIVATE: WIDTH NUMERIC "12" 107 | // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K" 108 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps" 109 | // Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "3" 110 | // Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "800" 111 | // Retrieval info: CONSTANT: WIDTH NUMERIC "12" 112 | // Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken 113 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 114 | // Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0] 115 | // Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0] 116 | // Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0] 117 | // Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0] 118 | // Retrieval info: USED_PORT: taps2x 0 0 12 0 OUTPUT NODEFVAL taps2x[11..0] 119 | // Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0 120 | // Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0 121 | // Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0 122 | // Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12 123 | // Retrieval info: CONNECT: taps2x 0 0 12 0 @taps 0 0 12 24 124 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 125 | // Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 126 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 127 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE 128 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE 129 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE 130 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE 131 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE 133 | // Retrieval info: LIB_FILE: altera_mf 134 | -------------------------------------------------------------------------------- /v/Line_Buffer1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 184 128) 24 | (text "Line_Buffer1" (rect 58 0 141 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 112 25 124)(font "Arial" )) 26 | (port 27 | (pt 0 40) 28 | (input) 29 | (text "shiftin[11..0]" (rect 0 0 68 14)(font "Arial" (font_size 8))) 30 | (text "shiftin[11..0]" (rect 20 33 76 46)(font "Arial" (font_size 8))) 31 | (line (pt 0 40)(pt 16 40)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 56) 35 | (input) 36 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 37 | (text "clock" (rect 20 49 43 62)(font "Arial" (font_size 8))) 38 | (line (pt 0 56)(pt 16 56)) 39 | ) 40 | (port 41 | (pt 0 72) 42 | (input) 43 | (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8))) 44 | (text "clken" (rect 20 65 43 78)(font "Arial" (font_size 8))) 45 | (line (pt 0 72)(pt 16 72)) 46 | ) 47 | (port 48 | (pt 184 56) 49 | (input) 50 | (text "taps1x[11..0]" (rect 0 0 73 14)(font "Arial" (font_size 8))) 51 | (text "taps1x[11..0]" (rect 103 49 163 62)(font "Arial" (font_size 8))) 52 | (line (pt 184 56)(pt 168 56)(line_width 3)) 53 | ) 54 | (port 55 | (pt 184 72) 56 | (input) 57 | (text "taps0x[11..0]" (rect 0 0 73 14)(font "Arial" (font_size 8))) 58 | (text "taps0x[11..0]" (rect 103 65 163 78)(font "Arial" (font_size 8))) 59 | (line (pt 184 72)(pt 168 72)(line_width 3)) 60 | ) 61 | (port 62 | (pt 184 40) 63 | (output) 64 | (text "shiftout[11..0]" (rect 0 0 76 14)(font "Arial" (font_size 8))) 65 | (text "shiftout[11..0]" (rect 100 33 163 46)(font "Arial" (font_size 8))) 66 | (line (pt 184 40)(pt 168 40)(line_width 3)) 67 | ) 68 | (drawing 69 | (text "altshift_taps" (rect 66 16 182 43)(font "Arial" )) 70 | (text "Number of taps 2" (rect 18 91 108 193)(font "Arial" )) 71 | (text "Tap distance 1280" (rect 18 101 109 213)(font "Arial" )) 72 | (line (pt 16 16)(pt 168 16)) 73 | (line (pt 168 16)(pt 168 112)) 74 | (line (pt 168 112)(pt 16 112)) 75 | (line (pt 16 112)(pt 16 16)) 76 | (line (pt 0 0)(pt 186 0)) 77 | (line (pt 186 0)(pt 186 130)) 78 | (line (pt 0 130)(pt 186 130)) 79 | (line (pt 0 0)(pt 0 130)) 80 | (line (pt 0 0)(pt 0 0)) 81 | (line (pt 0 0)(pt 0 0)) 82 | (line (pt 0 0)(pt 0 0)) 83 | (line (pt 0 0)(pt 0 0)) 84 | ) 85 | ) 86 | -------------------------------------------------------------------------------- /v/Line_Buffer1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "Shift register (RAM-based)" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Line_Buffer1.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Line_Buffer1.bsf"] 5 | -------------------------------------------------------------------------------- /v/Line_Buffer1.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %Shift register (RAM-based)% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTSHIFT_TAPS 5 | 6 | // ============================================================ 7 | // File Name: Line_Buffer1.v 8 | // Megafunction Name(s): 9 | // ALTSHIFT_TAPS 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module Line_Buffer1 ( 40 | clken, 41 | clock, 42 | shiftin, 43 | shiftout, 44 | taps0x, 45 | taps1x); 46 | 47 | input clken; 48 | input clock; 49 | input [11:0] shiftin; 50 | output [11:0] shiftout; 51 | output [11:0] taps0x; 52 | output [11:0] taps1x; 53 | `ifndef ALTERA_RESERVED_QIS 54 | // synopsys translate_off 55 | `endif 56 | tri1 clken; 57 | `ifndef ALTERA_RESERVED_QIS 58 | // synopsys translate_on 59 | `endif 60 | 61 | wire [11:0] sub_wire0; 62 | wire [23:0] sub_wire1; 63 | wire [11:0] shiftout = sub_wire0[11:0]; 64 | wire [23:12] sub_wire3 = sub_wire1[23:12]; 65 | wire [11:0] sub_wire2 = sub_wire1[11:0]; 66 | wire [11:0] taps0x = sub_wire2[11:0]; 67 | wire [11:0] taps1x = sub_wire3[23:12]; 68 | 69 | altshift_taps ALTSHIFT_TAPS_component ( 70 | .clock (clock), 71 | .clken (clken), 72 | .shiftin (shiftin), 73 | .shiftout (sub_wire0), 74 | .taps (sub_wire1) 75 | // synopsys translate_off 76 | , 77 | .aclr () 78 | // synopsys translate_on 79 | ); 80 | defparam 81 | ALTSHIFT_TAPS_component.intended_device_family = "Cyclone IV E", 82 | ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M9K", 83 | ALTSHIFT_TAPS_component.lpm_type = "altshift_taps", 84 | ALTSHIFT_TAPS_component.number_of_taps = 2, 85 | ALTSHIFT_TAPS_component.tap_distance = 1280, 86 | ALTSHIFT_TAPS_component.width = 12; 87 | 88 | 89 | endmodule 90 | 91 | // ============================================================ 92 | // CNX file retrieval info 93 | // ============================================================ 94 | // Retrieval info: PRIVATE: ACLR NUMERIC "0" 95 | // Retrieval info: PRIVATE: CLKEN NUMERIC "1" 96 | // Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1" 97 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 98 | // Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2" 99 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1" 100 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 101 | // Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280" 102 | // Retrieval info: PRIVATE: WIDTH NUMERIC "12" 103 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 104 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 105 | // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K" 106 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps" 107 | // Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2" 108 | // Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280" 109 | // Retrieval info: CONSTANT: WIDTH NUMERIC "12" 110 | // Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" 111 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" 112 | // Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL "shiftin[11..0]" 113 | // Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL "shiftout[11..0]" 114 | // Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL "taps0x[11..0]" 115 | // Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL "taps1x[11..0]" 116 | // Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 117 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 118 | // Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0 119 | // Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0 120 | // Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0 121 | // Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1.v TRUE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1.inc FALSE 124 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1.cmp FALSE 125 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1.bsf TRUE 126 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1_inst.v FALSE 127 | // Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1_bb.v FALSE 128 | // Retrieval info: LIB_FILE: altera_mf 129 | -------------------------------------------------------------------------------- /v/MEM_SWITCH.v: -------------------------------------------------------------------------------- 1 | // Memory Multiplexer 2 | module MEM_SWITCH (iGray, 3 | iFrameCount, 4 | iDVAL, 5 | oGray1, 6 | oGray2, 7 | oDVAL1, 8 | oDVAL2 9 | ); 10 | 11 | input [11:0] iGray; 12 | input iFrameCount; 13 | input iDVAL; 14 | 15 | output [11:0] oGray1; 16 | output [11:0] oGray2; 17 | output oDVAL1; 18 | output oDVAL2; 19 | 20 | reg [11:0] tempGray1; 21 | reg [11:0] tempGray2; 22 | 23 | assign oGray1 = tempGray1; 24 | assign oGray2 = tempGray2; 25 | 26 | assign oDVAL1 = iFrameCount ? iDVAL : 0; 27 | assign oDVAL2 = ~iFrameCount ? iDVAL : 0; 28 | 29 | always@(iFrameCount) 30 | begin 31 | 32 | if(iFrameCount) 33 | 34 | tempGray1 = iGray; 35 | 36 | else 37 | 38 | tempGray2 = iGray; 39 | 40 | end 41 | 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /v/RAW2RGB.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 20057 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: RAW2RGB 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny Fan :| 07/08/01 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | module RAW2RGB( oRed, 43 | oGreen, 44 | oBlue, 45 | oDVAL, 46 | iX_Cont, 47 | iY_Cont, 48 | iDATA, 49 | iDVAL, 50 | iCLK, 51 | iRST 52 | ); 53 | 54 | input [10:0] iX_Cont; 55 | input [10:0] iY_Cont; 56 | input [11:0] iDATA; 57 | input iDVAL; 58 | input iCLK; 59 | input iRST; 60 | output [11:0] oRed; 61 | output [11:0] oGreen; 62 | output [11:0] oBlue; 63 | output oDVAL; 64 | wire [11:0] mDATA_0; 65 | wire [11:0] mDATA_1; 66 | reg [11:0] mDATAd_0; 67 | reg [11:0] mDATAd_1; 68 | reg [11:0] mCCD_R; 69 | reg [12:0] mCCD_G; 70 | reg [11:0] mCCD_B; 71 | reg mDVAL; 72 | 73 | assign oRed = mCCD_R[11:0]; 74 | assign oGreen = mCCD_G[12:1]; 75 | assign oBlue = mCCD_B[11:0]; 76 | assign oDVAL = mDVAL; 77 | 78 | Line_Buffer1 u0 ( .clken(iDVAL), 79 | .clock(iCLK), 80 | .shiftin(iDATA), 81 | .taps0x(mDATA_1), 82 | .taps1x(mDATA_0) ); 83 | 84 | always@(posedge iCLK or negedge iRST) 85 | begin 86 | if(!iRST) 87 | begin 88 | mCCD_R <= 0; 89 | mCCD_G <= 0; 90 | mCCD_B <= 0; 91 | mDATAd_0<= 0; 92 | mDATAd_1<= 0; 93 | mDVAL <= 0; 94 | end 95 | else 96 | begin 97 | mDATAd_0 <= mDATA_0; 98 | mDATAd_1 <= mDATA_1; 99 | mDVAL <= {iY_Cont[0]|iX_Cont[0]} ? 1'b0 : iDVAL; 100 | if({iY_Cont[0],iX_Cont[0]}==2'b10) 101 | begin 102 | mCCD_R <= mDATA_0; 103 | mCCD_G <= mDATAd_0+mDATA_1; 104 | mCCD_B <= mDATAd_1; 105 | end 106 | else if({iY_Cont[0],iX_Cont[0]}==2'b11) 107 | begin 108 | mCCD_R <= mDATAd_0; 109 | mCCD_G <= mDATA_0+mDATAd_1; 110 | mCCD_B <= mDATA_1; 111 | end 112 | else if({iY_Cont[0],iX_Cont[0]}==2'b00) 113 | begin 114 | mCCD_R <= mDATA_1; 115 | mCCD_G <= mDATA_0+mDATAd_1; 116 | mCCD_B <= mDATAd_0; 117 | end 118 | else if({iY_Cont[0],iX_Cont[0]}==2'b01) 119 | begin 120 | mCCD_R <= mDATAd_1; 121 | mCCD_G <= mDATAd_0+mDATA_1; 122 | mCCD_B <= mDATA_0; 123 | end 124 | end 125 | end 126 | 127 | endmodule -------------------------------------------------------------------------------- /v/RGB2GRAY.v: -------------------------------------------------------------------------------- 1 | //Converts RGB color to Grayscale 2 | 3 | module RGB2GRAY(iRed, 4 | iGreen, 5 | iBlue, 6 | oGray, 7 | ); 8 | 9 | 10 | input [11:0] iRed; 11 | input [11:0] iGreen; 12 | input [11:0] iBlue; 13 | 14 | output [11:0] oGray; 15 | 16 | 17 | //oGray=0.299R+0.587G+0.114B; 18 | assign oGray = (iRed >> 2) + (iRed >> 5) + 19 | (iGreen >> 1) + (iGreen >> 4) + 20 | (iBlue >> 4) + (iBlue >> 5); 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /v/Reset_Delay.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2007 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: Reset_Delay 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | 43 | module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2,oRST_3,oRST_4); 44 | input iCLK; 45 | input iRST; 46 | output reg oRST_0; 47 | output reg oRST_1; 48 | output reg oRST_2; 49 | output reg oRST_3; 50 | output reg oRST_4; 51 | 52 | reg [31:0] Cont; 53 | 54 | always@(posedge iCLK or negedge iRST) 55 | begin 56 | if(!iRST) 57 | begin 58 | Cont <= 0; 59 | oRST_0 <= 0; 60 | oRST_1 <= 0; 61 | oRST_2 <= 0; 62 | oRST_3 <= 0; 63 | oRST_4 <= 0; 64 | end 65 | else 66 | begin 67 | if(Cont!=32'h01FFFFFF) 68 | Cont <= Cont+1; 69 | if(Cont>=32'h001FFFFF) 70 | oRST_0 <= 1; 71 | if(Cont>=32'h002FFFFF) 72 | oRST_1 <= 1; 73 | if(Cont>=32'h011FFFFF) 74 | oRST_2 <= 1; 75 | if(Cont>=32'h016FFFFF) 76 | oRST_3 <= 1; 77 | if(Cont>=32'h01FFFFFF) 78 | oRST_4 <= 1; 79 | end 80 | end 81 | 82 | endmodule -------------------------------------------------------------------------------- /v/SEG7_LUT.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2007 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: SEG7_LUT 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | 43 | module SEG7_LUT ( oSEG,iDIG ); 44 | input [3:0] iDIG; 45 | output [6:0] oSEG; 46 | reg [6:0] oSEG; 47 | 48 | always @(iDIG) 49 | begin 50 | case(iDIG) 51 | 4'h1: oSEG = 7'b1111001; // ---t---- 52 | 4'h2: oSEG = 7'b0100100; // | | 53 | 4'h3: oSEG = 7'b0110000; // lt rt 54 | 4'h4: oSEG = 7'b0011001; // | | 55 | 4'h5: oSEG = 7'b0010010; // ---m---- 56 | 4'h6: oSEG = 7'b0000010; // | | 57 | 4'h7: oSEG = 7'b1111000; // lb rb 58 | 4'h8: oSEG = 7'b0000000; // | | 59 | 4'h9: oSEG = 7'b0011000; // ---b---- 60 | 4'ha: oSEG = 7'b0001000; 61 | 4'hb: oSEG = 7'b0000011; 62 | 4'hc: oSEG = 7'b1000110; 63 | 4'hd: oSEG = 7'b0100001; 64 | 4'he: oSEG = 7'b0000110; 65 | 4'hf: oSEG = 7'b0001110; 66 | 4'h0: oSEG = 7'b1000000; 67 | endcase 68 | end 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /v/SEG7_LUT_8.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2007 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: SEG7_LUT_8 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision 41 | // -------------------------------------------------------------------- 42 | 43 | module SEG7_LUT_8 ( oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG ); 44 | input [31:0] iDIG; 45 | output [6:0] oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7; 46 | 47 | SEG7_LUT u0 ( oSEG0,iDIG[3:0] ); 48 | SEG7_LUT u1 ( oSEG1,iDIG[7:4] ); 49 | SEG7_LUT u2 ( oSEG2,iDIG[11:8] ); 50 | SEG7_LUT u3 ( oSEG3,iDIG[15:12] ); 51 | SEG7_LUT u4 ( oSEG4,iDIG[19:16] ); 52 | SEG7_LUT u5 ( oSEG5,iDIG[23:20] ); 53 | SEG7_LUT u6 ( oSEG6,iDIG[27:24] ); 54 | SEG7_LUT u7 ( oSEG7,iDIG[31:28] ); 55 | 56 | endmodule -------------------------------------------------------------------------------- /v/VGA_Controller.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2010 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: VGA_Controller 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | // V1.0 :| Johnny FAN Peli Li:| 22/07/2010:| Initial Revision 41 | // -------------------------------------------------------------------- 42 | 43 | module VGA_Controller( // Host Side 44 | iGrayMem1, 45 | iGrayMem2, 46 | iTrackMode, 47 | oRequest, 48 | // VGA Side 49 | oVGA_R, 50 | oVGA_G, 51 | oVGA_B, 52 | oVGA_H_SYNC, 53 | oVGA_V_SYNC, 54 | oVGA_SYNC, 55 | oVGA_BLANK, 56 | 57 | // Control Signal 58 | iCLK, 59 | iRST_N, 60 | iZOOM_MODE_SW, 61 | 62 | oActivityGraph 63 | ); 64 | 65 | // Horizontal Parameter ( Pixel ) 66 | parameter H_SYNC_CYC = 96; 67 | parameter H_SYNC_BACK = 48; 68 | parameter H_SYNC_ACT = 640; 69 | parameter H_SYNC_FRONT= 16; 70 | parameter H_SYNC_TOTAL= 800; 71 | 72 | // Virtical Parameter ( Line ) 73 | parameter V_SYNC_CYC = 2; 74 | parameter V_SYNC_BACK = 33; 75 | parameter V_SYNC_ACT = 480; 76 | parameter V_SYNC_FRONT= 10; 77 | parameter V_SYNC_TOTAL= 525; 78 | 79 | 80 | // Start Offset 81 | parameter X_START = H_SYNC_CYC+H_SYNC_BACK; 82 | parameter Y_START = V_SYNC_CYC+V_SYNC_BACK; 83 | // Host Side 84 | input [9:0] iGrayMem1; 85 | input [9:0] iGrayMem2; 86 | input [9:0] iTrackMode; 87 | output reg oRequest; 88 | // VGA Side 89 | output reg [9:0] oVGA_R; 90 | output reg [9:0] oVGA_G; 91 | output reg [9:0] oVGA_B; 92 | output reg oVGA_H_SYNC; 93 | output reg oVGA_V_SYNC; 94 | output reg oVGA_SYNC; 95 | output reg oVGA_BLANK; 96 | 97 | output reg [7:0] oActivityGraph; 98 | 99 | reg [18:0] GrayCount; 100 | 101 | wire [9:0] mVGA_R; 102 | wire [9:0] mVGA_G; 103 | wire [9:0] mVGA_B; 104 | reg mVGA_H_SYNC; 105 | reg mVGA_V_SYNC; 106 | wire mVGA_SYNC; 107 | wire mVGA_BLANK; 108 | 109 | // Control Signal 110 | input iCLK; 111 | input iRST_N; 112 | input iZOOM_MODE_SW; 113 | 114 | // Internal Registers and Wires 115 | reg [12:0] H_Cont; 116 | reg [12:0] V_Cont; 117 | 118 | wire [12:0] v_mask; 119 | 120 | 121 | 122 | assign v_mask = 13'd0 ;//iZOOM_MODE_SW ? 13'd0 : 13'd26; 123 | 124 | //////////////////////////////////////////////////////// 125 | 126 | assign mVGA_BLANK = mVGA_H_SYNC & mVGA_V_SYNC; 127 | assign mVGA_SYNC = 1'b0; 128 | 129 | assign mVGA_R = ( H_Cont>=X_START && H_Cont=Y_START+v_mask && V_Cont=X_START && H_Cont=Y_START+v_mask && V_Cont=X_START && H_Cont=Y_START+v_mask && V_Cont iGrayMem2) 171 | begin 172 | grayChange = ((iGrayMem1 - iGrayMem2) > GrayChangeThreshold); 173 | end 174 | 175 | else 176 | begin 177 | grayChange = ((iGrayMem2 - iGrayMem1) > GrayChangeThreshold); 178 | end 179 | end 180 | 181 | // Change display mode vs switches 182 | always@(grayChange or iTrackMode) 183 | begin 184 | 185 | case (iTrackMode[3:0]) 186 | 187 | 4'b0001 : // display only tracking data 188 | begin 189 | GrayValue = 0; 190 | RedValue = grayChange ? 1023 : 0; 191 | end 192 | 193 | 4'b0010 : // display tracking data on top of image 194 | begin 195 | 196 | GrayValue = grayChange ? 0 : iGrayMem1; 197 | RedValue = grayChange ? 1023 : iGrayMem1; 198 | 199 | end 200 | 201 | 4'b0100 : // display tracking data in cyan 202 | begin 203 | GrayValue = grayChange ? 1023 : 0; 204 | RedValue = 0; 205 | end 206 | 207 | default : // display camera image 208 | begin 209 | GrayValue = iGrayMem1; 210 | RedValue = iGrayMem1; 211 | end 212 | endcase 213 | 214 | // Change the threshold value from switches 215 | case (iTrackMode[7:4]) 216 | 4'b0001 : GrayChangeThreshold = 0; 217 | 4'b0010 : GrayChangeThreshold = 16; 218 | 4'b0100 : GrayChangeThreshold = 32; 219 | 4'b1000 : GrayChangeThreshold = 64; 220 | default : GrayChangeThreshold = 50; 221 | endcase 222 | 223 | end 224 | 225 | // Index Counter 226 | always@(H_Cont or V_Cont) 227 | begin 228 | 229 | if (( H_Cont>=X_START && H_Cont=Y_START+v_mask && V_Cont 0 && grayChange) 249 | GrayCount = GrayCount + 1; 250 | else 251 | GrayCount = 0; 252 | 253 | end 254 | 255 | //Adjust activity graph based on the amount of motion between frames 256 | always@(GrayCount) 257 | begin 258 | 259 | if(indexCount > 0) 260 | begin 261 | if(GrayCount > 10 && GrayCount <= 50) // 5% 262 | oActivityGraph = 1; 263 | else if(GrayCount > 50 && GrayCount <= 250) // 10% 264 | oActivityGraph = 3; 265 | else if(GrayCount > 250 && GrayCount <= 1000) // 25% 266 | oActivityGraph = 7; 267 | else if(GrayCount > 1000 && GrayCount <= 10000) // 50% 268 | oActivityGraph = 15; 269 | else if(GrayCount > 10000 && GrayCount <= 200000) // 60% 270 | oActivityGraph = 31; 271 | else if(GrayCount > 200000 && GrayCount <= 300000 ) // 75% 272 | oActivityGraph = 63; 273 | else if(GrayCount > 100000 && GrayCount <= 307200) // 100% 274 | oActivityGraph = 255; 275 | else 276 | oActivityGraph = 0; 277 | end 278 | end 279 | 280 | // sets binaryMotionArray to a 0 or 1 based on the whether or not motion 281 | // index of binaryMotionArray is based on indexCount 282 | always@(indexCount) 283 | begin 284 | binaryMotionArray[indexCount] = grayChange; 285 | end 286 | 287 | always@(negedge indexCount) 288 | begin 289 | if(indexCount >= distanceThresh) 290 | begin 291 | continousRow = 0; 292 | 293 | for( i = 0; i < distanceThresh; i = i + 1 ) 294 | begin 295 | continousRow = continousRow + binaryMotionArray[indexCount - i]; 296 | end 297 | 298 | if(continousRow >= densityThresh) 299 | begin 300 | 301 | for( i = 0; i < distanceThresh; i = i + 1 ) 302 | begin 303 | rowMotionArray[indexCount - i] = 1; 304 | end 305 | 306 | end 307 | 308 | end 309 | end 310 | 311 | 312 | always@(posedge iCLK or negedge iRST_N) 313 | begin 314 | if (!iRST_N) 315 | begin 316 | oVGA_R <= 0; 317 | oVGA_G <= 0; 318 | oVGA_B <= 0; 319 | oVGA_BLANK <= 0; 320 | oVGA_SYNC <= 0; 321 | oVGA_H_SYNC <= 0; 322 | oVGA_V_SYNC <= 0; 323 | end 324 | else 325 | begin 326 | oVGA_R <= mVGA_R; 327 | oVGA_G <= mVGA_G; 328 | oVGA_B <= mVGA_B; 329 | oVGA_BLANK <= mVGA_BLANK; 330 | oVGA_SYNC <= mVGA_SYNC; 331 | oVGA_H_SYNC <= mVGA_H_SYNC; 332 | oVGA_V_SYNC <= mVGA_V_SYNC; 333 | end 334 | end 335 | 336 | 337 | 338 | // Pixel LUT Address Generator 339 | always@(posedge iCLK or negedge iRST_N) 340 | begin 341 | if(!iRST_N) 342 | oRequest <= 0; 343 | else 344 | begin 345 | if( H_Cont>=X_START-2 && H_Cont=Y_START && V_Cont 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /v/sdram_pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_pll.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.ppf"] 6 | -------------------------------------------------------------------------------- /v/sdram_pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: sdram_pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 9.1 Build 350 03/24/2010 SP 2 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2010 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module sdram_pll ( 40 | inclk0, 41 | c0, 42 | c1, 43 | c2, 44 | c3, 45 | c4); 46 | 47 | input inclk0; 48 | output c0; 49 | output c1; 50 | output c2; 51 | output c3; 52 | output c4; 53 | 54 | wire [4:0] sub_wire0; 55 | wire [0:0] sub_wire8 = 1'h0; 56 | wire [4:4] sub_wire5 = sub_wire0[4:4]; 57 | wire [3:3] sub_wire4 = sub_wire0[3:3]; 58 | wire [2:2] sub_wire3 = sub_wire0[2:2]; 59 | wire [1:1] sub_wire2 = sub_wire0[1:1]; 60 | wire [0:0] sub_wire1 = sub_wire0[0:0]; 61 | wire c0 = sub_wire1; 62 | wire c1 = sub_wire2; 63 | wire c2 = sub_wire3; 64 | wire c3 = sub_wire4; 65 | wire c4 = sub_wire5; 66 | wire sub_wire6 = inclk0; 67 | wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; 68 | 69 | altpll altpll_component ( 70 | .inclk (sub_wire7), 71 | .clk (sub_wire0), 72 | .activeclock (), 73 | .areset (1'b0), 74 | .clkbad (), 75 | .clkena ({6{1'b1}}), 76 | .clkloss (), 77 | .clkswitch (1'b0), 78 | .configupdate (1'b0), 79 | .enable0 (), 80 | .enable1 (), 81 | .extclk (), 82 | .extclkena ({4{1'b1}}), 83 | .fbin (1'b1), 84 | .fbmimicbidir (), 85 | .fbout (), 86 | .fref (), 87 | .icdrclk (), 88 | .locked (), 89 | .pfdena (1'b1), 90 | .phasecounterselect ({4{1'b1}}), 91 | .phasedone (), 92 | .phasestep (1'b1), 93 | .phaseupdown (1'b1), 94 | .pllena (1'b1), 95 | .scanaclr (1'b0), 96 | .scanclk (1'b0), 97 | .scanclkena (1'b1), 98 | .scandata (1'b0), 99 | .scandataout (), 100 | .scandone (), 101 | .scanread (1'b0), 102 | .scanwrite (1'b0), 103 | .sclkout0 (), 104 | .sclkout1 (), 105 | .vcooverrange (), 106 | .vcounderrange ()); 107 | defparam 108 | altpll_component.bandwidth_type = "AUTO", 109 | altpll_component.clk0_divide_by = 1, 110 | altpll_component.clk0_duty_cycle = 50, 111 | altpll_component.clk0_multiply_by = 2, 112 | altpll_component.clk0_phase_shift = "0", 113 | altpll_component.clk1_divide_by = 1, 114 | altpll_component.clk1_duty_cycle = 50, 115 | altpll_component.clk1_multiply_by = 2, 116 | altpll_component.clk1_phase_shift = "-3000", 117 | altpll_component.clk2_divide_by = 2, 118 | altpll_component.clk2_duty_cycle = 50, 119 | altpll_component.clk2_multiply_by = 1, 120 | altpll_component.clk2_phase_shift = "0", 121 | altpll_component.clk3_divide_by = 2, 122 | altpll_component.clk3_duty_cycle = 50, 123 | altpll_component.clk3_multiply_by = 1, 124 | altpll_component.clk3_phase_shift = "0", 125 | altpll_component.clk4_divide_by = 5, 126 | altpll_component.clk4_duty_cycle = 50, 127 | altpll_component.clk4_multiply_by = 4, 128 | altpll_component.clk4_phase_shift = "0", 129 | altpll_component.compensate_clock = "CLK0", 130 | altpll_component.inclk0_input_frequency = 20000, 131 | altpll_component.intended_device_family = "Cyclone IV E", 132 | altpll_component.lpm_type = "altpll", 133 | altpll_component.operation_mode = "NORMAL", 134 | altpll_component.pll_type = "AUTO", 135 | altpll_component.port_activeclock = "PORT_UNUSED", 136 | altpll_component.port_areset = "PORT_UNUSED", 137 | altpll_component.port_clkbad0 = "PORT_UNUSED", 138 | altpll_component.port_clkbad1 = "PORT_UNUSED", 139 | altpll_component.port_clkloss = "PORT_UNUSED", 140 | altpll_component.port_clkswitch = "PORT_UNUSED", 141 | altpll_component.port_configupdate = "PORT_UNUSED", 142 | altpll_component.port_fbin = "PORT_UNUSED", 143 | altpll_component.port_inclk0 = "PORT_USED", 144 | altpll_component.port_inclk1 = "PORT_UNUSED", 145 | altpll_component.port_locked = "PORT_UNUSED", 146 | altpll_component.port_pfdena = "PORT_UNUSED", 147 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 148 | altpll_component.port_phasedone = "PORT_UNUSED", 149 | altpll_component.port_phasestep = "PORT_UNUSED", 150 | altpll_component.port_phaseupdown = "PORT_UNUSED", 151 | altpll_component.port_pllena = "PORT_UNUSED", 152 | altpll_component.port_scanaclr = "PORT_UNUSED", 153 | altpll_component.port_scanclk = "PORT_UNUSED", 154 | altpll_component.port_scanclkena = "PORT_UNUSED", 155 | altpll_component.port_scandata = "PORT_UNUSED", 156 | altpll_component.port_scandataout = "PORT_UNUSED", 157 | altpll_component.port_scandone = "PORT_UNUSED", 158 | altpll_component.port_scanread = "PORT_UNUSED", 159 | altpll_component.port_scanwrite = "PORT_UNUSED", 160 | altpll_component.port_clk0 = "PORT_USED", 161 | altpll_component.port_clk1 = "PORT_USED", 162 | altpll_component.port_clk2 = "PORT_USED", 163 | altpll_component.port_clk3 = "PORT_USED", 164 | altpll_component.port_clk4 = "PORT_USED", 165 | altpll_component.port_clk5 = "PORT_UNUSED", 166 | altpll_component.port_clkena0 = "PORT_UNUSED", 167 | altpll_component.port_clkena1 = "PORT_UNUSED", 168 | altpll_component.port_clkena2 = "PORT_UNUSED", 169 | altpll_component.port_clkena3 = "PORT_UNUSED", 170 | altpll_component.port_clkena4 = "PORT_UNUSED", 171 | altpll_component.port_clkena5 = "PORT_UNUSED", 172 | altpll_component.port_extclk0 = "PORT_UNUSED", 173 | altpll_component.port_extclk1 = "PORT_UNUSED", 174 | altpll_component.port_extclk2 = "PORT_UNUSED", 175 | altpll_component.port_extclk3 = "PORT_UNUSED", 176 | altpll_component.width_clock = 5; 177 | 178 | 179 | endmodule 180 | 181 | // ============================================================ 182 | // CNX file retrieval info 183 | // ============================================================ 184 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 185 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 186 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 187 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 188 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 189 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 190 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 191 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 192 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 193 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" 194 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 195 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 196 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 197 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 198 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" 199 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" 200 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" 201 | // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" 202 | // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" 203 | // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" 204 | // Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" 205 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 206 | // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" 207 | // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" 208 | // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" 209 | // Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" 210 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" 211 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" 212 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000" 213 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000" 214 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "40.000000" 215 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 216 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 217 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 218 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 219 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 220 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 221 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 222 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 223 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 224 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 225 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 226 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 227 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 228 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 229 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 230 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 231 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 232 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000" 233 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 234 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 235 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" 236 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" 237 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" 238 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" 239 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 240 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 241 | // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" 242 | // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" 243 | // Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" 244 | // Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" 245 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" 246 | // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "10" 247 | // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" 248 | // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" 249 | // Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1" 250 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 251 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" 252 | // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" 253 | // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" 254 | // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "25.00000000" 255 | // Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "40.00000000" 256 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" 257 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" 258 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" 259 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" 260 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1" 261 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 262 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" 263 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" 264 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" 265 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" 266 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 267 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 268 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 269 | // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-108.00000000" 270 | // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" 271 | // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" 272 | // Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" 273 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 274 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 275 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" 276 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" 277 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" 278 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps" 279 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 280 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 281 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 282 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 283 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 284 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 285 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 286 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 287 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 288 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 289 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif" 290 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 291 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 292 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 293 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 294 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 295 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 296 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 297 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 298 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 299 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 300 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 301 | // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" 302 | // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" 303 | // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" 304 | // Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" 305 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 306 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 307 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 308 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 309 | // Retrieval info: PRIVATE: USE_CLK1 STRING "1" 310 | // Retrieval info: PRIVATE: USE_CLK2 STRING "1" 311 | // Retrieval info: PRIVATE: USE_CLK3 STRING "1" 312 | // Retrieval info: PRIVATE: USE_CLK4 STRING "1" 313 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 314 | // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" 315 | // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" 316 | // Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" 317 | // Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" 318 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 319 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 320 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 321 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 322 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 323 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 324 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" 325 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 326 | // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" 327 | // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" 328 | // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" 329 | // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000" 330 | // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2" 331 | // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" 332 | // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" 333 | // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" 334 | // Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2" 335 | // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" 336 | // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" 337 | // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" 338 | // Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "5" 339 | // Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" 340 | // Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "4" 341 | // Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" 342 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 343 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 344 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 345 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 346 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 347 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 348 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 349 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 350 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 351 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 352 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 353 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 354 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 355 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 356 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 357 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 358 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 359 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 360 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 361 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 362 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 363 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 364 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 365 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 366 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 367 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 368 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 369 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 370 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 371 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 372 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 373 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 374 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" 375 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" 376 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" 377 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" 378 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 379 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 380 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 381 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 382 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 383 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 384 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 385 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 386 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 387 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 388 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 389 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 390 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 391 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 392 | // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" 393 | // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" 394 | // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" 395 | // Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" 396 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 397 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 398 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 399 | // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 400 | // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 401 | // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 402 | // Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 403 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 404 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE 405 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE 406 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE 407 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE 408 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE FALSE 409 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE 410 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE 411 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE 412 | // Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE 413 | // Retrieval info: LIB_FILE: altera_mf 414 | -------------------------------------------------------------------------------- /v/vga_pll.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2007 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 248 160) 24 | (text "vga_pll" (rect 105 0 151 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 144 25 156)(font "Arial" )) 26 | (port 27 | (pt 0 64) 28 | (input) 29 | (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) 30 | (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8))) 31 | (line (pt 0 64)(pt 48 64)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 80) 35 | (input) 36 | (text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8))) 37 | (text "areset" (rect 4 67 32 80)(font "Arial" (font_size 8))) 38 | (line (pt 0 80)(pt 48 80)(line_width 1)) 39 | ) 40 | (port 41 | (pt 248 64) 42 | (output) 43 | (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) 44 | (text "c0" (rect 233 51 244 64)(font "Arial" (font_size 8))) 45 | (line (pt 248 64)(pt 216 64)(line_width 1)) 46 | ) 47 | (drawing 48 | (text "Cyclone II" (rect 191 145 235 157)(font "Arial" )) 49 | (text "inclk0 frequency: 27.000 MHz" (rect 58 59 183 71)(font "Arial" )) 50 | (text "Operation Mode: Normal" (rect 58 73 159 85)(font "Arial" )) 51 | (text "Clk " (rect 59 96 76 108)(font "Arial" )) 52 | (text "Ratio" (rect 81 96 103 108)(font "Arial" )) 53 | (text "Ph (dg)" (rect 108 96 138 108)(font "Arial" )) 54 | (text "DC (%)" (rect 143 96 174 108)(font "Arial" )) 55 | (text "c0" (rect 62 111 72 123)(font "Arial" )) 56 | (text "4/1" (rect 86 111 99 123)(font "Arial" )) 57 | (text "0.00" (rect 114 111 132 123)(font "Arial" )) 58 | (text "50.00" (rect 147 111 170 123)(font "Arial" )) 59 | (line (pt 0 0)(pt 249 0)(line_width 1)) 60 | (line (pt 249 0)(pt 249 161)(line_width 1)) 61 | (line (pt 0 161)(pt 249 161)(line_width 1)) 62 | (line (pt 0 0)(pt 0 161)(line_width 1)) 63 | (line (pt 56 94)(pt 176 94)(line_width 1)) 64 | (line (pt 56 108)(pt 176 108)(line_width 1)) 65 | (line (pt 56 123)(pt 176 123)(line_width 1)) 66 | (line (pt 56 94)(pt 56 123)(line_width 1)) 67 | (line (pt 78 94)(pt 78 123)(line_width 3)) 68 | (line (pt 105 94)(pt 105 123)(line_width 3)) 69 | (line (pt 140 94)(pt 140 123)(line_width 3)) 70 | (line (pt 175 94)(pt 175 123)(line_width 1)) 71 | (line (pt 48 48)(pt 216 48)(line_width 1)) 72 | (line (pt 216 48)(pt 216 144)(line_width 1)) 73 | (line (pt 48 144)(pt 216 144)(line_width 1)) 74 | (line (pt 48 48)(pt 48 144)(line_width 1)) 75 | ) 76 | ) 77 | -------------------------------------------------------------------------------- /v/vga_pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | --------------------------------------------------------------------------------