├── LICENSE ├── README.md ├── extras ├── Makefile ├── README ├── example.v ├── icebreaker.pcf ├── rs232demo.v ├── rs232demo_tb.v └── stopwatch.v ├── setup_windows.md ├── summon-fpga-tools.sh ├── wtfpga-lab-solution ├── .gitignore ├── Makefile ├── clkdiv.v ├── icebreaker.pcf ├── main.mk ├── seven_seg_hex.v ├── seven_seg_mux.v └── wtfpga.v ├── wtfpga ├── .gitignore ├── Makefile ├── clkdiv.v ├── icebreaker.pcf ├── main.mk ├── seven_seg_hex.v ├── seven_seg_mux.v └── wtfpga.v └── wtfpgamanual.pdf /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. 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If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | DISCLAIMER 2 | ========== 3 | 4 | This workshop is outdated. There is a more up to date [iCEBreaker FPGA workshop](https://github.com/icebreaker-fpga/icebreaker-workshop). 5 | 6 | WTFpga 7 | ====== 8 | 2 hour crash course in FPGAs and Verilog 9 | 10 | Purpose 11 | ======= 12 | The purpose of this workshop is to jumpstart people new to FPGAs, getting them to the point where they can understand and make minor changes to Verilog designs, and see the results on hardware. 13 | 14 | When delivered as a workshop, laptops have Vivado preinstalled and the project preloaded so that attendees can get straight to toggling switches and flashing LEDs. 15 | 16 | The scope is intentionally limited to make sure it's doable in a couple hours time, so that attendees don't need to make a huge time commitment to get a hands-on understanding of FPGAs and Verilog 17 | 18 | What's not covered 19 | ================== 20 | To keep it simple, I skip over: 21 | 1. Toolchain Setup 22 | 2. Synchronous Logic 23 | 3. IP cores 24 | 4. Simulation 25 | 5. Testbenches 26 | 27 | ... and probably lots more things you'll want to be sure to learn more about once you get started. 28 | 29 | Changes 30 | ======= 31 | Version 1.0 targeted a generic Xilinx XC3S200A FPGA board using Xilinx ISE tools. Posted 2014 32 | 33 | Version 2.0 is significantly updated, targeting a Digilent Basys 3 board and Xilinx Vivado. Posted 2018 34 | 35 | Version 3.0 targetting the iCEBreaker dev board and using fully open source sythesis flow. Posted late 2018 36 | 37 | DIY 38 | === 39 | If you'd like to do the V3.0 workshop on your own, using the iCEBreaker dev board and tools, before you start, you'll need to: 40 | 41 | 1. Install icestudio, nextpnr-ice40, yosys. For the information on how to install them refer to http://www.clifford.at/icestorm/#install 42 | 43 | 2. Aquire a 1BitSquared iCEBreaker board and the iCEBreaker 7segment 44 | display and DIP switch PMOD 45 | boards. https://github.com/icebreaker-fpga/icebreaker https://github.com/icebreaker-fpga/icebreaker-pmod 46 | 47 | 3. Attach the 7 segment board to iCEBreaker port P1A, and attach the DIP switch board to iCEBreaker port P1B. 48 | 49 | 4. Walk through the pdf manual included. `pdfbook2 --paper=letter --inner-margin=0 wtfpgamanual.pdf` should prepare it for printing as a booklet if you prefer. 50 | 51 | 52 | Derivative use 53 | ============== 54 | Please use and distribute this material! If you need a more permissive license let me know! 55 | -------------------------------------------------------------------------------- /extras/Makefile: -------------------------------------------------------------------------------- 1 | PROJ = example 2 | # PROJ = rs232demo 3 | # PROJ = stopwatch 4 | 5 | all: $(PROJ).rpt $(PROJ).bin 6 | 7 | %.json: %.v 8 | yosys -p 'synth_ice40 -top top -json $@' $< 9 | 10 | %.asc: %.json icebreaker.pcf 11 | nextpnr-ice40 --up5k --freq 12 --asc $@ --pcf icebreaker.pcf --json $< 12 | 13 | %.bin: %.asc 14 | icepack $< $@ 15 | 16 | %.rpt: %.asc 17 | icetime -d up5k -mtr $@ $< 18 | 19 | %_tb: %_tb.v %.v 20 | iverilog -o $@ $^ 21 | 22 | %_tb.vcd: %_tb 23 | vvp -N $< +vcd=$@ 24 | 25 | %_syn.v: %.json 26 | yosys -p 'read_json $^; write_verilog $@' 27 | 28 | %_syntb: %_tb.v %_syn.v 29 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 30 | 31 | %_syntb.vcd: %_syntb 32 | vvp -N $< +vcd=$@ 33 | 34 | prog: $(PROJ).bin 35 | iceprog $< 36 | 37 | sudo-prog: $(PROJ).bin 38 | @echo 'Executing prog as root!!!' 39 | sudo iceprog $< 40 | 41 | clean: 42 | rm -f $(PROJ).json $(PROJ).asc $(PROJ).rpt $(PROJ).bin 43 | rm -f $(PROJ)_tb $(PROJ)_tb.vcd $(PROJ)_syn.v $(PROJ)_syntb $(PROJ)_syntb.vcd 44 | 45 | .SECONDARY: 46 | .PHONY: all prog clean 47 | -------------------------------------------------------------------------------- /extras/README: -------------------------------------------------------------------------------- 1 | Simple example for the iCEbreaker dev board: 2 | https://github.com/esden/icebreaker/ 3 | -------------------------------------------------------------------------------- /extras/example.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input CLK, 3 | 4 | output LED1, 5 | output LED2, 6 | output LED3, 7 | output LED4, 8 | output LED5, 9 | 10 | input BTN_N, 11 | input BTN1, 12 | input BTN2, 13 | input BTN3 14 | ); 15 | 16 | localparam BITS = 5; 17 | localparam LOG2DELAY = 22; 18 | 19 | reg [BITS+LOG2DELAY-1:0] counter = 0; 20 | reg [BITS-1:0] outcnt; 21 | 22 | always @(posedge CLK) begin 23 | counter <= counter + {!BTN_N, BTN1, BTN2, BTN3} + 1; 24 | outcnt <= counter >> LOG2DELAY; 25 | end 26 | 27 | assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1); 28 | endmodule 29 | -------------------------------------------------------------------------------- /extras/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RS232 5 | set_io -nowarn RX 6 6 | set_io -nowarn TX 9 7 | 8 | # LEDs and Button 9 | set_io -nowarn BTN_N 10 10 | set_io -nowarn LEDR_N 11 11 | set_io -nowarn LEDG_N 37 12 | 13 | # RGB LED Driver 14 | set_io -nowarn LED_RED_N 39 15 | set_io -nowarn LED_GRN_N 40 16 | set_io -nowarn LED_BLU_N 41 17 | 18 | # SPI Flash 19 | set_io -nowarn FLASH_SCK 15 20 | set_io -nowarn FLASH_SSB 16 21 | set_io -nowarn FLASH_IO0 14 22 | set_io -nowarn FLASH_IO1 17 23 | set_io -nowarn FLASH_IO2 12 24 | set_io -nowarn FLASH_IO3 13 25 | 26 | # PMOD 1A 27 | set_io -nowarn P1A1 4 28 | set_io -nowarn P1A2 2 29 | set_io -nowarn P1A3 47 30 | set_io -nowarn P1A4 45 31 | set_io -nowarn P1A7 3 32 | set_io -nowarn P1A8 48 33 | set_io -nowarn P1A9 46 34 | set_io -nowarn P1A10 44 35 | 36 | # PMOD 1B 37 | set_io -nowarn P1B1 43 38 | set_io -nowarn P1B2 38 39 | set_io -nowarn P1B3 34 40 | set_io -nowarn P1B4 31 41 | set_io -nowarn P1B7 42 42 | set_io -nowarn P1B8 36 43 | set_io -nowarn P1B9 32 44 | set_io -nowarn P1B10 28 45 | 46 | # LEDs and Buttons (PMOD 2) 47 | set_io -nowarn LED1 26 48 | set_io -nowarn LED2 27 49 | set_io -nowarn LED3 25 50 | set_io -nowarn LED4 23 51 | set_io -nowarn LED5 21 52 | set_io -nowarn BTN1 20 53 | set_io -nowarn BTN2 19 54 | set_io -nowarn BTN3 18 55 | -------------------------------------------------------------------------------- /extras/rs232demo.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input CLK, 3 | input RX, 4 | output TX, 5 | output reg LED1, 6 | output reg LED2, 7 | output reg LED3, 8 | output reg LED4, 9 | output reg LED5 10 | ); 11 | parameter integer BAUD_RATE = 9600; 12 | parameter integer CLOCK_FREQ_HZ = 12000000; 13 | localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE); 14 | 15 | reg [7:0] buffer; 16 | reg buffer_valid; 17 | 18 | reg [$clog2(3*HALF_PERIOD):0] cycle_cnt; 19 | reg [3:0] bit_cnt = 0; 20 | reg recv = 0; 21 | 22 | initial begin 23 | LED1 = 0; 24 | LED2 = 0; 25 | LED3 = 0; 26 | LED4 = 0; 27 | LED5 = 0; 28 | end 29 | 30 | always @(posedge CLK) begin 31 | buffer_valid <= 0; 32 | if (!recv) begin 33 | if (!RX) begin 34 | cycle_cnt <= HALF_PERIOD; 35 | bit_cnt <= 0; 36 | recv <= 1; 37 | end 38 | end else begin 39 | if (cycle_cnt == 2*HALF_PERIOD) begin 40 | cycle_cnt <= 0; 41 | bit_cnt <= bit_cnt + 1; 42 | if (bit_cnt == 9) begin 43 | buffer_valid <= 1; 44 | recv <= 0; 45 | end else begin 46 | buffer <= {RX, buffer[7:1]}; 47 | end 48 | end else begin 49 | cycle_cnt <= cycle_cnt + 1; 50 | end 51 | end 52 | end 53 | 54 | always @(posedge CLK) begin 55 | if (buffer_valid) begin 56 | if (buffer == "1") LED1 <= !LED1; 57 | if (buffer == "2") LED2 <= !LED2; 58 | if (buffer == "3") LED3 <= !LED3; 59 | if (buffer == "4") LED4 <= !LED4; 60 | if (buffer == "5") LED5 <= !LED5; 61 | end 62 | end 63 | 64 | assign TX = RX; 65 | endmodule 66 | -------------------------------------------------------------------------------- /extras/rs232demo_tb.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | localparam integer PERIOD = 12000000 / 9600; 3 | 4 | reg CLK; 5 | always #5 CLK = (CLK === 1'b0); 6 | 7 | reg RX = 1; 8 | wire TX; 9 | wire LED1; 10 | wire LED2; 11 | wire LED3; 12 | wire LED4; 13 | wire LED5; 14 | 15 | top uut ( 16 | .CLK (CLK ), 17 | .RX (RX ), 18 | .TX (TX ), 19 | .LED1(LED1), 20 | .LED2(LED2), 21 | .LED3(LED3), 22 | .LED4(LED4), 23 | .LED5(LED5) 24 | ); 25 | 26 | task send_byte; 27 | input [7:0] c; 28 | integer i; 29 | begin 30 | RX <= 0; 31 | repeat (PERIOD) @(posedge CLK); 32 | 33 | for (i = 0; i < 8; i = i+1) begin 34 | RX <= c[i]; 35 | repeat (PERIOD) @(posedge CLK); 36 | end 37 | 38 | RX <= 1; 39 | repeat (PERIOD) @(posedge CLK); 40 | end 41 | endtask 42 | 43 | reg [4095:0] vcdfile; 44 | 45 | initial begin 46 | if ($value$plusargs("vcd=%s", vcdfile)) begin 47 | $dumpfile(vcdfile); 48 | $dumpvars(0, testbench); 49 | end 50 | 51 | repeat (10 * PERIOD) @(posedge CLK); 52 | 53 | // turn all LEDs on 54 | send_byte("1"); 55 | send_byte("2"); 56 | send_byte("3"); 57 | send_byte("4"); 58 | send_byte("5"); 59 | 60 | // turn all LEDs off 61 | send_byte("1"); 62 | send_byte("2"); 63 | send_byte("3"); 64 | send_byte("4"); 65 | send_byte("5"); 66 | 67 | repeat (10 * PERIOD) @(posedge CLK); 68 | 69 | $finish; 70 | end 71 | endmodule 72 | -------------------------------------------------------------------------------- /extras/stopwatch.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input CLK, 3 | input BTN_N, BTN1, BTN2, BTN3, 4 | output LED1, LED2, LED3, LED4, LED5, 5 | output P1A1, P1A2, P1A3, P1A4, P1A7, P1A8, P1A9, P1A10, 6 | output P1B1, P1B2, P1B3, P1B4, P1B7, P1B8, P1B9, P1B10 7 | ); 8 | wire [7:0] ss_top, ss_bot; 9 | reg [7:0] disp_top = 0, disp_bot = 0; 10 | reg [7:0] lap_top = 0, lap_bot = 0; 11 | reg [7:0] lap_timeout = 0; 12 | 13 | wire [7:0] disp_top_inc, disp_bot_inc; 14 | 15 | assign { P1A10, P1A9, P1A8, P1A7, P1A4, P1A3, P1A2, P1A1 } = ss_top; 16 | assign { P1B10, P1B9, P1B8, P1B7, P1B4, P1B3, P1B2, P1B1 } = ss_bot; 17 | 18 | reg [20:0] clkdiv = 0; 19 | reg clkdiv_pulse = 0; 20 | 21 | reg running = 0; 22 | 23 | always @(posedge CLK) begin 24 | if (clkdiv == 120000) begin 25 | clkdiv <= 0; 26 | clkdiv_pulse <= 1; 27 | end else begin 28 | clkdiv <= clkdiv + 1; 29 | clkdiv_pulse <= 0; 30 | end 31 | 32 | if (clkdiv_pulse && running) begin 33 | {disp_top, disp_bot} <= {disp_top_inc, disp_bot_inc}; 34 | end 35 | 36 | if (clkdiv_pulse && lap_timeout) begin 37 | lap_timeout <= lap_timeout - 1; 38 | end 39 | 40 | // left button: start 41 | if (BTN3) begin 42 | running <= 1; 43 | end 44 | 45 | // center button: lap 46 | if (BTN2) begin 47 | lap_top <= disp_top; 48 | lap_bot <= disp_bot; 49 | lap_timeout <= 200; 50 | end 51 | 52 | // right button: stop 53 | if (BTN1) begin 54 | running <= 0; 55 | end 56 | 57 | // reset 58 | if (!BTN_N) begin 59 | {disp_top, disp_bot} <= 0; 60 | running <= 0; 61 | end 62 | end 63 | 64 | seven_seg_ctrl ss_ctrl_top ( 65 | .CLK(CLK), 66 | .din(lap_timeout ? lap_top : disp_top), 67 | .dout(ss_top) 68 | ); 69 | 70 | seven_seg_ctrl ss_ctrl_bot ( 71 | .CLK(CLK), 72 | .din(lap_timeout ? lap_bot : disp_bot), 73 | .dout(ss_bot) 74 | ); 75 | 76 | bcd16_increment bot_inc ( 77 | .din({disp_top, disp_bot}), 78 | .dout({disp_top_inc, disp_bot_inc}) 79 | ); 80 | endmodule 81 | 82 | module bcd16_increment ( 83 | input [15:0] din, 84 | output reg [15:0] dout 85 | ); 86 | always @* begin 87 | case (1'b1) 88 | din[15:0] == 16'h 9999: 89 | dout = 0; 90 | din[11:0] == 12'h 999: 91 | dout = {din[15:12] + 4'd 1, 12'h 000}; 92 | din[7:0] == 8'h 99: 93 | dout = {din[15:12], din[11:8] + 4'd 1, 8'h 00}; 94 | din[3:0] == 4'h 9: 95 | dout = {din[15:8], din[7:4] + 4'd 1, 4'h 0}; 96 | default: 97 | dout = {din[15:4], din[3:0] + 4'd 1}; 98 | endcase 99 | end 100 | endmodule 101 | 102 | module seven_seg_ctrl ( 103 | input CLK, 104 | input [7:0] din, 105 | output reg [7:0] dout 106 | ); 107 | wire [6:0] lsb_digit; 108 | wire [6:0] msb_digit; 109 | 110 | seven_seg_hex msb_nibble ( 111 | .din(din[7:4]), 112 | .dout(msb_digit) 113 | ); 114 | 115 | seven_seg_hex lsb_nibble ( 116 | .din(din[3:0]), 117 | .dout(lsb_digit) 118 | ); 119 | 120 | reg [9:0] clkdiv = 0; 121 | reg clkdiv_pulse = 0; 122 | reg msb_not_lsb = 0; 123 | 124 | always @(posedge CLK) begin 125 | clkdiv <= clkdiv + 1; 126 | clkdiv_pulse <= &clkdiv; 127 | msb_not_lsb <= msb_not_lsb ^ clkdiv_pulse; 128 | 129 | if (clkdiv_pulse) begin 130 | if (msb_not_lsb) begin 131 | dout[6:0] <= ~msb_digit; 132 | dout[7] <= 0; 133 | end else begin 134 | dout[6:0] <= ~lsb_digit; 135 | dout[7] <= 1; 136 | end 137 | end 138 | end 139 | endmodule 140 | 141 | module seven_seg_hex ( 142 | input [3:0] din, 143 | output reg [6:0] dout 144 | ); 145 | always @* 146 | case (din) 147 | 4'h0: dout = 7'b 0111111; 148 | 4'h1: dout = 7'b 0000110; 149 | 4'h2: dout = 7'b 1011011; 150 | 4'h3: dout = 7'b 1001111; 151 | 4'h4: dout = 7'b 1100110; 152 | 4'h5: dout = 7'b 1101101; 153 | 4'h6: dout = 7'b 1111101; 154 | 4'h7: dout = 7'b 0000111; 155 | 4'h8: dout = 7'b 1111111; 156 | 4'h9: dout = 7'b 1101111; 157 | 4'hA: dout = 7'b 1110111; 158 | 4'hB: dout = 7'b 1111100; 159 | 4'hC: dout = 7'b 0111001; 160 | 4'hD: dout = 7'b 1011110; 161 | 4'hE: dout = 7'b 1111001; 162 | 4'hF: dout = 7'b 1110001; 163 | endcase 164 | endmodule 165 | -------------------------------------------------------------------------------- /setup_windows.md: -------------------------------------------------------------------------------- 1 | iCEBreaker development on Windows 2 | ====== 3 | 4 | *1. Get the toolchain* (icestudio, nextpnr-ice40, yosys, make, iceprog) 5 | 6 | The Fomu project (https://fomu.im/) has a ready-to-use download to be used on Windows. Get it at https://github.com/im-tomu/fomu-toolchain, extract it and add the bin directory to your PATH (details are explained there). 7 | 8 | *2. Install USB driver* 9 | 10 | iceprog uses libusb. In order to get it working, you need to enable the correct driver: 11 | 12 | * Download and run the Zadig tool from https://zadig.akeo.ie/ 13 | * Connect the iCEBreaker board to your computer with a USB cable 14 | * Select Options->List all devices in Zadig 15 | * Select "iCEBreaker Vx.x (interface 0)" from the drop down 16 | * Select "libusbK" driver 17 | * Press "Replace driver" 18 | * Close Zadig 19 | 20 | You are now ready to use your iCEBreaker board. You can skip the WTFpga section on setup, the only thing you need is cloning the WTFpga git repository. 21 | 22 | -------------------------------------------------------------------------------- /summon-fpga-tools.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # Summon FPGA Tools build script 4 | # Written by Piotr Esden-Tempski , released as public domain. 5 | # 6 | # To the extent possible under law, the author(s) have dedicated all copyright 7 | # and related and neighboring rights to this software to the public domain 8 | # worldwide. This software is distributed without any warranty. 9 | # 10 | # You should have received a copy of the CC0 Public Domain Dedication along 11 | # with this software. If not, see . 12 | 13 | # 14 | # TODO: this should be automatically detected and the deps should be installed when needed. 15 | # 16 | # Requirements (example is for Debian, replace package names as needed): 17 | # 18 | # apt-get install flex bison libgmp3-dev libmpfr-dev libncurses5-dev \ 19 | # libmpc-dev autoconf texinfo build-essential libftdi-dev zlib1g-dev git \ 20 | # gperf 21 | # 22 | # Or on Ubuntu Maverick give `apt-get build-dep gcc-4.5` a try. 23 | # 24 | # brew install cmake python boost boost-python3 qt5 gperf 25 | # 26 | 27 | # Stop if any command fails 28 | set -e 29 | 30 | ############################################################################## 31 | # Default settings section 32 | # You probably want to customize those 33 | # You can also pass them as parameters to the script 34 | ############################################################################## 35 | PREFIX=${HOME}/sft # Install location of your final fpga tools 36 | # We do not support MacPorts only homebrew for the time being... 37 | #DARWIN_OPT_PATH=/usr/local # Path in which MacPorts or Fink is installed 38 | # Set to 'sudo' if you need superuser privileges while installing 39 | SUDO= 40 | # Set to 1 to be quieter while running 41 | QUIET=0 42 | # Set to 'master' or a git revision number to use instead of stable version 43 | ICESTORM_EN=1 44 | ICESTORM_GIT=master 45 | ARACHNEPNR_EN=1 46 | ARACHNEPNR_GIT=master 47 | NEXTPNR_EN=1 48 | NEXTPNR_GIT=master 49 | YOSYS_EN=1 50 | YOSYS_GIT=master 51 | IVERILOG_EN=1 52 | IVERILOG_GIT=v10-branch 53 | 54 | # Override automatic detection of cpus to compile on 55 | CPUS= 56 | 57 | # FTP options ... some environments do not support non-passive FTP 58 | # FETCH_NO_PASSIVE="--no-passive-ftp " 59 | FETCH_NO_CERTCHECK="--no-check-certificate " 60 | 61 | ############################################################################## 62 | # Parsing command line parameters 63 | ############################################################################## 64 | 65 | while [ $# -gt 0 ]; do 66 | case $1 in 67 | PREFIX=*) 68 | PREFIX=$(echo $1 | sed 's,^PREFIX=,,') 69 | ;; 70 | SUDO=*) 71 | SUDO=$(echo $1 | sed 's,^SUDO=,,') 72 | ;; 73 | QUIET=*) 74 | QUIET=$(echo $1 | sed 's,^QUIET=,,') 75 | ;; 76 | ICESTORM_GIT=*) 77 | ICESTORM_GIT=$(echo $1 | sed 's,^ICESTORM_GIT=,,') 78 | ;; 79 | ARACHNEPNR_GIT=*) 80 | ARACHNEPNR_GIT=$(echo $1 | sed 's,^ARACHNEPNR_GIT=,,') 81 | ;; 82 | NEXTPNR_GIT=*) 83 | NEXTPNR_GIT=$(echo $1 | sed 's,^NEXTPNR_GIT=,,') 84 | ;; 85 | YOSYS_GIT=*) 86 | YOSYS_GIT=$(echo $1 | sed 's,^YOSYS_GIT=,,') 87 | ;; 88 | IVERILOG_GIT=*) 89 | IVERILOG_GIT=$(echo $1 | sed 's,^IVERILOG_GIT=,,') 90 | ;; 91 | CPUS=*) 92 | CPUS=$(echo $1 | sed 's,^CPUS=,,') 93 | ;; 94 | *) 95 | echo "Unknown parameter: $1" 96 | exit 1 97 | ;; 98 | esac 99 | 100 | shift # shifting parameter list to access the next one 101 | done 102 | 103 | ############################################################################## 104 | # Version and download url settings section 105 | ############################################################################## 106 | 107 | DEFAULT_ICESTORM= 108 | DEFAULT_ARACHNEPNR= 109 | DEFAULT_NEXTPNR= 110 | DEFAULT_YOSYS=yosys-0.8 111 | DEFAULT_IVERILOG_VERSION=v10_2 112 | DEFAULT_IVERILOG=iverilog-${DEFAULT_IVERILOG_VERSION} 113 | 114 | ICESTORM=${ICESTORM:-${DEFAULT_ICESTORM}} 115 | ARACHNEPNR=${ARACHNEPNR:-${DEFAULT_ARACHNEPNR}} 116 | NEXTPNR=${NEXTPNR:-${DEFAULT_NEXTPNR}} 117 | YOSYS=${YOSYS:-${DEFAULT_YOSYS}}${IVERILOG} 118 | IVERILOG_VERSION=${IVERILOG_VERSION:-${DEFAULT_IVERILOG_VERSION}} 119 | IVERILOG=${IVERILOG:-${DEFAULT_IVERILOG}} 120 | 121 | ############################################################################## 122 | # Print settings 123 | ############################################################################## 124 | 125 | echo "Settings used for this build are:" 126 | echo "PREFIX=$PREFIX" 127 | echo "SUDO=$SUDO" 128 | echo "QUIET=$QUIET" 129 | echo "ICESTORM=$ICESTORM" 130 | echo "ICESTORM_GIT=$ICESTORM_GIT" 131 | echo "ARACHNEPNR=$ARACHNEPNR" 132 | echo "ARACHNEPNR_GIT=$ARACHNEPNR_GIT" 133 | echo "NEXTPNR=$NEXTPNR" 134 | echo "NEXTPNR_GIT=$NEXTPNR_GIT" 135 | echo "YOSYS=$YOSYS" 136 | echo "YOSYS_GIT=$YOSYS_GIT" 137 | echo "IVERILOG_VERSION=$IVERILOG_VERSION" 138 | echo "IVERILOG=$IVERILOG" 139 | echo "IVERILOG_GIT=$IVERILOG_GIT" 140 | echo "CPUS=$CPUS" 141 | 142 | ############################################################################## 143 | # Flags section 144 | ############################################################################## 145 | 146 | if [ "x${CPUS}" == "x" ]; then 147 | if which getconf > /dev/null; then 148 | CPUS=$(getconf _NPROCESSORS_ONLN) 149 | else 150 | CPUS=1 151 | fi 152 | 153 | PARALLEL=-j$((CPUS + 1)) 154 | else 155 | PARALLEL=-j${CPUS} 156 | fi 157 | 158 | echo "${CPUS} cpu's detected running make with '${PARALLEL}' flag" 159 | 160 | ICESTORMFLAGS= 161 | ARACHNEPNRFLAGS= 162 | NEXTPNRFLAGS= 163 | YOSYSFLAGS= 164 | 165 | # Pull in the local configuration, if any 166 | if [ -f local.sh ]; then 167 | . ./local.sh 168 | fi 169 | 170 | MAKEFLAGS=${PARALLEL} 171 | TARFLAGS=v 172 | 173 | if [ ${QUIET} != 0 ]; then 174 | TARFLAGS= 175 | MAKEFLAGS="${MAKEFLAGS} -s" 176 | fi 177 | 178 | export PATH="${PREFIX}/bin:${PATH}" 179 | 180 | SUMMON_DIR=$(pwd) 181 | SOURCES=${SUMMON_DIR}/sources 182 | STAMPS=${SUMMON_DIR}/stamps 183 | 184 | 185 | ############################################################################## 186 | # Tool section 187 | ############################################################################## 188 | TAR=tar 189 | 190 | ############################################################################## 191 | # OS and Tooldetection section 192 | # Detects which tools and flags to use 193 | ############################################################################## 194 | 195 | case "$(uname)" in 196 | Linux) 197 | echo "Found Linux OS." 198 | ;; 199 | Darwin) 200 | echo "Found Darwin OS." 201 | QT5_PREFIX="/usr/local/opt/qt5" 202 | PATH="/usr/local/opt/bison/bin:$PATH" 203 | LDFLAGS="-L/usr/local/opt/bison/lib" 204 | ;; 205 | CYGWIN*) 206 | echo "Found CygWin that means Windows most likely." 207 | ;; 208 | *) 209 | echo "Found unknown OS. Aborting!" 210 | exit 1 211 | ;; 212 | esac 213 | 214 | ############################################################################## 215 | # Building section 216 | # You probably don't have to touch anything after this 217 | ############################################################################## 218 | 219 | ############################################################################## 220 | # Helper function definitions 221 | ############################################################################## 222 | 223 | # Fetch a versioned file from a URL 224 | function fetch { 225 | if [ ! -e ${STAMPS}/$1.fetch ]; then 226 | if [ ! -e ${SOURCES}/$1 ]; then 227 | log "Downloading $1 sources..." 228 | if [ "x$3" != "x" ]; then 229 | wget -c ${FETCH_NO_PASSIVE} ${FETCH_NO_CERTCHECK} -O $3 $2 && touch ${STAMPS}/$1.fetch 230 | else 231 | wget -c ${FETCH_NO_PASSIVE} ${FETCH_NO_CERTCHECK} $2 && touch ${STAMPS}/$1.fetch 232 | fi 233 | fi 234 | fi 235 | } 236 | 237 | function clone { 238 | local NAME=$1 239 | local GIT_REF=$2 240 | local GIT_URL=$3 241 | local POST_CLONE=$4 242 | local GIT_SHA=$(git ls-remote ${GIT_URL} ${GIT_REF} | cut -f 1) 243 | 244 | # It seems that the ref is actually a SHA as it could not be found through ls-remote 245 | if [ "x${GIT_SHA}" == "x" ]; then 246 | local GIT_SHA=${GIT_REF} 247 | fi 248 | 249 | # Setting uppercase NAME variable for future use to the source file name 250 | eval $(echo ${NAME} | tr "[:lower:]" "[:upper:]")=${NAME}-${GIT_SHA} 251 | 252 | # Clone the repository and do all necessary operations until we get an archive 253 | if [ ! -e ${STAMPS}/${NAME}-${GIT_SHA}.fetch ]; then 254 | # Making sure there is nothing in our way 255 | if [ -e ${NAME}-${GIT_SHA} ]; then 256 | log "The clone directory ${NAME}-${GIT_SHA} already exists, removing..." 257 | rm -rf ${NAME}-${GIT_SHA} 258 | fi 259 | log "Cloning ${NAME}-${GIT_SHA} ..." 260 | git clone ${GIT_URL} ${NAME}-${GIT_SHA} 261 | cd ${NAME}-${GIT_SHA} 262 | log "Checking out the revision ${GIT_REF} with the SHA ${GIT_SHA} ..." 263 | git checkout -b sft-branch ${GIT_SHA} 264 | if [ "x${POST_CLONE}" != "x" ]; then 265 | log "Running post clone code for ${NAME}-${GIT_SHA} ..." 266 | ${POST_CLONE} 267 | fi 268 | log "Removing .git directory from ${NAME}-${GIT_SHA} ..." 269 | rm -rf .git 270 | cd .. 271 | log "Generating source archive for ${NAME}-${GIT_SHA} ..." 272 | tar cfj ${SOURCES}/${NAME}-${GIT_SHA}.tar.bz2 ${NAME}-${GIT_SHA} 273 | rm -rf ${NAME}-${GIT_SHA} 274 | touch ${STAMPS}/${NAME}-${GIT_SHA}.fetch 275 | fi 276 | } 277 | 278 | # Log a message out to the console 279 | function log { 280 | echo "******************************************************************" 281 | echo "* $*" 282 | echo "******************************************************************" 283 | } 284 | 285 | # Unpack an archive 286 | function unpack { 287 | log Unpacking $* 288 | # Use 'auto' mode decompression. Replace with a switch if tar doesn't support -a 289 | ARCHIVE=$(ls ${SOURCES}/$1.tar.*) 290 | case ${ARCHIVE} in 291 | *.bz2) 292 | echo "archive type bz2" 293 | TYPE=j 294 | ;; 295 | *.gz) 296 | echo "archive type gz" 297 | TYPE=z 298 | ;; 299 | *) 300 | echo "Unknown archive type of $1" 301 | echo ${ARCHIVE} 302 | exit 1 303 | ;; 304 | esac 305 | ${TAR} xf${TYPE}${TARFLAGS} ${SOURCES}/$1.tar.* 306 | } 307 | 308 | # Install a build 309 | function install { 310 | log $1 311 | ${SUDO} make ${MAKEFLAGS} $2 $3 $4 $5 $6 $7 $8 312 | } 313 | 314 | ############################################################################## 315 | # Create directories 316 | ############################################################################## 317 | 318 | mkdir -p ${STAMPS} ${SOURCES} 319 | 320 | cd ${SOURCES} 321 | 322 | ############################################################################## 323 | # Fetch sources 324 | ############################################################################## 325 | 326 | if [ ${ICESTORM_EN} != 0 ]; then 327 | if [ "x${ICESTORM_GIT}" == "x" ]; then 328 | log "There is no icestorm stable release download server yet!" 329 | exit 1 330 | #fetch ${ICESTORM} https://github.com/cliffordwolf/icestorm/archive/${ICESTORM}.tar.bz2 331 | else 332 | clone icestorm ${ICESTORM_GIT} git://github.com/cliffordwolf/icestorm.git 333 | fi 334 | fi 335 | 336 | if [ ${ARACHNEPNR_EN} != 0 ]; then 337 | if [ "x${ARACHNEPNR_GIT}" == "x" ]; then 338 | log "There is no arachne-pnr stable release download server yet!" 339 | exit 1 340 | #fetch ${ARACHNEPNR} https://github.com/YosysHQ/arachne-pnr/archive/${ARACHNEPNR}.tar.bz2 341 | else 342 | clone arachnepnr ${ARACHNEPNR_GIT} git://github.com/YosysHQ/arachne-pnr.git 343 | fi 344 | fi 345 | 346 | if [ ${NEXTPNR_EN} != 0 ]; then 347 | if [ "x${NEXTPNR_GIT}" == "x" ]; then 348 | log "There is no arachne-pnr stable release download server yet!" 349 | exit 1 350 | #fetch ${NEXTPNR} https://github.com/YosysHQ/nextpnr/archive/${NEXTPNR}.tar.bz2 351 | else 352 | clone nextpnr ${NEXTPNR_GIT} git://github.com/YosysHQ/nextpnr.git 353 | fi 354 | fi 355 | 356 | if [ ${YOSYS_EN} != 0 ]; then 357 | if [ "x${YOSYS_GIT}" == "x" ]; then 358 | fetch ${YOSYS} https://github.com/YosysHQ/yosys/archive/${YOSYS}.tar.gz 359 | else 360 | clone yosys ${YOSYS_GIT} git://github.com/YosysHQ/yosys.git 361 | fi 362 | fi 363 | 364 | # if [ ${IVERILOG_EN} != 0 ]; then 365 | # if [ "x${IVERILOG_GIT}" == "x" ]; then 366 | # fetch ${IVERILOG} https://github.com/steveicarus/iverilog/archive/${IVERILOG_VERSION}.tar.gz ${IVERILOG}.tar.gz 367 | # else 368 | # clone iverilog ${IVERILOG_GIT} git://github.com/steveicarus/iverilog.git 369 | # fi 370 | # fi 371 | 372 | ############################################################################## 373 | # Build tools 374 | ############################################################################## 375 | 376 | cd ${SUMMON_DIR} 377 | 378 | if [ ! -e build ]; then 379 | mkdir build 380 | fi 381 | 382 | if [ ! -e ${STAMPS}/${ICESTORM}.build ]; then 383 | unpack ${ICESTORM} 384 | cd ${ICESTORM} 385 | log "Building ${ICESTORM}" 386 | make ${MAKEFLAGS} PREFIX=${PREFIX} 387 | install ${ICESTORM} PREFIX=${PREFIX} install 388 | cd .. 389 | log "Cleaning up ${ICESTORM}" 390 | touch ${STAMPS}/${ICESTORM}.build 391 | rm -rf ${ICESTORM} 392 | fi 393 | 394 | if [ ! -e ${STAMPS}/${ARACHNEPNR}.build ]; then 395 | unpack ${ARACHNEPNR} 396 | cd ${ARACHNEPNR} 397 | log "Building ${ARACHNEPNR}" 398 | make ${MAKEFLAGS} PREFIX=${PREFIX} 399 | install ${ARACHNEPNR} PREFIX=${PREFIX} install 400 | cd .. 401 | log "Cleaning up ${ARACHNEPNR}" 402 | touch ${STAMPS}/${ARACHNEPNR}.build 403 | rm -rf ${ARACHNEPNR} 404 | fi 405 | 406 | if [ ! -e ${STAMPS}/${NEXTPNR}.build ]; then 407 | unpack ${NEXTPNR} 408 | cd build 409 | log "Configuring ${NEXTPNR}-ice40" 410 | CMAKE_PREFIX_PATH=${QT5_PREFIX:-${QT5_PREFIX}/lib/cmake/Qt5} 411 | cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=${PREFIX} \ 412 | -DCMAKE_PREFIX_PATH=${CMAKE_PREFIX_PATH} \ 413 | -DICEBOX_ROOT=${PREFIX}/share/icebox ../${NEXTPNR} 414 | log "Building ${NEXTPNR}-ice40" 415 | make ${MAKEFLAGS} 416 | install ${NEXTPNR} install 417 | cd .. 418 | log "Cleaning up ${NEXTPNR}-ice40" 419 | touch ${STAMPS}/${NEXTPNR}.build 420 | rm -rf build/* ${NEXTPNR} 421 | fi 422 | 423 | if [ ! -e ${STAMPS}/${YOSYS}.build ]; then 424 | unpack ${YOSYS} 425 | if [ "x${YOSYS_GIT}" == "x" ]; then 426 | cd yosys-${YOSYS} 427 | else 428 | cd ${YOSYS} 429 | fi 430 | log "Building ${YOSYS}" 431 | make ${MAKEFLAGS} PREFIX=${PREFIX} 432 | install ${YOSYS} PREFIX=${PREFIX} install 433 | cd .. 434 | log "Cleaning up ${YOSYS}" 435 | touch ${STAMPS}/${YOSYS}.build 436 | if [ "x${YOSYS_GIT}" == "x" ]; then 437 | rm -rf yosys-${YOSYS} 438 | else 439 | rm -rf ${YOSYS} 440 | fi 441 | fi 442 | 443 | # if [ ! -e ${STAMPS}/${IVERILOG}.build ]; then 444 | # unpack ${IVERILOG} 445 | # cd ${IVERILOG} 446 | # log "Running autogen for ${IVERILOG}" 447 | # sh ./autoconf.sh 448 | # cd ../build 449 | # log "Configuring ${IVERILOG}" 450 | # ../${IVERILOG}/configure --prefix=${PREFIX} 451 | # log "Building ${IVERILOG}" 452 | # make ${MAKEFLAGS} 453 | # install ${IVERILOG} install 454 | # cd .. 455 | # log "Cleaning up ${IVERILOG}" 456 | # touch ${STAMPS}/${IVERILOG}.build 457 | # rm -rf build/* ${IVERILOG} 458 | # fi 459 | -------------------------------------------------------------------------------- /wtfpga-lab-solution/.gitignore: -------------------------------------------------------------------------------- 1 | *.asc 2 | *.bin 3 | *.json 4 | *.log 5 | *.rpt 6 | -------------------------------------------------------------------------------- /wtfpga-lab-solution/Makefile: -------------------------------------------------------------------------------- 1 | PROJ = wtfpga 2 | ADD_SRC = clkdiv.v seven_seg_hex.v seven_seg_mux.v 3 | 4 | PIN_DEF = icebreaker.pcf 5 | DEVICE = up5k 6 | 7 | include main.mk 8 | -------------------------------------------------------------------------------- /wtfpga-lab-solution/clkdiv.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module clkdiv( 4 | input clk, 5 | output clkout 6 | ); 7 | 8 | reg [15:0] counter; 9 | assign clkout = counter[15]; 10 | 11 | always @(posedge clk) 12 | counter <= counter+1; 13 | endmodule 14 | -------------------------------------------------------------------------------- /wtfpga-lab-solution/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RS232 5 | set_io -nowarn RX 6 6 | set_io -nowarn TX 9 7 | 8 | # LEDs and Button 9 | set_io -nowarn BTN_N 10 10 | set_io -nowarn LEDR_N 11 11 | set_io -nowarn LEDG_N 37 12 | 13 | # RGB LED Driver 14 | set_io -nowarn LED_RED_N 39 15 | set_io -nowarn LED_GRN_N 40 16 | set_io -nowarn LED_BLU_N 41 17 | 18 | # SPI Flash 19 | set_io -nowarn FLASH_SCK 15 20 | set_io -nowarn FLASH_SSB 16 21 | set_io -nowarn FLASH_IO0 14 22 | set_io -nowarn FLASH_IO1 17 23 | set_io -nowarn FLASH_IO2 12 24 | set_io -nowarn FLASH_IO3 13 25 | 26 | # PMOD 1A 27 | set_io -nowarn P1A1 4 28 | set_io -nowarn P1A2 2 29 | set_io -nowarn P1A3 47 30 | set_io -nowarn P1A4 45 31 | set_io -nowarn P1A7 3 32 | set_io -nowarn P1A8 48 33 | set_io -nowarn P1A9 46 34 | set_io -nowarn P1A10 44 35 | 36 | # PMOD 1B 37 | set_io -nowarn P1B1 43 38 | set_io -nowarn P1B2 38 39 | set_io -nowarn P1B3 34 40 | set_io -nowarn P1B4 31 41 | set_io -nowarn P1B7 42 42 | set_io -nowarn P1B8 36 43 | set_io -nowarn P1B9 32 44 | set_io -nowarn P1B10 28 45 | 46 | # PMOD 2 47 | set_io -nowarn P2_1 27 48 | set_io -nowarn P2_2 25 49 | set_io -nowarn P2_3 21 50 | set_io -nowarn P2_4 19 51 | set_io -nowarn P2_7 26 52 | set_io -nowarn P2_8 23 53 | set_io -nowarn P2_9 20 54 | set_io -nowarn P2_10 18 55 | 56 | # LEDs and Buttons (PMOD 2) 57 | set_io -nowarn LED1 26 58 | set_io -nowarn LED2 27 59 | set_io -nowarn LED3 25 60 | set_io -nowarn LED4 23 61 | set_io -nowarn LED5 21 62 | set_io -nowarn BTN1 20 63 | set_io -nowarn BTN2 19 64 | set_io -nowarn BTN3 18 65 | 66 | set_io -nowarn led[0] 26 67 | set_io -nowarn led[1] 27 68 | set_io -nowarn led[2] 25 69 | set_io -nowarn led[3] 23 70 | set_io -nowarn led[4] 21 71 | 72 | ## WTFpga assignments 73 | # 7 Segment 74 | set_io -nowarn 7SAA 4 75 | set_io -nowarn 7SAE 2 76 | set_io -nowarn 7SAB 47 77 | set_io -nowarn 7SAF 45 78 | set_io -nowarn 7SAC 3 79 | set_io -nowarn 7SAG 48 80 | set_io -nowarn 7SAD 46 81 | set_io -nowarn 7SCA 44 82 | 83 | set_io -nowarn seg[0] 4 84 | set_io -nowarn seg[1] 2 85 | set_io -nowarn seg[2] 47 86 | set_io -nowarn seg[3] 45 87 | set_io -nowarn seg[4] 3 88 | set_io -nowarn seg[5] 48 89 | set_io -nowarn seg[6] 46 90 | set_io -nowarn ca 44 91 | 92 | # DIP-Switch 93 | set_io -nowarn DIP1 43 94 | set_io -nowarn DIP2 38 95 | set_io -nowarn DIP3 34 96 | set_io -nowarn DIP4 31 97 | set_io -nowarn DIP5 42 98 | set_io -nowarn DIP6 36 99 | set_io -nowarn DIP7 32 100 | set_io -nowarn DIP8 28 101 | 102 | set_io -nowarn sw[0] 43 103 | set_io -nowarn sw[1] 38 104 | set_io -nowarn sw[2] 34 105 | set_io -nowarn sw[3] 31 106 | set_io -nowarn sw[4] 42 107 | set_io -nowarn sw[5] 36 108 | set_io -nowarn sw[6] 32 109 | set_io -nowarn sw[7] 28 110 | -------------------------------------------------------------------------------- /wtfpga-lab-solution/main.mk: -------------------------------------------------------------------------------- 1 | 2 | all: $(PROJ).rpt $(PROJ).bin 3 | 4 | %.blif: %.v $(ADD_SRC) $(ADD_DEPS) 5 | yosys -ql $*.log -p 'synth_ice40 -top top -blif $@' $< $(ADD_SRC) 6 | 7 | %.json: %.v $(ADD_SRC) $(ADD_DEPS) 8 | yosys -ql $*.log -p 'synth_ice40 -top top -json $@' $< $(ADD_SRC) 9 | 10 | ifeq ($(USE_ARACHNEPNR),) 11 | %.asc: $(PIN_DEF) %.json 12 | nextpnr-ice40 --$(DEVICE) --json $(filter-out $<,$^) --pcf $< --asc $@ 13 | else 14 | %.asc: $(PIN_DEF) %.blif 15 | arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^ 16 | endif 17 | 18 | 19 | %.bin: %.asc 20 | icepack $< $@ 21 | 22 | %.rpt: %.asc 23 | icetime -d $(DEVICE) -mtr $@ $< 24 | 25 | %_tb: %_tb.v %.v 26 | iverilog -o $@ $^ 27 | 28 | %_tb.vcd: %_tb 29 | vvp -N $< +vcd=$@ 30 | 31 | %_syn.v: %.blif 32 | yosys -p 'read_blif -wideports $^; write_verilog $@' 33 | 34 | %_syntb: %_tb.v %_syn.v 35 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 36 | 37 | %_syntb.vcd: %_syntb 38 | vvp -N $< +vcd=$@ 39 | 40 | prog: $(PROJ).bin 41 | iceprog $< 42 | 43 | sudo-prog: $(PROJ).bin 44 | @echo 'Executing prog as root!!!' 45 | sudo iceprog $< 46 | 47 | clean: 48 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) 49 | 50 | .SECONDARY: 51 | .PHONY: all prog clean 52 | -------------------------------------------------------------------------------- /wtfpga-lab-solution/seven_seg_hex.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //module name and inputs/outputs 3 | module nibble_to_seven_seg( 4 | input [3:0] nibblein, 5 | output reg [6:0] segout 6 | ); 7 | 8 | always @* 9 | case (nibblein) 10 | 4'h0: segout = ~7'b0111111; 11 | 4'h1: segout = ~7'b0000110; 12 | 4'h2: segout = ~7'b1011011; 13 | 4'h3: segout = ~7'b1001111; 14 | 4'h4: segout = ~7'b1100110; 15 | 4'h5: segout = ~7'b1101101; 16 | 4'h6: segout = ~7'b1111101; 17 | 4'h7: segout = ~7'b0000111; 18 | 4'h8: segout = ~7'b1111111; 19 | 4'h9: segout = ~7'b1100111; 20 | 4'hA: segout = ~7'b1110111; 21 | 4'hB: segout = ~7'b1111100; 22 | 4'hC: segout = ~7'b0111001; 23 | 4'hD: segout = ~7'b1011110; 24 | 4'hE: segout = ~7'b1111001; 25 | 4'hF: segout = ~7'b1110001; 26 | // default case happens whenever an undefined input occurs... 27 | default: segout = ~7'b1001001; 28 | endcase 29 | endmodule 30 | -------------------------------------------------------------------------------- /wtfpga-lab-solution/seven_seg_mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module seven_seg_mux( 4 | input clk, 5 | input [6:0] disp0, disp1, 6 | output reg [6:0] segout, 7 | output disp_sel 8 | ); 9 | 10 | reg current; 11 | 12 | assign disp_sel=current; 13 | 14 | always @(posedge clk) 15 | case (current) 16 | 1:begin 17 | segout<=disp1; 18 | current <= 0; 19 | end 20 | 0:begin 21 | segout<=disp0; 22 | current <= 1; 23 | end 24 | endcase 25 | endmodule 26 | 27 | -------------------------------------------------------------------------------- /wtfpga-lab-solution/wtfpga.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //define our module and it's inputs/outputs 3 | module top( 4 | input CLK, 5 | input BTN1, 6 | input BTN2, 7 | input BTN3, 8 | input BTN_N, 9 | input [7:0] sw, 10 | output [4:0] led, 11 | output [6:0] seg, 12 | output ca 13 | ); 14 | 15 | //define wires and registers here 16 | wire [7:0] disp0,disp1; 17 | wire displayClock; 18 | reg [7:0] storedValue; 19 | wire [7:0] dispValue, sum, diff; 20 | 21 | //parallel assignments can go here 22 | assign led[4:0]=sw[4:0]; 23 | assign sum=storedValue+sw; 24 | assign diff=storedValue-sw; 25 | assign dispValue=BTN3?diff: 26 | BTN1?sum: 27 | BTN2?storedValue: 28 | sw; 29 | 30 | //always @ blocks can go here 31 | always @(negedge BTN_N) begin 32 | // commmands-to-run-when-triggered; 33 | storedValue<=sw; 34 | end 35 | //instantiate modules here 36 | 37 | nibble_to_seven_seg nibble0( 38 | .nibblein(dispValue[3:0]), 39 | .segout(disp0) 40 | ); 41 | 42 | nibble_to_seven_seg nibble1( 43 | .nibblein(dispValue[7:4]), 44 | .segout(disp1) 45 | ); 46 | 47 | clkdiv displayClockGen( 48 | .clk(CLK), 49 | .clkout(displayClock) 50 | ); 51 | 52 | seven_seg_mux display( 53 | .clk(displayClock), 54 | .disp0(disp0), 55 | .disp1(disp1), 56 | .segout(seg), 57 | .disp_sel(ca) 58 | ); 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /wtfpga/.gitignore: -------------------------------------------------------------------------------- 1 | *.asc 2 | *.bin 3 | *.json 4 | *.log 5 | *.rpt 6 | -------------------------------------------------------------------------------- /wtfpga/Makefile: -------------------------------------------------------------------------------- 1 | PROJ = wtfpga 2 | ADD_SRC = clkdiv.v seven_seg_hex.v seven_seg_mux.v 3 | 4 | PIN_DEF = icebreaker.pcf 5 | DEVICE = up5k 6 | 7 | include main.mk 8 | -------------------------------------------------------------------------------- /wtfpga/clkdiv.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module clkdiv( 4 | input clk, 5 | output clkout 6 | ); 7 | 8 | reg [15:0] counter; 9 | assign clkout = counter[15]; 10 | 11 | always @(posedge clk) 12 | counter <= counter+1; 13 | endmodule 14 | -------------------------------------------------------------------------------- /wtfpga/icebreaker.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RS232 5 | set_io -nowarn RX 6 6 | set_io -nowarn TX 9 7 | 8 | # LEDs and Button 9 | set_io -nowarn BTN_N 10 10 | set_io -nowarn LEDR_N 11 11 | set_io -nowarn LEDG_N 37 12 | 13 | # RGB LED Driver 14 | set_io -nowarn LED_RED_N 39 15 | set_io -nowarn LED_GRN_N 40 16 | set_io -nowarn LED_BLU_N 41 17 | 18 | # SPI Flash 19 | set_io -nowarn FLASH_SCK 15 20 | set_io -nowarn FLASH_SSB 16 21 | set_io -nowarn FLASH_IO0 14 22 | set_io -nowarn FLASH_IO1 17 23 | set_io -nowarn FLASH_IO2 12 24 | set_io -nowarn FLASH_IO3 13 25 | 26 | # PMOD 1A 27 | set_io -nowarn P1A1 4 28 | set_io -nowarn P1A2 2 29 | set_io -nowarn P1A3 47 30 | set_io -nowarn P1A4 45 31 | set_io -nowarn P1A7 3 32 | set_io -nowarn P1A8 48 33 | set_io -nowarn P1A9 46 34 | set_io -nowarn P1A10 44 35 | 36 | # PMOD 1B 37 | set_io -nowarn P1B1 43 38 | set_io -nowarn P1B2 38 39 | set_io -nowarn P1B3 34 40 | set_io -nowarn P1B4 31 41 | set_io -nowarn P1B7 42 42 | set_io -nowarn P1B8 36 43 | set_io -nowarn P1B9 32 44 | set_io -nowarn P1B10 28 45 | 46 | # PMOD 2 47 | set_io -nowarn P2_1 27 48 | set_io -nowarn P2_2 25 49 | set_io -nowarn P2_3 21 50 | set_io -nowarn P2_4 19 51 | set_io -nowarn P2_7 26 52 | set_io -nowarn P2_8 23 53 | set_io -nowarn P2_9 20 54 | set_io -nowarn P2_10 18 55 | 56 | # LEDs and Buttons (PMOD 2) 57 | set_io -nowarn LED1 26 58 | set_io -nowarn LED2 27 59 | set_io -nowarn LED3 25 60 | set_io -nowarn LED4 23 61 | set_io -nowarn LED5 21 62 | set_io -nowarn BTN1 20 63 | set_io -nowarn BTN2 19 64 | set_io -nowarn BTN3 18 65 | 66 | set_io -nowarn led[0] 26 67 | set_io -nowarn led[1] 27 68 | set_io -nowarn led[2] 25 69 | set_io -nowarn led[3] 23 70 | set_io -nowarn led[4] 21 71 | 72 | ## WTFpga assignments 73 | # 7 Segment 74 | set_io -nowarn 7SAA 4 75 | set_io -nowarn 7SAE 2 76 | set_io -nowarn 7SAB 47 77 | set_io -nowarn 7SAF 45 78 | set_io -nowarn 7SAC 3 79 | set_io -nowarn 7SAG 48 80 | set_io -nowarn 7SAD 46 81 | set_io -nowarn 7SCA 44 82 | 83 | set_io -nowarn seg[0] 4 84 | set_io -nowarn seg[1] 2 85 | set_io -nowarn seg[2] 47 86 | set_io -nowarn seg[3] 45 87 | set_io -nowarn seg[4] 3 88 | set_io -nowarn seg[5] 48 89 | set_io -nowarn seg[6] 46 90 | set_io -nowarn ca 44 91 | 92 | # DIP-Switch 93 | set_io -nowarn DIP1 43 94 | set_io -nowarn DIP2 38 95 | set_io -nowarn DIP3 34 96 | set_io -nowarn DIP4 31 97 | set_io -nowarn DIP5 42 98 | set_io -nowarn DIP6 36 99 | set_io -nowarn DIP7 32 100 | set_io -nowarn DIP8 28 101 | 102 | set_io -nowarn sw[0] 43 103 | set_io -nowarn sw[1] 38 104 | set_io -nowarn sw[2] 34 105 | set_io -nowarn sw[3] 31 106 | set_io -nowarn sw[4] 42 107 | set_io -nowarn sw[5] 36 108 | set_io -nowarn sw[6] 32 109 | set_io -nowarn sw[7] 28 110 | -------------------------------------------------------------------------------- /wtfpga/main.mk: -------------------------------------------------------------------------------- 1 | 2 | all: $(PROJ).rpt $(PROJ).bin 3 | 4 | %.blif: %.v $(ADD_SRC) $(ADD_DEPS) 5 | yosys -ql $*.log -p 'synth_ice40 -top top -blif $@' $< $(ADD_SRC) 6 | 7 | %.json: %.v $(ADD_SRC) $(ADD_DEPS) 8 | yosys -ql $*.log -p 'synth_ice40 -top top -json $@' $< $(ADD_SRC) 9 | 10 | ifeq ($(USE_ARACHNEPNR),) 11 | %.asc: $(PIN_DEF) %.json 12 | nextpnr-ice40 --$(DEVICE) --json $(filter-out $<,$^) --pcf $< --asc $@ 13 | else 14 | %.asc: $(PIN_DEF) %.blif 15 | arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^ 16 | endif 17 | 18 | 19 | %.bin: %.asc 20 | icepack $< $@ 21 | 22 | %.rpt: %.asc 23 | icetime -d $(DEVICE) -mtr $@ $< 24 | 25 | %_tb: %_tb.v %.v 26 | iverilog -o $@ $^ 27 | 28 | %_tb.vcd: %_tb 29 | vvp -N $< +vcd=$@ 30 | 31 | %_syn.v: %.blif 32 | yosys -p 'read_blif -wideports $^; write_verilog $@' 33 | 34 | %_syntb: %_tb.v %_syn.v 35 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 36 | 37 | %_syntb.vcd: %_syntb 38 | vvp -N $< +vcd=$@ 39 | 40 | prog: $(PROJ).bin 41 | iceprog $< 42 | 43 | sudo-prog: $(PROJ).bin 44 | @echo 'Executing prog as root!!!' 45 | sudo iceprog $< 46 | 47 | clean: 48 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) 49 | 50 | .SECONDARY: 51 | .PHONY: all prog clean 52 | -------------------------------------------------------------------------------- /wtfpga/seven_seg_hex.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //module name and inputs/outputs 3 | module nibble_to_seven_seg( 4 | input [3:0] nibblein, 5 | output reg [6:0] segout 6 | ); 7 | 8 | //always @* 9 | // case (nibblein) 10 | // 4'h0: segout = ~7'b0111111; 11 | // 4'h1: segout = ~7'b0000110; 12 | // 4'h2: segout = 13 | // 4'h3: segout = 14 | // 4'h4: segout = 15 | // 4'h5: segout = 16 | // 4'h6: segout = 17 | // 4'h7: segout = 18 | // 4'h8: segout = 19 | // 4'h9: segout = 20 | // 4'hA: segout = 21 | // 4'hB: segout = 22 | // 4'hC: segout = 23 | // 4'hD: segout = 24 | // 4'hE: segout = 25 | // 4'hF: segout = 26 | // default case happens whenever an undefined input occurs... 27 | // default: segout = ~7'b1001001; 28 | // endcase 29 | endmodule 30 | -------------------------------------------------------------------------------- /wtfpga/seven_seg_mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module seven_seg_mux( 4 | input clk, 5 | input [6:0] disp0, disp1, 6 | output reg [6:0] segout, 7 | output disp_sel 8 | ); 9 | 10 | reg current; 11 | 12 | assign disp_sel=current; 13 | 14 | always @(posedge clk) 15 | case (current) 16 | 1:begin 17 | segout<=disp1; 18 | current <= 0; 19 | end 20 | 0:begin 21 | segout<=disp0; 22 | current <= 1; 23 | end 24 | endcase 25 | endmodule 26 | 27 | -------------------------------------------------------------------------------- /wtfpga/wtfpga.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //define our module and it's inputs/outputs 3 | module top( 4 | input CLK, 5 | input BTN1, 6 | input BTN2, 7 | input BTN3, 8 | input BTN_N, 9 | input [7:0] sw, 10 | output [4:0] led, 11 | output [6:0] seg, 12 | output ca 13 | ); 14 | 15 | //define wires and registers here 16 | wire [7:0] disp0,disp1; 17 | wire displayClock; 18 | wire wire1, wire2; 19 | 20 | //parallel assignments can go here 21 | assign disp0 = 0; 22 | assign disp1 = 0; 23 | assign led[3:1]=5'b0; 24 | assign led[0]=wire1; 25 | assign led[4]=wire2; 26 | assign wire1=BTN1; 27 | assign wire2=BTN3; 28 | 29 | //always @ blocks can go here 30 | // always @(sensitivity list) begin 31 | // commmands-to-run-when-triggered; 32 | // end 33 | 34 | //instantiate modules here 35 | nibble_to_seven_seg nibble0( 36 | .nibblein(), 37 | .segout() 38 | ); 39 | 40 | clkdiv displayClockGen( 41 | .clk(CLK), 42 | .clkout(displayClock) 43 | ); 44 | 45 | seven_seg_mux display( 46 | .clk(displayClock), 47 | .disp0(disp0), 48 | .disp1(disp1), 49 | .segout(seg), 50 | .disp_sel(ca) 51 | ); 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /wtfpgamanual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/esden/WTFpga/1cd7ef27c7a78fe34f3723af74c5fab94ceb65ad/wtfpgamanual.pdf --------------------------------------------------------------------------------