├── hardware ├── .gitignore ├── v0.2 │ ├── panel │ │ ├── layout.def │ │ ├── fabdwg.txt │ │ ├── Makefile │ │ └── layout.cfg │ ├── fab │ │ ├── eurocircuits.drl │ │ ├── eurocircuits_png.dru │ │ ├── eurocircuits_europrint.dru │ │ └── eurocircuits_verified_4l.dru │ └── Makefile ├── v0.3 │ ├── panel │ │ ├── layout.def │ │ ├── fabdwg.txt │ │ ├── Makefile │ │ └── layout.cfg │ ├── fab │ │ ├── eurocircuits.drl │ │ ├── eurocircuits_png.dru │ │ ├── eurocircuits_europrint.dru │ │ └── eurocircuits_verified_4l.dru │ └── Makefile ├── v1.0 │ ├── panel │ │ ├── fabdwg.txt │ │ ├── layout.def │ │ ├── Makefile │ │ └── layout.cfg │ ├── fab │ │ ├── eurocircuits.drl │ │ ├── eurocircuits_png.dru │ │ ├── eurocircuits_europrint.dru │ │ └── eurocircuits_verified_4l.dru │ ├── Makefile │ ├── panel_rail.sch │ └── panel_rail.brd ├── lib │ ├── misc.lbr │ └── ftdi.lbr └── 20pin-adapter │ ├── 20pin-adapter.brd │ └── 20pin-adapter-teardrops.brd ├── support └── crossworks │ └── FLOSS-JTAG.xml └── README.md /hardware/.gitignore: -------------------------------------------------------------------------------- 1 | *.s\#* 2 | *.b\#* 3 | -------------------------------------------------------------------------------- /hardware/v0.2/panel/layout.def: -------------------------------------------------------------------------------- 1 | 2 | Row { 3 | Col { 4 | flossjtag Rotate 5 | } 6 | Col { 7 | 20pin-adapter 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /hardware/v0.3/panel/layout.def: -------------------------------------------------------------------------------- 1 | 2 | Row { 3 | Col { 4 | flossjtag Rotate 5 | } 6 | Col { 7 | 20pin-adapter 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /hardware/v0.2/panel/fabdwg.txt: -------------------------------------------------------------------------------- 1 | * FR4 Material 2 | * 1 oz. copper 3 | * All holes plated through 4 | * Drills shown as finished sizes 5 | * Board thickness 0.062" 6 | 7 | 8 | -------------------------------------------------------------------------------- /hardware/v0.3/panel/fabdwg.txt: -------------------------------------------------------------------------------- 1 | * FR4 Material 2 | * 1 oz. copper 3 | * All holes plated through 4 | * Drills shown as finished sizes 5 | * Board thickness 0.062" 6 | 7 | 8 | -------------------------------------------------------------------------------- /hardware/v1.0/panel/fabdwg.txt: -------------------------------------------------------------------------------- 1 | * FR4 Material 2 | * 1 oz. copper 3 | * All holes plated through 4 | * Drills shown as finished sizes 5 | * Board thickness 0.062" 6 | 7 | 8 | -------------------------------------------------------------------------------- /hardware/v1.0/panel/layout.def: -------------------------------------------------------------------------------- 1 | 2 | Row { 3 | panel_rail 4 | Col { 5 | flossjtag 6 | flossjtag 7 | } 8 | Col { 9 | flossjtag 10 | flossjtag 11 | } 12 | panel_rail 13 | } 14 | -------------------------------------------------------------------------------- /hardware/v0.2/panel/Makefile: -------------------------------------------------------------------------------- 1 | GERBMERGE = gerbmerge 2 | GERBV = gerbv 3 | 4 | CFG=layout.cfg 5 | DEF=layout.def 6 | 7 | _panel: 8 | cd ..; make gerber 9 | $(GERBMERGE) $(CFG) $(DEF) 10 | 11 | 12 | _view: 13 | $(GERBV) merged.*.ger merged.*.xln 14 | 15 | 16 | 17 | clean: 18 | rm -f merged.* *~ 19 | -------------------------------------------------------------------------------- /hardware/v0.3/panel/Makefile: -------------------------------------------------------------------------------- 1 | GERBMERGE = gerbmerge 2 | GERBV = gerbv 3 | 4 | CFG=layout.cfg 5 | DEF=layout.def 6 | 7 | _panel: 8 | cd ..; make gerber 9 | $(GERBMERGE) $(CFG) $(DEF) 10 | 11 | 12 | _view: 13 | $(GERBV) merged.*.ger merged.*.xln 14 | 15 | 16 | 17 | clean: 18 | rm -f merged.* *~ 19 | -------------------------------------------------------------------------------- /hardware/v1.0/panel/Makefile: -------------------------------------------------------------------------------- 1 | GERBMERGE = gerbmerge 2 | GERBV = gerbv 3 | 4 | CFG=layout.cfg 5 | DEF=layout.def 6 | 7 | _panel: 8 | cd ..; make gerber 9 | $(GERBMERGE) $(CFG) $(DEF) 10 | 11 | 12 | _view: 13 | $(GERBV) merged.*.ger merged.*.xln 14 | 15 | 16 | 17 | clean: 18 | rm -f merged.* *~ 19 | -------------------------------------------------------------------------------- /support/crossworks/FLOSS-JTAG.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /hardware/v0.2/fab/eurocircuits.drl: -------------------------------------------------------------------------------- 1 | T01 0.0157in 2 | T02 0.035in 3 | T03 0.042in 4 | T04 0.052in 5 | T05 0.0595in 6 | T06 0.086in 7 | T07 0.125in 8 | T08 0.152in 9 | T09 0.014in 10 | T10 0.032in 11 | T11 0.78in 12 | T12 0.024in 13 | T13 0.0465in 14 | T14 0.036in 15 | T15 0.136in 16 | T16 0.020in 17 | T17 0.032in 18 | T18 0.076in 19 | T19 0.0014in 20 | -------------------------------------------------------------------------------- /hardware/v0.3/fab/eurocircuits.drl: -------------------------------------------------------------------------------- 1 | T01 0.0157in 2 | T02 0.035in 3 | T03 0.042in 4 | T04 0.052in 5 | T05 0.0595in 6 | T06 0.086in 7 | T07 0.125in 8 | T08 0.152in 9 | T09 0.014in 10 | T10 0.032in 11 | T11 0.78in 12 | T12 0.024in 13 | T13 0.0465in 14 | T14 0.036in 15 | T15 0.136in 16 | T16 0.020in 17 | T17 0.032in 18 | T18 0.076in 19 | T19 0.0014in 20 | -------------------------------------------------------------------------------- /hardware/v1.0/fab/eurocircuits.drl: -------------------------------------------------------------------------------- 1 | T01 0.0157in 2 | T02 0.035in 3 | T03 0.042in 4 | T04 0.052in 5 | T05 0.0595in 6 | T06 0.086in 7 | T07 0.125in 8 | T08 0.152in 9 | T09 0.014in 10 | T10 0.032in 11 | T11 0.78in 12 | T12 0.024in 13 | T13 0.0465in 14 | T14 0.036in 15 | T15 0.136in 16 | T16 0.020in 17 | T17 0.032in 18 | T18 0.076in 19 | T19 0.0014in 20 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Free Libre Open-Source/-Hardware JTAG/UART Adapter based on the FT2232H chip. 2 | 3 | The hardware is licensed under Creative Commons Share Alike By Attribution 3.0 (CC-BY-SA 3.0) 4 | 5 | Copyright 2009-2010 Piotr Esden-Tempski 6 | 7 | # UART connector adapter side: 8 | 9 | | Pin No. | Name | 10 | |---------|-------| 11 | | 1 | +3.3V | 12 | | 2 | TXD | 13 | | 3 | RXD | 14 | | 4 | GND | 15 | 16 | The numbering of the connector is from left to right when looking from the edge 17 | of the board at the pins of the header. 18 | 19 | # Hardware design file notes: 20 | 21 | All designs up until version 1.0 of Floss-JTAG were 22 | designed in Cadsoft EAGLE. To view the files you will need to install EAGLE. 23 | Most of the designs are 4-layer; this means that you will need a paid version 24 | of the software to edit the inner layers of the board. 25 | 26 | 27 | -------------------------------------------------------------------------------- /hardware/v0.2/fab/eurocircuits_png.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "plot and go" design rules (5B) 2 | layerSetup = (1*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.2mm 6 | mdWirePad = 0.2mm 7 | mdWireVia = 0.2mm 8 | mdPadPad = 0.2mm 9 | mdPadVia = 0.2mm 10 | mdViaVia = 0.2mm 11 | mdSmdPad = 0.2mm 12 | mdSmdVia = 0.2mm 13 | mdSmdSmd = 0.2mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 40mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.2mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 10mil 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 10mil 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 10mil 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 8mil 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 8mil 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 13 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v0.3/fab/eurocircuits_png.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "plot and go" design rules (5B) 2 | layerSetup = (1*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.2mm 6 | mdWirePad = 0.2mm 7 | mdWireVia = 0.2mm 8 | mdPadPad = 0.2mm 9 | mdPadVia = 0.2mm 10 | mdViaVia = 0.2mm 11 | mdSmdPad = 0.2mm 12 | mdSmdVia = 0.2mm 13 | mdSmdSmd = 0.2mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 40mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.2mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 10mil 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 10mil 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 10mil 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 8mil 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 8mil 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 13 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v1.0/fab/eurocircuits_png.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "plot and go" design rules (5B) 2 | layerSetup = (1*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.2mm 6 | mdWirePad = 0.2mm 7 | mdWireVia = 0.2mm 8 | mdPadPad = 0.2mm 9 | mdPadVia = 0.2mm 10 | mdViaVia = 0.2mm 11 | mdSmdPad = 0.2mm 12 | mdSmdVia = 0.2mm 13 | mdSmdSmd = 0.2mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 40mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.2mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 10mil 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 10mil 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 10mil 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 8mil 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 8mil 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 13 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v0.2/fab/eurocircuits_europrint.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "europrint" design rules (6C) 2 | layerSetup = (1*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.2mm 6 | mdWirePad = 0.2mm 7 | mdWireVia = 0.2mm 8 | mdPadPad = 0.2mm 9 | mdPadVia = 0.2mm 10 | mdViaVia = 0.2mm 11 | mdSmdPad = 0.2mm 12 | mdSmdVia = 0.2mm 13 | mdSmdSmd = 0.2mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 40mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.2mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 10mil 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 10mil 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 10mil 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 5mil 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 8mil 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 13 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v0.3/fab/eurocircuits_europrint.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "europrint" design rules (6C) 2 | layerSetup = (1*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.2mm 6 | mdWirePad = 0.2mm 7 | mdWireVia = 0.2mm 8 | mdPadPad = 0.2mm 9 | mdPadVia = 0.2mm 10 | mdViaVia = 0.2mm 11 | mdSmdPad = 0.2mm 12 | mdSmdVia = 0.2mm 13 | mdSmdSmd = 0.2mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 40mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.2mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 10mil 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 10mil 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 10mil 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 5mil 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 8mil 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 13 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v1.0/fab/eurocircuits_europrint.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "europrint" design rules (6C) 2 | layerSetup = (1*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.2mm 6 | mdWirePad = 0.2mm 7 | mdWireVia = 0.2mm 8 | mdPadPad = 0.2mm 9 | mdPadVia = 0.2mm 10 | mdViaVia = 0.2mm 11 | mdSmdPad = 0.2mm 12 | mdSmdVia = 0.2mm 13 | mdSmdSmd = 0.2mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 40mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.2mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 10mil 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 10mil 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 10mil 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 5mil 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 8mil 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 13 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v0.2/fab/eurocircuits_verified_4l.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "verified" 4 layers design rules (6B) 2 | layerSetup = (1*2+15*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 0.2mm 1.5mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.15mm 6 | mdWirePad = 0.15mm 7 | mdWireVia = 0.15mm 8 | mdPadPad = 0.15mm 9 | mdPadVia = 0.15mm 10 | mdViaVia = 0.15mm 11 | mdSmdPad = 0.15mm 12 | mdSmdVia = 0.15mm 13 | mdSmdSmd = 0.15mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 20mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.15mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 0.177mm 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 0.235mm 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 0.177mm 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 0.177mm 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 0.235mm 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 31 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v0.3/fab/eurocircuits_verified_4l.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "verified" 4 layers design rules (6B) 2 | layerSetup = (1*2+15*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 0.2mm 1.5mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.15mm 6 | mdWirePad = 0.15mm 7 | mdWireVia = 0.15mm 8 | mdPadPad = 0.15mm 9 | mdPadVia = 0.15mm 10 | mdViaVia = 0.15mm 11 | mdSmdPad = 0.15mm 12 | mdSmdVia = 0.15mm 13 | mdSmdSmd = 0.15mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 20mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.15mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 0.177mm 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 0.235mm 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 0.177mm 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 0.177mm 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 0.235mm 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 31 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v1.0/fab/eurocircuits_verified_4l.dru: -------------------------------------------------------------------------------- 1 | description = EAGLE Design Rules\n

\neurocircuits "verified" 4 layers design rules (6B) 2 | layerSetup = (1*2+15*16) 3 | mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 4 | mtIsolate = 0.2mm 1.5mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 5 | mdWireWire = 0.15mm 6 | mdWirePad = 0.15mm 7 | mdWireVia = 0.15mm 8 | mdPadPad = 0.15mm 9 | mdPadVia = 0.15mm 10 | mdViaVia = 0.15mm 11 | mdSmdPad = 0.15mm 12 | mdSmdVia = 0.15mm 13 | mdSmdSmd = 0.15mm 14 | mdViaViaSameLayer = 8mil 15 | mnLayersViaInSmd = 2 16 | mdCopperDimension = 20mil 17 | mdDrill = 8mil 18 | mdSmdStop = 0mil 19 | msWidth = 0.15mm 20 | msDrill = 0.35mm 21 | msMicroVia = 35mm 22 | msBlindViaRatio = 0.500000 23 | rvPadTop = 0.250000 24 | rvPadInner = 0.250000 25 | rvPadBottom = 0.250000 26 | rvViaOuter = 0.250000 27 | rvViaInner = 0.250000 28 | rvMicroViaOuter = 0.250000 29 | rvMicroViaInner = 0.250000 30 | rlMinPadTop = 0.177mm 31 | rlMaxPadTop = 20mil 32 | rlMinPadInner = 0.235mm 33 | rlMaxPadInner = 20mil 34 | rlMinPadBottom = 0.177mm 35 | rlMaxPadBottom = 20mil 36 | rlMinViaOuter = 0.177mm 37 | rlMaxViaOuter = 20mil 38 | rlMinViaInner = 0.235mm 39 | rlMaxViaInner = 20mil 40 | rlMinMicroViaOuter = 4mil 41 | rlMaxMicroViaOuter = 20mil 42 | rlMinMicroViaInner = 4mil 43 | rlMaxMicroViaInner = 20mil 44 | psTop = -1 45 | psBottom = -1 46 | psFirst = -1 47 | psElongationLong = 100 48 | psElongationOffset = 100 49 | mvStopFrame = 1.000000 50 | mvCreamFrame = 0.000000 51 | mlMinStopFrame = 4mil 52 | mlMaxStopFrame = 4mil 53 | mlMinCreamFrame = 0mil 54 | mlMaxCreamFrame = 0mil 55 | mlViaStopLimit = 0mil 56 | srRoundness = 0.000000 57 | srMinRoundness = 0mil 58 | srMaxRoundness = 0mil 59 | slThermalGap = 0.500000 60 | slMinThermalGap = 20mil 61 | slMaxThermalGap = 100mil 62 | slAnnulusIsolate = 20mil 63 | slThermalIsolate = 10mil 64 | slAnnulusRestring = 0 65 | slThermalRestring = 1 66 | slThermalsForVias = 0 67 | checkGrid = 0 68 | checkAngle = 1 69 | checkFont = 1 70 | checkRestrict = 1 71 | useDiameter = 31 72 | maxErrors = 200 73 | -------------------------------------------------------------------------------- /hardware/v0.2/panel/layout.cfg: -------------------------------------------------------------------------------- 1 | [DEFAULT] 2 | # Change projdir to wherever your project files are, for example: 3 | # projdir = /home/stuff/projects/test 4 | # 5 | # or relative pathname from where you are running GerbMerge 6 | # 7 | # projdir = testdata 8 | # 9 | projdir=. 10 | 11 | [Options] 12 | 13 | # Set the inter-job spacing (inches) 14 | # 0.0787 ~= 2mm 15 | XSpacing=0.0787 16 | YSpacing=0.0787 17 | 18 | #PanelWidth = 3.28 19 | #PanelHeight = 4.17 20 | 21 | # Which layers to draw cut lines on. Omit this option 22 | # or set to 'None' for no cut lines. We don't want silkscreens 23 | # in this job so put cut lines and crop marks on copper layers. 24 | # NOTE: Layer names are ALL LOWERCASE, even if you define them 25 | # with uppercase letters below. 26 | #CutLineLayers = None 27 | CutLineLayers = *toplayer,*bottomlayer 28 | 29 | # Which layers to draw crop marks on. Omit this option 30 | # or set to 'None' for no crop marks. 31 | # NOTE: Layer names are ALL LOWERCASE, even if you define them 32 | # with uppercase letters below. 33 | CropMarkLayers = *toplayer,*bottomlayer 34 | 35 | # Mandatory option indicating name of file that maps Excellon 36 | # tool codes to drill sizes. 37 | ToolList=%(projdir)s/../fab/eurocircuits.drl 38 | 39 | # Must set this option since we are combining jobs with missing 40 | # layers names. That is, Hexapod just has copper, while we do want 41 | # to print soldermasks for Proj1. 42 | AllowMissingLayers = 1 43 | 44 | # Set to 1 to create a fabrication drawing 45 | FabricationDrawingFile = merged.fabdrawing.ger 46 | 47 | # Filename where optional additional text is to be added to fabrication 48 | # drawing. 49 | FabricationDrawingText = %(projdir)s/fabdwg.txt 50 | 51 | LeftMargin = 0 52 | RightMargin = 0 53 | TopMargin = 0 54 | BottomMargin = 0 55 | 56 | 57 | [flossjtag] 58 | Prefix = %(projdir)s/../flossjtag-teardrops 59 | *TopLayer=%(prefix)s.cmp 60 | *BottomLayer=%(prefix)s.sol 61 | *TopSoldermask=%(prefix)s.stc 62 | *BottomSoldermask=%(prefix)s.sts 63 | *TopSilkscreen=%(prefix)s.plc 64 | *InnerTopLayer=%(prefix)s.l02 65 | *InnerBotLayer=%(prefix)s.l15 66 | Drills=%(prefix)s.xln 67 | BoardOutline=%(prefix)s.bor 68 | 69 | [20pin-adapter] 70 | Prefix = %(projdir)s/../../20pin-adapter/20pin-adapter-teardrops 71 | *TopLayer=%(prefix)s.cmp 72 | *BottomLayer=%(prefix)s.sol 73 | *TopSoldermask=%(prefix)s.stc 74 | *BottomSoldermask=%(prefix)s.sts 75 | *TopSilkscreen=%(prefix)s.plc 76 | *InnerTopLayer=%(prefix)s.l02 77 | *InnerBotLayer=%(prefix)s.l15 78 | Drills=%(prefix)s.xln 79 | BoardOutline=%(prefix)s.bor 80 | -------------------------------------------------------------------------------- /hardware/v0.3/panel/layout.cfg: -------------------------------------------------------------------------------- 1 | [DEFAULT] 2 | # Change projdir to wherever your project files are, for example: 3 | # projdir = /home/stuff/projects/test 4 | # 5 | # or relative pathname from where you are running GerbMerge 6 | # 7 | # projdir = testdata 8 | # 9 | projdir=. 10 | 11 | [Options] 12 | 13 | # Set the inter-job spacing (inches) 14 | # 0.0787 ~= 2mm 15 | XSpacing=0.0787 16 | YSpacing=0.0787 17 | 18 | #PanelWidth = 3.28 19 | #PanelHeight = 4.17 20 | 21 | # Which layers to draw cut lines on. Omit this option 22 | # or set to 'None' for no cut lines. We don't want silkscreens 23 | # in this job so put cut lines and crop marks on copper layers. 24 | # NOTE: Layer names are ALL LOWERCASE, even if you define them 25 | # with uppercase letters below. 26 | #CutLineLayers = None 27 | CutLineLayers = *toplayer,*bottomlayer 28 | 29 | # Which layers to draw crop marks on. Omit this option 30 | # or set to 'None' for no crop marks. 31 | # NOTE: Layer names are ALL LOWERCASE, even if you define them 32 | # with uppercase letters below. 33 | CropMarkLayers = *toplayer,*bottomlayer 34 | 35 | # Mandatory option indicating name of file that maps Excellon 36 | # tool codes to drill sizes. 37 | ToolList=%(projdir)s/../fab/eurocircuits.drl 38 | 39 | # Must set this option since we are combining jobs with missing 40 | # layers names. That is, Hexapod just has copper, while we do want 41 | # to print soldermasks for Proj1. 42 | AllowMissingLayers = 1 43 | 44 | # Set to 1 to create a fabrication drawing 45 | FabricationDrawingFile = merged.fabdrawing.ger 46 | 47 | # Filename where optional additional text is to be added to fabrication 48 | # drawing. 49 | FabricationDrawingText = %(projdir)s/fabdwg.txt 50 | 51 | LeftMargin = 0 52 | RightMargin = 0 53 | TopMargin = 0 54 | BottomMargin = 0 55 | 56 | 57 | [flossjtag] 58 | Prefix = %(projdir)s/../flossjtag-teardrops 59 | *TopLayer=%(prefix)s.cmp 60 | *BottomLayer=%(prefix)s.sol 61 | *TopSoldermask=%(prefix)s.stc 62 | *BottomSoldermask=%(prefix)s.sts 63 | *TopSilkscreen=%(prefix)s.plc 64 | *InnerTopLayer=%(prefix)s.l02 65 | *InnerBotLayer=%(prefix)s.l15 66 | Drills=%(prefix)s.xln 67 | BoardOutline=%(prefix)s.bor 68 | 69 | [20pin-adapter] 70 | Prefix = %(projdir)s/../../20pin-adapter/20pin-adapter-teardrops 71 | *TopLayer=%(prefix)s.cmp 72 | *BottomLayer=%(prefix)s.sol 73 | *TopSoldermask=%(prefix)s.stc 74 | *BottomSoldermask=%(prefix)s.sts 75 | *TopSilkscreen=%(prefix)s.plc 76 | *InnerTopLayer=%(prefix)s.l02 77 | *InnerBotLayer=%(prefix)s.l15 78 | Drills=%(prefix)s.xln 79 | BoardOutline=%(prefix)s.bor 80 | -------------------------------------------------------------------------------- /hardware/v1.0/panel/layout.cfg: -------------------------------------------------------------------------------- 1 | [DEFAULT] 2 | # Change projdir to wherever your project files are, for example: 3 | # projdir = /home/stuff/projects/test 4 | # 5 | # or relative pathname from where you are running GerbMerge 6 | # 7 | # projdir = testdata 8 | # 9 | projdir=. 10 | 11 | [Options] 12 | 13 | # Set the inter-job spacing (inches) 14 | # 0.0787 ~= 2mm 15 | XSpacing=0.0787 16 | YSpacing=0.0787 17 | 18 | #PanelWidth = 3.28 19 | #PanelHeight = 4.17 20 | 21 | # Which layers to draw cut lines on. Omit this option 22 | # or set to 'None' for no cut lines. We don't want silkscreens 23 | # in this job so put cut lines and crop marks on copper layers. 24 | # NOTE: Layer names are ALL LOWERCASE, even if you define them 25 | # with uppercase letters below. 26 | #CutLineLayers = None 27 | CutLineLayers = *toplayer,*bottomlayer 28 | 29 | # Which layers to draw crop marks on. Omit this option 30 | # or set to 'None' for no crop marks. 31 | # NOTE: Layer names are ALL LOWERCASE, even if you define them 32 | # with uppercase letters below. 33 | CropMarkLayers = *toplayer,*bottomlayer 34 | 35 | # Mandatory option indicating name of file that maps Excellon 36 | # tool codes to drill sizes. 37 | ToolList=%(projdir)s/../fab/eurocircuits.drl 38 | 39 | # Must set this option since we are combining jobs with missing 40 | # layers names. That is, Hexapod just has copper, while we do want 41 | # to print soldermasks for Proj1. 42 | AllowMissingLayers = 1 43 | 44 | # Set to 1 to create a fabrication drawing 45 | FabricationDrawingFile = merged.fabdrawing.ger 46 | 47 | # Filename where optional additional text is to be added to fabrication 48 | # drawing. 49 | FabricationDrawingText = %(projdir)s/fabdwg.txt 50 | 51 | LeftMargin = 0 52 | RightMargin = 0 53 | TopMargin = 0 54 | BottomMargin = 0 55 | 56 | 57 | [flossjtag] 58 | Prefix = %(projdir)s/../flossjtag-teardrops 59 | *TopLayer=%(prefix)s.cmp 60 | *BottomLayer=%(prefix)s.sol 61 | *TopSoldermask=%(prefix)s.stc 62 | *BottomSoldermask=%(prefix)s.sts 63 | *TopSilkscreen=%(prefix)s.plc 64 | *BottomSilkscreen=%(prefix)s.pls 65 | *InnerTopLayer=%(prefix)s.l02 66 | *InnerBotLayer=%(prefix)s.l15 67 | Drills=%(prefix)s.xln 68 | BoardOutline=%(prefix)s.bor 69 | 70 | [panel_rail] 71 | Prefix = %(projdir)s/../panel_rail 72 | *TopLayer=%(prefix)s.cmp 73 | *BottomLayer=%(prefix)s.sol 74 | *TopSoldermask=%(prefix)s.stc 75 | *BottomSoldermask=%(prefix)s.sts 76 | *TopSilkscreen=%(prefix)s.plc 77 | *BottomSilkscreen=%(prefix)s.pls 78 | *InnerTopLayer=%(prefix)s.l02 79 | *InnerBotLayer=%(prefix)s.l15 80 | Drills=%(prefix)s.xln 81 | BoardOutline=%(prefix)s.bor 82 | -------------------------------------------------------------------------------- /hardware/v0.2/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Floss JTAG - Open Hardware JTAG adapter 3 | # Copyright (c) 2009 Piotr Esden-Tempski 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions 7 | # are met: 8 | # 1. Redistributions of source code must retain the above copyright 9 | # notice, this list of conditions and the following disclaimer. 10 | # 2. Redistributions in binary form must reproduce the above copyright 11 | # notice, this list of conditions and the following disclaimer in the 12 | # documentation and/or other materials provided with the distribution. 13 | # 3. The name of the author may not be used to endorse or promote products 14 | # derived from this software without specific prior written permission. 15 | # 16 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | # 27 | 28 | BRD_SRCS = flossjtag-teardrops.brd \ 29 | ../20pin-adapter/20pin-adapter-teardrops.brd 30 | 31 | DIRS = 32 | 33 | ##### This substitutions work only with EXACTLY ONE level of subdirectory !!!!! 34 | SCHEMATICS=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.schematics.ps)) 35 | TOP_LAYER=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.top_layer.ps)) 36 | TOP_COMP=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.top_comp.ps)) 37 | BOTTOM_LAYER=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.bottom_layer.ps)) 38 | BOTTOM_COMP=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.bottom_comp.ps)) 39 | POSTSCRIPTS= $(SCHEMATICS) $(TOP_LAYER) $(TOP_COMP) $(BOTTOM_LAYER) $(BOTTOM_COMP) 40 | PDF=$(POSTSCRIPTS:%.ps=%.pdf) 41 | 42 | 43 | GERB_O = $(BRD_SRCS:.brd=.all) 44 | 45 | all: gerber 46 | 47 | gerber: $(GERB_O) 48 | 49 | printable: dirs $(POSTSCRIPTS) $(PDF) 50 | 51 | dirs : 52 | mkdir -p $(DIRS:%=%/printable) 53 | 54 | 55 | ### GERBER GENERATION 56 | 57 | .PRECIOUS : %.cmp %.sol %.stc %.sts %.plc %.bor %.xln %.l02 %.l15 58 | 59 | %.all: %.cmp %.sol %.stc %.sts %.plc %.xln %.bor %.l02 %.l15 60 | touch $@ 61 | 62 | # Component side 63 | %.cmp : %.brd 64 | eagle -X -N -d GERBER_RS274X -o $@ $< Top Pads Vias 65 | # Solder side 66 | %.sol : %.brd 67 | eagle -X -N -d GERBER_RS274X -o $@ $< Bottom Pads Vias 68 | # Solder stop mask comp. side 69 | %.stc : %.brd 70 | eagle -X -N -d GERBER_RS274X -o $@ $< tStop 71 | # Solder stop mask sold. side 72 | %.sts : %.brd 73 | eagle -X -N -d GERBER_RS274X -o $@ $< bStop 74 | # Silkscreen comp. side 75 | %.plc : %.brd 76 | eagle -X -N -d GERBER_RS274X -o $@ $< Dimension tPlace tDocu 77 | # Drill data for NC drill st. 78 | # warning : eagle takes path of -R option from input file directory. 79 | %.xln : %.brd 80 | eagle -X -N -d EXCELLON -E -0.02 -E 0.1 -R fab/eurocircuits.drl -o $@ $< Drills Holes 81 | # Outline 82 | %.bor : %.brd 83 | eagle -X -N -d GERBER_RS274X -o $@ $< Dimension 84 | # Inner layer top 85 | %.l02 : %.brd 86 | eagle -X -N -d GERBER_RS274X -o $@ $< Route2 Pads Vias 87 | # Inner layer bot 88 | %.l15 : %.brd 89 | eagle -X -N -d GERBER_RS274X -o $@ $< Route15 Pads Vias 90 | 91 | 92 | ### POSTSCRIPT AND PDF GENERATION 93 | 94 | 95 | %.pdf : %.ps 96 | ps2pdf $< $@ 97 | 98 | %.schematics.ps : ../%.sch 99 | eagle -X -N -d PS -x.4 -y.2 -o $@ $< Nets Busses Symbols Names Values 100 | 101 | %.top_layer.ps : ../%.brd 102 | eagle -X -N -f- -m+ -d PS -h2 -w3 -o $@ $< Top Pad Via Dimension 103 | 104 | %.top_comp.ps : ../%.brd 105 | eagle -X -N -f- -d PS -h2 -w2 -o $@ $< Pad Via Dimension tPlace tNames tDocu 106 | 107 | %.bottom_layer.ps : ../%.brd 108 | eagle -X -N -f- -d PS -h2 -w3 -o $@ $< Bottom Pad Via Dimension 109 | 110 | %.bottom_comp.ps : ../%.brd 111 | eagle -X -N -f- -m+ -c -d PS -h2 -w2 -o $@ $< Pad Via Dimension bPlace bNames bDocu 112 | 113 | 114 | clean: 115 | @# gerber and excellon 116 | find .. -name '*.cmp' -exec rm -f {} \; 117 | find .. -name '*.sol' -exec rm -f {} \; 118 | find .. -name '*.stc' -exec rm -f {} \; 119 | find .. -name '*.sts' -exec rm -f {} \; 120 | find .. -name '*.plc' -exec rm -f {} \; 121 | find .. -name '*.bor' -exec rm -f {} \; 122 | find .. -name '*.xln' -exec rm -f {} \; 123 | find .. -name '*.dri' -exec rm -f {} \; 124 | find .. -name '*.gpi' -exec rm -f {} \; 125 | find .. -name '*.l02' -exec rm -f {} \; 126 | find .. -name '*.l15' -exec rm -f {} \; 127 | find .. -name '*.all' -exec rm -f {} \; 128 | @# printable 129 | find . -name '*.schematics.ps' -exec rm -f {} \; 130 | find . -name '*.schematics.pdf' -exec rm -f {} \; 131 | find . -name '*.top_layer.ps' -exec rm -f {} \; 132 | find . -name '*.top_layer.pdf' -exec rm -f {} \; 133 | find . -name '*.top_comp.ps' -exec rm -f {} \; 134 | find . -name '*.top_comp.pdf' -exec rm -f {} \; 135 | find . -name '*.bottom_layer.ps' -exec rm -f {} \; 136 | find . -name '*.bottom_layer.pdf' -exec rm -f {} \; 137 | find . -name '*.bottom_comp.ps' -exec rm -f {} \; 138 | find . -name '*.bottom_comp.pdf' -exec rm -f {} \; 139 | @# eagle error log 140 | find .. -name '*.erc' -exec rm -f {} \; 141 | @# eagle autorouter log 142 | find .. -name '*.pro' -exec rm -f {} \; 143 | @# eagle backups 144 | find .. -name '*#*' -exec rm -f {} \; 145 | @# emacs backups 146 | find .. -name '*~' -exec rm -f {} \; 147 | -------------------------------------------------------------------------------- /hardware/v0.3/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Floss JTAG - Open Hardware JTAG adapter 3 | # Copyright (c) 2009 Piotr Esden-Tempski 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions 7 | # are met: 8 | # 1. Redistributions of source code must retain the above copyright 9 | # notice, this list of conditions and the following disclaimer. 10 | # 2. Redistributions in binary form must reproduce the above copyright 11 | # notice, this list of conditions and the following disclaimer in the 12 | # documentation and/or other materials provided with the distribution. 13 | # 3. The name of the author may not be used to endorse or promote products 14 | # derived from this software without specific prior written permission. 15 | # 16 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | # 27 | 28 | BRD_SRCS = flossjtag-teardrops.brd \ 29 | ../20pin-adapter/20pin-adapter-teardrops.brd 30 | 31 | DIRS = 32 | 33 | ##### This substitutions work only with EXACTLY ONE level of subdirectory !!!!! 34 | SCHEMATICS=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.schematics.ps)) 35 | TOP_LAYER=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.top_layer.ps)) 36 | TOP_COMP=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.top_comp.ps)) 37 | BOTTOM_LAYER=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.bottom_layer.ps)) 38 | BOTTOM_COMP=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.bottom_comp.ps)) 39 | POSTSCRIPTS= $(SCHEMATICS) $(TOP_LAYER) $(TOP_COMP) $(BOTTOM_LAYER) $(BOTTOM_COMP) 40 | PDF=$(POSTSCRIPTS:%.ps=%.pdf) 41 | 42 | 43 | GERB_O = $(BRD_SRCS:.brd=.all) 44 | 45 | all: gerber 46 | 47 | gerber: $(GERB_O) 48 | 49 | printable: dirs $(POSTSCRIPTS) $(PDF) 50 | 51 | dirs : 52 | mkdir -p $(DIRS:%=%/printable) 53 | 54 | 55 | ### GERBER GENERATION 56 | 57 | .PRECIOUS : %.cmp %.sol %.stc %.sts %.plc %.bor %.xln %.l02 %.l15 58 | 59 | %.all: %.cmp %.sol %.stc %.sts %.plc %.xln %.bor %.l02 %.l15 60 | touch $@ 61 | 62 | # Component side 63 | %.cmp : %.brd 64 | eagle -X -N -d GERBER_RS274X -o $@ $< Top Pads Vias 65 | # Solder side 66 | %.sol : %.brd 67 | eagle -X -N -d GERBER_RS274X -o $@ $< Bottom Pads Vias 68 | # Solder stop mask comp. side 69 | %.stc : %.brd 70 | eagle -X -N -d GERBER_RS274X -o $@ $< tStop 71 | # Solder stop mask sold. side 72 | %.sts : %.brd 73 | eagle -X -N -d GERBER_RS274X -o $@ $< bStop 74 | # Silkscreen comp. side 75 | %.plc : %.brd 76 | eagle -X -N -d GERBER_RS274X -o $@ $< Dimension tPlace tDocu 77 | # Drill data for NC drill st. 78 | # warning : eagle takes path of -R option from input file directory. 79 | %.xln : %.brd 80 | eagle -X -N -d EXCELLON -E -0.02 -E 0.1 -R fab/eurocircuits.drl -o $@ $< Drills Holes 81 | # Outline 82 | %.bor : %.brd 83 | eagle -X -N -d GERBER_RS274X -o $@ $< Dimension 84 | # Inner layer top 85 | %.l02 : %.brd 86 | eagle -X -N -d GERBER_RS274X -o $@ $< Route2 Pads Vias 87 | # Inner layer bot 88 | %.l15 : %.brd 89 | eagle -X -N -d GERBER_RS274X -o $@ $< Route15 Pads Vias 90 | 91 | 92 | ### POSTSCRIPT AND PDF GENERATION 93 | 94 | 95 | %.pdf : %.ps 96 | ps2pdf $< $@ 97 | 98 | %.schematics.ps : ../%.sch 99 | eagle -X -N -d PS -x.4 -y.2 -o $@ $< Nets Busses Symbols Names Values 100 | 101 | %.top_layer.ps : ../%.brd 102 | eagle -X -N -f- -m+ -d PS -h2 -w3 -o $@ $< Top Pad Via Dimension 103 | 104 | %.top_comp.ps : ../%.brd 105 | eagle -X -N -f- -d PS -h2 -w2 -o $@ $< Pad Via Dimension tPlace tNames tDocu 106 | 107 | %.bottom_layer.ps : ../%.brd 108 | eagle -X -N -f- -d PS -h2 -w3 -o $@ $< Bottom Pad Via Dimension 109 | 110 | %.bottom_comp.ps : ../%.brd 111 | eagle -X -N -f- -m+ -c -d PS -h2 -w2 -o $@ $< Pad Via Dimension bPlace bNames bDocu 112 | 113 | 114 | clean: 115 | @# gerber and excellon 116 | find .. -name '*.cmp' -exec rm -f {} \; 117 | find .. -name '*.sol' -exec rm -f {} \; 118 | find .. -name '*.stc' -exec rm -f {} \; 119 | find .. -name '*.sts' -exec rm -f {} \; 120 | find .. -name '*.plc' -exec rm -f {} \; 121 | find .. -name '*.bor' -exec rm -f {} \; 122 | find .. -name '*.xln' -exec rm -f {} \; 123 | find .. -name '*.dri' -exec rm -f {} \; 124 | find .. -name '*.gpi' -exec rm -f {} \; 125 | find .. -name '*.l02' -exec rm -f {} \; 126 | find .. -name '*.l15' -exec rm -f {} \; 127 | find .. -name '*.all' -exec rm -f {} \; 128 | @# printable 129 | find . -name '*.schematics.ps' -exec rm -f {} \; 130 | find . -name '*.schematics.pdf' -exec rm -f {} \; 131 | find . -name '*.top_layer.ps' -exec rm -f {} \; 132 | find . -name '*.top_layer.pdf' -exec rm -f {} \; 133 | find . -name '*.top_comp.ps' -exec rm -f {} \; 134 | find . -name '*.top_comp.pdf' -exec rm -f {} \; 135 | find . -name '*.bottom_layer.ps' -exec rm -f {} \; 136 | find . -name '*.bottom_layer.pdf' -exec rm -f {} \; 137 | find . -name '*.bottom_comp.ps' -exec rm -f {} \; 138 | find . -name '*.bottom_comp.pdf' -exec rm -f {} \; 139 | @# eagle error log 140 | find .. -name '*.erc' -exec rm -f {} \; 141 | @# eagle autorouter log 142 | find .. -name '*.pro' -exec rm -f {} \; 143 | @# eagle backups 144 | find .. -name '*#*' -exec rm -f {} \; 145 | @# emacs backups 146 | find .. -name '*~' -exec rm -f {} \; 147 | -------------------------------------------------------------------------------- /hardware/v1.0/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Floss JTAG - Open Hardware JTAG adapter 3 | # Copyright (c) 2009 Piotr Esden-Tempski 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions 7 | # are met: 8 | # 1. Redistributions of source code must retain the above copyright 9 | # notice, this list of conditions and the following disclaimer. 10 | # 2. Redistributions in binary form must reproduce the above copyright 11 | # notice, this list of conditions and the following disclaimer in the 12 | # documentation and/or other materials provided with the distribution. 13 | # 3. The name of the author may not be used to endorse or promote products 14 | # derived from this software without specific prior written permission. 15 | # 16 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | # 27 | 28 | BRD_SRCS = flossjtag-teardrops.brd \ 29 | panel_rail.brd 30 | 31 | DIRS = 32 | 33 | ##### This substitutions work only with EXACTLY ONE level of subdirectory !!!!! 34 | SCHEMATICS=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.schematics.ps)) 35 | TOP_LAYER=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.top_layer.ps)) 36 | TOP_COMP=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.top_comp.ps)) 37 | BOTTOM_LAYER=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.bottom_layer.ps)) 38 | BOTTOM_COMP=$(subst /,/printable/,$(BRD_SRCS:%.brd=%.bottom_comp.ps)) 39 | POSTSCRIPTS= $(SCHEMATICS) $(TOP_LAYER) $(TOP_COMP) $(BOTTOM_LAYER) $(BOTTOM_COMP) 40 | PDF=$(POSTSCRIPTS:%.ps=%.pdf) 41 | 42 | 43 | GERB_O = $(BRD_SRCS:.brd=.all) 44 | 45 | all: gerber 46 | 47 | gerber: $(GERB_O) 48 | 49 | printable: dirs $(POSTSCRIPTS) $(PDF) 50 | 51 | dirs : 52 | mkdir -p $(DIRS:%=%/printable) 53 | 54 | 55 | ### GERBER GENERATION 56 | 57 | .PRECIOUS : %.cmp %.sol %.stc %.sts %.plc %.pls %.bor %.xln %.l02 %.l15 58 | 59 | %.all: %.cmp %.sol %.stc %.sts %.plc %.pls %.xln %.bor %.l02 %.l15 60 | touch $@ 61 | 62 | # Component side 63 | %.cmp : %.brd 64 | eagle -X -N -d GERBER_RS274X -o $@ $< Top Pads Vias 65 | # Solder side 66 | %.sol : %.brd 67 | eagle -X -N -d GERBER_RS274X -o $@ $< Bottom Pads Vias 68 | # Solder stop mask comp. side 69 | %.stc : %.brd 70 | eagle -X -N -d GERBER_RS274X -o $@ $< tStop 71 | # Solder stop mask sold. side 72 | %.sts : %.brd 73 | eagle -X -N -d GERBER_RS274X -o $@ $< bStop 74 | # Silkscreen comp. side 75 | %.plc : %.brd 76 | eagle -X -N -d GERBER_RS274X -o $@ $< Dimension tPlace 77 | # Silkscreen solder. side 78 | %.pls : %.brd 79 | eagle -X -N -d GERBER_RS274X -o $@ $< Dimension bPlace 80 | # Drill data for NC drill st. 81 | # warning : eagle takes path of -R option from input file directory. 82 | %.xln : %.brd 83 | eagle -X -N -d EXCELLON -E -0.02 -E 0.1 -R fab/eurocircuits.drl -o $@ $< Drills Holes 84 | # Outline 85 | %.bor : %.brd 86 | eagle -X -N -d GERBER_RS274X -o $@ $< Dimension 87 | # Inner layer top 88 | %.l02 : %.brd 89 | eagle -X -N -d GERBER_RS274X -o $@ $< Route2 Pads Vias 90 | # Inner layer bot 91 | %.l15 : %.brd 92 | eagle -X -N -d GERBER_RS274X -o $@ $< Route15 Pads Vias 93 | 94 | 95 | ### POSTSCRIPT AND PDF GENERATION 96 | 97 | 98 | %.pdf : %.ps 99 | ps2pdf $< $@ 100 | 101 | %.schematics.ps : ../%.sch 102 | eagle -X -N -d PS -x.4 -y.2 -o $@ $< Nets Busses Symbols Names Values 103 | 104 | %.top_layer.ps : ../%.brd 105 | eagle -X -N -f- -m+ -d PS -h2 -w3 -o $@ $< Top Pad Via Dimension 106 | 107 | %.top_comp.ps : ../%.brd 108 | eagle -X -N -f- -d PS -h2 -w2 -o $@ $< Pad Via Dimension tPlace tNames tDocu 109 | 110 | %.bottom_layer.ps : ../%.brd 111 | eagle -X -N -f- -d PS -h2 -w3 -o $@ $< Bottom Pad Via Dimension 112 | 113 | %.bottom_comp.ps : ../%.brd 114 | eagle -X -N -f- -m+ -c -d PS -h2 -w2 -o $@ $< Pad Via Dimension bPlace bNames bDocu 115 | 116 | 117 | clean: 118 | @# gerber and excellon 119 | find .. -name '*.cmp' -exec rm -f {} \; 120 | find .. -name '*.sol' -exec rm -f {} \; 121 | find .. -name '*.stc' -exec rm -f {} \; 122 | find .. -name '*.sts' -exec rm -f {} \; 123 | find .. -name '*.plc' -exec rm -f {} \; 124 | find .. -name '*.pls' -exec rm -f {} \; 125 | find .. -name '*.bor' -exec rm -f {} \; 126 | find .. -name '*.xln' -exec rm -f {} \; 127 | find .. -name '*.dri' -exec rm -f {} \; 128 | find .. -name '*.gpi' -exec rm -f {} \; 129 | find .. -name '*.l02' -exec rm -f {} \; 130 | find .. -name '*.l15' -exec rm -f {} \; 131 | find .. -name '*.all' -exec rm -f {} \; 132 | @# printable 133 | find . -name '*.schematics.ps' -exec rm -f {} \; 134 | find . -name '*.schematics.pdf' -exec rm -f {} \; 135 | find . -name '*.top_layer.ps' -exec rm -f {} \; 136 | find . -name '*.top_layer.pdf' -exec rm -f {} \; 137 | find . -name '*.top_comp.ps' -exec rm -f {} \; 138 | find . -name '*.top_comp.pdf' -exec rm -f {} \; 139 | find . -name '*.bottom_layer.ps' -exec rm -f {} \; 140 | find . -name '*.bottom_layer.pdf' -exec rm -f {} \; 141 | find . -name '*.bottom_comp.ps' -exec rm -f {} \; 142 | find . -name '*.bottom_comp.pdf' -exec rm -f {} \; 143 | @# eagle error log 144 | find .. -name '*.erc' -exec rm -f {} \; 145 | @# eagle autorouter log 146 | find .. -name '*.pro' -exec rm -f {} \; 147 | @# eagle backups 148 | find .. -name '*#*' -exec rm -f {} \; 149 | @# emacs backups 150 | find .. -name '*~' -exec rm -f {} \; 151 | -------------------------------------------------------------------------------- /hardware/v1.0/panel_rail.sch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | <b>Fiducial Alignment Points</b> 121 | Various fiducial points for machine vision alignment. 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | -------------------------------------------------------------------------------- /hardware/v1.0/panel_rail.brd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | <b>EAGLE Design Rules</b> 122 | <p> 123 | Die Standard-Design-Rules sind so gewählt, dass sie für 124 | die meisten Anwendungen passen. Sollte ihre Platine 125 | besondere Anforderungen haben, treffen Sie die erforderlichen 126 | Einstellungen hier und speichern die Design Rules unter 127 | einem neuen Namen ab. 128 | <b>EAGLE Design Rules</b> 129 | <p> 130 | The default Design Rules have been set to cover 131 | a wide range of applications. Your particular design 132 | may have different requirements, so please make the 133 | necessary adjustments and save your customized 134 | design rules under a new name. 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | -------------------------------------------------------------------------------- /hardware/lib/misc.lbr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | <b>RESISTOR</b> 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | >NAME 116 | >VALUE 117 | 118 | 119 | 120 | 121 | 122 | <B>Small Outline Narrow Plastic Gull Wing</B><p> 123 | 150-mil body, package type SN 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | >NAME 144 | >VALUE 145 | IPC SO8 146 | JEDEC MS-012 AA 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | >NAME 180 | >VALUE 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | >VALUE 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | >NAME 216 | >VALUE 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | >NAME 227 | >VALUE 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | >NAME 243 | >VALUE 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | Microchip: 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | -------------------------------------------------------------------------------- /hardware/lib/ftdi.lbr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | <b>48-pin plastic LQFP (FPT-48P-M26)</b><p> 63 | www.fma.fujitsu.com/pdf/e713717.pdf 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | >NAME 138 | >VALUE 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | >NAME 212 | >VALUE 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | -------------------------------------------------------------------------------- /hardware/20pin-adapter/20pin-adapter.brd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | FLOSSJTAG 87 | FLOSSJTAG 88 | CC-BY-SA 89 | CC-BY-SA 90 | 91 | 92 | 93 | 94 | 95 | <b>PIN HEADER</b> 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 1 179 | >NAME 180 | >VALUE 181 | 20 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | <b>CONNECTOR</b><p> 209 | wire to board 1.25 mm (.049 inch) pitch header<p> 210 | SMT<p> 211 | right angle 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | >NAME 277 | >VALUE 278 | 1 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | <b>EAGLE Design Rules</b> 302 | <p> 303 | Die Standard-Design-Rules sind so gewählt, dass sie für 304 | die meisten Anwendungen passen. Sollte ihre Platine 305 | besondere Anforderungen haben, treffen Sie die erforderlichen 306 | Einstellungen hier und speichern die Design Rules unter 307 | einem neuen Namen ab. 308 | <b>EAGLE Design Rules</b> 309 | <p> 310 | The default Design Rules have been set to cover 311 | a wide range of applications. Your particular design 312 | may have different requirements, so please make the 313 | necessary adjustments and save your customized 314 | design rules under a new name. 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | 363 | 364 | 365 | 366 | 367 | 368 | 369 | 370 | 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 398 | 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | 424 | 425 | 426 | 427 | 428 | 429 | 430 | 431 | 432 | 433 | 434 | 435 | 436 | 437 | 438 | 439 | 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | 451 | 452 | 453 | 454 | 455 | 456 | 457 | 458 | 459 | 460 | 461 | 462 | 463 | 464 | 465 | 466 | 467 | 468 | 469 | 470 | 471 | 472 | 473 | 474 | 475 | 476 | 477 | 478 | 479 | 480 | 481 | 482 | 483 | 484 | 485 | 486 | 487 | 488 | 489 | 490 | 491 | 492 | 493 | 494 | 495 | 496 | 497 | 498 | 499 | 500 | 501 | 502 | 503 | 504 | 505 | 506 | 507 | 508 | 509 | 510 | 511 | 512 | 513 | 514 | 515 | 516 | 517 | 518 | 519 | 520 | 521 | 522 | 523 | 524 | 525 | 526 | 527 | 528 | 529 | 530 | 531 | 532 | 533 | 534 | 535 | 536 | 537 | 538 | 539 | 540 | 541 | 542 | 543 | 544 | 545 | 546 | 547 | 548 | 549 | 550 | 551 | 552 | 553 | 554 | 555 | 556 | 557 | 558 | 559 | 560 | 561 | 562 | 563 | 564 | 565 | 566 | 567 | 568 | 569 | 570 | 571 | 572 | 573 | 574 | 575 | 576 | 577 | 578 | 579 | 580 | 581 | 582 | 583 | 584 | 585 | 586 | 587 | 588 | 589 | 590 | 591 | 592 | 593 | 594 | 595 | 596 | 597 | 598 | -------------------------------------------------------------------------------- /hardware/20pin-adapter/20pin-adapter-teardrops.brd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | FLOSSJTAG 87 | FLOSSJTAG 88 | CC-BY-SA 89 | CC-BY-SA 90 | 91 | 92 | 93 | 94 | 95 | <b>PIN HEADER</b> 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 1 179 | >NAME 180 | >VALUE 181 | 20 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | <b>CONNECTOR</b><p> 209 | wire to board 1.25 mm (.049 inch) pitch header<p> 210 | SMT<p> 211 | right angle 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | >NAME 277 | >VALUE 278 | 1 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | <b>EAGLE Design Rules</b> 302 | <p> 303 | Die Standard-Design-Rules sind so gewählt, dass sie für 304 | die meisten Anwendungen passen. Sollte ihre Platine 305 | besondere Anforderungen haben, treffen Sie die erforderlichen 306 | Einstellungen hier und speichern die Design Rules unter 307 | einem neuen Namen ab. 308 | <b>EAGLE Design Rules</b> 309 | <p> 310 | The default Design Rules have been set to cover 311 | a wide range of applications. Your particular design 312 | may have different requirements, so please make the 313 | necessary adjustments and save your customized 314 | design rules under a new name. 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | 363 | 364 | 365 | 366 | 367 | 368 | 369 | 370 | 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 398 | 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | 424 | 425 | 426 | 427 | 428 | 429 | 430 | 431 | 432 | 433 | 434 | 435 | 436 | 437 | 438 | 439 | 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | 451 | 452 | 453 | 454 | 455 | 456 | 457 | 458 | 459 | 460 | 461 | 462 | 463 | 464 | 465 | 466 | 467 | 468 | 469 | 470 | 471 | 472 | 473 | 474 | 475 | 476 | 477 | 478 | 479 | 480 | 481 | 482 | 483 | 484 | 485 | 486 | 487 | 488 | 489 | 490 | 491 | 492 | 493 | 494 | 495 | 496 | 497 | 498 | 499 | 500 | 501 | 502 | 503 | 504 | 505 | 506 | 507 | 508 | 509 | 510 | 511 | 512 | 513 | 514 | 515 | 516 | 517 | 518 | 519 | 520 | 521 | 522 | 523 | 524 | 525 | 526 | 527 | 528 | 529 | 530 | 531 | 532 | 533 | 534 | 535 | 536 | 537 | 538 | 539 | 540 | 541 | 542 | 543 | 544 | 545 | 546 | 547 | 548 | 549 | 550 | 551 | 552 | 553 | 554 | 555 | 556 | 557 | 558 | 559 | 560 | 561 | 562 | 563 | 564 | 565 | 566 | 567 | 568 | 569 | 570 | 571 | 572 | 573 | 574 | 575 | 576 | 577 | 578 | 579 | 580 | 581 | 582 | 583 | 584 | 585 | 586 | 587 | 588 | 589 | 590 | 591 | 592 | 593 | 594 | 595 | 596 | 597 | 598 | 599 | 600 | 601 | 602 | 603 | 604 | 605 | 606 | 607 | 608 | 609 | 610 | 611 | 612 | 613 | 614 | 615 | 616 | 617 | 618 | 619 | 620 | 621 | 622 | 623 | --------------------------------------------------------------------------------