├── .cargo └── config.toml ├── .gitignore ├── Cargo.lock ├── Cargo.toml ├── LICENSE-APACHE ├── LICENSE-MIT ├── README.md ├── build.rs ├── ld ├── esp32.x ├── esp32c2.x ├── esp32c3.x ├── esp32c6.x ├── esp32h2.x ├── esp32s2.x ├── esp32s3.x └── loader.x └── src ├── api.rs ├── api_xtensa.rs ├── flash.rs ├── main.rs ├── properties.rs └── tinfl.rs /.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [alias] 2 | esp32 = "build --release --features esp32 --target xtensa-esp32-none-elf" 3 | esp32s2 = "build --release --features esp32s2 --target xtensa-esp32s2-none-elf" 4 | esp32s3 = "build --release --features esp32s3 --target xtensa-esp32s3-none-elf" 5 | esp32c2 = "build --release --features esp32c2 --target riscv32imc-unknown-none-elf" 6 | esp32c3 = "build --release --features esp32c3 --target riscv32imc-unknown-none-elf" 7 | esp32c6 = "build --release --features esp32c6 --target riscv32imac-unknown-none-elf" 8 | esp32h2 = "build --release --features esp32h2 --target riscv32imac-unknown-none-elf" 9 | 10 | [target.'cfg(target_arch = "riscv32")'] 11 | rustflags = [ 12 | "-C", "link-arg=-Tld/loader.x", 13 | "-C", "link-args=-Map=target/esp-loader.map", 14 | "-C", "link-args=--nmagic", 15 | ] 16 | 17 | [target.'cfg(target_arch = "xtensa")'] 18 | rustflags = [ 19 | "-C", "linker=rust-lld", 20 | "-C", "link-arg=-Tld/loader.x" 21 | ] 22 | 23 | [unstable] 24 | build-std = [ "core" ] -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /target 2 | /output 3 | esp32c3.bin 4 | -------------------------------------------------------------------------------- /Cargo.lock: -------------------------------------------------------------------------------- 1 | # This file is automatically @generated by Cargo. 2 | # It is not intended for manual editing. 3 | version = 3 4 | 5 | [[package]] 6 | name = "esp-flashloader" 7 | version = "0.1.0" 8 | dependencies = [ 9 | "panic-never", 10 | "ufmt", 11 | ] 12 | 13 | [[package]] 14 | name = "panic-never" 15 | version = "0.1.0" 16 | source = "registry+https://github.com/rust-lang/crates.io-index" 17 | checksum = "b0dc75d1f6543e7468fe83fe67257da512d7f1d2d5b66adfbbcf86b22df8d370" 18 | 19 | [[package]] 20 | name = "proc-macro-hack" 21 | version = "0.5.20+deprecated" 22 | source = "registry+https://github.com/rust-lang/crates.io-index" 23 | checksum = "dc375e1527247fe1a97d8b7156678dfe7c1af2fc075c9a4db3690ecd2a148068" 24 | 25 | [[package]] 26 | name = "proc-macro2" 27 | version = "1.0.28" 28 | source = "registry+https://github.com/rust-lang/crates.io-index" 29 | checksum = "5c7ed8b8c7b886ea3ed7dde405212185f423ab44682667c8c6dd14aa1d9f6612" 30 | dependencies = [ 31 | "unicode-xid", 32 | ] 33 | 34 | [[package]] 35 | name = "quote" 36 | version = "1.0.9" 37 | source = "registry+https://github.com/rust-lang/crates.io-index" 38 | checksum = "c3d0b9745dc2debf507c8422de05d7226cc1f0644216dfdfead988f9b1ab32a7" 39 | dependencies = [ 40 | "proc-macro2", 41 | ] 42 | 43 | [[package]] 44 | name = "syn" 45 | version = "1.0.75" 46 | source = "registry+https://github.com/rust-lang/crates.io-index" 47 | checksum = "b7f58f7e8eaa0009c5fec437aabf511bd9933e4b2d7407bd05273c01a8906ea7" 48 | dependencies = [ 49 | "proc-macro2", 50 | "quote", 51 | "unicode-xid", 52 | ] 53 | 54 | [[package]] 55 | name = "ufmt" 56 | version = "0.1.2" 57 | source = "registry+https://github.com/rust-lang/crates.io-index" 58 | checksum = "31d3c0c63312dfc9d8e5c71114d617018a19f6058674003c0da29ee8d8036cdd" 59 | dependencies = [ 60 | "proc-macro-hack", 61 | "ufmt-macros", 62 | "ufmt-write", 63 | ] 64 | 65 | [[package]] 66 | name = "ufmt-macros" 67 | version = "0.2.0" 68 | source = "registry+https://github.com/rust-lang/crates.io-index" 69 | checksum = "e4ab6c92f30c996394a8bd525aef9f03ce01d0d7ac82d81902968057e37dd7d9" 70 | dependencies = [ 71 | "proc-macro-hack", 72 | "proc-macro2", 73 | "quote", 74 | "syn", 75 | ] 76 | 77 | [[package]] 78 | name = "ufmt-write" 79 | version = "0.1.0" 80 | source = "registry+https://github.com/rust-lang/crates.io-index" 81 | checksum = "e87a2ed6b42ec5e28cc3b94c09982969e9227600b2e3dcbc1db927a84c06bd69" 82 | 83 | [[package]] 84 | name = "unicode-xid" 85 | version = "0.2.2" 86 | source = "registry+https://github.com/rust-lang/crates.io-index" 87 | checksum = "8ccb82d61f80a663efe1f787a51b16b5a51e3314d6ac365b08639f52387b33f3" 88 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "esp-flashloader" 3 | version = "0.1.0" 4 | edition = "2018" 5 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 6 | 7 | [dependencies] 8 | panic-never = "0.1.0" 9 | ufmt = { version = "0.1.0", optional = true } 10 | 11 | 12 | [features] 13 | log = ["ufmt"] 14 | 15 | # targets 16 | esp32 = [] 17 | esp32s2 = [] 18 | esp32s3 = [] 19 | esp32c2 = [] 20 | esp32c3 = [] 21 | esp32c6 = [] 22 | esp32h2 = [] 23 | 24 | [profile.release] 25 | codegen-units = 1 26 | debug = false 27 | debug-assertions = false 28 | incremental = false 29 | lto = "fat" 30 | opt-level = 'z' 31 | overflow-checks = false 32 | -------------------------------------------------------------------------------- /LICENSE-APACHE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ### esp flash loader 2 | 3 | A probe-rs flash loader for Espressif chips. 4 | 5 | To build the flash loader: 6 | 7 | ```bash 8 | $ cargo $(CHIP_NAME) # builds the flashing stub 9 | $ target-gen elf target/$(RUST_TARGET)/release/esp-flashloader output/$(CHIP_NAME).yaml --update --name $(CHIP_NAME)-flashloader 10 | ``` 11 | 12 | Example for the updating the `esp32c3` flash algorithm. 13 | 14 | ```bash 15 | $ cargo esp32c3 16 | $ target-gen elf target/riscv32imc-unknown-none-elf/release/esp-flashloader output/esp32c3.yaml --update --name esp32c3-flashloader 17 | ``` 18 | 19 | ## Chip support 20 | 21 | | name | supported | 22 | | ------- | --------- | 23 | | esp32 | Y | 24 | | esp32s2 | Y | 25 | | esp32s3 | Y | 26 | | esp32c2 | Y | 27 | | esp32c3 | Y | 28 | | esp32c6 | Y | 29 | | esp32h2 | Y | 30 | 31 | ## Adding new chips 32 | 33 | 1. Add a feature for the chip inside `Cargo.toml` 34 | 2. Add a build alias to `.cargo/config.toml` 35 | 3. Add the [ROM API linker script](https://github.com/search?q=repo%3Aespressif%2Fesp-idf++path%3A*rom.api.ld&type=code) inside the `ld` directory. 36 | 4. Inside the ROM API linker script, add a memory section detailing where the program will be loaded. 37 | ```c 38 | MEMORY { 39 | /* Start 64k into the RAM region */ 40 | IRAM : ORIGIN = 0x40390000, LENGTH = 0x10000 41 | } 42 | ``` 43 | It's important to note that the algorithm cannot be loaded at the start of RAM, because probe-rs has a header it loads prior to the algo hence the 64K offset. 44 | IRAM origin and length can be obtained from esp-hal. Eg: [ESP32-C3 memory map](https://github.com/esp-rs/esp-hal/blob/ff80b69183739d04d1cb154b8232be01c0b26fd9/esp32c3-hal/ld/db-esp32c3-memory.x#L5-L22) 45 | 5. Add the following snippet to the `main()` function inside `build.rs`, adapting it for the new chip name. 46 | ```rust 47 | #[cfg(feature = "esp32c3")] 48 | let chip = "esp32c3"; 49 | ``` 50 | 6. [Define `spiconfig` for your the target in `flash.rs`](https://github.com/search?q=repo%3Aespressif%2Fesp-idf+ets_efuse_get_spiconfig+path%3A*c3*&type=code) 51 | 7. Add your device to the table in `main.rs` and calculate addresses. 52 | 8. Define your target's `STATE_ADDR` 53 | ```rust 54 | #[cfg(feature = "esp32c3")] 55 | const STATE_ADDR: usize = 0x3FCC_0000; 56 | ``` 57 | 9. Follow the instructions above for building 58 | - It may fail with: `rust-lld: error: undefined symbol: ` 59 | - In this case, you need to add the missing method in the ROM API linker script. 60 | - Eg. ESP32-C2 is missing `esp_rom_spiflash_attach`: 61 | 1. [Search the symbol in esp-idf](https://github.com/search?q=repo%3Aespressif%2Fesp-idf+esp_rom_spiflash_attach+path%3A*c2*&type=code) 62 | 2. Add it to the ROM API linker script: `PROVIDE(esp_rom_spiflash_attach = spi_flash_attach);` 63 | 10. Use `target-gen` _without_ the `update` flag to generate a new yaml algorithm. 64 | 11. Update the resulting yaml file 65 | 1. Update `name` 66 | 2. Update variants `name`, `type`, `core_access_options` and `memory_map` 67 | - The first `!Nvm` block represents the raw flash starting at 0 and up to the maximum supported external flash (check TRM for this, usually in "System and Memory/Features") 68 | - Next `!Ram` block corresponds to instruction bus for internal SRAM, see Internal Memory Address Mapping of TRM 69 | - Next `!Ram` block corresponds to data bus for internal SRAM, see Internal Memory Address Mapping of TRM 70 | - Next `!Nvm` corresponds to instruction bus for external memory, see External Memory Address Mapping of TRM 71 | - Next `!Nvm` corresponds to data bus for external memory, see External Memory Address Mapping of TRM 72 | 3. Add `load_address` under `flash_algorithms` and assign the IRAM `ORIGIN` value (step 4). 73 | 4. Add `data_load_address` under `flash_algorithms` and assign an appropriate value residing in DRAM. 74 | 4. Add `transfer_encoding: Miniz` under `load_address` 75 | 12. Upstream the new updates to probe-rs. 76 | -------------------------------------------------------------------------------- /build.rs: -------------------------------------------------------------------------------- 1 | use std::path::PathBuf; 2 | use std::{env, fs}; 3 | 4 | fn main() { 5 | let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); 6 | println!("cargo:rustc-link-search={}", out_dir.display()); 7 | 8 | fs::copy("ld/loader.x", out_dir.join("loader.x")).unwrap(); 9 | println!("cargo:rerun-if-changed=ld/loader.x"); 10 | 11 | #[cfg(feature = "esp32")] 12 | let chip = "esp32"; 13 | #[cfg(feature = "esp32s2")] 14 | let chip = "esp32s2"; 15 | #[cfg(feature = "esp32s3")] 16 | let chip = "esp32s3"; 17 | #[cfg(feature = "esp32c2")] 18 | let chip = "esp32c2"; 19 | #[cfg(feature = "esp32c3")] 20 | let chip = "esp32c3"; 21 | #[cfg(feature = "esp32c6")] 22 | let chip = "esp32c6"; 23 | #[cfg(feature = "esp32h2")] 24 | let chip = "esp32h2"; 25 | 26 | { 27 | fs::copy( 28 | format!("ld/{}.x", chip), 29 | out_dir.join(format!("{}.x", chip)), 30 | ) 31 | .unwrap(); 32 | println!("cargo:rerun-if-changed=ld/{}.x", chip); 33 | println!("cargo:rustc-link-arg=-Tld/{}.x", chip); 34 | } 35 | } 36 | -------------------------------------------------------------------------------- /ld/esp32.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | /* Middle of SRAM0 */ 3 | IRAM : ORIGIN = 0x40090000, LENGTH = 0x10000 4 | } 5 | 6 | /* 7 | ESP32 ROM address table 8 | Generated for ROM with MD5sum: 9 | ab8282ae908fe9e7a63fb2a4ac2df013 ../../rom_image/prorom.elf 10 | */ 11 | PROVIDE ( Add2SelfBigHex256 = 0x40015b7c ); 12 | PROVIDE ( AddBigHex256 = 0x40015b28 ); 13 | PROVIDE ( AddBigHexModP256 = 0x40015c98 ); 14 | PROVIDE ( AddP256 = 0x40015c74 ); 15 | PROVIDE ( AddPdiv2_256 = 0x40015ce0 ); 16 | PROVIDE ( app_gpio_arg = 0x3ffe003c ); 17 | PROVIDE ( app_gpio_handler = 0x3ffe0040 ); 18 | PROVIDE ( BasePoint_x_256 = 0x3ff97488 ); 19 | PROVIDE ( BasePoint_y_256 = 0x3ff97468 ); 20 | PROVIDE ( bigHexInversion256 = 0x400168f0 ); 21 | PROVIDE ( bigHexP256 = 0x3ff973bc ); 22 | PROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c ); 23 | PROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 ); 24 | PROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 ); 25 | PROVIDE ( btdm_r_data_init = 0x4001002c ); 26 | PROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 ); 27 | PROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 ); 28 | PROVIDE ( btdm_r_ip_func_p_set = 0x40019afc ); 29 | PROVIDE ( btdm_r_modules_func_p_get = 0x4005427c ); 30 | PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 ); 31 | PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 ); 32 | PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 ); 33 | PROVIDE ( cache_flash_mmu_set_rom = 0x400095e0 ); 34 | PROVIDE ( Cache_Flush_rom = 0x40009a14 ); 35 | PROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 ); 36 | PROVIDE ( Cache_Read_Enable_rom = 0x40009a84 ); 37 | PROVIDE ( Cache_Read_Init_rom = 0x40009950 ); 38 | PROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 ); 39 | /* This is static function, but can be used, not generated by script*/ 40 | PROVIDE ( calc_rtc_memory_crc = 0x40008170 ); 41 | PROVIDE ( __clear_cache = 0x40063860 ); 42 | PROVIDE ( co_default_bdaddr = 0x3ffae704 ); 43 | PROVIDE ( co_null_bdaddr = 0x3ffb80e0 ); 44 | PROVIDE ( co_sca2ppm = 0x3ff971e8 ); 45 | PROVIDE ( crc16_be = 0x4005d09c ); 46 | PROVIDE ( crc16_le = 0x4005d05c ); 47 | PROVIDE ( crc32_be = 0x4005d024 ); 48 | PROVIDE ( crc32_le = 0x4005cfec ); 49 | PROVIDE ( crc8_be = 0x4005d114 ); 50 | PROVIDE ( crc8_le = 0x4005d0e0 ); 51 | PROVIDE ( _data_end_rom = 0x4000d5c8 ); 52 | PROVIDE ( _data_end_btdm_rom = 0x4000d4f8 ); 53 | PROVIDE ( _data_start_rom = 0x4000d4f8 ); 54 | PROVIDE ( _data_start_btdm_rom = 0x4000d4f4 ); 55 | PROVIDE ( _data_start_btdm = 0x3ffae6e0); 56 | PROVIDE ( _data_end_btdm = 0x3ffaff10); 57 | PROVIDE ( _bss_start_btdm = 0x3ffb8000); 58 | PROVIDE ( _bss_end_btdm = 0x3ffbff70); 59 | PROVIDE ( dbg_default_handler = 0x3ff97218 ); 60 | PROVIDE ( dbg_default_state = 0x3ff97220 ); 61 | PROVIDE ( dbg_state = 0x3ffb8d5d ); 62 | PROVIDE ( DebugE256PublicKey_x = 0x3ff97428 ); 63 | PROVIDE ( DebugE256PublicKey_y = 0x3ff97408 ); 64 | PROVIDE ( DebugE256SecretKey = 0x3ff973e8 ); 65 | PROVIDE ( debug_timer = 0x3ffe042c ); 66 | PROVIDE ( debug_timerfn = 0x3ffe0430 ); 67 | PROVIDE ( dh_group14_generator = 0x3ff9ac60 ); 68 | PROVIDE ( dh_group14_prime = 0x3ff9ab60 ); 69 | PROVIDE ( dh_group15_generator = 0x3ff9ab5f ); 70 | PROVIDE ( dh_group15_prime = 0x3ff9a9df ); 71 | PROVIDE ( dh_group16_generator = 0x3ff9a9de ); 72 | PROVIDE ( dh_group16_prime = 0x3ff9a7de ); 73 | PROVIDE ( dh_group17_generator = 0x3ff9a7dd ); 74 | PROVIDE ( dh_group17_prime = 0x3ff9a4dd ); 75 | PROVIDE ( dh_group18_generator = 0x3ff9a4dc ); 76 | PROVIDE ( dh_group18_prime = 0x3ff9a0dc ); 77 | PROVIDE ( dh_group1_generator = 0x3ff9ae03 ); 78 | PROVIDE ( dh_group1_prime = 0x3ff9ada3 ); 79 | PROVIDE ( dh_group2_generator = 0x3ff9ada2 ); 80 | PROVIDE ( dh_group2_prime = 0x3ff9ad22 ); 81 | PROVIDE ( dh_group5_generator = 0x3ff9ad21 ); 82 | PROVIDE ( dh_group5_prime = 0x3ff9ac61 ); 83 | PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 ); 84 | PROVIDE ( ecc_env = 0x3ffb8d60 ); 85 | PROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 ); 86 | PROVIDE ( em_buf_env = 0x3ffb8d74 ); 87 | PROVIDE ( esp_crc8 = 0x4005d144 ); 88 | PROVIDE ( _etext = 0x4000d66c ); 89 | PROVIDE ( ets_readySet_ = 0x3ffe01f0 ); 90 | PROVIDE ( ets_startup_callback = 0x3ffe0404 ); 91 | PROVIDE ( rwip_coex_cfg = 0x3ff9914c ); 92 | PROVIDE ( rwip_priority = 0x3ff99159 ); 93 | PROVIDE ( exc_cause_table = 0x3ff991d0 ); 94 | PROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 ); 95 | PROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 ); 96 | PROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c ); 97 | PROVIDE ( g_phyFuns_instance = 0x3ffae0c4 ); 98 | PROVIDE ( g_rom_flashchip = 0x3ffae270 ); 99 | PROVIDE ( gTxMsg = 0x3ffe0050 ); 100 | PROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 ); 101 | PROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 ); 102 | PROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c ); 103 | PROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 ); 104 | PROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 ); 105 | PROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c ); 106 | PROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 ); 107 | PROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 ); 108 | PROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 ); 109 | PROVIDE ( hci_command_handler = 0x4004c928 ); 110 | PROVIDE ( hci_env = 0x3ffb9350 ); 111 | PROVIDE ( rwip_env = 0x3ffb8bcc ); 112 | PROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c ); 113 | PROVIDE ( hci_evt_desc_tab = 0x3ff9751c ); 114 | PROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 ); 115 | PROVIDE ( hci_fc_env = 0x3ffb9340 ); 116 | PROVIDE ( jd_decomp = 0x400613e8 ); 117 | PROVIDE ( jd_prepare = 0x40060fa8 ); 118 | PROVIDE ( ke_env = 0x3ffb93cc ); 119 | PROVIDE ( ke_handler_search = 0x4001a430 ); 120 | PROVIDE ( ke_task_env = 0x3ffb81d4 ); 121 | PROVIDE ( ke_event_env = 0x3ffb81a4 ); 122 | PROVIDE ( lb_default_handler = 0x3ff982b8 ); 123 | PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 ); 124 | PROVIDE ( lb_env = 0x3ffb9424 ); 125 | PROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c ); 126 | PROVIDE ( lb_state = 0x3ffb94e8 ); 127 | PROVIDE ( lc_default_handler = 0x3ff98648 ); 128 | PROVIDE ( lc_default_state_tab_p_get = 0x4002f494 ); 129 | PROVIDE ( lc_env = 0x3ffb94ec ); 130 | PROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 ); 131 | PROVIDE ( lc_state = 0x3ffb9508 ); 132 | PROVIDE ( ld_acl_br_sizes = 0x3ff98a2a ); 133 | PROVIDE ( ld_acl_br_types = 0x3ff98a36 ); 134 | PROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 ); 135 | PROVIDE ( ld_acl_edr_types = 0x3ff98a22 ); 136 | PROVIDE ( ld_env = 0x3ffb9510 ); 137 | PROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c ); 138 | PROVIDE ( ld_sched_params = 0x3ffb96c0 ); 139 | PROVIDE ( ld_sync_train_channels = 0x3ff98a3c ); 140 | PROVIDE ( llc_default_handler = 0x3ff98b3c ); 141 | PROVIDE ( llc_default_state_tab_p_get = 0x40046058 ); 142 | PROVIDE ( llc_env = 0x3ffb96d0 ); 143 | PROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 ); 144 | PROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 ); 145 | PROVIDE ( llc_hci_command_handler = 0x40042360 ); 146 | PROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 ); 147 | PROVIDE ( llc_state = 0x3ffb96f8 ); 148 | PROVIDE ( lldesc_build_chain = 0x4000a850 ); 149 | PROVIDE ( lldesc_num2link = 0x4000a948 ); 150 | PROVIDE ( lldesc_set_owner = 0x4000a974 ); 151 | PROVIDE ( lld_evt_deferred_elt_push = 0x400466b4 ); 152 | PROVIDE ( lld_evt_deferred_elt_pop = 0x400466dc ); 153 | PROVIDE ( lld_evt_winsize_change = 0x40046730 ); 154 | PROVIDE ( lld_evt_rxwin_compute = 0x400467c8 ); 155 | PROVIDE ( lld_evt_slave_time_compute = 0x40046818 ); 156 | PROVIDE ( lld_evt_env = 0x3ffb9704 ); 157 | PROVIDE ( lld_evt_elt_wait_get = 0x400468e4 ); 158 | PROVIDE ( lld_evt_get_next_free_slot = 0x4004692c ); 159 | PROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 ); 160 | PROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 ); 161 | PROVIDE ( lld_pdu_tx_flush_list = 0x4004a760 ); 162 | PROVIDE ( lld_pdu_pack = 0x4004ab14 ); 163 | PROVIDE ( LLM_AA_CT1 = 0x3ff98d8a ); 164 | PROVIDE ( LLM_AA_CT2 = 0x3ff98d88 ); 165 | PROVIDE ( llm_default_handler = 0x3ff98d80 ); 166 | PROVIDE ( llm_default_state_tab_p_get = 0x4004e718 ); 167 | PROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 ); 168 | PROVIDE ( llm_le_env = 0x3ffb976c ); 169 | PROVIDE ( llm_local_cmds = 0x3ff98d38 ); 170 | PROVIDE ( llm_local_data_len_values = 0x3ff98d1c ); 171 | PROVIDE ( llm_local_le_feats = 0x3ff98d30 ); 172 | PROVIDE ( llm_local_le_states = 0x3ff98d28 ); 173 | PROVIDE ( llm_state = 0x3ffb985c ); 174 | PROVIDE ( lm_default_handler = 0x3ff990e0 ); 175 | PROVIDE ( lm_default_state_tab_p_get = 0x40054268 ); 176 | PROVIDE ( lm_env = 0x3ffb9860 ); 177 | PROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c ); 178 | PROVIDE ( lm_local_supp_feats = 0x3ff990ee ); 179 | PROVIDE ( lm_n_page_tab = 0x3ff990e8 ); 180 | PROVIDE ( lmp_desc_tab = 0x3ff96e6c ); 181 | PROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c ); 182 | PROVIDE ( lm_state = 0x3ffb9a1c ); 183 | PROVIDE ( maxSecretKey_256 = 0x3ff97448 ); 184 | PROVIDE ( mmu_init = 0x400095a4 ); 185 | PROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 ); 186 | PROVIDE ( MultiplyBigHexModP256 = 0x400160b8 ); 187 | PROVIDE ( MultiplyByU32ModP256 = 0x40015fdc ); 188 | PROVIDE ( multofup = 0x4000ab8c ); 189 | PROVIDE ( mz_adler32 = 0x4005edbc ); 190 | PROVIDE ( mz_crc32 = 0x4005ee88 ); 191 | PROVIDE ( mz_free = 0x4005eed4 ); 192 | PROVIDE ( notEqual256 = 0x40015b04 ); 193 | PROVIDE ( one_bits = 0x3ff971f8 ); 194 | PROVIDE ( phy_get_romfuncs = 0x40004100 ); 195 | PROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 ); 196 | PROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c ); 197 | PROVIDE ( r_btdm_option_data = 0x3ffae6e0 ); 198 | PROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 ); 199 | PROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 ); 200 | PROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 ); 201 | PROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 ); 202 | PROVIDE ( r_bt_util_buf_init = 0x400100e4 ); 203 | PROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 ); 204 | PROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec ); 205 | PROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 ); 206 | PROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 ); 207 | PROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 ); 208 | PROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c ); 209 | PROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec ); 210 | PROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 ); 211 | PROVIDE ( r_co_bdaddr_compare = 0x40014324 ); 212 | PROVIDE ( r_co_bytes_to_string = 0x400142e4 ); 213 | PROVIDE ( r_co_list_check_size_available = 0x400142c4 ); 214 | PROVIDE ( r_co_list_extract = 0x4001404c ); 215 | PROVIDE ( r_co_list_extract_after = 0x40014118 ); 216 | PROVIDE ( r_co_list_find = 0x4001419c ); 217 | PROVIDE ( r_co_list_init = 0x40013f14 ); 218 | PROVIDE ( r_co_list_insert_after = 0x40014254 ); 219 | PROVIDE ( r_co_list_insert_before = 0x40014200 ); 220 | PROVIDE ( r_co_list_merge = 0x400141bc ); 221 | PROVIDE ( r_co_list_pool_init = 0x40013f30 ); 222 | PROVIDE ( r_co_list_pop_front = 0x40014028 ); 223 | PROVIDE ( r_co_list_push_back = 0x40013fb8 ); 224 | PROVIDE ( r_co_list_push_front = 0x40013ff4 ); 225 | PROVIDE ( r_co_list_size = 0x400142ac ); 226 | PROVIDE ( r_co_nb_good_channels = 0x40014360 ); 227 | PROVIDE ( r_co_slot_to_duration = 0x40014348 ); 228 | PROVIDE ( r_dbg_init = 0x40014394 ); 229 | PROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 ); 230 | PROVIDE ( r_dbg_swdiag_init = 0x40014470 ); 231 | PROVIDE ( r_dbg_swdiag_read = 0x400144a4 ); 232 | PROVIDE ( r_dbg_swdiag_write = 0x400144d0 ); 233 | PROVIDE ( r_E1 = 0x400108e8 ); 234 | PROVIDE ( r_E21 = 0x40010968 ); 235 | PROVIDE ( r_E22 = 0x400109b4 ); 236 | PROVIDE ( r_E3 = 0x40010a58 ); 237 | PROVIDE ( lm_n192_mod_mul = 0x40011dc0 ); 238 | PROVIDE ( lm_n192_mod_add = 0x40011e9c ); 239 | PROVIDE ( lm_n192_mod_sub = 0x40011eec ); 240 | PROVIDE ( r_ea_alarm_clear = 0x40015ab4 ); 241 | PROVIDE ( r_ea_alarm_set = 0x40015a10 ); 242 | PROVIDE ( r_ea_elt_cancel = 0x400150d0 ); 243 | PROVIDE ( r_ea_elt_create = 0x40015264 ); 244 | PROVIDE ( r_ea_elt_insert = 0x400152a8 ); 245 | PROVIDE ( r_ea_elt_remove = 0x400154f0 ); 246 | PROVIDE ( r_ea_finetimer_isr = 0x400155d4 ); 247 | PROVIDE ( r_ea_init = 0x40015228 ); 248 | PROVIDE ( r_ea_interval_create = 0x4001555c ); 249 | PROVIDE ( r_ea_interval_delete = 0x400155a8 ); 250 | PROVIDE ( r_ea_interval_duration_req = 0x4001597c ); 251 | PROVIDE ( r_ea_interval_insert = 0x4001557c ); 252 | PROVIDE ( r_ea_interval_remove = 0x40015590 ); 253 | PROVIDE ( ea_conflict_check = 0x40014e9c ); 254 | PROVIDE ( ea_prog_timer = 0x40014f88 ); 255 | PROVIDE ( r_ea_offset_req = 0x40015748 ); 256 | PROVIDE ( r_ea_sleep_check = 0x40015928 ); 257 | PROVIDE ( r_ea_sw_isr = 0x40015724 ); 258 | PROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 ); 259 | PROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 ); 260 | PROVIDE ( r_ecc_abort_key256_generation = 0x40017070 ); 261 | PROVIDE ( r_ecc_generate_key256 = 0x40016e00 ); 262 | PROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 ); 263 | PROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 ); 264 | PROVIDE ( r_ecc_get_debug_Keys = 0x40017224 ); 265 | PROVIDE ( r_ecc_init = 0x40016dbc ); 266 | PROVIDE ( ecc_point_multiplication_uint8_256 = 0x40016804); 267 | PROVIDE ( RecvBuff = 0x3ffe009c ); 268 | PROVIDE ( r_em_buf_init = 0x4001729c ); 269 | PROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 ); 270 | PROVIDE ( r_em_buf_rx_free = 0x400173c4 ); 271 | PROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 ); 272 | PROVIDE ( r_em_buf_tx_free = 0x4001741c ); 273 | PROVIDE ( r_F1_256 = 0x400133e4 ); 274 | PROVIDE ( r_F2_256 = 0x40013568 ); 275 | PROVIDE ( r_F3_256 = 0x40013664 ); 276 | PROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c ); 277 | PROVIDE ( r_G_256 = 0x40013470 ); 278 | PROVIDE ( r_H3 = 0x40013760 ); 279 | PROVIDE ( r_H4 = 0x40013830 ); 280 | PROVIDE ( r_h4tl_init = 0x40017878 ); 281 | PROVIDE ( r_h4tl_start = 0x40017924 ); 282 | PROVIDE ( r_h4tl_stop = 0x40017934 ); 283 | PROVIDE ( r_h4tl_write = 0x400178d0 ); 284 | PROVIDE ( r_H5 = 0x400138dc ); 285 | PROVIDE ( r_hashConcat = 0x40013a38 ); 286 | PROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c ); 287 | PROVIDE ( r_hci_acl_tx_data_received = 0x40019654 ); 288 | PROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 ); 289 | PROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac ); 290 | PROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c ); 291 | PROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 ); 292 | PROVIDE ( r_hci_cmd_received = 0x400192f8 ); 293 | PROVIDE ( r_hci_evt_filter_add = 0x40018a64 ); 294 | PROVIDE ( r_hci_evt_mask_set = 0x400189e4 ); 295 | PROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 ); 296 | PROVIDE ( r_hci_fc_acl_en = 0x400179d8 ); 297 | PROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c ); 298 | PROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 ); 299 | PROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 ); 300 | PROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c ); 301 | PROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 ); 302 | PROVIDE ( r_hci_fc_init = 0x40017974 ); 303 | PROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 ); 304 | PROVIDE ( r_hci_fc_sync_en = 0x40017a30 ); 305 | PROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 ); 306 | PROVIDE ( r_hci_init = 0x40018538 ); 307 | PROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 ); 308 | PROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 ); 309 | PROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 ); 310 | PROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 ); 311 | PROVIDE ( r_hci_reset = 0x4001856c ); 312 | PROVIDE ( r_hci_send_2_host = 0x400185bc ); 313 | PROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 ); 314 | PROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 ); 315 | PROVIDE ( r_hci_tl_init = 0x40019290 ); 316 | PROVIDE ( r_hci_tl_send = 0x40019228 ); 317 | PROVIDE ( r_hci_util_pack = 0x40019874 ); 318 | PROVIDE ( r_hci_util_unpack = 0x40019998 ); 319 | PROVIDE ( r_hci_voice_settings_get = 0x40018bdc ); 320 | PROVIDE ( r_hci_voice_settings_set = 0x40018be8 ); 321 | PROVIDE ( r_HMAC = 0x40013968 ); 322 | PROVIDE ( r_import_rf_phy_func = 0x3ffb8354 ); 323 | PROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 ); 324 | PROVIDE ( r_ip_funcs = 0x3ffae710 ); 325 | PROVIDE ( r_ip_funcs_p = 0x3ffae70c ); 326 | PROVIDE ( r_ke_check_malloc = 0x40019de0 ); 327 | PROVIDE ( r_ke_event_callback_set = 0x40019ba8 ); 328 | PROVIDE ( r_ke_event_clear = 0x40019c2c ); 329 | PROVIDE ( r_ke_event_flush = 0x40019ccc ); 330 | PROVIDE ( r_ke_event_get = 0x40019c78 ); 331 | PROVIDE ( r_ke_event_get_all = 0x40019cc0 ); 332 | PROVIDE ( r_ke_event_init = 0x40019b90 ); 333 | PROVIDE ( r_ke_event_schedule = 0x40019cdc ); 334 | PROVIDE ( r_ke_event_set = 0x40019be0 ); 335 | PROVIDE ( r_ke_flush = 0x4001a374 ); 336 | PROVIDE ( r_ke_free = 0x4001a014 ); 337 | PROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 ); 338 | PROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 ); 339 | PROVIDE ( r_ke_init = 0x4001a318 ); 340 | PROVIDE ( r_ke_is_free = 0x4001a184 ); 341 | PROVIDE ( r_ke_malloc = 0x40019eb4 ); 342 | PROVIDE ( r_ke_mem_init = 0x40019d3c ); 343 | PROVIDE ( r_ke_mem_is_empty = 0x40019d8c ); 344 | PROVIDE ( r_ke_msg_alloc = 0x4001a1e0 ); 345 | PROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 ); 346 | PROVIDE ( r_ke_msg_discard = 0x4001a850 ); 347 | PROVIDE ( r_ke_msg_forward = 0x4001a290 ); 348 | PROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac ); 349 | PROVIDE ( r_ke_msg_free = 0x4001a2cc ); 350 | PROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 ); 351 | PROVIDE ( r_ke_msg_save = 0x4001a858 ); 352 | PROVIDE ( r_ke_msg_send = 0x4001a234 ); 353 | PROVIDE ( r_ke_msg_send_basic = 0x4001a26c ); 354 | PROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec ); 355 | PROVIDE ( r_ke_queue_extract = 0x40055fd0 ); 356 | PROVIDE ( r_ke_queue_insert = 0x40056020 ); 357 | PROVIDE ( r_ke_sleep_check = 0x4001a3d8 ); 358 | PROVIDE ( r_ke_state_get = 0x4001a7d8 ); 359 | PROVIDE ( r_ke_state_set = 0x4001a6fc ); 360 | PROVIDE ( r_ke_stats_get = 0x4001a3f0 ); 361 | PROVIDE ( r_ke_task_check = 0x4001a8a4 ); 362 | PROVIDE ( r_ke_task_create = 0x4001a674 ); 363 | PROVIDE ( r_ke_task_delete = 0x4001a6c0 ); 364 | PROVIDE ( r_ke_task_init = 0x4001a650 ); 365 | PROVIDE ( r_ke_task_msg_flush = 0x4001a860 ); 366 | PROVIDE ( r_ke_timer_active = 0x4001ac08 ); 367 | PROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 ); 368 | PROVIDE ( r_ke_timer_clear = 0x4001ab90 ); 369 | PROVIDE ( r_ke_timer_init = 0x4001aa9c ); 370 | PROVIDE ( r_ke_timer_set = 0x4001aac0 ); 371 | PROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 ); 372 | PROVIDE ( r_KPrimC = 0x40010ad4 ); 373 | PROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 ); 374 | PROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 ); 375 | PROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 ); 376 | PROVIDE ( r_lb_init = 0x4001acd4 ); 377 | PROVIDE ( r_lb_mst_key = 0x4001afc0 ); 378 | PROVIDE ( r_lb_mst_key_cmp = 0x4001af74 ); 379 | PROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 ); 380 | PROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 ); 381 | PROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c ); 382 | PROVIDE ( r_lb_reset = 0x4001ad38 ); 383 | PROVIDE ( r_lb_send_lmp = 0x4001adbc ); 384 | PROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c ); 385 | PROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 ); 386 | PROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 ); 387 | PROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 ); 388 | PROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c ); 389 | PROVIDE ( r_lc_afh_set = 0x4001cc74 ); 390 | PROVIDE ( r_lc_afh_start = 0x4001d240 ); 391 | PROVIDE ( r_lc_auth_cmp = 0x4001cd54 ); 392 | PROVIDE ( r_lc_calc_link_key = 0x4001ce7c ); 393 | PROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 ); 394 | PROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc ); 395 | PROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac ); 396 | PROVIDE ( r_lc_chk_to = 0x4001d2a8 ); 397 | PROVIDE ( r_lc_cmd_stat_send = 0x4001c914 ); 398 | PROVIDE ( r_lc_comb_key_svr = 0x4001d30c ); 399 | PROVIDE ( r_lc_con_cmp = 0x4001d44c ); 400 | PROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc ); 401 | PROVIDE ( r_lc_conn_seq_done = 0x40021334 ); 402 | PROVIDE ( r_lc_detach = 0x4002037c ); 403 | PROVIDE ( r_lc_dhkey = 0x4001d564 ); 404 | PROVIDE ( r_lc_enc_cmp = 0x4001d8bc ); 405 | PROVIDE ( r_lc_enc_key_refresh = 0x4001d720 ); 406 | PROVIDE ( r_lc_end_chk_colli = 0x4001d858 ); 407 | PROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 ); 408 | PROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 ); 409 | PROVIDE ( r_lc_epr_change_lk = 0x4001db38 ); 410 | PROVIDE ( r_lc_epr_cmp = 0x4001da88 ); 411 | PROVIDE ( r_lc_epr_resp = 0x4001e0b4 ); 412 | PROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 ); 413 | PROVIDE ( r_lc_ext_feat = 0x40020d6c ); 414 | PROVIDE ( r_lc_feat = 0x40020984 ); 415 | PROVIDE ( r_lc_hl_connect = 0x400209e8 ); 416 | PROVIDE ( r_lc_init = 0x4001c948 ); 417 | PROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 ); 418 | PROVIDE ( r_lc_initiator_epr = 0x4001e064 ); 419 | PROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 ); 420 | PROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 ); 421 | PROVIDE ( r_lc_key_exch_end = 0x4001e140 ); 422 | PROVIDE ( r_lc_legacy_pair = 0x4001e1c0 ); 423 | PROVIDE ( r_lc_local_switch = 0x4001e22c ); 424 | PROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 ); 425 | PROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 ); 426 | PROVIDE ( r_lc_loc_auth = 0x40020ecc ); 427 | PROVIDE ( r_lc_locepr_lkref = 0x4001d648 ); 428 | PROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 ); 429 | PROVIDE ( r_lc_loc_sniff = 0x40020a6c ); 430 | PROVIDE ( r_lc_max_slot_mgt = 0x4001e410 ); 431 | PROVIDE ( r_lc_mst_key = 0x4001e7c0 ); 432 | PROVIDE ( r_lc_mst_qos_done = 0x4001ea80 ); 433 | PROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 ); 434 | PROVIDE ( r_lc_mutual_auth_end = 0x4001e670 ); 435 | PROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 ); 436 | PROVIDE ( r_lc_packet_type = 0x40021038 ); 437 | PROVIDE ( r_lc_pair = 0x40020ddc ); 438 | PROVIDE ( r_lc_pairing_cont = 0x4001eafc ); 439 | PROVIDE ( r_lc_passkey_comm = 0x4001ed20 ); 440 | PROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 ); 441 | PROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec ); 442 | PROVIDE ( r_lc_ptt = 0x4001ee2c ); 443 | PROVIDE ( r_lc_ptt_cmp = 0x4001eeec ); 444 | PROVIDE ( r_lc_qos_setup = 0x4001ef50 ); 445 | PROVIDE ( r_lc_rd_rem_name = 0x4001efd0 ); 446 | PROVIDE ( r_lc_release = 0x4001f8a8 ); 447 | PROVIDE ( r_lc_rem_enc = 0x4001f124 ); 448 | PROVIDE ( r_lc_rem_name_cont = 0x4001f290 ); 449 | PROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 ); 450 | PROVIDE ( r_lc_rem_sniff = 0x40020ca4 ); 451 | PROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 ); 452 | PROVIDE ( r_lc_rem_switch = 0x4001f070 ); 453 | PROVIDE ( r_lc_rem_trans_mode = 0x4001f314 ); 454 | PROVIDE ( r_lc_rem_unsniff = 0x400207a0 ); 455 | PROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c ); 456 | PROVIDE ( r_lc_reset = 0x4001c99c ); 457 | PROVIDE ( r_lc_resp_auth = 0x4001f518 ); 458 | PROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 ); 459 | PROVIDE ( r_lc_resp_num_comp = 0x40020074 ); 460 | PROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 ); 461 | PROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c ); 462 | PROVIDE ( r_lc_resp_pair = 0x400208a4 ); 463 | PROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 ); 464 | PROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c ); 465 | PROVIDE ( r_lc_restart_enc = 0x4001f8ec ); 466 | PROVIDE ( r_lc_restart_enc_cont = 0x4001f940 ); 467 | PROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 ); 468 | PROVIDE ( r_lc_restore_to = 0x4001f9e0 ); 469 | PROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 ); 470 | PROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 ); 471 | PROVIDE ( r_lc_rsw_done = 0x4001db94 ); 472 | PROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 ); 473 | PROVIDE ( r_lc_sco_detach = 0x40021e40 ); 474 | PROVIDE ( r_lc_sco_host_accept = 0x40022118 ); 475 | PROVIDE ( r_lc_sco_host_reject = 0x400222b8 ); 476 | PROVIDE ( r_lc_sco_host_request = 0x40021f4c ); 477 | PROVIDE ( r_lc_sco_host_request_disc = 0x4002235c ); 478 | PROVIDE ( r_lc_sco_init = 0x40021dc8 ); 479 | PROVIDE ( r_lc_sco_peer_accept = 0x40022780 ); 480 | PROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 ); 481 | PROVIDE ( r_lc_sco_peer_reject = 0x40022824 ); 482 | PROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c ); 483 | PROVIDE ( r_lc_sco_peer_request = 0x4002240c ); 484 | PROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec ); 485 | PROVIDE ( r_lc_sco_release = 0x40021eec ); 486 | PROVIDE ( r_lc_sco_reset = 0x40021dfc ); 487 | PROVIDE ( r_lc_sco_timeout = 0x40022bd4 ); 488 | PROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec ); 489 | PROVIDE ( r_lc_semi_key_cmp = 0x40020294 ); 490 | PROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c ); 491 | PROVIDE ( r_lc_send_enc_mode = 0x40020220 ); 492 | PROVIDE ( r_lc_send_lmp = 0x4001c1a8 ); 493 | PROVIDE ( r_lc_send_pdu_acc = 0x4001c21c ); 494 | PROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 ); 495 | PROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 ); 496 | PROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 ); 497 | PROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c ); 498 | PROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 ); 499 | PROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 ); 500 | PROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 ); 501 | PROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 ); 502 | PROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 ); 503 | PROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 ); 504 | PROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 ); 505 | PROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec ); 506 | PROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 ); 507 | PROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 ); 508 | PROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c ); 509 | PROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c ); 510 | PROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 ); 511 | PROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec ); 512 | PROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c ); 513 | PROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 ); 514 | PROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 ); 515 | PROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 ); 516 | PROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 ); 517 | PROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 ); 518 | PROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c ); 519 | PROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 ); 520 | PROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 ); 521 | PROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 ); 522 | PROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 ); 523 | PROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 ); 524 | PROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 ); 525 | PROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 ); 526 | PROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 ); 527 | PROVIDE ( r_lc_send_pdu_sres = 0x4001c548 ); 528 | PROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc ); 529 | PROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 ); 530 | PROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 ); 531 | PROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 ); 532 | PROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc ); 533 | PROVIDE ( r_lc_sniff_init = 0x40022cac ); 534 | PROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 ); 535 | PROVIDE ( r_lc_sniff_reset = 0x40022cc8 ); 536 | PROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 ); 537 | PROVIDE ( r_lc_sniff_sub_mode = 0x400204fc ); 538 | PROVIDE ( r_lc_sp_end = 0x400213a8 ); 539 | PROVIDE ( r_lc_sp_fail = 0x40020470 ); 540 | PROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc ); 541 | PROVIDE ( r_lc_ssr_nego = 0x4002125c ); 542 | PROVIDE ( r_lc_start = 0x4001ca28 ); 543 | PROVIDE ( r_lc_start_enc = 0x4001fb28 ); 544 | PROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c ); 545 | PROVIDE ( r_lc_start_key_exch = 0x4001fe10 ); 546 | PROVIDE ( r_lc_start_lmp_to = 0x4001fae8 ); 547 | PROVIDE ( r_lc_start_oob = 0x4001fffc ); 548 | PROVIDE ( r_lc_start_passkey = 0x4001feac ); 549 | PROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 ); 550 | PROVIDE ( r_lc_stop_afh_report = 0x40020184 ); 551 | PROVIDE ( r_lc_stop_enc = 0x40020110 ); 552 | PROVIDE ( r_lc_switch_cmp = 0x40020448 ); 553 | PROVIDE ( r_lc_unit_key_svr = 0x400206d8 ); 554 | PROVIDE ( r_lc_unsniff = 0x40020c50 ); 555 | PROVIDE ( r_lc_unsniff_cmp = 0x40020810 ); 556 | PROVIDE ( r_lc_unsniff_cont = 0x40020750 ); 557 | PROVIDE ( r_lc_upd_to = 0x4002065c ); 558 | PROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 ); 559 | PROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac ); 560 | PROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 ); 561 | PROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c ); 562 | PROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 ); 563 | PROVIDE ( r_lc_version = 0x40020a30 ); 564 | PROVIDE ( lc_set_encap_pdu_data_p192 = 0x4002e4c8 ); 565 | PROVIDE ( lc_set_encap_pdu_data_p256 = 0x4002e454 ); 566 | PROVIDE ( lm_get_auth_method = 0x40023420); 567 | PROVIDE ( lmp_accepted_ext_handler = 0x40027290 ); 568 | PROVIDE ( lmp_not_accepted_ext_handler = 0x40029c54 ); 569 | PROVIDE ( lmp_clk_adj_handler = 0x40027468 ); 570 | PROVIDE ( lmp_clk_adj_ack_handler = 0x400274f4 ); 571 | PROVIDE ( lm_get_auth_method = 0x40023420); 572 | PROVIDE ( lmp_accepted_ext_handler = 0x40027290 ); 573 | PROVIDE ( lmp_not_accepted_ext_handler = 0x40029c54 ); 574 | PROVIDE ( lmp_clk_adj_handler = 0x40027468 ); 575 | PROVIDE ( lmp_clk_adj_ack_handler = 0x400274f4 ); 576 | PROVIDE ( lmp_clk_adj_req_handler = 0x4002751c ); 577 | PROVIDE ( lmp_feats_res_ext_handler = 0x4002cac4 ); 578 | PROVIDE ( lmp_feats_req_ext_handler = 0x4002ccb0 ); 579 | PROVIDE ( lmp_pkt_type_tbl_req_handler = 0x40027574 ); 580 | PROVIDE ( lmp_esco_link_req_handler = 0x40027610 ); 581 | PROVIDE ( lmp_rmv_esco_link_req_handler = 0x400276e8 ); 582 | PROVIDE ( lmp_ch_class_req_handler = 0x40027730 ); 583 | PROVIDE ( lmp_ch_class_handler = 0x4002ca18 ); 584 | PROVIDE ( lmp_ssr_req_handler = 0x4002780c ); 585 | PROVIDE ( lmp_ssr_res_handler = 0x40027900 ); 586 | PROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 ); 587 | PROVIDE ( lmp_pause_enc_req_handler = 0x4002df90 ); 588 | PROVIDE ( lmp_resume_enc_req_handler = 0x4002e084 ); 589 | PROVIDE ( lmp_num_comparison_fail_handler = 0x40027a74 ); 590 | PROVIDE ( lmp_passkey_fail_handler = 0x40027aec ); 591 | PROVIDE ( lmp_keypress_notif_handler = 0x4002c5c8 ); 592 | PROVIDE ( lmp_pwr_ctrl_req_handler = 0x400263bc ); 593 | PROVIDE ( lmp_pwr_ctrl_res_handler = 0x40026480 ); 594 | PROVIDE ( lmp_auto_rate_handler = 0x40026548 ); 595 | PROVIDE ( lmp_pref_rate_handler = 0x4002657c ); 596 | PROVIDE ( lmp_name_req_handler = 0x40025050 ); 597 | PROVIDE ( lmp_name_res_handler = 0x400250bc ); 598 | PROVIDE ( lmp_not_accepted_handler = 0x400251d0 ); 599 | PROVIDE ( lmp_accepted_handler = 0x4002e894 ); 600 | PROVIDE ( lmp_clk_off_req_handler = 0x40025a44 ); 601 | PROVIDE ( lmp_clk_off_res_handler = 0x40025ab8 ); 602 | PROVIDE ( lmp_detach_handler = 0x40025b74 ); 603 | PROVIDE ( lmp_tempkey_handler = 0x4002b6b0 ); 604 | PROVIDE ( lmp_temprand_handler = 0x4002b74c ); 605 | PROVIDE ( lmp_sres_handler = 0x4002b840 ); 606 | PROVIDE ( lmp_aurand_handler = 0x4002bda0 ); 607 | PROVIDE ( lmp_unitkey_handler = 0x4002c13c ); 608 | PROVIDE ( lmp_combkey_handler = 0x4002c234 ); 609 | PROVIDE ( lmp_inrand_handler = 0x4002c414 ); 610 | PROVIDE ( lmp_oob_fail_handler = 0x40027b84 ); 611 | PROVIDE ( lmp_ping_req_handler = 0x40027c08 ); 612 | PROVIDE ( lmp_ping_res_handler = 0x40027c5c ); 613 | PROVIDE ( lmp_enc_mode_req_handler = 0x40025c60 ); 614 | PROVIDE ( lmp_enc_key_size_req_handler = 0x40025e54 ); 615 | PROVIDE ( lmp_switch_req_handler = 0x40025f84 ); 616 | PROVIDE ( lmp_start_enc_req_handler = 0x4002e124 ); 617 | PROVIDE ( lmp_stop_enc_req_handler = 0x4002de30 ); 618 | PROVIDE ( lmp_sniff_req_handler = 0x400260c8 ); 619 | PROVIDE ( lmp_unsniff_req_handler = 0x400261e0 ); 620 | PROVIDE ( lmp_incr_pwr_req_handler = 0x4002629c ); 621 | PROVIDE ( lmp_decr_pwr_req_handler = 0x400262f8 ); 622 | PROVIDE ( lmp_max_pwr_handler = 0x40026354 ); 623 | PROVIDE ( lmp_min_pwr_handler = 0x40026388 ); 624 | PROVIDE ( lmp_ver_req_handler = 0x400265f0 ); 625 | PROVIDE ( lmp_ver_res_handler = 0x40026670 ); 626 | PROVIDE ( lmp_qos_handler = 0x40026790 ); 627 | PROVIDE ( lmp_qos_req_handler = 0x40026844 ); 628 | PROVIDE ( lmp_sco_link_req_handler = 0x40026930 ); 629 | PROVIDE ( lmp_rmv_sco_link_req_handler = 0x40026a10 ); 630 | PROVIDE ( lmp_max_slot_handler = 0x40026a54 ); 631 | PROVIDE ( lmp_max_slot_req_handler = 0x40026aac ); 632 | PROVIDE ( lmp_timing_accu_req_handler = 0x40026b54 ); 633 | PROVIDE ( lmp_timing_accu_res_handler = 0x40026bcc ); 634 | PROVIDE ( lmp_setup_cmp_handler = 0x40026c84 ); 635 | PROVIDE ( lmp_feats_res_handler = 0x4002b548 ); 636 | PROVIDE ( lmp_feats_req_handler = 0x4002b620 ); 637 | PROVIDE ( lmp_host_con_req_handler = 0x4002b3d8 ); 638 | PROVIDE ( lmp_use_semi_perm_key_handler = 0x4002b4c4 ); 639 | PROVIDE ( lmp_slot_off_handler = 0x40026cc8 ); 640 | PROVIDE ( lmp_page_mode_req_handler = 0x40026d0c ); 641 | PROVIDE ( lmp_page_scan_mode_req_handler = 0x40026d4c ); 642 | PROVIDE ( lmp_supv_to_handler = 0x40026d94 ); 643 | PROVIDE ( lmp_test_activate_handler = 0x40026e7c ); 644 | PROVIDE ( lmp_test_ctrl_handler = 0x40026ee4 ); 645 | PROVIDE ( lmp_enc_key_size_mask_req_handler = 0x40027038 ); 646 | PROVIDE ( lmp_enc_key_size_mask_res_handler = 0x400270a4 ); 647 | PROVIDE ( lmp_set_afh_handler = 0x4002b2e4 ); 648 | PROVIDE ( lmp_encaps_hdr_handler = 0x40027120 ); 649 | PROVIDE ( lmp_encaps_payl_handler = 0x4002e590 ); 650 | PROVIDE ( lmp_sp_nb_handler = 0x4002acf0 ); 651 | PROVIDE ( lmp_sp_cfm_handler = 0x4002b170 ); 652 | PROVIDE ( lmp_dhkey_chk_handler = 0x4002ab48 ); 653 | PROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 ); 654 | PROVIDE ( lmp_io_cap_res_handler = 0x4002c670 ); 655 | PROVIDE ( lmp_io_cap_req_handler = 0x4002c7a4 ); 656 | PROVIDE ( lc_cmd_cmp_bd_addr_send = 0x4002cec4 ); 657 | PROVIDE ( ld_acl_tx_packet_type_select = 0x4002fb40 ); 658 | PROVIDE ( ld_acl_sched = 0x40033268 ); 659 | PROVIDE ( ld_acl_sniff_sched = 0x4003340c ); 660 | PROVIDE ( ld_acl_sniff_exit = 0x400312b4 ); 661 | PROVIDE ( ld_acl_rx = 0x4003274c ); 662 | PROVIDE ( ld_acl_tx = 0x4002ffdc ); 663 | PROVIDE ( ld_acl_rx_sync = 0x4002fbec ); 664 | PROVIDE ( ld_acl_rx_sync2 = 0x4002fd8c ); 665 | PROVIDE ( ld_acl_rx_no_sync = 0x4002fe78 ); 666 | PROVIDE ( ld_acl_clk_isr = 0x40030cf8 ); 667 | PROVIDE ( ld_acl_rsw_frm_cbk = 0x40033bb0 ); 668 | PROVIDE ( ld_sco_modify = 0x40031778 ); 669 | PROVIDE ( lm_cmd_cmp_send = 0x40051838 ); 670 | PROVIDE ( ld_sco_frm_cbk = 0x400349dc ); 671 | PROVIDE ( ld_acl_sco_rsvd_check = 0x4002fa94 ); 672 | PROVIDE ( ld_acl_sniff_frm_cbk = 0x4003482c ); 673 | PROVIDE ( ld_inq_end = 0x4003ab48 ); 674 | PROVIDE ( ld_inq_sched = 0x4003aba4 ); 675 | PROVIDE ( ld_inq_frm_cbk = 0x4003ae4c ); 676 | PROVIDE ( ld_pscan_frm_cbk = 0x4003ebe4 ); 677 | PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 ); 678 | PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 ); 679 | PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 ); 680 | PROVIDE ( r_ld_acl_afh_set = 0x40036b60 ); 681 | PROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 ); 682 | PROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 ); 683 | PROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 ); 684 | PROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 ); 685 | PROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 ); 686 | PROVIDE ( r_ld_acl_clk_set = 0x40036950 ); 687 | PROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 ); 688 | PROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 ); 689 | PROVIDE ( r_ld_acl_data_flush = 0x400357bc ); 690 | PROVIDE ( r_ld_acl_data_tx = 0x4003544c ); 691 | PROVIDE ( r_ld_acl_edr_set = 0x4003678c ); 692 | PROVIDE ( r_ld_acl_enc_key_load = 0x40036404 ); 693 | PROVIDE ( r_ld_acl_flow_off = 0x40035400 ); 694 | PROVIDE ( r_ld_acl_flow_on = 0x4003541c ); 695 | PROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c ); 696 | PROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 ); 697 | PROVIDE ( r_ld_acl_init = 0x40034d08 ); 698 | PROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 ); 699 | PROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 ); 700 | PROVIDE ( r_ld_acl_lsto_get = 0x400366b4 ); 701 | PROVIDE ( r_ld_acl_lsto_set = 0x400366f8 ); 702 | PROVIDE ( r_ld_acl_reset = 0x40034d24 ); 703 | PROVIDE ( r_ld_acl_role_get = 0x40036b30 ); 704 | PROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 ); 705 | PROVIDE ( r_ld_acl_rsw_req = 0x40035e74 ); 706 | PROVIDE ( r_ld_acl_rx_enc = 0x40036344 ); 707 | PROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 ); 708 | PROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 ); 709 | PROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c ); 710 | PROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 ); 711 | PROVIDE ( r_ld_acl_sniff = 0x4003617c ); 712 | PROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 ); 713 | PROVIDE ( r_ld_acl_ssr_set = 0x40036274 ); 714 | PROVIDE ( r_ld_acl_start = 0x40034ddc ); 715 | PROVIDE ( r_ld_acl_stop = 0x4003532c ); 716 | PROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 ); 717 | PROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c ); 718 | PROVIDE ( r_ld_acl_t_poll_get = 0x40036024 ); 719 | PROVIDE ( r_ld_acl_t_poll_set = 0x40036068 ); 720 | PROVIDE ( r_ld_acl_tx_enc = 0x400362f8 ); 721 | PROVIDE ( ld_acl_frm_cbk = 0x40034414 ); 722 | PROVIDE ( ld_acl_rsw_end = 0x40032bc0 ); 723 | PROVIDE ( ld_acl_end = 0x40033140 ); 724 | PROVIDE ( ld_acl_resched = 0x40033814 ); 725 | PROVIDE ( ld_acl_test_mode_update = 0x40032050 ); 726 | PROVIDE ( r_ld_acl_unsniff = 0x400361e0 ); 727 | PROVIDE ( r_ld_active_check = 0x4003cac4 ); 728 | PROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec ); 729 | PROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c ); 730 | PROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 ); 731 | PROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc ); 732 | PROVIDE ( r_ld_bcst_acl_start = 0x4003882c ); 733 | PROVIDE ( r_ld_bcst_afh_update = 0x40038f3c ); 734 | PROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c ); 735 | PROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 ); 736 | PROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 ); 737 | PROVIDE ( r_ld_bd_addr_get = 0x4003ca20 ); 738 | PROVIDE ( r_ld_channel_assess = 0x4003c184 ); 739 | PROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 ); 740 | PROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 ); 741 | PROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 ); 742 | PROVIDE ( r_ld_csb_rx_init = 0x40039690 ); 743 | PROVIDE ( r_ld_csb_rx_reset = 0x4003969c ); 744 | PROVIDE ( r_ld_csb_rx_start = 0x4003972c ); 745 | PROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 ); 746 | PROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc ); 747 | PROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c ); 748 | PROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 ); 749 | PROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 ); 750 | PROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 ); 751 | PROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 ); 752 | PROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 ); 753 | PROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 ); 754 | PROVIDE ( r_ld_fm_frame_isr = 0x4003a82c ); 755 | PROVIDE ( r_ld_fm_init = 0x4003a760 ); 756 | PROVIDE ( r_ld_fm_prog_check = 0x4003ab28 ); 757 | PROVIDE ( r_ld_fm_prog_disable = 0x4003a984 ); 758 | PROVIDE ( r_ld_fm_prog_enable = 0x4003a944 ); 759 | PROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 ); 760 | PROVIDE ( r_ld_fm_reset = 0x4003a794 ); 761 | PROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 ); 762 | PROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 ); 763 | PROVIDE ( r_ld_init = 0x4003c294 ); 764 | PROVIDE ( r_ld_inq_init = 0x4003b15c ); 765 | PROVIDE ( r_ld_inq_reset = 0x4003b168 ); 766 | PROVIDE ( r_ld_inq_start = 0x4003b1f0 ); 767 | PROVIDE ( r_ld_inq_stop = 0x4003b4f0 ); 768 | PROVIDE ( r_ld_iscan_eir_get = 0x4003c118 ); 769 | PROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 ); 770 | PROVIDE ( r_ld_iscan_init = 0x4003b9f0 ); 771 | PROVIDE ( r_ld_iscan_reset = 0x4003ba14 ); 772 | PROVIDE ( r_ld_iscan_restart = 0x4003ba44 ); 773 | PROVIDE ( r_ld_iscan_start = 0x4003bb28 ); 774 | PROVIDE ( r_ld_iscan_stop = 0x4003bf1c ); 775 | PROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 ); 776 | PROVIDE ( r_ld_page_init = 0x4003d808 ); 777 | PROVIDE ( r_ld_page_reset = 0x4003d814 ); 778 | PROVIDE ( r_ld_page_start = 0x4003d848 ); 779 | PROVIDE ( r_ld_page_stop = 0x4003da54 ); 780 | PROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 ); 781 | PROVIDE ( r_ld_pca_init = 0x4003deb4 ); 782 | PROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac ); 783 | PROVIDE ( r_ld_pca_local_config = 0x4003df6c ); 784 | PROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 ); 785 | PROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 ); 786 | PROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 ); 787 | PROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 ); 788 | PROVIDE ( r_ld_pca_reset = 0x4003df0c ); 789 | PROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 ); 790 | PROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 ); 791 | PROVIDE ( r_ld_pscan_init = 0x4003f474 ); 792 | PROVIDE ( r_ld_pscan_reset = 0x4003f498 ); 793 | PROVIDE ( r_ld_pscan_restart = 0x4003f4b8 ); 794 | PROVIDE ( r_ld_pscan_start = 0x4003f514 ); 795 | PROVIDE ( r_ld_pscan_stop = 0x4003f618 ); 796 | PROVIDE ( r_ld_read_clock = 0x4003c9e4 ); 797 | PROVIDE ( r_ld_reset = 0x4003c714 ); 798 | PROVIDE ( r_ld_sched_acl_add = 0x4003f978 ); 799 | PROVIDE ( r_ld_sched_acl_remove = 0x4003f99c ); 800 | PROVIDE ( r_ld_sched_compute = 0x4003f6f8 ); 801 | PROVIDE ( r_ld_sched_init = 0x4003f7ac ); 802 | PROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 ); 803 | PROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 ); 804 | PROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 ); 805 | PROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 ); 806 | PROVIDE ( r_ld_sched_page_add = 0x4003f910 ); 807 | PROVIDE ( r_ld_sched_page_remove = 0x4003f938 ); 808 | PROVIDE ( r_ld_sched_pscan_add = 0x4003f828 ); 809 | PROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 ); 810 | PROVIDE ( r_ld_sched_reset = 0x4003f7d4 ); 811 | PROVIDE ( r_ld_sched_sco_add = 0x4003fa4c ); 812 | PROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c ); 813 | PROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 ); 814 | PROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c ); 815 | PROVIDE ( r_ld_sched_sscan_add = 0x4003f868 ); 816 | PROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 ); 817 | PROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 ); 818 | PROVIDE ( r_ld_sco_data_tx = 0x40037ee8 ); 819 | PROVIDE ( r_ld_sco_start = 0x40037110 ); 820 | PROVIDE ( r_ld_sco_stop = 0x40037c40 ); 821 | PROVIDE ( r_ld_sco_update = 0x40037a74 ); 822 | PROVIDE ( r_ld_sscan_activated = 0x4004031c ); 823 | PROVIDE ( r_ld_sscan_init = 0x400402f0 ); 824 | PROVIDE ( r_ld_sscan_reset = 0x400402fc ); 825 | PROVIDE ( r_ld_sscan_start = 0x40040384 ); 826 | PROVIDE ( r_ld_strain_init = 0x400409f4 ); 827 | PROVIDE ( r_ld_strain_reset = 0x40040a00 ); 828 | PROVIDE ( r_ld_strain_start = 0x40040a8c ); 829 | PROVIDE ( r_ld_strain_stop = 0x40040df0 ); 830 | PROVIDE ( r_ld_timing_accuracy_get = 0x4003caac ); 831 | PROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c ); 832 | PROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 ); 833 | PROVIDE ( r_ld_util_bch_create = 0x40040fcc ); 834 | PROVIDE ( r_ld_util_fhs_pk = 0x400411c8 ); 835 | PROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 ); 836 | PROVIDE ( r_ld_util_stp_pk = 0x400413f4 ); 837 | PROVIDE ( r_ld_util_stp_unpk = 0x40041324 ); 838 | PROVIDE ( r_ld_version_get = 0x4003ca6c ); 839 | PROVIDE ( r_ld_wlcoex_set = 0x4003caf8 ); 840 | PROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 ); 841 | PROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c ); 842 | PROVIDE ( r_llc_ch_assess_local = 0x40041494 ); 843 | PROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 ); 844 | PROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 ); 845 | PROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac ); 846 | PROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 ); 847 | PROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c ); 848 | PROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 ); 849 | PROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c ); 850 | PROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 ); 851 | PROVIDE ( r_llc_con_update_complete_send = 0x40044d68 ); 852 | PROVIDE ( r_llc_con_update_finished = 0x4004518c ); 853 | PROVIDE ( r_llc_con_update_ind = 0x40045038 ); 854 | PROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 ); 855 | PROVIDE ( r_llc_end_evt_defer = 0x40046330 ); 856 | PROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c ); 857 | PROVIDE ( r_llc_init = 0x40044778 ); 858 | PROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 ); 859 | PROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 ); 860 | PROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc ); 861 | PROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 ); 862 | PROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 ); 863 | PROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 ); 864 | PROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 ); 865 | PROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 ); 866 | PROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 ); 867 | PROVIDE ( r_llc_llcp_get_autorize = 0x4004475c ); 868 | PROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 ); 869 | PROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac ); 870 | PROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 ); 871 | PROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 ); 872 | PROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c ); 873 | PROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 ); 874 | PROVIDE ( r_llc_llcp_recv_handler = 0x40044678 ); 875 | PROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c ); 876 | PROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c ); 877 | PROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 ); 878 | PROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 ); 879 | PROVIDE ( r_llc_llcp_tester_send = 0x400445e4 ); 880 | PROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 ); 881 | PROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c ); 882 | PROVIDE ( r_llc_lsto_con_update = 0x40045098 ); 883 | PROVIDE ( r_llc_ltk_req_send = 0x40044dc0 ); 884 | PROVIDE ( r_llc_map_update_finished = 0x40045260 ); 885 | PROVIDE ( r_llc_map_update_ind = 0x400450f0 ); 886 | PROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc ); 887 | PROVIDE ( r_llc_pdu_defer = 0x40046528 ); 888 | PROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac ); 889 | PROVIDE ( r_llc_reset = 0x400447b8 ); 890 | PROVIDE ( r_llc_start = 0x400447f4 ); 891 | PROVIDE ( r_llc_stop = 0x400449ac ); 892 | PROVIDE ( r_llc_util_bw_mgt = 0x4004629c ); 893 | PROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 ); 894 | PROVIDE ( r_llc_util_dicon_procedure = 0x40046130 ); 895 | PROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 ); 896 | PROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 ); 897 | PROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 ); 898 | PROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 ); 899 | PROVIDE ( r_llc_util_update_channel_map = 0x400461ac ); 900 | PROVIDE ( r_llc_version_rd_event_send = 0x40044e60 ); 901 | PROVIDE ( r_lld_adv_start = 0x40048b38 ); 902 | PROVIDE ( r_lld_adv_stop = 0x40048ea0 ); 903 | PROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 ); 904 | PROVIDE ( r_lld_con_param_req = 0x40049f0c ); 905 | PROVIDE ( r_lld_con_param_rsp = 0x40049e00 ); 906 | PROVIDE ( r_lld_con_start = 0x400491f8 ); 907 | PROVIDE ( r_lld_con_stop = 0x40049fdc ); 908 | PROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc ); 909 | PROVIDE ( r_lld_con_update_ind = 0x4004a30c ); 910 | PROVIDE ( r_lld_con_update_req = 0x40049b60 ); 911 | PROVIDE ( r_lld_core_reset = 0x40048a9c ); 912 | PROVIDE ( r_lld_crypt_isr = 0x4004a324 ); 913 | PROVIDE ( r_lld_evt_adv_create = 0x400481f4 ); 914 | PROVIDE ( r_lld_evt_canceled = 0x400485c8 ); 915 | PROVIDE ( r_lld_evt_channel_next = 0x40046aac ); 916 | PROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc ); 917 | PROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 ); 918 | PROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c ); 919 | PROVIDE ( r_lld_evt_drift_compute = 0x40047670 ); 920 | PROVIDE ( r_lld_evt_elt_delete = 0x40047538 ); 921 | PROVIDE ( r_lld_evt_elt_insert = 0x400474c8 ); 922 | PROVIDE ( r_lld_evt_end = 0x400483e8 ); 923 | PROVIDE ( r_lld_evt_end_isr = 0x4004862c ); 924 | PROVIDE ( r_lld_evt_init = 0x40046b3c ); 925 | PROVIDE ( r_lld_evt_init_evt = 0x40046cd0 ); 926 | PROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 ); 927 | PROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 ); 928 | PROVIDE ( r_lld_evt_prevent_stop = 0x40047adc ); 929 | PROVIDE ( r_lld_evt_restart = 0x40046d50 ); 930 | PROVIDE ( r_lld_evt_rx = 0x40048578 ); 931 | PROVIDE ( r_lld_evt_rx_isr = 0x40048678 ); 932 | PROVIDE ( r_lld_evt_scan_create = 0x40047ae8 ); 933 | PROVIDE ( r_lld_evt_schedule = 0x40047908 ); 934 | PROVIDE ( r_lld_evt_schedule_next = 0x400477dc ); 935 | PROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 ); 936 | PROVIDE ( r_lld_evt_slave_update = 0x40048138 ); 937 | PROVIDE ( r_lld_evt_update_create = 0x40047cd8 ); 938 | PROVIDE ( r_lld_get_mode = 0x40049ff8 ); 939 | PROVIDE ( r_lld_init = 0x4004873c ); 940 | PROVIDE ( r_lld_move_to_master = 0x400499e0 ); 941 | PROVIDE ( r_lld_move_to_slave = 0x4004a024 ); 942 | PROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 ); 943 | PROVIDE ( r_lld_pdu_check = 0x4004ac34 ); 944 | PROVIDE ( r_lld_pdu_data_send = 0x4004b018 ); 945 | PROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc ); 946 | PROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 ); 947 | PROVIDE ( r_lld_pdu_send_packet = 0x4004b774 ); 948 | PROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 ); 949 | PROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 ); 950 | PROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 ); 951 | PROVIDE ( r_lld_pdu_tx_push = 0x4004b080 ); 952 | PROVIDE ( r_lld_ral_renew_req = 0x4004a73c ); 953 | PROVIDE ( r_lld_scan_start = 0x40048ee0 ); 954 | PROVIDE ( r_lld_scan_stop = 0x40049190 ); 955 | PROVIDE ( r_lld_test_mode_rx = 0x4004a540 ); 956 | PROVIDE ( r_lld_test_mode_tx = 0x4004a350 ); 957 | PROVIDE ( r_lld_test_stop = 0x4004a710 ); 958 | PROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc ); 959 | PROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c ); 960 | PROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 ); 961 | PROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 ); 962 | PROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 ); 963 | PROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 ); 964 | PROVIDE ( r_lld_util_flush_list = 0x4004bbd8 ); 965 | PROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 ); 966 | PROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac ); 967 | PROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 ); 968 | PROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 ); 969 | PROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 ); 970 | PROVIDE ( r_lld_util_instant_get = 0x4004b890 ); 971 | PROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc ); 972 | PROVIDE ( r_lld_util_priority_set = 0x4004bd10 ); 973 | PROVIDE ( r_lld_util_priority_update = 0x4004bd78 ); 974 | PROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 ); 975 | PROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 ); 976 | PROVIDE ( r_lld_wlcoex_set = 0x4004bd98 ); 977 | PROVIDE ( r_llm_ble_ready = 0x4004cc34 ); 978 | PROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 ); 979 | PROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 ); 980 | PROVIDE ( r_llm_con_req_ind = 0x4004cc54 ); 981 | PROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 ); 982 | PROVIDE ( r_llm_create_con = 0x4004de78 ); 983 | PROVIDE ( r_llm_encryption_done = 0x4004dff8 ); 984 | PROVIDE ( r_llm_encryption_start = 0x4004e128 ); 985 | PROVIDE ( r_llm_end_evt_defer = 0x4004eb6c ); 986 | PROVIDE ( r_llm_init = 0x4004c9f8 ); 987 | PROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 ); 988 | PROVIDE ( r_llm_pdu_defer = 0x4004ec48 ); 989 | PROVIDE ( r_llm_ral_clear = 0x4004e1fc ); 990 | PROVIDE ( r_llm_ral_dev_add = 0x4004e23c ); 991 | PROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc ); 992 | PROVIDE ( r_llm_ral_get_rpa = 0x4004e400 ); 993 | PROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 ); 994 | PROVIDE ( r_llm_ral_update = 0x4004e4f8 ); 995 | PROVIDE ( r_llm_set_adv_data = 0x4004d960 ); 996 | PROVIDE ( r_llm_set_adv_en = 0x4004d7ec ); 997 | PROVIDE ( r_llm_set_adv_param = 0x4004d5f4 ); 998 | PROVIDE ( r_llm_set_scan_en = 0x4004db64 ); 999 | PROVIDE ( r_llm_set_scan_param = 0x4004dac8 ); 1000 | PROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 ); 1001 | PROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 ); 1002 | PROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc ); 1003 | PROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc ); 1004 | PROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 ); 1005 | PROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 ); 1006 | PROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 ); 1007 | PROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 ); 1008 | PROVIDE ( r_llm_util_bl_add = 0x4004e9ac ); 1009 | PROVIDE ( r_llm_util_bl_check = 0x4004e930 ); 1010 | PROVIDE ( r_llm_util_bl_rem = 0x4004ea70 ); 1011 | PROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 ); 1012 | PROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 ); 1013 | PROVIDE ( r_llm_util_check_map_validity = 0x4004e800 ); 1014 | PROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 ); 1015 | PROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 ); 1016 | PROVIDE ( r_llm_util_set_public_addr = 0x4004e89c ); 1017 | PROVIDE ( r_llm_wl_clr = 0x4004dc54 ); 1018 | PROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 ); 1019 | PROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 ); 1020 | PROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc ); 1021 | PROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 ); 1022 | PROVIDE ( r_lm_acl_disc = 0x4004f148 ); 1023 | PROVIDE ( r_LM_AddSniff = 0x40022d20 ); 1024 | PROVIDE ( r_lm_add_sync = 0x40051358 ); 1025 | PROVIDE ( r_lm_afh_activate_timer = 0x4004f444 ); 1026 | PROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 ); 1027 | PROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 ); 1028 | PROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c ); 1029 | PROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 ); 1030 | PROVIDE ( r_lm_check_active_sync = 0x40051334 ); 1031 | PROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c ); 1032 | PROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 ); 1033 | PROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c ); 1034 | PROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 ); 1035 | PROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 ); 1036 | PROVIDE ( r_LM_ComputePacketType = 0x4002f554 ); 1037 | PROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac ); 1038 | PROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 ); 1039 | PROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 ); 1040 | PROVIDE ( r_lm_dhkey_calc_init = 0x40013234 ); 1041 | PROVIDE ( r_lm_dhkey_compare = 0x400132d8 ); 1042 | PROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec ); 1043 | PROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 ); 1044 | PROVIDE ( r_lm_f1 = 0x40012bb8 ); 1045 | PROVIDE ( r_lm_f2 = 0x40012cfc ); 1046 | PROVIDE ( r_lm_f3 = 0x40013050 ); 1047 | PROVIDE ( r_lm_g = 0x40012f90 ); 1048 | PROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c ); 1049 | PROVIDE ( r_lm_get_auth_en = 0x4004f1ac ); 1050 | PROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c ); 1051 | PROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 ); 1052 | PROVIDE ( r_LM_GetFeature = 0x4002f924 ); 1053 | PROVIDE ( r_LM_GetLinkTimeout = 0x400233ec ); 1054 | PROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 ); 1055 | PROVIDE ( r_lm_get_loopback_mode = 0x4004f248 ); 1056 | PROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c ); 1057 | PROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 ); 1058 | PROVIDE ( r_LM_GetMasterKey = 0x4001b260 ); 1059 | PROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 ); 1060 | PROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 ); 1061 | PROVIDE ( r_lm_get_nb_acl = 0x4004ef9c ); 1062 | PROVIDE ( r_lm_get_nb_sync_link = 0x4005179c ); 1063 | PROVIDE ( r_lm_get_nonce = 0x400131c4 ); 1064 | PROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 ); 1065 | PROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 ); 1066 | PROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 ); 1067 | PROVIDE ( r_LM_GetPINType = 0x4004f1e8 ); 1068 | PROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 ); 1069 | PROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 ); 1070 | PROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 ); 1071 | PROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 ); 1072 | PROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 ); 1073 | PROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 ); 1074 | PROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c ); 1075 | PROVIDE ( r_lm_get_sp_en = 0x4004f1c0 ); 1076 | PROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 ); 1077 | PROVIDE ( r_lm_get_synchdl = 0x4005175c ); 1078 | PROVIDE ( r_lm_get_sync_param = 0x400503b4 ); 1079 | PROVIDE ( r_lm_init = 0x4004ed34 ); 1080 | PROVIDE ( r_lm_init_sync = 0x400512d8 ); 1081 | PROVIDE ( r_lm_is_acl_con = 0x4004f47c ); 1082 | PROVIDE ( r_lm_is_acl_con_role = 0x4004f49c ); 1083 | PROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 ); 1084 | PROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 ); 1085 | PROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 ); 1086 | PROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 ); 1087 | PROVIDE ( r_lm_look_for_sync = 0x40051774 ); 1088 | PROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c ); 1089 | PROVIDE ( r_lm_lt_addr_free = 0x4004ef74 ); 1090 | PROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 ); 1091 | PROVIDE ( r_LM_MakeCof = 0x4002f84c ); 1092 | PROVIDE ( r_LM_MakeRandVec = 0x400112d8 ); 1093 | PROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 ); 1094 | PROVIDE ( r_LM_MaxSlot = 0x4002f694 ); 1095 | PROVIDE ( r_lm_modif_sync = 0x40051578 ); 1096 | PROVIDE ( r_lm_n_is_zero = 0x40012170 ); 1097 | PROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 ); 1098 | PROVIDE ( r_lm_oob_f1 = 0x40012e54 ); 1099 | PROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 ); 1100 | PROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 ); 1101 | PROVIDE ( nvds_null_read = 0x400542a0 ); 1102 | PROVIDE ( nvds_null_write = 0x400542a8 ); 1103 | PROVIDE ( nvds_null_erase = 0x400542b0 ); 1104 | PROVIDE ( nvds_read = 0x400542c4 ); 1105 | PROVIDE ( nvds_write = 0x400542fc ); 1106 | PROVIDE ( nvds_erase = 0x40054334 ); 1107 | PROVIDE ( nvds_init_memory = 0x40054358 ); 1108 | PROVIDE ( r_lmp_pack = 0x4001135c ); 1109 | PROVIDE ( r_lmp_unpack = 0x4001149c ); 1110 | PROVIDE ( r_lm_read_features = 0x4004f0d8 ); 1111 | PROVIDE ( r_LM_RemoveSniff = 0x40023124 ); 1112 | PROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 ); 1113 | PROVIDE ( r_lm_remove_sync = 0x400517c8 ); 1114 | PROVIDE ( r_lm_reset_sync = 0x40051304 ); 1115 | PROVIDE ( r_lm_role_switch_finished = 0x4004f028 ); 1116 | PROVIDE ( r_lm_role_switch_start = 0x4004efe0 ); 1117 | PROVIDE ( r_lm_sco_nego_end = 0x40051828 ); 1118 | PROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 ); 1119 | PROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 ); 1120 | PROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc ); 1121 | PROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 ); 1122 | PROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 ); 1123 | PROVIDE ( r_lm_sp_n_one = 0x400123a4 ); 1124 | PROVIDE ( r_lm_sp_p192_add = 0x40012828 ); 1125 | PROVIDE ( r_lm_sp_p192_dbl = 0x4001268c ); 1126 | PROVIDE ( r_lm_sp_p192_invert = 0x40012b6c ); 1127 | PROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 ); 1128 | PROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 ); 1129 | PROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 ); 1130 | PROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 ); 1131 | PROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 ); 1132 | PROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 ); 1133 | PROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 ); 1134 | PROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 ); 1135 | PROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 ); 1136 | PROVIDE ( r_modules_funcs = 0x3ffafd6c ); 1137 | PROVIDE ( r_modules_funcs_p = 0x3ffafd68 ); 1138 | PROVIDE ( r_nvds_del = 0x400544c4 ); 1139 | PROVIDE ( r_nvds_get = 0x40054488 ); 1140 | PROVIDE ( r_nvds_init = 0x40054410 ); 1141 | PROVIDE ( r_nvds_lock = 0x400544fc ); 1142 | PROVIDE ( r_nvds_put = 0x40054534 ); 1143 | PROVIDE ( rom_abs_temp = 0x400054f0 ); 1144 | PROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c ); 1145 | PROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac ); 1146 | PROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 ); 1147 | PROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 ); 1148 | PROVIDE ( rom_bb_wdg_test_en = 0x40003b70 ); 1149 | PROVIDE ( rom_cbw2040_cfg = 0x400040b0 ); 1150 | PROVIDE ( rom_check_noise_floor = 0x40003c78 ); 1151 | PROVIDE ( rom_chip_i2c_readReg = 0x40004110 ); 1152 | PROVIDE ( rom_chip_i2c_writeReg = 0x40004168 ); 1153 | PROVIDE ( rom_chip_v7_bt_init = 0x40004d8c ); 1154 | PROVIDE ( rom_chip_v7_rx_init = 0x40004cec ); 1155 | PROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 ); 1156 | PROVIDE ( rom_chip_v7_tx_init = 0x40004d18 ); 1157 | PROVIDE ( rom_clk_force_on_vit = 0x40003710 ); 1158 | PROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 ); 1159 | PROVIDE ( rom_dc_iq_est = 0x400055c8 ); 1160 | PROVIDE ( rom_disable_agc = 0x40002fa4 ); 1161 | PROVIDE ( rom_enable_agc = 0x40002fcc ); 1162 | PROVIDE ( rom_en_pwdet = 0x4000506c ); 1163 | PROVIDE ( rom_gen_rx_gain_table = 0x40003e3c ); 1164 | PROVIDE ( rom_get_data_sat = 0x4000312c ); 1165 | PROVIDE ( rom_get_fm_sar_dout = 0x40005204 ); 1166 | PROVIDE ( rom_get_power_db = 0x40005fc8 ); 1167 | PROVIDE ( rom_get_pwctrl_correct = 0x400065d4 ); 1168 | PROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc ); 1169 | PROVIDE ( rom_get_rf_gain_qdb = 0x40006290 ); 1170 | PROVIDE ( rom_get_sar_dout = 0x40006564 ); 1171 | PROVIDE ( rom_i2c_readReg = 0x40004148 ); 1172 | PROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 ); 1173 | PROVIDE ( rom_i2c_writeReg = 0x400041a4 ); 1174 | PROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc ); 1175 | PROVIDE ( rom_index_to_txbbgain = 0x40004df8 ); 1176 | PROVIDE ( rom_iq_est_disable = 0x40005590 ); 1177 | PROVIDE ( rom_iq_est_enable = 0x40005514 ); 1178 | PROVIDE ( rom_linear_to_db = 0x40005f64 ); 1179 | PROVIDE ( rom_loopback_mode_en = 0x400030f8 ); 1180 | PROVIDE ( rom_meas_tone_pwr_db = 0x40006004 ); 1181 | PROVIDE ( rom_mhz2ieee = 0x4000404c ); 1182 | PROVIDE ( rom_noise_floor_auto_set = 0x40003bdc ); 1183 | PROVIDE ( rom_pbus_debugmode = 0x40004458 ); 1184 | PROVIDE ( rom_pbus_force_mode = 0x40004270 ); 1185 | PROVIDE ( rom_pbus_force_test = 0x400043c0 ); 1186 | PROVIDE ( rom_pbus_rd = 0x40004414 ); 1187 | PROVIDE ( rom_pbus_rd_addr = 0x40004334 ); 1188 | PROVIDE ( rom_pbus_rd_shift = 0x40004374 ); 1189 | PROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 ); 1190 | PROVIDE ( rom_pbus_set_dco = 0x40004638 ); 1191 | PROVIDE ( rom_pbus_set_rxgain = 0x40004480 ); 1192 | PROVIDE ( rom_pbus_workmode = 0x4000446c ); 1193 | PROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 ); 1194 | PROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c ); 1195 | PROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 ); 1196 | PROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 ); 1197 | PROVIDE ( rom_phy_disable_agc = 0x40002f6c ); 1198 | PROVIDE ( rom_phy_disable_cca = 0x40003000 ); 1199 | PROVIDE ( rom_phy_enable_agc = 0x40002f88 ); 1200 | PROVIDE ( rom_phy_enable_cca = 0x4000302c ); 1201 | PROVIDE ( rom_phy_freq_correct = 0x40004b44 ); 1202 | PROVIDE ( rom_phyFuns = 0x3ffae0c0 ); 1203 | PROVIDE ( rom_phy_get_noisefloor = 0x40003c2c ); 1204 | PROVIDE ( rom_phy_get_vdd33 = 0x4000642c ); 1205 | PROVIDE ( rom_pow_usr = 0x40003044 ); 1206 | PROVIDE ( rom_read_sar_dout = 0x400051c0 ); 1207 | PROVIDE ( rom_restart_cal = 0x400046e0 ); 1208 | PROVIDE ( rom_rfcal_pwrctrl = 0x40006058 ); 1209 | PROVIDE ( rom_rfcal_rxiq = 0x40005b4c ); 1210 | PROVIDE ( rom_rfcal_txcap = 0x40005dec ); 1211 | PROVIDE ( rom_rfpll_reset = 0x40004680 ); 1212 | PROVIDE ( rom_rfpll_set_freq = 0x400047f8 ); 1213 | PROVIDE ( rom_rtc_mem_backup = 0x40003db4 ); 1214 | PROVIDE ( rom_rtc_mem_recovery = 0x40003df4 ); 1215 | PROVIDE ( rom_rx_gain_force = 0x4000351c ); 1216 | PROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 ); 1217 | PROVIDE ( rom_rxiq_get_mis = 0x400058e4 ); 1218 | PROVIDE ( rom_rxiq_set_reg = 0x40005a00 ); 1219 | PROVIDE ( rom_set_cal_rxdc = 0x400030b8 ); 1220 | PROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 ); 1221 | PROVIDE ( rom_set_channel_freq = 0x40004880 ); 1222 | PROVIDE ( rom_set_loopback_gain = 0x40003060 ); 1223 | PROVIDE ( rom_set_noise_floor = 0x40003d48 ); 1224 | PROVIDE ( rom_set_pbus_mem = 0x400031a4 ); 1225 | PROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 ); 1226 | PROVIDE ( rom_set_rxclk_en = 0x40003594 ); 1227 | PROVIDE ( rom_set_txcap_reg = 0x40005d50 ); 1228 | PROVIDE ( rom_set_txclk_en = 0x40003564 ); 1229 | PROVIDE ( rom_spur_coef_cfg = 0x40003ac8 ); 1230 | PROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 ); 1231 | PROVIDE ( rom_start_tx_tone = 0x400036b4 ); 1232 | PROVIDE ( rom_start_tx_tone_step = 0x400035d0 ); 1233 | PROVIDE ( rom_stop_tx_tone = 0x40003f98 ); 1234 | PROVIDE ( _rom_store = 0x4000d66c ); 1235 | PROVIDE ( _rom_store_table = 0x4000d4f8 ); 1236 | PROVIDE ( rom_target_power_add_backoff = 0x40006268 ); 1237 | PROVIDE ( rom_tx_atten_set_interp = 0x400061cc ); 1238 | PROVIDE ( rom_txbbgain_to_index = 0x40004dc0 ); 1239 | PROVIDE ( rom_txcal_work_mode = 0x4000510c ); 1240 | PROVIDE ( rom_txdc_cal_init = 0x40004e10 ); 1241 | PROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 ); 1242 | PROVIDE ( rom_txiq_cover = 0x4000538c ); 1243 | PROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc ); 1244 | PROVIDE ( rom_txiq_set_reg = 0x40005154 ); 1245 | PROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c ); 1246 | PROVIDE ( rom_txtone_linear_pwr = 0x40005290 ); 1247 | PROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 ); 1248 | PROVIDE ( rom_write_gain_mem = 0x4000348c ); 1249 | PROVIDE ( rom_write_rfpll_sdm = 0x40004740 ); 1250 | PROVIDE ( roundup2 = 0x4000ab7c ); 1251 | PROVIDE ( r_plf_funcs_p = 0x3ffb8360 ); 1252 | PROVIDE ( r_rf_rw_bt_init = 0x40054868 ); 1253 | PROVIDE ( r_rf_rw_init = 0x40054b0c ); 1254 | PROVIDE ( r_rf_rw_le_init = 0x400549d0 ); 1255 | PROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c ); 1256 | PROVIDE ( r_rwble_init = 0x40054bf4 ); 1257 | PROVIDE ( r_rwble_isr = 0x40054e08 ); 1258 | PROVIDE ( r_rwble_reset = 0x40054ce8 ); 1259 | PROVIDE ( r_rwble_sleep_check = 0x40054d78 ); 1260 | PROVIDE ( r_rwble_version = 0x40054dac ); 1261 | PROVIDE ( r_rwbt_init = 0x40055160 ); 1262 | PROVIDE ( r_rwbt_isr = 0x40055248 ); 1263 | PROVIDE ( r_rwbt_reset = 0x400551bc ); 1264 | PROVIDE ( r_rwbt_sleep_check = 0x4005577c ); 1265 | PROVIDE ( r_rwbt_sleep_enter = 0x400557a4 ); 1266 | PROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc ); 1267 | PROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc ); 1268 | PROVIDE ( r_rwbt_version = 0x4005520c ); 1269 | PROVIDE ( r_rwip_assert_err = 0x40055f88 ); 1270 | PROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc ); 1271 | PROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c ); 1272 | PROVIDE ( r_rwip_init = 0x4005595c ); 1273 | PROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 ); 1274 | PROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 ); 1275 | PROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 ); 1276 | PROVIDE ( r_rwip_reset = 0x40055ab8 ); 1277 | PROVIDE ( r_rwip_schedule = 0x40055b38 ); 1278 | PROVIDE ( r_rwip_sleep = 0x40055b5c ); 1279 | PROVIDE ( r_rwip_sleep_enable = 0x40055f30 ); 1280 | PROVIDE ( r_rwip_version = 0x40055b20 ); 1281 | PROVIDE ( r_rwip_wakeup = 0x40055dc4 ); 1282 | PROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c ); 1283 | PROVIDE ( r_rwip_wakeup_end = 0x40055e18 ); 1284 | PROVIDE ( r_rwip_wlcoex_set = 0x40055f60 ); 1285 | PROVIDE ( r_SHA_256 = 0x40013a90 ); 1286 | PROVIDE ( rwip_coex_cfg = 0x3ff9914c ); 1287 | PROVIDE ( rwip_priority = 0x3ff99159 ); 1288 | PROVIDE ( rwip_rf = 0x3ffbdb28 ); 1289 | PROVIDE ( rwip_rf_p_get = 0x400558f4 ); 1290 | PROVIDE ( r_XorKey = 0x400112c0 ); 1291 | PROVIDE ( sha_blk_bits = 0x3ff99290 ); 1292 | PROVIDE ( sha_blk_bits_bytes = 0x3ff99288 ); 1293 | PROVIDE ( sha_blk_hash_bytes = 0x3ff9928c ); 1294 | PROVIDE ( sig_matrix = 0x3ffae293 ); 1295 | PROVIDE ( sip_after_tx_complete = 0x4000b358 ); 1296 | PROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c ); 1297 | PROVIDE ( sip_get_ptr = 0x4000b34c ); 1298 | PROVIDE ( sip_get_state = 0x4000ae2c ); 1299 | PROVIDE ( sip_init_attach = 0x4000ae58 ); 1300 | PROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 ); 1301 | PROVIDE ( sip_install_rx_data_cb = 0x4000ae20 ); 1302 | PROVIDE ( sip_is_active = 0x4000b3c0 ); 1303 | PROVIDE ( sip_post_init = 0x4000aed8 ); 1304 | PROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc ); 1305 | PROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c ); 1306 | PROVIDE ( sip_send = 0x4000af54 ); 1307 | PROVIDE ( sip_to_host_chain_append = 0x4000aef8 ); 1308 | PROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 ); 1309 | PROVIDE ( slc_add_credits = 0x4000baf4 ); 1310 | PROVIDE ( slc_enable = 0x4000b64c ); 1311 | PROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 ); 1312 | PROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 ); 1313 | PROVIDE ( slc_has_pkt_to_host = 0x4000b5fc ); 1314 | PROVIDE ( slc_init_attach = 0x4000b918 ); 1315 | PROVIDE ( slc_init_credit = 0x4000badc ); 1316 | PROVIDE ( slc_reattach = 0x4000b62c ); 1317 | PROVIDE ( slc_send_to_host_chain = 0x4000b6a0 ); 1318 | PROVIDE ( slc_set_host_io_max_window = 0x4000b89c ); 1319 | PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 ); 1320 | PROVIDE ( specialModP256 = 0x4001600c ); 1321 | PROVIDE ( __stack = 0x3ffe3f20 ); 1322 | PROVIDE ( __stack_app = 0x3ffe7e30 ); 1323 | PROVIDE ( _stack_sentry = 0x3ffe1320 ); 1324 | PROVIDE ( _stack_sentry_app = 0x3ffe5230 ); 1325 | PROVIDE ( _start = 0x40000704 ); 1326 | PROVIDE ( start_tb_console = 0x4005a980 ); 1327 | PROVIDE ( _stat_r = 0x4000bcb4 ); 1328 | PROVIDE ( _stext = 0x40000560 ); 1329 | PROVIDE ( SubtractBigHex256 = 0x40015bcc ); 1330 | PROVIDE ( SubtractBigHexMod256 = 0x40015e8c ); 1331 | PROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c ); 1332 | PROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 ); 1333 | PROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 ); 1334 | PROVIDE ( sw_to_hw = 0x3ffb8d40 ); 1335 | PROVIDE ( syscall_table_ptr_app = 0x3ffae020 ); 1336 | PROVIDE ( syscall_table_ptr_pro = 0x3ffae024 ); 1337 | PROVIDE ( tdefl_compress = 0x400600bc ); 1338 | PROVIDE ( tdefl_compress_buffer = 0x400607f4 ); 1339 | PROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 ); 1340 | PROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 ); 1341 | PROVIDE ( tdefl_get_adler32 = 0x400608d8 ); 1342 | PROVIDE ( tdefl_get_prev_return_status = 0x400608d0 ); 1343 | PROVIDE ( tdefl_init = 0x40060810 ); 1344 | PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c ); 1345 | PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 ); 1346 | PROVIDE ( tinfl_decompress = 0x4005ef30 ); 1347 | PROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 ); 1348 | PROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 ); 1349 | PROVIDE ( UartDev = 0x3ffe019c ); 1350 | PROVIDE ( user_code_start = 0x3ffe0400 ); 1351 | PROVIDE ( veryBigHexP256 = 0x3ff9736c ); 1352 | PROVIDE ( xthal_bcopy = 0x4000c098 ); 1353 | PROVIDE ( xthal_copy123 = 0x4000c124 ); 1354 | PROVIDE ( xthal_get_ccompare = 0x4000c078 ); 1355 | PROVIDE ( xthal_get_ccount = 0x4000c050 ); 1356 | PROVIDE ( xthal_get_interrupt = 0x4000c1e4 ); 1357 | PROVIDE ( xthal_get_intread = 0x4000c1e4 ); 1358 | PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 ); 1359 | PROVIDE ( xthal_memcpy = 0x4000c0bc ); 1360 | PROVIDE ( xthal_set_ccompare = 0x4000c058 ); 1361 | PROVIDE ( xthal_set_intclear = 0x4000c1ec ); 1362 | PROVIDE ( _xtos_set_intlevel = 0x4000bfdc ); 1363 | PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 ); 1364 | PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 ); 1365 | PROVIDE ( esp_rom_spiflash_config_param = 0x40063238 ); 1366 | PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 ); 1367 | PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 ); 1368 | PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 ); 1369 | PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c ); 1370 | PROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc ); 1371 | PROVIDE ( esp_rom_spiflash_attach = 0x40062a6c ); 1372 | PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 ); 1373 | PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 ); 1374 | PROVIDE ( SPI_write_enable = 0x40062320 ); 1375 | PROVIDE ( hci_le_rd_rem_used_feats_cmd_handler = 0x400417b4 ); 1376 | PROVIDE ( llcp_length_req_handler = 0x40043808 ); 1377 | PROVIDE ( llcp_unknown_rsp_handler = 0x40043ba8 ); 1378 | PROVIDE ( llcp_channel_map_req_handler = 0x4004291c ); 1379 | PROVIDE ( llcp_con_up_req_handler = 0x400426f0 ); 1380 | /* 1381 | These functions are xtos-related (or call xtos-related functions) and do not play well 1382 | with multicore FreeRTOS. Where needed, we provide alternatives that are multicore 1383 | compatible. These functions also use a chunk of static RAM, by not using them we can 1384 | allocate that RAM for general use. 1385 | */ 1386 | /* 1387 | PROVIDE ( _DebugExceptionVector = 0x40000280 ); 1388 | PROVIDE ( _DoubleExceptionVector = 0x400003c0 ); 1389 | PROVIDE ( _KernelExceptionVector = 0x40000300 ); 1390 | PROVIDE ( _GeneralException = 0x40000e14 ); 1391 | PROVIDE ( _ResetHandler = 0x40000450 ); 1392 | PROVIDE ( _ResetVector = 0x40000400 ); 1393 | PROVIDE ( _UserExceptionVector = 0x40000340 ); 1394 | PROVIDE ( _NMIExceptionVector = 0x400002c0 ); 1395 | PROVIDE ( _WindowOverflow12 = 0x40000100 ); 1396 | PROVIDE ( _WindowOverflow4 = 0x40000000 ); 1397 | PROVIDE ( _WindowOverflow8 = 0x40000080 ); 1398 | PROVIDE ( _WindowUnderflow12 = 0x40000140 ); 1399 | PROVIDE ( _WindowUnderflow4 = 0x40000040 ); 1400 | PROVIDE ( _WindowUnderflow8 = 0x400000c0 ); 1401 | PROVIDE ( _Level2FromVector = 0x40000954 ); 1402 | PROVIDE ( _Level3FromVector = 0x40000a28 ); 1403 | PROVIDE ( _Level4FromVector = 0x40000af8 ); 1404 | PROVIDE ( _Level5FromVector = 0x40000c68 ); 1405 | PROVIDE ( _Level2Vector = 0x40000180 ); 1406 | PROVIDE ( _Level3Vector = 0x400001c0 ); 1407 | PROVIDE ( _Level4Vector = 0x40000200 ); 1408 | PROVIDE ( _Level5Vector = 0x40000240 ); 1409 | PROVIDE ( _LevelOneInterrupt = 0x40000835 ); 1410 | PROVIDE ( _SyscallException = 0x400007cf ); 1411 | PROVIDE ( _xtos_alloca_handler = 0x40000010 ); 1412 | PROVIDE ( _xtos_cause3_handler = 0x40000dd8 ); 1413 | PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 ); 1414 | PROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 ); 1415 | PROVIDE ( _xtos_enabled = 0x3ffe0650 ); 1416 | PROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 ); 1417 | PROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 ); 1418 | PROVIDE ( _xtos_interrupt_table = 0x3ffe0658 ); 1419 | PROVIDE ( _xtos_ints_off = 0x4000bfac ); 1420 | PROVIDE ( _xtos_ints_on = 0x4000bf88 ); 1421 | PROVIDE ( _xtos_intstruct = 0x3ffe0650 ); 1422 | PROVIDE ( _xtos_l1int_handler = 0x40000814 ); 1423 | PROVIDE ( _xtos_p_none = 0x4000bfd4 ); 1424 | PROVIDE ( _xtos_restore_intlevel = 0x40000928 ); 1425 | PROVIDE ( _xtos_return_from_exc = 0x4000c034 ); 1426 | PROVIDE ( _xtos_set_exception_handler = 0x4000074c ); 1427 | PROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 ); 1428 | PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 ); 1429 | PROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 ); 1430 | PROVIDE ( _xtos_set_vpri = 0x40000934 ); 1431 | PROVIDE ( _xtos_syscall_handler = 0x40000790 ); 1432 | PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); 1433 | PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); 1434 | PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); 1435 | PROVIDE ( ets_intr_count = 0x3ffe03fc ); 1436 | */ 1437 | 1438 | /* These functions are part of the UART downloader but also contain general UART functions. */ 1439 | PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 ); 1440 | PROVIDE ( FilePacketSendReqMsgProc = 0x40008860 ); 1441 | PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 ); 1442 | PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c ); 1443 | PROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 ); 1444 | PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 ); 1445 | PROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec ); 1446 | PROVIDE ( MemDwnLdStartMsgProc = 0x40008948 ); 1447 | PROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc ); 1448 | PROVIDE ( MemPacketSendReqMsgProc = 0x40008978 ); 1449 | PROVIDE ( uart_baudrate_detect = 0x40009034 ); 1450 | PROVIDE ( uart_buff_switch = 0x400093c0 ); 1451 | PROVIDE ( UartConnCheck = 0x40008738 ); 1452 | PROVIDE ( UartConnectProc = 0x40008a04 ); 1453 | PROVIDE ( UartDwnLdProc = 0x40008ce8 ); 1454 | PROVIDE ( UartRegReadProc = 0x40008a58 ); 1455 | PROVIDE ( UartRegWriteProc = 0x40008a14 ); 1456 | PROVIDE ( UartSetBaudProc = 0x40008aac ); 1457 | PROVIDE ( UartSpiAttachProc = 0x40008a6c ); 1458 | PROVIDE ( UartSpiReadProc = 0x40008a80 ); 1459 | PROVIDE ( VerifyFlashMd5Proc = 0x40008c44 ); 1460 | PROVIDE ( GetUartDevice = 0x40009598 ); 1461 | PROVIDE ( RcvMsg = 0x4000954c ); 1462 | PROVIDE ( SendMsg = 0x40009384 ); 1463 | PROVIDE ( UartGetCmdLn = 0x40009564 ); 1464 | PROVIDE ( UartRxString = 0x400092fc ); 1465 | PROVIDE ( Uart_Init = 0x40009120 ); 1466 | PROVIDE ( recv_packet = 0x40009424 ); 1467 | PROVIDE ( send_packet = 0x40009340 ); 1468 | PROVIDE ( uartAttach = 0x40008fd0 ); 1469 | PROVIDE ( uart_div_modify = 0x400090cc ); 1470 | PROVIDE ( uart_rx_intr_handler = 0x40008f4c ); 1471 | PROVIDE ( uart_rx_one_char = 0x400092d0 ); 1472 | PROVIDE ( uart_rx_one_char_block = 0x400092a4 ); 1473 | PROVIDE ( uart_rx_readbuff = 0x40009394 ); 1474 | PROVIDE ( uart_tx_flush = 0x40009258 ); 1475 | PROVIDE ( uart_tx_one_char = 0x40009200 ); 1476 | PROVIDE ( uart_tx_one_char2 = 0x4000922c ); 1477 | PROVIDE ( uart_tx_switch = 0x40009028 ); 1478 | 1479 | 1480 | /* 1481 | These functions are part of the ROM GPIO driver. We do not use them; the provided esp-idf functions 1482 | replace them and this way we can re-use the fixed RAM addresses these routines need. 1483 | */ 1484 | /* <-- So you don't read over it: This comment disables the next lines. 1485 | PROVIDE ( gpio_init = 0x40009c20 ); 1486 | PROVIDE ( gpio_intr_ack = 0x40009dd4 ); 1487 | PROVIDE ( gpio_intr_ack_high = 0x40009e1c ); 1488 | PROVIDE ( gpio_intr_handler_register = 0x40009e6c ); 1489 | PROVIDE ( gpio_intr_pending = 0x40009cec ); 1490 | PROVIDE ( gpio_intr_pending_high = 0x40009cf8 ); 1491 | PROVIDE ( gpio_pending_mask = 0x3ffe0038 ); 1492 | PROVIDE ( gpio_pending_mask_high = 0x3ffe0044 ); 1493 | PROVIDE ( gpio_pin_intr_state_set = 0x40009d04 ); 1494 | PROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 ); 1495 | PROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c ); 1496 | PROVIDE ( gpio_register_get = 0x40009cbc ); 1497 | PROVIDE ( gpio_register_set = 0x40009bbc ); 1498 | */ 1499 | /* These are still part of that driver, but have been verified not to use static RAM, so they can be used. */ 1500 | PROVIDE ( gpio_output_set = 0x40009b24 ); 1501 | PROVIDE ( gpio_output_set_high = 0x40009b5c ); 1502 | PROVIDE ( gpio_input_get = 0x40009b88 ); 1503 | PROVIDE ( gpio_input_get_high = 0x40009b9c ); 1504 | PROVIDE ( gpio_matrix_in = 0x40009edc ); 1505 | PROVIDE ( gpio_matrix_out = 0x40009f0c ); 1506 | PROVIDE ( gpio_pad_select_gpio = 0x40009fdc ); 1507 | PROVIDE ( gpio_pad_set_drv = 0x4000a11c ); 1508 | PROVIDE ( gpio_pad_pulldown = 0x4000a348 ); 1509 | PROVIDE ( gpio_pad_pullup = 0x4000a22c ); 1510 | PROVIDE ( gpio_pad_hold = 0x4000a734 ); 1511 | PROVIDE ( gpio_pad_unhold = 0x4000a484 ); 1512 | 1513 | /* 1514 | These functions are part of the non-os kernel (etsc). 1515 | */ 1516 | PROVIDE ( ets_aes_crypt = 0x4005c9b8 ); 1517 | PROVIDE ( ets_aes_disable = 0x4005c8f8 ); 1518 | PROVIDE ( ets_aes_enable = 0x4005c8cc ); 1519 | PROVIDE ( ets_aes_set_endian = 0x4005c928 ); 1520 | PROVIDE ( ets_aes_setkey_dec = 0x4005c994 ); 1521 | PROVIDE ( ets_aes_setkey_enc = 0x4005c97c ); 1522 | PROVIDE ( ets_bigint_disable = 0x4005c4e0 ); 1523 | PROVIDE ( ets_bigint_enable = 0x4005c498 ); 1524 | PROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 ); 1525 | PROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 ); 1526 | PROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 ); 1527 | PROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c ); 1528 | PROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 ); 1529 | PROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc ); 1530 | PROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 ); 1531 | PROVIDE ( ets_bigint_mult_prepare = 0x4005c630 ); 1532 | PROVIDE ( ets_bigint_wait_finish = 0x4005c520 ); 1533 | PROVIDE ( ets_post = 0x4000673c ); 1534 | PROVIDE ( ets_run = 0x400066bc ); 1535 | PROVIDE ( ets_set_idle_cb = 0x40006674 ); 1536 | PROVIDE ( ets_task = 0x40006688 ); 1537 | PROVIDE ( ets_efuse_get_8M_clock = 0x40008710 ); 1538 | PROVIDE ( ets_efuse_get_spiconfig = 0x40008658 ); 1539 | PROVIDE ( ets_efuse_program_op = 0x40008628 ); 1540 | PROVIDE ( ets_efuse_read_op = 0x40008600 ); 1541 | PROVIDE ( ets_intr_lock = 0x400067b0 ); 1542 | PROVIDE ( ets_intr_unlock = 0x400067c4 ); 1543 | PROVIDE ( ets_isr_attach = 0x400067ec ); 1544 | PROVIDE ( ets_waiti0 = 0x400067d8 ); 1545 | PROVIDE ( intr_matrix_set = 0x4000681c ); 1546 | PROVIDE ( check_pos = 0x400068b8 ); 1547 | PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c ); 1548 | PROVIDE ( ets_set_startup_callback = 0x4000688c ); 1549 | PROVIDE ( ets_set_user_start = 0x4000687c ); 1550 | PROVIDE ( ets_unpack_flash_code = 0x40007018 ); 1551 | PROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c ); 1552 | PROVIDE ( rom_main = 0x400076c4 ); 1553 | PROVIDE ( ets_write_char_uart = 0x40007cf8 ); 1554 | PROVIDE ( ets_install_putc1 = 0x40007d18 ); 1555 | PROVIDE ( ets_install_putc2 = 0x40007d38 ); 1556 | PROVIDE ( ets_install_uart_printf = 0x40007d28 ); 1557 | PROVIDE ( ets_printf = 0x40007d54 ); 1558 | PROVIDE ( rtc_boot_control = 0x4000821c ); 1559 | PROVIDE ( rtc_get_reset_reason = 0x400081d4 ); 1560 | PROVIDE ( rtc_get_wakeup_cause = 0x400081f4 ); 1561 | PROVIDE ( rtc_select_apb_bridge = 0x40008288 ); 1562 | PROVIDE ( set_rtc_memory_crc = 0x40008208 ); 1563 | PROVIDE ( software_reset = 0x4000824c ); 1564 | PROVIDE ( software_reset_cpu = 0x40008264 ); 1565 | PROVIDE ( ets_secure_boot_check = 0x4005cb40 ); 1566 | PROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 ); 1567 | PROVIDE ( ets_secure_boot_check_start = 0x4005cbcc ); 1568 | PROVIDE ( ets_secure_boot_finish = 0x4005ca84 ); 1569 | PROVIDE ( ets_secure_boot_hash = 0x4005cad4 ); 1570 | PROVIDE ( ets_secure_boot_obtain = 0x4005cb14 ); 1571 | PROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 ); 1572 | PROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 ); 1573 | PROVIDE ( ets_secure_boot_start = 0x4005ca34 ); 1574 | PROVIDE ( ets_sha_disable = 0x4005c0a8 ); 1575 | PROVIDE ( ets_sha_enable = 0x4005c07c ); 1576 | PROVIDE ( ets_sha_finish = 0x4005c104 ); 1577 | PROVIDE ( ets_sha_init = 0x4005c0d4 ); 1578 | PROVIDE ( ets_sha_update = 0x4005c2a0 ); 1579 | PROVIDE ( ets_delay_us = 0x40008534 ); 1580 | PROVIDE ( ets_get_cpu_frequency = 0x4000855c ); 1581 | PROVIDE ( ets_get_detected_xtal_freq = 0x40008588 ); 1582 | PROVIDE ( ets_get_xtal_scale = 0x4000856c ); 1583 | PROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 ); /* Updates g_ticks_per_us on the current CPU only; not on the other core */ 1584 | 1585 | /* Following are static data, but can be used, not generated by script <<<<< btdm data */ 1586 | PROVIDE ( hci_tl_env = 0x3ffb8154 ); 1587 | PROVIDE ( ld_acl_env = 0x3ffb8258 ); 1588 | PROVIDE ( ea_env = 0x3ffb80ec ); 1589 | PROVIDE ( lc_sco_data_path_config = 0x3ffb81f8 ); 1590 | PROVIDE ( lc_sco_env = 0x3ffb81fc ); 1591 | PROVIDE ( ld_active_ch_map = 0x3ffb8334 ); 1592 | PROVIDE ( ld_bcst_acl_env = 0x3ffb8274 ); 1593 | PROVIDE ( ld_csb_rx_env = 0x3ffb8278 ); 1594 | PROVIDE ( ld_csb_tx_env = 0x3ffb827c ); 1595 | PROVIDE ( ld_env = 0x3ffb9510 ); 1596 | PROVIDE ( ld_fm_env = 0x3ffb8284 ); 1597 | PROVIDE ( ld_inq_env = 0x3ffb82e4 ); 1598 | PROVIDE ( ld_iscan_env = 0x3ffb82e8 ); 1599 | PROVIDE ( ld_page_env = 0x3ffb82f0 ); 1600 | PROVIDE ( ld_pca_env = 0x3ffb82f4 ); 1601 | PROVIDE ( ld_pscan_env = 0x3ffb8308 ); 1602 | PROVIDE ( ld_sched_env = 0x3ffb830c ); 1603 | PROVIDE ( ld_sched_params = 0x3ffb96c0 ); 1604 | PROVIDE ( ld_sco_env = 0x3ffb824c ); 1605 | PROVIDE ( ld_sscan_env = 0x3ffb832c ); 1606 | PROVIDE ( ld_strain_env = 0x3ffb8330 ); 1607 | PROVIDE ( LM_Sniff = 0x3ffb8230 ); 1608 | PROVIDE ( LM_SniffSubRate = 0x3ffb8214 ); 1609 | PROVIDE ( prbs_64bytes = 0x3ff98992 ); 1610 | PROVIDE ( nvds_env = 0x3ffb8364 ); 1611 | PROVIDE ( nvds_magic_number = 0x3ff9912a ); 1612 | PROVIDE ( TASK_DESC_LLD = 0x3ff98b58 ); 1613 | 1614 | PROVIDE ( ld_acl_clk_isr = 0x40030cf8 ); 1615 | PROVIDE ( ld_acl_evt_canceled_cbk = 0x40033944 ); 1616 | PROVIDE ( ld_acl_evt_stop_cbk = 0x40033870 ); 1617 | PROVIDE ( ld_acl_evt_start_cbk = 0x40030ab0 ); 1618 | PROVIDE ( ld_acl_test_mode_update = 0x40032050 ); 1619 | PROVIDE ( ld_acl_resched = 0x40033814 ); 1620 | PROVIDE ( ld_acl_rx_isr = 0x40033aa8 ); 1621 | PROVIDE ( lc_acl_disc_ind_handler = 0x4002f270 ); 1622 | PROVIDE ( lc_pca_sscan_start_req_handler = 0x40029b34 ); 1623 | PROVIDE ( lmp_feats_req_ext_handler = 0x4002ccb0 ); 1624 | PROVIDE ( ld_pscan_em_init = 0x4003e5e8 ); 1625 | PROVIDE ( ld_acl_rsw_start = 0x40032e90 ); 1626 | PROVIDE ( ld_acl_sniff_enter = 0x40031244 ); 1627 | PROVIDE ( ld_acl_sniff_trans_sched = 0x40033734 ); 1628 | PROVIDE ( lc_pwr_decr_ind_handler = 0x4002859c ); 1629 | PROVIDE ( lc_pwr_incr_ind_handler = 0x400284a8 ); 1630 | PROVIDE ( lc_pwr_max_ind_handler = 0x40028690 ); 1631 | /* Above are static data, but can be used, not generated by script >>>>> btdm data */ 1632 | 1633 | /* 1634 | Address table for SPI driver functions in ESP32 ROM. 1635 | These functions are only linked from ROM when SPI_FLASH_ROM_DRIVER_PATCH is not set in configuration. 1636 | */ 1637 | 1638 | PROVIDE ( esp_rom_spiflash_write_encrypted = 0x40062e78 ); 1639 | PROVIDE ( esp_rom_spiflash_erase_area = 0x400631ac ); 1640 | PROVIDE ( esp_rom_spiflash_erase_block = 0x40062c4c ); 1641 | PROVIDE ( esp_rom_spiflash_erase_chip = 0x40062c14 ); 1642 | PROVIDE ( esp_rom_spiflash_erase_sector = 0x40062ccc ); 1643 | PROVIDE ( esp_rom_spiflash_attach = 0x40062a6c ); 1644 | PROVIDE ( esp_rom_spiflash_lock = 0x400628f0 ); 1645 | PROVIDE ( esp_rom_spiflash_read = 0x40062ed8 ); 1646 | PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062b64 ); /* SPIMasterReadModeCnfig */ 1647 | PROVIDE ( esp_rom_spiflash_read_status = 0x4006226c ); 1648 | PROVIDE ( esp_rom_spiflash_read_statushigh = 0x40062448 ); 1649 | PROVIDE ( esp_rom_spiflash_write = 0x40062d50 ); 1650 | PROVIDE ( esp_rom_spiflash_enable_write = 0x40062320 ); 1651 | PROVIDE ( esp_rom_spiflash_write_status = 0x400622f0 ); 1652 | 1653 | /* always using patched versions of these functions 1654 | PROVIDE ( esp_rom_spiflash_wait_idle = 0x400622c0 ); 1655 | PROVIDE ( esp_rom_spiflash_unlock = 0x400????? ); 1656 | */ 1657 | -------------------------------------------------------------------------------- /ld/esp32c3.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | /* Start 64k into the RAM region */ 3 | IRAM : ORIGIN = 0x40390000, LENGTH = 0x10000 4 | } 5 | 6 | PROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c ); 7 | PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000110 ); 8 | PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000114 ); 9 | PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000118 ); 10 | PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000011c ); 11 | PROVIDE( esp_rom_spiflash_erase_chip = 0x40000120 ); 12 | PROVIDE( esp_rom_spiflash_erase_block = 0x40000124 ); 13 | PROVIDE( esp_rom_spiflash_erase_sector = 0x40000128 ); 14 | PROVIDE( esp_rom_spiflash_write = 0x4000012c ); 15 | PROVIDE( esp_rom_spiflash_read = 0x40000130 ); 16 | PROVIDE( esp_rom_spiflash_config_param = 0x40000134 ); 17 | PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000138 ); 18 | PROVIDE( esp_rom_spiflash_select_qio_pins = 0x4000013c ); 19 | PROVIDE( esp_rom_spiflash_unlock = 0x40000140 ); 20 | PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000144 ); 21 | PROVIDE( esp_rom_spi_flash_send_resume = 0x40000148 ); 22 | PROVIDE( esp_rom_spi_flash_update_id = 0x4000014c ); 23 | PROVIDE( esp_rom_spiflash_config_clk = 0x40000150 ); 24 | PROVIDE( esp_rom_spiflash_config_readmode = 0x40000154 ); 25 | PROVIDE( esp_rom_spiflash_read_status = 0x40000158 ); 26 | PROVIDE( esp_rom_spiflash_read_statushigh = 0x4000015c ); 27 | PROVIDE( esp_rom_spiflash_write_status = 0x40000160 ); 28 | PROVIDE( esp_rom_spiflash_attach = 0x40000164 ); 29 | PROVIDE( spi_flash_get_chip_size = 0x40000168 ); 30 | PROVIDE( spi_flash_guard_set = 0x4000016c ); 31 | PROVIDE( spi_flash_guard_get = 0x40000170 ); 32 | PROVIDE( spi_flash_write_config_set = 0x40000174 ); 33 | PROVIDE( spi_flash_write_config_get = 0x40000178 ); 34 | PROVIDE( spi_flash_safe_write_address_func_set = 0x4000017c ); 35 | PROVIDE( spi_flash_unlock = 0x40000180 ); 36 | PROVIDE( spi_flash_erase_range = 0x40000184 ); 37 | PROVIDE( spi_flash_erase_sector = 0x40000188 ); 38 | PROVIDE( spi_flash_write = 0x4000018c ); 39 | PROVIDE( spi_flash_read = 0x40000190 ); 40 | PROVIDE( spi_flash_write_encrypted = 0x40000194 ); 41 | PROVIDE( spi_flash_read_encrypted = 0x40000198 ); 42 | PROVIDE( spi_flash_mmap_os_func_set = 0x4000019c ); 43 | PROVIDE( spi_flash_mmap_page_num_init = 0x400001a0 ); 44 | PROVIDE( spi_flash_mmap = 0x400001a4 ); 45 | PROVIDE( spi_flash_mmap_pages = 0x400001a8 ); 46 | PROVIDE( spi_flash_munmap = 0x400001ac ); 47 | PROVIDE( spi_flash_mmap_dump = 0x400001b0 ); 48 | PROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 ); 49 | PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 ); 50 | PROVIDE( spi_flash_cache2phys = 0x400001bc ); 51 | PROVIDE( spi_flash_phys2cache = 0x400001c0 ); 52 | PROVIDE( spi_flash_disable_cache = 0x400001c4 ); 53 | PROVIDE( spi_flash_restore_cache = 0x400001c8 ); 54 | PROVIDE( spi_flash_cache_enabled = 0x400001cc ); 55 | PROVIDE( spi_flash_enable_cache = 0x400001d0 ); 56 | PROVIDE( spi_cache_mode_switch = 0x400001d4 ); 57 | PROVIDE( spi_common_set_dummy_output = 0x400001d8 ); 58 | PROVIDE( spi_common_set_flash_cs_timing = 0x400001dc ); 59 | PROVIDE( esp_enable_cache_flash_wrap = 0x400001e0 ); 60 | PROVIDE( SPIEraseArea = 0x400001e4 ); 61 | PROVIDE( SPILock = 0x400001e8 ); 62 | PROVIDE( SPIMasterReadModeCnfig = 0x400001ec ); 63 | PROVIDE( SPI_Common_Command = 0x400001f0 ); 64 | PROVIDE( SPI_WakeUp = 0x400001f4 ); 65 | PROVIDE( SPI_block_erase = 0x400001f8 ); 66 | PROVIDE( SPI_chip_erase = 0x400001fc ); 67 | PROVIDE( SPI_init = 0x40000200 ); 68 | PROVIDE( SPI_page_program = 0x40000204 ); 69 | PROVIDE( SPI_read_data = 0x40000208 ); 70 | PROVIDE( SPI_sector_erase = 0x4000020c ); 71 | PROVIDE( SPI_write_enable = 0x40000210 ); 72 | PROVIDE( SelectSpiFunction = 0x40000214 ); 73 | PROVIDE( SetSpiDrvs = 0x40000218 ); 74 | PROVIDE( Wait_SPI_Idle = 0x4000021c ); 75 | PROVIDE( spi_dummy_len_fix = 0x40000220 ); 76 | PROVIDE( Disable_QMode = 0x40000224 ); 77 | PROVIDE( Enable_QMode = 0x40000228 ); 78 | 79 | 80 | PROVIDE( ets_efuse_get_spiconfig = 0x4000071c ); 81 | 82 | 83 | PROVIDE( uart_tx_one_char = 0x40000068 ); 84 | 85 | /*************************************** 86 | Group miniz 87 | ***************************************/ 88 | 89 | /* Functions */ 90 | mz_adler32 = 0x400000c0; 91 | mz_crc32 = 0x400000c4; 92 | mz_free = 0x400000c8; 93 | tdefl_compress = 0x400000cc; 94 | tdefl_compress_buffer = 0x400000d0; 95 | tdefl_compress_mem_to_heap = 0x400000d4; 96 | tdefl_compress_mem_to_mem = 0x400000d8; 97 | tdefl_compress_mem_to_output = 0x400000dc; 98 | tdefl_get_adler32 = 0x400000e0; 99 | tdefl_get_prev_return_status = 0x400000e4; 100 | tdefl_init = 0x400000e8; 101 | tdefl_write_image_to_png_file_in_memory = 0x400000ec; 102 | tdefl_write_image_to_png_file_in_memory_ex = 0x400000f0; 103 | tinfl_decompress = 0x400000f4; 104 | tinfl_decompress_mem_to_callback = 0x400000f8; 105 | tinfl_decompress_mem_to_heap = 0x400000fc; 106 | tinfl_decompress_mem_to_mem = 0x40000100; -------------------------------------------------------------------------------- /ld/esp32c6.x: -------------------------------------------------------------------------------- 1 | 2 | MEMORY { 3 | /* Start 64k into the RAM region */ 4 | IRAM : ORIGIN = 0x40810000, LENGTH = 0x10000 5 | } 6 | 7 | PROVIDE(esp_rom_spiflash_attach = spi_flash_attach); 8 | 9 | 10 | /* 11 | * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | */ 15 | /* ROM function interface esp32c6.rom.ld for esp32c6 16 | * 17 | * 18 | * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b 19 | * 20 | * Compatible with ROM where ECO version equal or greater to 0. 21 | * 22 | * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 23 | */ 24 | 25 | /*************************************** 26 | Group common 27 | ***************************************/ 28 | 29 | /* Functions */ 30 | rtc_get_reset_reason = 0x40000018; 31 | analog_super_wdt_reset_happened = 0x4000001c; 32 | rtc_get_wakeup_cause = 0x40000020; 33 | rtc_unhold_all_pads = 0x40000024; 34 | ets_printf = 0x40000028; 35 | ets_install_putc1 = 0x4000002c; 36 | ets_install_putc2 = 0x40000030; 37 | ets_install_uart_printf = 0x40000034; 38 | ets_install_usb_printf = 0x40000038; 39 | ets_get_printf_channel = 0x4000003c; 40 | ets_delay_us = 0x40000040; 41 | ets_get_cpu_frequency = 0x40000044; 42 | ets_update_cpu_frequency = 0x40000048; 43 | ets_install_lock = 0x4000004c; 44 | UartRxString = 0x40000050; 45 | UartGetCmdLn = 0x40000054; 46 | uart_tx_one_char = 0x40000058; 47 | uart_tx_one_char2 = 0x4000005c; 48 | uart_rx_one_char = 0x40000060; 49 | uart_rx_one_char_block = 0x40000064; 50 | uart_rx_intr_handler = 0x40000068; 51 | uart_rx_readbuff = 0x4000006c; 52 | uartAttach = 0x40000070; 53 | uart_tx_flush = 0x40000074; 54 | uart_tx_wait_idle = 0x40000078; 55 | uart_div_modify = 0x4000007c; 56 | ets_write_char_uart = 0x40000080; 57 | uart_tx_switch = 0x40000084; 58 | roundup2 = 0x40000088; 59 | multofup = 0x4000008c; 60 | software_reset = 0x40000090; 61 | software_reset_cpu = 0x40000094; 62 | ets_clk_assist_debug_clock_enable = 0x40000098; 63 | clear_super_wdt_reset_flag = 0x4000009c; 64 | disable_default_watchdog = 0x400000a0; 65 | esp_rom_set_rtc_wake_addr = 0x400000a4; 66 | esp_rom_get_rtc_wake_addr = 0x400000a8; 67 | send_packet = 0x400000ac; 68 | recv_packet = 0x400000b0; 69 | GetUartDevice = 0x400000b4; 70 | UartDwnLdProc = 0x400000b8; 71 | GetSecurityInfoProc = 0x400000bc; 72 | Uart_Init = 0x400000c0; 73 | ets_set_user_start = 0x400000c4; 74 | /* Data (.data, .bss, .rodata) */ 75 | ets_rom_layout_p = 0x4004fffc; 76 | ets_ops_table_ptr = 0x4087fff8; 77 | g_saved_pc = 0x4087fffc; 78 | 79 | 80 | /*************************************** 81 | Group miniz 82 | ***************************************/ 83 | 84 | /* Functions */ 85 | mz_adler32 = 0x400000c8; 86 | mz_free = 0x400000cc; 87 | tdefl_compress = 0x400000d0; 88 | tdefl_compress_buffer = 0x400000d4; 89 | tdefl_compress_mem_to_heap = 0x400000d8; 90 | tdefl_compress_mem_to_mem = 0x400000dc; 91 | tdefl_compress_mem_to_output = 0x400000e0; 92 | tdefl_get_adler32 = 0x400000e4; 93 | tdefl_get_prev_return_status = 0x400000e8; 94 | tdefl_init = 0x400000ec; 95 | tdefl_write_image_to_png_file_in_memory = 0x400000f0; 96 | tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4; 97 | tinfl_decompress = 0x400000f8; 98 | tinfl_decompress_mem_to_callback = 0x400000fc; 99 | tinfl_decompress_mem_to_heap = 0x40000100; 100 | tinfl_decompress_mem_to_mem = 0x40000104; 101 | 102 | 103 | /*************************************** 104 | Group tjpgd 105 | ***************************************/ 106 | 107 | /* Functions */ 108 | jd_prepare = 0x40000108; 109 | jd_decomp = 0x4000010c; 110 | 111 | 112 | /*************************************** 113 | Group spiflash_legacy 114 | ***************************************/ 115 | 116 | /* Functions */ 117 | esp_rom_spiflash_wait_idle = 0x40000110; 118 | esp_rom_spiflash_write_encrypted = 0x40000114; 119 | esp_rom_spiflash_write_encrypted_dest = 0x40000118; 120 | esp_rom_spiflash_write_encrypted_enable = 0x4000011c; 121 | esp_rom_spiflash_write_encrypted_disable = 0x40000120; 122 | esp_rom_spiflash_erase_chip = 0x40000124; 123 | _esp_rom_spiflash_erase_sector = 0x40000128; 124 | _esp_rom_spiflash_erase_block = 0x4000012c; 125 | _esp_rom_spiflash_write = 0x40000130; 126 | _esp_rom_spiflash_read = 0x40000134; 127 | _esp_rom_spiflash_unlock = 0x40000138; 128 | _SPIEraseArea = 0x4000013c; 129 | _SPI_write_enable = 0x40000140; 130 | esp_rom_spiflash_erase_sector = 0x40000144; 131 | esp_rom_spiflash_erase_block = 0x40000148; 132 | esp_rom_spiflash_write = 0x4000014c; 133 | esp_rom_spiflash_read = 0x40000150; 134 | esp_rom_spiflash_unlock = 0x40000154; 135 | SPIEraseArea = 0x40000158; 136 | SPI_write_enable = 0x4000015c; 137 | esp_rom_spiflash_config_param = 0x40000160; 138 | esp_rom_spiflash_read_user_cmd = 0x40000164; 139 | esp_rom_spiflash_select_qio_pins = 0x40000168; 140 | esp_rom_spi_flash_auto_sus_res = 0x4000016c; 141 | esp_rom_spi_flash_send_resume = 0x40000170; 142 | esp_rom_spi_flash_update_id = 0x40000174; 143 | esp_rom_spiflash_config_clk = 0x40000178; 144 | esp_rom_spiflash_config_readmode = 0x4000017c; 145 | esp_rom_spiflash_read_status = 0x40000180; 146 | esp_rom_spiflash_read_statushigh = 0x40000184; 147 | esp_rom_spiflash_write_status = 0x40000188; 148 | spi_cache_mode_switch = 0x4000018c; 149 | spi_common_set_dummy_output = 0x40000190; 150 | spi_common_set_flash_cs_timing = 0x40000194; 151 | esp_rom_spi_set_address_bit_len = 0x40000198; 152 | SPILock = 0x4000019c; 153 | SPIMasterReadModeCnfig = 0x400001a0; 154 | SPI_Common_Command = 0x400001a4; 155 | SPI_WakeUp = 0x400001a8; 156 | SPI_block_erase = 0x400001ac; 157 | SPI_chip_erase = 0x400001b0; 158 | SPI_init = 0x400001b4; 159 | SPI_page_program = 0x400001b8; 160 | SPI_read_data = 0x400001bc; 161 | SPI_sector_erase = 0x400001c0; 162 | SelectSpiFunction = 0x400001c4; 163 | SetSpiDrvs = 0x400001c8; 164 | Wait_SPI_Idle = 0x400001cc; 165 | spi_dummy_len_fix = 0x400001d0; 166 | Disable_QMode = 0x400001d4; 167 | Enable_QMode = 0x400001d8; 168 | spi_flash_attach = 0x400001dc; 169 | spi_flash_get_chip_size = 0x400001e0; 170 | spi_flash_guard_set = 0x400001e4; 171 | spi_flash_guard_get = 0x400001e8; 172 | spi_flash_read_encrypted = 0x400001ec; 173 | /* Data (.data, .bss, .rodata) */ 174 | rom_spiflash_legacy_funcs = 0x4087fff0; 175 | rom_spiflash_legacy_data = 0x4087ffec; 176 | g_flash_guard_ops = 0x4087fff4; 177 | 178 | /* Note: esp_rom_spiflash_write_disable was moved from esp32c6.rom.spiflash.ld */ 179 | esp_rom_spiflash_write_disable = 0x40000278; 180 | 181 | /*************************************** 182 | Group hal_wdt 183 | ***************************************/ 184 | 185 | /* Functions */ 186 | wdt_hal_init = 0x40000394; 187 | wdt_hal_deinit = 0x40000398; 188 | wdt_hal_config_stage = 0x4000039c; 189 | wdt_hal_write_protect_disable = 0x400003a0; 190 | wdt_hal_write_protect_enable = 0x400003a4; 191 | wdt_hal_enable = 0x400003a8; 192 | wdt_hal_disable = 0x400003ac; 193 | wdt_hal_handle_intr = 0x400003b0; 194 | wdt_hal_feed = 0x400003b4; 195 | wdt_hal_set_flashboot_en = 0x400003b8; 196 | wdt_hal_is_enabled = 0x400003bc; 197 | 198 | 199 | /*************************************** 200 | Group hal_systimer 201 | ***************************************/ 202 | 203 | /* Functions */ 204 | /* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ 205 | /* systimer_hal_init = 0x400003c0; */ 206 | /* systimer_hal_deinit = 0x400003c4; */ 207 | 208 | systimer_hal_set_tick_rate_ops = 0x400003c8; 209 | systimer_hal_get_counter_value = 0x400003cc; 210 | systimer_hal_get_time = 0x400003d0; 211 | systimer_hal_set_alarm_target = 0x400003d4; 212 | systimer_hal_set_alarm_period = 0x400003d8; 213 | systimer_hal_get_alarm_value = 0x400003dc; 214 | systimer_hal_enable_alarm_int = 0x400003e0; 215 | systimer_hal_on_apb_freq_update = 0x400003e4; 216 | systimer_hal_counter_value_advance = 0x400003e8; 217 | systimer_hal_enable_counter = 0x400003ec; 218 | systimer_hal_select_alarm_mode = 0x400003f0; 219 | systimer_hal_connect_alarm_counter = 0x400003f4; 220 | systimer_hal_counter_can_stall_by_cpu = 0x400003f8; 221 | 222 | 223 | /*************************************** 224 | Group cache 225 | ***************************************/ 226 | 227 | /* Functions */ 228 | Cache_Get_ICache_Line_Size = 0x40000628; 229 | Cache_Get_Mode = 0x4000062c; 230 | Cache_Address_Through_Cache = 0x40000630; 231 | ROM_Boot_Cache_Init = 0x40000634; 232 | MMU_Set_Page_Mode = 0x40000638; 233 | MMU_Get_Page_Mode = 0x4000063c; 234 | Cache_Invalidate_ICache_Items = 0x40000640; 235 | Cache_Op_Addr = 0x40000644; 236 | Cache_Invalidate_Addr = 0x40000648; 237 | Cache_Invalidate_ICache_All = 0x4000064c; 238 | Cache_Mask_All = 0x40000650; 239 | Cache_UnMask_Dram0 = 0x40000654; 240 | Cache_Suspend_ICache_Autoload = 0x40000658; 241 | Cache_Resume_ICache_Autoload = 0x4000065c; 242 | Cache_Start_ICache_Preload = 0x40000660; 243 | Cache_ICache_Preload_Done = 0x40000664; 244 | Cache_End_ICache_Preload = 0x40000668; 245 | Cache_Config_ICache_Autoload = 0x4000066c; 246 | Cache_Enable_ICache_Autoload = 0x40000670; 247 | Cache_Disable_ICache_Autoload = 0x40000674; 248 | Cache_Enable_ICache_PreLock = 0x40000678; 249 | Cache_Disable_ICache_PreLock = 0x4000067c; 250 | Cache_Lock_ICache_Items = 0x40000680; 251 | Cache_Unlock_ICache_Items = 0x40000684; 252 | Cache_Lock_Addr = 0x40000688; 253 | Cache_Unlock_Addr = 0x4000068c; 254 | Cache_Disable_ICache = 0x40000690; 255 | Cache_Enable_ICache = 0x40000694; 256 | Cache_Suspend_ICache = 0x40000698; 257 | Cache_Resume_ICache = 0x4000069c; 258 | Cache_Freeze_ICache_Enable = 0x400006a0; 259 | Cache_Freeze_ICache_Disable = 0x400006a4; 260 | Cache_Set_IDROM_MMU_Size = 0x400006a8; 261 | Cache_Get_IROM_MMU_End = 0x400006ac; 262 | Cache_Get_DROM_MMU_End = 0x400006b0; 263 | Cache_MMU_Init = 0x400006b4; 264 | Cache_MSPI_MMU_Set = 0x400006b8; 265 | Cache_Travel_Tag_Memory = 0x400006bc; 266 | Cache_Get_Virtual_Addr = 0x400006c0; 267 | /* Data (.data, .bss, .rodata) */ 268 | rom_cache_op_cb = 0x4087ffcc; 269 | rom_cache_internal_table_ptr = 0x4087ffc8; 270 | 271 | 272 | /*************************************** 273 | Group clock 274 | ***************************************/ 275 | 276 | /* Functions */ 277 | ets_clk_get_xtal_freq = 0x400006c4; 278 | ets_clk_get_cpu_freq = 0x400006c8; 279 | ets_clk_apb_wait_ready = 0x400006cc; 280 | ets_clk_mspi_apb_wait_ready = 0x400006d0; 281 | 282 | 283 | /*************************************** 284 | Group gpio 285 | ***************************************/ 286 | 287 | /* Functions */ 288 | gpio_input_get = 0x400006d4; 289 | gpio_matrix_in = 0x400006d8; 290 | gpio_matrix_out = 0x400006dc; 291 | gpio_output_disable = 0x400006e0; 292 | gpio_output_enable = 0x400006e4; 293 | gpio_output_set = 0x400006e8; 294 | gpio_pad_hold = 0x400006ec; 295 | gpio_pad_input_disable = 0x400006f0; 296 | gpio_pad_input_enable = 0x400006f4; 297 | gpio_pad_pulldown = 0x400006f8; 298 | gpio_pad_pullup = 0x400006fc; 299 | gpio_pad_select_gpio = 0x40000700; 300 | gpio_pad_set_drv = 0x40000704; 301 | gpio_pad_unhold = 0x40000708; 302 | gpio_pin_wakeup_disable = 0x4000070c; 303 | gpio_pin_wakeup_enable = 0x40000710; 304 | gpio_bypass_matrix_in = 0x40000714; 305 | 306 | 307 | /*************************************** 308 | Group interrupts 309 | ***************************************/ 310 | 311 | /* Functions */ 312 | esprv_intc_int_set_priority = 0x40000718; 313 | esprv_intc_int_set_threshold = 0x4000071c; 314 | esprv_intc_int_enable = 0x40000720; 315 | esprv_intc_int_disable = 0x40000724; 316 | esprv_intc_int_set_type = 0x40000728; 317 | PROVIDE( intr_handler_set = 0x4000072c ); 318 | intr_matrix_set = 0x40000730; 319 | ets_intr_lock = 0x40000734; 320 | ets_intr_unlock = 0x40000738; 321 | ets_isr_attach = 0x4000073c; 322 | ets_isr_mask = 0x40000740; 323 | ets_isr_unmask = 0x40000744; 324 | 325 | 326 | /*************************************** 327 | Group crypto 328 | ***************************************/ 329 | 330 | /* Functions */ 331 | md5_vector = 0x40000748; 332 | MD5Init = 0x4000074c; 333 | MD5Update = 0x40000750; 334 | MD5Final = 0x40000754; 335 | crc32_le = 0x40000758; 336 | crc16_le = 0x4000075c; 337 | crc8_le = 0x40000760; 338 | crc32_be = 0x40000764; 339 | crc16_be = 0x40000768; 340 | crc8_be = 0x4000076c; 341 | esp_crc8 = 0x40000770; 342 | ets_sha_enable = 0x40000774; 343 | ets_sha_disable = 0x40000778; 344 | ets_sha_get_state = 0x4000077c; 345 | ets_sha_init = 0x40000780; 346 | ets_sha_process = 0x40000784; 347 | ets_sha_starts = 0x40000788; 348 | ets_sha_update = 0x4000078c; 349 | ets_sha_finish = 0x40000790; 350 | ets_sha_clone = 0x40000794; 351 | ets_hmac_enable = 0x40000798; 352 | ets_hmac_disable = 0x4000079c; 353 | ets_hmac_calculate_message = 0x400007a0; 354 | ets_hmac_calculate_downstream = 0x400007a4; 355 | ets_hmac_invalidate_downstream = 0x400007a8; 356 | ets_jtag_enable_temporarily = 0x400007ac; 357 | ets_aes_enable = 0x400007b0; 358 | ets_aes_disable = 0x400007b4; 359 | ets_aes_setkey = 0x400007b8; 360 | ets_aes_block = 0x400007bc; 361 | ets_aes_setkey_dec = 0x400007c0; 362 | ets_aes_setkey_enc = 0x400007c4; 363 | ets_bigint_enable = 0x400007c8; 364 | ets_bigint_disable = 0x400007cc; 365 | ets_bigint_multiply = 0x400007d0; 366 | ets_bigint_modmult = 0x400007d4; 367 | ets_bigint_modexp = 0x400007d8; 368 | ets_bigint_wait_finish = 0x400007dc; 369 | ets_bigint_getz = 0x400007e0; 370 | ets_ds_enable = 0x400007e4; 371 | ets_ds_disable = 0x400007e8; 372 | ets_ds_start_sign = 0x400007ec; 373 | ets_ds_is_busy = 0x400007f0; 374 | ets_ds_finish_sign = 0x400007f4; 375 | ets_ds_encrypt_params = 0x400007f8; 376 | ets_mgf1_sha256 = 0x400007fc; 377 | /* Data (.data, .bss, .rodata) */ 378 | crc32_le_table_ptr = 0x4004fff8; 379 | crc16_le_table_ptr = 0x4004fff4; 380 | crc8_le_table_ptr = 0x4004fff0; 381 | crc32_be_table_ptr = 0x4004ffec; 382 | crc16_be_table_ptr = 0x4004ffe8; 383 | crc8_be_table_ptr = 0x4004ffe4; 384 | 385 | 386 | /*************************************** 387 | Group efuse 388 | ***************************************/ 389 | 390 | /* Functions */ 391 | ets_efuse_read = 0x40000800; 392 | ets_efuse_program = 0x40000804; 393 | ets_efuse_clear_program_registers = 0x40000808; 394 | ets_efuse_write_key = 0x4000080c; 395 | ets_efuse_get_read_register_address = 0x40000810; 396 | ets_efuse_get_key_purpose = 0x40000814; 397 | ets_efuse_key_block_unused = 0x40000818; 398 | ets_efuse_find_unused_key_block = 0x4000081c; 399 | ets_efuse_rs_calculate = 0x40000820; 400 | ets_efuse_count_unused_key_blocks = 0x40000824; 401 | ets_efuse_secure_boot_enabled = 0x40000828; 402 | ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000082c; 403 | ets_efuse_cache_encryption_enabled = 0x40000830; 404 | ets_efuse_download_modes_disabled = 0x40000834; 405 | ets_efuse_find_purpose = 0x40000838; 406 | ets_efuse_force_send_resume = 0x4000083c; 407 | ets_efuse_get_flash_delay_us = 0x40000840; 408 | ets_efuse_get_mac = 0x40000844; 409 | ets_efuse_get_uart_print_control = 0x40000848; 410 | ets_efuse_direct_boot_mode_disabled = 0x4000084c; 411 | ets_efuse_security_download_modes_enabled = 0x40000850; 412 | ets_efuse_set_timing = 0x40000854; 413 | ets_efuse_jtag_disabled = 0x40000858; 414 | ets_efuse_usb_print_is_disabled = 0x4000085c; 415 | ets_efuse_usb_download_mode_disabled = 0x40000860; 416 | ets_efuse_usb_device_disabled = 0x40000864; 417 | ets_efuse_secure_boot_fast_wake_enabled = 0x40000868; 418 | 419 | 420 | /*************************************** 421 | Group secureboot 422 | ***************************************/ 423 | 424 | /* Functions */ 425 | ets_emsa_pss_verify = 0x4000086c; 426 | ets_rsa_pss_verify = 0x40000870; 427 | ets_secure_boot_verify_bootloader_with_keys = 0x40000874; 428 | ets_secure_boot_verify_signature = 0x40000878; 429 | ets_secure_boot_read_key_digests = 0x4000087c; 430 | ets_secure_boot_revoke_public_key_digest = 0x40000880; 431 | 432 | 433 | /*************************************** 434 | Group usb_device_uart 435 | ***************************************/ 436 | 437 | /* Functions */ 438 | usb_serial_device_rx_one_char = 0x40000a80; 439 | usb_serial_device_rx_one_char_block = 0x40000a84; 440 | usb_serial_device_tx_flush = 0x40000a88; 441 | usb_serial_device_tx_one_char = 0x40000a8c; 442 | 443 | 444 | /*************************************** 445 | Group lldesc 446 | ***************************************/ 447 | 448 | /* Functions */ 449 | lldesc_build_chain = 0x40000a90; 450 | 451 | 452 | /*************************************** 453 | Group sip 454 | ***************************************/ 455 | 456 | /* Functions */ 457 | sip_after_tx_complete = 0x40000a94; 458 | sip_alloc_to_host_evt = 0x40000a98; 459 | sip_download_begin = 0x40000a9c; 460 | sip_get_ptr = 0x40000aa0; 461 | sip_get_state = 0x40000aa4; 462 | sip_init_attach = 0x40000aa8; 463 | sip_install_rx_ctrl_cb = 0x40000aac; 464 | sip_install_rx_data_cb = 0x40000ab0; 465 | sip_is_active = 0x40000ab4; 466 | sip_post_init = 0x40000ab8; 467 | sip_reclaim_from_host_cmd = 0x40000abc; 468 | sip_reclaim_tx_data_pkt = 0x40000ac0; 469 | sip_send = 0x40000ac4; 470 | sip_to_host_chain_append = 0x40000ac8; 471 | sip_to_host_evt_send_done = 0x40000acc; 472 | 473 | 474 | /*************************************** 475 | Group slc 476 | ***************************************/ 477 | 478 | /* Functions */ 479 | slc_add_credits = 0x40000ad0; 480 | slc_enable = 0x40000ad4; 481 | slc_from_host_chain_fetch = 0x40000ad8; 482 | slc_from_host_chain_recycle = 0x40000adc; 483 | slc_has_pkt_to_host = 0x40000ae0; 484 | slc_init_attach = 0x40000ae4; 485 | slc_init_credit = 0x40000ae8; 486 | slc_reattach = 0x40000aec; 487 | slc_send_to_host_chain = 0x40000af0; 488 | slc_set_host_io_max_window = 0x40000af4; 489 | slc_to_host_chain_recycle = 0x40000af8; 490 | -------------------------------------------------------------------------------- /ld/esp32h2.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | /* Start 64k into the RAM region */ 3 | IRAM : ORIGIN = 0x40810000, LENGTH = 0x10000 4 | } 5 | 6 | PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); 7 | PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); 8 | PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); 9 | PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); 10 | 11 | /* 12 | * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 13 | * 14 | * SPDX-License-Identifier: Apache-2.0 15 | */ 16 | /* ROM function interface esp32h2.rom.ld for esp32h2 17 | * 18 | * 19 | * Generated from ./target/esp32h2/interface-esp32h2.yml md5sum c0ad4e113e5b29bb9d799f10f03edbc1 20 | * 21 | * Compatible with ROM where ECO version equal or greater to 0. 22 | * 23 | * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 24 | */ 25 | 26 | /*************************************** 27 | Group common 28 | ***************************************/ 29 | 30 | /* Functions */ 31 | rtc_get_reset_reason = 0x40000018; 32 | analog_super_wdt_reset_happened = 0x4000001c; 33 | rtc_get_wakeup_cause = 0x40000020; 34 | rtc_unhold_all_pads = 0x40000024; 35 | ets_printf = 0x40000028; 36 | ets_install_putc1 = 0x4000002c; 37 | ets_install_putc2 = 0x40000030; 38 | ets_install_uart_printf = 0x40000034; 39 | ets_install_usb_printf = 0x40000038; 40 | ets_get_printf_channel = 0x4000003c; 41 | ets_delay_us = 0x40000040; 42 | ets_get_cpu_frequency = 0x40000044; 43 | ets_update_cpu_frequency = 0x40000048; 44 | ets_install_lock = 0x4000004c; 45 | UartRxString = 0x40000050; 46 | UartGetCmdLn = 0x40000054; 47 | uart_tx_one_char = 0x40000058; 48 | uart_tx_one_char2 = 0x4000005c; 49 | uart_rx_one_char = 0x40000060; 50 | uart_rx_one_char_block = 0x40000064; 51 | uart_rx_intr_handler = 0x40000068; 52 | uart_rx_readbuff = 0x4000006c; 53 | uartAttach = 0x40000070; 54 | uart_tx_flush = 0x40000074; 55 | uart_tx_wait_idle = 0x40000078; 56 | uart_div_modify = 0x4000007c; 57 | ets_write_char_uart = 0x40000080; 58 | uart_tx_switch = 0x40000084; 59 | roundup2 = 0x40000088; 60 | multofup = 0x4000008c; 61 | software_reset = 0x40000090; 62 | software_reset_cpu = 0x40000094; 63 | ets_clk_assist_debug_clock_enable = 0x40000098; 64 | clear_super_wdt_reset_flag = 0x4000009c; 65 | disable_default_watchdog = 0x400000a0; 66 | esp_rom_set_rtc_wake_addr = 0x400000a4; 67 | esp_rom_get_rtc_wake_addr = 0x400000a8; 68 | send_packet = 0x400000ac; 69 | recv_packet = 0x400000b0; 70 | GetUartDevice = 0x400000b4; 71 | UartDwnLdProc = 0x400000b8; 72 | GetSecurityInfoProc = 0x400000bc; 73 | Uart_Init = 0x400000c0; 74 | ets_set_user_start = 0x400000c4; 75 | /* Data (.data, .bss, .rodata) */ 76 | ets_rom_layout_p = 0x4001fffc; 77 | ets_ops_table_ptr = 0x4084fff8; 78 | g_saved_pc = 0x4084fffc; 79 | 80 | 81 | /*************************************** 82 | Group miniz 83 | ***************************************/ 84 | 85 | /* Functions */ 86 | mz_adler32 = 0x400000c8; 87 | mz_free = 0x400000cc; 88 | tdefl_compress = 0x400000d0; 89 | tdefl_compress_buffer = 0x400000d4; 90 | tdefl_compress_mem_to_heap = 0x400000d8; 91 | tdefl_compress_mem_to_mem = 0x400000dc; 92 | tdefl_compress_mem_to_output = 0x400000e0; 93 | tdefl_get_adler32 = 0x400000e4; 94 | tdefl_get_prev_return_status = 0x400000e8; 95 | tdefl_init = 0x400000ec; 96 | tdefl_write_image_to_png_file_in_memory = 0x400000f0; 97 | tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4; 98 | tinfl_decompress = 0x400000f8; 99 | tinfl_decompress_mem_to_callback = 0x400000fc; 100 | tinfl_decompress_mem_to_heap = 0x40000100; 101 | tinfl_decompress_mem_to_mem = 0x40000104; 102 | 103 | 104 | /*************************************** 105 | Group spiflash_legacy 106 | ***************************************/ 107 | 108 | /* Functions */ 109 | esp_rom_spiflash_wait_idle = 0x40000108; 110 | esp_rom_spiflash_write_encrypted = 0x4000010c; 111 | esp_rom_spiflash_write_encrypted_dest = 0x40000110; 112 | esp_rom_spiflash_write_encrypted_enable = 0x40000114; 113 | esp_rom_spiflash_write_encrypted_disable = 0x40000118; 114 | esp_rom_spiflash_erase_chip = 0x4000011c; 115 | _esp_rom_spiflash_erase_sector = 0x40000120; 116 | _esp_rom_spiflash_erase_block = 0x40000124; 117 | _esp_rom_spiflash_write = 0x40000128; 118 | _esp_rom_spiflash_read = 0x4000012c; 119 | _esp_rom_spiflash_unlock = 0x40000130; 120 | _SPIEraseArea = 0x40000134; 121 | _SPI_write_enable = 0x40000138; 122 | esp_rom_spiflash_erase_sector = 0x4000013c; 123 | esp_rom_spiflash_erase_block = 0x40000140; 124 | esp_rom_spiflash_write = 0x40000144; 125 | esp_rom_spiflash_read = 0x40000148; 126 | esp_rom_spiflash_unlock = 0x4000014c; 127 | SPIEraseArea = 0x40000150; 128 | SPI_write_enable = 0x40000154; 129 | esp_rom_spiflash_config_param = 0x40000158; 130 | esp_rom_spiflash_read_user_cmd = 0x4000015c; 131 | esp_rom_spiflash_select_qio_pins = 0x40000160; 132 | esp_rom_spi_flash_auto_sus_res = 0x40000164; 133 | esp_rom_spi_flash_send_resume = 0x40000168; 134 | esp_rom_spi_flash_update_id = 0x4000016c; 135 | esp_rom_spiflash_config_clk = 0x40000170; 136 | esp_rom_spiflash_config_readmode = 0x40000174; 137 | esp_rom_spiflash_read_status = 0x40000178; 138 | esp_rom_spiflash_read_statushigh = 0x4000017c; 139 | esp_rom_spiflash_write_status = 0x40000180; 140 | spi_cache_mode_switch = 0x40000184; 141 | spi_common_set_dummy_output = 0x40000188; 142 | spi_common_set_flash_cs_timing = 0x4000018c; 143 | esp_rom_spi_set_address_bit_len = 0x40000190; 144 | SPILock = 0x40000194; 145 | SPIMasterReadModeCnfig = 0x40000198; 146 | SPI_Common_Command = 0x4000019c; 147 | SPI_WakeUp = 0x400001a0; 148 | SPI_block_erase = 0x400001a4; 149 | SPI_chip_erase = 0x400001a8; 150 | SPI_init = 0x400001ac; 151 | SPI_page_program = 0x400001b0; 152 | SPI_read_data = 0x400001b4; 153 | SPI_sector_erase = 0x400001b8; 154 | SelectSpiFunction = 0x400001bc; 155 | SetSpiDrvs = 0x400001c0; 156 | Wait_SPI_Idle = 0x400001c4; 157 | spi_dummy_len_fix = 0x400001c8; 158 | Disable_QMode = 0x400001cc; 159 | Enable_QMode = 0x400001d0; 160 | spi_flash_attach = 0x400001d4; 161 | spi_flash_get_chip_size = 0x400001d8; 162 | spi_flash_guard_set = 0x400001dc; 163 | spi_flash_guard_get = 0x400001e0; 164 | spi_flash_read_encrypted = 0x400001e4; 165 | /* Data (.data, .bss, .rodata) */ 166 | rom_spiflash_legacy_funcs = 0x4084fff0; 167 | rom_spiflash_legacy_data = 0x4084ffec; 168 | g_flash_guard_ops = 0x4084fff4; 169 | 170 | /* Note: esp_rom_spiflash_write_disable was moved from esp32c6.rom.spiflash.ld */ 171 | esp_rom_spiflash_write_disable = 0x40000270; 172 | 173 | /*************************************** 174 | Group hal_systimer 175 | ***************************************/ 176 | 177 | /* Functions */ 178 | /* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ 179 | /* systimer_hal_init = 0x400003b8; */ 180 | /* systimer_hal_deinit = 0x400003bc; */ 181 | 182 | systimer_hal_set_tick_rate_ops = 0x400003c0; 183 | systimer_hal_get_counter_value = 0x400003c4; 184 | systimer_hal_get_time = 0x400003c8; 185 | systimer_hal_set_alarm_target = 0x400003cc; 186 | systimer_hal_set_alarm_period = 0x400003d0; 187 | systimer_hal_get_alarm_value = 0x400003d4; 188 | systimer_hal_enable_alarm_int = 0x400003d8; 189 | systimer_hal_on_apb_freq_update = 0x400003dc; 190 | systimer_hal_counter_value_advance = 0x400003e0; 191 | systimer_hal_enable_counter = 0x400003e4; 192 | systimer_hal_select_alarm_mode = 0x400003e8; 193 | systimer_hal_connect_alarm_counter = 0x400003ec; 194 | systimer_hal_counter_can_stall_by_cpu = 0x400003f0; 195 | 196 | 197 | /*************************************** 198 | Group cache 199 | ***************************************/ 200 | 201 | /* Functions */ 202 | Cache_Get_ICache_Line_Size = 0x400005fc; 203 | Cache_Get_Mode = 0x40000600; 204 | Cache_Address_Through_Cache = 0x40000604; 205 | ROM_Boot_Cache_Init = 0x40000608; 206 | MMU_Set_Page_Mode = 0x4000060c; 207 | MMU_Get_Page_Mode = 0x40000610; 208 | Cache_Invalidate_ICache_Items = 0x40000614; 209 | Cache_Op_Addr = 0x40000618; 210 | Cache_Invalidate_Addr = 0x4000061c; 211 | Cache_Invalidate_ICache_All = 0x40000620; 212 | Cache_Mask_All = 0x40000624; 213 | Cache_UnMask_Dram0 = 0x40000628; 214 | Cache_Suspend_ICache_Autoload = 0x4000062c; 215 | Cache_Resume_ICache_Autoload = 0x40000630; 216 | Cache_Start_ICache_Preload = 0x40000634; 217 | Cache_ICache_Preload_Done = 0x40000638; 218 | Cache_End_ICache_Preload = 0x4000063c; 219 | Cache_Config_ICache_Autoload = 0x40000640; 220 | Cache_Enable_ICache_Autoload = 0x40000644; 221 | Cache_Disable_ICache_Autoload = 0x40000648; 222 | Cache_Enable_ICache_PreLock = 0x4000064c; 223 | Cache_Disable_ICache_PreLock = 0x40000650; 224 | Cache_Lock_ICache_Items = 0x40000654; 225 | Cache_Unlock_ICache_Items = 0x40000658; 226 | Cache_Lock_Addr = 0x4000065c; 227 | Cache_Unlock_Addr = 0x40000660; 228 | Cache_Disable_ICache = 0x40000664; 229 | Cache_Enable_ICache = 0x40000668; 230 | Cache_Suspend_ICache = 0x4000066c; 231 | Cache_Resume_ICache = 0x40000670; 232 | Cache_Freeze_ICache_Enable = 0x40000674; 233 | Cache_Freeze_ICache_Disable = 0x40000678; 234 | Cache_Set_IDROM_MMU_Size = 0x4000067c; 235 | Cache_Get_IROM_MMU_End = 0x40000680; 236 | Cache_Get_DROM_MMU_End = 0x40000684; 237 | Cache_MMU_Init = 0x40000688; 238 | Cache_MSPI_MMU_Set = 0x4000068c; 239 | Cache_Travel_Tag_Memory = 0x40000690; 240 | Cache_Get_Virtual_Addr = 0x40000694; 241 | /* Data (.data, .bss, .rodata) */ 242 | rom_cache_op_cb = 0x4084ffcc; 243 | rom_cache_internal_table_ptr = 0x4084ffc8; 244 | 245 | 246 | /*************************************** 247 | Group clock 248 | ***************************************/ 249 | 250 | /* Functions */ 251 | ets_clk_get_xtal_freq = 0x40000698; 252 | ets_clk_get_cpu_freq = 0x4000069c; 253 | 254 | 255 | /*************************************** 256 | Group gpio 257 | ***************************************/ 258 | 259 | /* Functions */ 260 | gpio_input_get = 0x400006a0; 261 | gpio_matrix_in = 0x400006a4; 262 | gpio_matrix_out = 0x400006a8; 263 | gpio_output_disable = 0x400006ac; 264 | gpio_output_enable = 0x400006b0; 265 | gpio_output_set = 0x400006b4; 266 | gpio_pad_hold = 0x400006b8; 267 | gpio_pad_input_disable = 0x400006bc; 268 | gpio_pad_input_enable = 0x400006c0; 269 | gpio_pad_pulldown = 0x400006c4; 270 | gpio_pad_pullup = 0x400006c8; 271 | gpio_pad_select_gpio = 0x400006cc; 272 | gpio_pad_set_drv = 0x400006d0; 273 | gpio_pad_unhold = 0x400006d4; 274 | gpio_pin_wakeup_disable = 0x400006d8; 275 | gpio_pin_wakeup_enable = 0x400006dc; 276 | gpio_bypass_matrix_in = 0x400006e0; 277 | 278 | 279 | /*************************************** 280 | Group interrupts 281 | ***************************************/ 282 | 283 | /* Functions */ 284 | esprv_intc_int_set_priority = 0x400006e4; 285 | esprv_intc_int_set_threshold = 0x400006e8; 286 | esprv_intc_int_enable = 0x400006ec; 287 | esprv_intc_int_disable = 0x400006f0; 288 | esprv_intc_int_set_type = 0x400006f4; 289 | PROVIDE( intr_handler_set = 0x400006f8 ); 290 | intr_matrix_set = 0x400006fc; 291 | ets_intr_lock = 0x40000700; 292 | ets_intr_unlock = 0x40000704; 293 | ets_isr_attach = 0x40000708; 294 | ets_isr_mask = 0x4000070c; 295 | ets_isr_unmask = 0x40000710; 296 | 297 | 298 | /*************************************** 299 | Group crypto 300 | ***************************************/ 301 | 302 | /* Functions */ 303 | md5_vector = 0x40000714; 304 | MD5Init = 0x40000718; 305 | MD5Update = 0x4000071c; 306 | MD5Final = 0x40000720; 307 | crc32_le = 0x40000724; 308 | crc16_le = 0x40000728; 309 | crc8_le = 0x4000072c; 310 | crc32_be = 0x40000730; 311 | crc16_be = 0x40000734; 312 | crc8_be = 0x40000738; 313 | esp_crc8 = 0x4000073c; 314 | ets_sha_enable = 0x40000740; 315 | ets_sha_disable = 0x40000744; 316 | ets_sha_get_state = 0x40000748; 317 | ets_sha_init = 0x4000074c; 318 | ets_sha_process = 0x40000750; 319 | ets_sha_starts = 0x40000754; 320 | ets_sha_update = 0x40000758; 321 | ets_sha_finish = 0x4000075c; 322 | ets_sha_clone = 0x40000760; 323 | ets_hmac_enable = 0x40000764; 324 | ets_hmac_disable = 0x40000768; 325 | ets_hmac_calculate_message = 0x4000076c; 326 | ets_hmac_calculate_downstream = 0x40000770; 327 | ets_hmac_invalidate_downstream = 0x40000774; 328 | ets_jtag_enable_temporarily = 0x40000778; 329 | ets_aes_enable = 0x4000077c; 330 | ets_aes_disable = 0x40000780; 331 | ets_aes_setkey = 0x40000784; 332 | ets_aes_block = 0x40000788; 333 | ets_aes_setkey_dec = 0x4000078c; 334 | ets_aes_setkey_enc = 0x40000790; 335 | ets_bigint_enable = 0x40000794; 336 | ets_bigint_disable = 0x40000798; 337 | ets_bigint_multiply = 0x4000079c; 338 | ets_bigint_modmult = 0x400007a0; 339 | ets_bigint_modexp = 0x400007a4; 340 | ets_bigint_wait_finish = 0x400007a8; 341 | ets_bigint_getz = 0x400007ac; 342 | ets_ds_enable = 0x400007b0; 343 | ets_ds_disable = 0x400007b4; 344 | ets_ds_start_sign = 0x400007b8; 345 | ets_ds_is_busy = 0x400007bc; 346 | ets_ds_finish_sign = 0x400007c0; 347 | ets_ds_encrypt_params = 0x400007c4; 348 | ets_mgf1_sha256 = 0x400007c8; 349 | /* Data (.data, .bss, .rodata) */ 350 | crc32_le_table_ptr = 0x4001fff8; 351 | crc16_le_table_ptr = 0x4001fff4; 352 | crc8_le_table_ptr = 0x4001fff0; 353 | crc32_be_table_ptr = 0x4001ffec; 354 | crc16_be_table_ptr = 0x4001ffe8; 355 | crc8_be_table_ptr = 0x4001ffe4; 356 | 357 | 358 | /*************************************** 359 | Group efuse 360 | ***************************************/ 361 | 362 | /* Functions */ 363 | ets_efuse_read = 0x400007cc; 364 | ets_efuse_program = 0x400007d0; 365 | ets_efuse_clear_program_registers = 0x400007d4; 366 | ets_efuse_write_key = 0x400007d8; 367 | ets_efuse_get_read_register_address = 0x400007dc; 368 | ets_efuse_get_key_purpose = 0x400007e0; 369 | ets_efuse_key_block_unused = 0x400007e4; 370 | ets_efuse_find_unused_key_block = 0x400007e8; 371 | ets_efuse_rs_calculate = 0x400007ec; 372 | ets_efuse_count_unused_key_blocks = 0x400007f0; 373 | ets_efuse_secure_boot_enabled = 0x400007f4; 374 | ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400007f8; 375 | ets_efuse_cache_encryption_enabled = 0x400007fc; 376 | ets_efuse_download_modes_disabled = 0x40000800; 377 | ets_efuse_find_purpose = 0x40000804; 378 | ets_efuse_force_send_resume = 0x40000808; 379 | ets_efuse_get_flash_delay_us = 0x4000080c; 380 | ets_efuse_get_mac = 0x40000810; 381 | ets_efuse_get_uart_print_control = 0x40000814; 382 | ets_efuse_direct_boot_mode_disabled = 0x40000818; 383 | ets_efuse_security_download_modes_enabled = 0x4000081c; 384 | ets_efuse_jtag_disabled = 0x40000820; 385 | ets_efuse_usb_print_is_disabled = 0x40000824; 386 | ets_efuse_usb_download_mode_disabled = 0x40000828; 387 | ets_efuse_usb_device_disabled = 0x4000082c; 388 | ets_efuse_secure_boot_fast_wake_enabled = 0x40000830; 389 | 390 | 391 | /*************************************** 392 | Group secureboot 393 | ***************************************/ 394 | 395 | /* Functions */ 396 | ets_emsa_pss_verify = 0x40000834; 397 | ets_rsa_pss_verify = 0x40000838; 398 | ets_ecdsa_verify = 0x4000083c; 399 | ets_secure_boot_verify_bootloader_with_keys = 0x40000840; 400 | ets_secure_boot_verify_signature = 0x40000844; 401 | ets_secure_boot_read_key_digests = 0x40000848; 402 | ets_secure_boot_revoke_public_key_digest = 0x4000084c; 403 | 404 | 405 | /*************************************** 406 | Group usb_device_uart 407 | ***************************************/ 408 | 409 | /* Functions */ 410 | usb_serial_device_rx_one_char = 0x400009c0; 411 | usb_serial_device_rx_one_char_block = 0x400009c4; 412 | usb_serial_device_tx_flush = 0x400009c8; 413 | usb_serial_device_tx_one_char = 0x400009cc; -------------------------------------------------------------------------------- /ld/esp32s2.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | /* SRAM1 + 0x4000 cache + 0x400 vectors */ 3 | IRAM : ORIGIN = 0x4002C400, LENGTH = 0x10000 4 | } 5 | 6 | /** 7 | * ESP32-S2 ROM address table (except symbols from libgcc and libc) 8 | * Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796 9 | * 10 | * These are all weak symbols that could be overwritten in ESP-IDF. 11 | */ 12 | 13 | PROVIDE ( ets_efuse_get_spiconfig = 0x4000e4a0 ); 14 | PROVIDE ( s_cdcacm_old_rts = 0x3ffffd34 ); 15 | PROVIDE ( SelectSpiFunction = 0x40015d08 ); 16 | PROVIDE ( SelectSpiQIO = 0x40015b88 ); 17 | PROVIDE ( SendMsg = 0x40012d0c ); 18 | PROVIDE ( send_packet = 0x40012cc8 ); 19 | PROVIDE ( set_rtc_memory_crc = 0x40010010 ); 20 | PROVIDE ( SetSpiDrvs = 0x40015c18 ); 21 | PROVIDE ( sig_matrix = 0x3ffffd57 ); 22 | PROVIDE ( software_reset = 0x40010068 ); 23 | PROVIDE ( software_reset_cpu = 0x40010080 ); 24 | PROVIDE ( SPI_block_erase = 0x4001623c ); 25 | PROVIDE ( spi_cache_mode_switch = 0x40016a00 ); 26 | PROVIDE ( SPI_chip_erase = 0x400161b8 ); 27 | PROVIDE ( SPIClkConfig = 0x400170a0 ); 28 | PROVIDE ( SPI_Common_Command = 0x400162e8 ); 29 | PROVIDE ( spi_common_set_flash_cs_timing = 0x40016c0c ); 30 | PROVIDE ( spi_dummy_len_fix = 0x40015b50 ); 31 | PROVIDE ( SPI_Encrypt_Write = 0x400177e0 ); 32 | PROVIDE ( SPI_Encrypt_Write_Dest = 0x400176cc ); 33 | PROVIDE ( SPIEraseArea = 0x40017470 ); 34 | PROVIDE ( SPIEraseBlock = 0x4001710c ); 35 | PROVIDE ( SPIEraseChip = 0x400170ec ); 36 | PROVIDE ( SPIEraseSector = 0x4001716c ); 37 | PROVIDE ( esp_rom_spiflash_attach = 0x40017004 ); 38 | PROVIDE ( spi_flash_boot_attach = 0x40016fc0 ); 39 | PROVIDE ( spi_flash_check_suspend_cb = 0x3ffffd58 ); 40 | PROVIDE ( SPI_flashchip_data = 0x3ffffd3c ); 41 | PROVIDE ( spi_flash_set_check_suspend_cb = 0x40015b3c ); 42 | PROVIDE ( SPI_init = 0x40016ce8 ); 43 | PROVIDE ( SPILock = 0x40016ed4 ); 44 | PROVIDE ( SPIMasterReadModeCnfig = 0x40017014 ); 45 | PROVIDE ( SPI_page_program = 0x400165a8 ); 46 | PROVIDE ( SPIParamCfg = 0x40017500 ); 47 | PROVIDE ( SPIRead = 0x4001728c ); 48 | PROVIDE ( SPI_read_data = 0x40015ed8 ); 49 | PROVIDE ( SPIReadModeCnfig = 0x40016f1c ); 50 | PROVIDE ( SPI_read_status = 0x40016084 ); 51 | PROVIDE ( SPI_read_status_high = 0x40016284 ); 52 | PROVIDE ( SPI_sector_erase = 0x400161ec ); 53 | PROVIDE ( spi_slave_download = 0x4001998c ); 54 | PROVIDE ( spi_slave_rom_check_conn = 0x40019724 ); 55 | PROVIDE ( spi_slave_rom_init = 0x40019774 ); 56 | PROVIDE ( spi_slave_rom_init_hw = 0x40019b5c ); 57 | PROVIDE ( spi_slave_rom_intr_enable = 0x40019b3c ); 58 | PROVIDE ( spi_slave_rom_rxdma_load = 0x40019da8 ); 59 | PROVIDE ( spi_slave_rom_txdma_load = 0x40019e3c ); 60 | PROVIDE ( SPIUnlock = 0x40016e88 ); 61 | PROVIDE ( SPI_user_command_read = 0x40015fc8 ); 62 | PROVIDE ( SPI_Wait_Idle = 0x40016680 ); 63 | PROVIDE ( SPI_WakeUp = 0x400160f4 ); 64 | PROVIDE ( SPIWrite = 0x400171cc ); 65 | PROVIDE ( SPI_write_enable = 0x4001655c ); 66 | PROVIDE ( SPI_Write_Encrypt_Disable = 0x40017694 ); 67 | PROVIDE ( SPI_Write_Encrypt_Enable = 0x40017678 ); 68 | PROVIDE ( SPI_write_status = 0x400162a4 ); 69 | PROVIDE ( tdefl_compress = 0x400041dc ); 70 | PROVIDE ( tdefl_compress_buffer = 0x40004938 ); 71 | PROVIDE ( tdefl_compress_mem_to_mem = 0x40004a50 ); 72 | PROVIDE ( tdefl_compress_mem_to_output = 0x40004a30 ); 73 | PROVIDE ( tdefl_get_adler32 = 0x40004a28 ); 74 | PROVIDE ( tdefl_get_prev_return_status = 0x40004a20 ); 75 | PROVIDE ( tdefl_init = 0x40004954 ); 76 | PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x40004a64 ); 77 | PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40004a58 ); 78 | PROVIDE ( tinfl_decompress = 0x40003000 ); 79 | PROVIDE ( tinfl_decompress_mem_to_callback = 0x400041a8 ); 80 | PROVIDE ( tinfl_decompress_mem_to_mem = 0x40004168 ); 81 | 82 | PROVIDE ( uart_tx_one_char = 0x40012b10 ); 83 | 84 | /** 85 | * SPI flash driver function, compatibility names. 86 | */ 87 | 88 | PROVIDE ( g_rom_spiflash_dummy_len_plus = dummy_len_plus); 89 | PROVIDE ( g_ticks_per_us_pro = g_ticks_per_us ); 90 | PROVIDE ( g_rom_flashchip = SPI_flashchip_data ); 91 | PROVIDE ( g_rom_spiflash_chip = SPI_flashchip_data ); 92 | PROVIDE ( esp_rom_spiflash_config_param = SPIParamCfg ); 93 | PROVIDE ( esp_rom_spiflash_read = SPIRead ); 94 | PROVIDE ( esp_rom_spiflash_read_status = SPI_read_status ); 95 | PROVIDE ( esp_rom_spiflash_read_statushigh = SPI_read_status_high ); 96 | PROVIDE ( esp_rom_spiflash_read_user_cmd = SPI_user_command_read ); 97 | PROVIDE ( esp_rom_spiflash_write = SPIWrite ); 98 | PROVIDE ( esp_rom_spiflash_write_encrypted_disable = SPI_Write_Encrypt_Disable ); 99 | PROVIDE ( esp_rom_spiflash_write_encrypted_enable = SPI_Write_Encrypt_Enable ); 100 | PROVIDE ( esp_rom_spiflash_config_clk = SPIClkConfig ); 101 | PROVIDE ( esp_rom_spiflash_select_qio_pins = SelectSpiQIO ); 102 | PROVIDE ( esp_rom_spiflash_unlock = SPIUnlock ); 103 | PROVIDE ( esp_rom_spiflash_erase_chip = SPIEraseChip ); 104 | PROVIDE ( esp_rom_spiflash_erase_sector = SPIEraseSector ); 105 | PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock ); 106 | PROVIDE ( esp_rom_spiflash_wait_idle = SPI_Wait_Idle ); 107 | PROVIDE ( esp_rom_spiflash_config_readmode = SPIReadModeCnfig ); 108 | PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock ); 109 | PROVIDE ( esp_rom_spiflash_write_encrypted = SPI_Encrypt_Write ); 110 | PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); -------------------------------------------------------------------------------- /ld/esp32s3.x: -------------------------------------------------------------------------------- 1 | MEMORY { 2 | /* SRAM2 + 0x8400 */ 3 | IRAM : ORIGIN = 0x40380400, LENGTH = 0x10000 4 | } 5 | 6 | /* ROM function interface esp32s3.rom.ld for esp32s3 7 | * 8 | * 9 | * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b 10 | * 11 | * Compatible with ROM where ECO version equal or greater to 0. 12 | * 13 | * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 14 | */ 15 | 16 | PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); 17 | 18 | /*************************************** 19 | Group miniz 20 | ***************************************/ 21 | 22 | /* Functions */ 23 | mz_adler32 = 0x4000078c; 24 | mz_crc32 = 0x40000798; 25 | mz_free = 0x400007a4; 26 | tdefl_compress = 0x400007b0; 27 | tdefl_compress_buffer = 0x400007bc; 28 | tdefl_compress_mem_to_heap = 0x400007c8; 29 | tdefl_compress_mem_to_mem = 0x400007d4; 30 | tdefl_compress_mem_to_output = 0x400007e0; 31 | tdefl_get_adler32 = 0x400007ec; 32 | tdefl_get_prev_return_status = 0x400007f8; 33 | tdefl_init = 0x40000804; 34 | tdefl_write_image_to_png_file_in_memory = 0x40000810; 35 | tdefl_write_image_to_png_file_in_memory_ex = 0x4000081c; 36 | tinfl_decompress = 0x40000828; 37 | tinfl_decompress_mem_to_callback = 0x40000834; 38 | tinfl_decompress_mem_to_heap = 0x40000840; 39 | tinfl_decompress_mem_to_mem = 0x4000084c; 40 | 41 | /*************************************** 42 | Group opi_flash 43 | ***************************************/ 44 | 45 | /* Functions */ 46 | PROVIDE( opi_flash_set_lock_func = 0x40000870 ); 47 | PROVIDE( esp_rom_spi_cmd_config = 0x4000087c ); 48 | PROVIDE( esp_rom_spi_cmd_start = 0x40000888 ); 49 | PROVIDE( esp_rom_opiflash_pin_config = 0x40000894 ); 50 | PROVIDE( esp_rom_spi_set_op_mode = 0x400008a0 ); 51 | PROVIDE( esp_rom_opiflash_mode_reset = 0x400008ac ); 52 | PROVIDE( esp_rom_opiflash_exec_cmd = 0x400008b8 ); 53 | PROVIDE( esp_rom_opiflash_soft_reset = 0x400008c4 ); 54 | PROVIDE( esp_rom_opiflash_read_id = 0x400008d0 ); 55 | PROVIDE( esp_rom_opiflash_rdsr = 0x400008dc ); 56 | PROVIDE( esp_rom_opiflash_wait_idle = 0x400008e8 ); 57 | PROVIDE( esp_rom_opiflash_wren = 0x400008f4 ); 58 | PROVIDE( esp_rom_opiflash_erase_sector = 0x40000900 ); 59 | PROVIDE( esp_rom_opiflash_erase_block_64k = 0x4000090c ); 60 | PROVIDE( esp_rom_opiflash_erase_area = 0x40000918 ); 61 | PROVIDE( esp_rom_opiflash_read = 0x40000924 ); 62 | PROVIDE( esp_rom_opiflash_write = 0x40000930 ); 63 | PROVIDE( esp_rom_spi_set_dtr_swap_mode = 0x4000093c ); 64 | PROVIDE( esp_rom_opiflash_exit_continuous_read_mode = 0x40000948 ); 65 | PROVIDE( esp_rom_opiflash_legacy_driver_init = 0x40000954 ); 66 | PROVIDE( esp_rom_opiflash_read_raw = 0x4004d9d4); 67 | 68 | /*************************************** 69 | Group spiflash_legacy 70 | ***************************************/ 71 | 72 | /* Functions */ 73 | PROVIDE( esp_rom_spiflash_wait_idle = 0x40000960 ); 74 | PROVIDE( esp_rom_spiflash_write_encrypted = 0x4000096c ); 75 | PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000978 ); 76 | PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000984 ); 77 | PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000990 ); 78 | PROVIDE( esp_rom_spiflash_erase_chip = 0x4000099c ); 79 | PROVIDE( _esp_rom_spiflash_erase_sector = 0x400009a8 ); 80 | PROVIDE( _esp_rom_spiflash_erase_block = 0x400009b4 ); 81 | PROVIDE( _esp_rom_spiflash_write = 0x400009c0 ); 82 | PROVIDE( _esp_rom_spiflash_read = 0x400009cc ); 83 | PROVIDE( _esp_rom_spiflash_unlock = 0x400009d8 ); 84 | PROVIDE( _SPIEraseArea = 0x400009e4 ); 85 | PROVIDE( _SPI_write_enable = 0x400009f0 ); 86 | PROVIDE( esp_rom_spiflash_erase_sector = 0x400009fc ); 87 | PROVIDE( esp_rom_spiflash_erase_block = 0x40000a08 ); 88 | PROVIDE( esp_rom_spiflash_write = 0x40000a14 ); 89 | PROVIDE( esp_rom_spiflash_read = 0x40000a20 ); 90 | PROVIDE( esp_rom_spiflash_unlock = 0x40000a2c ); 91 | PROVIDE( SPIEraseArea = 0x40000a38 ); 92 | PROVIDE( SPI_write_enable = 0x40000a44 ); 93 | PROVIDE( esp_rom_spiflash_config_param = 0x40000a50 ); 94 | PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000a5c ); 95 | PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000a68 ); 96 | PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000a74 ); 97 | PROVIDE( esp_rom_spi_flash_send_resume = 0x40000a80 ); 98 | PROVIDE( esp_rom_spi_flash_update_id = 0x40000a8c ); 99 | PROVIDE( esp_rom_spiflash_config_clk = 0x40000a98 ); 100 | PROVIDE( esp_rom_spiflash_config_readmode = 0x40000aa4 ); 101 | PROVIDE( esp_rom_spiflash_read_status = 0x40000ab0 ); 102 | PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000abc ); 103 | PROVIDE( esp_rom_spiflash_write_status = 0x40000ac8 ); 104 | PROVIDE( esp_rom_opiflash_cache_mode_config = 0x40000ad4 ); 105 | PROVIDE( esp_rom_spiflash_auto_wait_idle = 0x40000ae0 ); 106 | PROVIDE( spi_flash_attach = 0x40000aec ); 107 | PROVIDE( spi_flash_get_chip_size = 0x40000af8 ); 108 | PROVIDE( spi_flash_guard_set = 0x40000b04 ); 109 | PROVIDE( spi_flash_guard_get = 0x40000b10 ); 110 | PROVIDE( spi_flash_write_config_set = 0x40000b1c ); 111 | PROVIDE( spi_flash_write_config_get = 0x40000b28 ); 112 | PROVIDE( spi_flash_safe_write_address_func_set = 0x40000b34 ); 113 | PROVIDE( spi_flash_unlock = 0x40000b40 ); 114 | PROVIDE( spi_flash_erase_range = 0x40000b4c ); 115 | PROVIDE( spi_flash_erase_sector = 0x40000b58 ); 116 | PROVIDE( spi_flash_write = 0x40000b64 ); 117 | PROVIDE( spi_flash_read = 0x40000b70 ); 118 | PROVIDE( spi_flash_write_encrypted = 0x40000b7c ); 119 | PROVIDE( spi_flash_read_encrypted = 0x40000b88 ); 120 | PROVIDE( spi_flash_mmap_os_func_set = 0x40000b94 ); 121 | PROVIDE( spi_flash_mmap_page_num_init = 0x40000ba0 ); 122 | PROVIDE( spi_flash_mmap = 0x40000bac ); 123 | PROVIDE( spi_flash_mmap_pages = 0x40000bb8 ); 124 | PROVIDE( spi_flash_munmap = 0x40000bc4 ); 125 | PROVIDE( spi_flash_mmap_dump = 0x40000bd0 ); 126 | PROVIDE( spi_flash_check_and_flush_cache = 0x40000bdc ); 127 | PROVIDE( spi_flash_mmap_get_free_pages = 0x40000be8 ); 128 | PROVIDE( spi_flash_cache2phys = 0x40000bf4 ); 129 | PROVIDE( spi_flash_phys2cache = 0x40000c00 ); 130 | PROVIDE( spi_flash_disable_cache = 0x40000c0c ); 131 | PROVIDE( spi_flash_restore_cache = 0x40000c18 ); 132 | PROVIDE( spi_flash_cache_enabled = 0x40000c24 ); 133 | PROVIDE( spi_flash_enable_cache = 0x40000c30 ); 134 | PROVIDE( spi_cache_mode_switch = 0x40000c3c ); 135 | PROVIDE( spi_common_set_dummy_output = 0x40000c48 ); 136 | PROVIDE( spi_common_set_flash_cs_timing = 0x40000c54 ); 137 | PROVIDE( esp_rom_spi_set_address_bit_len = 0x40000c60 ); 138 | PROVIDE( esp_enable_cache_flash_wrap = 0x40000c6c ); 139 | PROVIDE( SPILock = 0x40000c78 ); 140 | PROVIDE( SPIMasterReadModeCnfig = 0x40000c84 ); 141 | PROVIDE( SPI_Common_Command = 0x40000c90 ); 142 | PROVIDE( SPI_WakeUp = 0x40000c9c ); 143 | PROVIDE( SPI_block_erase = 0x40000ca8 ); 144 | PROVIDE( SPI_chip_erase = 0x40000cb4 ); 145 | PROVIDE( SPI_init = 0x40000cc0 ); 146 | PROVIDE( SPI_page_program = 0x40000ccc ); 147 | PROVIDE( SPI_read_data = 0x40000cd8 ); 148 | PROVIDE( SPI_sector_erase = 0x40000ce4 ); 149 | PROVIDE( SelectSpiFunction = 0x40000cf0 ); 150 | PROVIDE( SetSpiDrvs = 0x40000cfc ); 151 | PROVIDE( Wait_SPI_Idle = 0x40000d08 ); 152 | PROVIDE( spi_dummy_len_fix = 0x40000d14 ); 153 | PROVIDE( Disable_QMode = 0x40000d20 ); 154 | PROVIDE( Enable_QMode = 0x40000d2c ); 155 | 156 | 157 | /* Functions */ 158 | ets_efuse_get_spiconfig = 0x40001f74; -------------------------------------------------------------------------------- /ld/loader.x: -------------------------------------------------------------------------------- 1 | /* Shared loader, requires MEMORY definitions each chip */ 2 | 3 | SECTIONS { 4 | /* Section for code and readonly data, specified by flashloader standard. */ 5 | PrgCode : { 6 | . = ALIGN(4); 7 | 8 | /* The KEEP is necessary to ensure that the 9 | * sections don't get garbage collected by the linker. 10 | * 11 | * Because this is not a normal binary with an entry point, 12 | * the linker would just discard all the code without the 13 | * KEEP statement here. 14 | */ 15 | 16 | KEEP(*(.literal)) 17 | KEEP(*(.literal.*)) 18 | 19 | KEEP(*(.rodata)) 20 | KEEP(*(.rodata.*)) 21 | 22 | KEEP(*(.text)) 23 | KEEP(*(.text.*)) 24 | 25 | KEEP(*(.srodata .srodata.*)) 26 | 27 | *(.data .data.*) 28 | *(.sdata .sdata.*) 29 | 30 | *(.bss .bss.*) 31 | *(.sbss .sbss.*) 32 | 33 | . = ALIGN(4); 34 | } > IRAM 35 | 36 | /* Description of the flash algorithm */ 37 | DeviceData : { 38 | /* The device data content is only for external tools, 39 | * and usually not referenced by the code. 40 | * 41 | * The KEEP statement ensures it's not removed by accident. 42 | */ 43 | KEEP(*(DeviceData)) 44 | } > IRAM 45 | } 46 | -------------------------------------------------------------------------------- /src/api.rs: -------------------------------------------------------------------------------- 1 | /// Setup the device for the flashing process. 2 | #[no_mangle] 3 | pub unsafe extern "C" fn Init(adr: u32, clk: u32, fnc: u32) -> i32 { 4 | crate::Init_impl(adr, clk, fnc) 5 | } 6 | 7 | /// Erase the sector at the given address in flash 8 | /// 9 | /// Returns 0 on success, 1 on failure. 10 | #[no_mangle] 11 | pub unsafe extern "C" fn EraseSector(adr: u32) -> i32 { 12 | crate::EraseSector_impl(adr) 13 | } 14 | 15 | #[no_mangle] 16 | pub unsafe extern "C" fn EraseChip() -> i32 { 17 | crate::EraseChip_impl() 18 | } 19 | 20 | #[no_mangle] 21 | pub unsafe extern "C" fn ProgramPage(adr: u32, sz: u32, buf: *const u8) -> i32 { 22 | crate::ProgramPage_impl(adr, sz, buf) 23 | } 24 | 25 | #[no_mangle] 26 | pub unsafe extern "C" fn Verify(adr: u32, sz: u32, buf: *const u8) -> i32 { 27 | crate::Verify_impl(adr, sz, buf) 28 | } 29 | 30 | #[no_mangle] 31 | pub unsafe extern "C" fn ReadFlash(adr: u32, sz: u32, buf: *mut u8) -> i32 { 32 | crate::ReadFlash_impl(adr, sz, buf) 33 | } 34 | 35 | #[no_mangle] 36 | pub unsafe extern "C" fn UnInit(fnc: u32) -> i32 { 37 | crate::UnInit_impl(fnc) 38 | } 39 | -------------------------------------------------------------------------------- /src/api_xtensa.rs: -------------------------------------------------------------------------------- 1 | use core::arch::global_asm; 2 | 3 | // Probe-rs doesn't know how to call a function on the Xtensa architecture. Due to the windowed 4 | // ABI, just jumping to the function address won't work. Instead, we need to use a call 5 | // instruction, which will set up the window increment and then jump to the function address. 6 | 7 | #[cfg(feature = "esp32")] 8 | #[no_mangle] 9 | // End of SRAM2 10 | static STACK_PTR: u32 = 0x3FFE_0000; 11 | 12 | #[cfg(feature = "esp32s2")] 13 | #[no_mangle] 14 | // End of SRAM1. SRAM0 may be used as cache and thus may be inaccessible. 15 | static STACK_PTR: u32 = 0x3FFD_F000; 16 | 17 | #[cfg(feature = "esp32s3")] 18 | #[no_mangle] 19 | // End of SRAM1 - DATA_CACHE_SIZE 20 | static STACK_PTR: u32 = 0x3FCD_0000; 21 | 22 | global_asm!( 23 | " 24 | Init: 25 | .global Init_impl 26 | l32r a1, STACK_PTR 27 | mov.n a6, a2 28 | mov.n a7, a3 29 | mov.n a8, a4 30 | call4 Init_impl 31 | mov.n a2, a6 32 | break 1, 15 33 | 34 | EraseSector: 35 | .global EraseSector_impl 36 | l32r a1, STACK_PTR 37 | mov.n a6, a2 38 | call4 EraseSector_impl 39 | mov.n a2, a6 40 | break 1, 15 41 | 42 | EraseChip: 43 | .global EraseChip_impl 44 | l32r a1, STACK_PTR 45 | call4 EraseChip_impl 46 | mov.n a2, a6 47 | break 1, 15 48 | 49 | ProgramPage: 50 | .global ProgramPage_impl 51 | l32r a1, STACK_PTR 52 | mov.n a6, a2 53 | mov.n a7, a3 54 | mov.n a8, a4 55 | call4 ProgramPage_impl 56 | mov.n a2, a6 57 | break 1, 15 58 | 59 | Verify: 60 | .global Verify_impl 61 | l32r a1, STACK_PTR 62 | mov.n a6, a2 63 | mov.n a7, a3 64 | mov.n a8, a4 65 | call4 Verify_impl 66 | mov.n a2, a6 67 | break 1, 15 68 | 69 | ReadFlash: 70 | .global ReadFlash_impl 71 | l32r a1, STACK_PTR 72 | mov.n a6, a2 73 | mov.n a7, a3 74 | mov.n a8, a4 75 | call4 ReadFlash_impl 76 | mov.n a2, a6 77 | break 1, 15 78 | 79 | UnInit: 80 | .global UnInit_impl 81 | l32r a1, STACK_PTR 82 | mov.n a6, a2 83 | call4 UnInit_impl 84 | mov.n a2, a6 85 | break 1, 15 86 | " 87 | ); 88 | -------------------------------------------------------------------------------- /src/flash.rs: -------------------------------------------------------------------------------- 1 | extern "C" { 2 | 3 | // fn esp_rom_spiflash_write_encrypted_enable(); 4 | // fn esp_rom_spiflash_write_encrypted_disable(); 5 | // fn esp_rom_spiflash_write_encrypted(addr: u32, data: *const u8, len: u32); 6 | // fn esp_rom_spiflash_select_qio_pins(); 7 | // fn esp_rom_spi_flash_auto_sus_res(); 8 | // fn esp_rom_spi_flash_send_resume(); 9 | // fn esp_rom_spi_flash_update_id(); 10 | // fn esp_rom_spiflash_config_clk(); 11 | // fn esp_rom_spiflash_config_readmode(); 12 | // fn esp_rom_spiflash_read_status(/* esp_rom_spiflash_chip_t *spi ,*/ status: *mut u32); 13 | // fn esp_rom_spiflash_read_statushigh(/* esp_rom_spiflash_chip_t *spi ,*/ status: *mut u32); 14 | // fn esp_rom_spiflash_write_status(/* esp_rom_spiflash_chip_t *spi ,*/ status: *mut u32); 15 | 16 | fn esp_rom_spiflash_erase_chip() -> i32; 17 | fn esp_rom_spiflash_erase_block(block_number: u32) -> i32; 18 | // fn esp_rom_spiflash_erase_sector(sector_number: u32) -> i32; 19 | /// address (4 byte alignment), data, length 20 | fn esp_rom_spiflash_write(dest_addr: u32, data: *const u8, len: u32) -> i32; 21 | /// address (4 byte alignment), data, length 22 | fn esp_rom_spiflash_read(src_addr: u32, data: *mut u8, len: u32) -> i32; 23 | fn esp_rom_spiflash_read_user_cmd(status: *mut u32, cmd: u8) -> i32; 24 | // fn esp_rom_spiflash_unlock() -> i32; 25 | // fn esp_rom_spiflash_lock(); // can't find in idf defs? 26 | fn esp_rom_spiflash_attach(config: u32, legacy: bool); 27 | 28 | fn esp_rom_spiflash_config_param( 29 | device_id: u32, 30 | chip_size: u32, 31 | block_size: u32, 32 | sector_size: u32, 33 | page_size: u32, 34 | status_mask: u32, 35 | ) -> u32; 36 | 37 | #[cfg(any( 38 | feature = "esp32", 39 | feature = "esp32s2", 40 | feature = "esp32s3", 41 | feature = "esp32c3", 42 | ))] 43 | fn ets_efuse_get_spiconfig() -> u32; 44 | } 45 | 46 | pub fn attach() -> i32 { 47 | #[cfg(any( 48 | feature = "esp32", 49 | feature = "esp32s2", 50 | feature = "esp32s3", 51 | feature = "esp32c3", 52 | ))] 53 | let spiconfig = unsafe { ets_efuse_get_spiconfig() }; 54 | 55 | #[cfg(any(feature = "esp32c2", feature = "esp32c6", feature = "esp32h2"))] 56 | let spiconfig = 0; 57 | 58 | // TODO: raise CPU frequency 59 | 60 | let config_result = unsafe { 61 | esp_rom_spiflash_config_param( 62 | 0, 63 | crate::properties::FLASH_SIZE, // total_size 64 | crate::properties::FLASH_BLOCK_SIZE, // block_size 65 | crate::properties::FLASH_SECTOR_SIZE, // sector_size 66 | crate::properties::PAGE_SIZE, // page_size 67 | crate::properties::FLASH_STATUS_MASK, // status_mask 68 | ) 69 | }; 70 | 71 | if config_result == 0 { 72 | unsafe { esp_rom_spiflash_attach(spiconfig, false) }; 73 | 0 74 | } else { 75 | -1 76 | } 77 | } 78 | 79 | pub fn erase_block(adr: u32) -> i32 { 80 | crate::dprintln!("ERASE @ {}", adr); 81 | 82 | unsafe { esp_rom_spiflash_erase_block(adr / crate::properties::FLASH_BLOCK_SIZE) } 83 | } 84 | 85 | pub fn erase_chip() -> i32 { 86 | unsafe { esp_rom_spiflash_erase_chip() } 87 | } 88 | 89 | pub fn write_flash(address: u32, data: &[u8]) -> i32 { 90 | if data.is_empty() { 91 | return 0; 92 | } 93 | let len = data.len() as u32; 94 | unsafe { esp_rom_spiflash_write(address, data.as_ptr(), len) } 95 | } 96 | 97 | pub fn read_flash(address: u32, data: &mut [u8]) -> i32 { 98 | if data.is_empty() { 99 | return 0; 100 | } 101 | let len = data.len() as u32; 102 | unsafe { esp_rom_spiflash_read(address, data.as_mut_ptr(), len) } 103 | } 104 | 105 | pub fn wait_for_idle() -> i32 { 106 | const SR_WIP: u32 = 1 << 0; 107 | 108 | let mut status = SR_WIP; 109 | while status & SR_WIP != 0 { 110 | let res = unsafe { esp_rom_spiflash_read_user_cmd(&mut status, 0x05) }; 111 | if res != 0 { 112 | return res; 113 | } 114 | } 115 | 116 | 0 117 | } 118 | -------------------------------------------------------------------------------- /src/main.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | #![cfg_attr( 4 | target_arch = "xtensa", 5 | feature(asm_experimental_arch, naked_functions) 6 | )] 7 | 8 | // Target memory configuration 9 | 10 | // Decompressor is 43776 bytes, reserve more in case compiler changes layout 11 | const _: [u8; 43776] = [0; core::mem::size_of::()]; 12 | 13 | // Placement: 14 | // - Xtensa: Pin stack top first, calculate backwards: 15 | // - 32K stack 16 | // - 32K for data pages 17 | // - 64K for decompressor state 18 | // - RISC-V: At the end of memory, calculate backwards: 19 | // - 64K for data pages (32K needed, but 64K is easier to calculate) 20 | // - 64K for decompressor state 21 | // - stack comes automatically after the loader 22 | 23 | // Xtensa | Image IRAM | Image DRAM | STATE_ADDR | data_load_addr | Stack (top) 24 | // -------- | ----------- | ----------- | ----------- | -------------- | ----------- 25 | // ESP32 | 0x4009_0000 | - | 0x3FFC_0000 | 0x3FFD_0000 | 0x3FFE_0000 26 | // ESP32-S2 | 0x4002_C400 | 0x3FFB_C400 | 0x3FFB_E000 | 0x3FFC_E000 | 0x3FFD_F000 27 | // ESP32-S3 | 0x4038_0400 | 0x3FC9_0400 | 0x3FCB_0000 | 0x3FCC_0000 | 0x3FCD_0000 28 | 29 | // RISC-V | Image IRAM | Image DRAM | STATE_ADDR | data_load_addr | DRAM end (avoiding cache) 30 | // -------- | ----------- | ----------- | ----------- | -------------- | ----------- 31 | // ESP32-C2 | 0x4038_C000 | 0x3FCA_C000 | 0x3FCB_0000 | 0x3FCC_0000 | 0x3FCD_0000 32 | // ESP32-C3 | 0x4039_0000 | 0x3FC1_0000 | 0x3FCB_0000 | 0x3FCC_0000 | 0x3FCD_0000 33 | // ESP32-C6 | 0x4081_0000 | 0x4081_0000 | 0x4084_0000 | 0x4085_0000 | 0x4086_0000 34 | // ESP32-H2 | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000 | 0x4083_8000 !! has smaller RAM, only reserve 32K for data 35 | 36 | // "State" base address 37 | #[cfg(feature = "esp32")] 38 | const STATE_ADDR: usize = 0x3FFC_0000; 39 | #[cfg(feature = "esp32s2")] 40 | const STATE_ADDR: usize = 0x3FFB_E000; 41 | #[cfg(feature = "esp32s3")] 42 | const STATE_ADDR: usize = 0x3FCB_0000; 43 | #[cfg(feature = "esp32c2")] 44 | const STATE_ADDR: usize = 0x3FCB_0000; 45 | #[cfg(feature = "esp32c3")] 46 | const STATE_ADDR: usize = 0x3FCB_0000; 47 | #[cfg(feature = "esp32c6")] 48 | const STATE_ADDR: usize = 0x4086_0000; 49 | #[cfg(feature = "esp32h2")] 50 | const STATE_ADDR: usize = 0x4082_0000; 51 | 52 | // End of target memory configuration 53 | 54 | // Define necessary functions for flash loader 55 | // 56 | // These are taken from the [ARM CMSIS-Pack documentation] 57 | // 58 | // [ARM CMSIS-Pack documentation]: https://arm-software.github.io/CMSIS_5/Pack/html/algorithmFunc.html 59 | 60 | use panic_never as _; 61 | 62 | use crate::tinfl::{ 63 | OutBuffer, TinflDecompressor, TINFL_STATUS_DONE, TINFL_STATUS_NEEDS_MORE_INPUT, 64 | }; 65 | 66 | #[cfg_attr(any(target_arch = "xtensa"), path = "api_xtensa.rs")] 67 | mod api; 68 | mod flash; 69 | mod properties; 70 | mod tinfl; 71 | 72 | #[cfg(not(any(target_arch = "xtensa", target_arch = "riscv32")))] 73 | compile_error!("specify the target with `--target`"); 74 | 75 | const ERROR_BASE_INTERNAL: i32 = -1000; 76 | const ERROR_BASE_TINFL: i32 = -2000; 77 | const ERROR_BASE_FLASH: i32 = -4000; 78 | 79 | #[cfg(feature = "log")] 80 | mod log { 81 | 82 | extern "C" { 83 | fn uart_tx_one_char(byte: u8); 84 | } 85 | 86 | use ufmt::uWrite; 87 | pub struct Uart; 88 | 89 | impl uWrite for Uart { 90 | type Error = (); 91 | fn write_str(&mut self, s: &str) -> Result<(), ()> { 92 | for &b in s.as_bytes() { 93 | unsafe { uart_tx_one_char(b) }; 94 | } 95 | Ok(()) 96 | } 97 | } 98 | } 99 | 100 | #[cfg(feature = "log")] 101 | #[macro_export] 102 | macro_rules! dprintln { 103 | () => { 104 | ufmt::uwriteln!(crate::log::Uart, "").ok() 105 | }; 106 | ($fmt:literal) => { 107 | ufmt::uwriteln!(crate::log::Uart, $fmt).ok() 108 | }; 109 | ($fmt:literal, $($arg:tt)*) => { 110 | ufmt::uwriteln!(crate::log::Uart, $fmt, $($arg)*).ok() 111 | }; 112 | } 113 | 114 | #[cfg(not(feature = "log"))] 115 | #[macro_export] 116 | macro_rules! dprintln { 117 | () => {}; 118 | ($fmt:expr) => {}; 119 | ($fmt:expr, $($arg:tt)*) => {}; 120 | } 121 | 122 | const INITED_MAGIC: u32 = 0xAAC0FFEE; 123 | const INITED: *mut u32 = STATE_ADDR as *mut u32; 124 | const DECOMPRESSOR: *mut Decompressor = (STATE_ADDR + 4) as *mut Decompressor; 125 | 126 | fn is_inited() -> bool { 127 | unsafe { *INITED == INITED_MAGIC } 128 | } 129 | 130 | /// Setup the device for the flashing process. 131 | #[no_mangle] 132 | pub unsafe extern "C" fn Init_impl(_adr: u32, _clk: u32, _fnc: u32) -> i32 { 133 | dprintln!("INIT"); 134 | 135 | if flash::attach() == 0 { 136 | *DECOMPRESSOR = Decompressor::new(); 137 | *INITED = INITED_MAGIC; 138 | 0 139 | } else { 140 | 1 141 | } 142 | } 143 | 144 | /// Erase the sector at the given address in flash 145 | /// 146 | /// Returns 0 on success, 1 on failure. 147 | #[no_mangle] 148 | pub unsafe extern "C" fn EraseSector_impl(adr: u32) -> i32 { 149 | if !is_inited() { 150 | return ERROR_BASE_INTERNAL - 1; 151 | }; 152 | flash::erase_block(adr) 153 | } 154 | 155 | #[no_mangle] 156 | pub unsafe extern "C" fn EraseChip_impl() -> i32 { 157 | if !is_inited() { 158 | return ERROR_BASE_INTERNAL - 1; 159 | }; 160 | flash::erase_chip() 161 | } 162 | 163 | #[no_mangle] 164 | pub unsafe extern "C" fn ProgramPage_impl(adr: u32, sz: u32, buf: *const u8) -> i32 { 165 | if !is_inited() { 166 | return ERROR_BASE_INTERNAL - 1; 167 | }; 168 | 169 | if (buf as u32) % 4 != 0 { 170 | dprintln!("ERROR buf not word aligned"); 171 | return ERROR_BASE_INTERNAL - 5; 172 | } 173 | 174 | dprintln!("PROGRAM {} bytes @ {}", sz, adr); 175 | 176 | let input = core::slice::from_raw_parts(buf, sz as usize); 177 | 178 | (*DECOMPRESSOR).program(adr, input) 179 | } 180 | 181 | #[no_mangle] 182 | pub unsafe extern "C" fn Verify_impl(adr: u32, sz: u32, buf: *const u8) -> i32 { 183 | if !is_inited() { 184 | return ERROR_BASE_INTERNAL - 1; 185 | }; 186 | 187 | if (buf as u32) % 4 != 0 { 188 | dprintln!("ERROR buf not word aligned"); 189 | return ERROR_BASE_INTERNAL - 5; 190 | } 191 | 192 | dprintln!("PROGRAM {} bytes @ {}", sz, adr); 193 | 194 | let input = core::slice::from_raw_parts(buf, sz as usize); 195 | 196 | (*DECOMPRESSOR).verify(adr, input) 197 | } 198 | 199 | #[no_mangle] 200 | pub unsafe extern "C" fn ReadFlash_impl(adr: u32, sz: u32, buf: *mut u8) -> i32 { 201 | if !is_inited() { 202 | return ERROR_BASE_INTERNAL - 1; 203 | }; 204 | 205 | if (buf as u32) % 4 != 0 { 206 | dprintln!("ERROR buf not word aligned"); 207 | return ERROR_BASE_INTERNAL - 5; 208 | } 209 | 210 | dprintln!("READ FLASH {} bytes @ {}", sz, adr); 211 | 212 | let buf = core::slice::from_raw_parts_mut(buf, sz as usize); 213 | crate::flash::read_flash(adr, buf) 214 | } 215 | 216 | #[no_mangle] 217 | pub unsafe extern "C" fn UnInit_impl(fnc: u32) -> i32 { 218 | if !is_inited() { 219 | return ERROR_BASE_INTERNAL - 1; 220 | }; 221 | 222 | *INITED = 0; 223 | 224 | if fnc == 2 { 225 | // The flash ROM functions don't wait for the end of the last operation. 226 | flash::wait_for_idle() 227 | } else { 228 | 0 229 | } 230 | } 231 | 232 | pub struct Decompressor { 233 | decompressor: TinflDecompressor, 234 | output: OutBuffer, 235 | image_start: u32, 236 | offset: u32, 237 | remaining_compressed: usize, 238 | } 239 | 240 | impl Decompressor { 241 | pub fn new() -> Self { 242 | Self { 243 | image_start: 0xFFFF_FFFF, 244 | offset: 0, 245 | output: OutBuffer::new(), 246 | remaining_compressed: 0, 247 | decompressor: TinflDecompressor::new(), 248 | } 249 | } 250 | 251 | fn reinit(&mut self, address: u32, compressed: u32) { 252 | self.image_start = address; 253 | self.offset = 0; 254 | 255 | self.remaining_compressed = compressed as usize; 256 | 257 | self.decompressor = TinflDecompressor::new(); 258 | self.output.take(|_| {}); 259 | } 260 | 261 | fn decompress(&mut self, input: &[u8], process: fn(u32, &[u8]) -> i32) -> i32 { 262 | if self.remaining_compressed == 0 { 263 | return ERROR_BASE_INTERNAL - 3; 264 | } 265 | 266 | // We may have to cut off some padding bytes. 267 | let chunk_len = self.remaining_compressed.min(input.len()); 268 | self.remaining_compressed -= chunk_len; 269 | 270 | // Signal tinfl_decompress() that this is the last chunk 271 | let last = self.remaining_compressed == 0; 272 | 273 | // Iterate through all the input 274 | let mut input = &input[..chunk_len]; 275 | let mut status = TINFL_STATUS_NEEDS_MORE_INPUT as i32; 276 | while !input.is_empty() && status > TINFL_STATUS_DONE as i32 { 277 | status = self 278 | .decompressor 279 | .decompress(&mut input, &mut self.output, last); 280 | 281 | if status == TINFL_STATUS_DONE as i32 || self.output.full() { 282 | // We're either finished or the decompressor can't continue 283 | // until we flush the buffer. 284 | let flush_status = self.flush(process); 285 | 286 | if flush_status < 0 { 287 | return ERROR_BASE_FLASH + flush_status; 288 | } 289 | } 290 | } 291 | 292 | if status < TINFL_STATUS_DONE as i32 { 293 | ERROR_BASE_TINFL + status 294 | } else { 295 | 0 296 | } 297 | } 298 | 299 | pub fn flush(&mut self, process: fn(address: u32, data: &[u8]) -> i32) -> i32 { 300 | let mut offset = self.offset; 301 | let address = self.image_start + offset; 302 | 303 | // Take buffer contents, write to flash and update offset. 304 | let status = self.output.take(|data| { 305 | offset += data.len() as u32; 306 | 307 | process(address, data) 308 | }); 309 | 310 | self.offset = offset; 311 | 312 | status 313 | } 314 | 315 | fn handle_compressed( 316 | &mut self, 317 | address: u32, 318 | mut data: &[u8], 319 | process: fn(u32, &[u8]) -> i32, 320 | ) -> i32 { 321 | if self.image_start != address { 322 | if data.len() < 4 { 323 | // We don't have enough bytes to read the length 324 | return ERROR_BASE_INTERNAL - 4; 325 | } 326 | 327 | // Image length is prepended to the first chunk, cut it off. 328 | let (length_bytes, remaining) = data.split_at(4); 329 | data = remaining; 330 | 331 | let compressed_length = u32::from_le_bytes([ 332 | length_bytes[0], 333 | length_bytes[1], 334 | length_bytes[2], 335 | length_bytes[3], 336 | ]); 337 | 338 | self.reinit(address, compressed_length); 339 | } 340 | self.decompress(data, process) 341 | } 342 | 343 | pub fn program(&mut self, address: u32, data: &[u8]) -> i32 { 344 | self.handle_compressed(address, data, write_to_flash) 345 | } 346 | 347 | pub fn verify(&mut self, address: u32, data: &[u8]) -> i32 { 348 | // We're supposed to return the address up to which we've verified. 349 | // However, we process compressed data and the caller expects us to respond in terms of 350 | // compressed offsets, so we don't actually know where comparison fails. 351 | let status = if self.handle_compressed(address, data, verify_flash) == 0 { 352 | address + data.len() as u32 353 | } else { 354 | address 355 | }; 356 | 357 | status as i32 358 | } 359 | } 360 | 361 | fn write_to_flash(address: u32, data: &[u8]) -> i32 { 362 | let status = crate::flash::write_flash(address, data); 363 | 364 | if status < 0 { 365 | return ERROR_BASE_FLASH + status; 366 | } 367 | 368 | 0 369 | } 370 | 371 | fn verify_flash(mut address: u32, mut data: &[u8]) -> i32 { 372 | const READBACK_BUFFER: usize = 256; 373 | let mut readback = unsafe { 374 | let mut buf = core::mem::MaybeUninit::<[u8; READBACK_BUFFER]>::uninit(); 375 | for i in 0..READBACK_BUFFER { 376 | buf.as_mut_ptr().cast::().write_volatile(i as u8); 377 | } 378 | buf.assume_init() 379 | }; 380 | 381 | while !data.is_empty() { 382 | let chunk_size = READBACK_BUFFER.min(data.len()); 383 | let (slice, rest) = unsafe { 384 | // SAFETY: skip is always at most `data.len()` 385 | data.split_at_unchecked(chunk_size) 386 | }; 387 | data = rest; 388 | 389 | let readback_slice = &mut readback[..chunk_size]; 390 | 391 | let status = crate::flash::read_flash(address, readback_slice); 392 | if status < 0 { 393 | return -1; 394 | } 395 | 396 | for (a, b) in slice.iter().zip(readback_slice.iter()) { 397 | if a != b { 398 | return -1; 399 | } 400 | } 401 | 402 | address += chunk_size as u32; 403 | } 404 | 405 | 0 406 | } 407 | -------------------------------------------------------------------------------- /src/properties.rs: -------------------------------------------------------------------------------- 1 | // esptool uses 16k for the buffer 2 | pub const PAGE_SIZE: u32 = 0x4000; 3 | pub const FLASH_BLOCK_SIZE: u32 = 65536; 4 | 5 | #[cfg(any( 6 | feature = "esp32", 7 | feature = "esp32c2", 8 | feature = "esp32c3", 9 | feature = "esp32c6", 10 | feature = "esp32h2" 11 | ))] 12 | // Max of 16MB 13 | pub const FLASH_SIZE: u32 = 0x1000000; 14 | 15 | #[cfg(any(feature = "esp32s2", feature = "esp32s3"))] 16 | // Max of 1GB 17 | pub const FLASH_SIZE: u32 = 0x40000000; 18 | 19 | pub const FLASH_STATUS_MASK: u32 = 0xFFFF; 20 | pub const FLASH_SECTOR_SIZE: u32 = 4096; 21 | 22 | #[allow(non_upper_case_globals)] 23 | #[no_mangle] 24 | #[used] 25 | #[link_section = "DeviceData"] 26 | pub static FlashDevice: FlashDeviceDescription = FlashDeviceDescription { 27 | vers: 0x0001, 28 | dev_name: [0u8; 128], 29 | dev_type: 5, 30 | dev_addr: 0x0, 31 | device_size: FLASH_SIZE, 32 | page_size: PAGE_SIZE, 33 | _reserved: 0, 34 | empty: 0xFF, 35 | program_time_out: 1000, 36 | erase_time_out: 2000, 37 | flash_sectors: sectors(), 38 | }; 39 | 40 | const fn sectors() -> [FlashSector; 512] { 41 | const SECTOR_END: FlashSector = FlashSector { 42 | size: 0xffff_ffff, 43 | address: 0xffff_ffff, 44 | }; 45 | 46 | let mut sectors = [FlashSector::default(); 512]; 47 | 48 | sectors[0] = FlashSector { 49 | size: FLASH_BLOCK_SIZE, 50 | address: 0x0, 51 | }; 52 | sectors[1] = SECTOR_END; 53 | 54 | sectors 55 | } 56 | 57 | #[repr(C)] 58 | pub struct FlashDeviceDescription { 59 | vers: u16, 60 | dev_name: [u8; 128], 61 | dev_type: u16, 62 | dev_addr: u32, 63 | device_size: u32, 64 | page_size: u32, 65 | _reserved: u32, 66 | empty: u8, 67 | program_time_out: u32, 68 | erase_time_out: u32, 69 | flash_sectors: [FlashSector; 512], 70 | } 71 | 72 | #[repr(C)] 73 | #[derive(Copy, Clone)] 74 | struct FlashSector { 75 | size: u32, 76 | address: u32, 77 | } 78 | 79 | impl FlashSector { 80 | const fn default() -> Self { 81 | FlashSector { 82 | size: 0, 83 | address: 0, 84 | } 85 | } 86 | } 87 | -------------------------------------------------------------------------------- /src/tinfl.rs: -------------------------------------------------------------------------------- 1 | use core::mem::MaybeUninit; 2 | 3 | use crate::ERROR_BASE_INTERNAL; 4 | 5 | extern "C" { 6 | /// Main low-level decompressor coroutine function. This is the only function actually needed 7 | /// for decompression. All the other functions are just high-level helpers for improved 8 | /// usability. 9 | /// This is a universal API, i.e. it can be used as a building block to build any desired higher 10 | /// level decompression API. In the limit case, it can be called once per every byte input or 11 | /// output. 12 | fn tinfl_decompress( 13 | decompressor: *mut TinflDecompressor, 14 | next_in: *const u8, 15 | in_bytes: *mut usize, 16 | out_buf_start: *mut u8, 17 | next_out: *mut u8, 18 | out_bytes: *mut usize, 19 | flags: u32, 20 | ) -> TinflStatus; 21 | } 22 | 23 | type TinflStatus = i8; 24 | // const TINFL_STATUS_FAILED_CANNOT_MAKE_PROGRESS: TinflStatus = -4; 25 | // const TINFL_STATUS_BAD_PARAM: TinflStatus = -3; 26 | // const TINFL_STATUS_ADLER32_MISMATCH: TinflStatus = -2; 27 | // const TINFL_STATUS_FAILED: TinflStatus = -1; 28 | pub const TINFL_STATUS_DONE: TinflStatus = 0; 29 | pub const TINFL_STATUS_NEEDS_MORE_INPUT: TinflStatus = 1; 30 | // const TINFL_STATUS_HAS_MORE_OUTPUT: TinflStatus = 2; 31 | 32 | const TINFL_MAX_HUFF_SYMBOLS_0: usize = 288; 33 | const TINFL_MAX_HUFF_TABLES: usize = 3; 34 | const TINFL_MAX_HUFF_SYMBOLS_1: usize = 32; 35 | const TINFL_FAST_LOOKUP_BITS: usize = 10; 36 | const TINFL_FAST_LOOKUP_SIZE: usize = 1 << TINFL_FAST_LOOKUP_BITS; 37 | 38 | // Decompression flags used by tinfl_decompress(). 39 | 40 | /// If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib 41 | /// stream). Otherwise, the input is a raw deflate stream. 42 | const TINFL_FLAG_PARSE_ZLIB_HEADER: u32 = 1; 43 | 44 | /// If set, there are more input bytes available beyond the end of the supplied input buffer. 45 | /// If clear, the input buffer contains all remaining input. 46 | const TINFL_FLAG_HAS_MORE_INPUT: u32 = 2; 47 | 48 | /// If set, the output buffer is large enough to hold the entire decompressed stream. 49 | /// If clear, the output buffer is at least the size of the dictionary (typically 32KB). 50 | // const TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: u32 = 4; 51 | 52 | /// Force adler-32 checksum computation of the decompressed bytes. 53 | // const TINFL_FLAG_COMPUTE_ADLER32: u32 = 8; 54 | 55 | #[repr(C)] 56 | struct TinflHuffTable { 57 | m_code_size: [u8; TINFL_MAX_HUFF_SYMBOLS_0], 58 | m_look_up: [u16; TINFL_FAST_LOOKUP_SIZE], 59 | m_tree: [u16; TINFL_MAX_HUFF_SYMBOLS_0 * 2], 60 | } 61 | 62 | #[repr(C)] 63 | pub struct TinflDecompressor { 64 | m_state: u32, 65 | m_num_bits: u32, 66 | m_zhdr0: u32, 67 | m_zhdr1: u32, 68 | m_z_adler32: u32, 69 | m_final: u32, 70 | m_type: u32, 71 | m_check_adler32: u32, 72 | m_dist: u32, 73 | m_counter: u32, 74 | m_num_extra: u32, 75 | m_table_sizes: [u32; TINFL_MAX_HUFF_TABLES], 76 | m_bit_buf: u32, 77 | m_dist_from_out_buf_start: usize, 78 | m_tables: [TinflHuffTable; TINFL_MAX_HUFF_TABLES], 79 | m_raw_header: [u8; 4], 80 | m_len_codes: [u8; TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137], 81 | } 82 | 83 | impl TinflDecompressor { 84 | pub fn new() -> Self { 85 | unsafe { 86 | let mut this = MaybeUninit::::uninit(); 87 | (*this.as_mut_ptr()).m_state = 0; 88 | this.assume_init() 89 | } 90 | } 91 | } 92 | 93 | pub struct OutBuffer { 94 | buffer: MaybeUninit<[u8; 32768]>, 95 | len: usize, 96 | } 97 | 98 | impl OutBuffer { 99 | pub const fn new() -> Self { 100 | Self { 101 | buffer: MaybeUninit::uninit(), 102 | len: 0, 103 | } 104 | } 105 | 106 | fn space(&self) -> usize { 107 | unsafe { self.buffer.assume_init() }.len() - self.len 108 | } 109 | 110 | unsafe fn pointers(&mut self) -> (*mut u8, *mut u8) { 111 | let write_idx = self.len; 112 | let start = core::ptr::addr_of_mut!(self.buffer).cast(); 113 | 114 | (start, start.add(write_idx)) 115 | } 116 | 117 | pub fn full(&self) -> bool { 118 | self.space() == 0 119 | } 120 | 121 | pub fn take(&mut self, out: impl FnOnce(&[u8]) -> R) -> R { 122 | let data = unsafe { 123 | // self.len is always <= self.buffer.len() 124 | let len = core::mem::take(&mut self.len); 125 | self.buffer.assume_init_mut().get_unchecked(..len) 126 | }; 127 | 128 | out(data) 129 | } 130 | } 131 | 132 | impl TinflDecompressor { 133 | pub fn decompress(&mut self, input: &mut &[u8], out: &mut OutBuffer, last: bool) -> i32 { 134 | let flags = if last { 135 | TINFL_FLAG_PARSE_ZLIB_HEADER 136 | } else { 137 | TINFL_FLAG_PARSE_ZLIB_HEADER | TINFL_FLAG_HAS_MORE_INPUT 138 | }; 139 | 140 | let mut in_bytes = input.len(); 141 | let data_buf = input.as_ptr(); 142 | 143 | let mut out_bytes = out.space(); 144 | let (out_buf, next_out) = unsafe { out.pointers() }; 145 | 146 | let status = unsafe { 147 | tinfl_decompress( 148 | self, 149 | data_buf, 150 | &mut in_bytes, 151 | out_buf, 152 | next_out, 153 | &mut out_bytes, 154 | flags, 155 | ) 156 | } as i32; 157 | 158 | if in_bytes > input.len() { 159 | // tinfl_decompress() shouldn't have consumed more bytes than we gave it 160 | // but let's not trust it 161 | return ERROR_BASE_INTERNAL - 2; 162 | } 163 | 164 | // Consume processed input 165 | *input = &input[in_bytes..]; 166 | 167 | // Update output buffer 168 | out.len += out_bytes; 169 | 170 | status 171 | } 172 | } 173 | --------------------------------------------------------------------------------