├── .github └── workflows │ └── ci.yml ├── .gitignore ├── Cargo.toml ├── LICENSE-APACHE ├── LICENSE-MIT ├── README.md ├── build.rs ├── examples └── empty.rs ├── rustfmt.toml └── src └── lib.rs /.github/workflows/ci.yml: -------------------------------------------------------------------------------- 1 | name: CI 2 | 3 | on: 4 | pull_request: 5 | branches: 6 | - main 7 | push: 8 | workflow_dispatch: 9 | 10 | env: 11 | CARGO_TERM_COLOR: always 12 | 13 | jobs: 14 | # -------------------------------------------------------------------------- 15 | # Check 16 | 17 | check: 18 | runs-on: ubuntu-latest 19 | 20 | steps: 21 | - uses: actions/checkout@v3 22 | - uses: dtolnay/rust-toolchain@v1 23 | with: 24 | toolchain: nightly 25 | components: rust-src 26 | - uses: Swatinem/rust-cache@v2 27 | 28 | - name: check 29 | run: cargo check --target=riscv32imc-unknown-none-elf -Zbuild-std=core 30 | - name: check examples 31 | run: cargo check --target=riscv32imc-unknown-none-elf -Zbuild-std=core --examples 32 | 33 | # -------------------------------------------------------------------------- 34 | # Lint 35 | 36 | clippy: 37 | runs-on: ubuntu-latest 38 | 39 | steps: 40 | - uses: actions/checkout@v3 41 | - uses: dtolnay/rust-toolchain@v1 42 | with: 43 | toolchain: nightly 44 | components: clippy 45 | - uses: Swatinem/rust-cache@v2 46 | 47 | - name: clippy 48 | run: cargo clippy -- -D warnings -A clippy::missing_safety_doc 49 | 50 | rustfmt: 51 | runs-on: ubuntu-latest 52 | 53 | steps: 54 | - uses: actions/checkout@v3 55 | - uses: dtolnay/rust-toolchain@v1 56 | with: 57 | toolchain: nightly 58 | components: rustfmt 59 | - uses: Swatinem/rust-cache@v2 60 | 61 | - name: rustfmt 62 | run: cargo fmt -- --check 63 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Generated by Cargo 2 | # will have compiled files and executables 3 | debug/ 4 | target/ 5 | 6 | # Remove Cargo.lock from gitignore if creating an executable, leave it for libraries 7 | # More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html 8 | Cargo.lock 9 | 10 | # These are backup files generated by rustfmt 11 | **/*.rs.bk 12 | 13 | # MSVC Windows builds of rustc generate these, which store debugging information 14 | *.pdb 15 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "esp-riscv-rt" 3 | version = "0.3.0" 4 | edition = "2021" 5 | rust-version = "1.60" 6 | description = "Minimal runtime / startup for RISC-V CPUs from Espressif" 7 | repository = "https://github.com/esp-rs/esp-riscv-rt" 8 | license = "MIT OR Apache-2.0" 9 | keywords = ["esp32", "riscv", "runtime", "startup"] 10 | categories = ["embedded", "no-std"] 11 | 12 | [dependencies] 13 | riscv = "0.10.1" 14 | riscv-rt-macros = "0.2.0" 15 | 16 | [dev-dependencies] 17 | panic-halt = "0.2.0" 18 | 19 | [features] 20 | has-mie-mip = [] 21 | zero-bss = [] 22 | zero-rtc-fast-bss = [] 23 | init-data = [] 24 | init-rw-text = [] 25 | init-rtc-fast-data = [] 26 | init-rtc-fast-text = [] 27 | -------------------------------------------------------------------------------- /LICENSE-APACHE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright 2022 esp-rs 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /LICENSE-MIT: -------------------------------------------------------------------------------- 1 | Copyright 2023 esp-rs 2 | 3 | Permission is hereby granted, free of charge, to any 4 | person obtaining a copy of this software and associated 5 | documentation files (the "Software"), to deal in the 6 | Software without restriction, including without 7 | limitation the rights to use, copy, modify, merge, 8 | publish, distribute, sublicense, and/or sell copies of 9 | the Software, and to permit persons to whom the Software 10 | is furnished to do so, subject to the following 11 | conditions: 12 | 13 | The above copyright notice and this permission notice 14 | shall be included in all copies or substantial portions 15 | of the Software. 16 | 17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF 18 | ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 19 | TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 20 | PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT 21 | SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 22 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR 24 | IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 | DEALINGS IN THE SOFTWARE. 26 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # esp-riscv-rt 2 | 3 | --- 4 | 5 | ## This project has moved! It can now be found in the [esp-rs/esp-hal](https://github.com/esp-rs/esp-hal/tree/main/esp-riscv-rt) mono repository. 6 | 7 | --- 8 | 9 | [![Crates.io](https://img.shields.io/crates/v/esp-riscv-rt?color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-riscv-rt) 10 | [![docs.rs](https://img.shields.io/docsrs/esp-riscv-rt?color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-riscv-rt) 11 | ![MSRV](https://img.shields.io/badge/MSRV-1.60-blue?style=flat-square) 12 | ![Crates.io](https://img.shields.io/crates/l/esp-riscv-rt?style=flat-square) 13 | 14 | > Minimal runtime / startup for RISC-V CPUs from Espressif. 15 | 16 | Much of the code in this repository originated in the [rust-embedded/riscv-rt](https://github.com/rust-embedded/riscv-rt) repository. 17 | 18 | ## [Documentation](https://docs.rs/crate/esp-riscv-rt) 19 | 20 | ## Minimum Supported Rust Version (MSRV) 21 | 22 | This crate is guaranteed to compile on stable Rust 1.60 and up. It _might_ 23 | compile with older versions but that may change in any new patch release. 24 | 25 | ## License 26 | 27 | Licensed under either of: 28 | 29 | - Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0) 30 | - MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT) 31 | 32 | at your option. 33 | 34 | ### Contribution 35 | 36 | Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in 37 | the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without 38 | any additional terms or conditions. 39 | -------------------------------------------------------------------------------- /build.rs: -------------------------------------------------------------------------------- 1 | use std::{env, path::PathBuf}; 2 | 3 | fn main() { 4 | let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); 5 | println!("cargo:rustc-link-search={}", out_dir.display()); 6 | } 7 | -------------------------------------------------------------------------------- /examples/empty.rs: -------------------------------------------------------------------------------- 1 | #![no_std] 2 | #![no_main] 3 | 4 | use panic_halt as _; 5 | 6 | #[esp_riscv_rt::entry] 7 | fn main() -> ! { 8 | // do something here 9 | loop {} 10 | } 11 | -------------------------------------------------------------------------------- /rustfmt.toml: -------------------------------------------------------------------------------- 1 | # Comments 2 | format_code_in_doc_comments = true 3 | normalize_comments = true 4 | wrap_comments = true 5 | 6 | # Imports 7 | group_imports = "StdExternalCrate" 8 | imports_granularity = "Crate" 9 | imports_layout = "HorizontalVertical" 10 | -------------------------------------------------------------------------------- /src/lib.rs: -------------------------------------------------------------------------------- 1 | //! Minimal startup / runtime for RISC-V CPUs from Espressif 2 | //! 3 | //! # Minimum Supported Rust Version (MSRV) 4 | //! 5 | //! This crate is guaranteed to compile on stable Rust 1.60 and up. It *might* 6 | //! compile with older versions but that may change in any new patch release. 7 | //! 8 | //! # Features 9 | //! 10 | //! This crate provides: 11 | //! 12 | //! - Before main initialization of the `.bss` and `.data` sections controlled 13 | //! by features 14 | //! - `#[entry]` to declare the entry point of the program 15 | 16 | // NOTE: Adapted from riscv-rt/src/lib.rs 17 | #![no_std] 18 | 19 | use core::arch::global_asm; 20 | 21 | pub use riscv; 22 | use riscv::register::{ 23 | mcause, 24 | mtvec::{self, TrapMode}, 25 | }; 26 | pub use riscv_rt_macros::{entry, pre_init}; 27 | 28 | pub use self::Interrupt as interrupt; 29 | 30 | #[export_name = "error: esp-riscv-rt appears more than once in the dependency graph"] 31 | #[doc(hidden)] 32 | pub static __ONCE__: () = (); 33 | 34 | extern "C" { 35 | // Boundaries of the .bss section 36 | static mut _bss_end: u32; 37 | static mut _bss_start: u32; 38 | 39 | // Boundaries of the .data section 40 | static mut _data_end: u32; 41 | static mut _data_start: u32; 42 | 43 | // Initial values of the .data section (stored in Flash) 44 | static _sidata: u32; 45 | } 46 | 47 | /// Rust entry point (_start_rust) 48 | /// 49 | /// Zeros bss section, initializes data section and calls main. This function 50 | /// never returns. 51 | #[link_section = ".init.rust"] 52 | #[export_name = "_start_rust"] 53 | pub unsafe extern "C" fn start_rust(a0: usize, a1: usize, a2: usize) -> ! { 54 | extern "Rust" { 55 | // This symbol will be provided by the user via `#[entry]` 56 | fn main(a0: usize, a1: usize, a2: usize) -> !; 57 | 58 | fn __post_init(); 59 | 60 | fn _setup_interrupts(); 61 | 62 | } 63 | 64 | __post_init(); 65 | 66 | _setup_interrupts(); 67 | 68 | main(a0, a1, a2); 69 | } 70 | 71 | /// Registers saved in trap handler 72 | #[allow(missing_docs)] 73 | #[derive(Debug, Default, Clone, Copy)] 74 | #[repr(C)] 75 | pub struct TrapFrame { 76 | pub ra: usize, 77 | pub t0: usize, 78 | pub t1: usize, 79 | pub t2: usize, 80 | pub t3: usize, 81 | pub t4: usize, 82 | pub t5: usize, 83 | pub t6: usize, 84 | pub a0: usize, 85 | pub a1: usize, 86 | pub a2: usize, 87 | pub a3: usize, 88 | pub a4: usize, 89 | pub a5: usize, 90 | pub a6: usize, 91 | pub a7: usize, 92 | pub s0: usize, 93 | pub s1: usize, 94 | pub s2: usize, 95 | pub s3: usize, 96 | pub s4: usize, 97 | pub s5: usize, 98 | pub s6: usize, 99 | pub s7: usize, 100 | pub s8: usize, 101 | pub s9: usize, 102 | pub s10: usize, 103 | pub s11: usize, 104 | pub gp: usize, 105 | pub tp: usize, 106 | pub sp: usize, 107 | pub pc: usize, 108 | pub mstatus: usize, 109 | pub mcause: usize, 110 | pub mtval: usize, 111 | } 112 | 113 | /// Trap entry point rust (_start_trap_rust) 114 | /// 115 | /// `scause`/`mcause` is read to determine the cause of the trap. XLEN-1 bit 116 | /// indicates if it's an interrupt or an exception. The result is examined and 117 | /// ExceptionHandler or one of the core interrupt handlers is called. 118 | #[link_section = ".trap.rust"] 119 | #[export_name = "_start_trap_rust"] 120 | pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) { 121 | extern "C" { 122 | fn ExceptionHandler(trap_frame: &TrapFrame); 123 | fn DefaultHandler(); 124 | } 125 | 126 | unsafe { 127 | let cause = mcause::read(); 128 | 129 | if cause.is_exception() { 130 | ExceptionHandler(&*trap_frame) 131 | } else if cause.code() < __INTERRUPTS.len() { 132 | let h = &__INTERRUPTS[cause.code()]; 133 | if h.reserved == 0 { 134 | DefaultHandler(); 135 | } else { 136 | (h.handler)(); 137 | } 138 | } else { 139 | DefaultHandler(); 140 | } 141 | } 142 | } 143 | 144 | #[doc(hidden)] 145 | #[no_mangle] 146 | #[allow(unused_variables, non_snake_case)] 147 | pub fn DefaultExceptionHandler(trap_frame: &TrapFrame) -> ! { 148 | loop { 149 | // Prevent this from turning into a UDF instruction 150 | // see rust-lang/rust#28728 for details 151 | continue; 152 | } 153 | } 154 | 155 | #[doc(hidden)] 156 | #[no_mangle] 157 | #[allow(unused_variables, non_snake_case)] 158 | pub fn DefaultInterruptHandler() { 159 | loop { 160 | // Prevent this from turning into a UDF instruction 161 | // see rust-lang/rust#28728 for details 162 | continue; 163 | } 164 | } 165 | 166 | // Interrupts 167 | #[doc(hidden)] 168 | pub enum Interrupt { 169 | UserSoft, 170 | SupervisorSoft, 171 | MachineSoft, 172 | UserTimer, 173 | SupervisorTimer, 174 | MachineTimer, 175 | UserExternal, 176 | SupervisorExternal, 177 | MachineExternal, 178 | } 179 | 180 | extern "C" { 181 | fn UserSoft(); 182 | fn SupervisorSoft(); 183 | fn MachineSoft(); 184 | fn UserTimer(); 185 | fn SupervisorTimer(); 186 | fn MachineTimer(); 187 | fn UserExternal(); 188 | fn SupervisorExternal(); 189 | fn MachineExternal(); 190 | } 191 | 192 | #[doc(hidden)] 193 | pub union Vector { 194 | pub handler: unsafe extern "C" fn(), 195 | pub reserved: usize, 196 | } 197 | 198 | #[doc(hidden)] 199 | #[no_mangle] 200 | pub static __INTERRUPTS: [Vector; 12] = [ 201 | Vector { handler: UserSoft }, 202 | Vector { 203 | handler: SupervisorSoft, 204 | }, 205 | Vector { reserved: 0 }, 206 | Vector { 207 | handler: MachineSoft, 208 | }, 209 | Vector { handler: UserTimer }, 210 | Vector { 211 | handler: SupervisorTimer, 212 | }, 213 | Vector { reserved: 0 }, 214 | Vector { 215 | handler: MachineTimer, 216 | }, 217 | Vector { 218 | handler: UserExternal, 219 | }, 220 | Vector { 221 | handler: SupervisorExternal, 222 | }, 223 | Vector { reserved: 0 }, 224 | Vector { 225 | handler: MachineExternal, 226 | }, 227 | ]; 228 | 229 | #[doc(hidden)] 230 | #[no_mangle] 231 | #[rustfmt::skip] 232 | pub unsafe extern "Rust" fn default_post_init() {} 233 | 234 | /// Default implementation of `_setup_interrupts` that sets `mtvec`/`stvec` to a 235 | /// trap handler address. 236 | #[doc(hidden)] 237 | #[no_mangle] 238 | #[rustfmt::skip] 239 | pub unsafe extern "Rust" fn default_setup_interrupts() { 240 | extern "C" { 241 | fn _start_trap(); 242 | } 243 | 244 | mtvec::write(_start_trap as usize, TrapMode::Direct); 245 | } 246 | 247 | /// Parse cfg attributes inside a global_asm call. 248 | macro_rules! cfg_global_asm { 249 | {@inner, [$($x:tt)*], } => { 250 | global_asm!{$($x)*} 251 | }; 252 | (@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => { 253 | #[cfg($meta)] 254 | cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*} 255 | #[cfg(not($meta))] 256 | cfg_global_asm!{@inner, [$($x)*], $($rest)*} 257 | }; 258 | {@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => { 259 | cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*} 260 | }; 261 | {$($asms:tt)*} => { 262 | cfg_global_asm!{@inner, [], $($asms)*} 263 | }; 264 | } 265 | 266 | cfg_global_asm! { 267 | r#" 268 | /* 269 | Entry point of all programs (_start). 270 | 271 | It initializes DWARF call frame information, the stack pointer, the 272 | frame pointer (needed for closures to work in start_rust) and the global 273 | pointer. Then it calls _start_rust. 274 | */ 275 | 276 | .section .init, "ax" 277 | .global _start 278 | 279 | _start: 280 | /* Jump to the absolute address defined by the linker script. */ 281 | lui ra, %hi(_abs_start) 282 | jr %lo(_abs_start)(ra) 283 | 284 | _abs_start: 285 | .option norelax 286 | .cfi_startproc 287 | .cfi_undefined ra 288 | "#, 289 | #[cfg(feature = "has-mie-mip")] 290 | r#" 291 | csrw mie, 0 292 | csrw mip, 0 293 | "#, 294 | #[cfg(feature = "zero-bss")] 295 | r#" 296 | la a0, _bss_start 297 | la a1, _bss_end 298 | mv a3, x0 299 | 1: 300 | sw a3, 0(a0) 301 | addi a0, a0, 4 302 | blt a0, a1, 1b 303 | "#, 304 | #[cfg(feature = "zero-rtc-fast-bss")] 305 | r#" 306 | la a0, _rtc_fast_bss_start 307 | la a1, _rtc_fast_bss_end 308 | mv a3, x0 309 | 1: 310 | sw a3, 0(a0) 311 | addi a0, a0, 4 312 | blt a0, a1, 1b 313 | "#, 314 | #[cfg(feature = "init-data")] 315 | r#" 316 | la a0, _data_start 317 | la a1, _data_end 318 | la a2, _sidata 319 | 1: 320 | lw a3, 0(a2) 321 | sw a3, 0(a0) 322 | addi a0, a0, 4 323 | addi a2, a2, 4 324 | blt a0, a1, 1b 325 | "#, 326 | #[cfg(feature = "init-rw-text")] 327 | r#" 328 | la a0, _srwtext 329 | la a1, _erwtext 330 | la a2, _irwtext 331 | 1: 332 | lw a3, 0(a2) 333 | sw a3, 0(a0) 334 | addi a0, a0, 4 335 | addi a2, a2, 4 336 | blt a0, a1, 1b 337 | "#, 338 | #[cfg(feature = "init-rtc-fast-data")] 339 | r#" 340 | la a0, _rtc_fast_data_start 341 | la a1, _rtc_fast_data_end 342 | la a2, _irtc_fast_data 343 | 1: 344 | lw a3, 0(a2) 345 | sw a3, 0(a0) 346 | addi a0, a0, 4 347 | addi a2, a2, 4 348 | blt a0, a1, 1b 349 | "#, 350 | #[cfg(feature = "init-rtc-fast-text")] 351 | r#" 352 | la a0, _srtc_fast_text 353 | la a1, _ertc_fast_text 354 | la a2, _irtc_fast_text 355 | 1: 356 | lw a3, 0(a2) 357 | sw a3, 0(a0) 358 | addi a0, a0, 4 359 | addi a2, a2, 4 360 | blt a0, a1, 1b 361 | "#, 362 | r#" 363 | li x1, 0 364 | li x2, 0 365 | li x3, 0 366 | li x4, 0 367 | li x5, 0 368 | li x6, 0 369 | li x7, 0 370 | li x8, 0 371 | li x9, 0 372 | li x10,0 373 | li x11,0 374 | li x12,0 375 | li x13,0 376 | li x14,0 377 | li x15,0 378 | li x16,0 379 | li x17,0 380 | li x18,0 381 | li x19,0 382 | li x20,0 383 | li x21,0 384 | li x22,0 385 | li x23,0 386 | li x24,0 387 | li x25,0 388 | li x26,0 389 | li x27,0 390 | li x28,0 391 | li x29,0 392 | li x30,0 393 | li x31,0 394 | 395 | .option push 396 | .option norelax 397 | la gp, __global_pointer$ 398 | .option pop 399 | 400 | // Check hart ID 401 | csrr t2, mhartid 402 | lui t0, %hi(_max_hart_id) 403 | add t0, t0, %lo(_max_hart_id) 404 | bgtu t2, t0, abort 405 | 406 | // Allocate stacks 407 | la sp, _stack_start 408 | lui t0, %hi(_hart_stack_size) 409 | add t0, t0, %lo(_hart_stack_size) 410 | 411 | beqz t2, 2f // Jump if single-hart 412 | mv t1, t2 413 | mv t3, t0 414 | 1: 415 | add t0, t0, t3 416 | addi t1, t1, -1 417 | bnez t1, 1b 418 | 2: 419 | sub sp, sp, t0 420 | 421 | // Set frame pointer 422 | add s0, sp, zero 423 | 424 | jal zero, _start_rust 425 | 426 | .cfi_endproc 427 | 428 | /* 429 | Trap entry points (_start_trap, _start_trapN for N in 1..=31) 430 | 431 | The default implementation saves all registers to the stack and calls 432 | _start_trap_rust, then restores all saved registers before `mret` 433 | */ 434 | .section .trap, "ax" 435 | .weak _start_trap 436 | .weak _start_trap1 437 | .weak _start_trap2 438 | .weak _start_trap3 439 | .weak _start_trap4 440 | .weak _start_trap5 441 | .weak _start_trap6 442 | .weak _start_trap7 443 | .weak _start_trap8 444 | .weak _start_trap9 445 | .weak _start_trap10 446 | .weak _start_trap11 447 | .weak _start_trap12 448 | .weak _start_trap13 449 | .weak _start_trap14 450 | .weak _start_trap15 451 | .weak _start_trap16 452 | .weak _start_trap17 453 | .weak _start_trap18 454 | .weak _start_trap19 455 | .weak _start_trap20 456 | .weak _start_trap21 457 | .weak _start_trap22 458 | .weak _start_trap23 459 | .weak _start_trap24 460 | .weak _start_trap25 461 | .weak _start_trap26 462 | .weak _start_trap27 463 | .weak _start_trap28 464 | .weak _start_trap29 465 | .weak _start_trap30 466 | .weak _start_trap31 467 | 468 | _start_trap1: 469 | _start_trap2: 470 | _start_trap3: 471 | _start_trap4: 472 | _start_trap5: 473 | _start_trap6: 474 | _start_trap7: 475 | _start_trap8: 476 | _start_trap9: 477 | _start_trap10: 478 | _start_trap11: 479 | _start_trap12: 480 | _start_trap13: 481 | _start_trap14: 482 | _start_trap15: 483 | _start_trap16: 484 | _start_trap17: 485 | _start_trap18: 486 | _start_trap19: 487 | _start_trap20: 488 | _start_trap21: 489 | _start_trap22: 490 | _start_trap23: 491 | _start_trap24: 492 | _start_trap25: 493 | _start_trap26: 494 | _start_trap27: 495 | _start_trap28: 496 | _start_trap29: 497 | _start_trap30: 498 | _start_trap31: 499 | 500 | _start_trap: 501 | addi sp, sp, -40*4 502 | 503 | sw ra, 0*4(sp) 504 | sw t0, 1*4(sp) 505 | sw t1, 2*4(sp) 506 | sw t2, 3*4(sp) 507 | sw t3, 4*4(sp) 508 | sw t4, 5*4(sp) 509 | sw t5, 6*4(sp) 510 | sw t6, 7*4(sp) 511 | sw a0, 8*4(sp) 512 | sw a1, 9*4(sp) 513 | sw a2, 10*4(sp) 514 | sw a3, 11*4(sp) 515 | sw a4, 12*4(sp) 516 | sw a5, 13*4(sp) 517 | sw a6, 14*4(sp) 518 | sw a7, 15*4(sp) 519 | sw s0, 16*4(sp) 520 | sw s1, 17*4(sp) 521 | sw s2, 18*4(sp) 522 | sw s3, 19*4(sp) 523 | sw s4, 20*4(sp) 524 | sw s5, 21*4(sp) 525 | sw s6, 22*4(sp) 526 | sw s7, 23*4(sp) 527 | sw s8, 24*4(sp) 528 | sw s9, 25*4(sp) 529 | sw s10, 26*4(sp) 530 | sw s11, 27*4(sp) 531 | sw gp, 28*4(sp) 532 | sw tp, 29*4(sp) 533 | csrrs t1, mepc, x0 534 | sw t1, 31*4(sp) 535 | csrrs t1, mstatus, x0 536 | sw t1, 32*4(sp) 537 | csrrs t1, mcause, x0 538 | sw t1, 33*4(sp) 539 | csrrs t1, mtval, x0 540 | sw t1, 34*4(sp) 541 | 542 | addi s0, sp, 40*4 543 | sw s0, 30*4(sp) 544 | 545 | add a0, sp, zero 546 | jal ra, _start_trap_rust_hal 547 | 548 | lw t1, 31*4(sp) 549 | csrrw x0, mepc, t1 550 | 551 | lw t1, 32*4(sp) 552 | csrrw x0, mstatus, t1 553 | 554 | lw ra, 0*4(sp) 555 | lw t0, 1*4(sp) 556 | lw t1, 2*4(sp) 557 | lw t2, 3*4(sp) 558 | lw t3, 4*4(sp) 559 | lw t4, 5*4(sp) 560 | lw t5, 6*4(sp) 561 | lw t6, 7*4(sp) 562 | lw a0, 8*4(sp) 563 | lw a1, 9*4(sp) 564 | lw a2, 10*4(sp) 565 | lw a3, 11*4(sp) 566 | lw a4, 12*4(sp) 567 | lw a5, 13*4(sp) 568 | lw a6, 14*4(sp) 569 | lw a7, 15*4(sp) 570 | lw s0, 16*4(sp) 571 | lw s1, 17*4(sp) 572 | lw s2, 18*4(sp) 573 | lw s3, 19*4(sp) 574 | lw s4, 20*4(sp) 575 | lw s5, 21*4(sp) 576 | lw s6, 22*4(sp) 577 | lw s7, 23*4(sp) 578 | lw s8, 24*4(sp) 579 | lw s9, 25*4(sp) 580 | lw s10, 26*4(sp) 581 | lw s11, 27*4(sp) 582 | lw gp, 28*4(sp) 583 | lw tp, 29*4(sp) 584 | lw sp, 30*4(sp) 585 | 586 | # SP was restored from the original SP 587 | mret 588 | 589 | /* Make sure there is an abort when linking */ 590 | .section .text.abort 591 | .globl abort 592 | abort: 593 | j abort 594 | 595 | /* 596 | Interrupt vector table (_vector_table) 597 | */ 598 | 599 | .section .trap, "ax" 600 | .weak _vector_table 601 | .type _vector_table, @function 602 | 603 | .option push 604 | .balign 0x100 605 | .option norelax 606 | .option norvc 607 | 608 | _vector_table: 609 | j _start_trap 610 | j _start_trap1 611 | j _start_trap2 612 | j _start_trap3 613 | j _start_trap4 614 | j _start_trap5 615 | j _start_trap6 616 | j _start_trap7 617 | j _start_trap8 618 | j _start_trap9 619 | j _start_trap10 620 | j _start_trap11 621 | j _start_trap12 622 | j _start_trap13 623 | j _start_trap14 624 | j _start_trap15 625 | j _start_trap16 626 | j _start_trap17 627 | j _start_trap18 628 | j _start_trap19 629 | j _start_trap20 630 | j _start_trap21 631 | j _start_trap22 632 | j _start_trap23 633 | j _start_trap24 634 | j _start_trap25 635 | j _start_trap26 636 | j _start_trap27 637 | j _start_trap28 638 | j _start_trap29 639 | j _start_trap30 640 | j _start_trap31 641 | 642 | .option pop 643 | "#, 644 | } 645 | --------------------------------------------------------------------------------