├── .github ├── FUNDING.yml ├── ISSUE_TEMPLATE │ ├── bug_report.md │ └── feature_request.md └── workflows │ └── main.yml ├── README.md ├── Si5351Arduino.code-workspace ├── examples ├── si5351_calibration │ └── si5351_calibration.ino ├── si5351_clk67_example │ └── si5351_clk67_example.ino ├── si5351_example │ └── si5351_example.ino ├── si5351_ext_ref │ └── si5351_ext_ref.ino ├── si5351_outputs │ └── si5351_outputs.ino ├── si5351_phase │ └── si5351_phase.ino ├── si5351_sweeper │ └── si5351_sweeper.ino └── si5351_vcxo │ └── si5351_vcxo.ino ├── keywords.txt ├── library.json ├── library.properties ├── licence.txt └── src ├── si5351.cpp └── si5351.h /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | # These are supported funding model platforms 2 | 3 | custom: ['https://paypal.me/NT7S'] 4 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug_report.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Bug report 3 | about: Create a report to help us improve 4 | title: '' 5 | labels: '' 6 | assignees: '' 7 | 8 | --- 9 | 10 | **Describe the bug** 11 | A clear and concise description of what the bug is. 12 | 13 | **To Reproduce** 14 | Steps to reproduce the behavior: 15 | 1. Go to '...' 16 | 2. Click on '....' 17 | 3. Scroll down to '....' 18 | 4. See error 19 | 20 | **Expected behavior** 21 | A clear and concise description of what you expected to happen. 22 | 23 | **Screenshots** 24 | If applicable, add screenshots to help explain your problem. 25 | 26 | **Desktop (please complete the following information):** 27 | - OS: [e.g. iOS] 28 | - Browser [e.g. chrome, safari] 29 | - Version [e.g. 22] 30 | 31 | **Smartphone (please complete the following information):** 32 | - Device: [e.g. iPhone6] 33 | - OS: [e.g. iOS8.1] 34 | - Browser [e.g. stock browser, safari] 35 | - Version [e.g. 22] 36 | 37 | **Additional context** 38 | Add any other context about the problem here. 39 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/feature_request.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Feature request 3 | about: Suggest an idea for this project 4 | title: '' 5 | labels: '' 6 | assignees: '' 7 | 8 | --- 9 | 10 | **Is your feature request related to a problem? Please describe.** 11 | A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] 12 | 13 | **Describe the solution you'd like** 14 | A clear and concise description of what you want to happen. 15 | 16 | **Describe alternatives you've considered** 17 | A clear and concise description of any alternative solutions or features you've considered. 18 | 19 | **Additional context** 20 | Add any other context or screenshots about the feature request here. 21 | -------------------------------------------------------------------------------- /.github/workflows/main.yml: -------------------------------------------------------------------------------- 1 | on: [push, pull_request] 2 | jobs: 3 | lint: 4 | runs-on: ubuntu-latest 5 | steps: 6 | - uses: actions/checkout@v4 7 | - uses: arduino/arduino-lint-action@v2 8 | with: 9 | library-manager: update 10 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Si5351 Library for Arduino 2 | ========================== 3 | This is a library for the Si5351 series of clock generator ICs from [Silicon Labs](http://www.silabs.com) for the Arduino development environment. It will allow you to control the Si5351 with an Arduino, and without depending on the proprietary ClockBuilder software from Silicon Labs. 4 | 5 | This library is focused towards usage in RF/amateur radio applications, but it may be useful in other cases. However, keep in mind that coding decisions are and will be made with those applications in mind first, so if you need something a bit different, please do fork this repository. 6 | 7 | **Please feel free to use the Issues feature of GitHub if you run into problems or have suggestions for important features to implement. This is the best way to get in touch.** 8 | 9 | Thanks For Your Support! 10 | ------------------------ 11 | If you would like to support my library development efforts, I would ask that you please consider purchasing a Si5351A Breakout Board from my [online store at etherkit.com](https://www.etherkit.com) sending a [one-time PayPal tip](https://paypal.me/NT7S), or [subscribe to me on Substack](https://nt7s.substack.com) for an ongoing contribution. Thank you! 12 | 13 | Library Installation 14 | --------------------- 15 | The best way to install the library is via the Arduino Library Manager, which is available if you are using Arduino IDE version 1.6.2 or greater. To install it this way, simply go to the menu Sketch > Include Library > Manage Libraries..., and then in the search box at the upper-right, type "Etherkit Si5351". Click on the entry in the list below, then click on the provided "Install" button. By installing the library this way, you will always have notifications of future library updates, and can easily switch between library versions. 16 | 17 | If you need to or would like to install the library in the old way, then you can download a copy of the library in a ZIP file. Download a ZIP file of the library from the GitHub repository by using the "Download ZIP" button at the right of the main repository page. Extract the ZIP file, then rename the unzipped folder as "Si5351". Finally, open the Arduino IDE, select menu Sketch > Import Library... > Add Library..., and select the renamed folder that you just downloaded. Restart the IDE and you should have access to the new library. 18 | 19 | Hardware Requirements and Setup 20 | ------------------------------- 21 | This library has been written for the Arduino platform and has been successfully tested on the Arduino Uno and an Uno clone. There should be no reason that it would not work on any other Arduino hardware with I2C support. 22 | 23 | The Si5351 is a +3.3 V only part, so if you are not using a +3.3 V microcontroller, be sure you have some kind of level conversion strategy. 24 | 25 | Wire the SDA and SCL pins of the Si5351 to the corresponding pins on the Arduino. Use the pin assignments posted on the [Arduino Wire library page](http://arduino.cc/en/Reference/Wire). Since the I2C interface is set to 100 kHz, use 1 to 10 kΩ pullup resistors from +3.3 V to the SDA and SCL lines. 26 | 27 | Connect a 25 MHz or 27 MHz crystal with a load capacitance of 6, 8, or 10 pF to the Si5351 XA and XB pins. Locate the crystal as close to the Si5351 as possible and keep the traces as short as possible. Please use a SMT crystal. A crystal with leads will have too much stray capacitance. 28 | 29 | Changes from v1 to v2 30 | --------------------- 31 | The public interface to the v2 library is similar to the v1 library, but a few of the most-used methods have had their signatures changed, so your old programs won't compile right out-of-the-box after a library upgrade. Most importantly, the _init()_ and _set_freq()_ methods are different, so you'll at least need to change these calls in your old sketches. 32 | 33 | The _init()_ method now has three parameters: the crystal load capacitance, the reference frequency, and the frequency correction value (with this last parameter being a new addition). You'll need to add that third parameter to your old _init()_ calls, but then you can delete any _set_correction()_ calls after that (unless you explicitly are changing the frequency correction after the initialization). 34 | 35 | The _set_freq()_ method is now more streamlined and only requires two parameters: the desired output frequency (from 4 kHz to 225 MHz) and clock output. In your old code, you can delete the 2nd parameter in _set_freq()_, which was the PLL frequency. In case you want to do things manually, there is now a new method called _set_freq_manual()_ (see below for details). 36 | 37 | Those two changes should cover nearly all upgrade scenarios, unless you were doing some lower-level use of the Si5351. 38 | 39 | Example 40 | ------- 41 | First, install the Si5351Arduino library into your instance of the Arduino IDE as described above. 42 | 43 | There is a simple example named **si5351_example.ino** that is placed in your examples menu under the Si5351Arduino folder. Open this to see how to initialize the Si5351 and set a couple of the outputs to different frequencies. The commentary below will analyze the sample sketch. 44 | 45 | Before you do anything with the Si5351, you will need to include the "si5351.h" and "Wire.h" header files and instantiate the Si5351 class. 46 | 47 | #include "si5351.h" 48 | #include "Wire.h" 49 | 50 | Si5351 si5351; 51 | 52 | Now in the _Setup()_ function, let's initialize communications with the Si5351, specify the load capacitance of the reference crystal, that we want to use the default reference oscillator frequency of 25 MHz (the second argument of "0" indicates that we want to use the default), and that we will apply no frequency correction at this point (the third argument of "0"): 53 | 54 | i2c_found = si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0); 55 | 56 | The _init()_ method returns a _bool_ which indicates whether the Arduino can communicate with a device on the I2C bus at the specified address (it does not verify that the device is an actual Si5351, but this is useful for ensuring that I2C communication is working). 57 | 58 | Next, let's set the CLK0 output to 14 MHz: 59 | 60 | si5351.set_freq(1400000000ULL, SI5351_CLK0); 61 | 62 | Frequencies are indicated in units of 0.01 Hz. Therefore, if you prefer to work in 1 Hz increments in your own code, simply multiply each frequency passed to the library by 100ULL (better yet, use the define called _SI5351_FREQ_MULT_ in the header file for this multiplication). 63 | 64 | In the main _Loop()_, we use the Serial port to monitor the status of the Si5351, using a method to update a public struct which holds the status bits: 65 | 66 | si5351.update_status(); 67 | Serial.print("SYS_INIT: "); 68 | Serial.print(si5351.dev_status.SYS_INIT); 69 | Serial.print(" LOL_A: "); 70 | Serial.print(si5351.dev_status.LOL_A); 71 | Serial.print(" LOL_B: "); 72 | Serial.print(si5351.dev_status.LOL_B); 73 | Serial.print(" LOS: "); 74 | Serial.print(si5351.dev_status.LOS); 75 | Serial.print(" REVID: "); 76 | Serial.println(si5351.dev_status.REVID); 77 | 78 | When the synthesizers are locked and the Si5351 is working correctly, you'll see an output similar to this one (the REVID may be different): 79 | 80 | SYS_INIT: 0 LOL_A: 0 LOL_B: 0 LOS: 0 REVID: 3 81 | 82 | The nominal status for each of those flags is a 0. When the program indicates 1, there may be a reference clock problem, tuning problem, or some kind of other issue. (Note that it may take the Si5351 a bit of time to return the proper status flags, so in program initialization issue _update_status()_ and then give the Si5351 a few hundred milliseconds to initialize before querying the status flags again.) 83 | 84 | A Brief Word about the Si5351 Architecture 85 | ------------------------------------------ 86 | The Si5351 consists of two main stages: two PLLs which are locked to the reference oscillator (a 25/27 MHz crystal) and which can be set from 600 to 900 MHz, and the output (multisynth) clocks which are locked to a PLL of choice and can be set from 500 kHz to 200 MHz (per the datasheet, although it does seem to be possible to set an output up to 225 MHz). 87 | 88 | The B variant has an additional VCXO stage with control voltage pin which can be used as a reference synth for a clock output (PLLB must be used as the source for any VCXO output clock). 89 | 90 | The C variant is able to take a reference clock input from 10 to 100 MHz separate from the standard crystal reference. If using this reference input, be sure to initialize the library with the correct frequency. 91 | 92 | This library makes PLL assignments based on ease of use. They can be changed manually if needed, although that can introduce complications (see _Manually Selecting a PLL Frequency_ below). 93 | 94 | Setting the Output Frequency 95 | ---------------------------- 96 | As indicated above, the library accepts and indicates clock and PLL frequencies in units of 0.01 Hz, as an _unsigned long long_ variable type (or _uint64_t_). When entering literal values, append ```ULL``` to make an explicit unsigned long long number to ensure proper tuning. Since many applications won't require sub-Hertz tuning, you may wish to use an _unsigned long_ (or _uint32_t_) variable to hold your tune frequency, then scale it up by multiplying by 100ULL before passing it to the _set_freq()_ method. 97 | 98 | Using the _set_freq()_ method is the easiest way to use the library and gives you a wide range of tuning options, but has some constraints in its usage. Outputs CLK0 through CLK5 by default are all locked to PLLA while CLK6 and CLK7 are locked to PLLB. Due to the nature of the Si5351 architecture, there may only be one CLK output among those sharing a PLL which may be set greater than 100 MHz (actually specified at 112.5 MHz by SiLabs, but stability issues have been found at the upper end). Therefore, once one CLK output has been set above 100 MHz, no more CLKs on the same PLL will be allowed to be set greater than 100 MHz (unless the one which is already set is changed to a frequency below this threshold). 99 | 100 | If the above constraints are not suitable, you need glitch-free tuning, or you are counting on multiple clocks being locked to the same reference, you may set the PLL frequency manually then make clock reference assignments to either of the PLLs. 101 | 102 | Manually Selecting a PLL Frequency 103 | ---------------------------------- 104 | Instead of letting the library choose a PLL frequency for your chosen output frequency, you can choose it yourself in the _set_freq_manual()_ method. This method is similar to _set_freq()_, but the second argument is the desired PLL frequency: 105 | 106 | si5351.set_freq_manual(19800000000ULL, 79200000000ULL, SI5351_CLK0); 107 | 108 | **If you use this method (or the other methods to tweak the PLL and multisynth settings manually), it is very important to remember that the library will no longer properly track the PLL and multisynth settings and that you alone will be responsible for keeping the synths tuned properly. Strange things can happen to your other outputs if they are already in use. Be sure to read the Si5351 datasheet and Silicon Labs AN619 before doing this so that you understand what you are doing.** 109 | 110 | When you are setting the PLL manually you need to be mindful of the limits of the IC. The multisynth (MS0 through MS5) is a fractional PLL, with limits described in AN619 as: 111 | 112 | >Valid Multisynth divider ratios are 4, 6, 8, and any fractional value between 8 + 1/1,048,575 and 900 + 0/1. 113 | This means that if any output is greater than 112.5 MHz (900 MHz/8), then this output frequency sets one 114 | of the VCO frequencies. 115 | 116 | To put this in other words, if you want to manually set the PLL and wish to have an output frequency greater than 100 MHz (changed in this library from the stated 112.5 MHz due to stability issues which were noticed), then the choice of PLL frequency is dictated by the choice of output frequency, and will need to be an even multiple of 4, 6, or 8. 117 | 118 | Further Details 119 | --------------- 120 | If we like we can adjust the output drive power: 121 | 122 | si5351.drive_strength(SI5351_CLK0, SI5351_DRIVE_4MA); 123 | 124 | The drive strength is the amount of current into a 50Ω load. 2 mA roughly corresponds to 3 dBm output and 8 mA is approximately 10 dBm output. 125 | 126 | Individual outputs can be turned on and off. In the second argument, use a 0 to disable and 1 to enable: 127 | 128 | si5351.output_enable(SI5351_CLK0, 0); 129 | 130 | You may invert a clock output signal by using this command: 131 | 132 | si5351.set_clock_invert(SI5351_CLK0, 1); 133 | 134 | Calibration 135 | ----------- 136 | There will be some inherent error in the reference oscillator's actual frequency, so we can account for this by measuring the difference between the uncalibrated actual and nominal output frequencies, then using that difference as a correction factor in the library. The _init()_ and _set_correction()_ methods use a signed integer calibration constant measured in parts-per-billion. The easiest way to determine this correction factor is to measure a 10 MHz signal from one of the clock outputs (in Hz, or better resolution if you can measure it), scale it to parts-per-billion, then use it in the _set_correction()_ method in future use of this particular reference oscillator. Once this correction factor is determined, it should not need to be measured again for the same reference oscillator/Si5351 pair unless you want to redo the calibration. With an accurate measurement at one frequency, this calibration should be good across the entire tuning range. 137 | 138 | The calibration method is called like this: 139 | 140 | si5351.set_correction(-6190, SI5351_PLL_INPUT_XO); 141 | 142 | However, you may use the third argument in the _init()_ method to specify the frequency correction and may not actually need to use the explict _set_correction()_ method in your code. 143 | 144 | A handy calibration program is provided with the library in the example folder named _si5351_calibration_. To use it, simply hook up your Arduino to your Si5351, then connect it to a PC with the Arduino IDE. Connect the CLK0 output of the Si5351 to a frequency counter capable of measuring at 10 MHz (the more resolution, the better). Load the sketch then open the serial terminal window. Follow the prompts in the serial terminal to change the output frequency until your frequency counter reads exactly 10.000 000 00 MHz. The output from the Arduino on your serial terminal will tell you the correction factor you will need for future use of that reference oscillator/Si5351 combination. 145 | 146 | One thing to note: the library is set for a 25 MHz reference crystal. If you are using a 27 MHz crystal, use the second parameter in the _init()_ method to specify that as the reference oscillator frequency. 147 | 148 | Phase 149 | ------ 150 | _Please see the example sketch **si5351_phase.ino**_ 151 | 152 | The phase of the output clock signal can be changed by using the set_phase() method. Phase is in relation to (and measured against the period of) the PLL that the output multisynth is referencing. When you change the phase register from its default of 0, you will need to keep a few considerations in mind. 153 | 154 | Setting the phase of a clock requires that you manually set the PLL and take the PLL frequency into account when calculation the value to place in the phase register. As shown on page 10 of Silicon Labs Application Note 619 (AN619), the phase register is a 7-bit register, where a bit represents a phase difference of 1/4 the PLL period. Therefore, the best way to get an accurate phase setting is to make the PLL an even multiple of the clock frequency, depending on what phase you need. 155 | 156 | If you need a 90 degree phase shift (as in many RF applications), then it is quite easy to determine your parameters. Pick a PLL frequency that is an even multiple of your clock frequency (remember that the PLL needs to be in the range of 600 to 900 MHz). Then to set a 90 degree phase shift, you simply enter that multiple into the phase register. Remember when setting multiple outputs to be phase-related to each other, they each need to be referenced to the same PLL. 157 | 158 | You can see this in action in a sketch in the examples folder called _si5351phase_. It shows how one would set up an I/Q pair of signals at 14.1 MHz. 159 | 160 | // We will output 14.1 MHz on CLK0 and CLK1. 161 | // A PLLA frequency of 705 MHz was chosen to give an even 162 | // divisor by 14.1 MHz. 163 | unsigned long long freq = 1410000000ULL; 164 | unsigned long long pll_freq = 70500000000ULL; 165 | 166 | // Set CLK0 and CLK1 to output 14.1 MHz with a fixed PLL frequency 167 | si5351.set_freq_manual(freq, pll_freq, SI5351_CLK0); 168 | si5351.set_freq_manual(freq, pll_freq, SI5351_CLK1); 169 | 170 | // Now we can set CLK1 to have a 90 deg phase shift by entering 171 | // 50 in the CLK1 phase register, since the ratio of the PLL to 172 | // the clock frequency is 50. 173 | si5351.set_phase(SI5351_CLK0, 0); 174 | si5351.set_phase(SI5351_CLK1, 50); 175 | 176 | // We need to reset the PLL before they will be in phase alignment 177 | si5351.pll_reset(SI5351_PLLA); 178 | 179 | 180 | CLK Output Options 181 | ------------------ 182 | _Please see the example sketch **si5351_outputs.ino**_ 183 | 184 | In most cases, you will most likely end up using the multisynth associated with a CLK output, but the Si5351 has some other options available as well. The reference clocks (both the crystal oscillator and the CLKIN signal) can be mirrored to any CLK output. Also CLK1 through CLK3 can mirror the MS0 (CLK0) output, and likewise the CLK5 through CLK7 outputs can mirror the MS4 (CLK4) output. 185 | 186 | If you choose to use one or more of these output options, you first need to enable the fanout option for that particular signal: 187 | 188 | // Enable clock fanout for the XO 189 | si5351.set_clock_fanout(SI5351_FANOUT_XO, 1); 190 | 191 | Once that is done, you can use the _set_clock_source()_ method to choose the output option you desire. Since the CLK outputs by default are turned off, you may need to turn your CLK output on as well: 192 | 193 | // Set CLK1 to output the XO signal 194 | si5351.set_clock_source(SI5351_CLK1, SI5351_CLK_SRC_XTAL); 195 | si5351.output_enable(SI5351_CLK1, 1); 196 | 197 | Using the VCXO (Si5351B) 198 | ----------------------- 199 | _Please see the example sketch **si5351_vcxo.ino**_ 200 | 201 | The Si5351B variant has a VCXO feature which can be used to provide voltage-tunable clock outputs, with a voltage control input on pin 3 of the IC. This functionality is provided on the PLLB oscillator internal to the Si5351, so you must assign any clock outputs that you wish to voltage control to PLLB. 202 | 203 | The library has a method named _set_vcxo()_ that allows you to set the PLLB frequency and the amount of pull range that you wish to use on that oscillator (from 30 to 240 parts-per-million). Using the VCXO is similar to manually setting an output frequency. First, call the _set_vcxo()_ method: 204 | 205 | #define PLLB_FREQ 87600000000ULL 206 | 207 | // Set VCXO osc to 876 MHz (146 MHz x 6), 40 ppm pull 208 | si5351.set_vcxo(PLLB_FREQ, 40); 209 | 210 | Next, we assign the desired VCXO clock output to PLLB: 211 | 212 | // Set CLK0 to be locked to VCXO 213 | si5351.set_ms_source(SI5351_CLK0, SI5351_PLLB); 214 | 215 | Finally, we use the _set_freq_manual()_ method to set the clock output center frequency: 216 | 217 | // Tune to 146 MHz center frequency 218 | si5351.set_freq_manual(14600000000ULL, PLLB_FREQ, SI5351_CLK0); 219 | 220 | Using an External Reference (Si5351C) 221 | ------------------------------------- 222 | _Please see the example sketch **si5351_ext_ref.ino**_ 223 | 224 | The Si5351C variant has a CLKIN input (pin 6) which allows the use of an alternate external CMOS clock reference from 10 to 100 MHz. Either PLLA and/or PLLB can be locked to this external reference. The library tracks the referenced frequencies and correction factors individually for both the crystal oscillator reference (XO) and external reference (CLKIN). 225 | 226 | The XO reference frequency is set during the call to _init()_. If you are going to use the external reference clock, then set its nominal frequency with the _set_ref_freq()_ method: 227 | 228 | // Set the CLKIN reference frequency to 10 MHz 229 | si5351.set_ref_freq(10000000UL, SI5351_PLL_INPUT_CLKIN); 230 | 231 | A correction factor for the external reference clock may also now be set: 232 | 233 | // Apply a correction factor to CLKIN 234 | si5351.set_correction(0, SI5351_PLL_INPUT_CLKIN); 235 | 236 | The _set_pll_input()_ method is used to set the desired PLLs to reference to the external reference signal on CLKIN instead of the XO signal: 237 | 238 | // Set PLLA and PLLB to use the signal on CLKIN instead of the XTAL 239 | si5351.set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN); 240 | si5351.set_pll_input(SI5351_PLLB, SI5351_PLL_INPUT_CLKIN); 241 | 242 | Once that is set, the library can be used as you normally would, with all of the frequency calculations done based on the reference frequency set in _set_ref_freq()_. 243 | 244 | 245 | Alternate I2C Addresses 246 | ----------------------- 247 | The standard I2C bus address for the Si5351 is 0x60, however there are other ICs in the wild that use alternate bus addresses. In order to accommodate these ICs, the class constructor can be called with the I2C bus address as a parameter, as shown in this example: 248 | 249 | Si5351 si5351(0x61); 250 | 251 | Startup Conditions 252 | ------------------ 253 | This library initializes the Si5351 parameters to the following values upon startup and on reset: 254 | 255 | Multisynths 0 through 5 (and hence the matching clock outputs CLK0 through CLK5) are assigned to PLLA, while Multisynths 6 and 7 are assigned to PLLB. 256 | 257 | PLLA and PLLB are set to 800 MHz (also defined as _SI5351_PLL_FIXED_ in the library). 258 | 259 | All CLK outputs are set to 0 Hz and disabled. 260 | 261 | Default drive strength is 2 mA on each output. 262 | 263 | Constraints 264 | ----------- 265 | * Two multisynths cannot share a PLL with when both outputs are >= 100 MHz. The library will refuse to set another multisynth to a frequency in that range if another multisynth sharing the same PLL is already within that frequency range. 266 | * Setting phase will be limited in the extreme edges of the output tuning ranges. Because the phase register is 7-bits in size and is denominated in units representing 1/4 the PLL period, not all phases can be set for all output frequencies. For example, if you need a 90° phase shift, the lowest frequency you can set it at is 4.6875 MHz (600 MHz PLL/128). 267 | * The frequency range of Multisynth 6 and 7 is ~18.45 kHz to 150 MHz. The library assigns PLLB to these two multisynths, so if you choose to use both, then both frequencies must be an even divisor of the PLL frequency (between 6 and 254), so plan accordingly. You can see the current PLLB frequency by accessing the _pllb_freq_ public member. 268 | * VCXO pull range can be ±30 to ±240 ppm 269 | 270 | Public Methods 271 | -------------- 272 | ### init() 273 | ``` 274 | /* 275 | * init(uint8_t xtal_load_c, uint32_t ref_osc_freq, int32_t corr) 276 | * 277 | * Setup communications to the Si5351 and set the crystal 278 | * load capacitance. 279 | * 280 | * xtal_load_c - Crystal load capacitance. Use the SI5351_CRYSTAL_LOAD_*PF 281 | * defines in the header file 282 | * xo_freq - Crystal/reference oscillator frequency in 1 Hz increments. 283 | * Defaults to 25000000 if a 0 is used here. 284 | * corr - Frequency correction constant in parts-per-billion 285 | * 286 | * Returns a boolean that indicates whether a device was found on the desired 287 | * I2C address. 288 | * 289 | */ 290 | bool Si5351::init(uint8_t xtal_load_c, uint32_t ref_osc_freq, uint32_t ref_osc_freq) 291 | ``` 292 | ### reset() 293 | ``` 294 | /* 295 | * reset(void) 296 | * 297 | * Call to reset the Si5351 to the state initialized by the library. 298 | * 299 | */ 300 | void Si5351::reset(void) 301 | ``` 302 | ### set_freq() 303 | ``` 304 | /* 305 | * set_freq(uint64_t freq, enum si5351_clock clk) 306 | * 307 | * Sets the clock frequency of the specified CLK output 308 | * 309 | * freq - Output frequency in Hz 310 | * clk - Clock output 311 | * (use the si5351_clock enum) 312 | */ 313 | uint8_t Si5351::set_freq(uint64_t freq, enum si5351_clock clk) 314 | ``` 315 | ### set_freq_manual() 316 | ``` 317 | /* 318 | * set_freq_manual(uint64_t freq, uint64_t pll_freq, enum si5351_clock clk) 319 | * 320 | * Sets the clock frequency of the specified CLK output using the given PLL 321 | * frequency. You must ensure that the MS is assigned to the correct PLL and 322 | * that the PLL is set to the correct frequency before using this method. 323 | * 324 | * It is important to note that if you use this method, you will have to 325 | * track that all settings are sane yourself. 326 | * 327 | * freq - Output frequency in Hz 328 | * pll_freq - Frequency of the PLL driving the Multisynth in Hz * 100 329 | * clk - Clock output 330 | * (use the si5351_clock enum) 331 | */ 332 | ``` 333 | ### set_pll() 334 | ``` 335 | /* 336 | * set_pll(uint64_t pll_freq, enum si5351_pll target_pll) 337 | * 338 | * Set the specified PLL to a specific oscillation frequency 339 | * 340 | * pll_freq - Desired PLL frequency in Hz * 100 341 | * target_pll - Which PLL to set 342 | * (use the si5351_pll enum) 343 | */ 344 | void Si5351::set_pll(uint64_t pll_freq, enum si5351_pll target_pll) 345 | ``` 346 | ### set_ms() 347 | ``` 348 | /* 349 | * set_ms(enum si5351_clock clk, struct Si5351RegSet ms_reg, uint8_t int_mode, uint8_t r_div, uint8_t div_by_4) 350 | * 351 | * Set the specified multisynth parameters. Not normally needed, but public for advanced users. 352 | * 353 | * clk - Clock output 354 | * (use the si5351_clock enum) 355 | * int_mode - Set integer mode 356 | * Set to 1 to enable, 0 to disable 357 | * r_div - Desired r_div ratio 358 | * div_by_4 - Set Divide By 4 mode 359 | * Set to 1 to enable, 0 to disable 360 | */ 361 | void Si5351::set_ms(enum si5351_clock clk, struct Si5351RegSet ms_reg, uint8_t int_mode, uint8_t r_div, uint8_t div_by_4) 362 | ``` 363 | ### output_enable() 364 | ``` 365 | /* 366 | * output_enable(enum si5351_clock clk, uint8_t enable) 367 | * 368 | * Enable or disable a chosen output 369 | * clk - Clock output 370 | * (use the si5351_clock enum) 371 | * enable - Set to 1 to enable, 0 to disable 372 | */ 373 | void Si5351::output_enable(enum si5351_clock clk, uint8_t enable) 374 | ``` 375 | ### drive_strength() 376 | ``` 377 | /* 378 | * drive_strength(enum si5351_clock clk, enum si5351_drive drive) 379 | * 380 | * Sets the drive strength of the specified clock output 381 | * 382 | * clk - Clock output 383 | * (use the si5351_clock enum) 384 | * drive - Desired drive level 385 | * (use the si5351_drive enum) 386 | */ 387 | void Si5351::drive_strength(enum si5351_clock clk, enum si5351_drive drive) 388 | ``` 389 | ### update_status() 390 | ``` 391 | /* 392 | * update_status(void) 393 | * 394 | * Call this to update the status structs, then access them 395 | * via the dev_status and dev_int_status global variables. 396 | * 397 | * See the header file for the struct definitions. These 398 | * correspond to the flag names for registers 0 and 1 in 399 | * the Si5351 datasheet. 400 | */ 401 | void Si5351::update_status(void) 402 | ``` 403 | ### set_correction() 404 | ``` 405 | /* 406 | * set_correction(int32_t corr, enum si5351_pll_input ref_osc) 407 | * 408 | * corr - Correction factor in ppb 409 | * ref_osc - Desired reference oscillator 410 | * (use the si5351_pll_input enum) 411 | * 412 | * Use this to set the oscillator correction factor. 413 | * This value is a signed 32-bit integer of the 414 | * parts-per-billion value that the actual oscillation 415 | * frequency deviates from the specified frequency. 416 | * 417 | * The frequency calibration is done as a one-time procedure. 418 | * Any desired test frequency within the normal range of the 419 | * Si5351 should be set, then the actual output frequency 420 | * should be measured as accurately as possible. The 421 | * difference between the measured and specified frequencies 422 | * should be calculated in Hertz, then multiplied by 10 in 423 | * order to get the parts-per-billion value. 424 | * 425 | * Since the Si5351 itself has an intrinsic 0 PPM error, this 426 | * correction factor is good across the entire tuning range of 427 | * the Si5351. Once this calibration is done accurately, it 428 | * should not have to be done again for the same Si5351 and 429 | * crystal. 430 | */ 431 | void Si5351::set_correction(int32_t corr, enum si5351_pll_input ref_osc) 432 | ``` 433 | ### set_phase() 434 | ``` 435 | /* 436 | * set_phase(enum si5351_clock clk, uint8_t phase) 437 | * 438 | * clk - Clock output 439 | * (use the si5351_clock enum) 440 | * phase - 7-bit phase word 441 | * (in units of VCO/4 period) 442 | * 443 | * Write the 7-bit phase register. This must be used 444 | * with a user-set PLL frequency so that the user can 445 | * calculate the proper tuning word based on the PLL period. 446 | */ 447 | void Si5351::set_phase(enum si5351_clock clk, uint8_t phase) 448 | ``` 449 | ### get_correction() 450 | ``` 451 | /* 452 | * get_correction(enum si5351_pll_input ref_osc) 453 | * 454 | * ref_osc - Desired reference oscillator 455 | * 0: crystal oscillator (XO) 456 | * 1: external clock input (CLKIN) 457 | * 458 | * Returns the oscillator correction factor stored 459 | * in RAM. 460 | */ 461 | int32_t Si5351::get_correction(enum si5351_pll_input ref_osc) 462 | ``` 463 | ### pll_reset() 464 | ``` 465 | /* 466 | * pll_reset(enum si5351_pll target_pll) 467 | * 468 | * target_pll - Which PLL to reset 469 | * (use the si5351_pll enum) 470 | * 471 | * Apply a reset to the indicated PLL. 472 | */ 473 | void Si5351::pll_reset(enum si5351_pll target_pll) 474 | ``` 475 | ### set_ms_source() 476 | ``` 477 | /* 478 | * set_ms_source(enum si5351_clock clk, enum si5351_pll pll) 479 | * 480 | * clk - Clock output 481 | * (use the si5351_clock enum) 482 | * pll - Which PLL to use as the source 483 | * (use the si5351_pll enum) 484 | * 485 | * Set the desired PLL source for a multisynth. 486 | */ 487 | void Si5351::set_ms_source(enum si5351_clock clk, enum si5351_pll pll) 488 | ``` 489 | ### set_int() 490 | ``` 491 | /* 492 | * set_int(enum si5351_clock clk, uint8_t int_mode) 493 | * 494 | * clk - Clock output 495 | * (use the si5351_clock enum) 496 | * enable - Set to 1 to enable, 0 to disable 497 | * 498 | * Set the indicated multisynth into integer mode. 499 | */ 500 | void Si5351::set_int(enum si5351_clock clk, uint8_t enable) 501 | ``` 502 | ### set_clock_pwr() 503 | ``` 504 | /* 505 | * set_clock_pwr(enum si5351_clock clk, uint8_t pwr) 506 | * 507 | * clk - Clock output 508 | * (use the si5351_clock enum) 509 | * pwr - Set to 1 to enable, 0 to disable 510 | * 511 | * Enable or disable power to a clock output (a power 512 | * saving feature). 513 | */ 514 | void Si5351::set_clock_pwr(enum si5351_clock clk, uint8_t pwr) 515 | ``` 516 | ### set_clock_invert() 517 | ``` 518 | /* 519 | * set_clock_invert(enum si5351_clock clk, uint8_t inv) 520 | * 521 | * clk - Clock output 522 | * (use the si5351_clock enum) 523 | * inv - Set to 1 to enable, 0 to disable 524 | * 525 | * Enable to invert the clock output waveform. 526 | */ 527 | void Si5351::set_clock_invert(enum si5351_clock clk, uint8_t inv) 528 | ``` 529 | ### set_clock_source() 530 | ``` 531 | /* 532 | * set_clock_source(enum si5351_clock clk, enum si5351_clock_source src) 533 | * 534 | * clk - Clock output 535 | * (use the si5351_clock enum) 536 | * src - Which clock source to use for the multisynth 537 | * (use the si5351_clock_source enum) 538 | * 539 | * Set the clock source for a multisynth (based on the options 540 | * presented for Registers 16-23 in the Silicon Labs AN619 document). 541 | * Choices are XTAL, CLKIN, MS0, or the multisynth associated with 542 | * the clock output. 543 | */ 544 | void Si5351::set_clock_source(enum si5351_clock clk, enum si5351_clock_source src) 545 | ``` 546 | ### set_clock_disable() 547 | ``` 548 | /* 549 | * set_clock_disable(enum si5351_clock clk, enum si5351_clock_disable dis_state) 550 | * 551 | * clk - Clock output 552 | * (use the si5351_clock enum) 553 | * dis_state - Desired state of the output upon disable 554 | * (use the si5351_clock_disable enum) 555 | * 556 | * Set the state of the clock output when it is disabled. Per page 27 557 | * of AN619 (Registers 24 and 25), there are four possible values: low, 558 | * high, high impedance, and never disabled. 559 | */ 560 | void Si5351::set_clock_disable(enum si5351_clock clk, enum si5351_clock_disable dis_state) 561 | ``` 562 | ### set_clock_fanout() 563 | ``` 564 | /* 565 | * set_clock_fanout(enum si5351_clock_fanout fanout, uint8_t enable) 566 | * 567 | * fanout - Desired clock fanout 568 | * (use the si5351_clock_fanout enum) 569 | * enable - Set to 1 to enable, 0 to disable 570 | * 571 | * Use this function to enable or disable the clock fanout options 572 | * for individual clock outputs. If you intend to output the XO or 573 | * CLKIN on the clock outputs, enable this first. 574 | * 575 | * By default, only the Multisynth fanout is enabled at startup. 576 | */ 577 | void Si5351::set_clock_fanout(enum si5351_clock_fanout fanout, uint8_t enable) 578 | ``` 579 | ### set_pll_input() 580 | ``` 581 | /* 582 | * set_pll_input(enum si5351_pll pll, enum si5351_pll_input input) 583 | * 584 | * pll - Which PLL to use as the source 585 | * (use the si5351_pll enum) 586 | * input - Which reference oscillator to use as PLL input 587 | * (use the si5351_pll_input enum) 588 | * 589 | * Set the desired reference oscillator source for the given PLL. 590 | */ 591 | void Si5351::set_pll_input(enum si5351_pll pll, enum si5351_pll_input input) 592 | ``` 593 | ### set_vcxo() 594 | ``` 595 | /* 596 | * set_vcxo(uint64_t pll_freq, uint8_t ppm) 597 | * 598 | * pll_freq - Desired PLL base frequency in Hz * 100 599 | * ppm - VCXO pull limit in ppm 600 | * 601 | * Set the parameters for the VCXO on the Si5351B. 602 | */ 603 | void Si5351::set_vcxo(uint64_t pll_freq, uint8_t ppm) 604 | ``` 605 | ### set_ref_freq() 606 | ``` 607 | /* 608 | * set_ref_freq(uint32_t ref_freq, enum si5351_pll_input ref_osc) 609 | * 610 | * ref_freq - Reference oscillator frequency in Hz 611 | * ref_osc - Which reference oscillator frequency to set 612 | * (use the si5351_pll_input enum) 613 | * 614 | * Set the reference frequency value for the desired reference oscillator 615 | */ 616 | void Si5351::set_ref_freq(uint32_t ref_freq, enum si5351_pll_input ref_osc) 617 | ``` 618 | ### si5351_write_bulk() 619 | ``` 620 | uint8_t Si5351::si5351_write_bulk(uint8_t addr, uint8_t bytes, uint8_t *data) 621 | ``` 622 | ### si5351_write() 623 | ``` 624 | uint8_t Si5351::si5351_write(uint8_t addr, uint8_t data) 625 | ``` 626 | ### si5351_read() 627 | ``` 628 | uint8_t Si5351::si5351_read(uint8_t addr) 629 | 630 | ``` 631 | 632 | Public Variables 633 | ---------------- 634 | struct Si5351Status dev_status; 635 | struct Si5351IntStatus dev_int_status; 636 | enum si5351_pll pll_assignment[8]; 637 | uint64_t clk_freq[8]; 638 | uint64_t plla_freq; 639 | uint64_t pllb_freq; 640 | uint32_t xtal_freq; 641 | 642 | Tokens 643 | ------ 644 | Here are the defines, structs, and enumerations you will find handy to use with the library. 645 | 646 | Crystal load capacitance: 647 | 648 | SI5351_CRYSTAL_LOAD_0PF 649 | SI5351_CRYSTAL_LOAD_6PF 650 | SI5351_CRYSTAL_LOAD_8PF 651 | SI5351_CRYSTAL_LOAD_10PF 652 | 653 | Clock outputs: 654 | 655 | enum si5351_clock {SI5351_CLK0, SI5351_CLK1, SI5351_CLK2, SI5351_CLK3, 656 | SI5351_CLK4, SI5351_CLK5, SI5351_CLK6, SI5351_CLK7}; 657 | 658 | PLL sources: 659 | 660 | enum si5351_pll {SI5351_PLLA, SI5351_PLLB}; 661 | 662 | Drive levels: 663 | 664 | enum si5351_drive {SI5351_DRIVE_2MA, SI5351_DRIVE_4MA, SI5351_DRIVE_6MA, SI5351_DRIVE_8MA}; 665 | 666 | Clock sources: 667 | 668 | enum si5351_clock_source {SI5351_CLK_SRC_XTAL, SI5351_CLK_SRC_CLKIN, SI5351_CLK_SRC_MS0, SI5351_CLK_SRC_MS}; 669 | 670 | Clock disable states: 671 | 672 | enum si5351_clock_disable {SI5351_CLK_DISABLE_LOW, SI5351_CLK_DISABLE_HIGH, SI5351_CLK_DISABLE_HI_Z, SI5351_CLK_DISABLE_NEVER}; 673 | 674 | Clock fanout: 675 | 676 | enum si5351_clock_fanout {SI5351_FANOUT_CLKIN, SI5351_FANOUT_XO, SI5351_FANOUT_MS}; 677 | 678 | PLL input sources: 679 | 680 | enum si5351_pll_input{SI5351_PLL_INPUT_XO, SI5351_PLL_INPUT_CLKIN}; 681 | 682 | Status register: 683 | 684 | struct Si5351Status 685 | { 686 | uint8_t SYS_INIT; 687 | uint8_t LOL_B; 688 | uint8_t LOL_A; 689 | uint8_t LOS; 690 | uint8_t REVID; 691 | }; 692 | 693 | Interrupt register: 694 | 695 | struct Si5351IntStatus 696 | { 697 | uint8_t SYS_INIT_STKY; 698 | uint8_t LOL_B_STKY; 699 | uint8_t LOL_A_STKY; 700 | uint8_t LOS_STKY; 701 | }; 702 | 703 | Raw Commands 704 | ------------ 705 | If you need to read and write raw data to the Si5351, there is public access to the library's _read()_, _write()_, and _write_bulk()_ methods. 706 | 707 | Unsupported Features 708 | -------------------- 709 | This library does not currently support the spread spectrum function of the Si5351. 710 | 711 | Changelog 712 | --------- 713 | 714 | * v2.2.0 715 | 716 | * Fix "Si5351 init does not initialize the ref freq nor corr entries for clkin", thanks to conr2286 717 | * Fix bug in read that would hang the micro when using ATtiny3226 (and probably other types of microcontrollers) 718 | 719 | * v2.1.4 720 | 721 | * Fix warning "reg may be uninitialized" 722 | 723 | * v2.1.3 724 | 725 | * Correct error in si5351_example.ino sketch 726 | 727 | * v2.1.2 728 | 729 | * Correct error in si5351_calibration.ino sketch 730 | 731 | * v2.1.1 732 | 733 | * Add bool return value to _init()_ indicating whether a device is on the I2C bus 734 | 735 | * v2.1.0 736 | 737 | * Add support for reference frequencies and corrections for both the XO and CLKIN 738 | 739 | * v2.0.7 740 | 741 | * Change _set_freq()_ behavior so that the output is only automatically enabled the very first time that _set_freq()_ is called 742 | 743 | * v2.0.6 744 | 745 | * Call _set_pll()_ in _set_correction()_ to ensure that the new correction factor is applied 746 | 747 | * v2.0.5 748 | 749 | * Remove PLL reset from _set_freq()_ when not necessary 750 | 751 | * v2.0.4 752 | 753 | * Fix error in VCXO algorithm 754 | 755 | * v2.0.3 756 | 757 | * Fix regression in _set_freq()_ that wiped out proper R div setting, causing errors in setting low frequency outputs 758 | 759 | * v2.0.2 760 | 761 | * Increase maximum frequency in _set_freq()_ to 225 MHz 762 | * Change SI5351_MULTISYNTH_SHARE_MAX from 112.5 MHz to 100 MHz due to stability issues 763 | * Add explicit reset of VCXO param in _reset()_ 764 | * Add I2C bus address parameter and default to class constructor 765 | * Update si5351_calibration example sketch 766 | 767 | * v2.0.1 768 | 769 | * Fix logic error in _set_freq()_ which causes errors in setting multiple clocks >100 MHz 770 | 771 | * v2.0.0 772 | 773 | * Complete rewrite of tuning algorithm 774 | * Add support for setting CLK6 and CLK7 775 | * Add support for VCXO (on Si5351B) 776 | * Change interface of _init()_ and _set_freq()_ 777 | * Add _set_freq_manual()_ method 778 | * Add _reset()_ method 779 | * Added many new example sketches 780 | 781 | * v1.1.2 782 | 783 | * Fix error where register 183 is not pre-loaded with correct value per AN619. Add define for SI5351_CRYSTAL_LOAD_0PF (undocumented in AN619 but present in the official ClockBuilder software). 784 | 785 | * v1.1.1 786 | 787 | * Fix if statement eval error in _set_clock_disable()_ 788 | 789 | * v1.1.0 790 | 791 | * Added _set_pll_input()_ method to allow toggling the PLL reference source for the Si5351C variant and added support to _init()_ for different PLL reference frequencies from 10 to 100 MHz. 792 | 793 | * v1.0.0 794 | 795 | * Initial release 796 | 797 | 798 | 799 | [1]: http://www.silabs.com 800 | [2]: https://www.etherkit.com 801 | -------------------------------------------------------------------------------- /Si5351Arduino.code-workspace: -------------------------------------------------------------------------------- 1 | { 2 | "folders": [ 3 | { 4 | "path": "." 5 | } 6 | ], 7 | "settings": { 8 | "terminal.integrated.env.linux": { 9 | "PATH": "/home/jason/.platformio/penv/bin:/home/jason/.platformio/penv:/home/jason/.cargo/bin:/home/jason/.cargo/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin", 10 | "PLATFORMIO_CALLER": "vscode" 11 | } 12 | } 13 | } -------------------------------------------------------------------------------- /examples/si5351_calibration/si5351_calibration.ino: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351_calibration.ino - Simple calibration routine for the Si5351 3 | * breakout board. 4 | * 5 | * Copyright 2015 - 2018 Paul Warren 6 | * Jason Milldrum 7 | * 8 | * Uses code from https://github.com/darksidelemm/open_radio_miniconf_2015 9 | * and the old version of the calibration sketch 10 | * 11 | * This sketch is free software: you can redistribute it and/or modify 12 | * it under the terms of the GNU General Public License as published by 13 | * the Free Software Foundation, either version 3 of the License, or 14 | * (at your option) any later version. 15 | * Foobar is distributed in the hope that it will be useful, 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | * GNU General Public License for more details. 19 | * You should have received a copy of the GNU General Public License. 20 | * If not, see . 21 | */ 22 | 23 | #include "si5351.h" 24 | #include "Wire.h" 25 | 26 | Si5351 si5351; 27 | 28 | int32_t cal_factor = 0; 29 | int32_t old_cal = 0; 30 | 31 | uint64_t rx_freq; 32 | uint64_t target_freq = 1000000000ULL; // 10 MHz, in hundredths of hertz 33 | 34 | void setup() 35 | { 36 | // Start serial and initialize the Si5351 37 | Serial.begin(57600); 38 | 39 | // The crystal load value needs to match in order to have an accurate calibration 40 | si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0); 41 | 42 | // Start on target frequency 43 | si5351.set_correction(cal_factor, SI5351_PLL_INPUT_XO); 44 | si5351.set_pll(SI5351_PLL_FIXED, SI5351_PLLA); 45 | si5351.set_freq(target_freq, SI5351_CLK0); 46 | } 47 | 48 | void loop() 49 | { 50 | si5351.update_status(); 51 | if (si5351.dev_status.SYS_INIT == 1) 52 | { 53 | Serial.println(F("Initialising Si5351, you shouldn't see many of these!")); 54 | delay(500); 55 | } 56 | else 57 | { 58 | Serial.println(); 59 | Serial.println(F("Adjust until your frequency counter reads as close to 10 MHz as possible.")); 60 | Serial.println(F("Press 'q' when complete.")); 61 | vfo_interface(); 62 | } 63 | } 64 | 65 | static void flush_input(void) 66 | { 67 | while (Serial.available() > 0) 68 | Serial.read(); 69 | } 70 | 71 | static void vfo_interface(void) 72 | { 73 | rx_freq = target_freq; 74 | cal_factor = old_cal; 75 | Serial.println(F(" Up: r t y u i o p")); 76 | Serial.println(F(" Down: f g h j k l ;")); 77 | Serial.println(F(" Hz: 0.01 0.1 1 10 100 1K 10k")); 78 | while (1) 79 | { 80 | if (Serial.available() > 0) 81 | { 82 | char c = Serial.read(); 83 | switch (c) 84 | { 85 | case 'q': 86 | flush_input(); 87 | Serial.println(); 88 | Serial.print(F("Calibration factor is ")); 89 | Serial.println(cal_factor); 90 | Serial.println(F("Setting calibration factor")); 91 | si5351.set_correction(cal_factor, SI5351_PLL_INPUT_XO); 92 | si5351.set_pll(SI5351_PLL_FIXED, SI5351_PLLA); 93 | Serial.println(F("Resetting target frequency")); 94 | si5351.set_freq(target_freq, SI5351_CLK0); 95 | old_cal = cal_factor; 96 | return; 97 | case 'r': rx_freq += 1; break; 98 | case 'f': rx_freq -= 1; break; 99 | case 't': rx_freq += 10; break; 100 | case 'g': rx_freq -= 10; break; 101 | case 'y': rx_freq += 100; break; 102 | case 'h': rx_freq -= 100; break; 103 | case 'u': rx_freq += 1000; break; 104 | case 'j': rx_freq -= 1000; break; 105 | case 'i': rx_freq += 10000; break; 106 | case 'k': rx_freq -= 10000; break; 107 | case 'o': rx_freq += 100000; break; 108 | case 'l': rx_freq -= 100000; break; 109 | case 'p': rx_freq += 1000000; break; 110 | case ';': rx_freq -= 1000000; break; 111 | default: 112 | // Do nothing 113 | continue; 114 | } 115 | 116 | cal_factor = (int32_t)(target_freq - rx_freq) + old_cal; 117 | si5351.set_correction(cal_factor, SI5351_PLL_INPUT_XO); 118 | si5351.set_pll(SI5351_PLL_FIXED, SI5351_PLLA); 119 | si5351.pll_reset(SI5351_PLLA); 120 | si5351.set_freq(target_freq, SI5351_CLK0); 121 | Serial.print(F("Current difference:")); 122 | Serial.println(cal_factor); 123 | } 124 | } 125 | } 126 | -------------------------------------------------------------------------------- /examples/si5351_clk67_example/si5351_clk67_example.ino: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351_clk67_example.ino - Simple example of setting CLK6 and CLK7 3 | * outputs using Si5351Arduino library 4 | * 5 | * Copyright (C) 2016 Jason Milldrum 6 | * 7 | * This program is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This program is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program. If not, see . 19 | */ 20 | 21 | #include "si5351.h" 22 | #include "Wire.h" 23 | 24 | Si5351 si5351; 25 | 26 | void setup() 27 | { 28 | // Start serial and initialize the Si5351 29 | Serial.begin(57600); 30 | si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0); 31 | 32 | // Set CLK0 to output 14 MHz 33 | si5351.set_freq(1400000000ULL, SI5351_CLK0); 34 | 35 | // Set CLK6 to 23 MHz, library sets PLL to 874 MHz 36 | si5351.set_freq(2300000000ULL, SI5351_CLK6); 37 | 38 | // This won't work since it is not an even multiple of the PLL (874 MHz) 39 | si5351.set_freq(1234567800ULL, SI5351_CLK7); 40 | 41 | // Setting CLK7 to 87.4 MHz will work 42 | si5351.set_freq(8740000000ULL, SI5351_CLK7); 43 | 44 | si5351.update_status(); 45 | delay(500); 46 | } 47 | 48 | void loop() 49 | { 50 | // Read the Status Register and print it every 10 seconds 51 | si5351.update_status(); 52 | Serial.print("PLLA: "); 53 | Serial.print((uint32_t)(si5351.plla_freq/100)); 54 | Serial.print(" PLLB: "); 55 | Serial.print((uint32_t)(si5351.pllb_freq/100)); 56 | Serial.print(" SYS_INIT: "); 57 | Serial.print(si5351.dev_status.SYS_INIT); 58 | Serial.print(" LOL_A: "); 59 | Serial.print(si5351.dev_status.LOL_A); 60 | Serial.print(" LOL_B: "); 61 | Serial.print(si5351.dev_status.LOL_B); 62 | Serial.print(" LOS: "); 63 | Serial.print(si5351.dev_status.LOS); 64 | Serial.print(" REVID: "); 65 | Serial.println(si5351.dev_status.REVID); 66 | 67 | delay(10000); 68 | } 69 | -------------------------------------------------------------------------------- /examples/si5351_example/si5351_example.ino: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351_example.ino - Simple example of using Si5351Arduino library 3 | * 4 | * Copyright (C) 2015 - 2016 Jason Milldrum 5 | * 6 | * This program is free software: you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation, either version 3 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License 17 | * along with this program. If not, see . 18 | */ 19 | 20 | #include "si5351.h" 21 | #include "Wire.h" 22 | 23 | Si5351 si5351; 24 | 25 | void setup() 26 | { 27 | bool i2c_found; 28 | 29 | // Start serial and initialize the Si5351 30 | Serial.begin(57600); 31 | i2c_found = si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0); 32 | if(!i2c_found) 33 | { 34 | Serial.println("Device not found on I2C bus!"); 35 | } 36 | 37 | // Set CLK0 to output 14 MHz 38 | si5351.set_freq(1400000000ULL, SI5351_CLK0); 39 | 40 | // Set CLK1 to output 175 MHz 41 | si5351.set_ms_source(SI5351_CLK1, SI5351_PLLB); 42 | si5351.set_freq_manual(17500000000ULL, 70000000000ULL, SI5351_CLK1); 43 | 44 | // Query a status update and wait a bit to let the Si5351 populate the 45 | // status flags correctly. 46 | si5351.update_status(); 47 | delay(500); 48 | } 49 | 50 | void loop() 51 | { 52 | // Read the Status Register and print it every 10 seconds 53 | si5351.update_status(); 54 | Serial.print("SYS_INIT: "); 55 | Serial.print(si5351.dev_status.SYS_INIT); 56 | Serial.print(" LOL_A: "); 57 | Serial.print(si5351.dev_status.LOL_A); 58 | Serial.print(" LOL_B: "); 59 | Serial.print(si5351.dev_status.LOL_B); 60 | Serial.print(" LOS: "); 61 | Serial.print(si5351.dev_status.LOS); 62 | Serial.print(" REVID: "); 63 | Serial.println(si5351.dev_status.REVID); 64 | 65 | delay(10000); 66 | } 67 | -------------------------------------------------------------------------------- /examples/si5351_ext_ref/si5351_ext_ref.ino: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351_ext_ref.ino - Simple example of using an external reference 3 | * clock with the Si5351Arduino library 4 | * 5 | * Copyright (C) 2016 Jason Milldrum 6 | * 7 | * This program is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This program is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program. If not, see . 19 | */ 20 | 21 | #include "si5351.h" 22 | #include "Wire.h" 23 | 24 | Si5351 si5351; 25 | 26 | void setup() 27 | { 28 | // Start serial 29 | Serial.begin(57600); 30 | 31 | // Initialize the Si5351 to use a 25 MHz clock on the XO input 32 | si5351.init(SI5351_CRYSTAL_LOAD_0PF, 0, 0); 33 | 34 | // Set the CLKIN reference frequency to 10 MHz 35 | si5351.set_ref_freq(10000000UL, SI5351_PLL_INPUT_CLKIN); 36 | 37 | // Apply a correction factor to CLKIN 38 | si5351.set_correction(0, SI5351_PLL_INPUT_CLKIN); 39 | 40 | // Set PLLA and PLLB to use the signal on CLKIN instead of the XTAL 41 | si5351.set_pll_input(SI5351_PLLA, SI5351_PLL_INPUT_CLKIN); 42 | si5351.set_pll_input(SI5351_PLLB, SI5351_PLL_INPUT_CLKIN); 43 | 44 | // Set CLK0 to output 14 MHz 45 | si5351.set_freq(1400000000ULL, SI5351_CLK0); 46 | 47 | si5351.update_status(); 48 | delay(500); 49 | } 50 | 51 | void loop() 52 | { 53 | // Read the Status Register and print it every 10 seconds 54 | si5351.update_status(); 55 | Serial.print(" SYS_INIT: "); 56 | Serial.print(si5351.dev_status.SYS_INIT); 57 | Serial.print(" LOL_A: "); 58 | Serial.print(si5351.dev_status.LOL_A); 59 | Serial.print(" LOL_B: "); 60 | Serial.print(si5351.dev_status.LOL_B); 61 | Serial.print(" LOS: "); 62 | Serial.print(si5351.dev_status.LOS); 63 | Serial.print(" REVID: "); 64 | Serial.println(si5351.dev_status.REVID); 65 | 66 | delay(10000); 67 | } 68 | -------------------------------------------------------------------------------- /examples/si5351_outputs/si5351_outputs.ino: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351_outputs.ino - How to set different output sources 3 | * with the Si5351Arduino library 4 | * 5 | * Copyright (C) 2016 Jason Milldrum 6 | * 7 | * This program is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This program is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program. If not, see . 19 | */ 20 | 21 | #include "si5351.h" 22 | #include "Wire.h" 23 | 24 | Si5351 si5351; 25 | 26 | void setup() 27 | { 28 | // Start serial and initialize the Si5351 29 | Serial.begin(57600); 30 | si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0); 31 | 32 | // Set CLK0 to output 14 MHz 33 | si5351.set_freq(1400000000ULL, SI5351_CLK0); 34 | 35 | // Enable clock fanout for the XO 36 | si5351.set_clock_fanout(SI5351_FANOUT_XO, 1); 37 | 38 | // Enable clock fanout for MS 39 | si5351.set_clock_fanout(SI5351_FANOUT_MS, 1); 40 | 41 | // Set CLK1 to output the XO signal 42 | si5351.set_clock_source(SI5351_CLK1, SI5351_CLK_SRC_XTAL); 43 | si5351.output_enable(SI5351_CLK1, 1); 44 | 45 | // Set CLK2 to mirror the MS0 (CLK0) output 46 | si5351.set_clock_source(SI5351_CLK2, SI5351_CLK_SRC_MS0); 47 | si5351.output_enable(SI5351_CLK2, 1); 48 | 49 | // Change CLK0 output to 10 MHz, observe how CLK2 also changes 50 | si5351.set_freq(1000000000ULL, SI5351_CLK0); 51 | 52 | si5351.update_status(); 53 | delay(500); 54 | } 55 | 56 | void loop() 57 | { 58 | // Read the Status Register and print it every 10 seconds 59 | si5351.update_status(); 60 | Serial.print(" SYS_INIT: "); 61 | Serial.print(si5351.dev_status.SYS_INIT); 62 | Serial.print(" LOL_A: "); 63 | Serial.print(si5351.dev_status.LOL_A); 64 | Serial.print(" LOL_B: "); 65 | Serial.print(si5351.dev_status.LOL_B); 66 | Serial.print(" LOS: "); 67 | Serial.print(si5351.dev_status.LOS); 68 | Serial.print(" REVID: "); 69 | Serial.println(si5351.dev_status.REVID); 70 | 71 | delay(10000); 72 | } 73 | -------------------------------------------------------------------------------- /examples/si5351_phase/si5351_phase.ino: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351_phase.ino - Example for setting phase with Si5351Arduino library 3 | * 4 | * Copyright (C) 2015 - 2016 Jason Milldrum 5 | * 6 | * This program is free software: you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation, either version 3 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License 17 | * along with this program. If not, see . 18 | */ 19 | 20 | /* 21 | * Setting the phase of a clock requires that you manually set the PLL and 22 | * take the PLL frequency into account when calculation the value to place 23 | * in the phase register. As shown on page 10 of Silicon Labs Application 24 | * Note 619 (AN619), the phase register is a 7-bit register, where a bit 25 | * represents a phase difference of 1/4 the PLL period. Therefore, the best 26 | * way to get an accurate phase setting is to make the PLL an even multiple 27 | * of the clock frequency, depending on what phase you need. 28 | * 29 | * If you need a 90 degree phase shift (as in many RF applications), then 30 | * it is quite easy to determine your parameters. Pick a PLL frequency that 31 | * is an even multiple of your clock frequency (remember that the PLL needs 32 | * to be in the range of 600 to 900 MHz). Then to set a 90 degree phase shift, 33 | * you simply enter that multiple into the phase register. Remember when 34 | * setting multiple outputs to be phase-related to each other, they each need 35 | * to be referenced to the same PLL. 36 | */ 37 | 38 | #include "si5351.h" 39 | #include "Wire.h" 40 | 41 | Si5351 si5351; 42 | 43 | void setup() 44 | { 45 | // Start serial and initialize the Si5351 46 | Serial.begin(57600); 47 | si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0); 48 | 49 | // We will output 14.1 MHz on CLK0 and CLK1. 50 | // A PLLA frequency of 705 MHz was chosen to give an even 51 | // divisor by 14.1 MHz. 52 | unsigned long long freq = 1410000000ULL; 53 | unsigned long long pll_freq = 70500000000ULL; 54 | 55 | // Set CLK0 and CLK1 to use PLLA as the MS source. 56 | // This is not explicitly necessary in v2 of this library, 57 | // as these are already the default assignments. 58 | // si5351.set_ms_source(SI5351_CLK0, SI5351_PLLA); 59 | // si5351.set_ms_source(SI5351_CLK1, SI5351_PLLA); 60 | 61 | // Set CLK0 and CLK1 to output 14.1 MHz with a fixed PLL frequency 62 | si5351.set_freq_manual(freq, pll_freq, SI5351_CLK0); 63 | si5351.set_freq_manual(freq, pll_freq, SI5351_CLK1); 64 | 65 | // Now we can set CLK1 to have a 90 deg phase shift by entering 66 | // 50 in the CLK1 phase register, since the ratio of the PLL to 67 | // the clock frequency is 50. 68 | si5351.set_phase(SI5351_CLK0, 0); 69 | si5351.set_phase(SI5351_CLK1, 50); 70 | 71 | // We need to reset the PLL before they will be in phase alignment 72 | si5351.pll_reset(SI5351_PLLA); 73 | 74 | // Query a status update and wait a bit to let the Si5351 populate the 75 | // status flags correctly. 76 | si5351.update_status(); 77 | delay(500); 78 | } 79 | 80 | void loop() 81 | { 82 | // Read the Status Register and print it every 10 seconds 83 | si5351.update_status(); 84 | Serial.print("SYS_INIT: "); 85 | Serial.print(si5351.dev_status.SYS_INIT); 86 | Serial.print(" LOL_A: "); 87 | Serial.print(si5351.dev_status.LOL_A); 88 | Serial.print(" LOL_B: "); 89 | Serial.print(si5351.dev_status.LOL_B); 90 | Serial.print(" LOS: "); 91 | Serial.print(si5351.dev_status.LOS); 92 | Serial.print(" REVID: "); 93 | Serial.println(si5351.dev_status.REVID); 94 | 95 | delay(10000); 96 | } 97 | -------------------------------------------------------------------------------- /examples/si5351_sweeper/si5351_sweeper.ino: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351_sweeper.ino - Si5351 Simple Sweep Generator 3 | * 4 | * Copyright (c) 2016 Thomas S. Knutsen 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining 7 | * a copy of this software and associated documentation files (the 8 | * "Software"), to deal in the Software without restriction, including 9 | * without limitation the rights to use, copy, modify, merge, publish, 10 | * distribute, sublicense, and/or sell copies of the Software, and to 11 | * permit persons to whom the Software is furnished to do so, subject 12 | * to the following conditions: 13 | * 14 | * The above copyright notice and this permission notice shall be 15 | * included in all copies or substantial portions of the Software. 16 | * 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR 21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22 | * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 | *WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 | * 25 | */ 26 | 27 | /* 28 | * Connect Si5351 to I2C 29 | * Sweep out is on pin 5, ranging from 0-5V (3.3V). 30 | * Use a filter on sweep out voltage. 100K + 1uF should be a good start. 31 | * A op-amp can be used to improve the filtering of the DC voltage. 32 | */ 33 | 34 | int correction = 0; // use the Si5351 correction sketch to find the frequency correction factor 35 | 36 | int inData = 0; 37 | long steps = 100; 38 | unsigned long startFreq = 10000000; 39 | unsigned long stopFreq = 100000000; 40 | int analogpin = 5; 41 | int delaytime = 50; 42 | 43 | #include 44 | #include "Wire.h" 45 | 46 | Si5351 si5351; 47 | 48 | 49 | void setup() 50 | { 51 | Serial.begin(57600); 52 | /* 53 | while (!Serial) { 54 | ; // wait for serial port to connect. Needed for Leonardo only 55 | } 56 | */ 57 | si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, correction); 58 | si5351.drive_strength(SI5351_CLK0, SI5351_DRIVE_6MA); 59 | info(); 60 | } 61 | 62 | void info() 63 | { 64 | Serial.println("Si5351 Sweeper"); 65 | Serial.println("A = Start frequency"); 66 | Serial.println("B = Stop frequency"); 67 | Serial.println("S = Stepsize"); 68 | Serial.println("M = Single sweep"); 69 | Serial.println("C = Continious sweep until Q"); 70 | Serial.print("T = Timestep in ms, currently "); 71 | Serial.println(delaytime); 72 | } 73 | 74 | 75 | void loop() 76 | { 77 | inData = 0; 78 | if(Serial.available() > 0) // see if incoming serial data: 79 | { 80 | inData = Serial.read(); // read oldest byte in serial buffer: 81 | } 82 | 83 | if(inData == 'M' || inData == 'm') 84 | { 85 | inData = 0; 86 | unsigned long freqstep = (stopFreq - startFreq) / steps; 87 | for(int i = 0; i < (steps + 1); i++ ) 88 | { 89 | unsigned long freq = startFreq + (freqstep*i); 90 | si5351.set_freq(freq * SI5351_FREQ_MULT, SI5351_CLK0); 91 | analogWrite(analogpin, map(i, 0, steps, 0, 255)); 92 | delay(delaytime); 93 | } 94 | si5351.output_enable(SI5351_CLK0, 0); 95 | } 96 | 97 | if(inData == 'C' || inData == 'c') 98 | { 99 | boolean running = true; 100 | inData = 0; 101 | while(running) 102 | { 103 | unsigned long freqstep = (stopFreq - startFreq) / steps; 104 | for (int i = 0; i < (steps + 1); i++ ) 105 | { 106 | unsigned long freq = startFreq + (freqstep * i); 107 | si5351.set_freq(freq * SI5351_FREQ_MULT, SI5351_CLK0); 108 | analogWrite(analogpin, map(i, 0, steps, 0, 255)); 109 | delay(delaytime); 110 | if(Serial.available() > 0) // see if incoming serial data: 111 | { 112 | inData = Serial.read(); // read oldest byte in serial buffer: 113 | if(inData == 'Q' || inData == 'q') 114 | { 115 | running = false; 116 | inData = 0; 117 | } 118 | } 119 | } 120 | } 121 | 122 | si5351.output_enable(SI5351_CLK0, 0); 123 | } 124 | 125 | if(inData == 'S' || inData == 's') 126 | { 127 | steps = Serial.parseInt(); 128 | Serial.print("Steps: "); 129 | Serial.println(steps); 130 | inData = 0; 131 | } 132 | 133 | if(inData == 'H' || inData == 'h') 134 | { 135 | info(); 136 | } 137 | 138 | if(inData == 'T' || inData == 't') 139 | { 140 | delaytime = Serial.parseInt(); 141 | Serial.print("time pr step: "); 142 | Serial.println(delaytime); 143 | inData = 0; 144 | } 145 | 146 | if(inData == 'L' || inData == 'l') 147 | { 148 | for (int i = 0; i < (steps+1); i++ ) 149 | { 150 | // print out the value you read: 151 | Serial.print(i * 10); 152 | Serial.print(';'); 153 | Serial.print(steps); 154 | Serial.print(';'); 155 | Serial.println(-i); 156 | delay(10); // delay in between reads for stability 157 | } 158 | inData = 0; 159 | } 160 | 161 | if(inData == 'A' || inData == 'a') 162 | { 163 | startFreq = Serial.parseInt(); 164 | Serial.print("Start: "); 165 | Serial.println(startFreq); 166 | inData = 0; 167 | } 168 | 169 | if(inData == 'B' || inData == 'b') 170 | { 171 | stopFreq = Serial.parseInt(); 172 | Serial.print("Stop: "); 173 | Serial.println(stopFreq); 174 | inData = 0; 175 | } 176 | } 177 | -------------------------------------------------------------------------------- /examples/si5351_vcxo/si5351_vcxo.ino: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351_vcxo.ino - Example for using the Si5351B VCXO functions 3 | * with Si5351Arduino library 4 | * 5 | * Copyright (C) 2016 Jason Milldrum 6 | * 7 | * This program is free software: you can redistribute it and/or modify 8 | * it under the terms of the GNU General Public License as published by 9 | * the Free Software Foundation, either version 3 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This program is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program. If not, see . 19 | */ 20 | 21 | #include "si5351.h" 22 | #include "Wire.h" 23 | 24 | #define PLLB_FREQ 87600000000ULL 25 | 26 | Si5351 si5351; 27 | 28 | void setup() 29 | { 30 | // Start serial and initialize the Si5351 31 | Serial.begin(57600); 32 | si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0); 33 | 34 | // Set VCXO osc to 876 MHz (146 MHz x 6), 40 ppm pull 35 | si5351.set_vcxo(PLLB_FREQ, 40); 36 | 37 | // Set CLK0 to be locked to VCXO 38 | si5351.set_ms_source(SI5351_CLK0, SI5351_PLLB); 39 | 40 | // Tune to 146 MHz center frequency 41 | si5351.set_freq_manual(14600000000ULL, PLLB_FREQ, SI5351_CLK0); 42 | 43 | si5351.update_status(); 44 | delay(500); 45 | } 46 | 47 | void loop() 48 | { 49 | // Read the Status Register and print it every 10 seconds 50 | si5351.update_status(); 51 | Serial.print("corr: "); 52 | Serial.print(si5351.get_correction()); 53 | Serial.print(" SYS_INIT: "); 54 | Serial.print(si5351.dev_status.SYS_INIT); 55 | Serial.print(" LOL_A: "); 56 | Serial.print(si5351.dev_status.LOL_A); 57 | Serial.print(" LOL_B: "); 58 | Serial.print(si5351.dev_status.LOL_B); 59 | Serial.print(" LOS: "); 60 | Serial.print(si5351.dev_status.LOS); 61 | Serial.print(" REVID: "); 62 | Serial.println(si5351.dev_status.REVID); 63 | 64 | delay(10000); 65 | } 66 | -------------------------------------------------------------------------------- /keywords.txt: -------------------------------------------------------------------------------- 1 | Si5351 KEYWORD1 2 | 3 | init KEYWORD2 4 | reset KEYWORD2 5 | set_freq KEYWORD2 6 | set_freq_manual KEYWORD2 7 | set_pll KEYWORD2 8 | set_ms KEYWORD2 9 | output_enable KEYWORD2 10 | drive_strength KEYWORD2 11 | update_status KEYWORD2 12 | set_correction KEYWORD2 13 | set_phase KEYWORD2 14 | get_correction KEYWORD2 15 | pll_reset KEYWORD2 16 | set_ms_source KEYWORD2 17 | set_int KEYWORD2 18 | set_clock_pwr KEYWORD2 19 | set_clock_invert KEYWORD2 20 | set_clock_source KEYWORD2 21 | set_clock_disable KEYWORD2 22 | set_clock_fanout KEYWORD2 23 | set_pll_input KEYWORD2 24 | set_vcxo KEYWORD2 25 | set_ref_freq KEYWORD2 26 | si5351_write_bulk KEYWORD2 27 | si5351_write KEYWORD2 28 | si5351_read KEYWORD2 29 | dev_status KEYWORD2 30 | dev_int_status KEYWORD2 31 | pll_assignment KEYWORD2 32 | clk_freq KEYWORD2 33 | plla_freq KEYWORD2 34 | pllb_freq KEYWORD2 35 | xtal_freq KEYWORD2 36 | plla_ref_osc KEYWORD2 37 | pllb_ref_osc KEYWORD2 38 | 39 | SI5351_PLL_FIXED LITERAL1 40 | SI5351_FREQ_MULT LITERAL1 41 | SI5351_DEFAULT_CLK LITERAL1 42 | SI5351_CRYSTAL_LOAD_0PF LITERAL1 43 | SI5351_CRYSTAL_LOAD_6PF LITERAL1 44 | SI5351_CRYSTAL_LOAD_8PF LITERAL1 45 | SI5351_CRYSTAL_LOAD_10PF LITERAL1 46 | SI5351_CLK0 LITERAL1 47 | SI5351_CLK1 LITERAL1 48 | SI5351_CLK2 LITERAL1 49 | SI5351_CLK3 LITERAL1 50 | SI5351_CLK4 LITERAL1 51 | SI5351_CLK5 LITERAL1 52 | SI5351_CLK6 LITERAL1 53 | SI5351_CLK7 LITERAL1 54 | SI5351_PLLA LITERAL1 55 | SI5351_PLLB LITERAL1 56 | SI5351_DRIVE_2MA LITERAL1 57 | SI5351_DRIVE_4MA LITERAL1 58 | SI5351_DRIVE_6MA LITERAL1 59 | SI5351_DRIVE_8MA LITERAL1 60 | SI5351_CLK_SRC_XTAL LITERAL1 61 | SI5351_CLK_SRC_CLKIN LITERAL1 62 | SI5351_CLK_SRC_MS0 LITERAL1 63 | SI5351_CLK_SRC_MS LITERAL1 64 | SI5351_CLK_DISABLE_LOW LITERAL1 65 | SI5351_CLK_DISABLE_HIGH LITERAL1 66 | SI5351_CLK_DISABLE_HI_Z LITERAL1 67 | SI5351_CLK_DISABLE_NEVER LITERAL1 68 | SI5351_FANOUT_CLKIN LITERAL1 69 | SI5351_FANOUT_XO LITERAL1 70 | SI5351_FANOUT_MS LITERAL1 71 | SI5351_PLL_INPUT_XO LITERAL1 72 | SI5351_PLL_INPUT_CLKIN LITERAL1 73 | SYS_INIT LITERAL1 74 | LOL_B LITERAL1 75 | LOL_A LITERAL1 76 | LOS LITERAL1 77 | REVID LITERAL1 78 | SYS_INIT_STKY LITERAL1 79 | LOL_B_STKY LITERAL1 80 | LOL_A_STKY LITERAL1 81 | LOS_STKY LITERAL1 82 | -------------------------------------------------------------------------------- /library.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "Etherkit Si5351", 3 | "keywords": "si5351", 4 | "description": "A full-featured library for the Si5351 series of clock generator ICs from Silicon Labs", 5 | "repository": 6 | { 7 | "type": "git", 8 | "url": "https://github.com/etherkit/Si5351Arduino" 9 | }, 10 | "authors": 11 | [ 12 | { 13 | "name": "Jason Milldrum", 14 | "email": "milldrum@gmail.com", 15 | "url": "http://nt7s.com", 16 | "maintainer": true 17 | } 18 | ], 19 | "version": "2.2.0", 20 | "frameworks": "arduino", 21 | "platforms": "*" 22 | } -------------------------------------------------------------------------------- /library.properties: -------------------------------------------------------------------------------- 1 | name=Etherkit Si5351 2 | version=2.2.0 3 | author=Jason Milldrum 4 | maintainer=Jason Milldrum 5 | sentence=A full-featured library for the Si5351 series of clock generator ICs from Silicon Labs 6 | paragraph=This library will allow you to control nearly all features of the Si5351, without depending on the proprietary ClockBuilder software from Silicon Labs. 7 | category=Device Control 8 | url=https://github.com/etherkit/Si5351Arduino 9 | architectures=* 10 | -------------------------------------------------------------------------------- /licence.txt: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. 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If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /src/si5351.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351.cpp - Si5351 library for Arduino 3 | * 4 | * Copyright (C) 2015 - 2019 Jason Milldrum 5 | * Dana H. Myers 6 | * 7 | * Some tuning algorithms derived from clk-si5351.c in the Linux kernel. 8 | * Sebastian Hesselbarth 9 | * Rabeeh Khoury 10 | * 11 | * This program is free software: you can redistribute it and/or modify 12 | * it under the terms of the GNU General Public License as published by 13 | * the Free Software Foundation, either version 3 of the License, or 14 | * (at your option) any later version. 15 | * 16 | * This program is distributed in the hope that it will be useful, 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | * GNU General Public License for more details. 20 | * 21 | * You should have received a copy of the GNU General Public License 22 | * along with this program. If not, see . 23 | */ 24 | 25 | #include 26 | 27 | #include "Arduino.h" 28 | #include "Wire.h" 29 | #include "si5351.h" 30 | 31 | 32 | /********************/ 33 | /* Public functions */ 34 | /********************/ 35 | 36 | Si5351::Si5351(uint8_t i2c_addr): 37 | i2c_bus_addr(i2c_addr) 38 | { 39 | xtal_freq[0] = SI5351_XTAL_FREQ; 40 | 41 | // Start by using XO ref osc as default for each PLL 42 | plla_ref_osc = SI5351_PLL_INPUT_XO; 43 | pllb_ref_osc = SI5351_PLL_INPUT_XO; 44 | clkin_div = SI5351_CLKIN_DIV_1; 45 | } 46 | 47 | /* 48 | * init(uint8_t xtal_load_c, uint32_t ref_osc_freq, int32_t corr) 49 | * 50 | * Setup communications to the Si5351 and set the crystal 51 | * load capacitance. 52 | * 53 | * xtal_load_c - Crystal load capacitance. Use the SI5351_CRYSTAL_LOAD_*PF 54 | * defines in the header file 55 | * xo_freq - Crystal/reference oscillator frequency in 1 Hz increments. 56 | * Defaults to 25000000 if a 0 is used here. 57 | * corr - Frequency correction constant in parts-per-billion 58 | * 59 | * Returns a boolean that indicates whether a device was found on the desired 60 | * I2C address. 61 | * 62 | */ 63 | bool Si5351::init(uint8_t xtal_load_c, uint32_t xo_freq, int32_t corr) 64 | { 65 | // Start I2C comms 66 | Wire.begin(); 67 | 68 | // Check for a device on the bus, bail out if it is not there 69 | Wire.beginTransmission(i2c_bus_addr); 70 | uint8_t reg_val; 71 | reg_val = Wire.endTransmission(); 72 | 73 | if(reg_val == 0) 74 | { 75 | // Wait for SYS_INIT flag to be clear, indicating that device is ready 76 | uint8_t status_reg = 0; 77 | do 78 | { 79 | status_reg = si5351_read(SI5351_DEVICE_STATUS); 80 | } while (status_reg >> 7 == 1); 81 | 82 | // Set crystal load capacitance 83 | si5351_write(SI5351_CRYSTAL_LOAD, (xtal_load_c & SI5351_CRYSTAL_LOAD_MASK) | 0b00010010); 84 | 85 | // Set up the XO and CLKIN reference frequencies 86 | if (xo_freq != 0) 87 | { 88 | set_ref_freq(xo_freq, SI5351_PLL_INPUT_XO); 89 | set_ref_freq(xo_freq, SI5351_PLL_INPUT_CLKIN); //Also CLKIN 90 | } 91 | else 92 | { 93 | set_ref_freq(SI5351_XTAL_FREQ, SI5351_PLL_INPUT_XO); 94 | set_ref_freq(SI5351_XTAL_FREQ, SI5351_PLL_INPUT_CLKIN); //Also CLKIN 95 | } 96 | 97 | // Set the frequency calibrations for the XO and CLKIN 98 | set_correction(corr, SI5351_PLL_INPUT_XO); 99 | set_correction(corr, SI5351_PLL_INPUT_CLKIN); 100 | 101 | reset(); 102 | 103 | return true; 104 | } 105 | else 106 | { 107 | return false; 108 | } 109 | } 110 | 111 | /* 112 | * reset(void) 113 | * 114 | * Call to reset the Si5351 to the state initialized by the library. 115 | * 116 | */ 117 | void Si5351::reset(void) 118 | { 119 | // Initialize the CLK outputs according to flowchart in datasheet 120 | // First, turn them off 121 | si5351_write(16, 0x80); 122 | si5351_write(17, 0x80); 123 | si5351_write(18, 0x80); 124 | si5351_write(19, 0x80); 125 | si5351_write(20, 0x80); 126 | si5351_write(21, 0x80); 127 | si5351_write(22, 0x80); 128 | si5351_write(23, 0x80); 129 | 130 | // Turn the clocks back on... 131 | si5351_write(16, 0x0c); 132 | si5351_write(17, 0x0c); 133 | si5351_write(18, 0x0c); 134 | si5351_write(19, 0x0c); 135 | si5351_write(20, 0x0c); 136 | si5351_write(21, 0x0c); 137 | si5351_write(22, 0x0c); 138 | si5351_write(23, 0x0c); 139 | 140 | // Set PLLA and PLLB to 800 MHz for automatic tuning 141 | set_pll(SI5351_PLL_FIXED, SI5351_PLLA); 142 | set_pll(SI5351_PLL_FIXED, SI5351_PLLB); 143 | 144 | // Make PLL to CLK assignments for automatic tuning 145 | pll_assignment[0] = SI5351_PLLA; 146 | pll_assignment[1] = SI5351_PLLA; 147 | pll_assignment[2] = SI5351_PLLA; 148 | pll_assignment[3] = SI5351_PLLA; 149 | pll_assignment[4] = SI5351_PLLA; 150 | pll_assignment[5] = SI5351_PLLA; 151 | pll_assignment[6] = SI5351_PLLB; 152 | pll_assignment[7] = SI5351_PLLB; 153 | 154 | set_ms_source(SI5351_CLK0, SI5351_PLLA); 155 | set_ms_source(SI5351_CLK1, SI5351_PLLA); 156 | set_ms_source(SI5351_CLK2, SI5351_PLLA); 157 | set_ms_source(SI5351_CLK3, SI5351_PLLA); 158 | set_ms_source(SI5351_CLK4, SI5351_PLLA); 159 | set_ms_source(SI5351_CLK5, SI5351_PLLA); 160 | set_ms_source(SI5351_CLK6, SI5351_PLLB); 161 | set_ms_source(SI5351_CLK7, SI5351_PLLB); 162 | 163 | // Reset the VCXO param 164 | si5351_write(SI5351_VXCO_PARAMETERS_LOW, 0); 165 | si5351_write(SI5351_VXCO_PARAMETERS_MID, 0); 166 | si5351_write(SI5351_VXCO_PARAMETERS_HIGH, 0); 167 | 168 | // Then reset the PLLs 169 | pll_reset(SI5351_PLLA); 170 | pll_reset(SI5351_PLLB); 171 | 172 | // Set initial frequencies 173 | uint8_t i; 174 | for(i = 0; i < 8; i++) 175 | { 176 | clk_freq[i] = 0; 177 | output_enable((enum si5351_clock)i, 0); 178 | clk_first_set[i] = false; 179 | } 180 | } 181 | 182 | /* 183 | * set_freq(uint64_t freq, enum si5351_clock clk) 184 | * 185 | * Sets the clock frequency of the specified CLK output. 186 | * Frequency range of 8 kHz to 150 MHz 187 | * 188 | * freq - Output frequency in Hz 189 | * clk - Clock output 190 | * (use the si5351_clock enum) 191 | */ 192 | uint8_t Si5351::set_freq(uint64_t freq, enum si5351_clock clk) 193 | { 194 | struct Si5351RegSet ms_reg; 195 | uint64_t pll_freq; 196 | uint8_t int_mode = 0; 197 | uint8_t div_by_4 = 0; 198 | uint8_t r_div = 0; 199 | 200 | // Check which Multisynth is being set 201 | if((uint8_t)clk <= (uint8_t)SI5351_CLK5) 202 | { 203 | // MS0 through MS5 logic 204 | // --------------------- 205 | 206 | // Lower bounds check 207 | if(freq > 0 && freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT) 208 | { 209 | freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT; 210 | } 211 | 212 | // Upper bounds check 213 | if(freq > SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT) 214 | { 215 | freq = SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT; 216 | } 217 | 218 | // If requested freq >100 MHz and no other outputs are already >100 MHz, 219 | // we need to recalculate PLLA and then recalculate all other CLK outputs 220 | // on same PLL 221 | if(freq > (SI5351_MULTISYNTH_SHARE_MAX * SI5351_FREQ_MULT)) 222 | { 223 | // Check other clocks on same PLL 224 | uint8_t i; 225 | for(i = 0; i < 6; i++) 226 | { 227 | if(clk_freq[i] > (SI5351_MULTISYNTH_SHARE_MAX * SI5351_FREQ_MULT)) 228 | { 229 | if(i != (uint8_t)clk && pll_assignment[i] == pll_assignment[clk]) 230 | { 231 | return 1; // won't set if any other clks already >100 MHz 232 | } 233 | } 234 | } 235 | 236 | // Enable the output on first set_freq only 237 | if(clk_first_set[(uint8_t)clk] == false) 238 | { 239 | output_enable(clk, 1); 240 | clk_first_set[(uint8_t)clk] = true; 241 | } 242 | 243 | // Set the freq in memory 244 | clk_freq[(uint8_t)clk] = freq; 245 | 246 | // Calculate the proper PLL frequency 247 | pll_freq = multisynth_calc(freq, 0, &ms_reg); 248 | 249 | // Set PLL 250 | set_pll(pll_freq, pll_assignment[clk]); 251 | 252 | // Recalculate params for other synths on same PLL 253 | for(i = 0; i < 6; i++) 254 | { 255 | if(clk_freq[i] != 0) 256 | { 257 | if(pll_assignment[i] == pll_assignment[clk]) 258 | { 259 | struct Si5351RegSet temp_reg; 260 | uint64_t temp_freq; 261 | 262 | // Select the proper R div value 263 | temp_freq = clk_freq[i]; 264 | r_div = select_r_div(&temp_freq); 265 | 266 | multisynth_calc(temp_freq, pll_freq, &temp_reg); 267 | 268 | // If freq > 150 MHz, we need to use DIVBY4 and integer mode 269 | if(temp_freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT) 270 | { 271 | div_by_4 = 1; 272 | int_mode = 1; 273 | } 274 | else 275 | { 276 | div_by_4 = 0; 277 | int_mode = 0; 278 | } 279 | 280 | // Set multisynth registers 281 | set_ms((enum si5351_clock)i, temp_reg, int_mode, r_div, div_by_4); 282 | } 283 | } 284 | } 285 | 286 | // Reset the PLL 287 | pll_reset(pll_assignment[clk]); 288 | } 289 | else 290 | { 291 | clk_freq[(uint8_t)clk] = freq; 292 | 293 | // Enable the output on first set_freq only 294 | if(clk_first_set[(uint8_t)clk] == false) 295 | { 296 | output_enable(clk, 1); 297 | clk_first_set[(uint8_t)clk] = true; 298 | } 299 | 300 | // Select the proper R div value 301 | r_div = select_r_div(&freq); 302 | 303 | // Calculate the synth parameters 304 | if(pll_assignment[clk] == SI5351_PLLA) 305 | { 306 | multisynth_calc(freq, plla_freq, &ms_reg); 307 | } 308 | else 309 | { 310 | multisynth_calc(freq, pllb_freq, &ms_reg); 311 | } 312 | 313 | // Set multisynth registers 314 | set_ms(clk, ms_reg, int_mode, r_div, div_by_4); 315 | 316 | // Reset the PLL 317 | //pll_reset(pll_assignment[clk]); 318 | } 319 | 320 | return 0; 321 | } 322 | else 323 | { 324 | // MS6 and MS7 logic 325 | // ----------------- 326 | 327 | // Lower bounds check 328 | if(freq > 0 && freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT) 329 | { 330 | freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT; 331 | } 332 | 333 | // Upper bounds check 334 | if(freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT) 335 | { 336 | freq = SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT - 1; 337 | } 338 | 339 | // If one of CLK6 or CLK7 is already set when trying to set the other, 340 | // we have to ensure that it will also have an integer division ratio 341 | // with the same PLL, otherwise do not set it. 342 | if(clk == SI5351_CLK6) 343 | { 344 | if(clk_freq[7] != 0) 345 | { 346 | if(pllb_freq % freq == 0) 347 | { 348 | if((pllb_freq / freq) % 2 != 0) 349 | { 350 | // Not an even divide ratio, no bueno 351 | return 1; 352 | } 353 | else 354 | { 355 | // Set the freq in memory 356 | clk_freq[(uint8_t)clk] = freq; 357 | 358 | // Select the proper R div value 359 | r_div = select_r_div_ms67(&freq); 360 | 361 | multisynth67_calc(freq, pllb_freq, &ms_reg); 362 | } 363 | } 364 | else 365 | { 366 | // Not an integer divide ratio, no good 367 | return 1; 368 | } 369 | } 370 | else 371 | { 372 | // No previous assignment, so set PLLB based on CLK6 373 | 374 | // Set the freq in memory 375 | clk_freq[(uint8_t)clk] = freq; 376 | 377 | // Select the proper R div value 378 | r_div = select_r_div_ms67(&freq); 379 | 380 | pll_freq = multisynth67_calc(freq, 0, &ms_reg); 381 | //pllb_freq = pll_freq; 382 | set_pll(pll_freq, SI5351_PLLB); 383 | } 384 | } 385 | else 386 | { 387 | if(clk_freq[6] != 0) 388 | { 389 | if(pllb_freq % freq == 0) 390 | { 391 | if((pllb_freq / freq) % 2 != 0) 392 | { 393 | // Not an even divide ratio, no bueno 394 | return 1; 395 | } 396 | else 397 | { 398 | // Set the freq in memory 399 | clk_freq[(uint8_t)clk] = freq; 400 | 401 | // Select the proper R div value 402 | r_div = select_r_div_ms67(&freq); 403 | 404 | multisynth67_calc(freq, pllb_freq, &ms_reg); 405 | } 406 | } 407 | else 408 | { 409 | // Not an integer divide ratio, no good 410 | return 1; 411 | } 412 | } 413 | else 414 | { 415 | // No previous assignment, so set PLLB based on CLK7 416 | 417 | // Set the freq in memory 418 | clk_freq[(uint8_t)clk] = freq; 419 | 420 | // Select the proper R div value 421 | r_div = select_r_div_ms67(&freq); 422 | 423 | pll_freq = multisynth67_calc(freq, 0, &ms_reg); 424 | //pllb_freq = pll_freq; 425 | set_pll(pll_freq, pll_assignment[clk]); 426 | } 427 | } 428 | 429 | div_by_4 = 0; 430 | int_mode = 0; 431 | 432 | // Set multisynth registers (MS must be set before PLL) 433 | set_ms(clk, ms_reg, int_mode, r_div, div_by_4); 434 | 435 | return 0; 436 | } 437 | } 438 | 439 | /* 440 | * set_freq_manual(uint64_t freq, uint64_t pll_freq, enum si5351_clock clk) 441 | * 442 | * Sets the clock frequency of the specified CLK output using the given PLL 443 | * frequency. You must ensure that the MS is assigned to the correct PLL and 444 | * that the PLL is set to the correct frequency before using this method. 445 | * 446 | * It is important to note that if you use this method, you will have to 447 | * track that all settings are sane yourself. 448 | * 449 | * freq - Output frequency in Hz 450 | * pll_freq - Frequency of the PLL driving the Multisynth in Hz * 100 451 | * clk - Clock output 452 | * (use the si5351_clock enum) 453 | */ 454 | uint8_t Si5351::set_freq_manual(uint64_t freq, uint64_t pll_freq, enum si5351_clock clk) 455 | { 456 | struct Si5351RegSet ms_reg; 457 | uint8_t int_mode = 0; 458 | uint8_t div_by_4 = 0; 459 | 460 | // Lower bounds check 461 | if(freq > 0 && freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT) 462 | { 463 | freq = SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT; 464 | } 465 | 466 | // Upper bounds check 467 | if(freq > SI5351_CLKOUT_MAX_FREQ * SI5351_FREQ_MULT) 468 | { 469 | freq = SI5351_CLKOUT_MAX_FREQ * SI5351_FREQ_MULT; 470 | } 471 | 472 | uint8_t r_div; 473 | 474 | clk_freq[(uint8_t)clk] = freq; 475 | 476 | set_pll(pll_freq, pll_assignment[clk]); 477 | 478 | // Enable the output 479 | output_enable(clk, 1); 480 | 481 | // Select the proper R div value 482 | r_div = select_r_div(&freq); 483 | 484 | // Calculate the synth parameters 485 | multisynth_calc(freq, pll_freq, &ms_reg); 486 | 487 | // If freq > 150 MHz, we need to use DIVBY4 and integer mode 488 | if(freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT) 489 | { 490 | div_by_4 = 1; 491 | int_mode = 1; 492 | } 493 | 494 | // Set multisynth registers (MS must be set before PLL) 495 | set_ms(clk, ms_reg, int_mode, r_div, div_by_4); 496 | 497 | return 0; 498 | } 499 | 500 | /* 501 | * set_pll(uint64_t pll_freq, enum si5351_pll target_pll) 502 | * 503 | * Set the specified PLL to a specific oscillation frequency 504 | * 505 | * pll_freq - Desired PLL frequency in Hz * 100 506 | * target_pll - Which PLL to set 507 | * (use the si5351_pll enum) 508 | */ 509 | void Si5351::set_pll(uint64_t pll_freq, enum si5351_pll target_pll) 510 | { 511 | struct Si5351RegSet pll_reg; 512 | 513 | if(target_pll == SI5351_PLLA) 514 | { 515 | pll_calc(SI5351_PLLA, pll_freq, &pll_reg, ref_correction[plla_ref_osc], 0); 516 | } 517 | else 518 | { 519 | pll_calc(SI5351_PLLB, pll_freq, &pll_reg, ref_correction[pllb_ref_osc], 0); 520 | } 521 | 522 | // Derive the register values to write 523 | 524 | // Prepare an array for parameters to be written to 525 | uint8_t *params = new uint8_t[20]; 526 | uint8_t i = 0; 527 | uint8_t temp; 528 | 529 | // Registers 26-27 530 | temp = ((pll_reg.p3 >> 8) & 0xFF); 531 | params[i++] = temp; 532 | 533 | temp = (uint8_t)(pll_reg.p3 & 0xFF); 534 | params[i++] = temp; 535 | 536 | // Register 28 537 | temp = (uint8_t)((pll_reg.p1 >> 16) & 0x03); 538 | params[i++] = temp; 539 | 540 | // Registers 29-30 541 | temp = (uint8_t)((pll_reg.p1 >> 8) & 0xFF); 542 | params[i++] = temp; 543 | 544 | temp = (uint8_t)(pll_reg.p1 & 0xFF); 545 | params[i++] = temp; 546 | 547 | // Register 31 548 | temp = (uint8_t)((pll_reg.p3 >> 12) & 0xF0); 549 | temp += (uint8_t)((pll_reg.p2 >> 16) & 0x0F); 550 | params[i++] = temp; 551 | 552 | // Registers 32-33 553 | temp = (uint8_t)((pll_reg.p2 >> 8) & 0xFF); 554 | params[i++] = temp; 555 | 556 | temp = (uint8_t)(pll_reg.p2 & 0xFF); 557 | params[i++] = temp; 558 | 559 | // Write the parameters 560 | if(target_pll == SI5351_PLLA) 561 | { 562 | si5351_write_bulk(SI5351_PLLA_PARAMETERS, i, params); 563 | plla_freq = pll_freq; 564 | } 565 | else if(target_pll == SI5351_PLLB) 566 | { 567 | si5351_write_bulk(SI5351_PLLB_PARAMETERS, i, params); 568 | pllb_freq = pll_freq; 569 | } 570 | 571 | delete params; 572 | } 573 | 574 | /* 575 | * set_ms(enum si5351_clock clk, struct Si5351RegSet ms_reg, uint8_t int_mode, uint8_t r_div, uint8_t div_by_4) 576 | * 577 | * Set the specified multisynth parameters. Not normally needed, but public for advanced users. 578 | * 579 | * clk - Clock output 580 | * (use the si5351_clock enum) 581 | * int_mode - Set integer mode 582 | * Set to 1 to enable, 0 to disable 583 | * r_div - Desired r_div ratio 584 | * div_by_4 - Set Divide By 4 mode 585 | * Set to 1 to enable, 0 to disable 586 | */ 587 | void Si5351::set_ms(enum si5351_clock clk, struct Si5351RegSet ms_reg, uint8_t int_mode, uint8_t r_div, uint8_t div_by_4) 588 | { 589 | uint8_t *params = new uint8_t[20]; 590 | uint8_t i = 0; 591 | uint8_t temp; 592 | uint8_t reg_val; 593 | 594 | 595 | if((uint8_t)clk <= (uint8_t)SI5351_CLK5) 596 | { 597 | // Registers 42-43 for CLK0 598 | temp = (uint8_t)((ms_reg.p3 >> 8) & 0xFF); 599 | params[i++] = temp; 600 | 601 | temp = (uint8_t)(ms_reg.p3 & 0xFF); 602 | params[i++] = temp; 603 | 604 | // Register 44 for CLK0 605 | reg_val = si5351_read((SI5351_CLK0_PARAMETERS + 2) + (clk * 8)); 606 | reg_val &= ~(0x03); 607 | temp = reg_val | ((uint8_t)((ms_reg.p1 >> 16) & 0x03)); 608 | params[i++] = temp; 609 | 610 | // Registers 45-46 for CLK0 611 | temp = (uint8_t)((ms_reg.p1 >> 8) & 0xFF); 612 | params[i++] = temp; 613 | 614 | temp = (uint8_t)(ms_reg.p1 & 0xFF); 615 | params[i++] = temp; 616 | 617 | // Register 47 for CLK0 618 | temp = (uint8_t)((ms_reg.p3 >> 12) & 0xF0); 619 | temp += (uint8_t)((ms_reg.p2 >> 16) & 0x0F); 620 | params[i++] = temp; 621 | 622 | // Registers 48-49 for CLK0 623 | temp = (uint8_t)((ms_reg.p2 >> 8) & 0xFF); 624 | params[i++] = temp; 625 | 626 | temp = (uint8_t)(ms_reg.p2 & 0xFF); 627 | params[i++] = temp; 628 | } 629 | else 630 | { 631 | // MS6 and MS7 only use one register 632 | temp = ms_reg.p1; 633 | } 634 | 635 | // Write the parameters 636 | switch(clk) 637 | { 638 | case SI5351_CLK0: 639 | si5351_write_bulk(SI5351_CLK0_PARAMETERS, i, params); 640 | set_int(clk, int_mode); 641 | ms_div(clk, r_div, div_by_4); 642 | break; 643 | case SI5351_CLK1: 644 | si5351_write_bulk(SI5351_CLK1_PARAMETERS, i, params); 645 | set_int(clk, int_mode); 646 | ms_div(clk, r_div, div_by_4); 647 | break; 648 | case SI5351_CLK2: 649 | si5351_write_bulk(SI5351_CLK2_PARAMETERS, i, params); 650 | set_int(clk, int_mode); 651 | ms_div(clk, r_div, div_by_4); 652 | break; 653 | case SI5351_CLK3: 654 | si5351_write_bulk(SI5351_CLK3_PARAMETERS, i, params); 655 | set_int(clk, int_mode); 656 | ms_div(clk, r_div, div_by_4); 657 | break; 658 | case SI5351_CLK4: 659 | si5351_write_bulk(SI5351_CLK4_PARAMETERS, i, params); 660 | set_int(clk, int_mode); 661 | ms_div(clk, r_div, div_by_4); 662 | break; 663 | case SI5351_CLK5: 664 | si5351_write_bulk(SI5351_CLK5_PARAMETERS, i, params); 665 | set_int(clk, int_mode); 666 | ms_div(clk, r_div, div_by_4); 667 | break; 668 | case SI5351_CLK6: 669 | si5351_write(SI5351_CLK6_PARAMETERS, temp); 670 | ms_div(clk, r_div, div_by_4); 671 | break; 672 | case SI5351_CLK7: 673 | si5351_write(SI5351_CLK7_PARAMETERS, temp); 674 | ms_div(clk, r_div, div_by_4); 675 | break; 676 | } 677 | 678 | delete params; 679 | } 680 | 681 | /* 682 | * output_enable(enum si5351_clock clk, uint8_t enable) 683 | * 684 | * Enable or disable a chosen output 685 | * clk - Clock output 686 | * (use the si5351_clock enum) 687 | * enable - Set to 1 to enable, 0 to disable 688 | */ 689 | void Si5351::output_enable(enum si5351_clock clk, uint8_t enable) 690 | { 691 | uint8_t reg_val; 692 | 693 | reg_val = si5351_read(SI5351_OUTPUT_ENABLE_CTRL); 694 | 695 | if(enable == 1) 696 | { 697 | reg_val &= ~(1<<(uint8_t)clk); 698 | } 699 | else 700 | { 701 | reg_val |= (1<<(uint8_t)clk); 702 | } 703 | 704 | si5351_write(SI5351_OUTPUT_ENABLE_CTRL, reg_val); 705 | } 706 | 707 | /* 708 | * drive_strength(enum si5351_clock clk, enum si5351_drive drive) 709 | * 710 | * Sets the drive strength of the specified clock output 711 | * 712 | * clk - Clock output 713 | * (use the si5351_clock enum) 714 | * drive - Desired drive level 715 | * (use the si5351_drive enum) 716 | */ 717 | void Si5351::drive_strength(enum si5351_clock clk, enum si5351_drive drive) 718 | { 719 | uint8_t reg_val; 720 | const uint8_t mask = 0x03; 721 | 722 | reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk); 723 | reg_val &= ~(mask); 724 | 725 | switch(drive) 726 | { 727 | case SI5351_DRIVE_2MA: 728 | reg_val |= 0x00; 729 | break; 730 | case SI5351_DRIVE_4MA: 731 | reg_val |= 0x01; 732 | break; 733 | case SI5351_DRIVE_6MA: 734 | reg_val |= 0x02; 735 | break; 736 | case SI5351_DRIVE_8MA: 737 | reg_val |= 0x03; 738 | break; 739 | default: 740 | break; 741 | } 742 | 743 | si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val); 744 | } 745 | 746 | /* 747 | * update_status(void) 748 | * 749 | * Call this to update the status structs, then access them 750 | * via the dev_status and dev_int_status global members. 751 | * 752 | * See the header file for the struct definitions. These 753 | * correspond to the flag names for registers 0 and 1 in 754 | * the Si5351 datasheet. 755 | */ 756 | void Si5351::update_status(void) 757 | { 758 | update_sys_status(&dev_status); 759 | update_int_status(&dev_int_status); 760 | } 761 | 762 | /* 763 | * set_correction(int32_t corr, enum si5351_pll_input ref_osc) 764 | * 765 | * corr - Correction factor in ppb 766 | * ref_osc - Desired reference oscillator 767 | * (use the si5351_pll_input enum) 768 | * 769 | * Use this to set the oscillator correction factor. 770 | * This value is a signed 32-bit integer of the 771 | * parts-per-billion value that the actual oscillation 772 | * frequency deviates from the specified frequency. 773 | * 774 | * The frequency calibration is done as a one-time procedure. 775 | * Any desired test frequency within the normal range of the 776 | * Si5351 should be set, then the actual output frequency 777 | * should be measured as accurately as possible. The 778 | * difference between the measured and specified frequencies 779 | * should be calculated in Hertz, then multiplied by 10 in 780 | * order to get the parts-per-billion value. 781 | * 782 | * Since the Si5351 itself has an intrinsic 0 PPM error, this 783 | * correction factor is good across the entire tuning range of 784 | * the Si5351. Once this calibration is done accurately, it 785 | * should not have to be done again for the same Si5351 and 786 | * crystal. 787 | */ 788 | void Si5351::set_correction(int32_t corr, enum si5351_pll_input ref_osc) 789 | { 790 | ref_correction[(uint8_t)ref_osc] = corr; 791 | 792 | // Recalculate and set PLL freqs based on correction value 793 | set_pll(plla_freq, SI5351_PLLA); 794 | set_pll(pllb_freq, SI5351_PLLB); 795 | } 796 | 797 | /* 798 | * set_phase(enum si5351_clock clk, uint8_t phase) 799 | * 800 | * clk - Clock output 801 | * (use the si5351_clock enum) 802 | * phase - 7-bit phase word 803 | * (in units of VCO/4 period) 804 | * 805 | * Write the 7-bit phase register. This must be used 806 | * with a user-set PLL frequency so that the user can 807 | * calculate the proper tuning word based on the PLL period. 808 | */ 809 | void Si5351::set_phase(enum si5351_clock clk, uint8_t phase) 810 | { 811 | // Mask off the upper bit since it is reserved 812 | phase = phase & 0b01111111; 813 | 814 | si5351_write(SI5351_CLK0_PHASE_OFFSET + (uint8_t)clk, phase); 815 | } 816 | 817 | /* 818 | * get_correction(enum si5351_pll_input ref_osc) 819 | * 820 | * ref_osc - Desired reference oscillator 821 | * 0: crystal oscillator (XO) 822 | * 1: external clock input (CLKIN) 823 | * 824 | * Returns the oscillator correction factor stored 825 | * in RAM. 826 | */ 827 | int32_t Si5351::get_correction(enum si5351_pll_input ref_osc) 828 | { 829 | return ref_correction[(uint8_t)ref_osc]; 830 | } 831 | 832 | /* 833 | * pll_reset(enum si5351_pll target_pll) 834 | * 835 | * target_pll - Which PLL to reset 836 | * (use the si5351_pll enum) 837 | * 838 | * Apply a reset to the indicated PLL. 839 | */ 840 | void Si5351::pll_reset(enum si5351_pll target_pll) 841 | { 842 | if(target_pll == SI5351_PLLA) 843 | { 844 | si5351_write(SI5351_PLL_RESET, SI5351_PLL_RESET_A); 845 | } 846 | else if(target_pll == SI5351_PLLB) 847 | { 848 | si5351_write(SI5351_PLL_RESET, SI5351_PLL_RESET_B); 849 | } 850 | } 851 | 852 | /* 853 | * set_ms_source(enum si5351_clock clk, enum si5351_pll pll) 854 | * 855 | * clk - Clock output 856 | * (use the si5351_clock enum) 857 | * pll - Which PLL to use as the source 858 | * (use the si5351_pll enum) 859 | * 860 | * Set the desired PLL source for a multisynth. 861 | */ 862 | void Si5351::set_ms_source(enum si5351_clock clk, enum si5351_pll pll) 863 | { 864 | uint8_t reg_val; 865 | 866 | reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk); 867 | 868 | if(pll == SI5351_PLLA) 869 | { 870 | reg_val &= ~(SI5351_CLK_PLL_SELECT); 871 | } 872 | else if(pll == SI5351_PLLB) 873 | { 874 | reg_val |= SI5351_CLK_PLL_SELECT; 875 | } 876 | 877 | si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val); 878 | 879 | pll_assignment[(uint8_t)clk] = pll; 880 | } 881 | 882 | /* 883 | * set_int(enum si5351_clock clk, uint8_t int_mode) 884 | * 885 | * clk - Clock output 886 | * (use the si5351_clock enum) 887 | * enable - Set to 1 to enable, 0 to disable 888 | * 889 | * Set the indicated multisynth into integer mode. 890 | */ 891 | void Si5351::set_int(enum si5351_clock clk, uint8_t enable) 892 | { 893 | uint8_t reg_val; 894 | reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk); 895 | 896 | if(enable == 1) 897 | { 898 | reg_val |= (SI5351_CLK_INTEGER_MODE); 899 | } 900 | else 901 | { 902 | reg_val &= ~(SI5351_CLK_INTEGER_MODE); 903 | } 904 | 905 | si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val); 906 | 907 | // Integer mode indication 908 | /* 909 | switch(clk) 910 | { 911 | case SI5351_CLK0: 912 | clk0_int_mode = enable; 913 | break; 914 | case SI5351_CLK1: 915 | clk1_int_mode = enable; 916 | break; 917 | case SI5351_CLK2: 918 | clk2_int_mode = enable; 919 | break; 920 | default: 921 | break; 922 | } 923 | */ 924 | } 925 | 926 | /* 927 | * set_clock_pwr(enum si5351_clock clk, uint8_t pwr) 928 | * 929 | * clk - Clock output 930 | * (use the si5351_clock enum) 931 | * pwr - Set to 1 to enable, 0 to disable 932 | * 933 | * Enable or disable power to a clock output (a power 934 | * saving feature). 935 | */ 936 | void Si5351::set_clock_pwr(enum si5351_clock clk, uint8_t pwr) 937 | { 938 | uint8_t reg_val; //, reg; 939 | reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk); 940 | 941 | if(pwr == 1) 942 | { 943 | reg_val &= 0b01111111; 944 | } 945 | else 946 | { 947 | reg_val |= 0b10000000; 948 | } 949 | 950 | si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val); 951 | } 952 | 953 | /* 954 | * set_clock_invert(enum si5351_clock clk, uint8_t inv) 955 | * 956 | * clk - Clock output 957 | * (use the si5351_clock enum) 958 | * inv - Set to 1 to enable, 0 to disable 959 | * 960 | * Enable to invert the clock output waveform. 961 | */ 962 | void Si5351::set_clock_invert(enum si5351_clock clk, uint8_t inv) 963 | { 964 | uint8_t reg_val; 965 | reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk); 966 | 967 | if(inv == 1) 968 | { 969 | reg_val |= (SI5351_CLK_INVERT); 970 | } 971 | else 972 | { 973 | reg_val &= ~(SI5351_CLK_INVERT); 974 | } 975 | 976 | si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val); 977 | } 978 | 979 | /* 980 | * set_clock_source(enum si5351_clock clk, enum si5351_clock_source src) 981 | * 982 | * clk - Clock output 983 | * (use the si5351_clock enum) 984 | * src - Which clock source to use for the multisynth 985 | * (use the si5351_clock_source enum) 986 | * 987 | * Set the clock source for a multisynth (based on the options 988 | * presented for Registers 16-23 in the Silicon Labs AN619 document). 989 | * Choices are XTAL, CLKIN, MS0, or the multisynth associated with 990 | * the clock output. 991 | */ 992 | void Si5351::set_clock_source(enum si5351_clock clk, enum si5351_clock_source src) 993 | { 994 | uint8_t reg_val; 995 | reg_val = si5351_read(SI5351_CLK0_CTRL + (uint8_t)clk); 996 | 997 | // Clear the bits first 998 | reg_val &= ~(SI5351_CLK_INPUT_MASK); 999 | 1000 | switch(src) 1001 | { 1002 | case SI5351_CLK_SRC_XTAL: 1003 | reg_val |= (SI5351_CLK_INPUT_XTAL); 1004 | break; 1005 | case SI5351_CLK_SRC_CLKIN: 1006 | reg_val |= (SI5351_CLK_INPUT_CLKIN); 1007 | break; 1008 | case SI5351_CLK_SRC_MS0: 1009 | if(clk == SI5351_CLK0) 1010 | { 1011 | return; 1012 | } 1013 | 1014 | reg_val |= (SI5351_CLK_INPUT_MULTISYNTH_0_4); 1015 | break; 1016 | case SI5351_CLK_SRC_MS: 1017 | reg_val |= (SI5351_CLK_INPUT_MULTISYNTH_N); 1018 | break; 1019 | default: 1020 | return; 1021 | } 1022 | 1023 | si5351_write(SI5351_CLK0_CTRL + (uint8_t)clk, reg_val); 1024 | } 1025 | 1026 | /* 1027 | * set_clock_disable(enum si5351_clock clk, enum si5351_clock_disable dis_state) 1028 | * 1029 | * clk - Clock output 1030 | * (use the si5351_clock enum) 1031 | * dis_state - Desired state of the output upon disable 1032 | * (use the si5351_clock_disable enum) 1033 | * 1034 | * Set the state of the clock output when it is disabled. Per page 27 1035 | * of AN619 (Registers 24 and 25), there are four possible values: low, 1036 | * high, high impedance, and never disabled. 1037 | */ 1038 | void Si5351::set_clock_disable(enum si5351_clock clk, enum si5351_clock_disable dis_state) 1039 | { 1040 | uint8_t reg_val, reg; 1041 | 1042 | if (clk >= SI5351_CLK0 && clk <= SI5351_CLK3) 1043 | { 1044 | reg = SI5351_CLK3_0_DISABLE_STATE; 1045 | } 1046 | else if(clk >= SI5351_CLK4 && clk <= SI5351_CLK7) 1047 | { 1048 | reg = SI5351_CLK7_4_DISABLE_STATE; 1049 | } 1050 | else return; 1051 | 1052 | reg_val = si5351_read(reg); 1053 | 1054 | if (clk >= SI5351_CLK0 && clk <= SI5351_CLK3) 1055 | { 1056 | reg_val &= ~(0b11 << (clk * 2)); 1057 | reg_val |= dis_state << (clk * 2); 1058 | } 1059 | else if(clk >= SI5351_CLK4 && clk <= SI5351_CLK7) 1060 | { 1061 | reg_val &= ~(0b11 << ((clk - 4) * 2)); 1062 | reg_val |= dis_state << ((clk - 4) * 2); 1063 | } 1064 | 1065 | si5351_write(reg, reg_val); 1066 | } 1067 | 1068 | /* 1069 | * set_clock_fanout(enum si5351_clock_fanout fanout, uint8_t enable) 1070 | * 1071 | * fanout - Desired clock fanout 1072 | * (use the si5351_clock_fanout enum) 1073 | * enable - Set to 1 to enable, 0 to disable 1074 | * 1075 | * Use this function to enable or disable the clock fanout options 1076 | * for individual clock outputs. If you intend to output the XO or 1077 | * CLKIN on the clock outputs, enable this first. 1078 | * 1079 | * By default, only the Multisynth fanout is enabled at startup. 1080 | */ 1081 | void Si5351::set_clock_fanout(enum si5351_clock_fanout fanout, uint8_t enable) 1082 | { 1083 | uint8_t reg_val; 1084 | reg_val = si5351_read(SI5351_FANOUT_ENABLE); 1085 | 1086 | switch(fanout) 1087 | { 1088 | case SI5351_FANOUT_CLKIN: 1089 | if(enable) 1090 | { 1091 | reg_val |= SI5351_CLKIN_ENABLE; 1092 | } 1093 | else 1094 | { 1095 | reg_val &= ~(SI5351_CLKIN_ENABLE); 1096 | } 1097 | break; 1098 | case SI5351_FANOUT_XO: 1099 | if(enable) 1100 | { 1101 | reg_val |= SI5351_XTAL_ENABLE; 1102 | } 1103 | else 1104 | { 1105 | reg_val &= ~(SI5351_XTAL_ENABLE); 1106 | } 1107 | break; 1108 | case SI5351_FANOUT_MS: 1109 | if(enable) 1110 | { 1111 | reg_val |= SI5351_MULTISYNTH_ENABLE; 1112 | } 1113 | else 1114 | { 1115 | reg_val &= ~(SI5351_MULTISYNTH_ENABLE); 1116 | } 1117 | break; 1118 | } 1119 | 1120 | si5351_write(SI5351_FANOUT_ENABLE, reg_val); 1121 | } 1122 | 1123 | /* 1124 | * set_pll_input(enum si5351_pll pll, enum si5351_pll_input input) 1125 | * 1126 | * pll - Which PLL to use as the source 1127 | * (use the si5351_pll enum) 1128 | * input - Which reference oscillator to use as PLL input 1129 | * (use the si5351_pll_input enum) 1130 | * 1131 | * Set the desired reference oscillator source for the given PLL. 1132 | */ 1133 | void Si5351::set_pll_input(enum si5351_pll pll, enum si5351_pll_input input) 1134 | { 1135 | uint8_t reg_val; 1136 | reg_val = si5351_read(SI5351_PLL_INPUT_SOURCE); 1137 | 1138 | // Clear the bits first 1139 | //reg_val &= ~(SI5351_CLKIN_DIV_MASK); 1140 | 1141 | switch(pll) 1142 | { 1143 | case SI5351_PLLA: 1144 | if(input == SI5351_PLL_INPUT_CLKIN) 1145 | { 1146 | reg_val |= SI5351_PLLA_SOURCE; 1147 | reg_val |= clkin_div; 1148 | plla_ref_osc = SI5351_PLL_INPUT_CLKIN; 1149 | } 1150 | else 1151 | { 1152 | reg_val &= ~(SI5351_PLLA_SOURCE); 1153 | plla_ref_osc = SI5351_PLL_INPUT_XO; 1154 | } 1155 | break; 1156 | case SI5351_PLLB: 1157 | if(input == SI5351_PLL_INPUT_CLKIN) 1158 | { 1159 | reg_val |= SI5351_PLLB_SOURCE; 1160 | reg_val |= clkin_div; 1161 | pllb_ref_osc = SI5351_PLL_INPUT_CLKIN; 1162 | } 1163 | else 1164 | { 1165 | reg_val &= ~(SI5351_PLLB_SOURCE); 1166 | pllb_ref_osc = SI5351_PLL_INPUT_XO; 1167 | } 1168 | break; 1169 | default: 1170 | return; 1171 | } 1172 | 1173 | si5351_write(SI5351_PLL_INPUT_SOURCE, reg_val); 1174 | 1175 | set_pll(plla_freq, SI5351_PLLA); 1176 | set_pll(pllb_freq, SI5351_PLLB); 1177 | } 1178 | 1179 | /* 1180 | * set_vcxo(uint64_t pll_freq, uint8_t ppm) 1181 | * 1182 | * pll_freq - Desired PLL base frequency in Hz * 100 1183 | * ppm - VCXO pull limit in ppm 1184 | * 1185 | * Set the parameters for the VCXO on the Si5351B. 1186 | */ 1187 | void Si5351::set_vcxo(uint64_t pll_freq, uint8_t ppm) 1188 | { 1189 | struct Si5351RegSet pll_reg; 1190 | uint64_t vcxo_param; 1191 | 1192 | // Bounds check 1193 | if(ppm < SI5351_VCXO_PULL_MIN) 1194 | { 1195 | ppm = SI5351_VCXO_PULL_MIN; 1196 | } 1197 | 1198 | if(ppm > SI5351_VCXO_PULL_MAX) 1199 | { 1200 | ppm = SI5351_VCXO_PULL_MAX; 1201 | } 1202 | 1203 | // Set PLLB params 1204 | vcxo_param = pll_calc(SI5351_PLLB, pll_freq, &pll_reg, ref_correction[pllb_ref_osc], 1); 1205 | 1206 | // Derive the register values to write 1207 | 1208 | // Prepare an array for parameters to be written to 1209 | uint8_t *params = new uint8_t[20]; 1210 | uint8_t i = 0; 1211 | uint8_t temp; 1212 | 1213 | // Registers 26-27 1214 | temp = ((pll_reg.p3 >> 8) & 0xFF); 1215 | params[i++] = temp; 1216 | 1217 | temp = (uint8_t)(pll_reg.p3 & 0xFF); 1218 | params[i++] = temp; 1219 | 1220 | // Register 28 1221 | temp = (uint8_t)((pll_reg.p1 >> 16) & 0x03); 1222 | params[i++] = temp; 1223 | 1224 | // Registers 29-30 1225 | temp = (uint8_t)((pll_reg.p1 >> 8) & 0xFF); 1226 | params[i++] = temp; 1227 | 1228 | temp = (uint8_t)(pll_reg.p1 & 0xFF); 1229 | params[i++] = temp; 1230 | 1231 | // Register 31 1232 | temp = (uint8_t)((pll_reg.p3 >> 12) & 0xF0); 1233 | temp += (uint8_t)((pll_reg.p2 >> 16) & 0x0F); 1234 | params[i++] = temp; 1235 | 1236 | // Registers 32-33 1237 | temp = (uint8_t)((pll_reg.p2 >> 8) & 0xFF); 1238 | params[i++] = temp; 1239 | 1240 | temp = (uint8_t)(pll_reg.p2 & 0xFF); 1241 | params[i++] = temp; 1242 | 1243 | // Write the parameters 1244 | si5351_write_bulk(SI5351_PLLB_PARAMETERS, i, params); 1245 | 1246 | delete params; 1247 | 1248 | // Write the VCXO parameters 1249 | vcxo_param = ((vcxo_param * ppm * SI5351_VCXO_MARGIN) / 100ULL) / 1000000ULL; 1250 | 1251 | temp = (uint8_t)(vcxo_param & 0xFF); 1252 | si5351_write(SI5351_VXCO_PARAMETERS_LOW, temp); 1253 | 1254 | temp = (uint8_t)((vcxo_param >> 8) & 0xFF); 1255 | si5351_write(SI5351_VXCO_PARAMETERS_MID, temp); 1256 | 1257 | temp = (uint8_t)((vcxo_param >> 16) & 0x3F); 1258 | si5351_write(SI5351_VXCO_PARAMETERS_HIGH, temp); 1259 | } 1260 | 1261 | /* 1262 | * set_ref_freq(uint32_t ref_freq, enum si5351_pll_input ref_osc) 1263 | * 1264 | * ref_freq - Reference oscillator frequency in Hz 1265 | * ref_osc - Which reference oscillator frequency to set 1266 | * (use the si5351_pll_input enum) 1267 | * 1268 | * Set the reference frequency value for the desired reference oscillator 1269 | */ 1270 | void Si5351::set_ref_freq(uint32_t ref_freq, enum si5351_pll_input ref_osc) 1271 | { 1272 | // uint8_t reg_val; 1273 | //reg_val = si5351_read(SI5351_PLL_INPUT_SOURCE); 1274 | 1275 | // Clear the bits first 1276 | //reg_val &= ~(SI5351_CLKIN_DIV_MASK); 1277 | 1278 | if(ref_freq <= 30000000UL) 1279 | { 1280 | xtal_freq[(uint8_t)ref_osc] = ref_freq; 1281 | //reg_val |= SI5351_CLKIN_DIV_1; 1282 | if(ref_osc == SI5351_PLL_INPUT_CLKIN) 1283 | { 1284 | clkin_div = SI5351_CLKIN_DIV_1; 1285 | } 1286 | } 1287 | else if(ref_freq > 30000000UL && ref_freq <= 60000000UL) 1288 | { 1289 | xtal_freq[(uint8_t)ref_osc] = ref_freq / 2; 1290 | //reg_val |= SI5351_CLKIN_DIV_2; 1291 | if(ref_osc == SI5351_PLL_INPUT_CLKIN) 1292 | { 1293 | clkin_div = SI5351_CLKIN_DIV_2; 1294 | } 1295 | } 1296 | else if(ref_freq > 60000000UL && ref_freq <= 100000000UL) 1297 | { 1298 | xtal_freq[(uint8_t)ref_osc] = ref_freq / 4; 1299 | //reg_val |= SI5351_CLKIN_DIV_4; 1300 | if(ref_osc == SI5351_PLL_INPUT_CLKIN) 1301 | { 1302 | clkin_div = SI5351_CLKIN_DIV_4; 1303 | } 1304 | } 1305 | else 1306 | { 1307 | //reg_val |= SI5351_CLKIN_DIV_1; 1308 | } 1309 | 1310 | //si5351_write(SI5351_PLL_INPUT_SOURCE, reg_val); 1311 | } 1312 | 1313 | uint8_t Si5351::si5351_write_bulk(uint8_t addr, uint8_t bytes, uint8_t *data) 1314 | { 1315 | Wire.beginTransmission(i2c_bus_addr); 1316 | Wire.write(addr); 1317 | for(int i = 0; i < bytes; i++) 1318 | { 1319 | Wire.write(data[i]); 1320 | } 1321 | return Wire.endTransmission(); 1322 | 1323 | } 1324 | 1325 | uint8_t Si5351::si5351_write(uint8_t addr, uint8_t data) 1326 | { 1327 | Wire.beginTransmission(i2c_bus_addr); 1328 | Wire.write(addr); 1329 | Wire.write(data); 1330 | return Wire.endTransmission(); 1331 | } 1332 | 1333 | uint8_t Si5351::si5351_read(uint8_t addr) 1334 | { 1335 | uint8_t reg_val = 0; 1336 | 1337 | Wire.beginTransmission(i2c_bus_addr); 1338 | Wire.write(addr); 1339 | Wire.endTransmission(); 1340 | 1341 | Wire.requestFrom(i2c_bus_addr, (uint8_t)1); 1342 | 1343 | while(Wire.available()) 1344 | { 1345 | reg_val = Wire.read(); 1346 | } 1347 | 1348 | return reg_val; 1349 | } 1350 | 1351 | /*********************/ 1352 | /* Private functions */ 1353 | /*********************/ 1354 | 1355 | uint64_t Si5351::pll_calc(enum si5351_pll pll, uint64_t freq, struct Si5351RegSet *reg, int32_t correction, uint8_t vcxo) 1356 | { 1357 | uint64_t ref_freq; 1358 | if(pll == SI5351_PLLA) 1359 | { 1360 | ref_freq = xtal_freq[(uint8_t)plla_ref_osc] * SI5351_FREQ_MULT; 1361 | } 1362 | else 1363 | { 1364 | ref_freq = xtal_freq[(uint8_t)pllb_ref_osc] * SI5351_FREQ_MULT; 1365 | } 1366 | //ref_freq = 15974400ULL * SI5351_FREQ_MULT; 1367 | uint32_t a, b, c, p1, p2, p3; 1368 | uint64_t lltmp; //, denom; 1369 | 1370 | // Factor calibration value into nominal crystal frequency 1371 | // Measured in parts-per-billion 1372 | 1373 | ref_freq = ref_freq + (int32_t)((((((int64_t)correction) << 31) / 1000000000LL) * ref_freq) >> 31); 1374 | 1375 | // PLL bounds checking 1376 | if (freq < SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT) 1377 | { 1378 | freq = SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT; 1379 | } 1380 | if (freq > SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT) 1381 | { 1382 | freq = SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT; 1383 | } 1384 | 1385 | // Determine integer part of feedback equation 1386 | a = freq / ref_freq; 1387 | 1388 | if (a < SI5351_PLL_A_MIN) 1389 | { 1390 | freq = ref_freq * SI5351_PLL_A_MIN; 1391 | } 1392 | if (a > SI5351_PLL_A_MAX) 1393 | { 1394 | freq = ref_freq * SI5351_PLL_A_MAX; 1395 | } 1396 | 1397 | // Find best approximation for b/c = fVCO mod fIN 1398 | // denom = 1000ULL * 1000ULL; 1399 | // lltmp = freq % ref_freq; 1400 | // lltmp *= denom; 1401 | // do_div(lltmp, ref_freq); 1402 | 1403 | //b = (((uint64_t)(freq % ref_freq)) * RFRAC_DENOM) / ref_freq; 1404 | if(vcxo) 1405 | { 1406 | b = (((uint64_t)(freq % ref_freq)) * 1000000ULL) / ref_freq; 1407 | c = 1000000ULL; 1408 | } 1409 | else 1410 | { 1411 | b = (((uint64_t)(freq % ref_freq)) * RFRAC_DENOM) / ref_freq; 1412 | c = b ? RFRAC_DENOM : 1; 1413 | } 1414 | 1415 | // Calculate parameters 1416 | p1 = 128 * a + ((128 * b) / c) - 512; 1417 | p2 = 128 * b - c * ((128 * b) / c); 1418 | p3 = c; 1419 | 1420 | // Recalculate frequency as fIN * (a + b/c) 1421 | lltmp = ref_freq; 1422 | lltmp *= b; 1423 | do_div(lltmp, c); 1424 | freq = lltmp; 1425 | freq += ref_freq * a; 1426 | 1427 | reg->p1 = p1; 1428 | reg->p2 = p2; 1429 | reg->p3 = p3; 1430 | 1431 | if(vcxo) 1432 | { 1433 | return (uint64_t)(128 * a * 1000000ULL + b); 1434 | } 1435 | else 1436 | { 1437 | return freq; 1438 | } 1439 | } 1440 | 1441 | uint64_t Si5351::multisynth_calc(uint64_t freq, uint64_t pll_freq, struct Si5351RegSet *reg) 1442 | { 1443 | uint64_t lltmp; 1444 | uint32_t a, b, c, p1, p2, p3; 1445 | uint8_t divby4 = 0; 1446 | uint8_t ret_val = 0; 1447 | 1448 | // Multisynth bounds checking 1449 | if (freq > SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT) 1450 | { 1451 | freq = SI5351_MULTISYNTH_MAX_FREQ * SI5351_FREQ_MULT; 1452 | } 1453 | if (freq < SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT) 1454 | { 1455 | freq = SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT; 1456 | } 1457 | 1458 | if (freq >= SI5351_MULTISYNTH_DIVBY4_FREQ * SI5351_FREQ_MULT) 1459 | { 1460 | divby4 = 1; 1461 | } 1462 | 1463 | if(pll_freq == 0) 1464 | { 1465 | // Find largest integer divider for max 1466 | // VCO frequency and given target frequency 1467 | if(divby4 == 0) 1468 | { 1469 | lltmp = SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT; // margin needed? 1470 | do_div(lltmp, freq); 1471 | if(lltmp == 5) 1472 | { 1473 | lltmp = 4; 1474 | } 1475 | else if(lltmp == 7) 1476 | { 1477 | lltmp = 6; 1478 | } 1479 | a = (uint32_t)lltmp; 1480 | } 1481 | else 1482 | { 1483 | a = 4; 1484 | } 1485 | 1486 | b = 0; 1487 | c = 1; 1488 | pll_freq = a * freq; 1489 | } 1490 | else 1491 | { 1492 | // Preset PLL, so return the actual freq for these params instead of PLL freq 1493 | ret_val = 1; 1494 | 1495 | // Determine integer part of feedback equation 1496 | a = pll_freq / freq; 1497 | 1498 | if (a < SI5351_MULTISYNTH_A_MIN) 1499 | { 1500 | freq = pll_freq / SI5351_MULTISYNTH_A_MIN; 1501 | } 1502 | if (a > SI5351_MULTISYNTH_A_MAX) 1503 | { 1504 | freq = pll_freq / SI5351_MULTISYNTH_A_MAX; 1505 | } 1506 | 1507 | b = (pll_freq % freq * RFRAC_DENOM) / freq; 1508 | c = b ? RFRAC_DENOM : 1; 1509 | } 1510 | 1511 | // Calculate parameters 1512 | if (divby4 == 1) 1513 | { 1514 | p3 = 1; 1515 | p2 = 0; 1516 | p1 = 0; 1517 | } 1518 | else 1519 | { 1520 | p1 = 128 * a + ((128 * b) / c) - 512; 1521 | p2 = 128 * b - c * ((128 * b) / c); 1522 | p3 = c; 1523 | } 1524 | 1525 | reg->p1 = p1; 1526 | reg->p2 = p2; 1527 | reg->p3 = p3; 1528 | 1529 | if(ret_val == 0) 1530 | { 1531 | return pll_freq; 1532 | } 1533 | else 1534 | { 1535 | return freq; 1536 | } 1537 | } 1538 | 1539 | uint64_t Si5351::multisynth67_calc(uint64_t freq, uint64_t pll_freq, struct Si5351RegSet *reg) 1540 | { 1541 | //uint8_t p1; 1542 | // uint8_t ret_val = 0; 1543 | uint32_t a; 1544 | uint64_t lltmp; 1545 | 1546 | // Multisynth bounds checking 1547 | if(freq > SI5351_MULTISYNTH67_MAX_FREQ * SI5351_FREQ_MULT) 1548 | { 1549 | freq = SI5351_MULTISYNTH67_MAX_FREQ * SI5351_FREQ_MULT; 1550 | } 1551 | if(freq < SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT) 1552 | { 1553 | freq = SI5351_MULTISYNTH_MIN_FREQ * SI5351_FREQ_MULT; 1554 | } 1555 | 1556 | if(pll_freq == 0) 1557 | { 1558 | // Find largest integer divider for max 1559 | // VCO frequency and given target frequency 1560 | lltmp = (SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT) - 100000000UL; // margin needed? 1561 | do_div(lltmp, freq); 1562 | a = (uint32_t)lltmp; 1563 | 1564 | // Divisor has to be even 1565 | if(a % 2 != 0) 1566 | { 1567 | a++; 1568 | } 1569 | 1570 | // Divisor bounds check 1571 | if(a < SI5351_MULTISYNTH_A_MIN) 1572 | { 1573 | a = SI5351_MULTISYNTH_A_MIN; 1574 | } 1575 | if(a > SI5351_MULTISYNTH67_A_MAX) 1576 | { 1577 | a = SI5351_MULTISYNTH67_A_MAX; 1578 | } 1579 | 1580 | pll_freq = a * freq; 1581 | 1582 | // PLL bounds checking 1583 | if(pll_freq > (SI5351_PLL_VCO_MAX * SI5351_FREQ_MULT)) 1584 | { 1585 | a -= 2; 1586 | pll_freq = a * freq; 1587 | } 1588 | else if(pll_freq < (SI5351_PLL_VCO_MIN * SI5351_FREQ_MULT)) 1589 | { 1590 | a += 2; 1591 | pll_freq = a * freq; 1592 | } 1593 | 1594 | reg->p1 = (uint8_t)a; 1595 | reg->p2 = 0; 1596 | reg->p3 = 0; 1597 | return pll_freq; 1598 | } 1599 | else 1600 | { 1601 | // Multisynth frequency must be integer division of PLL 1602 | if(pll_freq % freq) 1603 | { 1604 | // No good 1605 | return 0; 1606 | } 1607 | else 1608 | { 1609 | a = pll_freq / freq; 1610 | 1611 | // Division ratio bounds check 1612 | if(a < SI5351_MULTISYNTH_A_MIN || a > SI5351_MULTISYNTH67_A_MAX) 1613 | { 1614 | // No bueno 1615 | return 0; 1616 | } 1617 | else 1618 | { 1619 | reg->p1 = (uint8_t)a; 1620 | reg->p2 = 0; 1621 | reg->p3 = 0; 1622 | return 1; 1623 | } 1624 | } 1625 | } 1626 | } 1627 | 1628 | void Si5351::update_sys_status(struct Si5351Status *status) 1629 | { 1630 | uint8_t reg_val = 0; 1631 | 1632 | reg_val = si5351_read(SI5351_DEVICE_STATUS); 1633 | 1634 | // Parse the register 1635 | status->SYS_INIT = (reg_val >> 7) & 0x01; 1636 | status->LOL_B = (reg_val >> 6) & 0x01; 1637 | status->LOL_A = (reg_val >> 5) & 0x01; 1638 | status->LOS = (reg_val >> 4) & 0x01; 1639 | status->REVID = reg_val & 0x03; 1640 | } 1641 | 1642 | void Si5351::update_int_status(struct Si5351IntStatus *int_status) 1643 | { 1644 | uint8_t reg_val = 0; 1645 | 1646 | reg_val = si5351_read(SI5351_INTERRUPT_STATUS); 1647 | 1648 | // Parse the register 1649 | int_status->SYS_INIT_STKY = (reg_val >> 7) & 0x01; 1650 | int_status->LOL_B_STKY = (reg_val >> 6) & 0x01; 1651 | int_status->LOL_A_STKY = (reg_val >> 5) & 0x01; 1652 | int_status->LOS_STKY = (reg_val >> 4) & 0x01; 1653 | } 1654 | 1655 | void Si5351::ms_div(enum si5351_clock clk, uint8_t r_div, uint8_t div_by_4) 1656 | { 1657 | uint8_t reg_val = 0; 1658 | uint8_t reg_addr = 0; 1659 | 1660 | switch(clk) 1661 | { 1662 | case SI5351_CLK0: 1663 | reg_addr = SI5351_CLK0_PARAMETERS + 2; 1664 | break; 1665 | case SI5351_CLK1: 1666 | reg_addr = SI5351_CLK1_PARAMETERS + 2; 1667 | break; 1668 | case SI5351_CLK2: 1669 | reg_addr = SI5351_CLK2_PARAMETERS + 2; 1670 | break; 1671 | case SI5351_CLK3: 1672 | reg_addr = SI5351_CLK3_PARAMETERS + 2; 1673 | break; 1674 | case SI5351_CLK4: 1675 | reg_addr = SI5351_CLK4_PARAMETERS + 2; 1676 | break; 1677 | case SI5351_CLK5: 1678 | reg_addr = SI5351_CLK5_PARAMETERS + 2; 1679 | break; 1680 | case SI5351_CLK6: 1681 | reg_addr = SI5351_CLK6_7_OUTPUT_DIVIDER; 1682 | break; 1683 | case SI5351_CLK7: 1684 | reg_addr = SI5351_CLK6_7_OUTPUT_DIVIDER; 1685 | break; 1686 | } 1687 | 1688 | reg_val = si5351_read(reg_addr); 1689 | 1690 | if(clk <= (uint8_t)SI5351_CLK5) 1691 | { 1692 | // Clear the relevant bits 1693 | reg_val &= ~(0x7c); 1694 | 1695 | if(div_by_4 == 0) 1696 | { 1697 | reg_val &= ~(SI5351_OUTPUT_CLK_DIVBY4); 1698 | } 1699 | else 1700 | { 1701 | reg_val |= (SI5351_OUTPUT_CLK_DIVBY4); 1702 | } 1703 | 1704 | reg_val |= (r_div << SI5351_OUTPUT_CLK_DIV_SHIFT); 1705 | } 1706 | else if(clk == SI5351_CLK6) 1707 | { 1708 | // Clear the relevant bits 1709 | reg_val &= ~(0x07); 1710 | 1711 | reg_val |= r_div; 1712 | } 1713 | else if(clk == SI5351_CLK7) 1714 | { 1715 | // Clear the relevant bits 1716 | reg_val &= ~(0x70); 1717 | 1718 | reg_val |= (r_div << SI5351_OUTPUT_CLK_DIV_SHIFT); 1719 | } 1720 | 1721 | si5351_write(reg_addr, reg_val); 1722 | } 1723 | 1724 | uint8_t Si5351::select_r_div(uint64_t *freq) 1725 | { 1726 | uint8_t r_div = SI5351_OUTPUT_CLK_DIV_1; 1727 | 1728 | // Choose the correct R divider 1729 | if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 2)) 1730 | { 1731 | r_div = SI5351_OUTPUT_CLK_DIV_128; 1732 | *freq *= 128ULL; 1733 | } 1734 | else if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 2) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 4)) 1735 | { 1736 | r_div = SI5351_OUTPUT_CLK_DIV_64; 1737 | *freq *= 64ULL; 1738 | } 1739 | else if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 4) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 8)) 1740 | { 1741 | r_div = SI5351_OUTPUT_CLK_DIV_32; 1742 | *freq *= 32ULL; 1743 | } 1744 | else if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 8) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 16)) 1745 | { 1746 | r_div = SI5351_OUTPUT_CLK_DIV_16; 1747 | *freq *= 16ULL; 1748 | } 1749 | else if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 16) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 32)) 1750 | { 1751 | r_div = SI5351_OUTPUT_CLK_DIV_8; 1752 | *freq *= 8ULL; 1753 | } 1754 | else if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 32) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 64)) 1755 | { 1756 | r_div = SI5351_OUTPUT_CLK_DIV_4; 1757 | *freq *= 4ULL; 1758 | } 1759 | else if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 64) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 128)) 1760 | { 1761 | r_div = SI5351_OUTPUT_CLK_DIV_2; 1762 | *freq *= 2ULL; 1763 | } 1764 | 1765 | return r_div; 1766 | } 1767 | 1768 | uint8_t Si5351::select_r_div_ms67(uint64_t *freq) 1769 | { 1770 | uint8_t r_div = SI5351_OUTPUT_CLK_DIV_1; 1771 | 1772 | // Choose the correct R divider 1773 | if((*freq >= SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT) && (*freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 2)) 1774 | { 1775 | r_div = SI5351_OUTPUT_CLK_DIV_128; 1776 | *freq *= 128ULL; 1777 | } 1778 | else if((*freq >= SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 2) && (*freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 4)) 1779 | { 1780 | r_div = SI5351_OUTPUT_CLK_DIV_64; 1781 | *freq *= 64ULL; 1782 | } 1783 | else if((*freq >= SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 4) && (*freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 8)) 1784 | { 1785 | r_div = SI5351_OUTPUT_CLK_DIV_32; 1786 | *freq *= 32ULL; 1787 | } 1788 | else if((*freq >= SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 8) && (*freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 16)) 1789 | { 1790 | r_div = SI5351_OUTPUT_CLK_DIV_16; 1791 | *freq *= 16ULL; 1792 | } 1793 | else if((*freq >= SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 16) && (*freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 32)) 1794 | { 1795 | r_div = SI5351_OUTPUT_CLK_DIV_8; 1796 | *freq *= 8ULL; 1797 | } 1798 | else if((*freq >= SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 32) && (*freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 64)) 1799 | { 1800 | r_div = SI5351_OUTPUT_CLK_DIV_4; 1801 | *freq *= 4ULL; 1802 | } 1803 | else if((*freq >= SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 64) && (*freq < SI5351_CLKOUT67_MIN_FREQ * SI5351_FREQ_MULT * 128)) 1804 | { 1805 | r_div = SI5351_OUTPUT_CLK_DIV_2; 1806 | *freq *= 2ULL; 1807 | } 1808 | 1809 | return r_div; 1810 | } 1811 | -------------------------------------------------------------------------------- /src/si5351.h: -------------------------------------------------------------------------------- 1 | /* 2 | * si5351.h - Si5351 library for Arduino 3 | * 4 | * Copyright (C) 2015 - 2019 Jason Milldrum 5 | * Dana H. Myers 6 | * 7 | * Many defines derived from clk-si5351.h in the Linux kernel. 8 | * Sebastian Hesselbarth 9 | * Rabeeh Khoury 10 | * 11 | * do_div() macro derived from /include/asm-generic/div64.h in 12 | * the Linux kernel. 13 | * Copyright (C) 2003 Bernardo Innocenti 14 | * 15 | * This program is free software: you can redistribute it and/or modify 16 | * it under the terms of the GNU General Public License as published by 17 | * the Free Software Foundation, either version 3 of the License, or 18 | * (at your option) any later version. 19 | * 20 | * This program is distributed in the hope that it will be useful, 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 | * GNU General Public License for more details. 24 | * 25 | * You should have received a copy of the GNU General Public License 26 | * along with this program. If not, see . 27 | */ 28 | 29 | #ifndef SI5351_H_ 30 | #define SI5351_H_ 31 | 32 | #include "Arduino.h" 33 | #include "Wire.h" 34 | #include 35 | 36 | /* Define definitions */ 37 | 38 | #define SI5351_BUS_BASE_ADDR 0x60 39 | #define SI5351_XTAL_FREQ 25000000 40 | #define SI5351_PLL_FIXED 80000000000ULL 41 | #define SI5351_FREQ_MULT 100ULL 42 | #define SI5351_DEFAULT_CLK 1000000000ULL 43 | 44 | #define SI5351_PLL_VCO_MIN 600000000 45 | #define SI5351_PLL_VCO_MAX 900000000 46 | #define SI5351_MULTISYNTH_MIN_FREQ 500000 47 | #define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000 48 | #define SI5351_MULTISYNTH_MAX_FREQ 225000000 49 | #define SI5351_MULTISYNTH_SHARE_MAX 100000000 50 | #define SI5351_MULTISYNTH_SHARE_MIN 1024000 51 | #define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ 52 | #define SI5351_CLKOUT_MIN_FREQ 4000 53 | #define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ 54 | #define SI5351_CLKOUT67_MS_MIN SI5351_PLL_VCO_MIN / SI5351_MULTISYNTH67_A_MAX 55 | #define SI5351_CLKOUT67_MIN_FREQ SI5351_CLKOUT67_MS_MIN / 128 56 | #define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ 57 | 58 | #define SI5351_PLL_A_MIN 15 59 | #define SI5351_PLL_A_MAX 90 60 | #define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1) 61 | #define SI5351_PLL_C_MAX 1048575 62 | #define SI5351_MULTISYNTH_A_MIN 6 63 | #define SI5351_MULTISYNTH_A_MAX 1800 64 | #define SI5351_MULTISYNTH67_A_MAX 254 65 | #define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1) 66 | #define SI5351_MULTISYNTH_C_MAX 1048575 67 | #define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1) 68 | #define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1) 69 | #define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1) 70 | #define SI5351_VCXO_PULL_MIN 30 71 | #define SI5351_VCXO_PULL_MAX 240 72 | #define SI5351_VCXO_MARGIN 103 73 | 74 | #define SI5351_DEVICE_STATUS 0 75 | #define SI5351_INTERRUPT_STATUS 1 76 | #define SI5351_INTERRUPT_MASK 2 77 | #define SI5351_STATUS_SYS_INIT (1<<7) 78 | #define SI5351_STATUS_LOL_B (1<<6) 79 | #define SI5351_STATUS_LOL_A (1<<5) 80 | #define SI5351_STATUS_LOS (1<<4) 81 | #define SI5351_OUTPUT_ENABLE_CTRL 3 82 | #define SI5351_OEB_PIN_ENABLE_CTRL 9 83 | #define SI5351_PLL_INPUT_SOURCE 15 84 | #define SI5351_CLKIN_DIV_MASK (3<<6) 85 | #define SI5351_CLKIN_DIV_1 (0<<6) 86 | #define SI5351_CLKIN_DIV_2 (1<<6) 87 | #define SI5351_CLKIN_DIV_4 (2<<6) 88 | #define SI5351_CLKIN_DIV_8 (3<<6) 89 | #define SI5351_PLLB_SOURCE (1<<3) 90 | #define SI5351_PLLA_SOURCE (1<<2) 91 | 92 | #define SI5351_CLK0_CTRL 16 93 | #define SI5351_CLK1_CTRL 17 94 | #define SI5351_CLK2_CTRL 18 95 | #define SI5351_CLK3_CTRL 19 96 | #define SI5351_CLK4_CTRL 20 97 | #define SI5351_CLK5_CTRL 21 98 | #define SI5351_CLK6_CTRL 22 99 | #define SI5351_CLK7_CTRL 23 100 | #define SI5351_CLK_POWERDOWN (1<<7) 101 | #define SI5351_CLK_INTEGER_MODE (1<<6) 102 | #define SI5351_CLK_PLL_SELECT (1<<5) 103 | #define SI5351_CLK_INVERT (1<<4) 104 | #define SI5351_CLK_INPUT_MASK (3<<2) 105 | #define SI5351_CLK_INPUT_XTAL (0<<2) 106 | #define SI5351_CLK_INPUT_CLKIN (1<<2) 107 | #define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2) 108 | #define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2) 109 | #define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0) 110 | #define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0) 111 | #define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0) 112 | #define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0) 113 | #define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0) 114 | 115 | #define SI5351_CLK3_0_DISABLE_STATE 24 116 | #define SI5351_CLK7_4_DISABLE_STATE 25 117 | #define SI5351_CLK_DISABLE_STATE_MASK 3 118 | #define SI5351_CLK_DISABLE_STATE_LOW 0 119 | #define SI5351_CLK_DISABLE_STATE_HIGH 1 120 | #define SI5351_CLK_DISABLE_STATE_FLOAT 2 121 | #define SI5351_CLK_DISABLE_STATE_NEVER 3 122 | 123 | #define SI5351_PARAMETERS_LENGTH 8 124 | #define SI5351_PLLA_PARAMETERS 26 125 | #define SI5351_PLLB_PARAMETERS 34 126 | #define SI5351_CLK0_PARAMETERS 42 127 | #define SI5351_CLK1_PARAMETERS 50 128 | #define SI5351_CLK2_PARAMETERS 58 129 | #define SI5351_CLK3_PARAMETERS 66 130 | #define SI5351_CLK4_PARAMETERS 74 131 | #define SI5351_CLK5_PARAMETERS 82 132 | #define SI5351_CLK6_PARAMETERS 90 133 | #define SI5351_CLK7_PARAMETERS 91 134 | #define SI5351_CLK6_7_OUTPUT_DIVIDER 92 135 | #define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4) 136 | #define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0) 137 | #define SI5351_OUTPUT_CLK_DIV_SHIFT 4 138 | #define SI5351_OUTPUT_CLK_DIV6_SHIFT 0 139 | #define SI5351_OUTPUT_CLK_DIV_1 0 140 | #define SI5351_OUTPUT_CLK_DIV_2 1 141 | #define SI5351_OUTPUT_CLK_DIV_4 2 142 | #define SI5351_OUTPUT_CLK_DIV_8 3 143 | #define SI5351_OUTPUT_CLK_DIV_16 4 144 | #define SI5351_OUTPUT_CLK_DIV_32 5 145 | #define SI5351_OUTPUT_CLK_DIV_64 6 146 | #define SI5351_OUTPUT_CLK_DIV_128 7 147 | #define SI5351_OUTPUT_CLK_DIVBY4 (3<<2) 148 | 149 | #define SI5351_SSC_PARAM0 149 150 | #define SI5351_SSC_PARAM1 150 151 | #define SI5351_SSC_PARAM2 151 152 | #define SI5351_SSC_PARAM3 152 153 | #define SI5351_SSC_PARAM4 153 154 | #define SI5351_SSC_PARAM5 154 155 | #define SI5351_SSC_PARAM6 155 156 | #define SI5351_SSC_PARAM7 156 157 | #define SI5351_SSC_PARAM8 157 158 | #define SI5351_SSC_PARAM9 158 159 | #define SI5351_SSC_PARAM10 159 160 | #define SI5351_SSC_PARAM11 160 161 | #define SI5351_SSC_PARAM12 161 162 | 163 | #define SI5351_VXCO_PARAMETERS_LOW 162 164 | #define SI5351_VXCO_PARAMETERS_MID 163 165 | #define SI5351_VXCO_PARAMETERS_HIGH 164 166 | 167 | #define SI5351_CLK0_PHASE_OFFSET 165 168 | #define SI5351_CLK1_PHASE_OFFSET 166 169 | #define SI5351_CLK2_PHASE_OFFSET 167 170 | #define SI5351_CLK3_PHASE_OFFSET 168 171 | #define SI5351_CLK4_PHASE_OFFSET 169 172 | #define SI5351_CLK5_PHASE_OFFSET 170 173 | 174 | #define SI5351_PLL_RESET 177 175 | #define SI5351_PLL_RESET_B (1<<7) 176 | #define SI5351_PLL_RESET_A (1<<5) 177 | 178 | #define SI5351_CRYSTAL_LOAD 183 179 | #define SI5351_CRYSTAL_LOAD_MASK (3<<6) 180 | #define SI5351_CRYSTAL_LOAD_0PF (0<<6) 181 | #define SI5351_CRYSTAL_LOAD_6PF (1<<6) 182 | #define SI5351_CRYSTAL_LOAD_8PF (2<<6) 183 | #define SI5351_CRYSTAL_LOAD_10PF (3<<6) 184 | 185 | #define SI5351_FANOUT_ENABLE 187 186 | #define SI5351_CLKIN_ENABLE (1<<7) 187 | #define SI5351_XTAL_ENABLE (1<<6) 188 | #define SI5351_MULTISYNTH_ENABLE (1<<4) 189 | 190 | 191 | /* Macro definitions */ 192 | 193 | //#define RFRAC_DENOM ((1L << 20) - 1) 194 | #define RFRAC_DENOM 1000000ULL 195 | 196 | /* 197 | * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h 198 | * 199 | * The semantics of do_div() are: 200 | * 201 | * uint32_t do_div(uint64_t *n, uint32_t base) 202 | * { 203 | * uint32_t remainder = *n % base; 204 | * *n = *n / base; 205 | * return remainder; 206 | * } 207 | * 208 | * NOTE: macro parameter n is evaluated multiple times, 209 | * beware of side effects! 210 | */ 211 | 212 | # define do_div(n,base) ({ \ 213 | uint64_t __base = (base); \ 214 | uint64_t __rem; \ 215 | __rem = ((uint64_t)(n)) % __base; \ 216 | (n) = ((uint64_t)(n)) / __base; \ 217 | __rem; \ 218 | }) 219 | 220 | /* Enum definitions */ 221 | 222 | /* 223 | * enum si5351_variant - SiLabs Si5351 chip variant 224 | * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input) 225 | * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input) 226 | * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input) 227 | * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input) 228 | */ 229 | /* 230 | enum si5351_variant { 231 | SI5351_VARIANT_A = 1, 232 | SI5351_VARIANT_A3 = 2, 233 | SI5351_VARIANT_B = 3, 234 | SI5351_VARIANT_C = 4, 235 | }; 236 | */ 237 | 238 | enum si5351_clock {SI5351_CLK0, SI5351_CLK1, SI5351_CLK2, SI5351_CLK3, 239 | SI5351_CLK4, SI5351_CLK5, SI5351_CLK6, SI5351_CLK7}; 240 | 241 | enum si5351_pll {SI5351_PLLA, SI5351_PLLB}; 242 | 243 | enum si5351_drive {SI5351_DRIVE_2MA, SI5351_DRIVE_4MA, SI5351_DRIVE_6MA, SI5351_DRIVE_8MA}; 244 | 245 | enum si5351_clock_source {SI5351_CLK_SRC_XTAL, SI5351_CLK_SRC_CLKIN, SI5351_CLK_SRC_MS0, SI5351_CLK_SRC_MS}; 246 | 247 | enum si5351_clock_disable {SI5351_CLK_DISABLE_LOW, SI5351_CLK_DISABLE_HIGH, SI5351_CLK_DISABLE_HI_Z, SI5351_CLK_DISABLE_NEVER}; 248 | 249 | enum si5351_clock_fanout {SI5351_FANOUT_CLKIN, SI5351_FANOUT_XO, SI5351_FANOUT_MS}; 250 | 251 | enum si5351_pll_input {SI5351_PLL_INPUT_XO, SI5351_PLL_INPUT_CLKIN}; 252 | 253 | /* Struct definitions */ 254 | 255 | struct Si5351RegSet 256 | { 257 | uint32_t p1; 258 | uint32_t p2; 259 | uint32_t p3; 260 | }; 261 | 262 | struct Si5351Status 263 | { 264 | uint8_t SYS_INIT; 265 | uint8_t LOL_B; 266 | uint8_t LOL_A; 267 | uint8_t LOS; 268 | uint8_t REVID; 269 | }; 270 | 271 | struct Si5351IntStatus 272 | { 273 | uint8_t SYS_INIT_STKY; 274 | uint8_t LOL_B_STKY; 275 | uint8_t LOL_A_STKY; 276 | uint8_t LOS_STKY; 277 | }; 278 | 279 | class Si5351 280 | { 281 | public: 282 | Si5351(uint8_t i2c_addr = SI5351_BUS_BASE_ADDR); 283 | bool init(uint8_t, uint32_t, int32_t); 284 | void reset(void); 285 | uint8_t set_freq(uint64_t, enum si5351_clock); 286 | uint8_t set_freq_manual(uint64_t, uint64_t, enum si5351_clock); 287 | void set_pll(uint64_t, enum si5351_pll); 288 | void set_ms(enum si5351_clock, struct Si5351RegSet, uint8_t, uint8_t, uint8_t); 289 | void output_enable(enum si5351_clock, uint8_t); 290 | void drive_strength(enum si5351_clock, enum si5351_drive); 291 | void update_status(void); 292 | void set_correction(int32_t, enum si5351_pll_input); 293 | void set_phase(enum si5351_clock, uint8_t); 294 | int32_t get_correction(enum si5351_pll_input); 295 | void pll_reset(enum si5351_pll); 296 | void set_ms_source(enum si5351_clock, enum si5351_pll); 297 | void set_int(enum si5351_clock, uint8_t); 298 | void set_clock_pwr(enum si5351_clock, uint8_t); 299 | void set_clock_invert(enum si5351_clock, uint8_t); 300 | void set_clock_source(enum si5351_clock, enum si5351_clock_source); 301 | void set_clock_disable(enum si5351_clock, enum si5351_clock_disable); 302 | void set_clock_fanout(enum si5351_clock_fanout, uint8_t); 303 | void set_pll_input(enum si5351_pll, enum si5351_pll_input); 304 | void set_vcxo(uint64_t, uint8_t); 305 | void set_ref_freq(uint32_t, enum si5351_pll_input); 306 | uint8_t si5351_write_bulk(uint8_t, uint8_t, uint8_t *); 307 | uint8_t si5351_write(uint8_t, uint8_t); 308 | uint8_t si5351_read(uint8_t); 309 | struct Si5351Status dev_status = {.SYS_INIT = 0, .LOL_B = 0, .LOL_A = 0, 310 | .LOS = 0, .REVID = 0}; 311 | struct Si5351IntStatus dev_int_status = {.SYS_INIT_STKY = 0, .LOL_B_STKY = 0, 312 | .LOL_A_STKY = 0, .LOS_STKY = 0}; 313 | enum si5351_pll pll_assignment[8]; 314 | uint64_t clk_freq[8]; 315 | uint64_t plla_freq; 316 | uint64_t pllb_freq; 317 | enum si5351_pll_input plla_ref_osc; 318 | enum si5351_pll_input pllb_ref_osc; 319 | uint32_t xtal_freq[2]; 320 | private: 321 | uint64_t pll_calc(enum si5351_pll, uint64_t, struct Si5351RegSet *, int32_t, uint8_t); 322 | uint64_t multisynth_calc(uint64_t, uint64_t, struct Si5351RegSet *); 323 | uint64_t multisynth67_calc(uint64_t, uint64_t, struct Si5351RegSet *); 324 | void update_sys_status(struct Si5351Status *); 325 | void update_int_status(struct Si5351IntStatus *); 326 | void ms_div(enum si5351_clock, uint8_t, uint8_t); 327 | uint8_t select_r_div(uint64_t *); 328 | uint8_t select_r_div_ms67(uint64_t *); 329 | int32_t ref_correction[2]; 330 | uint8_t clkin_div; 331 | uint8_t i2c_bus_addr; 332 | bool clk_first_set[8]; 333 | }; 334 | 335 | #endif /* SI5351_H_ */ 336 | --------------------------------------------------------------------------------