├── .gitignore ├── .gitmodules ├── LICENSE.md ├── Makefile ├── README.md ├── bare-metal ├── README.md ├── common.mk ├── common │ ├── include │ │ ├── common.h │ │ ├── fpu.h │ │ ├── kprintf.h │ │ └── timer.h │ └── src │ │ ├── fpu.c │ │ ├── heap.c │ │ ├── kprintf.c │ │ └── main.lds ├── coremark │ ├── Makefile │ ├── core_portme.c │ ├── core_portme.h │ └── head.S ├── dhrystone │ ├── Makefile │ ├── head.S │ └── time_override.c ├── hello-world │ ├── Makefile │ ├── head.S │ └── main.c └── scripts │ ├── debugger_download_run_program.sh │ └── debugger_download_run_program.tcl ├── board ├── arty-a7-100t │ ├── Makefile.inc │ ├── README.md │ ├── arty-a7-100t.jpg │ ├── bootrom.dts │ ├── ethernet-arty-a7-100t.tcl │ ├── ethernet-arty-a7-100t.v │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── fan-control.v ├── genesys2 │ ├── Makefile.inc │ ├── bootrom.dts │ ├── ethernet-genesys2.tcl │ ├── ethernet-genesys2.v │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── jtag-boot.tcl ├── jtag-freq.tcl ├── kc705 │ ├── DDR3-1Rx64-1GB.prj │ ├── DDR3-1Rx64-2GB.prj │ ├── DDR3-1Rx64-4GB.prj │ ├── DDR3-2Rx64-8GB.prj │ ├── Makefile.inc │ ├── bootrom.dts │ ├── ethernet-kc705.tcl │ ├── ethernet-kc705.v │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── mem-reset-control.v ├── nexys-a7-100t │ ├── Makefile.inc │ ├── bootrom.dts │ ├── ethernet-nexys-a7-100t.tcl │ ├── ethernet-nexys-a7-100t.v │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── nexys-video │ ├── Makefile.inc │ ├── bootrom.dts │ ├── ethernet-nexys-video.tcl │ ├── ethernet-nexys-video.v │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── program-flash.tcl ├── rocket-freq ├── sitlinv-xc7k325t │ ├── DDR3-1Rx64-1GB.prj │ ├── DDR3-1Rx64-2GB.prj │ ├── DDR3-1Rx64-4GB.prj │ ├── DDR3-2Rx64-8GB.prj │ ├── Makefile.inc │ ├── bootrom.dts │ ├── ethernet-sitlinv-xc7k325t.tcl │ ├── ethernet-sitlinv-xc7k325t.v │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── sdc.xdc │ ├── sitlinv-xc7k325t.jpg │ ├── top.xdc │ └── uart.xdc ├── timing-constraints.tcl ├── u200 │ ├── Makefile.inc │ ├── bootrom.dts │ ├── ethernet-u200.tcl │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── riscv_wrapper.v │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── u250 │ ├── Makefile.inc │ ├── bootrom.dts │ ├── ethernet-u250.tcl │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── riscv_wrapper.v │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── vc707 │ ├── DDR3-1Rx64-1GB.prj │ ├── DDR3-1Rx64-2GB.prj │ ├── DDR3-1Rx64-4GB.prj │ ├── DDR3-2Rx64-8GB.prj │ ├── Makefile.inc │ ├── bootrom.dts │ ├── ethernet-vc707.tcl │ ├── ethernet-vc707.v │ ├── ethernet.xdc │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── vcu1525 │ ├── Makefile.inc │ ├── bootrom.c │ ├── bootrom.dts │ ├── bootrom.inc │ ├── ethernet-vcu1525.tcl │ ├── ethernet.xdc │ ├── m2 │ │ ├── riscv-2021.1.tcl │ │ ├── riscv-2021.2.tcl │ │ ├── riscv-2022.1.tcl │ │ ├── riscv-2022.2.tcl │ │ ├── riscv-2023.1.tcl │ │ ├── riscv-2023.2.tcl │ │ ├── riscv-2024.1.tcl │ │ ├── riscv-2024.2.tcl │ │ ├── riscv-2025.1.tcl │ │ ├── riscv-2025.2.tcl │ │ └── riscv_wrapper.v │ ├── m4 │ │ ├── riscv-2021.1.tcl │ │ ├── riscv-2021.2.tcl │ │ ├── riscv-2022.1.tcl │ │ ├── riscv-2022.2.tcl │ │ ├── riscv-2023.1.tcl │ │ ├── riscv-2023.2.tcl │ │ ├── riscv-2024.1.tcl │ │ ├── riscv-2024.2.tcl │ │ ├── riscv-2025.1.tcl │ │ ├── riscv-2025.2.tcl │ │ └── riscv_wrapper.v │ ├── riscv-2020.2.tcl │ ├── riscv-2021.1.tcl │ ├── riscv-2021.2.tcl │ ├── riscv-2022.1.tcl │ ├── riscv-2022.2.tcl │ ├── riscv-2023.1.tcl │ ├── riscv-2023.2.tcl │ ├── riscv-2024.1.tcl │ ├── riscv-2024.2.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── riscv_wrapper.v │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc └── x3522pv │ ├── Makefile.inc │ ├── bootrom.c │ ├── bootrom.dts │ ├── bootrom.inc │ ├── ethernet-x3522pv.tcl │ ├── ethernet.xdc │ ├── riscv-2024.1.tcl │ ├── riscv-2025.1.tcl │ ├── riscv-2025.2.tcl │ ├── riscv_wrapper.v │ ├── sdc.xdc │ ├── top.xdc │ └── uart.xdc ├── bootrom ├── Makefile ├── bootrom.c ├── bootrom.lds ├── common.h ├── diskio.h ├── ff.c ├── ff.h ├── ffconf.h ├── ffunicode.c ├── head.S ├── kprintf.c └── kprintf.h ├── docker ├── Dockerfile ├── patches │ └── vivado-2023.2-postinstall.patch └── vivado-installer │ ├── .gitignore │ ├── board_files.zip │ ├── install_config_vivado.2023.2.txt │ ├── install_config_vivado.2024.1.txt │ ├── install_config_vivado.2024.2.txt │ ├── install_config_vivado.2025.1.txt │ └── install_config_vivado.2025.2.txt ├── docs ├── images │ ├── console.png │ └── debug-bootrom.png ├── ubuntu-on-windows.md └── vivado-flash.md ├── ethernet ├── ethernet-sfp-10g.v └── ethernet.v ├── generators └── targetutils │ ├── build.sbt │ └── src │ └── main │ └── scala │ └── midas │ └── annotations.scala ├── mk-sd-card ├── mk-sd-image ├── mk-srams ├── patches ├── ethernet.patch ├── fpga-axi-eth.c ├── fpga-axi-sdc.c ├── fpga-axi-uart.c ├── gemmini.patch ├── linux.config ├── linux.patch ├── opensbi │ ├── Kconfig │ ├── configs │ │ └── defconfig │ ├── objects.mk │ └── platform.c ├── riscv-boom.patch ├── rocket-chip.patch ├── sifive-cache.patch ├── u-boot.patch └── u-boot │ ├── vivado_riscv64.h │ ├── vivado_riscv64 │ ├── Kconfig │ ├── Makefile │ ├── board.c │ ├── sdc.c │ └── serial.c │ └── vivado_riscv64_defconfig ├── project ├── build.properties └── plugins.sbt ├── qemu └── boot_qemu.sh ├── sbt-launch.jar ├── sdc ├── axi_sdc_controller.v ├── license.txt ├── sd_cmd_master.v ├── sd_cmd_serial_host.v ├── sd_data_master.v ├── sd_data_serial_host.v └── sd_defines.h ├── src └── main │ └── scala │ └── rocket.scala ├── uart └── uart.v ├── vhdl-wrapper ├── .classpath ├── .project ├── .settings │ └── org.eclipse.jdt.core.prefs ├── antlr-4.8-complete.jar └── src │ └── net │ └── largest │ └── riscv │ └── vhdl │ ├── Main.java │ ├── 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https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/riscv-2023.1.tcl -------------------------------------------------------------------------------- /board/u200/riscv-2023.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/riscv-2023.2.tcl -------------------------------------------------------------------------------- /board/u200/riscv-2024.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/riscv-2024.1.tcl -------------------------------------------------------------------------------- /board/u200/riscv-2024.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/riscv-2024.2.tcl -------------------------------------------------------------------------------- /board/u200/riscv-2025.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/riscv-2025.1.tcl -------------------------------------------------------------------------------- /board/u200/riscv-2025.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/riscv-2025.2.tcl -------------------------------------------------------------------------------- /board/u200/riscv_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/riscv_wrapper.v -------------------------------------------------------------------------------- /board/u200/sdc.xdc: -------------------------------------------------------------------------------- 1 | # SD card not supported -------------------------------------------------------------------------------- /board/u200/top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/top.xdc -------------------------------------------------------------------------------- /board/u200/uart.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u200/uart.xdc -------------------------------------------------------------------------------- /board/u250/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/Makefile.inc -------------------------------------------------------------------------------- /board/u250/bootrom.dts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/bootrom.dts -------------------------------------------------------------------------------- /board/u250/ethernet-u250.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/ethernet-u250.tcl -------------------------------------------------------------------------------- /board/u250/ethernet.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/ethernet.xdc -------------------------------------------------------------------------------- /board/u250/riscv-2020.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2020.2.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2021.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2021.1.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2021.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2021.2.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2022.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2022.1.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2022.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2022.2.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2023.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2023.1.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2023.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2023.2.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2024.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2024.1.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2024.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2024.2.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2025.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2025.1.tcl -------------------------------------------------------------------------------- /board/u250/riscv-2025.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv-2025.2.tcl -------------------------------------------------------------------------------- /board/u250/riscv_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/riscv_wrapper.v -------------------------------------------------------------------------------- /board/u250/sdc.xdc: -------------------------------------------------------------------------------- 1 | # SD card not supported -------------------------------------------------------------------------------- /board/u250/top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/top.xdc -------------------------------------------------------------------------------- /board/u250/uart.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/u250/uart.xdc -------------------------------------------------------------------------------- /board/vc707/DDR3-1Rx64-1GB.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/DDR3-1Rx64-1GB.prj -------------------------------------------------------------------------------- /board/vc707/DDR3-1Rx64-2GB.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/DDR3-1Rx64-2GB.prj -------------------------------------------------------------------------------- /board/vc707/DDR3-1Rx64-4GB.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/DDR3-1Rx64-4GB.prj -------------------------------------------------------------------------------- /board/vc707/DDR3-2Rx64-8GB.prj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/DDR3-2Rx64-8GB.prj -------------------------------------------------------------------------------- /board/vc707/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/Makefile.inc -------------------------------------------------------------------------------- /board/vc707/bootrom.dts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/bootrom.dts -------------------------------------------------------------------------------- /board/vc707/ethernet-vc707.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/ethernet-vc707.tcl -------------------------------------------------------------------------------- /board/vc707/ethernet-vc707.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/ethernet-vc707.v -------------------------------------------------------------------------------- /board/vc707/ethernet.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/ethernet.xdc -------------------------------------------------------------------------------- /board/vc707/riscv-2020.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2020.2.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2021.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2021.1.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2021.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2021.2.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2022.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2022.1.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2022.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2022.2.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2023.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2023.1.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2023.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2023.2.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2024.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2024.1.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2024.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2024.2.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2025.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2025.1.tcl -------------------------------------------------------------------------------- /board/vc707/riscv-2025.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/riscv-2025.2.tcl -------------------------------------------------------------------------------- /board/vc707/sdc.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/sdc.xdc -------------------------------------------------------------------------------- /board/vc707/top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/top.xdc -------------------------------------------------------------------------------- /board/vc707/uart.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vc707/uart.xdc -------------------------------------------------------------------------------- /board/vcu1525/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/Makefile.inc -------------------------------------------------------------------------------- /board/vcu1525/bootrom.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/bootrom.c -------------------------------------------------------------------------------- /board/vcu1525/bootrom.dts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/bootrom.dts -------------------------------------------------------------------------------- /board/vcu1525/bootrom.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/bootrom.inc -------------------------------------------------------------------------------- /board/vcu1525/ethernet-vcu1525.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/ethernet-vcu1525.tcl -------------------------------------------------------------------------------- /board/vcu1525/ethernet.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/ethernet.xdc -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2021.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2021.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2021.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2021.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2022.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2022.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2022.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2022.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2023.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2023.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2023.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2023.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2024.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2024.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2024.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2024.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2025.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2025.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv-2025.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv-2025.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m2/riscv_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m2/riscv_wrapper.v -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2021.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2021.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2021.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2021.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2022.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2022.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2022.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2022.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2023.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2023.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2023.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2023.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2024.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2024.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2024.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2024.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2025.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2025.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv-2025.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv-2025.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/m4/riscv_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/m4/riscv_wrapper.v -------------------------------------------------------------------------------- /board/vcu1525/riscv-2020.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2020.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2021.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2021.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2021.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2021.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2022.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2022.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2022.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2022.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2023.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2023.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2023.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2023.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2024.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2024.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2024.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2024.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2025.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2025.1.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv-2025.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv-2025.2.tcl -------------------------------------------------------------------------------- /board/vcu1525/riscv_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/riscv_wrapper.v -------------------------------------------------------------------------------- /board/vcu1525/sdc.xdc: -------------------------------------------------------------------------------- 1 | # SD card not supported -------------------------------------------------------------------------------- /board/vcu1525/top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/top.xdc -------------------------------------------------------------------------------- /board/vcu1525/uart.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/vcu1525/uart.xdc -------------------------------------------------------------------------------- /board/x3522pv/Makefile.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/Makefile.inc -------------------------------------------------------------------------------- /board/x3522pv/bootrom.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/bootrom.c -------------------------------------------------------------------------------- /board/x3522pv/bootrom.dts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/bootrom.dts -------------------------------------------------------------------------------- /board/x3522pv/bootrom.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/bootrom.inc -------------------------------------------------------------------------------- /board/x3522pv/ethernet-x3522pv.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/ethernet-x3522pv.tcl -------------------------------------------------------------------------------- /board/x3522pv/ethernet.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/ethernet.xdc -------------------------------------------------------------------------------- /board/x3522pv/riscv-2024.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/riscv-2024.1.tcl -------------------------------------------------------------------------------- /board/x3522pv/riscv-2025.1.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/riscv-2025.1.tcl -------------------------------------------------------------------------------- /board/x3522pv/riscv-2025.2.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/riscv-2025.2.tcl -------------------------------------------------------------------------------- /board/x3522pv/riscv_wrapper.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/riscv_wrapper.v -------------------------------------------------------------------------------- /board/x3522pv/sdc.xdc: -------------------------------------------------------------------------------- 1 | # SD card not supported -------------------------------------------------------------------------------- /board/x3522pv/top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/top.xdc -------------------------------------------------------------------------------- /board/x3522pv/uart.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/board/x3522pv/uart.xdc -------------------------------------------------------------------------------- /bootrom/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/Makefile -------------------------------------------------------------------------------- /bootrom/bootrom.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/bootrom.c -------------------------------------------------------------------------------- /bootrom/bootrom.lds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/bootrom.lds -------------------------------------------------------------------------------- /bootrom/common.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/common.h -------------------------------------------------------------------------------- /bootrom/diskio.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/diskio.h -------------------------------------------------------------------------------- /bootrom/ff.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/ff.c -------------------------------------------------------------------------------- /bootrom/ff.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/ff.h -------------------------------------------------------------------------------- /bootrom/ffconf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/ffconf.h -------------------------------------------------------------------------------- /bootrom/ffunicode.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/ffunicode.c -------------------------------------------------------------------------------- /bootrom/head.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eugene-tarassov/vivado-risc-v/HEAD/bootrom/head.S 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