├── .excludes ├── .git-blame-ignore-revs ├── .gitattributes ├── .github ├── autolabeler.yml ├── dependabot.yml ├── scripts │ ├── common.sh │ ├── docs.sh │ ├── ice40.sh │ ├── install.sh │ ├── ql.sh │ ├── setup-and-activate.sh │ ├── setup.sh │ ├── testarch.sh │ ├── tests.sh │ ├── xc7-vendor.sh │ ├── xc7.sh │ ├── xc7a200t-vendor.sh │ └── xc7a200t.sh └── workflows │ ├── Automerge.yml │ ├── Tests.yml │ └── update_conda_lock.yml ├── .gitignore ├── .gitmodules ├── .readthedocs.yml ├── .style.yapf ├── CMakeLists.txt ├── COPYING ├── Makefile ├── README.md ├── common ├── CMakeLists.txt ├── cmake │ ├── cmake_format.py │ ├── devices.cmake │ ├── env.cmake │ ├── file_targets.cmake │ ├── gen.cmake │ ├── image_gen.cmake │ ├── install.cmake │ ├── litex.cmake │ ├── sv2v.cmake │ ├── timings.cmake │ ├── tools.cmake │ ├── util.cmake │ ├── v2x.cmake │ └── xml.cmake ├── empty.svg ├── python_health_helper.sh ├── wire.eblif ├── xml │ ├── README.md │ ├── fpga_architecture.xsd │ ├── packed_netlist.xsd │ └── routing_resource.xsd └── yosys │ ├── CMakeLists.txt │ ├── equiv_simple_clk2fflogic.ys │ ├── equiv_simple_opt_full.ys │ ├── miter_and_tempinduct.ys │ ├── miter_and_tempinduct_large_N.ys │ └── miter_and_tempinduct_skip_1.ys ├── conda_lock.yml ├── docs ├── Makefile ├── _static │ ├── favicon.svg │ ├── images │ │ ├── overview.svg │ │ └── prjxray │ │ │ ├── arch-defs-flow.png │ │ │ ├── import-flow.png │ │ │ ├── import-wire-class.svg │ │ │ ├── rrgraph-wire.svg │ │ │ ├── vpr-rrgraph-types.svg │ │ │ └── vtr-rrgraph.png │ └── logo.svg ├── bitdoc │ ├── index.rst │ └── prjxray │ │ ├── flow-diagram.rst │ │ ├── index.rst │ │ ├── partial-reconfig.rst │ │ └── vtr-rrgraph.rst ├── conf.py ├── development │ ├── arch_notes.rst │ ├── cmake.md │ ├── getting-started.rst │ ├── notes.md │ ├── structure.rst │ └── vtr_notes.rst ├── index.rst ├── make.bat ├── packages.rst ├── requirements.txt └── tools.rst ├── environment.yml ├── lattice ├── ecp5 │ ├── .gitignore │ ├── cells │ │ └── slice │ │ │ └── TRELLIS_SLICE.sim.v │ ├── ecp5_tile_colormap.json │ └── primitives │ │ ├── io │ │ ├── BB │ │ │ └── BB.sim.v │ │ ├── IB │ │ │ └── IB.sim.v │ │ ├── OB │ │ │ └── OB.sim.v │ │ ├── OBZ │ │ │ └── OBZ.sim.v │ │ └── TRELLIS_IO │ │ │ └── TRELLIS_IO.sim.v │ │ ├── misc │ │ └── INV │ │ │ └── INV.sim.v │ │ └── slice │ │ ├── CCU2C │ │ └── CCU2C.sim.v │ │ ├── DPR16X4C │ │ └── DPR16X4C.sim.v │ │ ├── L6MUX21 │ │ └── L6MUX21.sim.v │ │ ├── LUT2 │ │ └── LUT2.sim.v │ │ ├── LUT4 │ │ └── LUT4.sim.v │ │ ├── PFUMX │ │ └── PFUMX.sim.v │ │ ├── TRELLIS_DPR16X4 │ │ └── TRELLIS_DPR16X4.sim.v │ │ ├── TRELLIS_FF │ │ └── TRELLIS_FF.sim.v │ │ └── TRELLIS_RAM16X2 │ │ └── TRELLIS_RAM16X2.sim.v └── ice40 │ ├── CMakeLists.txt │ ├── README.md │ ├── boards.cmake │ ├── cells │ ├── CMakeLists.txt │ ├── io_local │ │ └── io_local.pb_type.xml │ ├── lutff │ │ ├── CMakeLists.txt │ │ └── lutff.pb_type.xml │ └── plb │ │ ├── CMakeLists.txt │ │ └── plb.pb_type.xml │ ├── devices │ ├── CMakeLists.txt │ ├── layouts │ │ ├── CMakeLists.txt │ │ ├── N1k │ │ │ ├── CMakeLists.txt │ │ │ └── ntemplate.N1k.fixed_layout.xml │ │ ├── N384 │ │ │ ├── CMakeLists.txt │ │ │ └── ntemplate.N384.fixed_layout.xml │ │ ├── N4k │ │ │ ├── CMakeLists.txt │ │ │ └── ntemplate.N4k.fixed_layout.xml │ │ ├── N8k │ │ │ ├── CMakeLists.txt │ │ │ └── ntemplate.N8k.fixed_layout.xml │ │ ├── icebox │ │ │ └── CMakeLists.txt │ │ └── test4 │ │ │ └── test4.fixed_layout.xml │ ├── tile-routing-virt │ │ ├── arch.xml │ │ └── tiles │ │ │ ├── pio-b │ │ │ └── pio-b.pb_type.xml │ │ │ ├── pio-l │ │ │ └── pio-l.pb_type.xml │ │ │ ├── pio-lr │ │ │ ├── pio-lr.fc.xml │ │ │ ├── pio-lr.interconnect.xml │ │ │ └── pio-lr.pb_type.xml │ │ │ ├── pio-r │ │ │ └── pio-r.pb_type.xml │ │ │ ├── pio-t │ │ │ └── pio-t.pb_type.xml │ │ │ ├── pio-tb │ │ │ ├── pio-tb.fc.xml │ │ │ ├── pio-tb.interconnect.xml │ │ │ ├── pio-tb.pb_type.xml │ │ │ └── sb_pio.sim.v │ │ │ ├── pio │ │ │ ├── pio.interconnect.xml │ │ │ └── pio.pb_type.xml │ │ │ ├── plb │ │ │ └── plb.pb_type.xml │ │ │ ├── ramb │ │ │ └── ramb.pb_type.xml │ │ │ └── ramt │ │ │ └── ramt.pb_type.xml │ └── top-routing-virt │ │ ├── CMakeLists.txt │ │ ├── arch.xml │ │ └── tiles │ │ ├── CMakeLists.txt │ │ ├── dsp │ │ ├── CMakeLists.txt │ │ └── dsp.pb_type.xml │ │ ├── pio │ │ ├── CMakeLists.txt │ │ └── pio.pb_type.xml │ │ ├── plb │ │ ├── CMakeLists.txt │ │ └── plb.pb_type.xml │ │ └── ram │ │ ├── CMakeLists.txt │ │ └── ram.pb_type.xml │ ├── docs │ ├── carry-chain-routing-options.svg │ ├── neighbourhood-in.xcf │ └── neighbourhood-out.xcf │ ├── icestorm.cmake │ ├── primitives │ ├── CMakeLists.txt │ ├── mux2 │ │ └── CMakeLists.txt │ ├── mux4 │ │ └── CMakeLists.txt │ ├── sb_carry │ │ ├── CMakeLists.txt │ │ ├── sb_carry.model.xml │ │ ├── sb_carry.pb_type.xml │ │ └── sb_carry.sim.v │ ├── sb_ff │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── dff.pb_type.xml │ │ ├── dffe.pb_type.xml │ │ ├── dffes.pb_type.xml │ │ ├── dffs.pb_type.xml │ │ ├── sb_ff.model.xml │ │ └── sb_ff.pb_type.xml │ ├── sb_io │ │ └── sb_io.pb_type.xml │ ├── sb_lut │ │ ├── CMakeLists.txt │ │ ├── sb_lut.model.xml │ │ └── sb_lut.pb_type.xml │ └── sb_ram │ │ ├── CMakeLists.txt │ │ ├── sb_ram.model.xml │ │ └── sb_ram.pb_type.xml │ ├── tests │ ├── CMakeLists.txt │ ├── blink │ │ ├── CMakeLists.txt │ │ ├── example.v │ │ ├── example_tb.v │ │ ├── hx8k-b-evn.pcf │ │ ├── iceblink40-lp1k.pcf │ │ ├── icestick.pcf │ │ ├── icevision.pcf │ │ ├── tinyfpga-b2.pcf │ │ └── tinyfpga-bx.pcf │ ├── checker │ │ ├── CMakeLists.txt │ │ ├── checker.v │ │ ├── checker_tb.v │ │ └── icestick.pcf │ ├── ffpack │ │ ├── example.pcf │ │ ├── example.v │ │ ├── example_tb.v │ │ └── none.pcf │ ├── iceff │ │ ├── ff.pcf │ │ └── ff.v │ ├── iceinv │ │ ├── example.pcf │ │ └── example.v │ ├── icelut │ │ ├── and4 │ │ │ ├── lut.pcf │ │ │ └── lut.v │ │ ├── lut.pcf │ │ ├── lut.v │ │ ├── or4 │ │ │ ├── lut.pcf │ │ │ └── lut.v │ │ ├── route-through-in0 │ │ │ ├── lut.pcf │ │ │ └── lut.v │ │ ├── route-through-in1 │ │ │ ├── lut.pcf │ │ │ └── lut.v │ │ ├── route-through-in2 │ │ │ ├── lut.pcf │ │ │ └── lut.v │ │ ├── route-through-in3 │ │ │ ├── lut.pcf │ │ │ └── lut.v │ │ └── xor4 │ │ │ ├── lut.pcf │ │ │ └── lut.v │ └── iceram │ │ ├── CMakeLists.txt │ │ ├── hx8k-b-evn.pcf │ │ ├── iceblink40-lp1k.pcf │ │ ├── iceram.v │ │ ├── iceram_tb.v │ │ ├── icestick.pcf │ │ └── tinyfpga-bx.pcf │ └── utils │ ├── fasm_icebox │ ├── README.md │ ├── asc2fasm.py │ ├── fasm2asc.py │ ├── fasm_icebox_utils.py │ ├── ice40_feature.py │ └── tests │ │ └── test_fasm_icebox_utils.py │ ├── ice40_create_ioplace.py │ ├── ice40_generate_routing.py │ ├── ice40_import_bel_timing.py │ ├── ice40_import_layout_from_icebox.py │ ├── ice40_import_routing_from_icebox.py │ ├── ice40_list_layout_in_icebox.py │ └── pcf.py ├── library ├── CMakeLists.txt ├── lfsr.v ├── tbassert.v └── uart │ ├── CMakeLists.txt │ ├── baudgen.v │ ├── uart.v │ ├── uart_rx.v │ └── uart_tx.v ├── packaging ├── eos-s3_environment.yml ├── eos-s3_requirements.txt ├── requirements.txt ├── xc7_environment.yml └── xc7_requirements.txt ├── pylintrc ├── quicklogic ├── CMakeLists.txt ├── README.md ├── common │ ├── CMakeLists.txt │ ├── cmake │ │ ├── CMakeLists.txt │ │ ├── quicklogic_board.cmake │ │ ├── quicklogic_device.cmake │ │ ├── quicklogic_env.cmake │ │ ├── quicklogic_install.cmake │ │ ├── quicklogic_jlink.cmake │ │ ├── quicklogic_openocd.cmake │ │ ├── quicklogic_qlf_arch.cmake │ │ ├── quicklogic_qlf_device.cmake │ │ ├── quicklogic_toolchain_test.cmake │ │ └── run_toolchain_test.cmake │ └── utils │ │ └── CMakeLists.txt ├── docs │ ├── Pin-mapping.md │ └── images │ │ ├── image1.png │ │ └── image2.png ├── passthrough.eblif ├── pp3 │ ├── CMakeLists.txt │ ├── boards.cmake │ ├── cells_sim_gen.cmake │ ├── devices │ │ ├── CMakeLists.txt │ │ ├── ql-eos-s3-virt │ │ │ └── CMakeLists.txt │ │ └── ql-pp3e-virt │ │ │ └── CMakeLists.txt │ ├── primitives │ │ ├── CMakeLists.txt │ │ ├── assp │ │ │ ├── CMakeLists.txt │ │ │ ├── assp.model.xml │ │ │ ├── assp.pb_type.xml │ │ │ └── assp.sim.v │ │ ├── bidir │ │ │ ├── CMakeLists.txt │ │ │ ├── bidir.model.xml │ │ │ ├── bidir.pb_type.xml │ │ │ ├── bidir_cell.model.xml │ │ │ ├── bidir_cell.pb_type.xml │ │ │ └── bidir_cell.sim.v │ │ ├── clock │ │ │ ├── CMakeLists.txt │ │ │ ├── clock.model.xml │ │ │ ├── clock.pb_type.xml │ │ │ ├── clock_cell.model.xml │ │ │ ├── clock_cell.pb_type.xml │ │ │ └── clock_cell.sim.v │ │ ├── fpga_interconnect │ │ │ ├── CMakeLists.txt │ │ │ └── fpga_interconnect.sim.v │ │ ├── gmux │ │ │ ├── CMakeLists.txt │ │ │ ├── gmux.model.xml │ │ │ ├── gmux.pb_type.xml │ │ │ ├── gmux.sim.v │ │ │ ├── gmux_ic.model.xml │ │ │ ├── gmux_ic.pb_type.xml │ │ │ ├── gmux_ic.sim.v │ │ │ ├── gmux_ip.model.xml │ │ │ ├── gmux_ip.pb_type.xml │ │ │ └── gmux_ip.sim.v │ │ ├── gnd │ │ │ ├── CMakeLists.txt │ │ │ ├── gnd.model.xml │ │ │ ├── gnd.pb_type.xml │ │ │ └── gnd.sim.v │ │ ├── logic │ │ │ ├── CMakeLists.txt │ │ │ ├── b_frag.model.xml │ │ │ ├── b_frag.pb_type.xml │ │ │ ├── b_frag.sim.v │ │ │ ├── c_frag.model.xml │ │ │ ├── c_frag.pb_type.xml │ │ │ ├── c_frag.sim.v │ │ │ ├── c_frag_modes.model.xml │ │ │ ├── c_frag_modes.pb_type.xml │ │ │ ├── c_frag_modes.sim.v │ │ │ ├── f_frag.model.xml │ │ │ ├── f_frag.pb_type.xml │ │ │ ├── f_frag.sim.v │ │ │ ├── logic.model.xml │ │ │ ├── logic.pb_type.xml │ │ │ ├── logic.sim.v │ │ │ ├── logic_macro.model.xml │ │ │ ├── logic_macro.pb_type.xml │ │ │ ├── logic_macro.sim.v │ │ │ ├── q_frag.model.xml │ │ │ ├── q_frag.pb_type.xml │ │ │ ├── q_frag.sim.v │ │ │ ├── q_frag_modes.model.xml │ │ │ ├── q_frag_modes.pb_type.xml │ │ │ ├── q_frag_modes.sim.v │ │ │ ├── t_frag.model.xml │ │ │ ├── t_frag.pb_type.xml │ │ │ └── t_frag.sim.v │ │ ├── mult │ │ │ ├── CMakeLists.txt │ │ │ ├── mult.model.xml │ │ │ ├── mult.pb_type.xml │ │ │ └── mult.sim.v │ │ ├── ram │ │ │ ├── README.md │ │ │ ├── make_rams.py │ │ │ └── ram_modes.json │ │ ├── sdiomux │ │ │ ├── CMakeLists.txt │ │ │ ├── sdiomux.model.xml │ │ │ ├── sdiomux.pb_type.xml │ │ │ ├── sdiomux_cell.model.xml │ │ │ ├── sdiomux_cell.pb_type.xml │ │ │ └── sdiomux_cell.sim.v │ │ ├── vcc │ │ │ ├── CMakeLists.txt │ │ │ ├── vcc.model.xml │ │ │ ├── vcc.pb_type.xml │ │ │ └── vcc.sim.v │ │ └── vpr_pad │ │ │ ├── CMakeLists.txt │ │ │ ├── vpr_ipad.model.xml │ │ │ ├── vpr_ipad.pb_type.xml │ │ │ ├── vpr_opad.model.xml │ │ │ └── vpr_opad.pb_type.xml │ ├── ql-eos-s3-bels.json │ ├── ql-pp3e-bels.json │ ├── techmap │ │ ├── cells_map.v │ │ ├── lut2tomux2.v │ │ ├── lut2tomux4.v │ │ ├── lut3tomux2.v │ │ ├── mux4tomux2.v │ │ └── mux8tomux2.v │ ├── tests │ │ ├── CMakeLists.txt │ │ ├── bram │ │ │ ├── CMakeLists.txt │ │ │ ├── bram.v │ │ │ ├── chandalar.pcf │ │ │ └── jimbob4.pcf │ │ ├── btn_counter │ │ │ ├── CMakeLists.txt │ │ │ ├── README.md │ │ │ ├── btn_counter.v │ │ │ ├── chandalar-top.pcf │ │ │ ├── chandalar.pcf │ │ │ ├── jimbob4.pcf │ │ │ ├── pd64.pcf │ │ │ └── quickfeather.pcf │ │ ├── btn_ff │ │ │ ├── CMakeLists.txt │ │ │ ├── README.md │ │ │ ├── btn_ff.v │ │ │ ├── chandalar-top.pcf │ │ │ ├── chandalar.pcf │ │ │ └── jimbob4.pcf │ │ ├── btn_xor │ │ │ ├── CMakeLists.txt │ │ │ ├── README.md │ │ │ ├── btn_xor.v │ │ │ ├── chandalar-top.pcf │ │ │ ├── chandalar.pcf │ │ │ └── jimbob4.pcf │ │ ├── consts │ │ │ ├── CMakeLists.txt │ │ │ ├── chandalar.pcf │ │ │ ├── consts.v │ │ │ └── jimbob4.pcf │ │ ├── counter │ │ │ ├── CMakeLists.txt │ │ │ ├── README.md │ │ │ ├── chandalar.pcf │ │ │ ├── counter.v │ │ │ ├── iomux.json │ │ │ └── quickfeather.pcf │ │ ├── design_flow │ │ │ ├── CMakeLists.txt │ │ │ ├── IR_Remote │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── Simon_bit_serial_top_module │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── adder_8 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── bin2bcd │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── bin2seven │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── camif │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── cavlc_top │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── cf_fft_256_8 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── clock_test │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── clock_tree_design │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── chandalar.pcf │ │ │ │ └── clock_tree_design_pp3.v │ │ │ ├── counter_16bit │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── counter_32bit │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── counter_8bit │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── counter_al4s3b │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── design1 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── design10 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── design2 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── design3 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── design6 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── design8 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── design9 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── e_sdio_host_controller │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── fifo_test │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── i2c_master_top │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── iir │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── inferred_ram_test │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── jpeg_qnr │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── multiplier_8bit │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── osc_alu │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── rgb2ycrcb │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── rs_decoder_1 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── sdio_client_top │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── sha256 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── sha_top │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── shift_reg_576 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── smithwaterman │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── spi_master_top │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── sudoku_check │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── test_logic_cell │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ ├── top_120_13 │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── chandalar.pcf │ │ │ └── unsigned_mult_50 │ │ │ │ └── CMakeLists.txt │ │ ├── ext_counter │ │ │ ├── CMakeLists.txt │ │ │ ├── chandalar.pcf │ │ │ ├── ext_counter.v │ │ │ ├── jimbob4.pcf │ │ │ └── quickfeather.pcf │ │ ├── ext_mult │ │ │ ├── CMakeLists.txt │ │ │ ├── chandalar.pcf │ │ │ ├── ext_mult.v │ │ │ └── pd64.pcf │ │ ├── features │ │ │ ├── CMakeLists.txt │ │ │ ├── counter │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── counter.v │ │ │ │ └── quickfeather.pcf │ │ │ ├── counter_gclk │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── counter.v │ │ │ │ └── quickfeather.pcf │ │ │ ├── fifo │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── af512x16_512x16.v │ │ │ │ ├── af512x16_wrapper.v │ │ │ │ ├── af512x32_512x32.v │ │ │ │ ├── af512x32_wrapper.v │ │ │ │ ├── chandalar.pcf │ │ │ │ ├── chandalar_1clk.pcf │ │ │ │ ├── f1024x16_1024x16.v │ │ │ │ └── f1024x16_wrapper.v │ │ │ ├── install_test │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── consts │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ ├── chandalar_pinmap.csv │ │ │ │ │ └── consts.v │ │ │ │ ├── counter │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ └── counter.v │ │ │ │ ├── counter_assp │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── README.md │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ └── counter_assp.v │ │ │ │ ├── counter_gclk │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── README.md │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ ├── counter_gclk.sdc │ │ │ │ │ └── counter_gclk.v │ │ │ │ ├── lut1 │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ ├── chandalar_pinmap.csv │ │ │ │ │ └── lut1.v │ │ │ │ ├── lut2 │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ ├── chandalar_pinmap.csv │ │ │ │ │ └── lut2.v │ │ │ │ ├── lut3 │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ ├── chandalar_pinmap.csv │ │ │ │ │ └── lut3.v │ │ │ │ ├── lut4 │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ ├── chandalar_pinmap.csv │ │ │ │ │ └── lut4.v │ │ │ │ └── wire │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── chandalar.pcf │ │ │ │ │ ├── chandalar_pinmap.csv │ │ │ │ │ └── wire.v │ │ │ ├── ram │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── chandalar.pcf │ │ │ │ ├── r1024x16_1024x16.v │ │ │ │ ├── r1024x16_wrapper.v │ │ │ │ ├── r1024x8_1024x8.v │ │ │ │ ├── r1024x8_wrapper.v │ │ │ │ ├── r2048x8_2048x8.v │ │ │ │ ├── r2048x8_wrapper.v │ │ │ │ ├── r512x16_512x16.v │ │ │ │ ├── r512x16_wrapper.v │ │ │ │ ├── r512x32_512x32.v │ │ │ │ └── r512x32_wrapper.v │ │ │ └── ram_inference │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── chandalar.pcf │ │ │ │ └── ram_inference.v │ │ ├── lut │ │ │ ├── CMakeLists.txt │ │ │ ├── chandalar.pcf │ │ │ ├── jimbob4.pcf │ │ │ ├── lut1.v │ │ │ ├── lut2.v │ │ │ ├── lut3.v │ │ │ └── lut4.v │ │ ├── sdiomux_xor │ │ │ ├── CMakeLists.txt │ │ │ ├── chandalar.pcf │ │ │ ├── jimbob4.pcf │ │ │ └── sdiomux_xor.v │ │ └── wire │ │ │ ├── CMakeLists.txt │ │ │ ├── chandalar.pcf │ │ │ ├── jimbob4.pcf │ │ │ └── wire.v │ ├── timings │ │ └── README.md │ └── utils │ │ ├── CMakeLists.txt │ │ ├── create_clkmap_csv.py │ │ ├── create_pinmap_csv.py │ │ ├── utils.py │ │ └── verify_jlink_openocd.sh └── qlf_k4n8 │ ├── CMakeLists.txt │ ├── boards.cmake │ ├── devices │ ├── CMakeLists.txt │ └── umc22 │ │ ├── CMakeLists.txt │ │ ├── interface-mapping_24x24.xml │ │ ├── qlf_k4n8-qlf_k4n8_umc22.csv │ │ └── qlf_k4n8-qlf_k4n8_umc22_24x24.csv │ ├── techmap │ ├── CMakeLists.txt │ ├── cells_map.v │ └── cells_sim.v │ └── tests │ ├── CMakeLists.txt │ ├── design_flow │ ├── CMakeLists.txt │ ├── IR_Remote │ │ └── CMakeLists.txt │ ├── VexRiscv │ │ ├── CMakeLists.txt │ │ └── VexRiscv.sdc │ ├── adder_128 │ │ └── CMakeLists.txt │ ├── adder_64 │ │ └── CMakeLists.txt │ ├── adder_8 │ │ └── CMakeLists.txt │ ├── adder_FFs │ │ └── CMakeLists.txt │ ├── and2 │ │ └── CMakeLists.txt │ ├── and2_latch │ │ └── CMakeLists.txt │ ├── bin2bcd │ │ └── CMakeLists.txt │ ├── cavlc_top │ │ └── CMakeLists.txt │ ├── clock_tree_design │ │ └── CMakeLists.txt │ ├── conv2d │ │ ├── CMakeLists.txt │ │ └── conv2d.sdc │ ├── conv2d_no_ksa │ │ ├── CMakeLists.txt │ │ └── conv2d.sdc │ ├── counter_16bit │ │ ├── CMakeLists.txt │ │ ├── counter_16bit.pcf │ │ ├── counter_16bit.sdc │ │ ├── counter_16bit.v │ │ ├── counter_16bit_tb.v │ │ └── pinmap_qlf_k4n8_umc22.csv │ ├── counter_4clk │ │ ├── CMakeLists.txt │ │ ├── counter_4clk.sdc │ │ ├── counter_4clk.v │ │ └── test.pcf │ ├── e_sdio_host_controller │ │ └── CMakeLists.txt │ ├── full_adder │ │ └── CMakeLists.txt │ ├── io_reg_tc1 │ │ └── CMakeLists.txt │ ├── io_tc1 │ │ └── CMakeLists.txt │ ├── jpeg_qnr │ │ └── CMakeLists.txt │ ├── lut4_8ffs │ │ └── CMakeLists.txt │ ├── multi_enc_decx2x4 │ │ ├── CMakeLists.txt │ │ └── multi_enc_decx2x4.pcf │ ├── multiplier_8bit │ │ └── CMakeLists.txt │ ├── routing_test │ │ └── CMakeLists.txt │ ├── rs_decoder_1 │ │ └── CMakeLists.txt │ ├── sdio_client_top │ │ └── CMakeLists.txt │ ├── shift_reg_1024 │ │ └── CMakeLists.txt │ ├── shift_reg_576 │ │ └── CMakeLists.txt │ ├── shift_reg_8 │ │ └── CMakeLists.txt │ ├── spi_master_top │ │ └── CMakeLists.txt │ ├── top_120_13 │ │ ├── CMakeLists.txt │ │ └── top_120_13.pcf │ └── unsigned_mult_80 │ │ └── CMakeLists.txt │ ├── features │ ├── CMakeLists.txt │ ├── adder_columns │ │ └── CMakeLists.txt │ ├── adder_max │ │ └── CMakeLists.txt │ ├── clk_pcf_verify │ │ ├── CMakeLists.txt │ │ └── clock_tree_design.pcf │ ├── fast_corner │ │ └── CMakeLists.txt │ ├── install_test │ │ ├── .gitignore │ │ ├── CMakeLists.txt │ │ ├── compile_args │ │ │ ├── CMakeLists.txt │ │ │ ├── compile_args.v │ │ │ ├── includes │ │ │ │ └── add_2.v │ │ │ ├── libraries │ │ │ │ └── add_3.not_v │ │ │ └── pinmap_qlf_k4n8_umc22.csv │ │ └── counter_16bit │ │ │ ├── CMakeLists.txt │ │ │ ├── counter_16bit.pcf │ │ │ ├── counter_16bit.sdc │ │ │ ├── counter_16bit.v │ │ │ └── pinmap_qlf_k4n8_umc22.csv │ ├── io_max │ │ └── CMakeLists.txt │ ├── io_reg_max │ │ ├── CMakeLists.txt │ │ └── io_reg_max.pcf │ ├── pcf_and_sdc_option │ │ ├── CMakeLists.txt │ │ ├── shift_reg_8.pcf │ │ └── shift_reg_8.sdc │ ├── pcf_io_reg │ │ ├── CMakeLists.txt │ │ └── io_reg.pcf │ ├── pcf_option │ │ ├── CMakeLists.txt │ │ └── clock_tree_design.pcf │ ├── post_synthesis_comb │ │ ├── CMakeLists.txt │ │ └── multiplier_8bit_tb.v │ ├── post_synthesis_seq │ │ ├── CMakeLists.txt │ │ └── counter_16bit_tb.v │ ├── sdc_option │ │ ├── CMakeLists.txt │ │ └── shift_reg_8.sdc │ ├── shift_reg_4608 │ │ └── CMakeLists.txt │ └── slow_corner │ │ └── CMakeLists.txt │ └── synth_flow │ ├── CMakeLists.txt │ ├── des_perf │ └── CMakeLists.txt │ ├── iir │ └── CMakeLists.txt │ └── rgb2ycrcb │ └── CMakeLists.txt ├── requirements.txt ├── testarch ├── CMakeLists.txt ├── devices │ ├── CMakeLists.txt │ ├── clutff-bidir-s4 │ │ └── arch.xml │ ├── clutff-unidir-s4 │ │ ├── CMakeLists.txt │ │ └── arch.xml │ ├── ff-large │ │ └── arch.xml │ ├── ff1 │ │ └── arch.xml │ ├── layouts │ │ ├── 10x10.fixed_layout.xml │ │ ├── 1x1.fixed_layout.xml │ │ ├── 1x1.min.fixed_layout.xml │ │ ├── 1x2.fixed_layout.xml │ │ ├── 2x1.fixed_layout.xml │ │ ├── 2x4.fixed_layout.xml │ │ ├── 4x4.fixed_layout.xml │ │ ├── CMakeLists.txt │ │ └── all.xml │ ├── lutff-bidir-s4-g │ │ └── arch.xml │ ├── lutff-bidir-s4 │ │ └── arch.xml │ ├── lutff-dpio-bidir-s4 │ │ └── arch.xml │ ├── lutff-multi-sw │ │ └── arch.xml │ ├── lutff-unidir-s4 │ │ └── arch.xml │ ├── lutff3 │ │ └── arch.xml │ ├── routing │ │ ├── CMakeLists.txt │ │ ├── bidir-min.xml │ │ ├── bidir-s4-g.xml │ │ ├── bidir-s4.xml │ │ ├── device.xml │ │ ├── multi-sw.xml │ │ ├── unidir-min.xml │ │ └── unidir-s4.xml │ ├── test2 │ │ └── arch.xml │ ├── wire-bidir-min │ │ └── arch.xml │ ├── wire-bidir-s4 │ │ └── arch.xml │ ├── wire-unidir-min │ │ └── arch.xml │ └── wire-unidir-s4 │ │ └── arch.xml ├── primitives │ ├── CMakeLists.txt │ ├── const │ │ ├── CMakeLists.txt │ │ ├── gnd.model.xml │ │ ├── gnd.pb_type.xml │ │ ├── vcc.model.xml │ │ └── vcc.pb_type.xml │ ├── ff │ │ ├── CMakeLists.txt │ │ └── ff.sim.v │ ├── lut │ │ ├── CMakeLists.txt │ │ └── lut.sim.v │ ├── lutff │ │ ├── CMakeLists.txt │ │ ├── lutff.model.xml │ │ ├── lutff.pb_type.xml │ │ └── unused.lutff.sim.v │ └── omux │ │ └── CMakeLists.txt ├── techmap │ └── ff_map.v ├── tiles │ ├── CMakeLists.txt │ ├── clutff │ │ ├── CMakeLists.txt │ │ ├── clutff.model.xml │ │ └── clutff.pb_type.xml │ ├── const │ │ ├── CMakeLists.txt │ │ ├── gnd.model.xml │ │ ├── gnd.pb_type.xml │ │ ├── vcc.model.xml │ │ └── vcc.pb_type.xml │ ├── ff-large │ │ ├── CMakeLists.txt │ │ ├── ff-large.model.xml │ │ └── ff-large.pb_type.xml │ ├── ff1 │ │ ├── CMakeLists.txt │ │ ├── ff1.model.xml │ │ └── ff1.pb_type.xml │ ├── lutff │ │ ├── CMakeLists.txt │ │ ├── lutff.model.xml │ │ └── lutff.pb_type.xml │ ├── lutff3 │ │ ├── CMakeLists.txt │ │ ├── lutff3.model.xml │ │ └── lutff3.pb_type.xml │ └── wire │ │ ├── CMakeLists.txt │ │ ├── wire.model.xml │ │ └── wire.pb_type.xml ├── utils │ └── testarch_graph.py └── yosys.tcl ├── tests ├── .gitignore ├── 0-const │ ├── CMakeLists.txt │ └── const.v ├── 1-wire │ ├── CMakeLists.txt │ └── wire.v ├── 2-mwire │ ├── CMakeLists.txt │ └── mwire.v ├── 3-ff │ ├── CMakeLists.txt │ └── ff.v ├── 3-lut4 │ ├── CMakeLists.txt │ └── lut4.v ├── 3-lut5x2 │ ├── CMakeLists.txt │ └── lut5x2.v ├── 3-lut6 │ ├── CMakeLists.txt │ └── lut6.v ├── 3-lut7 │ ├── CMakeLists.txt │ └── lut7.v ├── 3-lut8 │ ├── CMakeLists.txt │ └── lut8.v ├── 4-lutff │ ├── CMakeLists.txt │ └── lutff.v ├── 4-mlut │ ├── CMakeLists.txt │ └── mlut.eblif ├── 5-lut_cascade_1 │ ├── CMakeLists.txt │ └── lut_cascade_1.v ├── 6-big_xor │ ├── CMakeLists.txt │ └── big_xor.v ├── 6-counter │ ├── CMakeLists.txt │ └── counter.v ├── 6-led │ ├── CMakeLists.txt │ └── led.v ├── 6-rot │ ├── CMakeLists.txt │ └── rot.v ├── 7-carry_stress │ ├── CMakeLists.txt │ └── generate_carry_test.py ├── 9-scalable_proc │ ├── CMakeLists.txt │ ├── README.md │ ├── basys3.pcf │ ├── basys3.xdc │ ├── basys3_top.v │ ├── parametrize.py │ ├── processing_unit.v │ ├── scalable_proc.v │ ├── simpleuart.v │ └── utils │ │ ├── receiver.py │ │ └── rom_generator.py ├── 9-soc │ ├── CMakeLists.txt │ ├── murax │ │ ├── CMakeLists.txt │ │ ├── Murax.v │ │ ├── Murax.v_toplevel_system_ram_ram_symbol0.bin │ │ ├── Murax.v_toplevel_system_ram_ram_symbol1.bin │ │ ├── Murax.v_toplevel_system_ram_ram_symbol2.bin │ │ ├── Murax.v_toplevel_system_ram_ram_symbol3.bin │ │ ├── README.md │ │ ├── basys3-full.pcf │ │ ├── basys3-full_toplevel_100.v │ │ ├── basys3-full_toplevel_50.v │ │ ├── basys3.pcf │ │ ├── basys3.xdc │ │ ├── basys3_toplevel.v │ │ ├── hx8k-b-evn.pcf │ │ ├── hx8k_b_evn_toplevel.v │ │ ├── nexys_video_toplevel_100.v │ │ └── nexys_video_toplevel_50.v │ └── picosoc │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── basys3-full_demo_100.v │ │ ├── basys3-full_demo_50.v │ │ ├── basys3.xdc │ │ ├── basys3_demo.v │ │ ├── basys3_demo_tb.v │ │ ├── firmware.hex │ │ ├── firmware │ │ ├── Makefile │ │ ├── README.md │ │ ├── firmware.c │ │ ├── sections.lds │ │ └── start.s │ │ ├── firmware_noflash_100.hex │ │ ├── firmware_noflash_25.hex │ │ ├── firmware_noflash_50.hex │ │ ├── hex2progmem.py │ │ ├── hx8k-b-evn.pcf │ │ ├── hx8kdemo.v │ │ ├── hx8kdemo_tb.v │ │ ├── nexys_video_demo_100.v │ │ ├── nexys_video_demo_50.v │ │ ├── picorv32.v │ │ ├── picosoc.v │ │ ├── picosoc_noflash.v │ │ ├── simpleuart.v │ │ ├── spiflash.v │ │ ├── spiflash_tb.v │ │ └── spimemio.v └── CMakeLists.txt ├── tox.ini ├── utils ├── CMakeLists.txt ├── check_cache.py ├── check_graph.py ├── check_ptc.py ├── clean_json5.py ├── compare_usage.py ├── concatenate_v_sources.py ├── conftest.py ├── convert_connection_box_to_mat.py ├── create_pinmap.py ├── deps_verilog.py ├── deps_xml.py ├── eblif.py ├── fusesoc_get_sources.py ├── gather_usage.py ├── grid_visualizer │ ├── README.md │ ├── examples │ │ └── tilegird_artix7_roi_0_0_52_61.svg │ ├── grid_visualizer.py │ └── tile_color_scheme_extractor.py ├── ipynb │ └── Parameter_Sweep_using_fpga_tool_perf.ipynb ├── lib │ ├── __init__.py │ ├── argparse_extra.py │ ├── asserts.py │ ├── collections_extra.py │ ├── connection_box_tools.py │ ├── connection_database.py │ ├── connection_database.sql │ ├── deps.py │ ├── flatten.py │ ├── mux.py │ ├── parse_route.py │ ├── path.py │ ├── pb_type.py │ ├── pb_type_test.py │ ├── pb_type_xml.py │ ├── perf_utils.py │ ├── progressbar_utils.py │ ├── rr_graph │ │ ├── README.md │ │ ├── __init__.py │ │ ├── __main__.py │ │ ├── channel.py │ │ ├── channel2.py │ │ ├── graph.py │ │ ├── graph2.py │ │ ├── points.py │ │ ├── tests │ │ │ ├── __init__.py │ │ │ ├── test_channel.py │ │ │ ├── test_channel2.py │ │ │ ├── test_graph.py │ │ │ ├── test_graph2.py │ │ │ ├── test_points.py │ │ │ └── test_tracks.py │ │ └── tracks.py │ ├── rr_graph_capnp │ │ ├── __init__.py │ │ └── graph2.py │ ├── rr_graph_xml │ │ ├── graph2.py │ │ └── utils.py │ └── xmlinc.py ├── listdirs.py ├── listfiles.py ├── mux_gen.py ├── n.py ├── newest.py ├── pcf_compare.py ├── plot_connection_box.py ├── print_connection_map_lookahead.py ├── print_graph.py ├── print_net_sources.py ├── print_place_delay_matrix.py ├── print_qor.py ├── quiet_cmd.sh ├── reparse_graph.py ├── report_block_usage.py ├── report_timing.py ├── rr_graph_walk │ ├── README.md │ └── rr_graph_walk.py ├── simple_router_analysis.py ├── specialize_carrychains.py ├── template.arch.xml ├── tile_splitter │ ├── __init__.py │ ├── grid.py │ └── tests │ │ ├── __init__.py │ │ └── test_grid.py ├── update_arch_tiles.py ├── update_arch_timings.py ├── update_cache.py ├── update_tools │ ├── .gitignore │ ├── Makefile │ └── update_tools.py ├── vpr_pbtype_arch_wrapper.py ├── vpr_pbtype_to_eblif.py └── vpr_place_view.py ├── vpr ├── CMakeLists.txt ├── buf │ ├── CMakeLists.txt │ ├── buf.model.xml │ └── buf.pb_type.xml ├── const │ ├── CMakeLists.txt │ └── const.pb_type.xml ├── dual-pad │ ├── CMakeLists.txt │ ├── dual-pad.pb_type.xml │ ├── ibuf.pb_type.xml │ └── obuf.pb_type.xml ├── ff │ ├── CMakeLists.txt │ └── vpr_ff.sim.v ├── ibuf │ ├── CMakeLists.txt │ └── ibuf.pb_type.xml ├── muxes │ ├── CMakeLists.txt │ └── logic │ │ ├── CMakeLists.txt │ │ ├── mux2 │ │ ├── CMakeLists.txt │ │ ├── mux2.sim.v │ │ └── simtest │ │ │ └── test_mux2.py │ │ ├── mux4 │ │ └── mux4.sim.v │ │ ├── mux5 │ │ └── mux5.sim.v │ │ ├── mux6 │ │ └── mux6.sim.v │ │ ├── mux7 │ │ └── mux7.sim.v │ │ └── mux8 │ │ ├── CMakeLists.txt │ │ └── mux8.sim.v ├── obuf │ ├── CMakeLists.txt │ └── obuf.pb_type.xml ├── pad │ ├── CMakeLists.txt │ └── pad.pb_type.xml ├── primitives.v └── wire │ ├── CMakeLists.txt │ └── wire.pb_type.xml └── xilinx ├── CMakeLists.txt ├── common ├── CMakeLists.txt ├── cmake │ ├── CMakeLists.txt │ ├── arch_define.cmake │ ├── device_define.cmake │ ├── install.cmake │ ├── project_ray.cmake │ └── vivado.cmake ├── libraries │ ├── cells_xtra.xml │ ├── generate_verilog.py │ └── parse_pdf_modules.py ├── primitives │ ├── CMakeLists.txt │ ├── bram │ │ ├── CMakeLists.txt │ │ ├── bram.model.xml │ │ ├── bram.pb_type.xml │ │ ├── ramb18e1.model.xml │ │ ├── ramb18e1.pb_type.xml │ │ ├── rambfifo36e1.model.xml │ │ └── rambfifo36e1.pb_type.xml │ ├── bram_l │ │ ├── CMakeLists.txt │ │ ├── bram_l.model.xml │ │ └── bram_l.pb_type.xml │ ├── bram_r │ │ ├── CMakeLists.txt │ │ ├── bram_r.model.xml │ │ └── bram_r.pb_type.xml │ ├── bufgctrl │ │ ├── CMakeLists.txt │ │ ├── bufgctrl.model.xml │ │ └── bufgctrl.pb_type.xml │ ├── bufhce │ │ ├── CMakeLists.txt │ │ ├── ntemplate.bufhceN.model.xml │ │ └── ntemplate.bufhceN.pb_type.xml │ ├── common_slice │ │ ├── CMakeLists.txt │ │ ├── Nlut │ │ │ ├── CMakeLists.txt │ │ │ ├── notes.md │ │ │ ├── ntemplate.Nlut.model.xml │ │ │ ├── ntemplate.Nlut.pb_type.xml │ │ │ └── ntemplate.Nlut.sim.v │ │ ├── carry │ │ │ ├── CMakeLists.txt │ │ │ ├── carry0.model.xml │ │ │ ├── carry0.pb_type.xml │ │ │ ├── carry0.sim.v │ │ │ ├── carry4_vpr.model.xml │ │ │ ├── carry4_vpr.pb_type.xml │ │ │ ├── carry4_vpr.sim.v │ │ │ └── carry_cout_plug.sim.v │ │ ├── common_lut_and_f78mux.model.xml │ │ ├── common_lut_and_f78mux.pb_type.xml │ │ ├── common_slice.model.xml │ │ ├── common_slice.pb_type.xml │ │ ├── common_slice.sim.v │ │ ├── muxes │ │ │ ├── CMakeLists.txt │ │ │ ├── f6mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── f7amux │ │ │ │ └── CMakeLists.txt │ │ │ ├── f7bmux │ │ │ │ └── CMakeLists.txt │ │ │ └── f8mux │ │ │ │ └── CMakeLists.txt │ │ └── routing │ │ │ ├── CMakeLists.txt │ │ │ ├── N5ffmux │ │ │ └── CMakeLists.txt │ │ │ ├── Ncy0 │ │ │ └── CMakeLists.txt │ │ │ ├── Nused │ │ │ ├── CMakeLists.txt │ │ │ ├── ntemplate.Nused.model.xml │ │ │ ├── ntemplate.Nused.pb_type.xml │ │ │ └── ntemplate.Nused.sim.v │ │ │ ├── affmux │ │ │ └── CMakeLists.txt │ │ │ ├── aoutmux │ │ │ └── CMakeLists.txt │ │ │ ├── bffmux │ │ │ └── CMakeLists.txt │ │ │ ├── boutmux │ │ │ └── CMakeLists.txt │ │ │ ├── ceusedmux │ │ │ ├── CMakeLists.txt │ │ │ ├── ceusedmux.pb_type.xml │ │ │ └── ceusedmux.sim.v │ │ │ ├── cffmux │ │ │ └── CMakeLists.txt │ │ │ ├── clkinv │ │ │ ├── CMakeLists.txt │ │ │ ├── clkinv.pb_type.xml │ │ │ └── clkinv.sim.v │ │ │ ├── coutmux │ │ │ └── CMakeLists.txt │ │ │ ├── coutused │ │ │ ├── CMakeLists.txt │ │ │ ├── coutused.pb_type.xml │ │ │ └── coutused.sim.v │ │ │ ├── dffmux │ │ │ └── CMakeLists.txt │ │ │ ├── doutmux │ │ │ └── CMakeLists.txt │ │ │ ├── precyinit_mux │ │ │ └── CMakeLists.txt │ │ │ └── srusedmux │ │ │ ├── CMakeLists.txt │ │ │ ├── srusedmux.pb_type.xml │ │ │ └── srusedmux.sim.v │ ├── dsp48e1 │ │ ├── CMakeLists.txt │ │ ├── alu │ │ │ ├── CMakeLists.txt │ │ │ └── alu.sim.v │ │ ├── alumode_mux │ │ │ └── CMakeLists.txt │ │ ├── carryinsel_logic │ │ │ ├── CMakeLists.txt │ │ │ ├── carryin_mux │ │ │ │ └── CMakeLists.txt │ │ │ └── carryinsel_logic.sim.v │ │ ├── carryinsel_mux │ │ │ └── CMakeLists.txt │ │ ├── creg_mux │ │ │ └── CMakeLists.txt │ │ ├── dsp48e1.sim.v │ │ ├── dual_ad_preadder │ │ │ ├── CMakeLists.txt │ │ │ ├── a_adder_mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── acout_mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── ain_mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── amult_mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── amux │ │ │ │ └── CMakeLists.txt │ │ │ ├── dmux │ │ │ │ └── CMakeLists.txt │ │ │ └── dual_ad_preadder.sim.v │ │ ├── dual_b_reg │ │ │ ├── CMakeLists.txt │ │ │ ├── b1reg_mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── b2reg_mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── bc_mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── bin_mux │ │ │ │ └── CMakeLists.txt │ │ │ ├── bmult_mux │ │ │ │ └── CMakeLists.txt │ │ │ └── dual_b_reg.sim.v │ │ ├── inmode_mux │ │ │ └── CMakeLists.txt │ │ ├── mult25x18 │ │ │ ├── CMakeLists.txt │ │ │ └── mult25x18.sim.v │ │ ├── mult_mux │ │ │ └── CMakeLists.txt │ │ ├── nmux2 │ │ │ └── nmux2.sim.v │ │ ├── nreg │ │ │ ├── CMakeLists.txt │ │ │ ├── nreg.sim.v │ │ │ └── reg.sim.v │ │ ├── opmode_mux │ │ │ └── CMakeLists.txt │ │ ├── xmux │ │ │ └── CMakeLists.txt │ │ ├── ymux │ │ │ └── CMakeLists.txt │ │ └── zmux │ │ │ └── CMakeLists.txt │ ├── ff │ │ ├── CMakeLists.txt │ │ ├── ff.model.xml │ │ └── ff.pb_type.xml │ ├── gtpe2_channel │ │ ├── CMakeLists.txt │ │ ├── gtpe2_channel.model.xml │ │ └── gtpe2_channel.pb_type.xml │ ├── gtpe2_common │ │ ├── CMakeLists.txt │ │ ├── gtpe2_common.model.xml │ │ └── gtpe2_common.pb_type.xml │ ├── ibufds_gte2 │ │ ├── CMakeLists.txt │ │ ├── ibufds_gte2.model.xml │ │ └── ibufds_gte2.pb_type.xml │ ├── idelayctrl │ │ ├── CMakeLists.txt │ │ ├── idelayctrl.model.xml │ │ └── idelayctrl.pb_type.xml │ ├── idelaye2 │ │ ├── CMakeLists.txt │ │ ├── idelaye2.model.xml │ │ └── idelaye2.pb_type.xml │ ├── ilogice3 │ │ ├── CMakeLists.txt │ │ ├── ilogice3.model.xml │ │ └── ilogice3.pb_type.xml │ ├── iob33 │ │ ├── CMakeLists.txt │ │ ├── inpad.pb_type.xml │ │ ├── iob33.model.xml │ │ ├── iob33.pb_type.xml │ │ ├── modes │ │ │ ├── CMakeLists.txt │ │ │ ├── ibuf.xml │ │ │ ├── iobuf.xml │ │ │ ├── no_ibuf.xml │ │ │ ├── no_obuf.xml │ │ │ └── obuft.xml │ │ └── outpad.pb_type.xml │ ├── iob33m │ │ ├── CMakeLists.txt │ │ ├── iob33m.model.xml │ │ └── iob33m.pb_type.xml │ ├── iob33s │ │ ├── CMakeLists.txt │ │ ├── iob33s.model.xml │ │ └── iob33s.pb_type.xml │ ├── ipad │ │ ├── CMakeLists.txt │ │ ├── ipad.model.xml │ │ └── ipad.pb_type.xml │ ├── mmcme2_adv │ │ ├── CMakeLists.txt │ │ ├── mmcme2_adv.model.xml │ │ └── mmcme2_adv.pb_type.xml │ ├── ologice3 │ │ ├── CMakeLists.txt │ │ ├── ologice3.model.xml │ │ └── ologice3.pb_type.xml │ ├── opad │ │ ├── CMakeLists.txt │ │ ├── opad.model.xml │ │ └── opad.pb_type.xml │ ├── pcie_2_1 │ │ ├── CMakeLists.txt │ │ ├── pcie_2_1.model.xml │ │ └── pcie_2_1.pb_type.xml │ ├── plle2_adv │ │ ├── CMakeLists.txt │ │ ├── plle2_adv.model.xml │ │ └── plle2_adv.pb_type.xml │ ├── ps7 │ │ ├── CMakeLists.txt │ │ ├── ps7.model.xml │ │ └── ps7.pb_type.xml │ ├── slicel │ │ ├── CMakeLists.txt │ │ ├── ntemplate.slicelN.model.xml │ │ ├── ntemplate.slicelN.pb_type.xml │ │ └── slicel.sim.v │ ├── slicem │ │ ├── CMakeLists.txt │ │ ├── Ndram │ │ │ ├── CMakeLists.txt │ │ │ ├── README.md │ │ │ ├── b_dram.pb_type.xml │ │ │ ├── d_dram.pb_type.xml │ │ │ ├── d_dram128.pb_type.xml │ │ │ ├── dpram32.pb_type.xml │ │ │ ├── dpram64.pb_type.xml │ │ │ ├── dpram64_for_ram128x1d.pb_type.xml │ │ │ ├── ntemplate.N_dram.model.xml │ │ │ ├── ntemplate.N_dram.pb_type.xml │ │ │ ├── ntemplate.N_dram128.pb_type.xml │ │ │ └── spram32.pb_type.xml │ │ ├── di64_stub.sim.v │ │ ├── dram.md │ │ ├── dram_2_output_stub.sim.v │ │ ├── dram_4_output_stub.sim.v │ │ ├── dram_8_output_stub.sim.v │ │ ├── modes.md │ │ ├── shift.md │ │ ├── slicem.model.xml │ │ ├── slicem.pb_type.xml │ │ ├── srl │ │ │ ├── CMakeLists.txt │ │ │ ├── a_srl.pb_type.xml │ │ │ ├── ntemplate.N_srl.pb_type.xml │ │ │ ├── srlc16e_vpr.model.xml │ │ │ ├── srlc16e_vpr_0.pb_type.xml │ │ │ ├── srlc16e_vpr_1.pb_type.xml │ │ │ ├── srlc32e_vpr.model.xml │ │ │ └── srlc32e_vpr.pb_type.xml │ │ └── wemux.pb_type.xml │ └── tieoff │ │ ├── CMakeLists.txt │ │ └── tieoff.sim.v └── utils │ ├── CMakeLists.txt │ ├── README.md │ ├── add_pack_patterns.py │ ├── animate_router_pop.py │ ├── annotate_vpr_log.py │ ├── output_timing.tcl │ ├── prjxray_arch_import.py │ ├── prjxray_assign_tile_pin_direction.py │ ├── prjxray_constant_site_pins.py │ ├── prjxray_create_edges.py │ ├── prjxray_create_equiv_tiles.py │ ├── prjxray_create_pinmap_csv.py │ ├── prjxray_create_synth_tiles.py │ ├── prjxray_db_cache.py │ ├── prjxray_define_segments.py │ ├── prjxray_edge_library.py │ ├── prjxray_find_inode.py │ ├── prjxray_form_channels.py │ ├── prjxray_generate_dummy_site.py │ ├── prjxray_get_fabric.py │ ├── prjxray_import_tile_capacity.py │ ├── prjxray_lookup_inode.py │ ├── prjxray_make_ps7_models.py │ ├── prjxray_pcf_to_xdc.py │ ├── prjxray_physical_tile_import.py │ ├── prjxray_print_net_map.py │ ├── prjxray_routing_import.py │ ├── prjxray_tile_import.py │ ├── timing_summary.py │ ├── timing_utils.tcl │ ├── vivado_create_runme.py │ └── vivado_create_sim.py └── xc7 ├── CMakeLists.txt ├── README.md ├── arch.cmake ├── archs ├── CMakeLists.txt ├── artix7 │ ├── CMakeLists.txt │ ├── devices │ │ ├── CMakeLists.txt │ │ ├── xc7a50t-arty-swbut-overlay-virt │ │ │ ├── CMakeLists.txt │ │ │ └── design.json │ │ ├── xc7a50t-arty-swbut-pr1-roi-virt │ │ │ ├── CMakeLists.txt │ │ │ └── design.json │ │ ├── xc7a50t-arty-swbut-roi-virt │ │ │ └── CMakeLists.txt │ │ ├── xc7a50t-arty-switch-processing-overlay-virt │ │ │ ├── CMakeLists.txt │ │ │ └── design.json │ │ ├── xc7a50t-arty-switch-processing-pr1-roi-virt │ │ │ ├── CMakeLists.txt │ │ │ └── design.json │ │ ├── xc7a50t-arty-switch-processing-pr2-roi-virt │ │ │ ├── CMakeLists.txt │ │ │ └── design.json │ │ ├── xc7a50t-arty-uart-roi-virt │ │ │ └── CMakeLists.txt │ │ ├── xc7a50t-basys3-roi-virt │ │ │ └── CMakeLists.txt │ │ ├── xc7a50t-bottom-virt │ │ │ └── CMakeLists.txt │ │ └── xc7a50t-virt │ │ │ └── CMakeLists.txt │ └── tiles │ │ ├── CMakeLists.txt │ │ ├── bram_l │ │ └── CMakeLists.txt │ │ ├── bram_r │ │ └── CMakeLists.txt │ │ ├── bufgctrl │ │ └── CMakeLists.txt │ │ ├── clbll_l │ │ └── CMakeLists.txt │ │ ├── clbll_r │ │ └── CMakeLists.txt │ │ ├── clblm_l │ │ └── CMakeLists.txt │ │ ├── clblm_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_bot_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_top_r │ │ └── CMakeLists.txt │ │ ├── clk_hrow_bot_r │ │ └── CMakeLists.txt │ │ ├── clk_hrow_top_r │ │ └── CMakeLists.txt │ │ ├── cmt_top_l_lower_b │ │ └── CMakeLists.txt │ │ ├── cmt_top_l_upper_t │ │ └── CMakeLists.txt │ │ ├── cmt_top_r_lower_b │ │ └── CMakeLists.txt │ │ ├── cmt_top_r_upper_t │ │ └── CMakeLists.txt │ │ ├── gtp_channel_0 │ │ └── CMakeLists.txt │ │ ├── gtp_channel_1 │ │ └── CMakeLists.txt │ │ ├── gtp_channel_2 │ │ └── CMakeLists.txt │ │ ├── gtp_channel_3 │ │ └── CMakeLists.txt │ │ ├── gtp_common │ │ └── CMakeLists.txt │ │ ├── gtpe2_channel │ │ └── CMakeLists.txt │ │ ├── gtpe2_common │ │ └── CMakeLists.txt │ │ ├── hclk_ioi3 │ │ └── CMakeLists.txt │ │ ├── ibufds_gte2 │ │ └── CMakeLists.txt │ │ ├── int_l │ │ └── CMakeLists.txt │ │ ├── int_r │ │ └── CMakeLists.txt │ │ ├── ipad │ │ └── CMakeLists.txt │ │ ├── liob33_sing │ │ └── CMakeLists.txt │ │ ├── mmcme2_adv │ │ └── CMakeLists.txt │ │ ├── opad │ │ └── CMakeLists.txt │ │ ├── pcie_2_1 │ │ └── CMakeLists.txt │ │ ├── pcie_bot │ │ └── CMakeLists.txt │ │ ├── riopad_m │ │ └── CMakeLists.txt │ │ ├── slicel │ │ └── CMakeLists.txt │ │ └── slicem │ │ └── CMakeLists.txt ├── artix7_100t │ ├── CMakeLists.txt │ ├── devices │ │ ├── CMakeLists.txt │ │ └── xc7a100t-virt │ │ │ └── CMakeLists.txt │ └── tiles │ │ ├── CMakeLists.txt │ │ ├── bram_l │ │ └── CMakeLists.txt │ │ ├── bram_r │ │ └── CMakeLists.txt │ │ ├── bufgctrl │ │ └── CMakeLists.txt │ │ ├── clbll_l │ │ └── CMakeLists.txt │ │ ├── clbll_r │ │ └── CMakeLists.txt │ │ ├── clblm_l │ │ └── CMakeLists.txt │ │ ├── clblm_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_bot_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_top_r │ │ └── CMakeLists.txt │ │ ├── cmt_top_l_upper_t │ │ └── CMakeLists.txt │ │ ├── cmt_top_r_upper_t │ │ └── CMakeLists.txt │ │ ├── gtp_channel_0 │ │ └── CMakeLists.txt │ │ ├── gtp_channel_1 │ │ └── CMakeLists.txt │ │ ├── gtp_channel_2 │ │ └── CMakeLists.txt │ │ ├── gtp_channel_3 │ │ └── CMakeLists.txt │ │ ├── gtp_common │ │ └── CMakeLists.txt │ │ ├── gtpe2_channel │ │ └── CMakeLists.txt │ │ ├── gtpe2_common │ │ └── CMakeLists.txt │ │ ├── hclk_ioi3 │ │ └── CMakeLists.txt │ │ ├── ibufds_gte2 │ │ └── CMakeLists.txt │ │ ├── ipad │ │ └── CMakeLists.txt │ │ ├── liob33_sing │ │ └── CMakeLists.txt │ │ ├── opad │ │ └── CMakeLists.txt │ │ ├── pcie_2_1 │ │ └── CMakeLists.txt │ │ ├── pcie_bot │ │ └── CMakeLists.txt │ │ ├── riopad_m │ │ └── CMakeLists.txt │ │ ├── slicel │ │ └── CMakeLists.txt │ │ └── slicem │ │ └── CMakeLists.txt ├── artix7_200t │ ├── CMakeLists.txt │ ├── devices │ │ ├── CMakeLists.txt │ │ ├── xc7a200t-mid-virt │ │ │ └── CMakeLists.txt │ │ └── xc7a200t-virt │ │ │ └── CMakeLists.txt │ └── tiles │ │ ├── CMakeLists.txt │ │ ├── bram_l │ │ └── CMakeLists.txt │ │ ├── bram_r │ │ └── CMakeLists.txt │ │ ├── bufgctrl │ │ └── CMakeLists.txt │ │ ├── clbll_l │ │ └── CMakeLists.txt │ │ ├── clbll_r │ │ └── CMakeLists.txt │ │ ├── clblm_l │ │ └── CMakeLists.txt │ │ ├── clblm_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_bot_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_top_r │ │ └── CMakeLists.txt │ │ ├── gtp_channel_0_mid_left │ │ └── CMakeLists.txt │ │ ├── gtp_channel_0_mid_right │ │ └── CMakeLists.txt │ │ ├── gtp_channel_1_mid_left │ │ └── CMakeLists.txt │ │ ├── gtp_channel_1_mid_right │ │ └── CMakeLists.txt │ │ ├── gtp_channel_2_mid_left │ │ └── CMakeLists.txt │ │ ├── gtp_channel_2_mid_right │ │ └── CMakeLists.txt │ │ ├── gtp_channel_3_mid_left │ │ └── CMakeLists.txt │ │ ├── gtp_channel_3_mid_right │ │ └── CMakeLists.txt │ │ ├── gtp_common_mid_left │ │ └── CMakeLists.txt │ │ ├── gtp_common_mid_right │ │ └── CMakeLists.txt │ │ ├── gtpe2_channel │ │ └── CMakeLists.txt │ │ ├── gtpe2_common │ │ └── CMakeLists.txt │ │ ├── hclk_ioi3 │ │ └── CMakeLists.txt │ │ ├── ibufds_gte2 │ │ └── CMakeLists.txt │ │ ├── ipad │ │ └── CMakeLists.txt │ │ ├── opad │ │ └── CMakeLists.txt │ │ ├── pcie_2_1 │ │ └── CMakeLists.txt │ │ ├── pcie_bot │ │ └── CMakeLists.txt │ │ ├── slicel │ │ └── CMakeLists.txt │ │ └── slicem │ │ └── CMakeLists.txt ├── spartan7 │ ├── CMakeLists.txt │ ├── devices │ │ ├── CMakeLists.txt │ │ └── xc7s50-virt │ │ │ └── CMakeLists.txt │ └── tiles │ │ ├── CMakeLists.txt │ │ ├── bram_l │ │ └── CMakeLists.txt │ │ ├── bram_r │ │ └── CMakeLists.txt │ │ ├── bufgctrl │ │ └── CMakeLists.txt │ │ ├── clbll_l │ │ └── CMakeLists.txt │ │ ├── clbll_r │ │ └── CMakeLists.txt │ │ ├── clblm_l │ │ └── CMakeLists.txt │ │ ├── clblm_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_bot_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_top_r │ │ └── CMakeLists.txt │ │ ├── cmt_top_l_lower_b │ │ └── CMakeLists.txt │ │ ├── cmt_top_r_lower_b │ │ └── CMakeLists.txt │ │ ├── hclk_ioi3 │ │ └── CMakeLists.txt │ │ ├── mmcme2_adv │ │ └── CMakeLists.txt │ │ ├── slicel │ │ └── CMakeLists.txt │ │ └── slicem │ │ └── CMakeLists.txt ├── zynq7 │ ├── CMakeLists.txt │ ├── devices │ │ ├── CMakeLists.txt │ │ ├── xc7z010-virt │ │ │ └── CMakeLists.txt │ │ └── xc7z010-zybo-roi-virt │ │ │ └── CMakeLists.txt │ └── tiles │ │ ├── CMakeLists.txt │ │ ├── bram_l │ │ └── CMakeLists.txt │ │ ├── bram_r │ │ └── CMakeLists.txt │ │ ├── bufgctrl │ │ └── CMakeLists.txt │ │ ├── clbll_l │ │ └── CMakeLists.txt │ │ ├── clbll_r │ │ └── CMakeLists.txt │ │ ├── clblm_l │ │ └── CMakeLists.txt │ │ ├── clblm_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_bot_r │ │ └── CMakeLists.txt │ │ ├── clk_bufg_top_r │ │ └── CMakeLists.txt │ │ ├── cmt_top_l_upper_t │ │ └── CMakeLists.txt │ │ ├── cmt_top_r_upper_t │ │ └── CMakeLists.txt │ │ ├── hclk_ioi3 │ │ └── CMakeLists.txt │ │ ├── int_l │ │ └── CMakeLists.txt │ │ ├── int_r │ │ └── CMakeLists.txt │ │ ├── liob33_sing │ │ └── CMakeLists.txt │ │ ├── pss2 │ │ └── CMakeLists.txt │ │ ├── slicel │ │ └── CMakeLists.txt │ │ └── slicem │ │ └── CMakeLists.txt └── zynq7_z020 │ ├── CMakeLists.txt │ ├── devices │ ├── CMakeLists.txt │ └── xc7z020-virt │ │ └── CMakeLists.txt │ └── tiles │ ├── CMakeLists.txt │ ├── bram_l │ └── CMakeLists.txt │ ├── bram_r │ └── CMakeLists.txt │ ├── bufgctrl │ └── CMakeLists.txt │ ├── clbll_l │ └── CMakeLists.txt │ ├── clbll_r │ └── CMakeLists.txt │ ├── clblm_l │ └── CMakeLists.txt │ ├── clblm_r │ └── CMakeLists.txt │ ├── clk_bufg_bot_r │ └── CMakeLists.txt │ ├── clk_bufg_top_r │ └── CMakeLists.txt │ ├── cmt_top_l_upper_t │ └── CMakeLists.txt │ ├── cmt_top_r_upper_t │ └── CMakeLists.txt │ ├── hclk_ioi3 │ └── CMakeLists.txt │ ├── int_l │ └── CMakeLists.txt │ ├── int_r │ └── CMakeLists.txt │ ├── liob33_sing │ └── CMakeLists.txt │ ├── pss2 │ └── CMakeLists.txt │ ├── slicel │ └── CMakeLists.txt │ └── slicem │ └── CMakeLists.txt ├── artix7_tile_colormap.json ├── bels.json ├── boards.cmake ├── dummy.xml ├── empty.xml ├── techmap ├── carry_map.v ├── cells_map.v ├── cells_sim.v ├── clean_carry_map.v ├── iobs.v ├── retarget.v └── unmap.v ├── tests ├── CMakeLists.txt ├── bram │ ├── CMakeLists.txt │ └── bram.v ├── bram_init_test │ ├── CMakeLists.txt │ ├── bram_init_test_18.v │ └── bram_init_test_36.v ├── bram_sdp_init_test │ ├── CMakeLists.txt │ ├── bram_sdp_init_test_18.v │ └── bram_sdp_init_test_36.v ├── bram_sdp_test │ ├── CMakeLists.txt │ ├── bram_sdp_test_18.v │ └── bram_sdp_test_36.v ├── bram_shifter │ ├── CMakeLists.txt │ ├── bram_shifter_18.v │ └── bram_shifter_36.v ├── bram_test │ ├── CMakeLists.txt │ ├── bram_test.v │ └── generate_test.py ├── bufgce │ ├── CMakeLists.txt │ ├── bufgce_arty.v │ └── bufgce_nexys_video.v ├── bufgmux │ ├── CMakeLists.txt │ ├── arty.xdc │ ├── bufgmux.v │ └── nexys_video.xdc ├── buttons │ ├── CMakeLists.txt │ ├── buttons_arty.v │ ├── buttons_arty_overlay.v │ ├── buttons_arty_rev.v │ ├── buttons_ax7050.v │ ├── buttons_ax7050.xdc │ ├── buttons_basys3.v │ ├── buttons_basys3_full.v │ ├── buttons_marszx3.v │ ├── buttons_nexys_video.v │ ├── buttons_pynqz1.v │ ├── buttons_zedboard.v │ └── buttons_zybo.v ├── carry │ ├── CMakeLists.txt │ └── carry.v ├── chain_packing │ ├── CMakeLists.txt │ └── counter.v ├── common │ ├── CMakeLists.txt │ ├── arty_swbut.pcf │ ├── arty_swbut_pr.pcf │ ├── arty_swbut_pr_2clk.pcf │ ├── arty_swbut_pr_overlay.pcf │ ├── arty_switch_processing_monolithic.pcf │ ├── arty_switch_processing_overlay.pcf │ ├── arty_switch_processing_pr1.pcf │ ├── arty_switch_processing_pr2.pcf │ ├── arty_uart.pcf │ ├── basys3.pcf │ ├── basys3.sdc │ ├── basys3.xdc │ ├── basys3_bottom.pcf │ ├── basys3_bottom_pmod.pcf │ ├── basys3_pmod.pcf │ ├── error_output_logic.v │ ├── error_output_logic_tb.v │ ├── error_output_logic_unt.v │ ├── marszx3.pcf │ ├── netv2_a100t_pcie_complex.xdc │ ├── nexys_swbut.pcf │ ├── nexys_video.pcf │ ├── nexys_video.xdc │ ├── nexys_video_noclk.xdc │ ├── pynqz1.pcf │ ├── ram_shifter.v │ ├── ram_test.v │ ├── read_uart.py │ ├── rom_test.v │ ├── zedboard.pcf │ ├── zybo.pcf │ └── zybo_z7.pcf ├── counter │ ├── CMakeLists.txt │ ├── counter.v │ ├── counter_arty.v │ ├── counter_arty_2clk.v │ ├── counter_arty_bufg.v │ ├── counter_arty_overlay.v │ ├── counter_ax7050.v │ ├── counter_ax7050.xdc │ ├── counter_basys3.v │ ├── counter_marszx3.v │ ├── counter_microzed.v │ ├── counter_nexys.v │ ├── counter_nexys_video.v │ ├── counter_nexys_video.xdc │ ├── counter_pynqz1.v │ ├── counter_zedboard.v │ └── counter_zybo_z7.v ├── ddr │ ├── CMakeLists.txt │ ├── arty.pcf │ ├── arty.sdc │ ├── arty.xdc │ ├── arty_clocks.xdc │ ├── ddr_uart.v │ ├── ddr_uart_100t.v │ ├── mem.init │ ├── mem_1.init │ └── scripts │ │ ├── README.md │ │ ├── arty.py │ │ ├── csr.csv │ │ ├── sdram_init.py │ │ └── test_sdram.py ├── dram │ ├── CMakeLists.txt │ ├── dram_1_128x1d.v │ ├── dram_1_256x1s.v │ ├── dram_1_32m.v │ ├── dram_1_64m.v │ ├── dram_2_128x1s.v │ ├── dram_2_32x1d.v │ ├── dram_2_64x1d.v │ ├── dram_4_32x1s.v │ ├── dram_4_32x2s.v │ ├── dram_4_64x1s.v │ └── dram_8_32x1s.v ├── dram_shifter │ ├── CMakeLists.txt │ ├── dram_shifter_128x1d.v │ ├── dram_shifter_128x1s.v │ ├── dram_shifter_256x1s.v │ ├── dram_shifter_32m.v │ ├── dram_shifter_32x1d.v │ ├── dram_shifter_32x1s.v │ ├── dram_shifter_64m.v │ ├── dram_shifter_64x1d.v │ └── dram_shifter_64x1s.v ├── dram_test │ ├── CMakeLists.txt │ ├── dram_test_32m.v │ ├── dram_test_32x1d.v │ ├── dram_test_64m.v │ └── dram_test_64x1d.v ├── ff_sr_ce │ ├── CMakeLists.txt │ ├── create_sby.py │ ├── ff_ce_sr.v │ ├── ff_ce_sr_testbench.v │ ├── ff_type.v │ └── generate.py ├── gclk_active │ ├── CMakeLists.txt │ ├── README.md │ ├── basys3.pcf │ └── gclk_through.v ├── gtp_channel │ ├── CMakeLists.txt │ ├── basys3.xdc │ ├── gtp_channel.v │ └── nexys_video.xdc ├── gtp_common │ ├── CMakeLists.txt │ ├── basys3.xdc │ └── gtp_common.v ├── iddr_oddr │ ├── CMakeLists.txt │ ├── README.md │ ├── data_generator.v │ ├── iddr_basys3.v │ ├── iddr_basys3.xdc │ ├── iddr_wrapper.v │ ├── ioddr_hw_test_basys3.pcf │ ├── ioddr_hw_test_basys3.v │ ├── ioddr_tester.v │ ├── oddr_basys3.v │ ├── oddr_basys3.xdc │ ├── oddr_wrapper.v │ ├── tddr_basys3.pcf │ └── tddr_basys3.v ├── idelayctrl │ ├── CMakeLists.txt │ ├── README.md │ ├── arty.pcf │ └── idelayctrl.v ├── install_test │ ├── CMakeLists.txt │ ├── Makefile │ ├── arty-100t.xdc │ ├── basys3.xdc │ ├── counter.v │ ├── nexys_video.xdc │ └── requirements.txt ├── iobuf │ ├── CMakeLists.txt │ └── iobuf_basys3.v ├── iobuf_i2c │ ├── CMakeLists.txt │ ├── README.md │ ├── i2c_master.v │ ├── i2c_probe.v │ ├── i2c_scan.v │ ├── i2c_slave.v │ ├── iobuf_i2c_basys3.v │ └── simpleuart.v ├── iobuf_infer │ ├── CMakeLists.txt │ └── iobuf_infer_basys3.v ├── iologic_packing │ ├── CMakeLists.txt │ ├── README.md │ └── generate.py ├── iosettings │ ├── CMakeLists.txt │ ├── README.md │ └── generate.py ├── lcu │ ├── CMakeLists.txt │ ├── arty.pcf │ ├── lcu.v │ └── lcu_tb.v ├── mmcm │ ├── CMakeLists.txt │ ├── README.md │ ├── gen_random_cases.py │ ├── mmcm_buf_basys3_bottom.v │ ├── mmcm_dual.v │ ├── mmcm_ext_basys3_bottom.v │ ├── mmcm_int_basys3_bottom.v │ ├── mmcm_int_frac_basys3_bottom.v │ ├── mmcm_none_basys3_bottom.v │ ├── mmcm_packing.v │ ├── mmcm_random_case.tpl │ └── mmcme2_test.v ├── multixdc_counter │ ├── CMakeLists.txt │ ├── README.md │ ├── arty_0.xdc │ ├── arty_1.xdc │ └── arty_2.xdc ├── obuf_packing │ ├── CMakeLists.txt │ ├── README.md │ ├── dummy.pcf │ └── obuf_packing.v ├── obufds │ ├── CMakeLists.txt │ ├── basys3.pcf │ └── obufds_basys3.v ├── obuftds │ ├── CMakeLists.txt │ ├── basys3.pcf │ └── obuftds_basys3.v ├── oserdes_routing │ ├── CMakeLists.txt │ ├── dummy.pcf │ └── oserdes_routing.v ├── pcie │ ├── CMakeLists.txt │ ├── pcie_arty100t.v │ ├── pcie_basys3.v │ └── pcie_nexys_video.v ├── pcie_complex │ ├── CMakeLists.txt │ ├── README.md │ └── pcie_complex.v ├── pll │ ├── CMakeLists.txt │ ├── README.md │ ├── pll_buf_basys3_bottom.v │ ├── pll_ext_basys3_bottom.v │ ├── pll_int_basys3_bottom.v │ └── plle2_test.v ├── ps7 │ ├── CMakeLists.txt │ ├── axi_lite_reg │ │ ├── AxiPeriph.v │ │ ├── CMakeLists.txt │ │ ├── Readme.md │ │ ├── axi_reg.v │ │ ├── build.py │ │ └── zybo.xdc │ └── counter_emio │ │ ├── CMakeLists.txt │ │ ├── counter_emio.v │ │ └── zybo.xdc ├── serdes │ ├── CMakeLists.txt │ ├── basys3.pcf │ ├── generate_tests.py │ ├── serdes_basys3.v │ ├── serdes_basys3_idelay.v │ ├── serdes_test.v │ └── serdes_test_idelay.v ├── simple_ff │ ├── CMakeLists.txt │ ├── simple_ff.v │ ├── simple_ff_full.v │ └── simple_ff_full_loc.v ├── soc │ ├── CMakeLists.txt │ ├── ibex │ │ ├── CMakeLists.txt │ │ ├── generate.py │ │ ├── ibex.patch │ │ ├── led.vmem │ │ ├── pins_artya7.pcf │ │ ├── pins_artya7.sdc │ │ ├── pins_nexys_video.pcf │ │ └── pins_nexys_video.sdc │ └── litex │ │ ├── CMakeLists.txt │ │ ├── fixup_xdc.py │ │ ├── generate.py │ │ ├── generate_linux.py │ │ ├── linux │ │ ├── CMakeLists.txt │ │ ├── arty_clocks.xdc │ │ └── soc_linux.py │ │ ├── mini │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ └── arty_clocks.xdc │ │ ├── mini_ddr │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ └── arty_clocks.xdc │ │ └── mini_ddr_eth │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ └── arty_clocks.xdc ├── srl │ ├── CMakeLists.txt │ ├── common │ │ ├── CMakeLists.txt │ │ ├── rom.v │ │ ├── srl32_chain_seg.v │ │ ├── srl_chain_mixed.v │ │ ├── srl_init_tester.v │ │ ├── srl_shift_tester.v │ │ ├── srlc16e.v │ │ └── srlc32e.v │ ├── srl16_amc31 │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── basys3_dffmux_top.v │ │ ├── basys3_doutmux_top.v │ │ ├── srl16_dffmux_mc31_tb.v │ │ └── srl16_doutmux_mc31_tb.v │ ├── srl16_chain │ │ ├── CMakeLists.txt │ │ ├── basys3_top.v │ │ └── srl16_chain_tb.v │ ├── srl16_init │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── basys3_top.v │ │ └── srl16_init_tb.v │ ├── srl16_shift │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── basys3_top.v │ │ └── srl16_shift_tb.v │ ├── srl32_amc31 │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── basys3_dffmux_top.v │ │ ├── basys3_doutmux_top.v │ │ ├── srl32_dffmux_mc31_tb.v │ │ └── srl32_doutmux_mc31_tb.v │ ├── srl32_chain │ │ ├── CMakeLists.txt │ │ ├── basys3_top.v │ │ └── srl32_chain_tb.v │ ├── srl32_init │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── basys3_top.v │ │ └── srl32_init_tb.v │ └── srl32_shift │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── basys3_top.v │ │ └── srl32_shift_tb.v ├── switch_processing │ ├── CMakeLists.txt │ ├── switch_processing_add_1.v │ ├── switch_processing_arty_monolithic.v │ ├── switch_processing_arty_overlay.v │ ├── switch_processing_blink.v │ └── switch_processing_identity.v └── uart_loopback │ ├── CMakeLists.txt │ ├── uart_loopback.v │ └── uart_loopback_zedboard.v └── zynq7_tile_colormap.json /.git-blame-ignore-revs: -------------------------------------------------------------------------------- 1 | 6104aafffae1b4a1c1c0acab1e6e49b46bbf104c -------------------------------------------------------------------------------- /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | 3 | updates: 4 | 5 | - package-ecosystem: gitsubmodule 6 | directory: / 7 | schedule: 8 | interval: daily 9 | open-pull-requests-limit: 99 10 | labels: 11 | - dependencies 12 | - third-party 13 | 14 | - package-ecosystem: github-actions 15 | directory: / 16 | schedule: 17 | interval: weekly 18 | open-pull-requests-limit: 99 19 | -------------------------------------------------------------------------------- /.github/scripts/docs.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | export CMAKE_FLAGS="-GNinja" 4 | 5 | source $(dirname "$0")/setup-and-activate.sh 6 | 7 | pushd build 8 | 9 | make_target docs "Building documentation (make docs)" 10 | 11 | popd 12 | -------------------------------------------------------------------------------- /.github/scripts/ice40.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | export CMAKE_FLAGS="-GNinja" 4 | 5 | source $(dirname "$0")/setup-and-activate.sh 6 | 7 | pushd build 8 | 9 | make_target all_ice40 "Running ice40 tests (make all_ice40)" 10 | ninja print_qor > ice40_qor.csv 11 | 12 | popd 13 | -------------------------------------------------------------------------------- /.github/scripts/setup-and-activate.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | source $(dirname "$0")/setup.sh 4 | 5 | set -e 6 | source $(dirname "$0")/common.sh 7 | 8 | source env/conda/bin/activate f4pga_arch_def_base 9 | -------------------------------------------------------------------------------- /.github/scripts/testarch.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | export CMAKE_FLAGS="-GNinja" 4 | 5 | source $(dirname "$0")/setup-and-activate.sh 6 | 7 | pushd build 8 | 9 | make_target all_testarch "Running testarch tests (make all_testarch)" 10 | 11 | popd 12 | -------------------------------------------------------------------------------- /.github/scripts/xc7a200t-vendor.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | source $(dirname "$0")/xc7-vendor.sh a200t 4 | -------------------------------------------------------------------------------- /.github/scripts/xc7a200t.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | source $(dirname "$0")/xc7.sh a200t 4 | -------------------------------------------------------------------------------- /.github/workflows/update_conda_lock.yml: -------------------------------------------------------------------------------- 1 | name: update_conda_lock 2 | 3 | on: 4 | push: 5 | pull_request: 6 | schedule: 7 | - cron: '0 3 * * *' 8 | workflow_dispatch: 9 | 10 | jobs: 11 | 12 | update-locks: 13 | uses: f4pga/actions/.github/workflows/update_conda_lock.yml@main 14 | secrets: 15 | SSH_DEPLOY_KEY: ${{ secrets.SSH_DEPLOY_KEY }} 16 | GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} 17 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | env/ 2 | 3 | # Python files 4 | __pycache__/ 5 | *.py[cod] 6 | 7 | # pytest files 8 | .cache 9 | .pytest_cache 10 | 11 | # CMake output 12 | build 13 | *.orig 14 | build-* 15 | 16 | model.xml 17 | pb_type.xml 18 | *.sort.xml 19 | *~ 20 | 21 | /docs/_build/ 22 | /docs/_theme/ 23 | -------------------------------------------------------------------------------- /.style.yapf: -------------------------------------------------------------------------------- 1 | [style] 2 | based_on_style = pep8 3 | split_before_expression_after_opening_paren = True 4 | split_before_first_argument = True 5 | split_complex_comprehension = True 6 | split_penalty_comprehension = 2100 7 | dedent_closing_brackets=True 8 | indent_dictionary_value=True 9 | -------------------------------------------------------------------------------- /common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(yosys) 2 | -------------------------------------------------------------------------------- /common/empty.svg: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /common/wire.eblif: -------------------------------------------------------------------------------- 1 | .model top 2 | .inputs di 3 | .outputs do 4 | .names di do 5 | 1 1 6 | .end 7 | -------------------------------------------------------------------------------- /common/xml/README.md: -------------------------------------------------------------------------------- 1 | # XML Schemas 2 | 3 | This directory contains a number of XML schemas for the different file formats used by VPR. 4 | 5 | - fpga_architecture.xsd contains the schema for the FPGA Architecture Definition XML. 6 | - packed_netlist.xsd contains the packed netlist format. 7 | - routing_resource.xsd contains information about the routing resources within the FPGA. -------------------------------------------------------------------------------- /common/yosys/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE miter_and_tempinduct.ys) 2 | add_file_target(FILE miter_and_tempinduct_skip_1.ys) 3 | add_file_target(FILE equiv_simple_clk2fflogic.ys) 4 | add_file_target(FILE equiv_simple_opt_full.ys) 5 | add_file_target(FILE miter_and_tempinduct_large_N.ys) 6 | -------------------------------------------------------------------------------- /common/yosys/miter_and_tempinduct.ys: -------------------------------------------------------------------------------- 1 | # Equivalance check script that creates a miter circuit and proves used 2 | # temporaly induction that the miter circuit never asserts. 3 | hierarchy 4 | proc 5 | clk2fflogic 6 | miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter 7 | sat -prove trigger 0 -verify -tempinduct miter 8 | -------------------------------------------------------------------------------- /docs/_static/favicon.svg: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /docs/_static/images/prjxray/arch-defs-flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/docs/_static/images/prjxray/arch-defs-flow.png -------------------------------------------------------------------------------- /docs/_static/images/prjxray/import-flow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/docs/_static/images/prjxray/import-flow.png -------------------------------------------------------------------------------- /docs/_static/images/prjxray/vtr-rrgraph.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/docs/_static/images/prjxray/vtr-rrgraph.png -------------------------------------------------------------------------------- /docs/bitdoc/prjxray/index.rst: -------------------------------------------------------------------------------- 1 | ============= 2 | Project X-Ray 3 | ============= 4 | 5 | This section contains the information about the methods and tools used for managing :doc:`prjxray:index` data inside the 6 | Architecture Definitions Project. 7 | 8 | .. toctree:: 9 | :maxdepth: 2 10 | 11 | flow-diagram 12 | vtr-rrgraph 13 | partial-reconfig 14 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | myst-parser 2 | sphinx 3 | http://github.com/f4pga/sphinx_f4pga_theme/archive/f4pga.zip#sphinx-f4pga-theme 4 | sphinxcontrib-images 5 | -------------------------------------------------------------------------------- /lattice/ecp5/.gitignore: -------------------------------------------------------------------------------- 1 | Makefile 2 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/io/BB/BB.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module BB(input I, T, output O, inout B); 3 | assign B = T ? 1'bz : I; 4 | assign O = B; 5 | endmodule 6 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/io/IB/IB.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module IB(input I, output O); 3 | assign O = I; 4 | endmodule 5 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/io/OB/OB.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module OB(input I, output O); 3 | assign O = I; 4 | endmodule 5 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/io/OBZ/OBZ.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module OBZ(input I, T, output O); 3 | assign O = T ? 1'bz : I; 4 | endmodule 5 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/misc/INV/INV.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module INV(input A, output Z); 3 | assign Z = !A; 4 | endmodule 5 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/slice/L6MUX21/L6MUX21.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module L6MUX21 (input D0, D1, SD, output Z); 3 | assign Z = SD ? D1 : D0; 4 | endmodule 5 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/slice/LUT2/LUT2.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module LUT2(input A, B, output Z); 3 | parameter [3:0] INIT = 4'h0; 4 | wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; 5 | assign Z = A ? s1[1] : s1[0]; 6 | endmodule 7 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/slice/LUT4/LUT4.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module LUT4(input A, B, C, D, output Z); 3 | parameter [15:0] INIT = 16'h0000; 4 | wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; 5 | wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0]; 6 | wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0]; 7 | assign Z = A ? s1[1] : s1[0]; 8 | endmodule 9 | -------------------------------------------------------------------------------- /lattice/ecp5/primitives/slice/PFUMX/PFUMX.sim.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module PFUMX (input ALUT, BLUT, C0, output Z); 3 | assign Z = C0 ? ALUT : BLUT; 4 | endmodule 5 | -------------------------------------------------------------------------------- /lattice/ice40/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include(icestorm.cmake) 2 | 3 | icestorm_setup() 4 | 5 | add_subdirectory(primitives) 6 | add_subdirectory(cells) 7 | add_subdirectory(devices) 8 | include(boards.cmake) 9 | 10 | add_subdirectory(tests) 11 | -------------------------------------------------------------------------------- /lattice/ice40/cells/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(lutff) 2 | add_subdirectory(plb) 3 | -------------------------------------------------------------------------------- /lattice/ice40/cells/lutff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE lutff.pb_type.xml SCANNER_TYPE xml) 2 | -------------------------------------------------------------------------------- /lattice/ice40/cells/plb/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE plb.pb_type.xml SCANNER_TYPE xml) 2 | -------------------------------------------------------------------------------- /lattice/ice40/devices/layouts/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(N1k) 2 | add_subdirectory(N384) 3 | add_subdirectory(N4k) 4 | add_subdirectory(N8k) 5 | add_subdirectory(icebox) 6 | -------------------------------------------------------------------------------- /lattice/ice40/devices/layouts/N1k/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ntemplate.N1k.fixed_layout.xml) 2 | n_template( 3 | NAME N1k.fixed_layout.xml 4 | PREFIXES lp;hx 5 | SRCS ntemplate.N1k.fixed_layout.xml 6 | ) 7 | -------------------------------------------------------------------------------- /lattice/ice40/devices/layouts/N384/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ntemplate.N384.fixed_layout.xml) 2 | n_template( 3 | NAME N384.fixed_layout.xml 4 | PREFIXES lp;hx 5 | SRCS ntemplate.N384.fixed_layout.xml 6 | ) 7 | -------------------------------------------------------------------------------- /lattice/ice40/devices/layouts/N4k/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ntemplate.N4k.fixed_layout.xml) 2 | n_template( 3 | NAME N4k.fixed_layout.xml 4 | PREFIXES lp;hx 5 | SRCS ntemplate.N4k.fixed_layout.xml 6 | ) 7 | -------------------------------------------------------------------------------- /lattice/ice40/devices/layouts/N4k/ntemplate.N4k.fixed_layout.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /lattice/ice40/devices/layouts/N8k/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ntemplate.N8k.fixed_layout.xml) 2 | n_template( 3 | NAME N8k.fixed_layout.xml 4 | PREFIXES lp;hx 5 | SRCS ntemplate.N8k.fixed_layout.xml 6 | ) 7 | -------------------------------------------------------------------------------- /lattice/ice40/devices/top-routing-virt/tiles/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(dsp) 2 | add_subdirectory(pio) 3 | add_subdirectory(plb) 4 | add_subdirectory(ram) 5 | -------------------------------------------------------------------------------- /lattice/ice40/devices/top-routing-virt/tiles/dsp/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE dsp.pb_type.xml SCANNER_TYPE xml) 2 | -------------------------------------------------------------------------------- /lattice/ice40/devices/top-routing-virt/tiles/pio/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE pio.pb_type.xml SCANNER_TYPE xml) 2 | -------------------------------------------------------------------------------- /lattice/ice40/devices/top-routing-virt/tiles/plb/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE plb.pb_type.xml SCANNER_TYPE xml) 2 | -------------------------------------------------------------------------------- /lattice/ice40/devices/top-routing-virt/tiles/ram/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ram.pb_type.xml SCANNER_TYPE xml) 2 | -------------------------------------------------------------------------------- /lattice/ice40/docs/neighbourhood-in.xcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/lattice/ice40/docs/neighbourhood-in.xcf -------------------------------------------------------------------------------- /lattice/ice40/docs/neighbourhood-out.xcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/lattice/ice40/docs/neighbourhood-out.xcf -------------------------------------------------------------------------------- /lattice/ice40/primitives/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(mux2) 2 | add_subdirectory(mux4) 3 | add_subdirectory(sb_lut) 4 | add_subdirectory(sb_ff) 5 | add_subdirectory(sb_carry) 6 | add_subdirectory(sb_ram) 7 | -------------------------------------------------------------------------------- /lattice/ice40/primitives/mux2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME ice_mux2 3 | INPUTS LT,FF 4 | MUX_NAME ICE_MUX2 5 | SPLIT_INPUTS 1 6 | TYPE logic 7 | WIDTH 2 8 | ) 9 | -------------------------------------------------------------------------------- /lattice/ice40/primitives/mux4/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen(NAME ice_mux4 MUX_NAME ICE_MUX4 TYPE logic WIDTH 4) 2 | -------------------------------------------------------------------------------- /lattice/ice40/primitives/sb_carry/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE sb_carry.model.xml SCANNER_TYPE xml) 2 | 3 | add_file_target(FILE sb_carry.pb_type.xml SCANNER_TYPE xml) 4 | -------------------------------------------------------------------------------- /lattice/ice40/primitives/sb_carry/sb_carry.sim.v: -------------------------------------------------------------------------------- 1 | module SB_CARRY (CO, I0, I1, CI); 2 | output wire CO; 3 | input wire I0; 4 | input wire I1; 5 | input wire CI; 6 | 7 | assign CO = (I0 && I1) || ((I0 || I1) && CI); 8 | endmodule 9 | -------------------------------------------------------------------------------- /lattice/ice40/primitives/sb_ff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE sb_ff.model.xml SCANNER_TYPE xml) 2 | 3 | add_file_target(FILE sb_ff.pb_type.xml SCANNER_TYPE xml) 4 | -------------------------------------------------------------------------------- /lattice/ice40/primitives/sb_lut/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE sb_lut.model.xml SCANNER_TYPE xml) 2 | 3 | add_file_target(FILE sb_lut.pb_type.xml SCANNER_TYPE xml) 4 | -------------------------------------------------------------------------------- /lattice/ice40/primitives/sb_ram/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE sb_ram.model.xml SCANNER_TYPE xml) 2 | 3 | add_file_target(FILE sb_ram.pb_type.xml SCANNER_TYPE xml) 4 | -------------------------------------------------------------------------------- /lattice/ice40/tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(blink) 2 | add_subdirectory(checker) 3 | add_subdirectory(iceram) 4 | -------------------------------------------------------------------------------- /lattice/ice40/tests/blink/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(BOARDS iceblink40-lp1k icestick) 2 | 3 | if (NOT LIGHT_BUILD) 4 | list(APPEND BOARDS hx8k-b-evn icevision tinyfpga-b2 tinyfpga-bx) 5 | endif (NOT LIGHT_BUILD) 6 | 7 | add_fpga_target_boards( 8 | NAME blink 9 | BOARDS ${BOARDS} 10 | SOURCES 11 | example.v 12 | TESTBENCH_SOURCES 13 | example_tb.v 14 | IMPLICIT_INPUT_IO_FILES 15 | ) 16 | -------------------------------------------------------------------------------- /lattice/ice40/tests/blink/hx8k-b-evn.pcf: -------------------------------------------------------------------------------- 1 | #set_io LED0 B5 2 | #set_io LED1 B4 3 | set_io LED2 A2 4 | set_io LED3 A1 5 | set_io LED4 C5 6 | set_io LED5 C4 7 | #set_io LED6 B3 8 | #set_io LED7 C3 9 | set_io clk J3 10 | -------------------------------------------------------------------------------- /lattice/ice40/tests/blink/iceblink40-lp1k.pcf: -------------------------------------------------------------------------------- 1 | set_io LED5 A29 # Actually LD1 2 | set_io LED2 B20 3 | set_io LED3 B19 4 | set_io LED4 A25 5 | set_io clk A9 6 | -------------------------------------------------------------------------------- /lattice/ice40/tests/blink/icestick.pcf: -------------------------------------------------------------------------------- 1 | # full iCEstick pinout: 2 | # http://www.pighixxx.com/test/portfolio-items/icestick/ 3 | 4 | #set_io --warn-no-port RX 9 5 | #set_io --warn-no-port TX 8 6 | #set_io LED1 99 7 | set_io LED2 98 8 | set_io LED3 97 9 | set_io LED4 96 10 | set_io LED5 95 11 | set_io clk 21 12 | -------------------------------------------------------------------------------- /lattice/ice40/tests/blink/icevision.pcf: -------------------------------------------------------------------------------- 1 | set_io LED5 39 # RGB0 / LC1 / LDEX1 / LDB1 2 | set_io LED4 40 # RGB1 / LC2 / LDEX2 / LDB2 3 | set_io LED3 41 # RGB2 / LC3 / LDEX3 / LDB3 4 | set_io LED2 6 # IOB_13B / 6 / GPIO 2 5 | set_io clk 44 # period 41.66 6 | -------------------------------------------------------------------------------- /lattice/ice40/tests/blink/tinyfpga-b2.pcf: -------------------------------------------------------------------------------- 1 | set_io LED5 J1 # pin13 2 | set_io LED4 H1 # pin12 3 | set_io LED3 G1 # pin11 4 | set_io LED2 E1 # pin10 5 | set_io clk B4 6 | # clock signal 7 | # set_io clk B4 8 | # set_io clk B5 9 | # set_io clk C4 10 | # set_io clk C5 11 | -------------------------------------------------------------------------------- /lattice/ice40/tests/blink/tinyfpga-bx.pcf: -------------------------------------------------------------------------------- 1 | set_io --warn-no-port LED3 J9 2 | set_io --warn-no-port LED4 E8 3 | set_io --warn-no-port LED5 J2 4 | 5 | # LED 6 | set_io --warn-no-port LED2 B3 7 | 8 | # 16MHz clock 9 | set_io --warn-no-port clk B2 # input 10 | 11 | -------------------------------------------------------------------------------- /lattice/ice40/tests/checker/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_fpga_target_boards( 2 | NAME checker 3 | BOARDS icestick 4 | SOURCES 5 | checker.v 6 | TESTBENCH_SOURCES 7 | checker_tb.v 8 | IMPLICIT_INPUT_IO_FILES 9 | ) 10 | -------------------------------------------------------------------------------- /lattice/ice40/tests/checker/icestick.pcf: -------------------------------------------------------------------------------- 1 | # full iCEstick pinout: 2 | # http://www.pighixxx.com/test/portfolio-items/icestick/ 3 | 4 | #set_io --warn-no-port RX 9 5 | #set_io --warn-no-port TX 8 6 | set_io LED1 99 7 | set_io LED2 98 8 | set_io LED3 97 9 | set_io LED4 96 10 | set_io LED5 95 11 | set_io clk 21 12 | -------------------------------------------------------------------------------- /lattice/ice40/tests/ffpack/example.pcf: -------------------------------------------------------------------------------- 1 | set_io cen 59 2 | set_io rst 56 3 | set_io ina 53 4 | set_io inb 51 5 | set_io clk 13 6 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceff/ff.pcf: -------------------------------------------------------------------------------- 1 | set_io di 59 2 | set_io do 56 3 | set_io clk 13 4 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceff/ff.v: -------------------------------------------------------------------------------- 1 | // Single flip-flip test. 2 | module top(input clk, input di, output do); 3 | always @( posedge clk ) 4 | do <= di; 5 | endmodule // top 6 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceinv/example.pcf: -------------------------------------------------------------------------------- 1 | set_io btn 59 2 | set_io LED3 56 3 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceinv/example.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input btn, 3 | output LED3, 4 | ); 5 | assign LED3 = btn; 6 | endmodule 7 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/and4/lut.pcf: -------------------------------------------------------------------------------- 1 | ../lut.pcf -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/and4/lut.v: -------------------------------------------------------------------------------- 1 | // 4-input, and LUT test. 2 | module top( (* keep *) input [3:0] I, output O); 3 | always @(I) 4 | case(I) 5 | 4'b1111 : O = 1; 6 | default : O = 0; 7 | endcase 8 | endmodule // top 9 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/lut.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] 59 2 | set_io I[1] 56 3 | set_io I[2] 53 4 | set_io I[3] 51 5 | set_io O 13 6 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/lut.v: -------------------------------------------------------------------------------- 1 | // 4-input LUT test. 2 | module top(input [3:0] I, output O); 3 | always @(I) 4 | case(I) 5 | 4'b1000 : O = 1; 6 | 4'b1001 : O = 1; 7 | 4'b1010 : O = 1; 8 | 4'b1100 : O = 1; 9 | 4'b1110 : O = 1; 10 | 4'b1111 : O = 1; 11 | default : O = 0; 12 | endcase 13 | endmodule // top 14 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/or4/lut.pcf: -------------------------------------------------------------------------------- 1 | ../lut.pcf -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/or4/lut.v: -------------------------------------------------------------------------------- 1 | // 4-input, or LUT test. 2 | module top( (* keep *) input [3:0] I, output O); 3 | always @(I) 4 | case(I) 5 | 4'b0000 : O = 0; 6 | default : O = 1; 7 | endcase 8 | endmodule // top 9 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/route-through-in0/lut.pcf: -------------------------------------------------------------------------------- 1 | ../lut.pcf -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/route-through-in0/lut.v: -------------------------------------------------------------------------------- 1 | // 4-input, route-through LUT test. 2 | module top( (* keep *) input [3:0] I, output O); 3 | always @(I) 4 | 5 | case(I) 6 | 4'b???1 : O = 1; 7 | 4'b???0 : O = 0; 8 | endcase 9 | endmodule // top 10 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/route-through-in1/lut.pcf: -------------------------------------------------------------------------------- 1 | ../lut.pcf -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/route-through-in1/lut.v: -------------------------------------------------------------------------------- 1 | // 4-input, route-through LUT test. 2 | module top( (* keep *) input [3:0] I, output O); 3 | //Cell instances 4 | SB_LUT4 #( 5 | .LUT_INIT(16'b0100000000000000) 6 | ) LUT ( 7 | .I0(1'b0), 8 | .I1(I[1]), 9 | .I2(1'b0), 10 | .I3(1'b0), 11 | .O(O) 12 | ); 13 | endmodule // top 14 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/route-through-in2/lut.pcf: -------------------------------------------------------------------------------- 1 | ../lut.pcf -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/route-through-in2/lut.v: -------------------------------------------------------------------------------- 1 | // 4-input, route-through LUT test. 2 | module top( (* keep *) input [3:0] I, output O); 3 | always @(I) 4 | case(I) 5 | 4'b?1?? : O = 1; 6 | 4'b?0?? : O = 0; 7 | endcase 8 | endmodule // top 9 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/route-through-in3/lut.pcf: -------------------------------------------------------------------------------- 1 | ../lut.pcf -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/route-through-in3/lut.v: -------------------------------------------------------------------------------- 1 | // 4-input, route-through LUT test. 2 | module top( (* keep *) input [3:0] I, output O); 3 | always @(I) 4 | case(I) 5 | 4'b1??? : O = 1; 6 | 4'b0??? : O = 0; 7 | endcase 8 | endmodule // top 9 | -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/xor4/lut.pcf: -------------------------------------------------------------------------------- 1 | ../lut.pcf -------------------------------------------------------------------------------- /lattice/ice40/tests/icelut/xor4/lut.v: -------------------------------------------------------------------------------- 1 | // 4-input, xor LUT test. 2 | module top( (* keep *) input [3:0] I, output O); 3 | always @(I) 4 | case(I) 5 | 4'b1000 : O = 1; 6 | 4'b0100 : O = 1; 7 | 4'b0010 : O = 1; 8 | 4'b0001 : O = 1; 9 | default : O = 0; 10 | endcase 11 | endmodule // top 12 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceram/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(BOARDS iceblink40-lp1k icestick) 2 | 3 | if (NOT LIGHT_BUILD) 4 | list(APPEND BOARDS hx8k-b-evn tinyfpga-bx) 5 | endif (NOT LIGHT_BUILD) 6 | 7 | add_fpga_target_boards( 8 | NAME iceram 9 | BOARDS ${BOARDS} 10 | SOURCES 11 | iceram.v 12 | TESTBENCH_SOURCES 13 | iceram_tb.v 14 | IMPLICIT_INPUT_IO_FILES 15 | ) 16 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceram/hx8k-b-evn.pcf: -------------------------------------------------------------------------------- 1 | #set_io LED0 B5 2 | set_io LED1 B4 3 | set_io LED2 A2 4 | set_io LED3 A1 5 | set_io LED4 C5 6 | set_io LED5 C4 7 | #set_io LED6 B3 8 | #set_io LED7 C3 9 | set_io clk J3 10 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceram/iceblink40-lp1k.pcf: -------------------------------------------------------------------------------- 1 | set_io LED1 A29 2 | set_io LED2 B20 3 | set_io LED3 B19 4 | set_io LED4 A25 5 | set_io LED5 A32 # PMOD J5 - P0 6 | set_io clk A9 # 3.33 MHz (or 333 kHz or 33.3MHz -- see JP2) 7 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceram/icestick.pcf: -------------------------------------------------------------------------------- 1 | # full iCEstick pinout: 2 | # http://www.pighixxx.com/test/portfolio-items/icestick/ 3 | 4 | #set_io --warn-no-port RX 9 5 | #set_io --warn-no-port TX 8 6 | set_io LED1 99 7 | set_io LED2 98 8 | set_io LED3 97 9 | set_io LED4 96 10 | set_io LED5 95 11 | set_io clk 21 12 | -------------------------------------------------------------------------------- /lattice/ice40/tests/iceram/tinyfpga-bx.pcf: -------------------------------------------------------------------------------- 1 | set_io --warn-no-port LED2 G1 2 | set_io --warn-no-port LED3 J9 3 | set_io --warn-no-port LED4 E8 4 | set_io --warn-no-port LED5 J2 5 | 6 | # LED 7 | set_io --warn-no-port LED1 B3 8 | 9 | # 16MHz clock 10 | set_io --warn-no-port clk B2 # input 11 | 12 | -------------------------------------------------------------------------------- /lattice/ice40/utils/fasm_icebox/asc2fasm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import sys 3 | from fasm_icebox_utils import asc_to_fasm 4 | 5 | 6 | def main(args): 7 | # parse args 8 | with open(args[1], "w") as f: 9 | asc_to_fasm(args[0], f) 10 | 11 | 12 | if __name__ == "__main__": 13 | main(sys.argv[1:]) 14 | -------------------------------------------------------------------------------- /library/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(uart) 2 | 3 | add_file_target(FILE lfsr.v SCANNER_TYPE verilog) 4 | add_file_target(FILE tbassert.v SCANNER_TYPE verilog) 5 | -------------------------------------------------------------------------------- /library/uart/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | foreach(file baudgen.v uart_rx.v uart_tx.v uart.v) 2 | add_file_target(FILE ${file} SCANNER_TYPE verilog) 3 | list(APPEND SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/${file}) 4 | endforeach() 5 | 6 | add_custom_target(uart_library) 7 | set_target_properties(uart_library PROPERTIES SOURCES "${SOURCES}") 8 | -------------------------------------------------------------------------------- /pylintrc: -------------------------------------------------------------------------------- 1 | [MESSAGES CONTROL] 2 | enable=bad-indentation,eval-used,invalid-name,missing-docstring,old-style-class,protected-access,unused-import 3 | 4 | [REPORTS] 5 | output-format=colorized 6 | reports=no 7 | -------------------------------------------------------------------------------- /quicklogic/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(common) 2 | 3 | add_quicklogic_plugins() 4 | 5 | set(QLF_FPGA_DATABASE_DIR quicklogic/third_party/qlfpga-symbiflow-plugins) 6 | set(QLF_FPGA_PLUGINS_DIR quicklogic/third_party/qlfpga-symbiflow-plugins) 7 | 8 | add_subdirectory(qlf_k4n8) 9 | add_subdirectory(pp3) 10 | -------------------------------------------------------------------------------- /quicklogic/common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(cmake) 2 | add_subdirectory(utils) 3 | 4 | -------------------------------------------------------------------------------- /quicklogic/common/cmake/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include(quicklogic_board.cmake) 2 | include(quicklogic_device.cmake) 3 | include(quicklogic_install.cmake) 4 | include(quicklogic_qlf_arch.cmake) 5 | include(quicklogic_qlf_device.cmake) 6 | include(quicklogic_toolchain_test.cmake) 7 | include(quicklogic_jlink.cmake) 8 | include(quicklogic_openocd.cmake) 9 | include(quicklogic_env.cmake) 10 | -------------------------------------------------------------------------------- /quicklogic/common/utils/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | get_target_property_required(PYTHON3 env PYTHON3) 2 | -------------------------------------------------------------------------------- /quicklogic/docs/images/image1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/quicklogic/docs/images/image1.png -------------------------------------------------------------------------------- /quicklogic/docs/images/image2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/quicklogic/docs/images/image2.png -------------------------------------------------------------------------------- /quicklogic/passthrough.eblif: -------------------------------------------------------------------------------- 1 | .model top 2 | .inputs I 3 | .outputs O 4 | .subckt BIDIR_CELL I_DAT=x I_PAD_$inp=I 5 | .cname ibuf 6 | .subckt BIDIR_CELL O_DAT=x O_PAD_$out=O 7 | .cname obuf 8 | .end 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(vpr_pad) 2 | add_subdirectory(assp) 3 | add_subdirectory(bidir) 4 | add_subdirectory(clock) 5 | add_subdirectory(fpga_interconnect) 6 | add_subdirectory(gmux) 7 | add_subdirectory(gnd) 8 | add_subdirectory(logic) 9 | add_subdirectory(mult) 10 | add_subdirectory(sdiomux) 11 | add_subdirectory(vcc) 12 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/assp/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE assp.sim.v SCANNER_TYPE verilog) 2 | 3 | add_file_target(FILE assp.pb_type.xml SCANNER_TYPE xml) 4 | add_file_target(FILE assp.model.xml SCANNER_TYPE xml) 5 | 6 | add_to_cells_sim(assp.sim.v) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/bidir/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE bidir_cell.sim.v SCANNER_TYPE verilog) 2 | 3 | add_file_target(FILE bidir_cell.pb_type.xml SCANNER_TYPE xml) 4 | add_file_target(FILE bidir_cell.model.xml SCANNER_TYPE xml) 5 | add_file_target(FILE bidir.pb_type.xml SCANNER_TYPE xml) 6 | add_file_target(FILE bidir.model.xml SCANNER_TYPE xml) 7 | 8 | add_to_cells_sim(bidir_cell.sim.v) 9 | 10 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/bidir/bidir.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/clock/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE clock_cell.sim.v SCANNER_TYPE verilog) 2 | 3 | add_file_target(FILE clock_cell.pb_type.xml SCANNER_TYPE xml) 4 | add_file_target(FILE clock_cell.model.xml SCANNER_TYPE xml) 5 | add_file_target(FILE clock.pb_type.xml SCANNER_TYPE xml) 6 | add_file_target(FILE clock.model.xml SCANNER_TYPE xml) 7 | 8 | add_to_cells_sim(clock_cell.sim.v) 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/clock/clock.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/clock/clock_cell.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/fpga_interconnect/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE fpga_interconnect.sim.v SCANNER_TYPE verilog) 2 | 3 | add_to_cells_sim(fpga_interconnect.sim.v) 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/gmux/gmux.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/gmux/gmux_ic.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/gnd/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE gnd.sim.v SCANNER_TYPE verilog) 2 | 3 | add_file_target(FILE gnd.pb_type.xml SCANNER_TYPE xml) 4 | add_file_target(FILE gnd.model.xml SCANNER_TYPE xml) 5 | 6 | add_to_cells_sim(gnd.sim.v) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/gnd/gnd.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/gnd/gnd.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | .subckt GND 4 | 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/gnd/gnd.sim.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps/1ps 2 | (* whitebox *) 3 | module GND ( 4 | output wire GND 5 | ); 6 | 7 | assign GND = 1'b0; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/logic/c_frag_modes.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/logic/q_frag_modes.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/mult/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE mult.sim.v SCANNER_TYPE verilog) 2 | 3 | add_file_target(FILE mult.pb_type.xml SCANNER_TYPE xml) 4 | add_file_target(FILE mult.model.xml SCANNER_TYPE xml) 5 | 6 | add_to_cells_sim(mult.sim.v) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/sdiomux/sdiomux.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vcc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE vcc.sim.v SCANNER_TYPE verilog) 2 | 3 | add_file_target(FILE vcc.pb_type.xml SCANNER_TYPE xml) 4 | add_file_target(FILE vcc.model.xml SCANNER_TYPE xml) 5 | 6 | add_to_cells_sim(vcc.sim.v) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vcc/vcc.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vcc/vcc.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | .subckt VCC 4 | 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vcc/vcc.sim.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps/1ps 2 | (* whitebox *) 3 | module VCC ( 4 | output wire VCC 5 | ); 6 | 7 | assign VCC = 1'b1; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vpr_pad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE vpr_ipad.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE vpr_opad.pb_type.xml SCANNER_TYPE xml) 3 | add_file_target(FILE vpr_ipad.model.xml SCANNER_TYPE xml) 4 | add_file_target(FILE vpr_opad.model.xml SCANNER_TYPE xml) 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vpr_pad/vpr_ipad.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vpr_pad/vpr_ipad.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | .input 4 | 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vpr_pad/vpr_opad.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/primitives/vpr_pad/vpr_opad.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | .output 4 | 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/bram/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/bram/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_counter/btn_counter.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | output wire [3:0] led 4 | ); 5 | 6 | reg [3:0] cnt; 7 | initial cnt <= 0; 8 | 9 | always @(posedge clk) 10 | cnt <= cnt + 1; 11 | 12 | assign led = cnt; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_counter/chandalar-top.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | set_io led[0] B4 3 | set_io led[1] B3 4 | set_io led[2] C4 5 | set_io led[3] A4 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_counter/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | set_io led[0] H7 3 | set_io led[1] G7 4 | set_io led[2] F6 5 | set_io led[3] E8 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_counter/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io clk A3 2 | set_io led[0] A1 3 | set_io led[1] A2 4 | set_io led[2] B1 5 | set_io led[3] B3 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_counter/pd64.pcf: -------------------------------------------------------------------------------- 1 | set_io clk A4 2 | set_io led[0] A2 3 | set_io led[1] A3 4 | set_io led[2] A6 5 | set_io led[3] A7 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_counter/quickfeather.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 62 2 | set_io led[0] 34 3 | set_io led[1] 39 4 | set_io led[2] 38 5 | set_io led[3] 25 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_ff/README.md: -------------------------------------------------------------------------------- 1 | # A single flip-flop with button-triggered clock and data. 2 | 3 | This test instantiates a single flip-flop and exposes its clock input to `FBIO_0` and data input to `FBIO_1`. The output is connected to a LED on the `FBIO_21` pad. 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_ff/btn_ff.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | input wire d, 4 | output reg q 5 | ); 6 | 7 | always @(posedge clk) 8 | q <= d; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_ff/chandalar-top.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | set_io d C1 3 | set_io q B4 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_ff/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | set_io d C1 3 | set_io q H7 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_ff/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io clk A1 2 | set_io d A2 3 | set_io q A3 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_xor/README.md: -------------------------------------------------------------------------------- 1 | # A combinational XOR function of two inputs. 2 | 3 | This test implements a XOR function which inputs are connected to `FBIO_0` and `FBIO_1`. The output is connected to a LED on the `FBIO_21` pad. 4 | 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_xor/btn_xor.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [1:0] I, 3 | output wire O 4 | ); 5 | 6 | assign O = I[0] ^ I[1]; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_xor/chandalar-top.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io O B4 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_xor/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io O H7 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/btn_xor/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] D4 2 | set_io I[1] D5 3 | set_io O A2 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/consts/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io O B2 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/consts/consts.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [1:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT4 #(.INIT(0)) a_lut_with_consts ( 7 | .I0(I[0]), 8 | .I1(I[1]), 9 | .I2(1'b0), 10 | .I3(1'b1), 11 | .O(O) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/consts/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] A3 2 | set_io I[1] A2 3 | set_io O B3 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/counter/README.md: -------------------------------------------------------------------------------- 1 | # A 24-bit counter with LED output 2 | 3 | This design implements a 24-bit counter driven by the `Clk16` clock signal from the SoC. The design instantiates the `qlal4s3b_cell_macro` cell access SoC signal(s). 4 | 5 | The value of 4 MSBs of the counter is exposed to `FBIO_21`, `FBIO_22`, `FBIO_26` and `FBIO_18` which correspond to LEDs 2, 4, 5 and 6 on the Chandalar board. -------------------------------------------------------------------------------- /quicklogic/pp3/tests/counter/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io led[0] IO_21 2 | set_io led[1] G7 3 | set_io led[2] F6 4 | set_io led[3] E8 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/counter/iomux.json: -------------------------------------------------------------------------------- 1 | { 2 | "pads": { 3 | "3": { 4 | "func_sel": 0, 5 | "ctrl_sel": "fabric", 6 | "mode": "none", 7 | "pull": "none", 8 | "drive": 2, 9 | "slew": "slow", 10 | "schmitt": 0 11 | } 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/counter/quickfeather.pcf: -------------------------------------------------------------------------------- 1 | set_io led[0] 34 2 | set_io led[1] 39 3 | set_io led[2] 38 4 | set_io led[3] IO_3 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/Simon_bit_serial_top_module/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io cipher_out H7 2 | set_io clk G7 # Clock 3 | set_io data_in A4 4 | set_io data_rdy[0] G1 5 | set_io data_rdy[1] B4 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/cf_fft_256_8/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clock_c A5 2 | set_io data_0_i B3 3 | set_io data_0_o B5 4 | set_io data_1_i B4 5 | set_io data_1_o E2 6 | set_io enable_i G1 7 | set_io reset_i H4 8 | set_io sync_i F6 9 | set_io sync_o G7 10 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/clock_test/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk_out1 B2 2 | set_io clk_out2 B3 3 | set_io clk_out3 A4 4 | set_io clk_out4 B5 5 | set_io clk_out5 E8 6 | set_io tff_out H7 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/counter_8bit/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | set_io async_set A1 3 | set_io comb_out C3 4 | set_io enable B3 5 | set_io count[0] A2 6 | set_io count[1] B2 7 | set_io count[2] A3 8 | set_io count[3] C4 9 | set_io count[4] B4 10 | set_io count[5] A4 11 | set_io count[6] C5 12 | set_io count[7] B5 13 | 14 | 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/design10/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io CSn_o B3 2 | set_io SCLK_o C3 3 | set_io SDATA_i B5 4 | set_io spi_ss_i B2 5 | set_io spi_sck_i D6 6 | set_io spi_miso_o A4 -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/design2/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io IR_TXD_o F7 2 | set_io IR_RXD_i F6 3 | set_io I2S_CLK_i C4 4 | set_io I2S_WS_CLK_i B3 5 | set_io I2S_DIN_i A4 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/design3/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I2S_CLK_o C4 2 | set_io I2S_CLK_i B4 3 | set_io I2S_WS_CLK_i B3 4 | set_io I2S_DIN_i A4 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/design9/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io GPIO_PIN[7] G6 2 | set_io GPIO_PIN[6] G4 3 | set_io GPIO_PIN[5] H5 4 | set_io GPIO_PIN[4] F6 5 | set_io GPIO_PIN[3] F7 6 | set_io GPIO_PIN[2] G7 7 | set_io GPIO_PIN[1] H7 8 | set_io GPIO_PIN[0] E8 9 | set_io I2C_SDA C1 10 | set_io I2C_SCL B1 11 | set_io CLK_4MHZ_OUT H1 12 | set_io CLK_1MHZ_OUT F1 -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/e_sdio_host_controller/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io sys_clk A3 2 | set_io reset B1 3 | set_io sd_bclkx2 C4 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/fifo_test/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io GPIO_PIN[7] A2 2 | set_io GPIO_PIN[6] B2 3 | set_io GPIO_PIN[5] C3 4 | set_io GPIO_PIN[4] B3 5 | set_io GPIO_PIN[3] D6 6 | set_io GPIO_PIN[1] A4 7 | set_io GPIO_PIN[2] C5 8 | set_io GPIO_PIN[0] B5 -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/inferred_ram_test/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io GPIO_PIN[0] E8 2 | set_io GPIO_PIN[1] C5 3 | set_io GPIO_PIN[2] G1 4 | set_io GPIO_PIN[3] C6 5 | set_io GPIO_PIN[4] F6 6 | set_io GPIO_PIN[5] A1 7 | set_io GPIO_PIN[6] B2 8 | set_io GPIO_PIN[7] C4 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/jpeg_qnr/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk C4 # Clock 2 | set_io din A1 3 | set_io dout C3 4 | set_io douten G2 5 | set_io dstrb E3 6 | set_io ena F2 7 | set_io qnt_cnt B3 8 | set_io qnt_val B2 9 | set_io rst H6 10 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/rgb2ycrcb/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io b F6 2 | set_io cb C4 3 | set_io clk C4 # Clock 4 | set_io cr D6 5 | set_io ena F4 6 | set_io g H8 7 | set_io r A5 8 | set_io y H1 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/rs_decoder_1/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk G6 # Clock 2 | set_io clrn A3 3 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/sha256/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk_i C4 # Clock 2 | set_io cmd_i A4 3 | set_io cmd_o H4 4 | set_io cmd_w_i B4 5 | set_io rst_i F4 6 | set_io text_i G8 7 | set_io text_o D7 8 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/sha_top/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk_i G6 # Clock 2 | set_io rst_i B4 3 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/shift_reg_576/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk G6 # Clock 2 | set_io clr G7 3 | set_io shift_in B2 4 | set_io shift_out F3 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/spi_master_top/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io arst_i H5 2 | set_io wb_clk_i H6 # Clock 3 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/sudoku_check/chandalar.pcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/quicklogic/pp3/tests/design_flow/sudoku_check/chandalar.pcf -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/test_logic_cell/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | set_io ff_in_sel A1 3 | set_io fs_in C3 4 | set_io bb2_in B3 5 | set_io ba1_in A2 6 | set_io tb1_in B2 7 | set_io ta2_in A3 8 | set_io tsel_in C4 9 | set_io tabsel_in B4 10 | set_io bsel_in A4 11 | set_io babsel_in C5 12 | set_io tbsel_in B5 13 | set_io ff_out D6 14 | set_io f_out A5 15 | set_io t_out C6 16 | set_io c_out E7 17 | 18 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/design_flow/top_120_13/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk1 H6 # Clock 2 | set_io clk2 A3 # Clock 3 | set_io clk3 C4 # Clock 4 | set_io out1x[0] A4 5 | set_io reset D7 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/ext_counter/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | set_io led[0] H7 3 | set_io led[1] G7 4 | set_io led[2] F6 5 | set_io led[3] E8 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/ext_counter/ext_counter.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | output wire [3:0] led 4 | ); 5 | 6 | reg [23:0] cnt; 7 | initial cnt <= 0; 8 | 9 | always @(posedge clk) 10 | cnt <= cnt + 1; 11 | 12 | assign led = cnt[23:20]; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/ext_counter/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io clk A1 2 | set_io led[0] A2 3 | set_io led[1] A3 4 | set_io led[2] B1 5 | set_io led[3] B3 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/ext_counter/quickfeather.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 63 2 | set_io led[0] 34 3 | set_io led[1] 39 4 | set_io led[2] 38 5 | set_io led[3] 25 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/ext_mult/ext_mult.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [ 7:0] dat_a, 3 | input wire [ 7:0] dat_b, 4 | output wire [15:0] dat_o 5 | ); 6 | 7 | // Asynchronous multiplier implemented using logic. 8 | // For the purpose of timing model evaluation. 9 | assign dat_o = dat_a * dat_b; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Add feature specific testcases here 2 | add_subdirectory(install_test) 3 | 4 | add_subdirectory(counter_gclk) 5 | add_subdirectory(counter) 6 | add_subdirectory(ram_inference) 7 | add_subdirectory(ram) 8 | add_subdirectory(fifo) 9 | 10 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/counter/counter.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | output wire [3:0] led 4 | ); 5 | 6 | reg [3:0] cnt; 7 | initial cnt <= 0; 8 | 9 | always @(posedge clk) 10 | cnt <= cnt + 1; 11 | 12 | assign led = cnt; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/counter/quickfeather.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 62 2 | set_io led[0] 34 3 | set_io led[1] 39 4 | set_io led[2] 38 5 | set_io led[3] 25 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/counter_gclk/counter.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | output wire [3:0] led 4 | ); 5 | 6 | reg [3:0] cnt; 7 | initial cnt <= 0; 8 | 9 | always @(posedge clk) 10 | cnt <= cnt + 1; 11 | 12 | assign led = cnt; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/counter_gclk/quickfeather.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 63 2 | set_io led[0] 34 3 | set_io led[1] 39 4 | set_io led[2] 38 5 | set_io led[3] 25 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/fifo/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io Push_Clk A3 2 | set_io Pop_Clk C4 3 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/fifo/chandalar_1clk.pcf: -------------------------------------------------------------------------------- 1 | set_io Clk A3 2 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Tests for packing and placing primitives. Not to be run on actual HW ! 2 | add_subdirectory(wire) 3 | add_subdirectory(lut1) 4 | add_subdirectory(lut2) 5 | add_subdirectory(lut3) 6 | add_subdirectory(lut4) 7 | add_subdirectory(consts) 8 | 9 | add_subdirectory(counter) 10 | add_subdirectory(counter_gclk) 11 | add_subdirectory(counter_assp) 12 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/consts/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_binary_toolchain_test( 2 | TEST_NAME consts 3 | DEVICE ql-eos-s3 4 | PINMAP PD64 5 | EXTRA_ARGS "-dump post_verilog" 6 | ) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/consts/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io O B2 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/consts/consts.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [1:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT4 #(.INIT(0)) a_lut_with_consts ( 7 | .I0(I[0]), 8 | .I1(I[1]), 9 | .I2(1'b0), 10 | .I3(1'b1), 11 | .O(O) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/counter/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk B1 2 | set_io led[0] H7 3 | set_io led[1] G7 4 | set_io led[2] F6 5 | set_io led[3] E8 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/counter/counter.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | output wire [3:0] led 4 | ); 5 | 6 | reg [3:0] cnt; 7 | initial cnt <= 0; 8 | 9 | always @(posedge clk) 10 | cnt <= cnt + 1; 11 | 12 | assign led = cnt; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/counter_assp/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io led[0] H7 2 | set_io led[1] G7 3 | set_io led[2] F6 4 | set_io led[3] E8 5 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/counter_gclk/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk A3 2 | set_io led[0] H7 3 | set_io led[1] G7 4 | set_io led[2] F6 5 | set_io led[3] E8 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/counter_gclk/counter_gclk.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 100.0 clk 2 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/counter_gclk/counter_gclk.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | output wire [3:0] led 4 | ); 5 | 6 | reg [3:0] cnt; 7 | initial cnt <= 0; 8 | 9 | always @(posedge clk) 10 | cnt <= cnt + 1; 11 | 12 | assign led = cnt; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut1/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_binary_toolchain_test( 2 | TEST_NAME lut1 3 | DEVICE ql-eos-s3 4 | PINMAP PD64 5 | EXTRA_ARGS "-dump post_verilog" 6 | ) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut1/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io I[2] A1 4 | set_io I[3] A2 5 | set_io O B2 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut1/lut1.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [3:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT1 #(.INIT(2'b01)) the_lut ( 7 | .I0(I[0]), 8 | .O(O) 9 | ); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_binary_toolchain_test( 2 | TEST_NAME lut2 3 | DEVICE ql-eos-s3 4 | PINMAP PD64 5 | EXTRA_ARGS "-dump post_verilog" 6 | ) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut2/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io I[2] A1 4 | set_io I[3] A2 5 | set_io O B2 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut2/lut2.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [3:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT2 #(.INIT(4'b0000)) the_lut ( 7 | .I0(I[0]), 8 | .I1(I[1]), 9 | .O(O) 10 | ); 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_binary_toolchain_test( 2 | TEST_NAME lut3 3 | DEVICE ql-eos-s3 4 | PINMAP PD64 5 | EXTRA_ARGS "-dump post_verilog" 6 | ) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut3/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io I[2] A1 4 | set_io I[3] A2 5 | set_io O B2 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut3/lut3.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [3:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT3 #(.INIT(0)) the_lut ( 7 | .I0(I[0]), 8 | .I1(I[1]), 9 | .I2(I[2]), 10 | .O(O) 11 | ); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut4/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_binary_toolchain_test( 2 | TEST_NAME lut4 3 | DEVICE ql-eos-s3 4 | PINMAP PD64 5 | EXTRA_ARGS "-dump post_verilog" 6 | ) 7 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut4/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io I[2] A1 4 | set_io I[3] A2 5 | set_io O B2 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/lut4/lut4.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [3:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT4 #(.INIT(0)) the_lut ( 7 | .I0(I[0]), 8 | .I1(I[1]), 9 | .I2(I[2]), 10 | .I3(I[3]), 11 | .O(O) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/wire/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_binary_toolchain_test( 2 | TEST_NAME wire 3 | DEVICE ql-eos-s3 4 | PINMAP PD64 5 | ) 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/wire/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io inp B1 2 | set_io out C1 3 | 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/install_test/wire/wire.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire inp, 3 | output wire out 4 | ); 5 | 6 | assign out = inp; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/ram/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io WClk A3 2 | set_io RClk C4 3 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/features/ram_inference/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io clk A3 2 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/lut/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] B1 2 | set_io I[1] C1 3 | set_io I[2] A1 4 | set_io I[3] A2 5 | set_io O B2 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/lut/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] A2 2 | set_io I[1] A3 3 | set_io I[2] B1 4 | set_io I[3] B3 5 | set_io O A1 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/lut/lut1.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [3:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT1 #(.INIT(2'b01)) the_lut ( 7 | .I0(I[0]), 8 | .O(O) 9 | ); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/lut/lut2.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [3:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT2 #(.INIT(4'b0000)) the_lut ( 7 | .I0(I[0]), 8 | .I1(I[1]), 9 | .O(O) 10 | ); 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/lut/lut3.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [3:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT3 #(.INIT(0)) the_lut ( 7 | .I0(I[0]), 8 | .I1(I[1]), 9 | .I2(I[2]), 10 | .O(O) 11 | ); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/lut/lut4.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [3:0] I, 3 | output wire O 4 | ); 5 | 6 | LUT4 #(.INIT(0)) the_lut ( 7 | .I0(I[0]), 8 | .I1(I[1]), 9 | .I2(I[2]), 10 | .I3(I[3]), 11 | .O(O) 12 | ); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/sdiomux_xor/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] D2 2 | set_io I[1] F1 3 | set_io O[0] H1 4 | set_io O[1] E8 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/sdiomux_xor/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io I[0] A1 2 | set_io I[1] A2 3 | set_io O[0] A3 4 | set_io O[1] B1 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/sdiomux_xor/sdiomux_xor.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire [1:0] I, 3 | output wire [1:0] O 4 | ); 5 | 6 | assign O[0] = I[0] ^ I[1]; 7 | assign O[1] = I[0] ^ I[1]; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/wire/chandalar.pcf: -------------------------------------------------------------------------------- 1 | set_io inp B1 2 | set_io out C1 3 | 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/wire/jimbob4.pcf: -------------------------------------------------------------------------------- 1 | set_io inp A1 2 | set_io out A2 3 | 4 | -------------------------------------------------------------------------------- /quicklogic/pp3/tests/wire/wire.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire inp, 3 | output wire out 4 | ); 5 | 6 | assign out = inp; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /quicklogic/pp3/timings/README.md: -------------------------------------------------------------------------------- 1 | SDF files are generated hence this folder is empty. 2 | -------------------------------------------------------------------------------- /quicklogic/pp3/utils/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | get_target_property_required(PYTHON3 env PYTHON3) 2 | -------------------------------------------------------------------------------- /quicklogic/pp3/utils/verify_jlink_openocd.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # look for duplicated configuration script footer, 4 | # exit with 1 if duplicate found (bad script format) 5 | 6 | # $1 - jlink/openocd script 7 | # $2 - output file 8 | 9 | 10 | cat $1 | grep '0x40004d[0-9]\{2\}' | awk '{print $2}' | sort | uniq -d > $2 11 | [ -s $2 ] && exit 1 || exit 0 12 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/devices/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(umc22) 2 | 3 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/techmap/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE cells_sim.v) 2 | add_file_target(FILE cells_map.v) 3 | 4 | get_file_target(CELLS_SIM_TARGET cells_sim.v) 5 | get_file_target(CELLS_MAP_TARGET cells_map.v) 6 | 7 | add_dependencies( 8 | ${CELLS_SIM_TARGET} 9 | ${CELLS_MAP_TARGET} 10 | ) 11 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/techmap/cells_map.v: -------------------------------------------------------------------------------- 1 | // Yosys techmap library that adapts the design for the VPR architecture. 2 | 3 | // Currently there is one-to-one relationship between cells emmited by synthesis tools (Yosys) and those expected by VPR. 4 | // There is no need for VPR specific technology mapping hence for now this file remains empty. 5 | 6 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/design_flow/VexRiscv/VexRiscv.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 0 * 2 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/design_flow/conv2d/conv2d.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 0 * 2 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/design_flow/conv2d_no_ksa/conv2d.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 0 * 2 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/design_flow/counter_16bit/counter_16bit.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 20 clk 2 | set_clock_uncertainty 2.0 3 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/design_flow/counter_4clk/counter_4clk.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.0 clk1 -waveform {0.000 5.000} 2 | create_clock -period 10.0 clk2 -waveform {0.000 5.000} 3 | create_clock -period 10.0 clk3 -waveform {0.000 5.000} 4 | create_clock -period 10.0 clk4 -waveform {0.000 5.000} 5 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/design_flow/counter_4clk/test.pcf: -------------------------------------------------------------------------------- 1 | set_io led[0] user_OUT_B[30] 2 | set_io led[1] user_OUT_T[11] 3 | set_io led[2] user_OUT_B[74] 4 | set_io led[3] user_OUT_R[35] 5 | set_clk clk[0] clk1 6 | set_clk clk[1] clk2 7 | set_clk clk[2] clk3 8 | set_clk clk[3] clk4 9 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/design_flow/multi_enc_decx2x4/multi_enc_decx2x4.pcf: -------------------------------------------------------------------------------- 1 | set_io dataout[0] user_OUT_R[0] 2 | set_io clock user_IN_R[7] 3 | set_io reset user_IN_R[8] 4 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/design_flow/top_120_13/top_120_13.pcf: -------------------------------------------------------------------------------- 1 | set_io clk1 user_IN_B[10] 2 | set_io clk2 user_IN_B[11] 3 | set_io clk3 user_IN_B[12] 4 | set_io reset user_IN_B[13] 5 | set_io out1x[0] user_OUT_B[10] 6 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/clk_pcf_verify/clock_tree_design.pcf: -------------------------------------------------------------------------------- 1 | set_io t user_IN_T[1] 2 | set_io clr_n user_IN_T[2] 3 | set_io sel[0] user_IN_R[0] 4 | set_io sel[1] user_IN_R[1] 5 | set_io mux_out[0] user_OUT_R[0] 6 | 7 | set_clk clk[0] clk[3] 8 | set_clk clk[1] clk[2] 9 | set_clk clk[2] clk[0] 10 | set_clk clk[3] clk[1] 11 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/install_test/.gitignore: -------------------------------------------------------------------------------- 1 | Makefile.symbiflow 2 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/install_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(counter_16bit) 2 | add_subdirectory(compile_args) 3 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/install_test/compile_args/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_binary_toolchain_test( 2 | TEST_NAME compile_args 3 | DEVICE qlf_k4n8 4 | PINMAP pinmap_qlf_k4n8_umc22.csv 5 | EXTRA_ARGS "+incdir+${CMAKE_CURRENT_SOURCE_DIR}/includes -y ${CMAKE_CURRENT_SOURCE_DIR}/libraries +libext+not_v" 6 | ) 7 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/install_test/compile_args/includes/add_2.v: -------------------------------------------------------------------------------- 1 | module add_2 (in, out); 2 | input wire [7:0] in; 3 | output wire [7:0] out; 4 | 5 | assign out = in + 2; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/install_test/compile_args/libraries/add_3.not_v: -------------------------------------------------------------------------------- 1 | module add_3 (in, out); 2 | input wire [7:0] in; 3 | output wire [7:0] out; 4 | 5 | assign out = in + 3; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/install_test/counter_16bit/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_binary_toolchain_test( 2 | TEST_NAME counter_16bit 3 | DEVICE qlf_k4n8 4 | PINMAP pinmap_qlf_k4n8_umc22.csv 5 | ) 6 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/install_test/counter_16bit/counter_16bit.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 20 clk 2 | set_clock_uncertainty 2.0 3 | 4 | set_input_delay -clock clk -max 1.0 [get_ports user_IN_T[0]] 5 | set_input_delay -clock clk -max 0.5 [get_ports user_IN_T[1]] 6 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/io_reg_max/io_reg_max.pcf: -------------------------------------------------------------------------------- 1 | set_io demux_out[0] user_OUT_R[0] 2 | set_io mux_in[0] user_IN_R[7] 3 | set_io com_sel[1] user_IN_R[8] 4 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/pcf_and_sdc_option/shift_reg_8.pcf: -------------------------------------------------------------------------------- 1 | set_io shift_in user_IN_T[0] 2 | set_io clr user_IN_T[1] 3 | set_io shift_out user_OUT_T[10] 4 | 5 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/pcf_and_sdc_option/shift_reg_8.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 15.0 clk -waveform {0.000 5.000} 2 | set_clock_uncertainty 2.0 3 | 4 | set_input_delay -clock clk -max 1 [get_ports user_IN_T[0]] 5 | set_input_delay -clock clk -max 1 [get_ports clr] 6 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/pcf_io_reg/io_reg.pcf: -------------------------------------------------------------------------------- 1 | set_io in user_IN_T[0] 2 | set_clk clk[3] clk 3 | set_io out user_OUT_T[8] 4 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/features/sdc_option/shift_reg_8.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 15.0 clk -waveform {0.000 5.000} 2 | set_clock_uncertainty 2.0 3 | -------------------------------------------------------------------------------- /quicklogic/qlf_k4n8/tests/synth_flow/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(des_perf) 2 | add_subdirectory(iir) 3 | add_subdirectory(rgb2ycrcb) 4 | -------------------------------------------------------------------------------- /testarch/primitives/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(ff) 2 | add_subdirectory(lut) 3 | add_subdirectory(lutff) 4 | add_subdirectory(omux) 5 | add_subdirectory(const) 6 | -------------------------------------------------------------------------------- /testarch/primitives/const/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE gnd.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE vcc.model.xml SCANNER_TYPE xml) 3 | add_file_target(FILE gnd.pb_type.xml SCANNER_TYPE xml) 4 | add_file_target(FILE vcc.pb_type.xml SCANNER_TYPE xml) 5 | -------------------------------------------------------------------------------- /testarch/primitives/const/gnd.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /testarch/primitives/const/gnd.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | bel 5 | blackbox 6 | 7 | 8 | -------------------------------------------------------------------------------- /testarch/primitives/const/vcc.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /testarch/primitives/const/vcc.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | bel 5 | blackbox 6 | 7 | 8 | -------------------------------------------------------------------------------- /testarch/primitives/ff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ff.sim.v SCANNER_TYPE verilog) 2 | v2x(NAME ff SRCS ff.sim.v) 3 | -------------------------------------------------------------------------------- /testarch/primitives/ff/ff.sim.v: -------------------------------------------------------------------------------- 1 | module FF(clk, D, Q); 2 | 3 | (* PORT_CLASS = "clock" *) 4 | input clk; 5 | 6 | (* PORT_CLASS = "D" *) (* SETUP = "clk 10e-12" *) 7 | input D; 8 | 9 | (* PORT_CLASS = "Q" *) (* CLK_TO_Q = "clk 10e-12" *) 10 | output reg Q; 11 | 12 | always @(posedge clk) 13 | Q <= D; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /testarch/primitives/lut/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE lut.sim.v SCANNER_TYPE verilog) 2 | v2x(NAME lut SRCS lut.sim.v) 3 | -------------------------------------------------------------------------------- /testarch/primitives/lut/lut.sim.v: -------------------------------------------------------------------------------- 1 | (* whitebox *) (* CLASS="lut" *) 2 | module LUT (in, out); 3 | parameter [15:0] INIT = 16'hDEAD; 4 | 5 | (* PORT_CLASS = "lut_in" *) 6 | input [3:0] in; 7 | 8 | (* PORT_CLASS = "lut_out" *) 9 | (* DELAY_MATRIX_in = "10e-12; 10e-12; 10e-12; 10e-12" *) 10 | output out; 11 | 12 | assign out = INIT[in]; 13 | endmodule 14 | -------------------------------------------------------------------------------- /testarch/primitives/lutff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE lutff.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE lutff.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /testarch/primitives/lutff/lutff.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /testarch/primitives/omux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME omux 3 | INPUTS LT,FF 4 | MUX_NAME OMUX 5 | SPLIT_INPUTS 1 6 | TYPE routing 7 | WIDTH 2 8 | ) 9 | -------------------------------------------------------------------------------- /testarch/techmap/ff_map.v: -------------------------------------------------------------------------------- 1 | module \$_DFF_N_ (input D, C, output Q); FF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .clk(C)); endmodule 2 | module \$_DFF_P_ (input D, C, output Q); FF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .clk(C)); endmodule 3 | -------------------------------------------------------------------------------- /testarch/tiles/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(clutff) 2 | add_subdirectory(ff-large) 3 | add_subdirectory(ff1) 4 | add_subdirectory(lutff) 5 | add_subdirectory(lutff3) 6 | add_subdirectory(wire) 7 | add_subdirectory(const) 8 | -------------------------------------------------------------------------------- /testarch/tiles/clutff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE clutff.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE clutff.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /testarch/tiles/const/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE vcc.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE vcc.pb_type.xml SCANNER_TYPE xml) 3 | add_file_target(FILE gnd.model.xml SCANNER_TYPE xml) 4 | add_file_target(FILE gnd.pb_type.xml SCANNER_TYPE xml) 5 | -------------------------------------------------------------------------------- /testarch/tiles/const/gnd.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /testarch/tiles/const/vcc.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /testarch/tiles/ff-large/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ff-large.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ff-large.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /testarch/tiles/ff-large/ff-large.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /testarch/tiles/ff1/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ff1.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ff1.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /testarch/tiles/ff1/ff1.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /testarch/tiles/lutff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE lutff.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE lutff.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /testarch/tiles/lutff/lutff.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /testarch/tiles/lutff3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE lutff3.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE lutff3.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /testarch/tiles/lutff3/lutff3.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /testarch/tiles/wire/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE wire.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE wire.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /testarch/tiles/wire/wire.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /tests/.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore the build output dir 2 | build 3 | build-* 4 | 5 | # Ignore build log files 6 | *.log 7 | -------------------------------------------------------------------------------- /tests/0-const/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 0-const 3 | SOURCES const.v 4 | BOARDS ${BOARDS} 5 | DEFINES USE_LUT_CONSTANTS=1 6 | 7 | ) 8 | -------------------------------------------------------------------------------- /tests/0-const/const.v: -------------------------------------------------------------------------------- 1 | module top(output out); 2 | assign out = 1; 3 | endmodule // top 4 | -------------------------------------------------------------------------------- /tests/1-wire/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 1-wire 3 | SOURCES wire.v 4 | BOARDS ${BOARDS} 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /tests/1-wire/wire.v: -------------------------------------------------------------------------------- 1 | module top(input in, output out); 2 | assign out = in; 3 | endmodule // top 4 | -------------------------------------------------------------------------------- /tests/2-mwire/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 2-mwire 3 | SOURCES mwire.v 4 | BOARDS ${BOARDS} 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /tests/2-mwire/mwire.v: -------------------------------------------------------------------------------- 1 | module top(input i0, input i1, input i2, output o0, output o1, output o2, output o3, output o4, output o5); 2 | assign o0 = i0; 3 | assign o1 = i1; 4 | assign o2 = i1; 5 | assign o3 = i2; 6 | assign o4 = i2; 7 | assign o5 = i2; 8 | endmodule // top 9 | -------------------------------------------------------------------------------- /tests/3-ff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 3-ff 3 | SOURCES ff.v 4 | BOARDS ${BOARDS} 5 | EQUIV_CHECK_SCRIPT 6 | ${f4pga-arch-defs_SOURCE_DIR}/common/yosys/equiv_simple_clk2fflogic.ys 7 | ) 8 | 9 | -------------------------------------------------------------------------------- /tests/3-ff/ff.v: -------------------------------------------------------------------------------- 1 | // Single flip-flip test. 2 | module top(input clk, input di, output do); 3 | always @( posedge clk ) 4 | do <= di; 5 | endmodule // top 6 | -------------------------------------------------------------------------------- /tests/3-lut4/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 3-lut4 3 | SOURCES lut4.v 4 | BOARDS ${BOARDS} 5 | ) 6 | -------------------------------------------------------------------------------- /tests/3-lut4/lut4.v: -------------------------------------------------------------------------------- 1 | // 4-input LUT test. 2 | module top(input [3:0] I, output O); 3 | always @(I) 4 | case(I) 5 | 4'b0000 : O = 1; 6 | 4'b1000 : O = 1; 7 | 4'b1100 : O = 1; 8 | 4'b1010 : O = 1; 9 | 4'b1001 : O = 1; 10 | 4'b1111 : O = 1; 11 | default : O = 0; 12 | endcase 13 | endmodule // top 14 | -------------------------------------------------------------------------------- /tests/3-lut5x2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 3-lut5x2 3 | SOURCES lut5x2.v 4 | BOARDS ${FULL_BOARDS} 5 | ) 6 | -------------------------------------------------------------------------------- /tests/3-lut6/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 3-lut6 3 | SOURCES lut6.v 4 | BOARDS ${BOARDS} 5 | ) 6 | -------------------------------------------------------------------------------- /tests/3-lut7/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 3-lut7 3 | SOURCES lut7.v 4 | BOARDS ${BOARDS} 5 | ) 6 | -------------------------------------------------------------------------------- /tests/3-lut8/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 3-lut8 3 | SOURCES lut8.v 4 | BOARDS ${FULL_BOARDS} 5 | ) 6 | -------------------------------------------------------------------------------- /tests/4-lutff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 4-lutff 3 | SOURCES lutff.v 4 | BOARDS ${BOARDS} 5 | EQUIV_CHECK_SCRIPT 6 | ${f4pga-arch-defs_SOURCE_DIR}/common/yosys/equiv_simple_clk2fflogic.ys 7 | ) 8 | -------------------------------------------------------------------------------- /tests/4-lutff/lutff.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk, 3 | input [3:0] i, 4 | output reg o 5 | ); 6 | always @(posedge clk) 7 | o <= ^i; 8 | endmodule 9 | -------------------------------------------------------------------------------- /tests/4-mlut/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE mlut.eblif) 2 | add_simple_test( 3 | NAME 4-mlut 4 | SOURCES mlut.eblif 5 | BOARDS ${BOARDS} 6 | EXPLICIT_ADD_FILE_TARGET 7 | NO_SYNTHESIS 8 | ) 9 | -------------------------------------------------------------------------------- /tests/4-mlut/mlut.eblif: -------------------------------------------------------------------------------- 1 | .model top 2 | .inputs I0 I1 I2 I3 I4 I5 I6 3 | .outputs O1 O2 O3 4 | .names I0 I1 I2 I3 O1 5 | 1000 1 6 | 1001 1 7 | 1010 1 8 | 1100 1 9 | 1110 1 10 | 1111 1 11 | .names I4 I1 I2 I3 O2 12 | 1000 1 13 | 1001 1 14 | 1010 1 15 | 1100 1 16 | 1110 1 17 | 1111 1 18 | .names I4 I5 I6 O3 19 | 100 1 20 | 100 1 21 | 101 1 22 | 110 1 23 | 111 1 24 | .end 25 | -------------------------------------------------------------------------------- /tests/5-lut_cascade_1/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 5-lut_cascade_1 3 | SOURCES lut_cascade_1.v 4 | BOARDS ${BOARDS} 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /tests/6-big_xor/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 6-big_xor 3 | SOURCES big_xor.v 4 | BOARDS ${BOARDS} 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /tests/6-big_xor/big_xor.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input [6:0] in, 3 | output out 4 | ); 5 | assign out = ^in; 6 | endmodule 7 | -------------------------------------------------------------------------------- /tests/6-counter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 6-counter 3 | SOURCES counter.v 4 | BOARDS ${BOARDS} 5 | ) 6 | -------------------------------------------------------------------------------- /tests/6-counter/counter.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk, 3 | output o 4 | ); 5 | reg [2:0] counter = 0; 6 | always @(posedge clk) 7 | counter <= counter + 1; 8 | assign o = counter[2]; 9 | endmodule 10 | -------------------------------------------------------------------------------- /tests/6-led/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_simple_test( 2 | NAME 6-led 3 | SOURCES led.v 4 | BOARDS ${FULL_BOARDS} 5 | ROUTE_ONLY 6 | DEFINES USE_LUT_CONSTANTS=1 7 | ) 8 | -------------------------------------------------------------------------------- /tests/9-scalable_proc/basys3.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.0 clk 2 | 3 | -------------------------------------------------------------------------------- /tests/9-soc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(murax) 2 | add_subdirectory(picosoc) 3 | -------------------------------------------------------------------------------- /tests/9-soc/murax/basys3.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.0 clk 2 | -------------------------------------------------------------------------------- /tests/9-soc/picosoc/basys3.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.0 clk 2 | -------------------------------------------------------------------------------- /tests/9-soc/picosoc/firmware/README.md: -------------------------------------------------------------------------------- 1 | # PicoSoC demo firmware 2 | 3 | Run `make all` to build HEX files with the firmware. You need to have RiscV toolchain installed and the env. var. `RISCV` pointing to it. 4 | -------------------------------------------------------------------------------- /utils/clean_json5.py: -------------------------------------------------------------------------------- 1 | import pyjson5 2 | import simplejson 3 | import sys 4 | 5 | 6 | def main(): 7 | simplejson.dump(pyjson5.load(sys.stdin), sys.stdout, indent=2) 8 | 9 | 10 | if __name__ == "__main__": 11 | main() 12 | -------------------------------------------------------------------------------- /utils/conftest.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | collect_ignore = [ 4 | "vlog/vlog_to_model.py", # Can't be imported - Issue #61 5 | "vlog/vlog_to_pbtype.py", # Can't be imported - Issue #61 6 | ] 7 | -------------------------------------------------------------------------------- /utils/lib/__init__.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | -------------------------------------------------------------------------------- /utils/lib/rr_graph/__main__.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | from .. import rr_graph 3 | 4 | if __name__ == "__main__": 5 | import doctest 6 | failure_count, test_count = doctest.testmod(rr_graph) 7 | assert test_count > 0 8 | assert failure_count == 0, "Doctests failed!" 9 | -------------------------------------------------------------------------------- /utils/lib/rr_graph/tests/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/utils/lib/rr_graph/tests/__init__.py -------------------------------------------------------------------------------- /utils/lib/rr_graph_capnp/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/utils/lib/rr_graph_capnp/__init__.py -------------------------------------------------------------------------------- /utils/lib/rr_graph_xml/utils.py: -------------------------------------------------------------------------------- 1 | from __future__ import print_function 2 | import lxml.etree as ET 3 | 4 | 5 | def read_xml_file(rr_graph_file): 6 | return ET.parse(rr_graph_file, ET.XMLParser(remove_blank_text=True)) 7 | -------------------------------------------------------------------------------- /utils/quiet_cmd.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | if [[ $VERBOSE -gt 0 ]]; then 3 | set -x 4 | fi 5 | 6 | OUTPUT=$(mktemp $(basename $1).output.XXX) 7 | 8 | set +e 9 | "$@" > $OUTPUT 2>&1 10 | RESULT=$? 11 | set -e 12 | if [[ $RESULT -ne 0 ]] || [[ $VERBOSE -gt 0 ]]; then 13 | cat $OUTPUT 14 | fi 15 | rm $OUTPUT 16 | exit $RESULT 17 | -------------------------------------------------------------------------------- /utils/tile_splitter/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/utils/tile_splitter/__init__.py -------------------------------------------------------------------------------- /utils/tile_splitter/tests/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/utils/tile_splitter/tests/__init__.py -------------------------------------------------------------------------------- /utils/update_tools/.gitignore: -------------------------------------------------------------------------------- 1 | vtr/ 2 | -------------------------------------------------------------------------------- /vpr/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(buf) 2 | add_subdirectory(const) 3 | add_subdirectory(ff) 4 | add_subdirectory(ibuf) 5 | add_subdirectory(muxes) 6 | add_subdirectory(obuf) 7 | add_subdirectory(pad) 8 | add_subdirectory(dual-pad) 9 | add_subdirectory(wire) 10 | -------------------------------------------------------------------------------- /vpr/buf/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE buf.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE buf.pb_type.xml SCANNER_TYPE xml) 3 | 4 | -------------------------------------------------------------------------------- /vpr/buf/buf.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /vpr/buf/buf.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /vpr/const/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE const.pb_type.xml SCANNER_TYPE xml) 2 | 3 | -------------------------------------------------------------------------------- /vpr/dual-pad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE dual-pad.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ibuf.pb_type.xml SCANNER_TYPE xml) 3 | add_file_target(FILE obuf.pb_type.xml SCANNER_TYPE xml) 4 | -------------------------------------------------------------------------------- /vpr/dual-pad/dual-pad.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /vpr/ff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE vpr_ff.sim.v SCANNER_TYPE verilog) 2 | v2x(NAME vpr_ff SRCS vpr_ff.sim.v) 3 | -------------------------------------------------------------------------------- /vpr/ibuf/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ibuf.pb_type.xml SCANNER_TYPE xml) 2 | 3 | -------------------------------------------------------------------------------- /vpr/muxes/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(logic) 2 | -------------------------------------------------------------------------------- /vpr/muxes/logic/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(mux2) 2 | add_subdirectory(mux8) 3 | -------------------------------------------------------------------------------- /vpr/muxes/logic/mux2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE mux2.sim.v SCANNER_TYPE verilog) 2 | v2x(NAME mux2 SRCS mux2.sim.v) 3 | -------------------------------------------------------------------------------- /vpr/muxes/logic/mux2/mux2.sim.v: -------------------------------------------------------------------------------- 1 | `ifndef VPR_MUXES_LOGIC_MUX2 2 | `define VPR_MUXES_LOGIC_MUX2 3 | 4 | module MUX2(I0, I1, S0, O); 5 | input wire I0; 6 | input wire I1; 7 | input wire S0; 8 | output wire O; 9 | 10 | assign O = S0 ? I1 : I0; 11 | endmodule 12 | 13 | `endif 14 | -------------------------------------------------------------------------------- /vpr/muxes/logic/mux8/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE mux8.sim.v SCANNER_TYPE verilog) 2 | v2x(NAME mux8 SRCS mux8.sim.v) 3 | -------------------------------------------------------------------------------- /vpr/obuf/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE obuf.pb_type.xml SCANNER_TYPE xml) 2 | -------------------------------------------------------------------------------- /vpr/pad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE pad.pb_type.xml SCANNER_TYPE xml) 2 | -------------------------------------------------------------------------------- /vpr/wire/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE wire.pb_type.xml SCANNER_TYPE xml) 2 | 3 | -------------------------------------------------------------------------------- /xilinx/common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(cmake) 2 | add_subdirectory(utils) 3 | add_subdirectory(primitives) 4 | -------------------------------------------------------------------------------- /xilinx/common/cmake/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include(project_ray.cmake) 2 | include(arch_define.cmake) 3 | include(device_define.cmake) 4 | include(vivado.cmake) 5 | -------------------------------------------------------------------------------- /xilinx/common/primitives/bram/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ramb18e1.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ramb18e1.pb_type.xml SCANNER_TYPE xml) 3 | 4 | add_file_target(FILE rambfifo36e1.model.xml SCANNER_TYPE xml) 5 | add_file_target(FILE rambfifo36e1.pb_type.xml SCANNER_TYPE xml) 6 | 7 | add_file_target(FILE bram.model.xml SCANNER_TYPE xml) 8 | add_file_target(FILE bram.pb_type.xml SCANNER_TYPE xml) 9 | -------------------------------------------------------------------------------- /xilinx/common/primitives/bram/bram.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /xilinx/common/primitives/bram_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE bram_l.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE bram_l.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/bram_l/bram_l.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /xilinx/common/primitives/bram_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE bram_r.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE bram_r.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/bram_r/bram_r.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /xilinx/common/primitives/bufgctrl/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE bufgctrl.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE bufgctrl.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/bufhce/ntemplate.bufhceN.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/Nlut/ntemplate.Nlut.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/muxes/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(f6mux) 2 | add_subdirectory(f7amux) 3 | add_subdirectory(f7bmux) 4 | add_subdirectory(f8mux) 5 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/muxes/f6mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME f6mux 3 | COMMENT 4 | "MUX which is used to create a LUT6 from two LUT5s" 5 | MUX_NAME F6MUX 6 | INPUTS I0,I1 7 | OUTPUT O 8 | SELECTS S 9 | SUBCKT MUXF6 10 | SPLIT_INPUTS 11 | 1 12 | SPLIT_SELECTS 13 | 1 14 | TYPE logic 15 | WIDTH 2 16 | ) 17 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/muxes/f7amux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME f7amux 3 | COMMENT "F7AMUX is used to create a LUT7 from two LUT6s." 4 | MUX_NAME F7AMUX 5 | SUBCKT MUXF7 6 | INPUTS I0,I1 7 | OUTPUT O 8 | SELECTS S 9 | SPLIT_INPUTS 1 10 | SPLIT_SELECTS 1 11 | TYPE logic 12 | WIDTH 2 13 | ) 14 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/muxes/f7bmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME f7bmux 3 | COMMENT "F7BMUX is used to create a LUT7 from two LUT6s." 4 | MUX_NAME F7BMUX 5 | SUBCKT MUXF7 6 | INPUTS I0,I1 7 | OUTPUT O 8 | SELECTS S 9 | SPLIT_INPUTS 1 10 | SPLIT_SELECTS 1 11 | TYPE logic 12 | WIDTH 2 13 | ) 14 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/muxes/f8mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME f8mux 3 | COMMENT 4 | "F8MUX is used to create a LUT8 from two LUT7s (which are built out of two LUT6s themselves)." 5 | MUX_NAME F8MUX 6 | INPUTS I0,I1 7 | OUTPUT O 8 | SELECTS S 9 | SUBCKT MUXF8 10 | SPLIT_INPUTS 11 | 1 12 | SPLIT_SELECTS 13 | 1 14 | TYPE logic 15 | WIDTH 2 16 | ) 17 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/N5ffmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME ntemplate.N5ffmux 3 | COMMENT "MUX on inputs to N5FF inputs." 4 | INPUTS IN_B,IN_A 5 | MUX_NAME {N}5FFMUX 6 | NTEMPLATE_PREFIXES a;b;c;d 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/Ncy0/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME ntemplate.Ncy0 3 | INPUTS O5,{N}X 4 | MUX_NAME {N}CY0 5 | NTEMPLATE_PREFIXES a;b;c;d 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 2 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/Nused/ntemplate.Nused.model.xml: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/Nused/ntemplate.Nused.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/Nused/ntemplate.Nused.sim.v: -------------------------------------------------------------------------------- 1 | `include "../../../../../../vpr/muxes/logic/mux2/mux2.sim.v" 2 | 3 | module {N}USED(I0, O); 4 | 5 | input wire I0; 6 | 7 | parameter [0:0] S = 0; 8 | 9 | output wire O; 10 | 11 | MUX2 mux ( 12 | .I0(I0), 13 | .I1(0), 14 | .S0(S), 15 | .O(O) 16 | ); 17 | endmodule 18 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/affmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME affmux 3 | INPUTS XOR,O6,O5,F7,CY,AX 4 | MUX_NAME AFFMUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 6 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/aoutmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME aoutmux 3 | INPUTS A5Q,XOR,O6,O5,F7,CY 4 | MUX_NAME AOUTMUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 6 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/bffmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME bffmux 3 | INPUTS XOR,O6,O5,F8,CY,BX 4 | MUX_NAME BFFMUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 6 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/boutmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME boutmux 3 | INPUTS B5Q,XOR,O6,O5,F8,CY 4 | MUX_NAME BOUTMUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 6 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/ceusedmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ceusedmux.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ceusedmux.sim.v SCANNER_TYPE verilog) 3 | add_verilog_image_gen(FILE ceusedmux.sim.v) 4 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/ceusedmux/ceusedmux.sim.v: -------------------------------------------------------------------------------- 1 | `include "../../../../../../vpr/muxes/logic/mux2/mux2.sim.v" 2 | 3 | module CEUSEDMUX(IN, OUT); 4 | input wire IN; 5 | 6 | parameter S = 0; 7 | output wire OUT; 8 | 9 | MUX2 mux ( 10 | .I0(1), 11 | .I1(IN), 12 | .S0(S), 13 | .O(OUT) 14 | ); 15 | endmodule 16 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/cffmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME cffmux 3 | INPUTS XOR,O6,O5,F7,CY,CX 4 | MUX_NAME CFFMUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 6 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/clkinv/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE clkinv.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE clkinv.sim.v SCANNER_TYPE verilog) 3 | add_verilog_image_gen(FILE clkinv.sim.v) 4 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/clkinv/clkinv.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/clkinv/clkinv.sim.v: -------------------------------------------------------------------------------- 1 | `include "../../../../../../vpr/muxes/logic/mux2/mux2.sim.v" 2 | 3 | module CLKINV(CLK, OUT); 4 | input wire CLK; 5 | 6 | parameter INV = 0; 7 | output wire OUT; 8 | 9 | MUX2 mux ( 10 | .I0(CLK), 11 | .I1(~CLK), 12 | .S0(INV), 13 | .O(OUT) 14 | ); 15 | endmodule 16 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/coutmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME coutmux 3 | INPUTS C5Q,XOR,O6,O5,F7,CY 4 | MUX_NAME COUTMUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 6 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/coutused/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE coutused.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE coutused.sim.v SCANNER_TYPE verilog) 3 | add_verilog_image_gen(FILE coutused.sim.v) 4 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/coutused/coutused.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/coutused/coutused.sim.v: -------------------------------------------------------------------------------- 1 | `include "../../../../../../vpr/muxes/logic/mux2/mux2.sim.v" 2 | 3 | module COUTUSED(IN, OUT); 4 | input wire IN; 5 | 6 | parameter S = 0; 7 | output wire OUT; 8 | 9 | MUX2 mux ( 10 | .I0(0), 11 | .I1(IN), 12 | .S0(S), 13 | .O(OUT) 14 | ); 15 | endmodule 16 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/dffmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME dffmux 3 | INPUTS XOR,O6,O5,DX,CY 4 | MUX_NAME DFFMUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 5 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/doutmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME doutmux 3 | INPUTS D5Q,XOR,O6,O5,CY 4 | MUX_NAME DOUTMUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 5 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/precyinit_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME precyinit_mux 3 | INPUTS CI,CYINIT,C0,C1 4 | MUX_NAME PRECYINIT_MUX 5 | OUTPUT OUT 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 4 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/srusedmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE srusedmux.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE srusedmux.sim.v SCANNER_TYPE verilog) 3 | add_verilog_image_gen(FILE srusedmux.sim.v) 4 | -------------------------------------------------------------------------------- /xilinx/common/primitives/common_slice/routing/srusedmux/srusedmux.sim.v: -------------------------------------------------------------------------------- 1 | `include "../../../../../../vpr/muxes/logic/mux2/mux2.sim.v" 2 | 3 | module SRUSEDMUX(IN, OUT); 4 | input wire IN; 5 | 6 | parameter S = 0; 7 | output wire OUT; 8 | 9 | MUX2 mux ( 10 | .I0(0), 11 | .I1(IN), 12 | .S0(S), 13 | .O(OUT) 14 | ); 15 | endmodule 16 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/alu/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE alu.sim.v SCANNER_TYPE verilog) 2 | v2x(NAME alu SRCS alu.sim.v) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/alumode_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME alumode_mux 3 | COMMENT "DSP48E1 ALUMODE mux" 4 | DATA_WIDTH 4 5 | INPUTS BYPASS,REG 6 | MUX_NAME ALUMODE_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/carryinsel_logic/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(carryin_mux) 2 | add_file_target(FILE carryinsel_logic.sim.v SCANNER_TYPE verilog) 3 | v2x(NAME carryinsel_logic SRCS carryinsel_logic.sim.v) 4 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/carryinsel_logic/carryin_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME carryin_mux 3 | COMMENT "mux used in CARRYIN selection" 4 | INPUTS BYPASS,REG 5 | MUX_NAME CARRYIN_MUX 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 2 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/carryinsel_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME carryinsel_mux 3 | COMMENT "DSP48E1 CARRYINSEL mux" 4 | DATA_WIDTH 3 5 | INPUTS BYPASS,REG 6 | MUX_NAME CARRYINSEL_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/creg_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME creg_mux 3 | COMMENT "DSP48E1 CREG mux" 4 | DATA_WIDTH 48 5 | INPUTS BYPASS,REG 6 | MUX_NAME CREG_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_ad_preadder/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(a_adder_mux) 2 | add_subdirectory(acout_mux) 3 | add_subdirectory(ain_mux) 4 | add_subdirectory(amult_mux) 5 | add_subdirectory(amux) 6 | add_subdirectory(dmux) 7 | add_file_target(FILE dual_ad_preadder.sim.v SCANNER_TYPE verilog) 8 | v2x(NAME dual_ad_preadder SRCS dual_ad_preadder.sim.v) 9 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_ad_preadder/a_adder_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME a_adder_mux 3 | COMMENT "DSP48E1 a adder mux" 4 | DATA_WIDTH 25 5 | INPUTS A2,A1 6 | MUX_NAME A_ADDER_MUX 7 | SPLIT_INPUTS 1 8 | TYPE logic 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_ad_preadder/acout_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME acout_mux 3 | COMMENT "DSP48E1 ac output mux" 4 | DATA_WIDTH 30 5 | MUX_NAME ACOUT_MUX 6 | SPLIT_INPUTS 1 7 | TYPE routing 8 | WIDTH 2 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_ad_preadder/ain_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME ain_mux 3 | COMMENT "DSP48E1 a input mux" 4 | DATA_WIDTH 30 5 | INPUTS A,ACIN 6 | MUX_NAME AIN_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_ad_preadder/amult_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME amult_mux 3 | COMMENT "DSP48E1 mux that select output to feed forward to A multipler" 4 | DATA_WIDTH 25 5 | INPUTS A,ADDER_OUT 6 | MUX_NAME AMULT_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_ad_preadder/amux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME areg_mux 3 | COMMENT "DSP48E1 a register mux" 4 | DATA_WIDTH 30 5 | INPUTS BYPASS,REG 6 | MUX_NAME AREG_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_ad_preadder/dmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME dreg_mux 3 | COMMENT "DSP48E1 D register mux" 4 | DATA_WIDTH 25 5 | INPUTS BYPASS,REG 6 | MUX_NAME DREG_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_b_reg/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(b1reg_mux) 2 | add_subdirectory(b2reg_mux) 3 | add_subdirectory(bc_mux) 4 | add_subdirectory(bin_mux) 5 | add_subdirectory(bmult_mux) 6 | add_file_target(FILE dual_b_reg.sim.v SCANNER_TYPE verilog) 7 | v2x(NAME dual_b_reg SRCS dual_b_reg.sim.v) 8 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_b_reg/b1reg_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME b1reg_mux 3 | COMMENT "DSP48E1 b1 register bypass mux" 4 | DATA_WIDTH 18 5 | INPUTS BYPASS,REG 6 | MUX_NAME B1REG_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_b_reg/b2reg_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME b2reg_mux 3 | COMMENT "DSP48E1 b2 register bypass mux" 4 | DATA_WIDTH 18 5 | INPUTS BYPASS,REG 6 | MUX_NAME B2REG_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_b_reg/bc_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME bc_mux 3 | COMMENT "DSP48E1 BC out mux" 4 | DATA_WIDTH 18 5 | INPUTS B1REG,B2 6 | MUX_NAME BC_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_b_reg/bin_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME bin_mux 3 | COMMENT "DSP48E1 B input mux" 4 | DATA_WIDTH 18 5 | INPUTS B,BCIN 6 | MUX_NAME BIN_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/dual_b_reg/bmult_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME bmult_mux 3 | COMMENT "DSP48E1 b multiplier output mux" 4 | DATA_WIDTH 18 5 | INPUTS B2,B1REG 6 | MUX_NAME BMULT_MUX 7 | SPLIT_INPUTS 1 8 | TYPE logic 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/inmode_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME inmode_mux 3 | COMMENT "DSP48E1 INMODE mux" 4 | DATA_WIDTH 5 5 | INPUTS BYPASS,REG 6 | MUX_NAME INMODE_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/mult25x18/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE mult25x18.sim.v SCANNER_TYPE verilog) 2 | v2x(NAME mult25x18 SRCS mult25x18.sim.v) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/mult_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME mult_mux 3 | COMMENT "DSP48E1 MREG mux" 4 | DATA_WIDTH 86 5 | INPUTS BYPASS,REG 6 | MUX_NAME MULT_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/nreg/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE reg.sim.v SCANNER_TYPE verilog) 2 | v2x(NAME reg SRCS reg.sim.v) 3 | add_file_target(FILE nreg.sim.v SCANNER_TYPE verilog) 4 | v2x(NAME nreg SRCS nreg.sim.v) 5 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/opmode_mux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME opmode_mux 3 | COMMENT "DSP48E1 OPMODE mux" 4 | DATA_WIDTH 7 5 | INPUTS BYPASS,REG 6 | MUX_NAME OPMODE_MUX 7 | SPLIT_INPUTS 1 8 | TYPE routing 9 | WIDTH 2 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/xmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME dsp48_xmux 3 | COMMENT "DSP48E1 Xmux" 4 | DATA_WIDTH 48 5 | INPUTS ZEROS,M,P,AB_CAT 6 | MUX_NAME DSP48_XMUX 7 | SPLIT_INPUTS 1 8 | TYPE logic 9 | WIDTH 4 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/ymux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME dsp48_ymux 3 | COMMENT "DSP48E1 Ymux" 4 | DATA_WIDTH 48 5 | INPUTS ZEROS,M,ONES,C 6 | MUX_NAME DSP48_YMUX 7 | SPLIT_INPUTS 1 8 | TYPE logic 9 | WIDTH 4 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/dsp48e1/zmux/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | mux_gen( 2 | NAME dsp48_zmux 3 | COMMENT "DSP48E1 Zmux" 4 | DATA_WIDTH 48 5 | INPUTS ZEROS,PCIN,P,C,P2,PCIN_UPSHIFT,P_UPSHIFT 6 | MUX_NAME DSP48_ZMUX 7 | SPLIT_INPUTS 1 8 | TYPE logic 9 | WIDTH 7 10 | ) 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/ff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ff.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ff.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/gtpe2_channel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE gtpe2_channel.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE gtpe2_channel.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/gtpe2_common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE gtpe2_common.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE gtpe2_common.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/ibufds_gte2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ibufds_gte2.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ibufds_gte2.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/ibufds_gte2/ibufds_gte2.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /xilinx/common/primitives/idelayctrl/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE idelayctrl.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE idelayctrl.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/idelayctrl/idelayctrl.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /xilinx/common/primitives/idelayctrl/idelayctrl.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /xilinx/common/primitives/idelaye2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE idelaye2.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE idelaye2.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/ilogice3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ilogice3.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ilogice3.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/iob33/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE inpad.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE outpad.pb_type.xml SCANNER_TYPE xml) 3 | 4 | add_subdirectory("modes") 5 | 6 | add_file_target(FILE iob33.pb_type.xml SCANNER_TYPE xml) 7 | add_file_target(FILE iob33.model.xml SCANNER_TYPE xml) 8 | -------------------------------------------------------------------------------- /xilinx/common/primitives/iob33/inpad.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | bel 5 | input 6 | 7 | 8 | -------------------------------------------------------------------------------- /xilinx/common/primitives/iob33/modes/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE no_ibuf.xml SCANNER_TYPE xml) 2 | add_file_target(FILE no_obuf.xml SCANNER_TYPE xml) 3 | add_file_target(FILE ibuf.xml SCANNER_TYPE xml) 4 | add_file_target(FILE obuft.xml SCANNER_TYPE xml) 5 | add_file_target(FILE iobuf.xml SCANNER_TYPE xml) 6 | -------------------------------------------------------------------------------- /xilinx/common/primitives/iob33/outpad.pb_type.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | bel 5 | output 6 | 7 | 8 | -------------------------------------------------------------------------------- /xilinx/common/primitives/iob33m/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE iob33m.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE iob33m.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/iob33s/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE iob33s.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE iob33s.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/ipad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ipad.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ipad.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/ipad/ipad.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/mmcme2_adv/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE mmcme2_adv.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE mmcme2_adv.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/ologice3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ologice3.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ologice3.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/opad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE opad.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE opad.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/opad/opad.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /xilinx/common/primitives/pcie_2_1/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE pcie_2_1.model.xml SCANNER_TYPE xml) 2 | add_file_target(FILE pcie_2_1.pb_type.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/plle2_adv/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE plle2_adv.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE plle2_adv.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/ps7/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE ps7.pb_type.xml SCANNER_TYPE xml) 2 | add_file_target(FILE ps7.model.xml SCANNER_TYPE xml) 3 | -------------------------------------------------------------------------------- /xilinx/common/primitives/slicel/ntemplate.slicelN.model.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /xilinx/common/primitives/slicem/di64_stub.sim.v: -------------------------------------------------------------------------------- 1 | // Simple passthrough box to for DI mux selection on dual port DRAMs. 2 | (* lib_whitebox *) 3 | module DI64_STUB( 4 | input DI, 5 | output DO 6 | ); 7 | (* DELAY_CONST_DI="0" *) 8 | wire DO; 9 | 10 | assign DO = DI; 11 | endmodule 12 | -------------------------------------------------------------------------------- /xilinx/common/primitives/tieoff/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target( 2 | FILE tieoff.sim.v 3 | SCANNER_TYPE verilog 4 | ) 5 | v2x( 6 | NAME tieoff 7 | SRCS tieoff.sim.v 8 | ) 9 | -------------------------------------------------------------------------------- /xilinx/common/primitives/tieoff/tieoff.sim.v: -------------------------------------------------------------------------------- 1 | (* whitebox *) 2 | module TIEOFF( 3 | HARD0, HARD1 4 | ); 5 | output wire HARD0; 6 | output wire HARD1; 7 | 8 | assign HARD0 = 0; 9 | assign HARD1 = 1; 10 | endmodule 11 | -------------------------------------------------------------------------------- /xilinx/common/utils/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE "add_pack_patterns.py") 2 | -------------------------------------------------------------------------------- /xilinx/common/utils/output_timing.tcl: -------------------------------------------------------------------------------- 1 | set timing_utils [lindex $argv 0] 2 | set timing_json [lindex $argv 1] 3 | 4 | source $timing_utils 5 | output_timing $timing_json 6 | -------------------------------------------------------------------------------- /xilinx/xc7/arch.cmake: -------------------------------------------------------------------------------- 1 | add_subdirectory(archs) 2 | include(boards.cmake) 3 | add_subdirectory(tests) 4 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(artix7) 2 | add_subdirectory(artix7_100t) 3 | add_subdirectory(artix7_200t) 4 | add_subdirectory(zynq7) 5 | add_subdirectory(zynq7_z020) 6 | add_subdirectory(spartan7) 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/devices/xc7a50t-arty-swbut-roi-virt/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define_type( 2 | ARCH artix7 3 | DEVICE xc7a50t-arty-swbut 4 | ROI_DIR ${PRJXRAY_DB_DIR}/artix7/harness/arty-a7/swbut 5 | TILE_TYPES 6 | CLBLL_L 7 | CLBLL_R 8 | CLBLM_L 9 | CLBLM_R 10 | BRAM_L 11 | PB_TYPES 12 | SLICEL 13 | SLICEM 14 | BRAM_L 15 | ) 16 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/devices/xc7a50t-arty-uart-roi-virt/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define_type( 2 | ARCH artix7 3 | DEVICE xc7a50t-arty-uart 4 | ROI_DIR ${PRJXRAY_DB_DIR}/artix7/harness/arty-a7/uart 5 | TILE_TYPES 6 | CLBLL_L 7 | CLBLL_R 8 | CLBLM_L 9 | CLBLM_R 10 | BRAM_L 11 | PB_TYPES 12 | SLICEL 13 | SLICEM 14 | BRAM_L 15 | ) 16 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/devices/xc7a50t-basys3-roi-virt/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define_type( 2 | ARCH artix7 3 | DEVICE xc7a50t-basys3 4 | ROI_DIR ${PRJXRAY_DB_DIR}/artix7/harness/basys3/swbut 5 | TILE_TYPES 6 | CLBLL_L 7 | CLBLL_R 8 | CLBLM_L 9 | CLBLM_R 10 | BRAM_L 11 | PB_TYPES 12 | SLICEL 13 | SLICEM 14 | BRAM_L 15 | ) 16 | 17 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/bram_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE BRAM_L 4 | SITE_TYPES BRAM_L/BRAM_L 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_L 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/bram_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE BRAM_R 4 | SITE_TYPES BRAM_R/BRAM_R 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_R 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/clbll_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE CLBLL_L 4 | SITE_TYPES SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/clbll_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE CLBLL_R 4 | SITE_TYPES SLICEL 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/clblm_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE CLBLM_L 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/clblm_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE CLBLM_R 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/clk_bufg_bot_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE CLK_BUFG_BOT_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/clk_bufg_top_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE CLK_BUFG_TOP_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/cmt_top_l_lower_b/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE CMT_TOP_L_LOWER_B 4 | SITE_TYPES MMCME2_ADV 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/cmt_top_l_upper_t/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE CMT_TOP_L_UPPER_T 4 | SITE_TYPES PLLE2_ADV/PLLE2_ADV 5 | EQUIVALENT_SITES CMT_TOP_L_UPPER_T 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/cmt_top_r_lower_b/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE CMT_TOP_R_LOWER_B 4 | SITE_TYPES MMCME2_ADV 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/cmt_top_r_upper_t/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE CMT_TOP_R_UPPER_T 4 | SITE_TYPES PLLE2_ADV/PLLE2_ADV 5 | EQUIVALENT_SITES CMT_TOP_R_UPPER_T 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/gtp_channel_0/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE GTP_CHANNEL_0 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/gtp_channel_1/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE GTP_CHANNEL_1 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/gtp_channel_2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE GTP_CHANNEL_2 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/gtp_channel_3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE GTP_CHANNEL_3 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/gtp_common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7 3 | TILE GTP_COMMON 4 | SITE_TYPES GTPE2_COMMON IBUFDS_GTE2 IPAD 5 | UNUSED_WIRES GTEASTREFCLK0 GTEASTREFCLK1 GTWESTREFCLK0 GTWESTREFCLK1 6 | ) 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/gtpe2_channel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE GTPE2_CHANNEL 4 | SITE_AS_TILE 5 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL 6 | EQUIVALENT_SITES GTPE2_CHANNEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/gtpe2_common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE GTPE2_COMMON 4 | SITE_AS_TILE 5 | SITE_TYPES GTPE2_COMMON/GTPE2_COMMON 6 | EQUIVALENT_SITES GTPE2_COMMON 7 | UNUSED_WIRES GTEASTREFCLK0 GTEASTREFCLK1 GTWESTREFCLK0 GTWESTREFCLK1 8 | ) 9 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/hclk_ioi3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE HCLK_IOI3 4 | SITE_TYPES IDELAYCTRL/IDELAYCTRL 5 | EQUIVALENT_SITES HCLK_IOI3 6 | SITE_COORDS Y 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/ibufds_gte2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE IBUFDS_GTE2 4 | SITE_AS_TILE 5 | SITE_TYPES IBUFDS_GTE2/IBUFDS_GTE2 6 | EQUIVALENT_SITES IBUFDS_GTE2 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/int_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE INT_L 4 | SITE_TYPES TIEOFF/TIEOFF 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/int_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE INT_R 4 | SITE_TYPES TIEOFF/TIEOFF 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/ipad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE IPAD 4 | SITE_AS_TILE 5 | SITE_TYPES IPAD/IPAD 6 | EQUIVALENT_SITES IPAD 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/liob33_sing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE LIOB33_SING 4 | SITE_TYPES IOB33 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/mmcme2_adv/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE MMCME2_ADV 4 | SITE_AS_TILE 5 | SITE_TYPES MMCME2_ADV/MMCME2_ADV 6 | EQUIVALENT_SITES MMCME2_ADV 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/opad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE OPAD 4 | SITE_AS_TILE 5 | SITE_TYPES OPAD/OPAD 6 | EQUIVALENT_SITES OPAD 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/riopad_m/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE RIOPAD_M 4 | SITE_TYPES IOB33M/IOB33M ILOGICE3/ILOGICE3 OLOGICE3/OLOGICE3 IDELAYE2/IDELAYE2 5 | USE_DATABASE 6 | EQUIVALENT_SITES RIOPAD_M 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/slicel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE SLICEL 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEL/SLICEL0 6 | EQUIVALENT_SITES SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7/tiles/slicem/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7 3 | TILE SLICEM 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEM/SLICEM 6 | EQUIVALENT_SITES SLICEM SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/devices/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define( 2 | ARCH artix7_100t 3 | PART xc7a100tfgg676-1 4 | DEVICES xc7a100t 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/bram_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE BRAM_L 4 | SITE_TYPES BRAM_L/BRAM_L 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_L 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/bram_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE BRAM_R 4 | SITE_TYPES BRAM_R/BRAM_R 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_R 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/clbll_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE CLBLL_L 4 | SITE_TYPES SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/clbll_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE CLBLL_R 4 | SITE_TYPES SLICEL 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/clblm_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE CLBLM_L 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/clblm_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE CLBLM_R 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/clk_bufg_bot_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE CLK_BUFG_BOT_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/clk_bufg_top_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE CLK_BUFG_TOP_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/cmt_top_l_upper_t/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE CMT_TOP_L_UPPER_T 4 | SITE_TYPES PLLE2_ADV/PLLE2_ADV 5 | EQUIVALENT_SITES CMT_TOP_L_UPPER_T 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/cmt_top_r_upper_t/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE CMT_TOP_R_UPPER_T 4 | SITE_TYPES PLLE2_ADV/PLLE2_ADV 5 | EQUIVALENT_SITES CMT_TOP_R_UPPER_T 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/gtp_channel_0/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE GTP_CHANNEL_0 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/gtp_channel_1/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE GTP_CHANNEL_1 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/gtp_channel_2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE GTP_CHANNEL_2 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/gtp_channel_3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE GTP_CHANNEL_3 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/gtp_common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_100t 3 | TILE GTP_COMMON 4 | SITE_TYPES GTPE2_COMMON IBUFDS_GTE2 IPAD 5 | UNUSED_WIRES GTEASTREFCLK0 GTEASTREFCLK1 GTWESTREFCLK0 GTWESTREFCLK1 6 | ) 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/gtpe2_channel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE GTPE2_CHANNEL 4 | SITE_AS_TILE 5 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL 6 | EQUIVALENT_SITES GTPE2_CHANNEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/gtpe2_common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE GTPE2_COMMON 4 | SITE_AS_TILE 5 | SITE_TYPES GTPE2_COMMON/GTPE2_COMMON 6 | EQUIVALENT_SITES GTPE2_COMMON 7 | UNUSED_WIRES GTEASTREFCLK0 GTEASTREFCLK1 GTWESTREFCLK0 GTWESTREFCLK1 8 | ) 9 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/hclk_ioi3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE HCLK_IOI3 4 | SITE_TYPES IDELAYCTRL/IDELAYCTRL 5 | EQUIVALENT_SITES HCLK_IOI3 6 | SITE_COORDS Y 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/ibufds_gte2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE IBUFDS_GTE2 4 | SITE_AS_TILE 5 | SITE_TYPES IBUFDS_GTE2/IBUFDS_GTE2 6 | EQUIVALENT_SITES IBUFDS_GTE2 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/ipad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE IPAD 4 | SITE_AS_TILE 5 | SITE_TYPES IPAD/IPAD 6 | EQUIVALENT_SITES IPAD 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/liob33_sing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE LIOB33_SING 4 | SITE_TYPES IOB33 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/opad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE OPAD 4 | SITE_AS_TILE 5 | SITE_TYPES OPAD/OPAD 6 | EQUIVALENT_SITES OPAD 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/riopad_m/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE RIOPAD_M 4 | SITE_TYPES IOB33M/IOB33M ILOGICE3/ILOGICE3 OLOGICE3/OLOGICE3 IDELAYE2/IDELAYE2 5 | USE_DATABASE 6 | EQUIVALENT_SITES RIOPAD_M 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/slicel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE SLICEL 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEL/SLICEL0 6 | EQUIVALENT_SITES SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_100t/tiles/slicem/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_100t 3 | TILE SLICEM 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEM/SLICEM 6 | EQUIVALENT_SITES SLICEM SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/devices/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define( 2 | ARCH artix7_200t 3 | PART xc7a200tffg1156-1 4 | DEVICES xc7a200t xc7a200t-mid 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/bram_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE BRAM_L 4 | SITE_TYPES BRAM_L/BRAM_L 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_L 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/bram_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE BRAM_R 4 | SITE_TYPES BRAM_R/BRAM_R 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_R 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/clbll_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE CLBLL_L 4 | SITE_TYPES SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/clbll_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE CLBLL_R 4 | SITE_TYPES SLICEL 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/clblm_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE CLBLM_L 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/clblm_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE CLBLM_R 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/clk_bufg_bot_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE CLK_BUFG_BOT_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/clk_bufg_top_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE CLK_BUFG_TOP_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_channel_0_mid_left/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_CHANNEL_0_MID_LEFT 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_channel_0_mid_right/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_CHANNEL_0_MID_RIGHT 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_channel_1_mid_left/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_CHANNEL_1_MID_LEFT 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_channel_1_mid_right/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_CHANNEL_1_MID_RIGHT 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_channel_2_mid_left/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_CHANNEL_2_MID_LEFT 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_channel_2_mid_right/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_CHANNEL_2_MID_RIGHT 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_channel_3_mid_left/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_CHANNEL_3_MID_LEFT 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_channel_3_mid_right/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_CHANNEL_3_MID_RIGHT 4 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL IPAD/IPAD OPAD/OPAD 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_common_mid_left/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_COMMON_MID_LEFT 4 | SITE_TYPES GTPE2_COMMON IBUFDS_GTE2 IPAD 5 | UNUSED_WIRES GTEASTREFCLK0 GTEASTREFCLK1 GTWESTREFCLK0 GTWESTREFCLK1 6 | ) 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtp_common_mid_right/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH artix7_200t 3 | TILE GTP_COMMON_MID_RIGHT 4 | SITE_TYPES GTPE2_COMMON IBUFDS_GTE2 IPAD 5 | UNUSED_WIRES GTEASTREFCLK0 GTEASTREFCLK1 GTWESTREFCLK0 GTWESTREFCLK1 6 | ) 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtpe2_channel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE GTPE2_CHANNEL 4 | SITE_AS_TILE 5 | SITE_TYPES GTPE2_CHANNEL/GTPE2_CHANNEL 6 | EQUIVALENT_SITES GTPE2_CHANNEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/gtpe2_common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE GTPE2_COMMON 4 | SITE_AS_TILE 5 | SITE_TYPES GTPE2_COMMON/GTPE2_COMMON 6 | EQUIVALENT_SITES GTPE2_COMMON 7 | UNUSED_WIRES GTEASTREFCLK0 GTEASTREFCLK1 GTWESTREFCLK0 GTWESTREFCLK1 8 | ) 9 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/hclk_ioi3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE HCLK_IOI3 4 | SITE_TYPES IDELAYCTRL/IDELAYCTRL 5 | EQUIVALENT_SITES HCLK_IOI3 6 | SITE_COORDS Y 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/ibufds_gte2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE IBUFDS_GTE2 4 | SITE_AS_TILE 5 | SITE_TYPES IBUFDS_GTE2/IBUFDS_GTE2 6 | EQUIVALENT_SITES IBUFDS_GTE2 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/ipad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE IPAD 4 | SITE_AS_TILE 5 | SITE_TYPES IPAD/IPAD 6 | EQUIVALENT_SITES IPAD 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/opad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE OPAD 4 | SITE_AS_TILE 5 | SITE_TYPES OPAD/OPAD 6 | EQUIVALENT_SITES OPAD 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/slicel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE SLICEL 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEL/SLICEL0 6 | EQUIVALENT_SITES SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/artix7_200t/tiles/slicem/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH artix7_200t 3 | TILE SLICEM 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEM/SLICEM 6 | EQUIVALENT_SITES SLICEM SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/devices/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define( 2 | ARCH spartan7 3 | PART xc7s50fgga484-1 4 | DEVICES xc7s50 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/bram_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH spartan7 3 | TILE BRAM_L 4 | SITE_TYPES BRAM_L/BRAM_L 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_L 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/bram_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH spartan7 3 | TILE BRAM_R 4 | SITE_TYPES BRAM_R/BRAM_R 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_R 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/clbll_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH spartan7 3 | TILE CLBLL_L 4 | SITE_TYPES SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/clbll_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH spartan7 3 | TILE CLBLL_R 4 | SITE_TYPES SLICEL 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/clblm_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH spartan7 3 | TILE CLBLM_L 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/clblm_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH spartan7 3 | TILE CLBLM_R 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/clk_bufg_bot_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH spartan7 3 | TILE CLK_BUFG_BOT_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/clk_bufg_top_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH spartan7 3 | TILE CLK_BUFG_TOP_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/cmt_top_l_lower_b/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH spartan7 3 | TILE CMT_TOP_L_LOWER_B 4 | SITE_TYPES MMCME2_ADV 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/cmt_top_r_lower_b/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH spartan7 3 | TILE CMT_TOP_R_LOWER_B 4 | SITE_TYPES MMCME2_ADV 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/hclk_ioi3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH spartan7 3 | TILE HCLK_IOI3 4 | SITE_TYPES IDELAYCTRL/IDELAYCTRL 5 | EQUIVALENT_SITES HCLK_IOI3 6 | SITE_COORDS Y 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/mmcme2_adv/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH spartan7 3 | TILE MMCME2_ADV 4 | SITE_AS_TILE 5 | SITE_TYPES MMCME2_ADV/MMCME2_ADV 6 | EQUIVALENT_SITES MMCME2_ADV 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/slicel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH spartan7 3 | TILE SLICEL 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEL/SLICEL0 6 | EQUIVALENT_SITES SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/spartan7/tiles/slicem/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH spartan7 3 | TILE SLICEM 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEM/SLICEM 6 | EQUIVALENT_SITES SLICEM SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/devices/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define( 2 | ARCH zynq7 3 | PART xc7z010clg400-1 4 | DEVICES xc7z010-zybo 5 | USE_ROI 6 | ) 7 | 8 | add_xc_device_define( 9 | ARCH zynq7 10 | PART xc7z010clg400-1 11 | DEVICES xc7z010 12 | ) 13 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/devices/xc7z010-zybo-roi-virt/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define_type( 2 | ARCH zynq7 3 | DEVICE xc7z010-zybo 4 | ROI_DIR ${PRJXRAY_DB_DIR}/zynq7/harness/zybo/swbut 5 | TILE_TYPES 6 | CLBLL_L 7 | CLBLL_R 8 | CLBLM_L 9 | CLBLM_R 10 | BRAM_L 11 | PB_TYPES 12 | SLICEL 13 | SLICEM 14 | BRAM_L 15 | ) 16 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/bram_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE BRAM_L 4 | SITE_TYPES BRAM_L/BRAM_L 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_L 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/bram_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE BRAM_R 4 | SITE_TYPES BRAM_R/BRAM_R 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_R 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/clbll_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7 3 | TILE CLBLL_L 4 | SITE_TYPES SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/clbll_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7 3 | TILE CLBLL_R 4 | SITE_TYPES SLICEL 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/clblm_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7 3 | TILE CLBLM_L 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/clblm_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7 3 | TILE CLBLM_R 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/clk_bufg_bot_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7 3 | TILE CLK_BUFG_BOT_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/clk_bufg_top_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7 3 | TILE CLK_BUFG_TOP_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/cmt_top_l_upper_t/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_xray_tile( 2 | PART zynq7 3 | TILE CMT_TOP_L_UPPER_T 4 | SITE_TYPES PLLE2_ADV/PLLE2_ADV 5 | EQUIVALENT_SITES CMT_TOP_L_UPPER_T 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/cmt_top_r_upper_t/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_xray_tile( 2 | PART zynq7 3 | TILE CMT_TOP_R_UPPER_T 4 | SITE_TYPES PLLE2_ADV/PLLE2_ADV 5 | EQUIVALENT_SITES CMT_TOP_R_UPPER_T 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/hclk_ioi3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE HCLK_IOI3 4 | SITE_TYPES IDELAYCTRL/IDELAYCTRL 5 | EQUIVALENT_SITES HCLK_IOI3 6 | SITE_COORDS Y 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/int_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE INT_L 4 | SITE_TYPES TIEOFF/TIEOFF 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/int_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE INT_R 4 | SITE_TYPES TIEOFF/TIEOFF 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/liob33_sing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE LIOB33_SING 4 | SITE_TYPES IOB33 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/pss2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE PSS2 4 | SITE_TYPES PS7/PS7 5 | EQUIVALENT_SITES PSS2 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/slicel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE SLICEL 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEL/SLICEL0 6 | EQUIVALENT_SITES SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7/tiles/slicem/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7 3 | TILE SLICEM 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEM/SLICEM 6 | EQUIVALENT_SITES SLICEM SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/devices/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_xc_device_define( 2 | ARCH zynq7_z020 3 | PART xc7z020clg484-1 4 | DEVICES xc7z020 5 | ) 6 | 7 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/bram_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE BRAM_L 4 | SITE_TYPES BRAM_L/BRAM_L 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_L 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/bram_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE BRAM_R 4 | SITE_TYPES BRAM_R/BRAM_R 5 | FUSED_SITES 6 | EQUIVALENT_SITES BRAM_R 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/clbll_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7_z020 3 | TILE CLBLL_L 4 | SITE_TYPES SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/clbll_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7_z020 3 | TILE CLBLL_R 4 | SITE_TYPES SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/clblm_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7_z020 3 | TILE CLBLM_L 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/clblm_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7_z020 3 | TILE CLBLM_R 4 | SITE_TYPES SLICEM/SLICEL SLICEL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/clk_bufg_bot_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7_z020 3 | TILE CLK_BUFG_BOT_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/clk_bufg_top_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile_capacity( 2 | ARCH zynq7_z020 3 | TILE CLK_BUFG_TOP_R 4 | SITE_TYPES BUFGCTRL 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/cmt_top_l_upper_t/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_xray_tile( 2 | PART zynq7_z020 3 | TILE CMT_TOP_L_UPPER_T 4 | SITE_TYPES PLLE2_ADV/PLLE2_ADV 5 | EQUIVALENT_SITES CMT_TOP_L_UPPER_T 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/cmt_top_r_upper_t/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_xray_tile( 2 | PART zynq7_z020 3 | TILE CMT_TOP_R_UPPER_T 4 | SITE_TYPES PLLE2_ADV/PLLE2_ADV 5 | EQUIVALENT_SITES CMT_TOP_R_UPPER_T 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/hclk_ioi3/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE HCLK_IOI3 4 | SITE_TYPES IDELAYCTRL/IDELAYCTRL 5 | EQUIVALENT_SITES HCLK_IOI3 6 | SITE_COORDS Y 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/int_l/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE INT_L 4 | SITE_TYPES TIEOFF/TIEOFF 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/int_r/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE INT_R 4 | SITE_TYPES TIEOFF/TIEOFF 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/liob33_sing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE LIOB33_SING 4 | SITE_TYPES IOB33 5 | ) 6 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/pss2/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE PSS2 4 | SITE_TYPES PS7/PS7 5 | EQUIVALENT_SITES PSS2 6 | NO_FASM_PREFIX 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/slicel/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE SLICEL 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEL/SLICEL0 6 | EQUIVALENT_SITES SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/archs/zynq7_z020/tiles/slicem/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project_ray_tile( 2 | ARCH zynq7_z020 3 | TILE SLICEM 4 | SITE_AS_TILE 5 | SITE_TYPES SLICEM/SLICEM 6 | EQUIVALENT_SITES SLICEM SLICEL 7 | ) 8 | -------------------------------------------------------------------------------- /xilinx/xc7/empty.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /xilinx/xc7/techmap/retarget.v: -------------------------------------------------------------------------------- 1 | module FD (output reg Q, input C, D); 2 | 3 | parameter [0:0] INIT = 1'b0; 4 | 5 | FDRE #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Q(Q), .C(C), .D(D), .CE(1'b1), .R(1'b0)); 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/bram/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE bram.v SCANNER_TYPE verilog) 2 | 3 | add_fpga_target( 4 | NAME bram 5 | BOARD basys3 6 | INPUT_IO_FILE ${COMMON}/basys3.pcf 7 | SOURCES bram.v 8 | EXPLICIT_ADD_FILE_TARGET 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/bufgmux/arty.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN E3 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | set_property PACKAGE_PIN H5 [get_ports led] 4 | set_property IOSTANDARD LVCMOS33 [get_ports led] 5 | set_property PACKAGE_PIN A8 [get_ports sw] 6 | set_property IOSTANDARD LVCMOS33 [get_ports sw] 7 | 8 | create_clock -period 10.0 clk 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/bufgmux/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN R4 [get_ports clk] 2 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 3 | set_property PACKAGE_PIN T14 [get_ports led] 4 | set_property IOSTANDARD LVCMOS25 [get_ports led] 5 | set_property PACKAGE_PIN E22 [get_ports sw] 6 | set_property IOSTANDARD LVCMOS12 [get_ports sw] 7 | 8 | create_clock -period 10.0 clk 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_arty.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | 4 | input wire [7:0] sw, 5 | output wire [7:0] led, 6 | ); 7 | assign led = sw; 8 | endmodule 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_arty_rev.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | 4 | input wire [7:0] sw, 5 | output wire [0:7] led, 6 | ); 7 | assign led = sw; 8 | endmodule 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_ax7050.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module top ( 3 | 4 | input wire [1:0] sw, 5 | output wire [1:0] led, 6 | ); 7 | assign led = sw; 8 | endmodule 9 | 10 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_basys3.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | 4 | input wire rx, 5 | output wire tx, 6 | 7 | input wire [15:0] sw, 8 | output wire [15:0] led 9 | ); 10 | assign led = sw; 11 | 12 | // uart loopback 13 | assign tx = rx; 14 | endmodule 15 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_basys3_full.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | 4 | input wire [15:0] sw, 5 | output wire [15:0] led, 6 | 7 | input wire rx, 8 | output wire tx 9 | ); 10 | 11 | assign led = sw; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_marszx3.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | 4 | output [3:0] wire led 5 | ); 6 | assign led = 4'b1010; 7 | endmodule 8 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_nexys_video.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | 4 | input wire [7:0] sw, 5 | output wire [7:0] led, 6 | 7 | input wire rx, 8 | output wire tx 9 | ); 10 | assign led = sw; 11 | endmodule 12 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_zedboard.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | 4 | input wire [7:0] sw, 5 | output wire [7:0] led 6 | ); 7 | assign led = sw; 8 | endmodule 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/buttons/buttons_zybo.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | 4 | input wire [2:0] sw, 5 | output wire [3:0] led 6 | ); 7 | assign led[2:0] = sw; 8 | endmodule 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/carry/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE carry.v SCANNER_TYPE verilog) 2 | add_fpga_target( 3 | NAME carry_basys3 4 | BOARD basys3 5 | INPUT_IO_FILE ${COMMON}/basys3.pcf 6 | SOURCES carry.v 7 | EXPLICIT_ADD_FILE_TARGET 8 | ) 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/carry/carry.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input wire clk, 3 | 4 | input wire rx, 5 | output wire tx, 6 | 7 | input wire [15:0] sw, 8 | output wire [15:0] led 9 | ); 10 | assign led = sw; 11 | 12 | // Uart loopback 13 | assign tx = rx; 14 | endmodule 15 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/chain_packing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE counter.v SCANNER_TYPE verilog) 2 | add_fpga_target_boards( 3 | NAME chain_packing 4 | BOARDS basys3-full 5 | INPUT_IO_FILE ${COMMON}/basys3.pcf 6 | SOURCES counter.v 7 | EXPLICIT_ADD_FILE_TARGET 8 | ) 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/common/arty_switch_processing_pr1.pcf: -------------------------------------------------------------------------------- 1 | set_io clk SYN0 2 | 3 | set_io rst SYN9 4 | 5 | set_io in[0] SYN1 6 | set_io in[1] SYN2 7 | set_io in[2] SYN3 8 | set_io in[3] SYN4 9 | 10 | set_io out[0] SYN5 11 | set_io out[1] SYN6 12 | set_io out[2] SYN7 13 | set_io out[3] SYN8 14 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/common/arty_switch_processing_pr2.pcf: -------------------------------------------------------------------------------- 1 | set_io clk SYN0 2 | 3 | set_io rst SYN9 4 | 5 | set_io in[0] SYN1 6 | set_io in[1] SYN2 7 | set_io in[2] SYN3 8 | set_io in[3] SYN4 9 | 10 | set_io out[0] SYN5 11 | set_io out[1] SYN6 12 | set_io out[2] SYN7 13 | set_io out[3] SYN8 14 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/common/arty_uart.pcf: -------------------------------------------------------------------------------- 1 | # clk 2 | set_io clk E3 3 | 4 | # reset button 5 | set_io rst C2 6 | 7 | # led corresponds to LD7 in arty. 8 | set_io led T10 9 | 10 | # tx and rx are serial transmitter and receiver 11 | set_io rx A9 12 | set_io tx D10 13 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/common/basys3.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10 clk 2 | 3 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/common/basys3.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.0 clk 2 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/common/marszx3.pcf: -------------------------------------------------------------------------------- 1 | # Mars-ZX3 33 MHz CLK 2 | set_io clk Y6 3 | 4 | # Outputs: led[3:0] 5 | set_io led[0] H18 6 | set_io led[1] AA14 7 | set_io led[2] AA13 8 | set_io led[3] AB15 9 | 10 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/common/zybo.pcf: -------------------------------------------------------------------------------- 1 | # 125MHz clk 2 | set_io clk K17 3 | 4 | # in[] correspond with SW0-SW3 on the zybo 5 | set_io sw[0] G15 6 | set_io sw[1] K18 7 | set_io sw[2] K19 8 | 9 | # out[] correspond with LD0-LD3 on the zybo 10 | set_io led[0] M14 11 | set_io led[1] M15 12 | set_io led[2] G14 13 | set_io led[3] D18 14 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/common/zybo_z7.pcf: -------------------------------------------------------------------------------- 1 | # 125MHz clk 2 | set_io clk K17 3 | 4 | # in[] correspond with SW0-SW3 on the zybo 5 | set_io sw[0] G15 6 | set_io sw[1] P15 7 | set_io sw[2] W13 8 | set_io sw[3] T16 9 | 10 | # out[] correspond with LD0-LD3 on the zybo 11 | set_io led[0] M14 12 | set_io led[1] M15 13 | set_io led[2] G14 14 | set_io led[3] D18 15 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/counter/counter_marszx3.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | 4 | output wire [3:0] led 5 | ); 6 | 7 | localparam BITS = 8; 8 | localparam LOG2DELAY = 18; 9 | 10 | reg [BITS+LOG2DELAY-1:0] counter = 0; 11 | 12 | always @(posedge clk) begin 13 | counter <= counter + 1; 14 | end 15 | 16 | assign led = counter >> LOG2DELAY; 17 | endmodule 18 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/counter/counter_zedboard.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | 4 | input wire [7:0] sw, 5 | output wire [7:0] led 6 | ); 7 | 8 | localparam BITS = 8; 9 | localparam LOG2DELAY = 18; 10 | 11 | reg [BITS+LOG2DELAY-1:0] counter = 0; 12 | 13 | always @(posedge clk) begin 14 | counter <= counter + 1; 15 | end 16 | 17 | assign led = counter >> LOG2DELAY; 18 | endmodule 19 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/ddr/arty_clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk100 -period 10.0 [get_nets clk100] 2 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/ddr/mem.init: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/f4pga/f4pga-arch-defs/3d4df2ea79dca19b8c5c155e0396e84f52e50451/xilinx/xc7/tests/ddr/mem.init -------------------------------------------------------------------------------- /xilinx/xc7/tests/gclk_active/basys3.pcf: -------------------------------------------------------------------------------- 1 | set_io clk W5 2 | set_io out A14 3 | 4 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/gclk_active/gclk_through.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | output wire out 4 | ); 5 | 6 | // ============================================================================ 7 | 8 | wire clk_g; 9 | 10 | (* LOC="BUFGCTRL_X0Y0" *) 11 | BUFG bufg1 (.I(clk), .O(clk_g)); 12 | 13 | assign out = clk_g; 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/gtp_channel/basys3.xdc: -------------------------------------------------------------------------------- 1 | set_property LOC D2 [get_ports {tx_p}] 2 | set_property LOC D1 [get_ports {tx_n}] 3 | set_property LOC B4 [get_ports {rx_p}] 4 | set_property LOC A4 [get_ports {rx_n}] 5 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/gtp_channel/nexys_video.xdc: -------------------------------------------------------------------------------- 1 | set_property LOC D7 [get_ports {tx_p}] 2 | set_property LOC C7 [get_ports {tx_n}] 3 | set_property LOC D9 [get_ports {rx_p}] 4 | set_property LOC C9 [get_ports {rx_n}] 5 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/gtp_common/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_fpga_target( 2 | NAME gtp_common 3 | BOARD basys3-full 4 | INPUT_XDC_FILES basys3.xdc 5 | SOURCES gtp_common.v 6 | ) 7 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/gtp_common/basys3.xdc: -------------------------------------------------------------------------------- 1 | set_property LOC A8 [get_ports clk_n_0] 2 | set_property LOC B8 [get_ports clk_p_0] 3 | set_property LOC A10 [get_ports clk_n_1] 4 | set_property LOC B10 [get_ports clk_p_1] 5 | set_property LOC V17 [get_ports test_in] 6 | set_property LOC U16 [get_ports test_out] 7 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/idelayctrl/arty.pcf: -------------------------------------------------------------------------------- 1 | # 100 MHz CLK 2 | set_io clk E3 3 | 4 | # Reset 5 | set_io rst C2 6 | 7 | # LEDs 8 | set_io led[0] H5 9 | set_io led[1] J5 10 | set_io led[2] C6 11 | set_io led[3] G3 12 | set_io led[4] J3 13 | set_io led[5] K1 14 | set_io led[6] F6 15 | set_io led[7] J4 16 | set_io led[8] J2 17 | set_io led[9] H6 18 | 19 | # SWs 20 | set_io sw[0] A8 21 | set_io sw[1] R2 22 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/install_test/requirements.txt: -------------------------------------------------------------------------------- 1 | lxml 2 | simplejson 3 | intervaltree 4 | python-constraint 5 | git+https://github.com/symbiflow/fasm 6 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/iologic_packing/README.md: -------------------------------------------------------------------------------- 1 | # IOB + ILOGIC/OLOGIC test suite 2 | 3 | These test cases verifies SymbiFlow support for all possible (and legal) combinations of these elements. 4 | 5 | The tests are not intended to be run on a hardware (pinout is somewhat fake). For speedup the Basys3 (bottom graph) device target is used. 6 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/multixdc_counter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE arty_0.xdc) 2 | add_file_target(FILE arty_1.xdc) 3 | add_file_target(FILE arty_2.xdc) 4 | 5 | add_fpga_target( 6 | NAME multixdc_counter_arty 7 | BOARD arty-full 8 | SOURCES ${COUNTER_SRC}/counter_arty.v 9 | INPUT_XDC_FILES arty_0.xdc arty_1.xdc arty_2.xdc 10 | EXPLICIT_ADD_FILE_TARGET 11 | ) 12 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/multixdc_counter/README.md: -------------------------------------------------------------------------------- 1 | multixdc_counter test 2 | ===================== 3 | 4 | This test is intended to check multi-XDCs designs. 5 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/multixdc_counter/arty_0.xdc: -------------------------------------------------------------------------------- 1 | # clk 2 | set_property LOC E3 [get_ports {clk}] 3 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/obuf_packing/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE obuf_packing.v SCANNER_TYPE verilog) 2 | add_file_target(FILE dummy.pcf) 3 | 4 | add_fpga_target( 5 | NAME obuf_packing 6 | BOARD arty-full 7 | SOURCES obuf_packing.v 8 | INPUT_IO_FILE dummy.pcf 9 | EXPLICIT_ADD_FILE_TARGET 10 | ) 11 | 12 | add_vivado_target( 13 | NAME obuf_packing_vivado 14 | PARENT_NAME obuf_packing 15 | ) 16 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/obuf_packing/README.md: -------------------------------------------------------------------------------- 1 | # OBUF(T)(DS) packing test 2 | 3 | This is a test for packing and diff fasm for OBUF, OBUFT, OBUFDS and OBUFTDS. 4 | The pinout is fake - it's just for toolchain verification. 5 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/obufds/basys3.pcf: -------------------------------------------------------------------------------- 1 | set_io sw[8] V2 2 | set_io sw[9] T3 3 | set_io sw[10] T2 4 | set_io sw[11] R3 5 | 6 | set_io diff_p[0] U19 7 | set_io diff_n[0] V19 8 | set_io diff_p[1] V13 9 | set_io diff_n[1] V14 10 | 11 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/obuftds/basys3.pcf: -------------------------------------------------------------------------------- 1 | set_io sw[8] V2 2 | set_io sw[9] T3 3 | set_io sw[10] T2 4 | set_io sw[11] R3 5 | 6 | set_io diff_p[0] U19 7 | set_io diff_n[0] V19 8 | set_io diff_p[1] V13 9 | set_io diff_n[1] V14 10 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/oserdes_routing/dummy.pcf: -------------------------------------------------------------------------------- 1 | set_io clk1 M18 2 | set_io clk2 L17 3 | 4 | set_io i_d[0] L18 5 | set_io i_d[1] K18 6 | 7 | set_io i_t P19 8 | 9 | set_io out[0] U15 10 | set_io out[1] V13 11 | 12 | set_io o_d V19 13 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/pcie_complex/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_file_target(FILE pcie_complex.v SCANNER_TYPE verilog) 2 | 3 | add_fpga_target( 4 | NAME pcie_complex_netv2_a100t 5 | BOARD netv2-a100t 6 | INPUT_XDC_FILES ${COMMON}/netv2_a100t_pcie_complex.xdc 7 | SOURCES pcie_complex.v 8 | EXPLICIT_ADD_FILE_TARGET 9 | ) 10 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/pcie_complex/README.md: -------------------------------------------------------------------------------- 1 | PCIe complex test 2 | ================= 3 | 4 | This test is intended to check the correct P&R flow and bitstream generation 5 | for a design with GTP and PCIe blocks. 6 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/ps7/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(counter_emio) 2 | add_subdirectory(axi_lite_reg) 3 | 4 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/soc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(litex) 2 | add_subdirectory(ibex) 3 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/soc/ibex/pins_artya7.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.0 clkgen.io_clk_buf -waveform {0.000 5.000} 2 | create_clock -period 40.0 clkgen.clk_50_unbuf -waveform {0.000 20.000} 3 | create_clock -period 10.0 clkgen.clk_fb_unbuf -waveform {0.000 5.000} 4 | create_clock -period 40.0 clkgen.clk_sys -waveform {0.000 20.000} 5 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/soc/ibex/pins_nexys_video.pcf: -------------------------------------------------------------------------------- 1 | set_io IO_CLK R4 2 | set_io LED[0] T14 3 | set_io LED[1] T15 4 | set_io LED[2] T16 5 | set_io LED[3] U16 6 | set_io IO_RST_N G4 7 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/soc/ibex/pins_nexys_video.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.0 clkgen.io_clk_buf -waveform {0.000 5.000} 2 | create_clock -period 40.0 clkgen.clk_50_unbuf -waveform {0.000 20.000} 3 | create_clock -period 10.0 clkgen.clk_fb_unbuf -waveform {0.000 5.000} 4 | create_clock -period 40.0 clkgen.clk_sys -waveform {0.000 20.000} 5 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/soc/litex/linux/arty_clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk100 -period 10.0 [get_nets clk100] 2 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/soc/litex/mini/arty_clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk100 -period 10.0 [get_nets clk100] 2 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/soc/litex/mini_ddr/arty_clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk100 -period 10.0 [get_nets clk100] 2 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/soc/litex/mini_ddr_eth/arty_clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk100 -period 10.0 [get_nets clk100] 2 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/srl/common/rom.v: -------------------------------------------------------------------------------- 1 | module ROM 2 | ( 3 | input wire clk, 4 | input wire [8:0] adr, 5 | output reg dat 6 | ); 7 | 8 | // ROM content 9 | parameter [511:0] CONTENT = 512'd0; 10 | 11 | // Data output 12 | always @(posedge clk) 13 | dat <= CONTENT[adr]; 14 | 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/switch_processing/switch_processing_add_1.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input [3:0] in, 3 | output [3:0] out, 4 | input clk, 5 | input rst 6 | ); 7 | assign out = in + 1; 8 | endmodule 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/switch_processing/switch_processing_identity.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input [3:0] in, 3 | output [3:0] out, 4 | input clk, 5 | input rst 6 | ); 7 | assign out = in; 8 | endmodule 9 | -------------------------------------------------------------------------------- /xilinx/xc7/tests/uart_loopback/uart_loopback.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input wire clk, 3 | 4 | input wire rx, 5 | output wire tx, 6 | 7 | input wire rst, 8 | input wire led // unused 9 | ); 10 | 11 | assign tx = rx; 12 | 13 | endmodule 14 | --------------------------------------------------------------------------------