├── .gitattributes ├── .github ├── check_license.sh ├── check_python_scripts.sh ├── kokoro │ ├── continuous-db-kintexus.cfg │ ├── continuous-db-zynqusp.cfg │ ├── ctest2junit.xsl │ ├── database.cfg │ ├── db-full.sh │ ├── db-quick.sh │ ├── kokoro-cfg.py │ ├── nothing.sh │ ├── presubmit-db-kintexus.cfg │ ├── presubmit-db-zynqusp.cfg │ ├── steps │ │ ├── git.sh │ │ ├── hostinfo.sh │ │ ├── hostsetup.sh │ │ ├── prjuray-env.sh │ │ └── xilinx.sh │ ├── tests.cfg │ └── tests.sh ├── update-contributing.py └── workflows │ └── licensing.yml ├── .gitignore ├── .gitmodules ├── .travis.yml ├── AUTHORS ├── CONTRIBUTING.md ├── LICENSE ├── Makefile ├── README.md ├── database └── Makefile ├── docs ├── .gitignore ├── Makefile ├── _static │ └── .keepme ├── conf.py ├── developer-certificate-of-origin ├── index.rst ├── requirements.txt └── zynq_jtag.md ├── download-latest-db.sh ├── fuzzers ├── 000-init-db │ └── Makefile ├── 001-part-yaml │ ├── .gitignore │ ├── Makefile │ ├── Makefile.specimen │ ├── add_iobanks.py │ ├── generate.tcl │ └── top.v ├── 002-tilegrid │ ├── Makefile │ ├── README.md │ ├── add_tdb.py │ ├── bitslice_tiles │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── bram │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── bram_block │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── cle │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── clel_int │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── clem_int │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── clem_r │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── cmt_right │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── fuzzaddr │ │ ├── common.mk │ │ ├── generate.py │ │ └── generate.sh │ ├── generate.py │ ├── generate.sh │ ├── generate_full.py │ ├── generate_tiles.tcl │ ├── hdio_bot_right │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── hdio_top_right │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── hpio_right │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── intf_r_pcie4_hdio │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── ps8_intf │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── pss_alto │ │ ├── Makefile │ │ ├── generate.tcl │ │ ├── top.py │ │ └── top.tpl │ ├── rclk_dsp_intf_clkbuf │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── rclk_hdio │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── rclk_int │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── rclk_other │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── rclk_pss_alto │ │ ├── Makefile │ │ ├── generate.tcl │ │ └── top.py │ ├── top.v │ ├── util.py │ └── util.tcl ├── 004-tileinfo │ ├── Makefile │ ├── analyze_errors.py │ ├── cleanup_site_pins.py │ ├── generate.sh │ ├── generate_after_dump.sh │ ├── generate_grid.py │ ├── get_nodescount.tcl │ ├── get_speed_model.tcl │ ├── get_tilescount.tcl │ ├── ignored_wires │ │ └── zynqusp │ │ │ └── xczu3eg-sfvc784-1-e_ignored_wires.txt │ ├── jobnodes.tcl │ ├── jobtiles.tcl │ ├── reduce_site_types.py │ ├── reduce_tile_types.py │ └── run_fuzzer.py ├── 005-pins │ ├── Makefile │ ├── generate.sh │ └── generate.tcl ├── 007-timing │ ├── Makefile │ ├── bel │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── runme.sh │ │ ├── runme.tcl │ │ └── tim2json.py │ ├── routing-bels │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── runme.sh │ │ ├── runme.tcl │ │ └── tim2sdf.py │ └── utils │ │ ├── __init__.py │ │ └── utils.py ├── 010-cle-lutinit │ ├── Makefile │ ├── README.md │ ├── generate.py │ ├── generate.sh │ ├── generate.tcl │ ├── generate_top.sh │ ├── top.py │ └── top.tpl ├── 011-cle-ffconfig │ ├── Makefile │ ├── README.md │ ├── bits.dbf │ ├── generate.py │ ├── generate.sh │ ├── generate.tcl │ ├── prims.py │ ├── top.py │ ├── top.sh │ └── top.tpl ├── 012-cle-ffsr │ ├── Makefile │ ├── README.md │ ├── generate.py │ ├── generate.sh │ ├── generate.tcl │ ├── generate_top.sh │ ├── top.py │ └── top.tpl ├── 013-cle-ncy0 │ ├── Makefile │ ├── README.md │ ├── generate.py │ ├── generate.sh │ ├── generate.tcl │ ├── top.py │ └── top.sh ├── 014-cle-spec │ ├── Makefile │ ├── README.md │ ├── dump_features.tcl │ ├── generate.sh │ ├── generate.tcl │ ├── generate_features.sh │ ├── top.py │ └── top.sh ├── 017-cle-precyinit │ ├── Makefile │ ├── README.md │ ├── generate.py │ ├── generate.sh │ ├── generate.tcl │ ├── tag_groups.txt │ ├── top.py │ ├── top.sh │ └── top.tpl ├── 020-bram │ ├── Makefile │ ├── README.md │ ├── dump_features.tcl │ ├── generate.sh │ ├── generate.tcl │ ├── generate_features.sh │ ├── top.py │ └── top.sh ├── 021-bram-data │ ├── Makefile │ ├── README.md │ ├── dump_features.tcl │ ├── generate.sh │ ├── generate.tcl │ ├── generate_features.sh │ ├── top.py │ └── top.sh ├── 031-iob-spec │ ├── Makefile │ ├── dump_features.tcl │ ├── generate.sh │ ├── generate.tcl │ ├── generate_features.sh │ ├── iob_features.txt │ ├── solution_width.txt │ ├── top.py │ ├── top.sh │ └── zero_feature_enums.txt ├── 050-int-seed │ ├── Makefile │ ├── README.md │ ├── dump_features.tcl │ ├── generate.sh │ ├── generate.tcl │ ├── generate_features.sh │ ├── top.py │ └── top.sh ├── 060-rclk-seed │ ├── Makefile │ ├── dump_features.tcl │ ├── generate.sh │ ├── generate.tcl │ ├── generate_features.sh │ ├── solution_width.txt │ ├── top.py │ └── top.sh ├── 070-ps8-int │ ├── Makefile │ ├── dump_features.tcl │ ├── feature_filters.txt │ ├── generate.sh │ ├── generate.tcl │ ├── generate_features.sh │ ├── top.py │ └── top.sh ├── 071-ps8-bufg │ ├── Makefile │ ├── README.md │ ├── dump_features.tcl │ ├── generate.sh │ ├── generate.tcl │ ├── generate_features.sh │ ├── generate_permutations.py │ ├── solution_width.txt │ ├── top.py │ └── top.sh ├── 100-spec │ └── generate_features.sh ├── Makefile └── run_fuzzer.py ├── minitests ├── bram │ ├── bram18 │ │ ├── Makefile │ │ └── top.v │ ├── bram36 │ │ ├── Makefile │ │ └── top.v │ └── uram │ │ ├── Makefile │ │ └── top.v ├── clb │ ├── bused │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README.md │ │ └── top.v │ ├── carry_cin_cyinit │ │ ├── Makefile │ │ ├── README │ │ └── top.v │ ├── configs │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README │ │ └── top.v │ ├── dram │ │ ├── Makefile │ │ └── top.v │ └── muxf9 │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README.md │ │ └── top.v ├── delay │ ├── Makefile │ └── top.v ├── dsp │ ├── Makefile │ └── top.v ├── litex │ ├── README.md │ ├── linux │ │ └── zcu104 │ │ │ ├── README.md │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── VexRiscv_Linux.v │ │ │ ├── mem.init │ │ │ ├── mem_1.init │ │ │ ├── runme.py │ │ │ ├── top.v │ │ │ └── top.xdc │ └── zephyr │ │ └── zcu104 │ │ ├── README.md │ │ └── src │ │ ├── Makefile │ │ ├── VexRiscv_Full.v │ │ ├── mem.init │ │ ├── mem_1.init │ │ ├── mem_2.init │ │ ├── runme.py │ │ ├── top.v │ │ └── top.xdc ├── mmcm │ ├── Makefile │ └── top.v ├── opentitan │ ├── .gitignore │ ├── README.md │ ├── src.vivado │ │ ├── Makefile │ │ ├── boot_rom_fpga_nexysvideo.vmem │ │ ├── lowrisc_constants_top_pkg_0 │ │ │ └── rtl │ │ │ │ └── top_pkg.sv │ │ ├── lowrisc_dv_pins_if_0 │ │ │ └── pins_if.sv │ │ ├── lowrisc_ibex_ibex_core_0.1 │ │ │ └── rtl │ │ │ │ ├── ibex_alu.sv │ │ │ │ ├── ibex_compressed_decoder.sv │ │ │ │ ├── ibex_controller.sv │ │ │ │ ├── ibex_core.sv │ │ │ │ ├── ibex_cs_registers.sv │ │ │ │ ├── ibex_decoder.sv │ │ │ │ ├── ibex_ex_block.sv │ │ │ │ ├── ibex_fetch_fifo.sv │ │ │ │ ├── ibex_id_stage.sv │ │ │ │ ├── ibex_if_stage.sv │ │ │ │ ├── ibex_load_store_unit.sv │ │ │ │ ├── ibex_multdiv_fast.sv │ │ │ │ ├── ibex_multdiv_slow.sv │ │ │ │ ├── ibex_pkg.sv │ │ │ │ ├── ibex_pmp.sv │ │ │ │ ├── ibex_prefetch_buffer.sv │ │ │ │ └── ibex_register_file_ff.sv │ │ ├── lowrisc_ip_aes_0.5 │ │ │ └── rtl │ │ │ │ ├── aes.sv │ │ │ │ ├── aes_cipher_control.sv │ │ │ │ ├── aes_cipher_core.sv │ │ │ │ ├── aes_control.sv │ │ │ │ ├── aes_core.sv │ │ │ │ ├── aes_key_expand.sv │ │ │ │ ├── aes_mix_columns.sv │ │ │ │ ├── aes_mix_single_column.sv │ │ │ │ ├── aes_pkg.sv │ │ │ │ ├── aes_reg_pkg.sv │ │ │ │ ├── aes_reg_top.sv │ │ │ │ ├── aes_sbox.sv │ │ │ │ ├── aes_sbox_canright.sv │ │ │ │ ├── aes_sbox_lut.sv │ │ │ │ ├── aes_shift_rows.sv │ │ │ │ └── aes_sub_bytes.sv │ │ ├── lowrisc_ip_alert_handler_component_0.1 │ │ │ └── rtl │ │ │ │ ├── alert_handler.sv │ │ │ │ ├── alert_handler_accu.sv │ │ │ │ ├── alert_handler_class.sv │ │ │ │ ├── alert_handler_esc_timer.sv │ │ │ │ ├── alert_handler_ping_timer.sv │ │ │ │ ├── alert_handler_reg_wrap.sv │ │ │ │ └── alert_pkg.sv │ │ ├── lowrisc_ip_flash_ctrl_0.1 │ │ │ └── rtl │ │ │ │ ├── flash_ctrl.sv │ │ │ │ ├── flash_ctrl_reg_pkg.sv │ │ │ │ ├── flash_ctrl_reg_top.sv │ │ │ │ ├── flash_erase_ctrl.sv │ │ │ │ ├── flash_mp.sv │ │ │ │ ├── flash_phy.sv │ │ │ │ ├── flash_prog_ctrl.sv │ │ │ │ └── flash_rd_ctrl.sv │ │ ├── lowrisc_ip_flash_ctrl_pkg_0.1 │ │ │ └── rtl │ │ │ │ └── flash_ctrl_pkg.sv │ │ ├── lowrisc_ip_gpio_0.1 │ │ │ └── rtl │ │ │ │ ├── gpio.sv │ │ │ │ ├── gpio_reg_pkg.sv │ │ │ │ └── gpio_reg_top.sv │ │ ├── lowrisc_ip_hmac_0.1 │ │ │ └── rtl │ │ │ │ ├── hmac.sv │ │ │ │ ├── hmac_core.sv │ │ │ │ ├── hmac_pkg.sv │ │ │ │ ├── hmac_reg_pkg.sv │ │ │ │ ├── hmac_reg_top.sv │ │ │ │ ├── sha2.sv │ │ │ │ └── sha2_pad.sv │ │ ├── lowrisc_ip_nmi_gen_0.1 │ │ │ └── rtl │ │ │ │ ├── nmi_gen.sv │ │ │ │ ├── nmi_gen_reg_pkg.sv │ │ │ │ └── nmi_gen_reg_top.sv │ │ ├── lowrisc_ip_pinmux_component_0.1 │ │ │ └── rtl │ │ │ │ └── pinmux.sv │ │ ├── lowrisc_ip_rv_core_ibex_0.1 │ │ │ └── rtl │ │ │ │ └── rv_core_ibex.sv │ │ ├── lowrisc_ip_rv_dm_0.1 │ │ │ └── rtl │ │ │ │ ├── rv_dm.sv │ │ │ │ └── tlul_adapter_host.sv │ │ ├── lowrisc_ip_rv_plic_component_0.1 │ │ │ └── rtl │ │ │ │ ├── rv_plic_gateway.sv │ │ │ │ └── rv_plic_target.sv │ │ ├── lowrisc_ip_rv_timer_0.1 │ │ │ └── rtl │ │ │ │ ├── rv_timer.sv │ │ │ │ ├── rv_timer_reg_pkg.sv │ │ │ │ ├── rv_timer_reg_top.sv │ │ │ │ └── timer_core.sv │ │ ├── lowrisc_ip_spi_device_0.1 │ │ │ └── rtl │ │ │ │ ├── spi_device.sv │ │ │ │ ├── spi_device_pkg.sv │ │ │ │ ├── spi_device_reg_pkg.sv │ │ │ │ ├── spi_device_reg_top.sv │ │ │ │ ├── spi_fwm_rxf_ctrl.sv │ │ │ │ ├── spi_fwm_txf_ctrl.sv │ │ │ │ └── spi_fwmode.sv │ │ ├── lowrisc_ip_uart_0.1 │ │ │ └── rtl │ │ │ │ ├── uart.sv │ │ │ │ ├── uart_core.sv │ │ │ │ ├── uart_reg_pkg.sv │ │ │ │ ├── uart_reg_top.sv │ │ │ │ ├── uart_rx.sv │ │ │ │ └── uart_tx.sv │ │ ├── lowrisc_ip_usb_fs_nb_pe_0.1 │ │ │ └── rtl │ │ │ │ ├── usb_consts_pkg.sv │ │ │ │ ├── usb_fs_nb_in_pe.sv │ │ │ │ ├── usb_fs_nb_out_pe.sv │ │ │ │ ├── usb_fs_nb_pe.sv │ │ │ │ ├── usb_fs_rx.sv │ │ │ │ ├── usb_fs_tx.sv │ │ │ │ └── usb_fs_tx_mux.sv │ │ ├── lowrisc_ip_usbdev_0.1 │ │ │ └── rtl │ │ │ │ ├── usbdev.sv │ │ │ │ ├── usbdev_flop_2syncpulse.sv │ │ │ │ ├── usbdev_iomux.sv │ │ │ │ ├── usbdev_linkstate.sv │ │ │ │ ├── usbdev_reg_pkg.sv │ │ │ │ ├── usbdev_reg_top.sv │ │ │ │ └── usbdev_usbif.sv │ │ ├── lowrisc_ip_xbar_main_0.1 │ │ │ ├── tl_main_pkg.sv │ │ │ └── xbar_main.sv │ │ ├── lowrisc_ip_xbar_peri_0.1 │ │ │ ├── tl_peri_pkg.sv │ │ │ └── xbar_peri.sv │ │ ├── lowrisc_prim_all_0.1 │ │ │ └── rtl │ │ │ │ ├── prim_alert_receiver.sv │ │ │ │ ├── prim_alert_sender.sv │ │ │ │ ├── prim_arbiter_ppc.sv │ │ │ │ ├── prim_arbiter_tree.sv │ │ │ │ ├── prim_clock_inverter.sv │ │ │ │ ├── prim_esc_receiver.sv │ │ │ │ ├── prim_esc_sender.sv │ │ │ │ ├── prim_fifo_async.sv │ │ │ │ ├── prim_fifo_sync.sv │ │ │ │ ├── prim_filter.sv │ │ │ │ ├── prim_filter_ctr.sv │ │ │ │ ├── prim_flop_2sync.sv │ │ │ │ ├── prim_intr_hw.sv │ │ │ │ ├── prim_lfsr.sv │ │ │ │ ├── prim_packer.sv │ │ │ │ ├── prim_pulse_sync.sv │ │ │ │ ├── prim_ram_2p_adv.sv │ │ │ │ ├── prim_ram_2p_async_adv.sv │ │ │ │ ├── prim_secded_39_32_dec.sv │ │ │ │ ├── prim_secded_39_32_enc.sv │ │ │ │ ├── prim_sram_arbiter.sv │ │ │ │ ├── prim_subreg.sv │ │ │ │ └── prim_subreg_ext.sv │ │ ├── lowrisc_prim_assert_0.1 │ │ │ └── rtl │ │ │ │ └── prim_assert.sv │ │ ├── lowrisc_prim_clock_gating_0 │ │ │ └── abstract │ │ │ │ └── prim_clock_gating.sv │ │ ├── lowrisc_prim_clock_mux2_0 │ │ │ └── abstract │ │ │ │ └── prim_clock_mux2.sv │ │ ├── lowrisc_prim_diff_decode_0 │ │ │ └── rtl │ │ │ │ └── prim_diff_decode.sv │ │ ├── lowrisc_prim_flash_0 │ │ │ └── abstract │ │ │ │ └── prim_flash.sv │ │ ├── lowrisc_prim_generic_clock_gating_0 │ │ │ └── rtl │ │ │ │ └── prim_generic_clock_gating.sv │ │ ├── lowrisc_prim_generic_clock_mux2_0 │ │ │ └── rtl │ │ │ │ └── prim_generic_clock_mux2.sv │ │ ├── lowrisc_prim_generic_flash_0 │ │ │ └── rtl │ │ │ │ └── prim_generic_flash.sv │ │ ├── lowrisc_prim_generic_pad_wrapper_0 │ │ │ └── rtl │ │ │ │ └── prim_generic_pad_wrapper.sv │ │ ├── lowrisc_prim_generic_ram_1p_0 │ │ │ └── rtl │ │ │ │ └── prim_generic_ram_1p.sv │ │ ├── lowrisc_prim_generic_ram_2p_0 │ │ │ └── rtl │ │ │ │ └── prim_generic_ram_2p.sv │ │ ├── lowrisc_prim_generic_rom_0 │ │ │ └── rtl │ │ │ │ └── prim_generic_rom.sv │ │ ├── lowrisc_prim_pad_wrapper_0 │ │ │ └── abstract │ │ │ │ └── prim_pad_wrapper.sv │ │ ├── lowrisc_prim_prim_pkg_0.1 │ │ │ └── rtl │ │ │ │ └── prim_pkg.sv │ │ ├── lowrisc_prim_ram_1p_0 │ │ │ └── abstract │ │ │ │ └── prim_ram_1p.sv │ │ ├── lowrisc_prim_ram_2p_0 │ │ │ └── abstract │ │ │ │ └── prim_ram_2p.sv │ │ ├── lowrisc_prim_rom_0 │ │ │ └── abstract │ │ │ │ └── prim_rom.sv │ │ ├── lowrisc_prim_xilinx_clock_gating_0 │ │ │ └── rtl │ │ │ │ └── prim_xilinx_clock_gating.sv │ │ ├── lowrisc_prim_xilinx_clock_mux2_0 │ │ │ └── rtl │ │ │ │ └── prim_xilinx_clock_mux2.sv │ │ ├── lowrisc_prim_xilinx_pad_wrapper_0 │ │ │ └── rtl │ │ │ │ └── prim_xilinx_pad_wrapper.sv │ │ ├── lowrisc_prim_xilinx_ram_2p_0 │ │ │ └── rtl │ │ │ │ └── prim_xilinx_ram_2p.sv │ │ ├── lowrisc_prim_xilinx_rom_0 │ │ │ └── rtl │ │ │ │ └── prim_xilinx_rom.sv │ │ ├── lowrisc_systems_top_earlgrey_0.1 │ │ │ └── rtl │ │ │ │ ├── autogen │ │ │ │ └── top_earlgrey.sv │ │ │ │ └── padctl.sv │ │ ├── lowrisc_systems_top_earlgrey_zcu104_0.1 │ │ │ ├── data │ │ │ │ └── pins_zcu104.xdc │ │ │ └── rtl │ │ │ │ ├── clkgen_xilusp.sv │ │ │ │ └── top_earlgrey_zcu104.sv │ │ ├── lowrisc_tlul_adapter_reg_0.1 │ │ │ └── rtl │ │ │ │ └── tlul_adapter_reg.sv │ │ ├── lowrisc_tlul_adapter_sram_0.1 │ │ │ └── rtl │ │ │ │ └── tlul_adapter_sram.sv │ │ ├── lowrisc_tlul_common_0.1 │ │ │ └── rtl │ │ │ │ ├── tlul_assert.sv │ │ │ │ ├── tlul_assert_multiple.sv │ │ │ │ ├── tlul_err.sv │ │ │ │ ├── tlul_fifo_async.sv │ │ │ │ └── tlul_fifo_sync.sv │ │ ├── lowrisc_tlul_headers_0.1 │ │ │ └── rtl │ │ │ │ └── tlul_pkg.sv │ │ ├── lowrisc_tlul_socket_1n_0.1 │ │ │ └── rtl │ │ │ │ ├── tlul_err_resp.sv │ │ │ │ └── tlul_socket_1n.sv │ │ ├── lowrisc_tlul_socket_m1_0.1 │ │ │ └── rtl │ │ │ │ └── tlul_socket_m1.sv │ │ ├── lowrisc_tlul_sram2tlul_0.1 │ │ │ └── rtl │ │ │ │ └── sram2tlul.sv │ │ ├── lowrisc_top_earlgrey_alert_handler_reg_0.1 │ │ │ └── rtl │ │ │ │ └── autogen │ │ │ │ ├── alert_handler_reg_pkg.sv │ │ │ │ └── alert_handler_reg_top.sv │ │ ├── lowrisc_top_earlgrey_pinmux_reg_0.1 │ │ │ └── rtl │ │ │ │ └── autogen │ │ │ │ ├── pinmux_reg_pkg.sv │ │ │ │ └── pinmux_reg_top.sv │ │ ├── lowrisc_top_earlgrey_rv_plic_0.1 │ │ │ └── rtl │ │ │ │ └── autogen │ │ │ │ ├── rv_plic.sv │ │ │ │ ├── rv_plic_reg_pkg.sv │ │ │ │ └── rv_plic_reg_top.sv │ │ ├── pulp-platform_riscv-dbg_0.1_0 │ │ │ └── pulp_riscv_dbg │ │ │ │ ├── debug_rom │ │ │ │ └── debug_rom.sv │ │ │ │ └── src │ │ │ │ ├── dm_csrs.sv │ │ │ │ ├── dm_mem.sv │ │ │ │ ├── dm_pkg.sv │ │ │ │ ├── dm_sba.sv │ │ │ │ ├── dmi_cdc.sv │ │ │ │ ├── dmi_jtag.sv │ │ │ │ └── dmi_jtag_tap.sv │ │ └── runme.py │ └── src.yosys │ │ ├── Makefile │ │ ├── boot_rom_fpga_nexysvideo.vmem │ │ ├── pins_zcu104.xdc │ │ ├── runme.py │ │ └── sv2v.sh ├── pll │ ├── Makefile │ └── top.v ├── serdes │ ├── iserdes │ │ ├── Makefile │ │ └── top.v │ └── oserdes │ │ ├── Makefile │ │ └── top.v ├── util │ ├── common.mk │ ├── runme.py │ └── runme.sh └── zynqmp_blinky │ ├── Makefile │ ├── README.md │ ├── load_script.gdb │ ├── pl │ ├── Makefile │ ├── syn+par.tcl │ ├── top.v │ └── ultra96v2.xdc │ ├── program.sh │ └── ps │ ├── 0001-Add-zcu104.patch │ └── Makefile ├── requirements.txt ├── settings ├── zynq_usp_3eg.sh ├── zynq_usp_7ev.sh └── zynqusp.sh ├── spec ├── picosoc_top.v ├── slice.v ├── slice_carry.v └── slice_memory.v ├── third_party ├── VexRiscv │ ├── LICENSE │ ├── README.prjuray │ ├── VexRiscv_Full.v │ └── VexRiscv_Linux.v ├── litex │ ├── LICENSE │ ├── README.prjuray │ ├── VexRiscv_Lite.v │ ├── top_linux.v │ └── top_zephyr.v ├── picosoc │ ├── LICENSE │ └── picorv32.v └── reformat.tcl ├── tools ├── .gitignore ├── Makefile ├── assemble.cpp ├── bits.py ├── bits_to_tiles.py ├── columns.py ├── common.cpp ├── common.h ├── correlate.cpp ├── dump_bitstream.cpp ├── dump_bram_dsp_test.tcl ├── dump_clocking_test.tcl ├── dump_features.tcl ├── dump_features_test.tcl ├── explain.cpp ├── filter.py ├── frames.py ├── frames_2.py ├── ll.py ├── oddtiles.py ├── registers.inc ├── stripdb.cpp ├── tilebits.py ├── tilegrid_report.py ├── update_tilebits_all.sh └── write_roi.py └── utils ├── annotate_unknown.py ├── bit2fasm.py ├── bitsmaker.py ├── bitstream.py ├── bitstream_analyzer.py ├── checkdb.py ├── clock_utils.py ├── cmp.py ├── create_feature_extents.py ├── create_segdata_from_features.py ├── dbfixup.py ├── environment.python.sh ├── environment.sh ├── fasm2bit.py ├── fasm2frames.py ├── fasm_assembler.py ├── fasm_disassembler.py ├── filter_features.py ├── filter_solution_width.py ├── fuzzpins.tcl ├── generate_active_bufce_row.tcl ├── generate_all_pip_features.tcl ├── generate_invpips.tcl ├── genheader.sh ├── get_bufce_leaf_clock_regions.tcl ├── get_bufg_direct_outputs.tcl ├── get_ccio_pins.tcl ├── get_general_purpose_io.tcl ├── get_pins.tcl ├── get_ps8_bufg_pin_map.tcl ├── get_ps8_intf.tcl ├── get_ps8_intf_inputs.tcl ├── get_ps8_pin_map.tcl ├── info_md.py ├── io_utils.py ├── iob_cleanup.py ├── lut_maker.py ├── makesdf.py ├── maskmerge.sh ├── mergedb.py ├── mergedb.sh ├── node_lookup.py ├── output_io_configs.py ├── parsedb.py ├── roi.py ├── sdfmerge.py ├── segmaker.py ├── segmatch_all_types.py ├── sort_db.py ├── spec ├── __init__.py ├── bram18.py ├── bram18_2.py ├── bram18_3.py ├── bram36.py ├── bram36_sdp.py ├── bram36_sdp_2.py ├── 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