├── media-libs └── mesa │ ├── Manifest │ ├── files │ ├── eselect-mesa.conf.9.2 │ └── mesa-13.0.2-liverpool.patch │ ├── mesa-13.0.2.ebuild │ └── metadata.xml ├── metadata └── layout.conf ├── sys-firmware └── ps4-ucode │ ├── Manifest │ ├── files │ └── resize_firmware.py │ ├── metadata.xml │ └── ps4-ucode-20161205.ebuild ├── x11-drivers ├── xf86-video-amdgpu │ ├── Manifest │ ├── files │ │ └── xf86-video-amdgpu-1.2.0-liverpool.patch │ ├── metadata.xml │ └── xf86-video-amdgpu-1.2.0.ebuild └── xf86-video-ati │ ├── Manifest │ ├── files │ └── xf86-video-ati-7.6.1-liverpool.patch │ ├── metadata.xml │ └── xf86-video-ati-7.8.0.ebuild └── x11-libs └── libdrm ├── Manifest ├── files ├── amd-patches │ ├── 0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch │ ├── 0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch │ ├── 0028-amdgpu-add-query-for-aperture-va-range.patch │ ├── 0029-amdgpu-Implement-SVM-v2.patch │ ├── 0030-amdgpu-SVM-test-v2.patch │ ├── 0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch │ ├── 0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch │ ├── 0033-tests-amdgpu-Add-verbose-outputs-v2.patch │ ├── 0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch │ ├── 0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch │ ├── 0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch │ ├── 0037-tests-amdgpu-add-the-heap-info-for-query.patch │ ├── 0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch │ ├── 0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch │ ├── 0040-amdgpu-add-query-amdgpu-capability-defination.patch │ ├── 0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch │ ├── 0042-amdgpu-add-amdgpu_query_capability-interface.patch │ ├── 0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch │ ├── 0044-amdgpu-support-alloc-va-from-range.patch │ ├── 0045-tests-amdgpu-add-alloc-va-from-range-test.patch │ ├── 0047-tests-amdgpu-move-va_range_test-above-svm_test.patch │ ├── 0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch │ ├── 0056-amdgpu-change-max-allocation.patch │ ├── 0057-amdgpu-fix-print-format-error-V2.patch │ ├── 0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch │ ├── 0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch │ ├── 0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch │ ├── 0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch │ ├── 0074-drm-fix-a-bug-in-va-range-allocation.patch │ ├── 0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch │ ├── 0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch │ ├── 0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch │ ├── 0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch │ ├── 0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch │ ├── 0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch │ ├── 0104-drm-amdgpu-add-freesync-ioctl-defines.patch │ ├── 0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch │ ├── 0109-amdgpu-tests-remove-debug-info-in-cs-test.patch │ ├── 0114-amdgpu-add-more-capability-query.patch │ └── 0116-tests-amdgpu-add-direct-gma-test.patch └── libdrm-2.4.74-liverpool.patch ├── libdrm-2.4.74.ebuild └── metadata.xml /media-libs/mesa/Manifest: -------------------------------------------------------------------------------- 1 | DIST mesa-13.0.2.tar.xz 9159100 SHA256 a6ed622645f4ed61da418bf65adde5bcc4bb79023c36ba7d6b45b389da4416d5 SHA512 e4e2b9d685910f9b1d70958c50f54d059263623865571a92c3aa185914f4f7aa745d74afc9706b64ecd1f8d04c603ad03a78365d976382e2664284dc6a8351be WHIRLPOOL 49cb109e3b97f491f7682155a3194fd3df8808235a45a18539a8ecf55d2e3a9ba13dabb13f819822e256b272b4145efad029e38e7c666a5bf7abe7906528f6d2 2 | -------------------------------------------------------------------------------- /media-libs/mesa/files/eselect-mesa.conf.9.2: -------------------------------------------------------------------------------- 1 | # mesa classic/gallium implementations in this release 2 | 3 | # Syntax description: 4 | # * MESA_IMPLEMENTATIONS contains a space-delimited list of switchable 5 | # classic/gallium implementations. 6 | # * MESA_DRIVERS is an associative array, for each member "foo" of 7 | # MESA_IMPLEMENTATIONS it contains the following elements: 8 | # foo,description - Human-readable description of the driver 9 | # foo,classicdriver - Filename of the classic driver 10 | # foo,galliumdriver - Filename of the gallium driver 11 | # foo,default - which of classic or gallium is chosen by default 12 | 13 | MESA_IMPLEMENTATIONS="i915 i965 r300 r600 sw" 14 | declare -A MESA_DRIVERS || die "MESA_DRIVERS already in environment and not associative." 15 | 16 | MESA_DRIVERS[i915,description]="i915 (Intel 915, 945)" 17 | MESA_DRIVERS[i915,classicdriver]="i915_dri.so" 18 | MESA_DRIVERS[i915,galliumdriver]="i915g_dri.so" 19 | MESA_DRIVERS[i915,default]="gallium" 20 | 21 | MESA_DRIVERS[i965,description]="i965 (Intel GMA 965, G/Q3x, G/Q4x, HD)" 22 | MESA_DRIVERS[i965,classicdriver]="i965_dri.so" 23 | MESA_DRIVERS[i965,galliumdriver]="ilo_dri.so" 24 | MESA_DRIVERS[i965,default]="classic" 25 | 26 | MESA_DRIVERS[r300,description]="r300 (Radeon R300-R500)" 27 | MESA_DRIVERS[r300,classicdriver]="r300_dri.so" 28 | MESA_DRIVERS[r300,galliumdriver]="r300g_dri.so" 29 | MESA_DRIVERS[r300,default]="gallium" 30 | 31 | MESA_DRIVERS[r600,description]="r600 (Radeon R600-R700, Evergreen, Northern Islands)" 32 | MESA_DRIVERS[r600,classicdriver]="r600_dri.so" 33 | MESA_DRIVERS[r600,galliumdriver]="r600g_dri.so" 34 | MESA_DRIVERS[r600,default]="gallium" 35 | 36 | MESA_DRIVERS[sw,description]="sw (Software renderer)" 37 | MESA_DRIVERS[sw,classicdriver]="swrast_dri.so" 38 | MESA_DRIVERS[sw,galliumdriver]="swrastg_dri.so" 39 | MESA_DRIVERS[sw,default]="gallium" 40 | -------------------------------------------------------------------------------- /media-libs/mesa/files/mesa-13.0.2-liverpool.patch: -------------------------------------------------------------------------------- 1 | diff -urN mesa-13.0.2-old/include/pci_ids/radeonsi_pci_ids.h mesa-13.0.2/include/pci_ids/radeonsi_pci_ids.h 2 | --- mesa-13.0.2-old/include/pci_ids/radeonsi_pci_ids.h 2017-01-02 17:54:00.225315261 +0100 3 | +++ mesa-13.0.2/include/pci_ids/radeonsi_pci_ids.h 2017-01-02 17:54:07.971096863 +0100 4 | @@ -122,6 +122,8 @@ 5 | CHIPSET(0x985E, MULLINS_985E, MULLINS) 6 | CHIPSET(0x985F, MULLINS_985F, MULLINS) 7 | 8 | +CHIPSET(0x9920, LIVERPOOL_9920, LIVERPOOL) 9 | + 10 | CHIPSET(0x1304, KAVERI_1304, KAVERI) 11 | CHIPSET(0x1305, KAVERI_1305, KAVERI) 12 | CHIPSET(0x1306, KAVERI_1306, KAVERI) 13 | diff -urN mesa-13.0.2-old/src/amd/common/ac_llvm_util.c mesa-13.0.2/src/amd/common/ac_llvm_util.c 14 | --- mesa-13.0.2-old/src/amd/common/ac_llvm_util.c 2017-01-02 17:54:00.112318479 +0100 15 | +++ mesa-13.0.2/src/amd/common/ac_llvm_util.c 2017-01-02 18:15:53.990994519 +0100 16 | @@ -90,6 +90,8 @@ 17 | return "hawaii"; 18 | case CHIP_MULLINS: 19 | return "mullins"; 20 | + case CHIP_LIVERPOOL: 21 | + return "bonaire"; 22 | case CHIP_TONGA: 23 | return "tonga"; 24 | case CHIP_ICELAND: 25 | diff -urN mesa-13.0.2-old/src/amd/common/amd_family.h mesa-13.0.2/src/amd/common/amd_family.h 26 | --- mesa-13.0.2-old/src/amd/common/amd_family.h 2017-01-02 17:54:00.112318479 +0100 27 | +++ mesa-13.0.2/src/amd/common/amd_family.h 2017-01-02 17:54:07.972096835 +0100 28 | @@ -82,6 +82,7 @@ 29 | CHIP_BONAIRE, 30 | CHIP_KAVERI, 31 | CHIP_KABINI, 32 | + CHIP_LIVERPOOL, 33 | CHIP_HAWAII, 34 | CHIP_MULLINS, 35 | CHIP_TONGA, 36 | diff -urN mesa-13.0.2-old/src/amd/common/amdgpu_id.h mesa-13.0.2/src/amd/common/amdgpu_id.h 37 | --- mesa-13.0.2-old/src/amd/common/amdgpu_id.h 2017-01-02 17:54:00.112318479 +0100 38 | +++ mesa-13.0.2/src/amd/common/amdgpu_id.h 2017-01-02 18:09:21.680883273 +0100 39 | @@ -108,6 +108,7 @@ 40 | enum { 41 | KV_SPECTRE_A0 = 0x01, /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */ 42 | KV_SPOOKY_A0 = 0x41, /* KV2 with Spooky GFX core, including downgraded from Spectre core, 3-4-1-1 (CU-Pix-Primitive-RB) */ 43 | + LVP_STARSHA_A0 = 0x61, /* LVP with Starsha GFX core */ 44 | KB_KALINDI_A0 = 0x81, /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ 45 | KB_KALINDI_A1 = 0x82, /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ 46 | BV_KALINDI_A2 = 0x85, /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ 47 | @@ -122,6 +123,7 @@ 48 | ((eChipRev >= KV_SPOOKY_A0) && (eChipRev < KB_KALINDI_A0)) /* identify all versions of SPOOKY and supported features set */ 49 | #define ASICREV_IS_KALINDI(eChipRev) \ 50 | ((eChipRev >= KB_KALINDI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of KALINDI and supported features set */ 51 | + 52 | 53 | /* Following macros are subset of ASICREV_IS_KALINDI macro */ 54 | #define ASICREV_IS_KALINDI_BHAVANI(eChipRev) \ 55 | diff -urN mesa-13.0.2-old/src/amd/vulkan/si_cmd_buffer.c mesa-13.0.2/src/amd/vulkan/si_cmd_buffer.c 56 | --- mesa-13.0.2-old/src/amd/vulkan/si_cmd_buffer.c 2017-01-02 17:54:00.116318365 +0100 57 | +++ mesa-13.0.2/src/amd/vulkan/si_cmd_buffer.c 2017-01-02 18:14:04.116093349 +0100 58 | @@ -319,6 +319,10 @@ 59 | raster_config = 0x00000000; 60 | raster_config_1 = 0x00000000; 61 | break; 62 | + case CHIP_LIVERPOOL: 63 | + raster_config = 0x2a00161a; 64 | + raster_config_1 = 0x00000000; 65 | + break; 66 | default: 67 | fprintf(stderr, 68 | "radeonsi: Unknown GPU, using 0 for raster_config\n"); 69 | diff -urN mesa-13.0.2-old/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c mesa-13.0.2/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c 70 | --- mesa-13.0.2-old/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c 2017-01-02 17:54:00.115318394 +0100 71 | +++ mesa-13.0.2/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c 2017-01-02 18:14:57.162537978 +0100 72 | @@ -100,6 +100,7 @@ 73 | case CHIP_KABINI: return "AMD RADV KABINI"; 74 | case CHIP_HAWAII: return "AMD RADV HAWAII"; 75 | case CHIP_MULLINS: return "AMD RADV MULLINS"; 76 | + case CHIP_LIVERPOOL: return "AMD RADV LIVERPOOL"; 77 | case CHIP_TONGA: return "AMD RADV TONGA"; 78 | case CHIP_ICELAND: return "AMD RADV ICELAND"; 79 | case CHIP_CARRIZO: return "AMD RADV CARRIZO"; 80 | @@ -228,6 +229,10 @@ 81 | ws->family = FAMILY_KV; 82 | ws->rev_id = ML_GODAVARI_A0; 83 | break; 84 | + case CHIP_LIVERPOOL: 85 | + ws->family = FAMILY_KV; 86 | + ws->rev_id = LVP_STARSHA_A0; 87 | + break; 88 | case CHIP_TONGA: 89 | ws->family = FAMILY_VI; 90 | ws->rev_id = VI_TONGA_P_A0; 91 | diff -urN mesa-13.0.2-old/src/gallium/drivers/radeon/r600_pipe_common.c mesa-13.0.2/src/gallium/drivers/radeon/r600_pipe_common.c 92 | --- mesa-13.0.2-old/src/gallium/drivers/radeon/r600_pipe_common.c 2017-01-02 17:53:59.809327125 +0100 93 | +++ mesa-13.0.2/src/gallium/drivers/radeon/r600_pipe_common.c 2017-01-02 17:54:07.972096835 +0100 94 | @@ -727,6 +727,7 @@ 95 | case CHIP_BONAIRE: return "AMD BONAIRE"; 96 | case CHIP_KAVERI: return "AMD KAVERI"; 97 | case CHIP_KABINI: return "AMD KABINI"; 98 | + case CHIP_LIVERPOOL: return "AMD LIVERPOOL"; 99 | case CHIP_HAWAII: return "AMD HAWAII"; 100 | case CHIP_MULLINS: return "AMD MULLINS"; 101 | case CHIP_TONGA: return "AMD TONGA"; 102 | @@ -853,6 +854,7 @@ 103 | case CHIP_BONAIRE: return "bonaire"; 104 | case CHIP_KABINI: return "kabini"; 105 | case CHIP_KAVERI: return "kaveri"; 106 | + case CHIP_LIVERPOOL: return "bonaire"; 107 | case CHIP_HAWAII: return "hawaii"; 108 | case CHIP_MULLINS: 109 | return "mullins"; 110 | diff -urN mesa-13.0.2-old/src/gallium/drivers/radeonsi/si_pipe.c mesa-13.0.2/src/gallium/drivers/radeonsi/si_pipe.c 111 | --- mesa-13.0.2-old/src/gallium/drivers/radeonsi/si_pipe.c 2017-01-02 17:53:59.839326268 +0100 112 | +++ mesa-13.0.2/src/gallium/drivers/radeonsi/si_pipe.c 2017-01-02 17:54:07.972096835 +0100 113 | @@ -723,6 +723,7 @@ 114 | case CHIP_VERDE: 115 | case CHIP_BONAIRE: 116 | case CHIP_HAWAII: 117 | + case CHIP_LIVERPOOL: 118 | case CHIP_TONGA: 119 | case CHIP_FIJI: 120 | case CHIP_POLARIS10: 121 | diff -urN mesa-13.0.2-old/src/gallium/drivers/radeonsi/si_state.c mesa-13.0.2/src/gallium/drivers/radeonsi/si_state.c 122 | --- mesa-13.0.2-old/src/gallium/drivers/radeonsi/si_state.c 2017-01-02 17:53:59.838326297 +0100 123 | +++ mesa-13.0.2/src/gallium/drivers/radeonsi/si_state.c 2017-01-02 17:54:07.974096779 +0100 124 | @@ -3867,6 +3867,10 @@ 125 | raster_config = 0x00000000; /* 0x00000002 */ 126 | raster_config_1 = 0x00000000; 127 | break; 128 | + case CHIP_LIVERPOOL: 129 | + raster_config = 0x2a00161a; 130 | + raster_config_1 = 0x00000000; 131 | + break; 132 | case CHIP_KABINI: 133 | case CHIP_MULLINS: 134 | case CHIP_STONEY: 135 | diff -urN mesa-13.0.2-old/src/gallium/targets/d3dadapter9/description.c mesa-13.0.2/src/gallium/targets/d3dadapter9/description.c 136 | --- mesa-13.0.2-old/src/gallium/targets/d3dadapter9/description.c 2017-01-02 17:53:59.929323697 +0100 137 | +++ mesa-13.0.2/src/gallium/targets/d3dadapter9/description.c 2017-01-02 17:54:07.974096779 +0100 138 | @@ -52,6 +52,7 @@ 139 | {"KAVERI", "AMD Radeon(TM) R7 Graphics"}, 140 | {"KABINI", "AMD Radeon HD 8400 / R3 Series"}, 141 | {"BONAIRE", "AMD Radeon HD 8770"}, 142 | + {"LIVERPOOL", "AMD Liverpool (PlayStation 4)"}, 143 | {"OLAND", "AMD Radeon HD 8670"}, 144 | {"HAINAN", "AMD Radeon HD 8600M Series"}, 145 | {"TAHITI", "AMD Radeon HD 7900 Series"}, 146 | diff -urN mesa-13.0.2-old/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c mesa-13.0.2/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 147 | --- mesa-13.0.2-old/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 2017-01-02 17:53:59.962322755 +0100 148 | +++ mesa-13.0.2/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 2017-01-02 18:09:53.995069669 +0100 149 | @@ -272,6 +272,9 @@ 150 | ws->family = FAMILY_KV; 151 | ws->rev_id = ML_GODAVARI_A0; 152 | break; 153 | + case CHIP_LIVERPOOL: 154 | + ws->family = FAMILY_KV; 155 | + ws->rev_id = LVP_STARSHA_A0; 156 | case CHIP_TONGA: 157 | ws->family = FAMILY_VI; 158 | ws->rev_id = VI_TONGA_P_A0; 159 | diff -urN mesa-13.0.2-old/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c mesa-13.0.2/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 160 | --- mesa-13.0.2-old/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 2017-01-02 17:53:59.956322926 +0100 161 | +++ mesa-13.0.2/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 2017-01-02 17:54:07.975096752 +0100 162 | @@ -291,6 +291,7 @@ 163 | case CHIP_BONAIRE: 164 | case CHIP_KAVERI: 165 | case CHIP_KABINI: 166 | + case CHIP_LIVERPOOL: 167 | case CHIP_HAWAII: 168 | case CHIP_MULLINS: 169 | ws->info.chip_class = CIK; 170 | @@ -489,6 +490,7 @@ 171 | case CHIP_TAHITI: 172 | case CHIP_PITCAIRN: 173 | case CHIP_BONAIRE: 174 | + case CHIP_LIVERPOOL: 175 | ws->info.max_se = 2; 176 | break; 177 | case CHIP_HAWAII: 178 | -------------------------------------------------------------------------------- /media-libs/mesa/mesa-13.0.2.ebuild: -------------------------------------------------------------------------------- 1 | # Copyright 1999-2016 Gentoo Foundation 2 | # Distributed under the terms of the GNU General Public License v2 3 | # $Id$ 4 | 5 | EAPI=5 6 | 7 | EGIT_REPO_URI="git://anongit.freedesktop.org/mesa/mesa" 8 | 9 | if [[ ${PV} = 9999 ]]; then 10 | GIT_ECLASS="git-r3" 11 | EXPERIMENTAL="true" 12 | fi 13 | 14 | PYTHON_COMPAT=( python2_7 ) 15 | 16 | inherit autotools multilib-minimal python-any-r1 pax-utils ${GIT_ECLASS} 17 | 18 | OPENGL_DIR="xorg-x11" 19 | 20 | MY_P="${P/_/-}" 21 | FOLDER="${PV/_rc*/}" 22 | 23 | DESCRIPTION="OpenGL-like graphic library for Linux" 24 | HOMEPAGE="http://mesa3d.sourceforge.net/" 25 | 26 | if [[ $PV == 9999 ]]; then 27 | SRC_URI="" 28 | KEYWORDS="" 29 | else 30 | SRC_URI="ftp://ftp.freedesktop.org/pub/mesa/${FOLDER}/${MY_P}.tar.xz" 31 | KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~mips ~ppc ~ppc64 ~s390 ~sh ~sparc ~x86 ~amd64-fbsd ~x86-fbsd ~x86-freebsd ~amd64-linux ~arm-linux ~ia64-linux ~x86-linux ~sparc-solaris ~x64-solaris ~x86-solaris" 32 | fi 33 | 34 | LICENSE="MIT" 35 | SLOT="0" 36 | RESTRICT="!bindist? ( bindist )" 37 | 38 | INTEL_CARDS="i915 i965 ilo intel" 39 | RADEON_CARDS="r100 r200 r300 r600 radeon radeonsi" 40 | VIDEO_CARDS="${INTEL_CARDS} ${RADEON_CARDS} freedreno nouveau vc4 vmware" 41 | for card in ${VIDEO_CARDS}; do 42 | IUSE_VIDEO_CARDS+=" video_cards_${card}" 43 | done 44 | 45 | IUSE="${IUSE_VIDEO_CARDS} 46 | bindist +classic d3d9 debug +dri3 +egl +gallium +gbm gcrypt gles1 gles2 47 | libressl +llvm +nettle +nptl opencl osmesa pax_kernel openmax openssl pic 48 | selinux vaapi valgrind vdpau vulkan wayland xvmc xa kernel_FreeBSD" 49 | 50 | REQUIRED_USE=" 51 | || ( gcrypt libressl nettle openssl ) 52 | d3d9? ( dri3 gallium ) 53 | llvm? ( gallium ) 54 | opencl? ( gallium llvm ) 55 | openmax? ( gallium ) 56 | gles1? ( egl ) 57 | gles2? ( egl ) 58 | vaapi? ( gallium ) 59 | vdpau? ( gallium ) 60 | vulkan? ( || ( video_cards_i965 video_cards_radeonsi ) ) 61 | wayland? ( egl gbm ) 62 | xa? ( gallium ) 63 | video_cards_freedreno? ( gallium ) 64 | video_cards_intel? ( classic ) 65 | video_cards_i915? ( || ( classic gallium ) ) 66 | video_cards_i965? ( classic ) 67 | video_cards_ilo? ( gallium ) 68 | video_cards_nouveau? ( || ( classic gallium ) ) 69 | video_cards_radeon? ( || ( classic gallium ) 70 | gallium? ( x86? ( llvm ) amd64? ( llvm ) ) ) 71 | video_cards_r100? ( classic ) 72 | video_cards_r200? ( classic ) 73 | video_cards_r300? ( gallium x86? ( llvm ) amd64? ( llvm ) ) 74 | video_cards_r600? ( gallium ) 75 | video_cards_radeonsi? ( gallium llvm ) 76 | video_cards_vmware? ( gallium ) 77 | ${PYTHON_REQUIRED_USE} 78 | " 79 | 80 | LIBDRM_DEPSTRING=">=x11-libs/libdrm-2.4.72" 81 | # keep correct libdrm and dri2proto dep 82 | # keep blocks in rdepend for binpkg 83 | RDEPEND=" 84 | !=app-eselect/eselect-opengl-1.3.0 90 | >=dev-libs/expat-2.1.0-r3:=[${MULTILIB_USEDEP}] 91 | >=x11-libs/libX11-1.6.2:=[${MULTILIB_USEDEP}] 92 | >=x11-libs/libxshmfence-1.1:=[${MULTILIB_USEDEP}] 93 | >=x11-libs/libXdamage-1.1.4-r1:=[${MULTILIB_USEDEP}] 94 | >=x11-libs/libXext-1.3.2:=[${MULTILIB_USEDEP}] 95 | >=x11-libs/libXxf86vm-1.1.3:=[${MULTILIB_USEDEP}] 96 | >=x11-libs/libxcb-1.9.3:=[${MULTILIB_USEDEP}] 97 | x11-libs/libXfixes:=[${MULTILIB_USEDEP}] 98 | llvm? ( !kernel_FreeBSD? ( 99 | video_cards_radeonsi? ( virtual/libelf:0=[${MULTILIB_USEDEP}] ) 100 | !video_cards_r600? ( 101 | video_cards_radeon? ( virtual/libelf:0=[${MULTILIB_USEDEP}] ) 102 | ) ) 103 | >=sys-devel/llvm-3.6.0:=[${MULTILIB_USEDEP}] 104 | ) 105 | nettle? ( dev-libs/nettle:=[${MULTILIB_USEDEP}] ) 106 | !nettle? ( 107 | gcrypt? ( dev-libs/libgcrypt:=[${MULTILIB_USEDEP}] ) 108 | !gcrypt? ( 109 | libressl? ( dev-libs/libressl:=[${MULTILIB_USEDEP}] ) 110 | !libressl? ( dev-libs/openssl:=[${MULTILIB_USEDEP}] ) 111 | ) 112 | ) 113 | opencl? ( 114 | app-eselect/eselect-opencl 115 | dev-libs/libclc 116 | !kernel_FreeBSD? ( virtual/libelf:0=[${MULTILIB_USEDEP}] ) 117 | ) 118 | openmax? ( >=media-libs/libomxil-bellagio-0.9.3:=[${MULTILIB_USEDEP}] ) 119 | vaapi? ( 120 | >=x11-libs/libva-1.6.0:=[${MULTILIB_USEDEP}] 121 | video_cards_nouveau? ( !<=x11-libs/libva-vdpau-driver-0.7.4-r3 ) 122 | ) 123 | vdpau? ( >=x11-libs/libvdpau-1.1:=[${MULTILIB_USEDEP}] ) 124 | wayland? ( >=dev-libs/wayland-1.2.0:=[${MULTILIB_USEDEP}] ) 125 | xvmc? ( >=x11-libs/libXvMC-1.0.8:=[${MULTILIB_USEDEP}] ) 126 | ${LIBDRM_DEPSTRING}[video_cards_freedreno?,video_cards_nouveau?,video_cards_vc4?,video_cards_vmware?,${MULTILIB_USEDEP}] 127 | " 128 | for card in ${INTEL_CARDS}; do 129 | RDEPEND="${RDEPEND} 130 | video_cards_${card}? ( ${LIBDRM_DEPSTRING}[video_cards_intel] ) 131 | " 132 | done 133 | 134 | for card in ${RADEON_CARDS}; do 135 | RDEPEND="${RDEPEND} 136 | video_cards_${card}? ( ${LIBDRM_DEPSTRING}[video_cards_radeon] ) 137 | " 138 | done 139 | RDEPEND="${RDEPEND} 140 | video_cards_radeonsi? ( ${LIBDRM_DEPSTRING}[video_cards_amdgpu] ) 141 | " 142 | 143 | # FIXME: kill the sys-devel/llvm[video_cards_radeon] compat once 144 | # LLVM < 3.9 is out of the game 145 | DEPEND="${RDEPEND} 146 | llvm? ( 147 | video_cards_radeonsi? ( || ( 148 | sys-devel/llvm[llvm_targets_AMDGPU] 149 | sys-devel/llvm[video_cards_radeon] 150 | ) ) 151 | ) 152 | opencl? ( 153 | >=sys-devel/llvm-3.4.2:=[${MULTILIB_USEDEP}] 154 | >=sys-devel/clang-3.4.2:=[${MULTILIB_USEDEP}] 155 | >=sys-devel/gcc-4.6 156 | ) 157 | sys-devel/gettext 158 | virtual/pkgconfig 159 | valgrind? ( dev-util/valgrind ) 160 | >=x11-proto/dri2proto-2.8-r1:=[${MULTILIB_USEDEP}] 161 | dri3? ( 162 | >=x11-proto/dri3proto-1.0:=[${MULTILIB_USEDEP}] 163 | >=x11-proto/presentproto-1.0:=[${MULTILIB_USEDEP}] 164 | ) 165 | >=x11-proto/glproto-1.4.17-r1:=[${MULTILIB_USEDEP}] 166 | >=x11-proto/xextproto-7.2.1-r1:=[${MULTILIB_USEDEP}] 167 | >=x11-proto/xf86driproto-2.1.1-r1:=[${MULTILIB_USEDEP}] 168 | >=x11-proto/xf86vidmodeproto-2.3.1-r1:=[${MULTILIB_USEDEP}] 169 | " 170 | [[ ${PV} == 9999 ]] && DEPEND+=" 171 | sys-devel/bison 172 | sys-devel/flex 173 | ${PYTHON_DEPS} 174 | $(python_gen_any_dep ">=dev-python/mako-0.7.3[\${PYTHON_USEDEP}]") 175 | " 176 | 177 | S="${WORKDIR}/${MY_P}" 178 | EGIT_CHECKOUT_DIR=${S} 179 | 180 | QA_WX_LOAD=" 181 | x86? ( 182 | !pic? ( 183 | usr/lib*/libglapi.so.0.0.0 184 | usr/lib*/libGLESv1_CM.so.1.1.0 185 | usr/lib*/libGLESv2.so.2.0.0 186 | usr/lib*/libGL.so.1.2.0 187 | usr/lib*/libOSMesa.so.8.0.0 188 | ) 189 | )" 190 | 191 | pkg_setup() { 192 | # warning message for bug 459306 193 | if use llvm && has_version sys-devel/llvm[!debug=]; then 194 | ewarn "Mismatch between debug USE flags in media-libs/mesa and sys-devel/llvm" 195 | ewarn "detected! This can cause problems. For details, see bug 459306." 196 | fi 197 | 198 | python-any-r1_pkg_setup 199 | } 200 | 201 | src_prepare() { 202 | epatch "${FILESDIR}/mesa-13.0.2-liverpool.patch" 203 | [[ ${PV} == 9999 ]] && eautoreconf 204 | } 205 | 206 | multilib_src_configure() { 207 | local myconf 208 | 209 | if use classic; then 210 | # Configurable DRI drivers 211 | driver_enable swrast 212 | 213 | # Intel code 214 | driver_enable video_cards_i915 i915 215 | driver_enable video_cards_i965 i965 216 | if ! use video_cards_i915 && \ 217 | ! use video_cards_i965; then 218 | driver_enable video_cards_intel i915 i965 219 | fi 220 | 221 | # Nouveau code 222 | driver_enable video_cards_nouveau nouveau 223 | 224 | # ATI code 225 | driver_enable video_cards_r100 radeon 226 | driver_enable video_cards_r200 r200 227 | if ! use video_cards_r100 && \ 228 | ! use video_cards_r200; then 229 | driver_enable video_cards_radeon radeon r200 230 | fi 231 | fi 232 | 233 | if use egl; then 234 | myconf+=" --with-egl-platforms=x11$(use wayland && echo ",wayland")$(use gbm && echo ",drm")" 235 | fi 236 | 237 | if use gallium; then 238 | myconf+=" 239 | $(use_enable d3d9 nine) 240 | $(use_enable llvm gallium-llvm) 241 | $(use_enable openmax omx) 242 | $(use_enable vaapi va) 243 | $(use_enable vdpau) 244 | $(use_enable xa) 245 | $(use_enable xvmc) 246 | " 247 | use vaapi && myconf+=" --with-va-libdir=/usr/$(get_libdir)/va/drivers" 248 | 249 | gallium_enable swrast 250 | gallium_enable video_cards_vc4 vc4 251 | gallium_enable video_cards_vmware svga 252 | gallium_enable video_cards_nouveau nouveau 253 | gallium_enable video_cards_i915 i915 254 | gallium_enable video_cards_ilo ilo 255 | if ! use video_cards_i915 && \ 256 | ! use video_cards_i965; then 257 | gallium_enable video_cards_intel i915 258 | fi 259 | 260 | gallium_enable video_cards_r300 r300 261 | gallium_enable video_cards_r600 r600 262 | gallium_enable video_cards_radeonsi radeonsi 263 | if ! use video_cards_r300 && \ 264 | ! use video_cards_r600; then 265 | gallium_enable video_cards_radeon r300 r600 266 | fi 267 | 268 | gallium_enable video_cards_freedreno freedreno 269 | # opencl stuff 270 | if use opencl; then 271 | myconf+=" 272 | $(use_enable opencl) 273 | --with-clang-libdir="${EPREFIX}/usr/lib" 274 | " 275 | fi 276 | fi 277 | 278 | if use vulkan; then 279 | vulkan_enable video_cards_i965 intel 280 | vulkan_enable video_cards_radeonsi radeon 281 | fi 282 | 283 | # x86 hardened pax_kernel needs glx-rts, bug 240956 284 | if [[ ${ABI} == x86 ]]; then 285 | myconf+=" $(use_enable pax_kernel glx-read-only-text)" 286 | fi 287 | 288 | # on abi_x86_32 hardened we need to have asm disable 289 | if [[ ${ABI} == x86* ]] && use pic; then 290 | myconf+=" --disable-asm" 291 | fi 292 | 293 | if use gallium; then 294 | myconf+=" $(use_enable osmesa gallium-osmesa)" 295 | else 296 | myconf+=" $(use_enable osmesa)" 297 | fi 298 | 299 | # build fails with BSD indent, bug #428112 300 | use userland_GNU || export INDENT=cat 301 | 302 | ECONF_SOURCE="${S}" \ 303 | econf \ 304 | --enable-dri \ 305 | --enable-glx \ 306 | --enable-shared-glapi \ 307 | --disable-shader-cache \ 308 | $(use_enable !bindist texture-float) \ 309 | $(use_enable d3d9 nine) \ 310 | $(use_enable debug) \ 311 | $(use_enable dri3) \ 312 | $(use_enable egl) \ 313 | $(use_enable gbm) \ 314 | $(use_enable gles1) \ 315 | $(use_enable gles2) \ 316 | $(use_enable nptl glx-tls) \ 317 | --enable-valgrind=$(usex valgrind auto no) \ 318 | --enable-llvm-shared-libs \ 319 | --with-dri-drivers=${DRI_DRIVERS} \ 320 | --with-gallium-drivers=${GALLIUM_DRIVERS} \ 321 | --with-vulkan-drivers=${VULKAN_DRIVERS} \ 322 | --with-sha1=$(usex nettle libnettle $(usex gcrypt libgcrypt libcrypto)) \ 323 | PYTHON2="${PYTHON}" \ 324 | ${myconf} 325 | } 326 | 327 | multilib_src_install() { 328 | emake install DESTDIR="${D}" 329 | 330 | if use classic || use gallium; then 331 | ebegin "Moving DRI/Gallium drivers for dynamic switching" 332 | local gallium_drivers=( i915_dri.so i965_dri.so r300_dri.so r600_dri.so swrast_dri.so ) 333 | keepdir /usr/$(get_libdir)/dri 334 | dodir /usr/$(get_libdir)/mesa 335 | for x in ${gallium_drivers[@]}; do 336 | if [ -f "$(get_libdir)/gallium/${x}" ]; then 337 | mv -f "${ED}/usr/$(get_libdir)/dri/${x}" "${ED}/usr/$(get_libdir)/dri/${x/_dri.so/g_dri.so}" \ 338 | || die "Failed to move ${x}" 339 | fi 340 | done 341 | if use classic; then 342 | emake -C "${BUILD_DIR}/src/mesa/drivers/dri" DESTDIR="${D}" install 343 | fi 344 | for x in "${ED}"/usr/$(get_libdir)/dri/*.so; do 345 | if [ -f ${x} -o -L ${x} ]; then 346 | mv -f "${x}" "${x/dri/mesa}" \ 347 | || die "Failed to move ${x}" 348 | fi 349 | done 350 | pushd "${ED}"/usr/$(get_libdir)/dri || die "pushd failed" 351 | ln -s ../mesa/*.so . || die "Creating symlink failed" 352 | # remove symlinks to drivers known to eselect 353 | for x in ${gallium_drivers[@]}; do 354 | if [ -f ${x} -o -L ${x} ]; then 355 | rm "${x}" || die "Failed to remove ${x}" 356 | fi 357 | done 358 | popd 359 | eend $? 360 | fi 361 | if use opencl; then 362 | ebegin "Moving Gallium/Clover OpenCL implementation for dynamic switching" 363 | local cl_dir="/usr/$(get_libdir)/OpenCL/vendors/mesa" 364 | dodir ${cl_dir}/{lib,include} 365 | if [ -f "${ED}/usr/$(get_libdir)/libOpenCL.so" ]; then 366 | mv -f "${ED}"/usr/$(get_libdir)/libOpenCL.so* \ 367 | "${ED}"${cl_dir} 368 | fi 369 | if [ -f "${ED}/usr/include/CL/opencl.h" ]; then 370 | mv -f "${ED}"/usr/include/CL \ 371 | "${ED}"${cl_dir}/include 372 | fi 373 | eend $? 374 | fi 375 | 376 | if use openmax; then 377 | echo "XDG_DATA_DIRS=\"${EPREFIX}/usr/share/mesa/xdg\"" > "${T}/99mesaxdgomx" 378 | doenvd "${T}"/99mesaxdgomx 379 | keepdir /usr/share/mesa/xdg 380 | fi 381 | } 382 | 383 | multilib_src_install_all() { 384 | prune_libtool_files --all 385 | einstalldocs 386 | 387 | if use !bindist; then 388 | dodoc docs/patents.txt 389 | fi 390 | 391 | # Install config file for eselect mesa 392 | insinto /usr/share/mesa 393 | newins "${FILESDIR}/eselect-mesa.conf.9.2" eselect-mesa.conf 394 | 395 | # Mesa should not install these 396 | if use vulkan; then 397 | rm "${ED}"/usr/include/vulkan/{vulkan.h,vk_platform.h} || die 398 | fi 399 | } 400 | 401 | multilib_src_test() { 402 | if use llvm; then 403 | local llvm_tests='lp_test_arit lp_test_arit lp_test_blend lp_test_blend lp_test_conv lp_test_conv lp_test_format lp_test_format lp_test_printf lp_test_printf' 404 | pushd src/gallium/drivers/llvmpipe >/dev/null || die 405 | emake ${llvm_tests} 406 | pax-mark m ${llvm_tests} 407 | popd >/dev/null || die 408 | fi 409 | emake check 410 | } 411 | 412 | pkg_postinst() { 413 | # Switch to the xorg implementation. 414 | echo 415 | eselect opengl set --use-old ${OPENGL_DIR} 416 | 417 | # Select classic/gallium drivers 418 | if use classic || use gallium; then 419 | eselect mesa set --auto 420 | fi 421 | 422 | # Switch to mesa opencl 423 | if use opencl; then 424 | eselect opencl set --use-old ${PN} 425 | fi 426 | 427 | # run omxregister-bellagio to make the OpenMAX drivers known system-wide 428 | if use openmax; then 429 | ebegin "Registering OpenMAX drivers" 430 | BELLAGIO_SEARCH_PATH="${EPREFIX}/usr/$(get_libdir)/libomxil-bellagio0" \ 431 | OMX_BELLAGIO_REGISTRY=${EPREFIX}/usr/share/mesa/xdg/.omxregister \ 432 | omxregister-bellagio 433 | eend $? 434 | fi 435 | 436 | # warn about patent encumbered texture-float 437 | if use !bindist; then 438 | elog "USE=\"bindist\" was not set. Potentially patent encumbered code was" 439 | elog "enabled. Please see patents.txt for an explanation." 440 | fi 441 | 442 | if ! has_version media-libs/libtxc_dxtn; then 443 | elog "Note that in order to have full S3TC support, it is necessary to install" 444 | elog "media-libs/libtxc_dxtn as well. This may be necessary to get nice" 445 | elog "textures in some apps, and some others even require this to run." 446 | fi 447 | } 448 | 449 | pkg_prerm() { 450 | if use openmax; then 451 | rm "${EPREFIX}"/usr/share/mesa/xdg/.omxregister 452 | fi 453 | } 454 | 455 | # $1 - VIDEO_CARDS flag 456 | # other args - names of DRI drivers to enable 457 | # TODO: avoid code duplication for a more elegant implementation 458 | driver_enable() { 459 | case $# in 460 | # for enabling unconditionally 461 | 1) 462 | DRI_DRIVERS+=",$1" 463 | ;; 464 | *) 465 | if use $1; then 466 | shift 467 | for i in $@; do 468 | DRI_DRIVERS+=",${i}" 469 | done 470 | fi 471 | ;; 472 | esac 473 | } 474 | 475 | gallium_enable() { 476 | case $# in 477 | # for enabling unconditionally 478 | 1) 479 | GALLIUM_DRIVERS+=",$1" 480 | ;; 481 | *) 482 | if use $1; then 483 | shift 484 | for i in $@; do 485 | GALLIUM_DRIVERS+=",${i}" 486 | done 487 | fi 488 | ;; 489 | esac 490 | } 491 | 492 | vulkan_enable() { 493 | case $# in 494 | # for enabling unconditionally 495 | 1) 496 | VULKAN_DRIVERS+=",$1" 497 | ;; 498 | *) 499 | if use $1; then 500 | shift 501 | for i in $@; do 502 | VULKAN_DRIVERS+=",${i}" 503 | done 504 | fi 505 | ;; 506 | esac 507 | } 508 | -------------------------------------------------------------------------------- /media-libs/mesa/metadata.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | x11@gentoo.org 6 | X11 7 | 8 | 9 | Disable patent-encumbered ARB_texture_float, EXT_texture_shared_exponent, and EXT_packed_float extensions. 10 | Build drivers based on the classic architecture. 11 | Enable Direct 3D9 API through Nine state tracker. Can be used together with patched wine. 12 | Enable DRI3 support. 13 | Enable EGL support. 14 | Build drivers based on Gallium3D, the new architecture for 3D graphics drivers. 15 | Use dev-libs/libgcrypt for low level sha1 utility functions. 16 | Enable the Graphics Buffer Manager for EGL on KMS. 17 | Enable GLESv1 support. 18 | Enable GLESv2 support. 19 | Use dev-libs/libressl for low level sha1 utility functions. 20 | Enable LLVM backend for Gallium3D. 21 | Use dev-libs/nettle for low level sha1 utility functions. 22 | Enable the Clover Gallium OpenCL state tracker. 23 | Enable OpenMAX video decode/encode acceleration for Gallium3D. 24 | Use dev-libs/openssl for low level sha1 utility functions. May cause issues with games from Steam. 25 | Build the Mesa library for off-screen rendering. 26 | Enable if the user plans to run the package under a pax enabled hardened kernel 27 | disable optimized assembly code that is not PIC friendly 28 | Compile in valgrind memory hints 29 | Enable the VDPAU acceleration interface for the Gallium3D Video Layer. 30 | Enable Vulkan drivers 31 | Enable support for dev-libs/wayland 32 | Enable the XA (X Acceleration) API for Gallium3D. 33 | Enable the XvMC acceleration interface for the Gallium3D Video Layer. 34 | 35 | 36 | mesa3d 37 | 38 | 39 | -------------------------------------------------------------------------------- /metadata/layout.conf: -------------------------------------------------------------------------------- 1 | masters = gentoo 2 | repo-name = ps4-overlay 3 | thin-manifests = true 4 | -------------------------------------------------------------------------------- /sys-firmware/ps4-ucode/Manifest: -------------------------------------------------------------------------------- 1 | DIST radeon-ucode-20160628.tar 831920 SHA256 342827150d83e2e986e1673dbddb8bf7c63008ae9525de15dfc2284845594a30 SHA512 7ecad7f3c7c734b04a9bf4d01cd7436298ac397fecc97bc0a27d10d26b2c1ee07e5c8428f4ad75dd15aec297a3e15f6c8cc9c227dbb5b6a58a5d9a541d59340e WHIRLPOOL bd1b672eb34853d2fb4c97baf39413bc648584d287bd46a51ae81aaba43faca5702d04a921c798ee6f0f91f5b98a971882f10bb70499c574af3ccfa94796523b 2 | -------------------------------------------------------------------------------- /sys-firmware/ps4-ucode/files/resize_firmware.py: -------------------------------------------------------------------------------- 1 | import zlib, sys, struct 2 | 3 | want_size = int(sys.argv[2]) - 0x100 4 | want_blob_sz = want_size & ~0x7ff 5 | want_jt_sz = want_size & 0x7ff 6 | 7 | print "want: 0x%x / 0x%x / 0x%x (total, blob, jt)" % (want_size, want_blob_sz, want_jt_sz) 8 | 9 | with open(sys.argv[1], "rb") as fd: 10 | hdr = fd.read(0x20) 11 | sub_hdr = fd.read(0xe0) 12 | ucode = fd.read() 13 | 14 | total_size, p1, ucode_size = struct.unpack(" want_blob_sz: 29 | ucode_blob = ucode_blob[:want_blob_sz] 30 | 31 | if ucode_jt_sz < want_jt_sz: 32 | ucode_jt += ucode_jt[-4:] * ((want_jt_sz - ucode_jt_sz) / 4) 33 | elif ucode_jt_sz > want_jt_sz: 34 | ucode_jt = ucode_jt[:want_jt_sz] 35 | 36 | if want_jt_sz > 0: 37 | sub_hdr = struct.pack(" 2 | 3 | 4 | 5 | x11@gentoo.org 6 | X11 7 | 8 | 9 | Install firmware for older chipsets which are optionally supported by AMDGPU 10 | 11 | 12 | -------------------------------------------------------------------------------- /sys-firmware/ps4-ucode/ps4-ucode-20161205.ebuild: -------------------------------------------------------------------------------- 1 | # Copyright 1999-2016 Gentoo Foundation 2 | # Distributed under the terms of the GNU General Public License v2 3 | # $Id$ 4 | 5 | EAPI=5 6 | 7 | inherit linux-info 8 | 9 | DESCRIPTION="Microcode for Liverpool APU" 10 | HOMEPAGE="https://people.freedesktop.org/~agd5f/radeon_ucode/" 11 | SRC_URI="mirror://gentoo/radeon-ucode-20160628.tar" 12 | 13 | LICENSE="radeon-ucode" 14 | SLOT="0" 15 | KEYWORDS="amd64 x86" 16 | IUSE="legacy" 17 | 18 | RDEPEND=">sys-kernel/linux-firmware-20150812" 19 | 20 | S=${WORKDIR}/radeon 21 | 22 | src_compile() { 23 | python "${FILESDIR}"/resize_firmware.py hawaii_pfp.bin 17024 liverpool_pfp.bin 24 | python "${FILESDIR}"/resize_firmware.py hawaii_me.bin 17024 liverpool_me.bin 25 | } 26 | 27 | src_install() { 28 | insinto /lib/firmware/radeon 29 | 30 | for unit in mec mec2 sdma sdma1 uvd vce; do 31 | newins kaveri_${unit}.bin liverpool_${unit}.bin 32 | done 33 | 34 | doins liverpool_pfp.bin 35 | doins liverpool_me.bin 36 | newins hawaii_ce.bin liverpool_ce.bin 37 | } 38 | 39 | pkg_postinst() { 40 | ewarn "If you build in AMDGPU into your kernel, it will by default use the" 41 | ewarn "outdated GPU microcode that ships with the PS4 operating system," 42 | ewarn "as provided by ps4-kexec. In order to take advantage of this updated" 43 | ewarn "microcode, you must build the contents of /lib/firmware/radeon into" 44 | ewarn "your initramfs, which will then override the legacy versions." 45 | ewarn 46 | ewarn "Conversely, this package does not provide liverpool_rlc.bin, for" 47 | ewarn "which you must use the legacy version provided by ps4-kexec. If" 48 | ewarn "you are building amdgpu/radeon as a module, you must copy it out" 49 | ewarn "from the initramfs (as provided by ps4-kexec) into your filesystem" 50 | ewarn "so it can continue to be used after boot." 51 | ewarn 52 | ewarn "You may also want to install sys-kernel/linux-firmware, and also" 53 | ewarn "copy /lib/firmware/mrvl/sd8797_uapsta.bin to your initramfs if you" 54 | ewarn "build your WLAN/Bluetooth driver into the kernel." 55 | } 56 | -------------------------------------------------------------------------------- /x11-drivers/xf86-video-amdgpu/Manifest: -------------------------------------------------------------------------------- 1 | DIST xf86-video-amdgpu-1.2.0.tar.bz2 388108 SHA256 275b1aac5f127f55ba3d7480a1df89eace1d02650e24e46908067fc875e76c8f SHA512 92253848e81e41ec971f0a706639eda4b5231b6944148e21bc0f58ac1d10b963a76a5f10f8ca7ec4b3a631306636ec31efa3e62433f5b95ebdb26e2b0561d0f2 WHIRLPOOL 5437497626f443abda8bdc1d98fea5e0b37874ccd81150b8299a8d5c6393e67e1829c4b14cb017a415da5f7d500f475bc4accc9b8a7d9eaf0dfcf98147c24dcd 2 | -------------------------------------------------------------------------------- /x11-drivers/xf86-video-amdgpu/files/xf86-video-amdgpu-1.2.0-liverpool.patch: -------------------------------------------------------------------------------- 1 | diff -urN xf86-video-amdgpu-1.2.0-old/src/amdgpu_chipinfo_gen.h xf86-video-amdgpu-1.2.0/src/amdgpu_chipinfo_gen.h 2 | --- xf86-video-amdgpu-1.2.0-old/src/amdgpu_chipinfo_gen.h 2017-01-02 17:32:49.432909312 +0100 3 | +++ xf86-video-amdgpu-1.2.0/src/amdgpu_chipinfo_gen.h 2017-01-02 17:34:49.724788279 +0100 4 | @@ -116,6 +116,7 @@ 5 | { 0x985D, CHIP_FAMILY_MULLINS }, 6 | { 0x985E, CHIP_FAMILY_MULLINS }, 7 | { 0x985F, CHIP_FAMILY_MULLINS }, 8 | + { 0x9920, CHIP_FAMILY_LIVERPOOL }, 9 | { 0x1304, CHIP_FAMILY_KAVERI }, 10 | { 0x1305, CHIP_FAMILY_KAVERI }, 11 | { 0x1306, CHIP_FAMILY_KAVERI }, 12 | diff -urN xf86-video-amdgpu-1.2.0-old/src/amdgpu_chipset_gen.h xf86-video-amdgpu-1.2.0/src/amdgpu_chipset_gen.h 13 | --- xf86-video-amdgpu-1.2.0-old/src/amdgpu_chipset_gen.h 2017-01-02 17:32:49.431909350 +0100 14 | +++ xf86-video-amdgpu-1.2.0/src/amdgpu_chipset_gen.h 2017-01-02 17:34:49.724788279 +0100 15 | @@ -116,6 +116,7 @@ 16 | { PCI_CHIP_MULLINS_985D, "MULLINS" }, 17 | { PCI_CHIP_MULLINS_985E, "MULLINS" }, 18 | { PCI_CHIP_MULLINS_985F, "MULLINS" }, 19 | + { PCI_CHIP_LIVERPOOL_9920, "LIVERPOOL" }, 20 | { PCI_CHIP_KAVERI_1304, "KAVERI" }, 21 | { PCI_CHIP_KAVERI_1305, "KAVERI" }, 22 | { PCI_CHIP_KAVERI_1306, "KAVERI" }, 23 | @@ -203,6 +204,7 @@ 24 | { 0, "BONAIRE" }, 25 | { 0, "KABINI" }, 26 | { 0, "MULLINS" }, 27 | + { 0, "LIVERPOOL" }, 28 | { 0, "KAVERI" }, 29 | { 0, "HAWAII" }, 30 | { 0, "TOPAZ" }, 31 | diff -urN xf86-video-amdgpu-1.2.0-old/src/amdgpu_kms.c xf86-video-amdgpu-1.2.0/src/amdgpu_kms.c 32 | --- xf86-video-amdgpu-1.2.0-old/src/amdgpu_kms.c 2017-01-02 17:32:49.431909350 +0100 33 | +++ xf86-video-amdgpu-1.2.0/src/amdgpu_kms.c 2017-01-02 17:36:10.957075719 +0100 34 | @@ -1415,8 +1415,9 @@ 35 | else 36 | pAMDGPUEnt->HasCRTC2 = TRUE; 37 | 38 | - if (info->ChipFamily >= CHIP_FAMILY_TAHITI && 39 | - info->ChipFamily <= CHIP_FAMILY_HAINAN) { 40 | + if ((info->ChipFamily >= CHIP_FAMILY_TAHITI && 41 | + info->ChipFamily <= CHIP_FAMILY_HAINAN) || 42 | + info->ChipFamily == CHIP_FAMILY_LIVERPOOL) { 43 | info->cursor_w = CURSOR_WIDTH; 44 | info->cursor_h = CURSOR_HEIGHT; 45 | } else { 46 | diff -urN xf86-video-amdgpu-1.2.0-old/src/amdgpu_pci_chipset_gen.h xf86-video-amdgpu-1.2.0/src/amdgpu_pci_chipset_gen.h 47 | --- xf86-video-amdgpu-1.2.0-old/src/amdgpu_pci_chipset_gen.h 2017-01-02 17:32:49.432909312 +0100 48 | +++ xf86-video-amdgpu-1.2.0/src/amdgpu_pci_chipset_gen.h 2017-01-02 17:34:49.724788279 +0100 49 | @@ -116,6 +116,7 @@ 50 | { PCI_CHIP_MULLINS_985D, PCI_CHIP_MULLINS_985D, RES_SHARED_VGA }, 51 | { PCI_CHIP_MULLINS_985E, PCI_CHIP_MULLINS_985E, RES_SHARED_VGA }, 52 | { PCI_CHIP_MULLINS_985F, PCI_CHIP_MULLINS_985F, RES_SHARED_VGA }, 53 | + { PCI_CHIP_LIVERPOOL_9920, PCI_CHIP_LIVERPOOL_9920, RES_SHARED_VGA }, 54 | { PCI_CHIP_KAVERI_1304, PCI_CHIP_KAVERI_1304, RES_SHARED_VGA }, 55 | { PCI_CHIP_KAVERI_1305, PCI_CHIP_KAVERI_1305, RES_SHARED_VGA }, 56 | { PCI_CHIP_KAVERI_1306, PCI_CHIP_KAVERI_1306, RES_SHARED_VGA }, 57 | diff -urN xf86-video-amdgpu-1.2.0-old/src/amdgpu_pci_device_match_gen.h xf86-video-amdgpu-1.2.0/src/amdgpu_pci_device_match_gen.h 58 | --- xf86-video-amdgpu-1.2.0-old/src/amdgpu_pci_device_match_gen.h 2017-01-02 17:32:49.433909274 +0100 59 | +++ xf86-video-amdgpu-1.2.0/src/amdgpu_pci_device_match_gen.h 2017-01-02 17:34:49.724788279 +0100 60 | @@ -116,6 +116,7 @@ 61 | ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985D, 0 ), 62 | ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985E, 0 ), 63 | ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985F, 0 ), 64 | + ATI_DEVICE_MATCH( PCI_CHIP_LIVERPOOL_9920, 0 ), 65 | ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1304, 0 ), 66 | ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1305, 0 ), 67 | ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1306, 0 ), 68 | diff -urN xf86-video-amdgpu-1.2.0-old/src/amdgpu_probe.h xf86-video-amdgpu-1.2.0/src/amdgpu_probe.h 69 | --- xf86-video-amdgpu-1.2.0-old/src/amdgpu_probe.h 2017-01-02 17:32:49.432909312 +0100 70 | +++ xf86-video-amdgpu-1.2.0/src/amdgpu_probe.h 2017-01-02 17:36:42.908109289 +0100 71 | @@ -68,6 +68,7 @@ 72 | CHIP_FAMILY_KABINI, 73 | CHIP_FAMILY_HAWAII, 74 | CHIP_FAMILY_MULLINS, 75 | + CHIP_FAMILY_LIVERPOOL, 76 | CHIP_FAMILY_TOPAZ, 77 | CHIP_FAMILY_TONGA, 78 | CHIP_FAMILY_CARRIZO, 79 | diff -urN xf86-video-amdgpu-1.2.0-old/src/ati_pciids_gen.h xf86-video-amdgpu-1.2.0/src/ati_pciids_gen.h 80 | --- xf86-video-amdgpu-1.2.0-old/src/ati_pciids_gen.h 2017-01-02 17:32:49.432909312 +0100 81 | +++ xf86-video-amdgpu-1.2.0/src/ati_pciids_gen.h 2017-01-02 17:34:49.724788279 +0100 82 | @@ -114,6 +114,7 @@ 83 | #define PCI_CHIP_MULLINS_985D 0x985D 84 | #define PCI_CHIP_MULLINS_985E 0x985E 85 | #define PCI_CHIP_MULLINS_985F 0x985F 86 | +#define PCI_CHIP_LIVERPOOL_9920 0x9920 87 | #define PCI_CHIP_KAVERI_1304 0x1304 88 | #define PCI_CHIP_KAVERI_1305 0x1305 89 | #define PCI_CHIP_KAVERI_1306 0x1306 90 | diff -urN xf86-video-amdgpu-1.2.0-old/src/pcidb/ati_pciids.csv xf86-video-amdgpu-1.2.0/src/pcidb/ati_pciids.csv 91 | --- xf86-video-amdgpu-1.2.0-old/src/pcidb/ati_pciids.csv 2017-01-02 17:32:49.433909274 +0100 92 | +++ xf86-video-amdgpu-1.2.0/src/pcidb/ati_pciids.csv 2017-01-02 17:34:41.574177338 +0100 93 | @@ -115,6 +115,7 @@ 94 | "0x985D","MULLINS_985D","MULLINS","MULLINS" 95 | "0x985E","MULLINS_985E","MULLINS","MULLINS" 96 | "0x985F","MULLINS_985F","MULLINS","MULLINS" 97 | +"0x9920","LIVERPOOL_9920","LIVERPOOL","LIVERPOOL" 98 | "0x1304","KAVERI_1304","KAVERI","KAVERI" 99 | "0x1305","KAVERI_1305","KAVERI","KAVERI" 100 | "0x1306","KAVERI_1306","KAVERI","KAVERI" 101 | -------------------------------------------------------------------------------- /x11-drivers/xf86-video-amdgpu/metadata.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | x11@gentoo.org 6 | X11 7 | 8 | 9 | Enable Glamor OpenGL 2D acceleration 10 | 11 | 12 | -------------------------------------------------------------------------------- /x11-drivers/xf86-video-amdgpu/xf86-video-amdgpu-1.2.0.ebuild: -------------------------------------------------------------------------------- 1 | # Copyright 1999-2016 Gentoo Foundation 2 | # Distributed under the terms of the GNU General Public License v2 3 | # $Id$ 4 | 5 | EAPI=5 6 | XORG_DRI="always" 7 | inherit xorg-2 8 | 9 | if [[ ${PV} == 9999* ]]; then 10 | XORG_EAUTORECONF=yes 11 | SRC_URI="" 12 | KEYWORDS="" 13 | else 14 | KEYWORDS="~amd64 ~x86" 15 | fi 16 | 17 | DESCRIPTION="Accelerated Open Source driver for AMDGPU cards" 18 | 19 | IUSE="glamor" 20 | 21 | RDEPEND="x11-libs/libdrm[video_cards_amdgpu] 22 | x11-base/xorg-server[glamor(-)?]" 23 | DEPEND="${RDEPEND}" 24 | 25 | src_prepare() { 26 | epatch "${FILESDIR}/xf86-video-amdgpu-1.2.0-liverpool.patch" 27 | xorg-2_src_prepare 28 | } 29 | 30 | src_configure() { 31 | XORG_CONFIGURE_OPTIONS="$(use_enable glamor)" 32 | xorg-2_src_configure 33 | } 34 | -------------------------------------------------------------------------------- /x11-drivers/xf86-video-ati/Manifest: -------------------------------------------------------------------------------- 1 | DIST xf86-video-ati-7.8.0.tar.bz2 845702 SHA256 401f5de772928f3dc4ce43a885adb0a47a2f61aa4a9e45d2ab3d184136a9d6fa SHA512 e09b7aca819656359d32b11f4314f2ad77b7a28d481b2cf17ea62f2e2385f9b40f568d5c76360c800c60c00671f0262277cdefde4c0744f2ed9b3b2fa90a37a9 WHIRLPOOL b5e8a4cf546bb56f1e481e9dc7da8dc850c4fb231d10c592a7e2ffbfb9da0a64edb1b208b326283a6a94e4c0c5aefe5e4a04a984475e7ac5a5bab757ad0f990b 2 | -------------------------------------------------------------------------------- /x11-drivers/xf86-video-ati/files/xf86-video-ati-7.6.1-liverpool.patch: -------------------------------------------------------------------------------- 1 | diff -ur xf86-video-ati-7.6.1-orig/src/ati_pciids_gen.h xf86-video-ati-7.6.1/src/ati_pciids_gen.h 2 | --- xf86-video-ati-7.6.1-orig/src/ati_pciids_gen.h 2016-01-04 22:17:14.431957071 +0000 3 | +++ xf86-video-ati-7.6.1/src/ati_pciids_gen.h 2016-01-04 23:38:53.747444976 +0000 4 | @@ -746,6 +746,7 @@ 5 | #define PCI_CHIP_MULLINS_985D 0x985D 6 | #define PCI_CHIP_MULLINS_985E 0x985E 7 | #define PCI_CHIP_MULLINS_985F 0x985F 8 | +#define PCI_CHIP_LIVERPOOL_9920 0x9920 9 | #define PCI_CHIP_KAVERI_1304 0x1304 10 | #define PCI_CHIP_KAVERI_1305 0x1305 11 | #define PCI_CHIP_KAVERI_1306 0x1306 12 | diff -ur xf86-video-ati-7.6.1-orig/src/pcidb/ati_pciids.csv xf86-video-ati-7.6.1/src/pcidb/ati_pciids.csv 13 | --- xf86-video-ati-7.6.1-orig/src/pcidb/ati_pciids.csv 2016-01-04 22:17:14.433957093 +0000 14 | +++ xf86-video-ati-7.6.1/src/pcidb/ati_pciids.csv 2016-01-04 23:38:41.482305297 +0000 15 | @@ -747,6 +747,7 @@ 16 | "0x985D","MULLINS_985D","MULLINS",1,1,,,1,"MULLINS" 17 | "0x985E","MULLINS_985E","MULLINS",1,1,,,1,"MULLINS" 18 | "0x985F","MULLINS_985F","MULLINS",1,1,,,1,"MULLINS" 19 | +"0x9920","LIVERPOOL_9920","LIVERPOOL",,1,,,1,"LIVERPOOL" 20 | "0x1304","KAVERI_1304","KAVERI",1,1,,,1,"KAVERI" 21 | "0x1305","KAVERI_1305","KAVERI",,1,,,1,"KAVERI" 22 | "0x1306","KAVERI_1306","KAVERI",1,1,,,1,"KAVERI" 23 | diff -ur xf86-video-ati-7.6.1-orig/src/radeon_chipinfo_gen.h xf86-video-ati-7.6.1/src/radeon_chipinfo_gen.h 24 | --- xf86-video-ati-7.6.1-orig/src/radeon_chipinfo_gen.h 2016-01-04 22:17:14.431957071 +0000 25 | +++ xf86-video-ati-7.6.1/src/radeon_chipinfo_gen.h 2016-01-04 23:38:53.747444976 +0000 26 | @@ -666,6 +666,7 @@ 27 | { 0x985D, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, 28 | { 0x985E, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, 29 | { 0x985F, CHIP_FAMILY_MULLINS, 1, 1, 0, 0, 1 }, 30 | + { 0x9920, CHIP_FAMILY_LIVERPOOL, 0, 1, 0, 0, 1 }, 31 | { 0x1304, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, 32 | { 0x1305, CHIP_FAMILY_KAVERI, 0, 1, 0, 0, 1 }, 33 | { 0x1306, CHIP_FAMILY_KAVERI, 1, 1, 0, 0, 1 }, 34 | diff -ur xf86-video-ati-7.6.1-orig/src/radeon_chipset_gen.h xf86-video-ati-7.6.1/src/radeon_chipset_gen.h 35 | --- xf86-video-ati-7.6.1-orig/src/radeon_chipset_gen.h 2016-01-04 22:17:14.431957071 +0000 36 | +++ xf86-video-ati-7.6.1/src/radeon_chipset_gen.h 2016-01-04 23:38:53.747444976 +0000 37 | @@ -666,6 +666,7 @@ 38 | { PCI_CHIP_MULLINS_985D, "MULLINS" }, 39 | { PCI_CHIP_MULLINS_985E, "MULLINS" }, 40 | { PCI_CHIP_MULLINS_985F, "MULLINS" }, 41 | + { PCI_CHIP_LIVERPOOL_9920, "LIVERPOOL" }, 42 | { PCI_CHIP_KAVERI_1304, "KAVERI" }, 43 | { PCI_CHIP_KAVERI_1305, "KAVERI" }, 44 | { PCI_CHIP_KAVERI_1306, "KAVERI" }, 45 | diff -ur xf86-video-ati-7.6.1-orig/src/radeon_kms.c xf86-video-ati-7.6.1/src/radeon_kms.c 46 | --- xf86-video-ati-7.6.1-orig/src/radeon_kms.c 2016-01-04 22:17:14.432957082 +0000 47 | +++ xf86-video-ati-7.6.1/src/radeon_kms.c 2016-01-04 23:40:00.289199008 +0000 48 | @@ -1264,7 +1264,8 @@ 49 | } 50 | 51 | /* set cursor size */ 52 | - if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) { 53 | + if (info->ChipFamily >= CHIP_FAMILY_BONAIRE && 54 | + info->ChipFamily != CHIP_FAMILY_LIVERPOOL) { 55 | info->cursor_w = CURSOR_WIDTH_CIK; 56 | info->cursor_h = CURSOR_HEIGHT_CIK; 57 | } else { 58 | diff -ur xf86-video-ati-7.6.1-orig/src/radeon_pci_chipset_gen.h xf86-video-ati-7.6.1/src/radeon_pci_chipset_gen.h 59 | --- xf86-video-ati-7.6.1-orig/src/radeon_pci_chipset_gen.h 2016-01-04 22:17:14.430957060 +0000 60 | +++ xf86-video-ati-7.6.1/src/radeon_pci_chipset_gen.h 2016-01-04 23:38:53.747444976 +0000 61 | @@ -666,6 +666,7 @@ 62 | { PCI_CHIP_MULLINS_985D, PCI_CHIP_MULLINS_985D, RES_SHARED_VGA }, 63 | { PCI_CHIP_MULLINS_985E, PCI_CHIP_MULLINS_985E, RES_SHARED_VGA }, 64 | { PCI_CHIP_MULLINS_985F, PCI_CHIP_MULLINS_985F, RES_SHARED_VGA }, 65 | + { PCI_CHIP_LIVERPOOL_9920, PCI_CHIP_LIVERPOOL_9920, RES_SHARED_VGA }, 66 | { PCI_CHIP_KAVERI_1304, PCI_CHIP_KAVERI_1304, RES_SHARED_VGA }, 67 | { PCI_CHIP_KAVERI_1305, PCI_CHIP_KAVERI_1305, RES_SHARED_VGA }, 68 | { PCI_CHIP_KAVERI_1306, PCI_CHIP_KAVERI_1306, RES_SHARED_VGA }, 69 | diff -ur xf86-video-ati-7.6.1-orig/src/radeon_pci_device_match_gen.h xf86-video-ati-7.6.1/src/radeon_pci_device_match_gen.h 70 | --- xf86-video-ati-7.6.1-orig/src/radeon_pci_device_match_gen.h 2016-01-04 22:17:14.431957071 +0000 71 | +++ xf86-video-ati-7.6.1/src/radeon_pci_device_match_gen.h 2016-01-04 23:38:53.747444976 +0000 72 | @@ -666,6 +666,7 @@ 73 | ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985D, 0 ), 74 | ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985E, 0 ), 75 | ATI_DEVICE_MATCH( PCI_CHIP_MULLINS_985F, 0 ), 76 | + ATI_DEVICE_MATCH( PCI_CHIP_LIVERPOOL_9920, 0 ), 77 | ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1304, 0 ), 78 | ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1305, 0 ), 79 | ATI_DEVICE_MATCH( PCI_CHIP_KAVERI_1306, 0 ), 80 | diff -ur xf86-video-ati-7.6.1-orig/src/radeon_probe.h xf86-video-ati-7.6.1/src/radeon_probe.h 81 | --- xf86-video-ati-7.6.1-orig/src/radeon_probe.h 2016-01-04 22:17:14.433957093 +0000 82 | +++ xf86-video-ati-7.6.1/src/radeon_probe.h 2016-01-04 23:40:29.938534549 +0000 83 | @@ -115,6 +115,7 @@ 84 | CHIP_FAMILY_BONAIRE, 85 | CHIP_FAMILY_KAVERI, 86 | CHIP_FAMILY_KABINI, 87 | + CHIP_FAMILY_LIVERPOOL, 88 | CHIP_FAMILY_HAWAII, 89 | CHIP_FAMILY_MULLINS, 90 | CHIP_FAMILY_LAST 91 | -------------------------------------------------------------------------------- /x11-drivers/xf86-video-ati/metadata.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | x11@gentoo.org 6 | X11 7 | 8 | 9 | Enable Glamor OpenGL 2D acceleration 10 | 11 | 12 | -------------------------------------------------------------------------------- /x11-drivers/xf86-video-ati/xf86-video-ati-7.8.0.ebuild: -------------------------------------------------------------------------------- 1 | # Copyright 1999-2016 Gentoo Foundation 2 | # Distributed under the terms of the GNU General Public License v2 3 | # $Id$ 4 | 5 | EAPI=5 6 | 7 | XORG_DRI=always 8 | inherit linux-info xorg-2 9 | 10 | DESCRIPTION="ATI video driver" 11 | HOMEPAGE="http://www.x.org/wiki/ati/" 12 | 13 | KEYWORDS="~alpha ~amd64 ~ia64 ~ppc ~ppc64 ~sparc ~x86 ~amd64-fbsd" 14 | IUSE="+glamor udev" 15 | 16 | RDEPEND=">=x11-libs/libdrm-2.4.58[video_cards_radeon] 17 | >=x11-libs/libpciaccess-0.8.0 18 | glamor? ( x11-base/xorg-server[glamor] ) 19 | udev? ( virtual/udev )" 20 | DEPEND="${RDEPEND} 21 | x11-proto/fontsproto 22 | x11-proto/randrproto 23 | x11-proto/renderproto 24 | x11-proto/videoproto 25 | x11-proto/xextproto 26 | x11-proto/xf86driproto 27 | x11-proto/xproto" 28 | 29 | pkg_pretend() { 30 | if use kernel_linux ; then 31 | if kernel_is -ge 3 9; then 32 | CONFIG_CHECK="~!DRM_RADEON_UMS ~!FB_RADEON" 33 | else 34 | CONFIG_CHECK="~DRM_RADEON_KMS ~!FB_RADEON" 35 | fi 36 | fi 37 | check_extra_config 38 | } 39 | 40 | src_prepare() { 41 | epatch "${FILESDIR}/xf86-video-ati-7.6.1-liverpool.patch" 42 | xorg-2_src_prepare 43 | } 44 | 45 | src_configure() { 46 | XORG_CONFIGURE_OPTIONS=( 47 | $(use_enable glamor) 48 | $(use_enable udev) 49 | ) 50 | xorg-2_src_configure 51 | } 52 | -------------------------------------------------------------------------------- /x11-libs/libdrm/Manifest: -------------------------------------------------------------------------------- 1 | DIST libdrm-2.4.74.tar.bz2 781730 SHA256 d80dd5a76c401f4c8756dcccd999c63d7e0a3bad258d96a829055cfd86ef840b SHA512 5b9784bf00bb8179ad59f2fbe5600b51ede3f79dd1ea2cb50485ffaabf74e83d766b2deb6833b99692a303e6780286ecce41b88a2d7c15f9e839bc7182a8879d WHIRLPOOL 25a85b5cbfa02b6e4e75f517dd445b5182593a04485ad6ac715e88ae6f7f3952de49096f17c27be7c9bcd2eab064147952e49c1d0957dd95d4e672ba68cd5bc0 2 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0026-amdgpu-add-the-interface-of-waiting-multiple-fences.patch: -------------------------------------------------------------------------------- 1 | From 30da7e6ac1682b5de547686369d1b8199c6929c3 Mon Sep 17 00:00:00 2001 2 | From: Junwei Zhang 3 | Date: Wed, 19 Aug 2015 17:39:37 +0800 4 | Subject: [PATCH 026/117] amdgpu: add the interface of waiting multiple fences 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | Signed-off-by: Junwei Zhang 10 | Reviewed-by: Christian König 11 | Reviewed-by: Jammy Zhou 12 | --- 13 | amdgpu/amdgpu.h | 22 +++++++++++++++ 14 | amdgpu/amdgpu_cs.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++ 15 | include/drm/amdgpu_drm.h | 27 ++++++++++++++++++ 16 | 3 files changed, 121 insertions(+) 17 | 18 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 19 | index 0851306..8822a0c 100644 20 | --- a/amdgpu/amdgpu.h 21 | +++ b/amdgpu/amdgpu.h 22 | @@ -907,6 +907,28 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 23 | uint64_t flags, 24 | uint32_t *expired); 25 | 26 | +/** 27 | + * Wait for multiple fences 28 | + * 29 | + * \param fences - \c [in] The fence array to wait 30 | + * \param fence_count - \c [in] The fence count 31 | + * \param wait_all - \c [in] If true, wait all fences to be signaled, 32 | + * otherwise, wait at least one fence 33 | + * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds 34 | + * \param status - \c [out] '1' for signaled, '0' for timeout 35 | + * 36 | + * \return 0 on success 37 | + * <0 - Negative POSIX Error code 38 | + * 39 | + * \note Currently it supports only one amdgpu_device. All fences come from 40 | + * the same amdgpu_device with the same fd. 41 | +*/ 42 | +int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 43 | + uint32_t fence_count, 44 | + bool wait_all, 45 | + uint64_t timeout_ns, 46 | + uint32_t *status); 47 | + 48 | /* 49 | * Query / Info API 50 | * 51 | diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c 52 | index b4f41b0..896352b 100644 53 | --- a/amdgpu/amdgpu_cs.c 54 | +++ b/amdgpu/amdgpu_cs.c 55 | @@ -435,6 +435,78 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 56 | return r; 57 | } 58 | 59 | +static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, 60 | + uint32_t fence_count, 61 | + bool wait_all, 62 | + uint64_t timeout_ns, 63 | + uint32_t *status) 64 | +{ 65 | + struct drm_amdgpu_fence *drm_fences; 66 | + amdgpu_device_handle dev = fences[0].context->dev; 67 | + union drm_amdgpu_wait_fences args; 68 | + int r; 69 | + uint32_t i; 70 | + 71 | + drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count); 72 | + for (i = 0; i < fence_count; i++) { 73 | + drm_fences[i].ctx_id = fences[i].context->id; 74 | + drm_fences[i].ip_type = fences[i].ip_type; 75 | + drm_fences[i].ip_instance = fences[i].ip_instance; 76 | + drm_fences[i].ring = fences[i].ring; 77 | + drm_fences[i].seq_no = fences[i].fence; 78 | + } 79 | + 80 | + memset(&args, 0, sizeof(args)); 81 | + args.in.fences = (uint64_t)(uintptr_t)drm_fences; 82 | + args.in.fence_count = fence_count; 83 | + args.in.wait_all = wait_all; 84 | + args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns); 85 | + 86 | + r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args); 87 | + if (r) 88 | + return -errno; 89 | + 90 | + *status = args.out.status; 91 | + return 0; 92 | +} 93 | + 94 | +int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 95 | + uint32_t fence_count, 96 | + bool wait_all, 97 | + uint64_t timeout_ns, 98 | + uint32_t *status) 99 | +{ 100 | + uint32_t ioctl_status = 0; 101 | + uint32_t i; 102 | + int r; 103 | + 104 | + /* Sanity check */ 105 | + if (NULL == fences) 106 | + return -EINVAL; 107 | + if (NULL == status) 108 | + return -EINVAL; 109 | + if (fence_count <= 0) 110 | + return -EINVAL; 111 | + for (i = 0; i < fence_count; i++) { 112 | + if (NULL == fences[i].context) 113 | + return -EINVAL; 114 | + if (fences[i].ip_type >= AMDGPU_HW_IP_NUM) 115 | + return -EINVAL; 116 | + if (fences[i].ring >= AMDGPU_CS_MAX_RINGS) 117 | + return -EINVAL; 118 | + } 119 | + 120 | + *status = 0; 121 | + 122 | + r = amdgpu_ioctl_wait_fences(fences, fence_count, wait_all, timeout_ns, 123 | + &ioctl_status); 124 | + 125 | + if (!r) 126 | + *status = ioctl_status; 127 | + 128 | + return r; 129 | +} 130 | + 131 | int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) 132 | { 133 | struct amdgpu_semaphore *gpu_semaphore; 134 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 135 | index fbdd118..2cbea72 100644 136 | --- a/include/drm/amdgpu_drm.h 137 | +++ b/include/drm/amdgpu_drm.h 138 | @@ -46,6 +46,7 @@ 139 | #define DRM_AMDGPU_WAIT_CS 0x09 140 | #define DRM_AMDGPU_GEM_OP 0x10 141 | #define DRM_AMDGPU_GEM_USERPTR 0x11 142 | +#define DRM_AMDGPU_WAIT_FENCES 0x12 143 | 144 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 145 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 146 | @@ -59,6 +60,7 @@ 147 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 148 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 149 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 150 | +#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 151 | 152 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 153 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 154 | @@ -297,6 +299,31 @@ union drm_amdgpu_wait_cs { 155 | struct drm_amdgpu_wait_cs_out out; 156 | }; 157 | 158 | +struct drm_amdgpu_fence { 159 | + uint32_t ctx_id; 160 | + uint32_t ip_type; 161 | + uint32_t ip_instance; 162 | + uint32_t ring; 163 | + uint64_t seq_no; 164 | +}; 165 | + 166 | +struct drm_amdgpu_wait_fences_in { 167 | + /** This points to uint64_t * which points to fences */ 168 | + uint64_t fences; 169 | + uint32_t fence_count; 170 | + uint32_t wait_all; 171 | + uint64_t timeout_ns; 172 | +}; 173 | + 174 | +struct drm_amdgpu_wait_fences_out { 175 | + uint64_t status; 176 | +}; 177 | + 178 | +union drm_amdgpu_wait_fences { 179 | + struct drm_amdgpu_wait_fences_in in; 180 | + struct drm_amdgpu_wait_fences_out out; 181 | +}; 182 | + 183 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 184 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 185 | 186 | -- 187 | 2.7.4 188 | 189 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0027-amdgpu-tests-add-multi-fence-test-in-base-test.patch: -------------------------------------------------------------------------------- 1 | From 41469768b0e55ae414aaf6b61b0d83f348518169 Mon Sep 17 00:00:00 2001 2 | From: Junwei Zhang 3 | Date: Fri, 21 Aug 2015 10:14:48 +0800 4 | Subject: [PATCH 027/117] amdgpu/tests: add multi-fence test in base test 5 | 6 | Signed-off-by: Junwei Zhang 7 | Reviewed-by: Jammy Zhou 8 | --- 9 | tests/amdgpu/basic_tests.c | 100 +++++++++++++++++++++++++++++++++++++++++++++ 10 | 1 file changed, 100 insertions(+) 11 | 12 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 13 | index fa0ed12..56db935 100644 14 | --- a/tests/amdgpu/basic_tests.c 15 | +++ b/tests/amdgpu/basic_tests.c 16 | @@ -46,6 +46,7 @@ static void amdgpu_memory_alloc(void); 17 | static void amdgpu_command_submission_gfx(void); 18 | static void amdgpu_command_submission_compute(void); 19 | static void amdgpu_command_submission_sdma(void); 20 | +static void amdgpu_command_submission_multi_fence(void); 21 | static void amdgpu_userptr_test(void); 22 | static void amdgpu_semaphore_test(void); 23 | 24 | @@ -56,6 +57,7 @@ CU_TestInfo basic_tests[] = { 25 | { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, 26 | { "Command submission Test (Compute)", amdgpu_command_submission_compute }, 27 | { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, 28 | + { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, 29 | { "SW semaphore Test", amdgpu_semaphore_test }, 30 | CU_TEST_INFO_NULL, 31 | }; 32 | @@ -898,6 +900,104 @@ static void amdgpu_command_submission_sdma(void) 33 | amdgpu_command_submission_sdma_copy_linear(); 34 | } 35 | 36 | +static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) 37 | +{ 38 | + amdgpu_context_handle context_handle; 39 | + amdgpu_bo_handle ib_result_handle, ib_result_ce_handle; 40 | + void *ib_result_cpu, *ib_result_ce_cpu; 41 | + uint64_t ib_result_mc_address, ib_result_ce_mc_address; 42 | + struct amdgpu_cs_request ibs_request[2] = {0}; 43 | + struct amdgpu_cs_ib_info ib_info[2]; 44 | + struct amdgpu_cs_fence fence_status[2] = {0}; 45 | + uint32_t *ptr; 46 | + uint32_t expired; 47 | + amdgpu_bo_list_handle bo_list; 48 | + amdgpu_va_handle va_handle, va_handle_ce; 49 | + int r; 50 | + int i, ib_cs_num = 2; 51 | + 52 | + r = amdgpu_cs_ctx_create(device_handle, &context_handle); 53 | + CU_ASSERT_EQUAL(r, 0); 54 | + 55 | + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, 56 | + AMDGPU_GEM_DOMAIN_GTT, 0, 57 | + &ib_result_handle, &ib_result_cpu, 58 | + &ib_result_mc_address, &va_handle); 59 | + CU_ASSERT_EQUAL(r, 0); 60 | + 61 | + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, 62 | + AMDGPU_GEM_DOMAIN_GTT, 0, 63 | + &ib_result_ce_handle, &ib_result_ce_cpu, 64 | + &ib_result_ce_mc_address, &va_handle_ce); 65 | + CU_ASSERT_EQUAL(r, 0); 66 | + 67 | + r = amdgpu_get_bo_list(device_handle, ib_result_handle, 68 | + ib_result_ce_handle, &bo_list); 69 | + CU_ASSERT_EQUAL(r, 0); 70 | + 71 | + memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); 72 | + 73 | + /* IT_SET_CE_DE_COUNTERS */ 74 | + ptr = ib_result_ce_cpu; 75 | + ptr[0] = 0xc0008900; 76 | + ptr[1] = 0; 77 | + ptr[2] = 0xc0008400; 78 | + ptr[3] = 1; 79 | + ib_info[0].ib_mc_address = ib_result_ce_mc_address; 80 | + ib_info[0].size = 4; 81 | + ib_info[0].flags = AMDGPU_IB_FLAG_CE; 82 | + 83 | + /* IT_WAIT_ON_CE_COUNTER */ 84 | + ptr = ib_result_cpu; 85 | + ptr[0] = 0xc0008600; 86 | + ptr[1] = 0x00000001; 87 | + ib_info[1].ib_mc_address = ib_result_mc_address; 88 | + ib_info[1].size = 2; 89 | + 90 | + for (i = 0; i < ib_cs_num; i++) { 91 | + ibs_request[i].ip_type = AMDGPU_HW_IP_GFX; 92 | + ibs_request[i].number_of_ibs = 2; 93 | + ibs_request[i].ibs = ib_info; 94 | + ibs_request[i].resources = bo_list; 95 | + ibs_request[i].fence_info.handle = NULL; 96 | + } 97 | + 98 | + r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num); 99 | + 100 | + CU_ASSERT_EQUAL(r, 0); 101 | + 102 | + for (i = 0; i < ib_cs_num; i++) { 103 | + fence_status[i].context = context_handle; 104 | + fence_status[i].ip_type = AMDGPU_HW_IP_GFX; 105 | + fence_status[i].fence = ibs_request[i].seq_no; 106 | + } 107 | + 108 | + r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all, 109 | + AMDGPU_TIMEOUT_INFINITE, 110 | + &expired); 111 | + CU_ASSERT_EQUAL(r, 0); 112 | + 113 | + r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 114 | + ib_result_mc_address, 4096); 115 | + CU_ASSERT_EQUAL(r, 0); 116 | + 117 | + r = amdgpu_bo_unmap_and_free(ib_result_ce_handle, va_handle_ce, 118 | + ib_result_ce_mc_address, 4096); 119 | + CU_ASSERT_EQUAL(r, 0); 120 | + 121 | + r = amdgpu_bo_list_destroy(bo_list); 122 | + CU_ASSERT_EQUAL(r, 0); 123 | + 124 | + r = amdgpu_cs_ctx_free(context_handle); 125 | + CU_ASSERT_EQUAL(r, 0); 126 | +} 127 | + 128 | +static void amdgpu_command_submission_multi_fence(void) 129 | +{ 130 | + amdgpu_command_submission_multi_fence_wait_all(true); 131 | + amdgpu_command_submission_multi_fence_wait_all(false); 132 | +} 133 | + 134 | static void amdgpu_userptr_test(void) 135 | { 136 | int i, r, j; 137 | -- 138 | 2.7.4 139 | 140 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0028-amdgpu-add-query-for-aperture-va-range.patch: -------------------------------------------------------------------------------- 1 | From 6699587911b702ad612ad0e942214186ca04c1c2 Mon Sep 17 00:00:00 2001 2 | From: Flora Cui 3 | Date: Sat, 10 Oct 2015 17:25:06 +0800 4 | Subject: [PATCH 028/117] amdgpu: add query for aperture va range 5 | 6 | Change-Id: I4358cdd7cd86f172967e063eac13708941c4e566 7 | Signed-off-by: Flora Cui 8 | Reviewed-by: Jammy Zhou 9 | Reviewed-by: Alex Deucher 10 | --- 11 | amdgpu/amdgpu.h | 30 ++++++++++++++++++++++++++++++ 12 | amdgpu/amdgpu_gpu_info.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 13 | include/drm/amdgpu_drm.h | 16 ++++++++++++++++ 14 | 3 files changed, 91 insertions(+) 15 | 16 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 17 | index 8822a0c..ccb4971 100644 18 | --- a/amdgpu/amdgpu.h 19 | +++ b/amdgpu/amdgpu.h 20 | @@ -1081,6 +1081,36 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, 21 | struct amdgpu_gds_resource_info *gds_info); 22 | 23 | /** 24 | +* Query private aperture range 25 | +* 26 | +* \param dev - [in] Device handle. See #amdgpu_device_initialize() 27 | +* \param start - \c [out] Start of private aperture 28 | +* \param end - \c [out] End of private aperture 29 | +* 30 | +* \return 0 on success\n 31 | +* <0 - Negative POSIX Error code 32 | +* 33 | +*/ 34 | +int amdgpu_query_private_aperture(amdgpu_device_handle dev, 35 | + uint64_t *start, 36 | + uint64_t *end); 37 | + 38 | +/** 39 | +* Query shared aperture range 40 | +* 41 | +* \param dev - [in] Device handle. See #amdgpu_device_initialize() 42 | +* \param start - \c [out] Start of shared aperture 43 | +* \param end - \c [out] End of shared aperture 44 | +* 45 | +* \return 0 on success\n 46 | +* <0 - Negative POSIX Error code 47 | +* 48 | +*/ 49 | +int amdgpu_query_shared_aperture(amdgpu_device_handle dev, 50 | + uint64_t *start, 51 | + uint64_t *end); 52 | + 53 | +/** 54 | * Read a set of consecutive memory-mapped registers. 55 | * Not all registers are allowed to be read by userspace. 56 | * 57 | diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c 58 | index 0cc17f1..73d8d11 100644 59 | --- a/amdgpu/amdgpu_gpu_info.c 60 | +++ b/amdgpu/amdgpu_gpu_info.c 61 | @@ -308,3 +308,48 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, 62 | 63 | return 0; 64 | } 65 | + 66 | +static int amdgpu_query_virtual_range_info(amdgpu_device_handle dev, 67 | + uint32_t aperture, 68 | + uint64_t *start, 69 | + uint64_t *end) 70 | +{ 71 | + struct drm_amdgpu_virtual_range range_info; 72 | + struct drm_amdgpu_info request; 73 | + int r; 74 | + 75 | + memset(&range_info, 0, sizeof(range_info)); 76 | + request.return_pointer = (uintptr_t)&range_info; 77 | + request.return_size = sizeof(range_info); 78 | + request.query = AMDGPU_INFO_VIRTUAL_RANGE; 79 | + request.virtual_range.aperture = aperture; 80 | + 81 | + r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, 82 | + sizeof(struct drm_amdgpu_info)); 83 | + if (r) 84 | + return r; 85 | + 86 | + *start = range_info.start; 87 | + *end = range_info.end; 88 | + return 0; 89 | +} 90 | + 91 | +int amdgpu_query_private_aperture(amdgpu_device_handle dev, 92 | + uint64_t *start, 93 | + uint64_t *end) 94 | +{ 95 | + return amdgpu_query_virtual_range_info(dev, 96 | + AMDGPU_SUA_APERTURE_PRIVATE, 97 | + start, 98 | + end); 99 | +} 100 | + 101 | +int amdgpu_query_shared_aperture(amdgpu_device_handle dev, 102 | + uint64_t *start, 103 | + uint64_t *end) 104 | +{ 105 | + return amdgpu_query_virtual_range_info(dev, 106 | + AMDGPU_SUA_APERTURE_SHARED, 107 | + start, 108 | + end); 109 | +} 110 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 111 | index 2cbea72..f97acd1 100644 112 | --- a/include/drm/amdgpu_drm.h 113 | +++ b/include/drm/amdgpu_drm.h 114 | @@ -504,6 +504,8 @@ struct drm_amdgpu_cs_chunk_data { 115 | #define AMDGPU_INFO_DEV_INFO 0x16 116 | /* visible vram usage */ 117 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 118 | +/* virtual range */ 119 | +#define AMDGPU_INFO_VIRTUAL_RANGE 0x18 120 | 121 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 122 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 123 | @@ -560,6 +562,11 @@ struct drm_amdgpu_info { 124 | } read_mmr_reg; 125 | 126 | struct drm_amdgpu_query_fw query_fw; 127 | + 128 | + struct { 129 | + uint32_t aperture; 130 | + uint32_t _pad; 131 | + } virtual_range; 132 | }; 133 | }; 134 | 135 | @@ -669,4 +676,13 @@ struct drm_amdgpu_info_hw_ip { 136 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 137 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo */ 138 | 139 | +/** 140 | + * Definition of System Unified Address (SUA) apertures 141 | + */ 142 | +#define AMDGPU_SUA_APERTURE_PRIVATE 1 143 | +#define AMDGPU_SUA_APERTURE_SHARED 2 144 | +struct drm_amdgpu_virtual_range { 145 | + uint64_t start; 146 | + uint64_t end; 147 | +}; 148 | #endif 149 | -- 150 | 2.7.4 151 | 152 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0029-amdgpu-Implement-SVM-v2.patch: -------------------------------------------------------------------------------- 1 | From f34f4232b7a2dad9bb1aaaa68f77ed5a5fa76456 Mon Sep 17 00:00:00 2001 2 | From: Alex Xie 3 | Date: Tue, 20 Oct 2015 11:47:14 -0400 4 | Subject: [PATCH 029/117] amdgpu: Implement SVM v2 5 | 6 | SWDEV-75927: Coarse Grain SVM support for OpenCL 2.0 7 | Add SVM API. 8 | Implement SVM to reserve CPU and GPU VM address space for SVM. Implement commit/uncommit function for SVM. 9 | 10 | v2: 11 | Merge patch1 and patch2. 12 | Update description of the commit. 13 | Address review comments on coding style. 14 | Update comments in source code. 15 | Fix one issue in function amdgpu_va_range_query. The start of the range should be dev->vamgr_svm->va_min. 16 | Fix an error code. 17 | 18 | Change-Id: Ib804b075347646ee6c4b4159583f1b4a0325df08 19 | Signed-off-by: Alex Xie 20 | Reviewed-by: Alex Deucher 21 | --- 22 | amdgpu/amdgpu.h | 28 ++++++++- 23 | amdgpu/amdgpu_device.c | 3 + 24 | amdgpu/amdgpu_internal.h | 6 ++ 25 | amdgpu/amdgpu_vamgr.c | 145 ++++++++++++++++++++++++++++++++++++++++++++++- 26 | 4 files changed, 178 insertions(+), 4 deletions(-) 27 | 28 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 29 | index ccb4971..79314fb 100644 30 | --- a/amdgpu/amdgpu.h 31 | +++ b/amdgpu/amdgpu.h 32 | @@ -87,7 +87,9 @@ enum amdgpu_bo_handle_type { 33 | enum amdgpu_gpu_va_range 34 | { 35 | /** Allocate from "normal"/general range */ 36 | - amdgpu_gpu_va_range_general = 0 37 | + amdgpu_gpu_va_range_general = 0, 38 | + /** Allocate from svm range */ 39 | + amdgpu_gpu_va_range_svm = 1 40 | }; 41 | 42 | /*--------------------------------------------------------------------------*/ 43 | @@ -1238,6 +1240,30 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, 44 | uint32_t ops); 45 | 46 | /** 47 | + * Commit SVM allocation in a process 48 | + * 49 | + * \param va_range_handle - \c [in] Handle of SVM allocation 50 | + * \param cpu - \c [out] CPU pointer. The value is equal to GPU VM address. 51 | + * 52 | + * \return 0 on success\n 53 | + * <0 - Negative POSIX Error code 54 | + * 55 | +*/ 56 | +int amdgpu_svm_commit(amdgpu_va_handle va_range_handle, 57 | + void **cpu); 58 | + 59 | +/** 60 | + * Uncommit SVM alloation in process's CPU_VM 61 | + * 62 | + * \param va_range_handle - \c [in] Handle of SVM allocation 63 | + * 64 | + * \return 0 on success\n 65 | + * <0 - Negative POSIX Error code 66 | + * 67 | +*/ 68 | +int amdgpu_svm_uncommit(amdgpu_va_handle va_range_handle); 69 | + 70 | +/** 71 | * create semaphore 72 | * 73 | * \param sem - \c [out] semaphore handle 74 | diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c 75 | index e5a923e..eb71c44 100644 76 | --- a/amdgpu/amdgpu_device.c 77 | +++ b/amdgpu/amdgpu_device.c 78 | @@ -130,6 +130,7 @@ static int amdgpu_get_auth(int fd, int *auth) 79 | 80 | static void amdgpu_device_free_internal(amdgpu_device_handle dev) 81 | { 82 | + amdgpu_svm_vamgr_deinit(dev); 83 | amdgpu_vamgr_deinit(dev->vamgr); 84 | free(dev->vamgr); 85 | amdgpu_vamgr_deinit(dev->vamgr_32); 86 | @@ -275,6 +276,8 @@ int amdgpu_device_initialize(int fd, 87 | amdgpu_vamgr_init(dev->vamgr_32, start, max, 88 | dev->dev_info.virtual_address_alignment); 89 | 90 | + amdgpu_svm_vamgr_init(dev); 91 | + 92 | *major_version = dev->major_version; 93 | *minor_version = dev->minor_version; 94 | *device_handle = dev; 95 | diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h 96 | index 557ba1f..3ae92d9 100644 97 | --- a/amdgpu/amdgpu_internal.h 98 | +++ b/amdgpu/amdgpu_internal.h 99 | @@ -54,6 +54,7 @@ struct amdgpu_bo_va_hole { 100 | struct amdgpu_bo_va_mgr { 101 | /* the start virtual address */ 102 | uint64_t va_offset; 103 | + uint64_t va_min; 104 | uint64_t va_max; 105 | struct list_head va_holes; 106 | pthread_mutex_t bo_va_mutex; 107 | @@ -87,6 +88,8 @@ struct amdgpu_device { 108 | struct amdgpu_bo_va_mgr *vamgr; 109 | /** The VA manager for the 32bit address space */ 110 | struct amdgpu_bo_va_mgr *vamgr_32; 111 | + /** The VA manager for SVM address space */ 112 | + struct amdgpu_bo_va_mgr *vamgr_svm; 113 | }; 114 | 115 | struct amdgpu_bo { 116 | @@ -148,6 +151,9 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, 117 | drm_private void 118 | amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size); 119 | 120 | +int amdgpu_svm_vamgr_init(struct amdgpu_device *dev); 121 | +void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev); 122 | + 123 | drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); 124 | 125 | drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); 126 | diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c 127 | index 8a707cb..f664216 100644 128 | --- a/amdgpu/amdgpu_vamgr.c 129 | +++ b/amdgpu/amdgpu_vamgr.c 130 | @@ -36,18 +36,30 @@ 131 | int amdgpu_va_range_query(amdgpu_device_handle dev, 132 | enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) 133 | { 134 | - if (type == amdgpu_gpu_va_range_general) { 135 | + switch (type) { 136 | + case amdgpu_gpu_va_range_general: 137 | *start = dev->dev_info.virtual_address_offset; 138 | *end = dev->dev_info.virtual_address_max; 139 | return 0; 140 | + case amdgpu_gpu_va_range_svm: 141 | + if (dev->vamgr_svm) { 142 | + *start = dev->vamgr_svm->va_min; 143 | + *end = dev->vamgr_svm->va_max; 144 | + } else { 145 | + *start = 0ULL; 146 | + *end = 0ULL; 147 | + } 148 | + return 0; 149 | + default: 150 | + return -EINVAL; 151 | } 152 | - return -EINVAL; 153 | } 154 | 155 | drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, 156 | uint64_t max, uint64_t alignment) 157 | { 158 | mgr->va_offset = start; 159 | + mgr->va_min = start; 160 | mgr->va_max = max; 161 | mgr->va_alignment = alignment; 162 | 163 | @@ -235,7 +247,12 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, 164 | { 165 | struct amdgpu_bo_va_mgr *vamgr; 166 | 167 | - if (flags & AMDGPU_VA_RANGE_32_BIT) 168 | + if (amdgpu_gpu_va_range_svm == va_range_type) { 169 | + vamgr = dev->vamgr_svm; 170 | + if (!vamgr) 171 | + return -EINVAL; 172 | + } 173 | + else if (flags & AMDGPU_VA_RANGE_32_BIT) 174 | vamgr = dev->vamgr_32; 175 | else 176 | vamgr = dev->vamgr; 177 | @@ -285,3 +302,125 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) 178 | free(va_range_handle); 179 | return 0; 180 | } 181 | + 182 | +/** 183 | + * Initialize SVM VAM manager. 184 | + * When this function return error, future SVM allocation will fail. 185 | + * Caller may ignore the error code returned by this function. 186 | + * 187 | + * \param dev - \c [in] amdgpu_device pointer 188 | + * 189 | + * \return 0 on success\n 190 | + * <0 - Negative POSIX Error code 191 | + * 192 | + */ 193 | +int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 194 | +{ 195 | + uint64_t start; 196 | + uint64_t end; 197 | + /* size of SVM range */ 198 | + uint64_t size; 199 | + uint64_t base_required; 200 | + /* Size of step when looking for SVM range. */ 201 | + uint64_t step; 202 | + /*Will not search less than this address. */ 203 | + uint64_t min_base_required; 204 | + void * cpu_address; 205 | + /* return value of this function. */ 206 | + int ret; 207 | + 208 | + ret = amdgpu_va_range_query(dev, amdgpu_gpu_va_range_general, &start, &end); 209 | + if (ret) 210 | + return ret; 211 | + 212 | + /* size of the general VM */ 213 | + size = end - start; 214 | + /* size of SVM range */ 215 | + size = size / 4; 216 | + /* at least keep lower 4G for process usage in CPU address space*/ 217 | + min_base_required = 4ULL * 1024ULL * 1024ULL * 1024ULL; 218 | + step = size / 8; 219 | + 220 | + ret = -ENOSPC; 221 | + /* We try to find a hole both in CPU/GPU VM address space for SVM from top 222 | + * to bottom. 223 | + */ 224 | + for (base_required = end - size; base_required >= min_base_required; 225 | + base_required -= step) { 226 | + start = amdgpu_vamgr_find_va(dev->vamgr, size, 227 | + dev->dev_info.virtual_address_alignment, base_required); 228 | + if (start != base_required) 229 | + continue; 230 | + 231 | + /* Try to map the SVM range in CPU VM */ 232 | + cpu_address = mmap((void *)start, size, PROT_NONE, 233 | + MAP_PRIVATE | MAP_NORESERVE | MAP_ANONYMOUS, -1, 0); 234 | + if (cpu_address == (void *)start) { 235 | + dev->vamgr_svm = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); 236 | + if (dev->vamgr_svm == NULL) { 237 | + amdgpu_vamgr_free_va(dev->vamgr, start, size); 238 | + munmap(cpu_address, size); 239 | + ret = -ENOMEM; 240 | + } else { 241 | + amdgpu_vamgr_init(dev->vamgr_svm, start, start + size, 242 | + dev->dev_info.virtual_address_alignment); 243 | + ret = 0; 244 | + } 245 | + break; 246 | + } else if (cpu_address == MAP_FAILED) { 247 | + /* Probably there is no space in this process's address space for 248 | + such size of SVM range. This is very rare for 64 bit CPU. 249 | + */ 250 | + amdgpu_vamgr_free_va(dev->vamgr, start, size); 251 | + ret = -ENOMEM; 252 | + break; 253 | + } else { /* cpu_address != (void *)start */ 254 | + /* This CPU VM address (start) is not available*/ 255 | + amdgpu_vamgr_free_va(dev->vamgr, start, size); 256 | + munmap(cpu_address, size); 257 | + base_required -= step; 258 | + } 259 | + } 260 | + 261 | + return ret; 262 | +} 263 | + 264 | +void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) 265 | +{ 266 | + if (dev->vamgr_svm) { 267 | + amdgpu_vamgr_deinit(dev->vamgr_svm); 268 | + munmap((void *)dev->vamgr_svm->va_min, 269 | + dev->vamgr_svm->va_max - dev->vamgr_svm->va_min); 270 | + free(dev->vamgr_svm); 271 | + } 272 | +} 273 | + 274 | +int amdgpu_svm_commit(amdgpu_va_handle va_range_handle, 275 | + void **cpu) 276 | +{ 277 | + if (!va_range_handle || !va_range_handle->address) 278 | + return -EINVAL; 279 | + if (va_range_handle->range != amdgpu_gpu_va_range_svm) 280 | + return -EINVAL; 281 | + 282 | + if (mprotect((void *)va_range_handle->address, 283 | + va_range_handle->size, PROT_READ | PROT_WRITE) == 0) { 284 | + *cpu = (void *)va_range_handle->address; 285 | + return 0; 286 | + } else 287 | + return errno; 288 | +} 289 | + 290 | +int amdgpu_svm_uncommit(amdgpu_va_handle va_range_handle) 291 | +{ 292 | + if (!va_range_handle || !va_range_handle->address) 293 | + return -EINVAL; 294 | + if (va_range_handle->range != amdgpu_gpu_va_range_svm) 295 | + return -EINVAL; 296 | + 297 | + if (mprotect((void *)va_range_handle->address, 298 | + va_range_handle->size, PROT_NONE) == 0) { 299 | + return 0; 300 | + } else 301 | + return errno; 302 | +} 303 | -- 304 | 2.7.4 305 | 306 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0030-amdgpu-SVM-test-v2.patch: -------------------------------------------------------------------------------- 1 | From 7b1f524b40c1ec014265f49646d10ef8cd52659d Mon Sep 17 00:00:00 2001 2 | From: Alex Xie 3 | Date: Tue, 20 Oct 2015 11:52:08 -0400 4 | Subject: [PATCH 030/117] amdgpu: SVM test v2 5 | 6 | SWDEV-75927: Coarse Grain SVM support for OpenCL 2.0 Add SVM relevant test. 7 | 8 | v2: 9 | Update the description of this commit. 10 | Fix an issue that the SVM feature should not be tested when SVM range is not supported. 11 | Remove test for query function for general VM range. 12 | 13 | Change-Id: I21fad07611d88280ffa1375ecf1de95c305cac22 14 | Signed-off-by: Alex Xie 15 | Reviewed-by: Alex Deucher 16 | --- 17 | tests/amdgpu/basic_tests.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 18 | 1 file changed, 46 insertions(+) 19 | 20 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 21 | index 56db935..eb73578 100644 22 | --- a/tests/amdgpu/basic_tests.c 23 | +++ b/tests/amdgpu/basic_tests.c 24 | @@ -49,6 +49,7 @@ static void amdgpu_command_submission_sdma(void); 25 | static void amdgpu_command_submission_multi_fence(void); 26 | static void amdgpu_userptr_test(void); 27 | static void amdgpu_semaphore_test(void); 28 | +static void amdgpu_svm_test(void); 29 | 30 | CU_TestInfo basic_tests[] = { 31 | { "Query Info Test", amdgpu_query_info_test }, 32 | @@ -59,9 +60,11 @@ CU_TestInfo basic_tests[] = { 33 | { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, 34 | { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, 35 | { "SW semaphore Test", amdgpu_semaphore_test }, 36 | + { "SVM Test", amdgpu_svm_test }, 37 | CU_TEST_INFO_NULL, 38 | }; 39 | #define BUFFER_SIZE (8 * 1024) 40 | +#define SVM_TEST_COUNT 16 41 | #define SDMA_PKT_HEADER_op_offset 0 42 | #define SDMA_PKT_HEADER_op_mask 0x000000FF 43 | #define SDMA_PKT_HEADER_op_shift 0 44 | @@ -1077,3 +1080,46 @@ static void amdgpu_userptr_test(void) 45 | r = amdgpu_cs_ctx_free(context_handle); 46 | CU_ASSERT_EQUAL(r, 0); 47 | } 48 | + 49 | +static void amdgpu_svm_test(void) 50 | +{ 51 | + int r; 52 | + uint64_t svm_mc; 53 | + amdgpu_va_handle va_handle[SVM_TEST_COUNT]; 54 | + void *cpu; 55 | + uint64_t start; 56 | + uint64_t end; 57 | + int i; 58 | + 59 | + r = amdgpu_va_range_query(device_handle, 60 | + amdgpu_gpu_va_range_svm, &start, &end); 61 | + CU_ASSERT_EQUAL(r, 0); 62 | + 63 | + /* If there is no SVM range, exit this function.*/ 64 | + if (start == 0ULL && end == 0ULL) 65 | + return; 66 | + 67 | + CU_ASSERT(start < end); 68 | + CU_ASSERT(end - start >= 1ULL * 1024ULL * 1024ULL * 1024ULL); 69 | + 70 | + for (i = 0; i < SVM_TEST_COUNT; i++) { 71 | + r = amdgpu_va_range_alloc(device_handle, 72 | + amdgpu_gpu_va_range_svm, 73 | + 64 * 1024 * 1024, 1, 0, &svm_mc, 74 | + &va_handle[i], 0); 75 | + CU_ASSERT_EQUAL(r, 0); 76 | + 77 | + r = amdgpu_svm_commit(va_handle[i], &cpu); 78 | + CU_ASSERT_EQUAL(r, 0); 79 | + CU_ASSERT_PTR_NOT_NULL(cpu); 80 | + CU_ASSERT_EQUAL(svm_mc, (uint64_t)cpu); 81 | + } 82 | + 83 | + for (i = 0; i < SVM_TEST_COUNT; i++) { 84 | + r = amdgpu_svm_uncommit(va_handle[i]); 85 | + CU_ASSERT_EQUAL(r, 0); 86 | + 87 | + r = amdgpu_va_range_free(va_handle[i]); 88 | + CU_ASSERT_EQUAL(r, 0); 89 | + } 90 | +} 91 | -- 92 | 2.7.4 93 | 94 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0031-amdgpu-Implement-multiGPU-SVM-support-v2.patch: -------------------------------------------------------------------------------- 1 | From e977542110f13aa8b0d3e4cf89f56140f0a0009f Mon Sep 17 00:00:00 2001 2 | From: Alex Xie 3 | Date: Thu, 29 Oct 2015 16:13:45 -0400 4 | Subject: [PATCH 031/117] amdgpu: Implement multiGPU SVM support v2 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | With this change, if there are multiple GPU devices, SVM range and allocation is global to all GPU devices. 10 | This is to meet the OpenCL 2.0 SVM requirement. This is not a perfect solution. But we have not found better solution. 11 | 12 | Constraints: 13 | 1. Application should initialize all relevant devices before allocate SVM address. 14 | 2. If devices do not have similar GPU VM configuration, libdrm can disable SVM when new device are initialized. 15 | 16 | v2: 17 | 1. Put svm_refcount and svm_valid as a field of amdgpu_bo_va_mgr. 18 | 2. Adjust title. 19 | 20 | Change-Id: I2cfa97e61a9ae1184da9a95f15398e050cb5caaf 21 | Signed-off-by: Alex Xie 22 | Reviewed-by: Jammy Zhou 23 | Reviewed-by: Christian König 24 | --- 25 | amdgpu/amdgpu_internal.h | 6 +++-- 26 | amdgpu/amdgpu_vamgr.c | 61 ++++++++++++++++++++++++++++++++---------------- 27 | 2 files changed, 45 insertions(+), 22 deletions(-) 28 | 29 | diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h 30 | index 3ae92d9..0506853 100644 31 | --- a/amdgpu/amdgpu_internal.h 32 | +++ b/amdgpu/amdgpu_internal.h 33 | @@ -59,6 +59,10 @@ struct amdgpu_bo_va_mgr { 34 | struct list_head va_holes; 35 | pthread_mutex_t bo_va_mutex; 36 | uint32_t va_alignment; 37 | + /* reference count. It is used by SVM for mulit GPU.*/ 38 | + atomic_t refcount; 39 | + /* Is the VM manager valid. It is used by SVM for mulit GPU.*/ 40 | + bool valid; 41 | }; 42 | 43 | struct amdgpu_va { 44 | @@ -88,8 +92,6 @@ struct amdgpu_device { 45 | struct amdgpu_bo_va_mgr *vamgr; 46 | /** The VA manager for the 32bit address space */ 47 | struct amdgpu_bo_va_mgr *vamgr_32; 48 | - /** The VA manager for SVM address space */ 49 | - struct amdgpu_bo_va_mgr *vamgr_svm; 50 | }; 51 | 52 | struct amdgpu_bo { 53 | diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c 54 | index f664216..945b006 100644 55 | --- a/amdgpu/amdgpu_vamgr.c 56 | +++ b/amdgpu/amdgpu_vamgr.c 57 | @@ -33,6 +33,9 @@ 58 | #include "amdgpu_internal.h" 59 | #include "util_math.h" 60 | 61 | +/* Devices share SVM range. So a global SVM VAM manager is needed. */ 62 | +static struct amdgpu_bo_va_mgr vamgr_svm; 63 | + 64 | int amdgpu_va_range_query(amdgpu_device_handle dev, 65 | enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) 66 | { 67 | @@ -42,9 +45,9 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, 68 | *end = dev->dev_info.virtual_address_max; 69 | return 0; 70 | case amdgpu_gpu_va_range_svm: 71 | - if (dev->vamgr_svm) { 72 | - *start = dev->vamgr_svm->va_min; 73 | - *end = dev->vamgr_svm->va_max; 74 | + if (vamgr_svm.valid) { 75 | + *start = vamgr_svm.va_min; 76 | + *end = vamgr_svm.va_max; 77 | } else { 78 | *start = 0ULL; 79 | *end = 0ULL; 80 | @@ -248,8 +251,8 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, 81 | struct amdgpu_bo_va_mgr *vamgr; 82 | 83 | if (amdgpu_gpu_va_range_svm == va_range_type) { 84 | - vamgr = dev->vamgr_svm; 85 | - if (!vamgr) 86 | + vamgr = &vamgr_svm; 87 | + if (!vamgr->valid) 88 | return -EINVAL; 89 | } 90 | else if (flags & AMDGPU_VA_RANGE_32_BIT) 91 | @@ -329,6 +332,23 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 92 | /* return value of this function. */ 93 | int ret; 94 | 95 | + if (atomic_inc_return(&vamgr_svm.refcount) != 1) { 96 | + /* This is not the first time to initialize SVM in this process. */ 97 | + if (!vamgr_svm.valid) 98 | + return -ENOSPC; 99 | + 100 | + start = amdgpu_vamgr_find_va(dev->vamgr, 101 | + vamgr_svm.va_max - vamgr_svm.va_min, 102 | + dev->dev_info.virtual_address_alignment, vamgr_svm.va_min); 103 | + 104 | + if (start != vamgr_svm.va_min) { 105 | + vamgr_svm.valid = false; 106 | + return -ENOSPC; 107 | + } 108 | + 109 | + return 0; 110 | + } 111 | + 112 | ret = amdgpu_va_range_query(dev, amdgpu_gpu_va_range_general, &start, &end); 113 | if (ret) 114 | return ret; 115 | @@ -356,16 +376,9 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 116 | cpu_address = mmap((void *)start, size, PROT_NONE, 117 | MAP_PRIVATE | MAP_NORESERVE | MAP_ANONYMOUS, -1, 0); 118 | if (cpu_address == (void *)start) { 119 | - dev->vamgr_svm = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); 120 | - if (dev->vamgr_svm == NULL) { 121 | - amdgpu_vamgr_free_va(dev->vamgr, start, size); 122 | - munmap(cpu_address, size); 123 | - ret = -ENOMEM; 124 | - } else { 125 | - amdgpu_vamgr_init(dev->vamgr_svm, start, start + size, 126 | - dev->dev_info.virtual_address_alignment); 127 | - ret = 0; 128 | - } 129 | + amdgpu_vamgr_init(&vamgr_svm, start, start + size, 130 | + dev->dev_info.virtual_address_alignment); 131 | + ret = 0; 132 | break; 133 | } else if (cpu_address == MAP_FAILED) { 134 | /* Probably there is no space in this process's address space for 135 | @@ -382,16 +395,24 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 136 | } 137 | } 138 | 139 | + if (!ret) 140 | + vamgr_svm.valid = true; 141 | + 142 | return ret; 143 | } 144 | 145 | void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) 146 | { 147 | - if (dev->vamgr_svm) { 148 | - amdgpu_vamgr_deinit(dev->vamgr_svm); 149 | - munmap((void *)dev->vamgr_svm->va_min, 150 | - dev->vamgr_svm->va_max - dev->vamgr_svm->va_min); 151 | - free(dev->vamgr_svm); 152 | + if (atomic_dec_and_test(&vamgr_svm.refcount)) { 153 | + /* This is the last device referencing SVM. */ 154 | + if (vamgr_svm.va_max != 0) { 155 | + /* SVM was initialized successfull. So SVM need uninitialization.*/ 156 | + amdgpu_vamgr_deinit(&vamgr_svm); 157 | + munmap((void *)vamgr_svm.va_min, 158 | + vamgr_svm.va_max - vamgr_svm.va_min); 159 | + vamgr_svm.va_max = 0; 160 | + } 161 | + vamgr_svm.valid = false; 162 | } 163 | } 164 | 165 | -- 166 | 2.7.4 167 | 168 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0032-tests-amdgpu-Add-test-for-multi-GPUs-SVM-test-v3.patch: -------------------------------------------------------------------------------- 1 | From ce7de7e34c1a87d56bcc7a8ebeac1a25756c5991 Mon Sep 17 00:00:00 2001 2 | From: Alex Xie 3 | Date: Fri, 30 Oct 2015 12:04:07 -0400 4 | Subject: [PATCH 032/117] tests/amdgpu: Add test for multi GPUs SVM test v3 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | 1. We try to open all GPUs when test starts. 10 | 2. Test multi GPUs for SVM 11 | 3. Add verbose output option and facility into this unit test app. 12 | 13 | v2: 14 | 1. Adjust title 15 | 2. Use drmGetDevices to get the number of cards available. 16 | 3. Add warning output option and facility into this unit test app. 17 | 4. Adjust a comment and delete useless C statement when open function call fails. 18 | 5. Add two informative outputs in single SVM test. 19 | 20 | v3: 21 | 1. Use general device name from drmGetDevices instead of fixed name. 22 | 2. open devices in a single "for" statement. 23 | 3. Create a function to close all devices. 24 | 25 | Change-Id: I313c13eabd6f0c2d3107ba37413e8ebd871faa0e 26 | Signed-off-by: Alex Xie 27 | Acked-by: Christian König 28 | --- 29 | tests/amdgpu/amdgpu_test.c | 92 +++++++++++++++++++++++++++++++++++++++------- 30 | tests/amdgpu/amdgpu_test.h | 5 +++ 31 | tests/amdgpu/basic_tests.c | 71 +++++++++++++++++++++++++++++++++++ 32 | 3 files changed, 154 insertions(+), 14 deletions(-) 33 | 34 | diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c 35 | index 71f357c..1e71fbf 100644 36 | --- a/tests/amdgpu/amdgpu_test.c 37 | +++ b/tests/amdgpu/amdgpu_test.c 38 | @@ -56,6 +56,10 @@ 39 | */ 40 | int drm_amdgpu[MAX_CARDS_SUPPORTED]; 41 | 42 | +static int num_devices; 43 | +static bool verbose = false; 44 | +static bool warning = false; 45 | + 46 | /** The table of all known test suites to run */ 47 | static CU_SuiteInfo suites[] = { 48 | { 49 | @@ -106,14 +110,24 @@ static void display_test_suites(void) 50 | } 51 | } 52 | 53 | +static void amdgpu_close_all() 54 | +{ 55 | + int i; 56 | + for (i = 0; i < num_devices; i++) 57 | + if (drm_amdgpu[i] > 0) 58 | + close(drm_amdgpu[i]); 59 | +} 60 | 61 | /** Help string for command line parameters */ 62 | -static const char usage[] = "Usage: %s [-hl] [<-s > [-t ]]\n" 63 | +static const char usage[] = 64 | + "Usage: %s [-hlvw] [<-s > [-t ]]\n" 65 | "where:\n" 66 | " l - Display all suites and their tests\n" 67 | + " v - Verbose output\n" 68 | + " w - Output warning message\n" 69 | " h - Display this help\n"; 70 | /** Specified options strings for getopt */ 71 | -static const char options[] = "hls:t:"; 72 | +static const char options[] = "hlvws:t:"; 73 | 74 | /* The main() function for setting up and running the tests. 75 | * Returns a CUE_SUCCESS on successful running, another 76 | @@ -127,8 +141,10 @@ int main(int argc, char **argv) 77 | int test_id = -1; /* By default run all tests in the suite */ 78 | CU_pSuite pSuite = NULL; 79 | CU_pTest pTest = NULL; 80 | + drmDevicePtr devices[MAX_CARDS_SUPPORTED]; 81 | 82 | int aval = drmAvailable(); 83 | + char card_name[256]; 84 | 85 | if (aval == 0) { 86 | fprintf(stderr, "DRM driver is not available\n"); 87 | @@ -153,6 +169,12 @@ int main(int argc, char **argv) 88 | case 't': 89 | test_id = atoi(optarg); 90 | break; 91 | + case 'v': 92 | + verbose = true; 93 | + break; 94 | + case 'w': 95 | + warning = true; 96 | + break; 97 | case '?': 98 | case 'h': 99 | fprintf(stderr, usage, argv[0]); 100 | @@ -163,17 +185,31 @@ int main(int argc, char **argv) 101 | } 102 | } 103 | 104 | - /* Try to open all possible radeon connections 105 | - * Right now: Open only the 0. 106 | + /* Try to open all possible amdgpu connections 107 | */ 108 | - printf("Try to open the card 0..\n"); 109 | - drm_amdgpu[0] = open("/dev/dri/card0", O_RDWR | O_CLOEXEC); 110 | - 111 | - if (drm_amdgpu[0] < 0) { 112 | - perror("Cannot open /dev/dri/card0\n"); 113 | + num_devices = drmGetDevices(devices, MAX_CARDS_SUPPORTED); 114 | + amdgpu_vprintf("\n Number of DRI devices is %d\n", num_devices); 115 | + if (num_devices > MAX_CARDS_SUPPORTED) 116 | + num_devices = MAX_CARDS_SUPPORTED; 117 | + if (num_devices <= 0) { 118 | + perror("Cannot query number of DRI devices.\n"); 119 | exit(EXIT_FAILURE); 120 | } 121 | 122 | + for (i = 0; i < num_devices; i++) { 123 | + amdgpu_vprintf("Try to open %s..\n", 124 | + devices[i]->nodes[DRM_NODE_PRIMARY]); 125 | + drm_amdgpu[i] = open(devices[i]->nodes[DRM_NODE_PRIMARY], 126 | + O_RDWR | O_CLOEXEC); 127 | + if (i == 0 && drm_amdgpu[i] < 0) { 128 | + drmFreeDevices(devices, num_devices); 129 | + /* It is essential to open first connection to run any test. */ 130 | + perror("Cannot open first card.\n"); 131 | + exit(EXIT_FAILURE); 132 | + } 133 | + } 134 | + drmFreeDevices(devices, num_devices); 135 | + 136 | /** Display version of DRM driver */ 137 | drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); 138 | 139 | @@ -191,7 +227,7 @@ int main(int argc, char **argv) 140 | 141 | /* initialize the CUnit test registry */ 142 | if (CUE_SUCCESS != CU_initialize_registry()) { 143 | - close(drm_amdgpu[0]); 144 | + amdgpu_close_all(); 145 | return CU_get_error(); 146 | } 147 | 148 | @@ -200,7 +236,7 @@ int main(int argc, char **argv) 149 | fprintf(stderr, "suite registration failed - %s\n", 150 | CU_get_error_msg()); 151 | CU_cleanup_registry(); 152 | - close(drm_amdgpu[0]); 153 | + amdgpu_close_all(); 154 | exit(EXIT_FAILURE); 155 | } 156 | 157 | @@ -222,7 +258,7 @@ int main(int argc, char **argv) 158 | fprintf(stderr, "Invalid test id: %d\n", 159 | test_id); 160 | CU_cleanup_registry(); 161 | - close(drm_amdgpu[0]); 162 | + amdgpu_close_all(); 163 | exit(EXIT_FAILURE); 164 | } 165 | } else 166 | @@ -231,13 +267,41 @@ int main(int argc, char **argv) 167 | fprintf(stderr, "Invalid suite id : %d\n", 168 | suite_id); 169 | CU_cleanup_registry(); 170 | - close(drm_amdgpu[0]); 171 | + amdgpu_close_all(); 172 | exit(EXIT_FAILURE); 173 | } 174 | } else 175 | CU_basic_run_tests(); 176 | 177 | CU_cleanup_registry(); 178 | - close(drm_amdgpu[0]); 179 | + amdgpu_close_all(); 180 | + 181 | return CU_get_error(); 182 | } 183 | + 184 | +void amdgpu_vprintf(char *fmt, ...) 185 | +{ 186 | + va_list args; 187 | + if (verbose) { 188 | + va_start(args, fmt); 189 | + vprintf(fmt, args); 190 | + va_end(args); 191 | + } 192 | +} 193 | + 194 | +void amdgpu_warning(bool condition, char *fmt, ...) 195 | +{ 196 | + if (warning && condition) 197 | + { 198 | + printf ("WARNING: "); 199 | + va_list args; 200 | + va_start(args, fmt); 201 | + vprintf(fmt, args); 202 | + va_end(args); 203 | + } 204 | +} 205 | + 206 | +int amdgpu_num_devices() 207 | +{ 208 | + return num_devices; 209 | +} 210 | diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h 211 | index fca92ad..5c47ba3 100644 212 | --- a/tests/amdgpu/amdgpu_test.h 213 | +++ b/tests/amdgpu/amdgpu_test.h 214 | @@ -104,6 +104,11 @@ extern CU_TestInfo vce_tests[]; 215 | /** 216 | * Helper functions 217 | */ 218 | + 219 | +void amdgpu_vprintf(char *fmt, ...); 220 | +void amdgpu_warning(bool condition, char *fmt, ...); 221 | +int amdgpu_num_devices(); 222 | + 223 | static inline amdgpu_bo_handle gpu_mem_alloc( 224 | amdgpu_device_handle device_handle, 225 | uint64_t size, 226 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 227 | index eb73578..23178e0 100644 228 | --- a/tests/amdgpu/basic_tests.c 229 | +++ b/tests/amdgpu/basic_tests.c 230 | @@ -50,6 +50,7 @@ static void amdgpu_command_submission_multi_fence(void); 231 | static void amdgpu_userptr_test(void); 232 | static void amdgpu_semaphore_test(void); 233 | static void amdgpu_svm_test(void); 234 | +static void amdgpu_multi_svm_test(void); 235 | 236 | CU_TestInfo basic_tests[] = { 237 | { "Query Info Test", amdgpu_query_info_test }, 238 | @@ -61,6 +62,7 @@ CU_TestInfo basic_tests[] = { 239 | { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, 240 | { "SW semaphore Test", amdgpu_semaphore_test }, 241 | { "SVM Test", amdgpu_svm_test }, 242 | + { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, 243 | CU_TEST_INFO_NULL, 244 | }; 245 | #define BUFFER_SIZE (8 * 1024) 246 | @@ -1094,6 +1096,8 @@ static void amdgpu_svm_test(void) 247 | r = amdgpu_va_range_query(device_handle, 248 | amdgpu_gpu_va_range_svm, &start, &end); 249 | CU_ASSERT_EQUAL(r, 0); 250 | + amdgpu_vprintf("\n"); 251 | + amdgpu_vprintf("SVM range is from 0x%llx to 0x%llx.\n", start, end); 252 | 253 | /* If there is no SVM range, exit this function.*/ 254 | if (start == 0ULL && end == 0ULL) 255 | @@ -1108,6 +1112,7 @@ static void amdgpu_svm_test(void) 256 | 64 * 1024 * 1024, 1, 0, &svm_mc, 257 | &va_handle[i], 0); 258 | CU_ASSERT_EQUAL(r, 0); 259 | + amdgpu_vprintf("Allocate SVM MC 0x%llx.\n", svm_mc); 260 | 261 | r = amdgpu_svm_commit(va_handle[i], &cpu); 262 | CU_ASSERT_EQUAL(r, 0); 263 | @@ -1123,3 +1128,69 @@ static void amdgpu_svm_test(void) 264 | CU_ASSERT_EQUAL(r, 0); 265 | } 266 | } 267 | + 268 | +static void amdgpu_multi_svm_test(void) 269 | +{ 270 | + int r; 271 | + int i; 272 | + uint64_t svm_mcs[MAX_CARDS_SUPPORTED]; 273 | + amdgpu_va_handle va_handles[MAX_CARDS_SUPPORTED]; 274 | + amdgpu_device_handle device_handles[MAX_CARDS_SUPPORTED]; 275 | + uint32_t major_version; 276 | + uint32_t minor_version; 277 | + int num_devices; 278 | + 279 | + device_handles[0] = device_handle; 280 | + num_devices = amdgpu_num_devices(); 281 | + 282 | + for (i = 1; i < num_devices; i++) 283 | + if (drm_amdgpu[i] > 0) { 284 | + r = amdgpu_device_initialize(drm_amdgpu[i], &major_version, 285 | + &minor_version, &device_handles[i]); 286 | + CU_ASSERT_EQUAL(r, 0); 287 | + } 288 | + 289 | + amdgpu_vprintf("\n"); 290 | + amdgpu_vprintf(" Testing to alloc and free SVM in all GPUs.\n"); 291 | + amdgpu_vprintf(" The svm_mcs generally are same.\n"); 292 | + for (i = 0; i < num_devices; i++) 293 | + if (drm_amdgpu[i] > 0) { 294 | + r = amdgpu_va_range_alloc(device_handles[i], 295 | + amdgpu_gpu_va_range_svm, 296 | + 0x1000000, 1, 0, &svm_mcs[i], 297 | + &va_handles[i], 0); 298 | + CU_ASSERT_EQUAL(r, 0); 299 | + amdgpu_vprintf(" card %d, svm_mc 0x%llx\n", i, svm_mcs[i]); 300 | + amdgpu_warning(svm_mcs[i] != svm_mcs[0], 301 | + "The SVM from different GPUs should be able to be allocated" 302 | + " from same location."); 303 | + r = amdgpu_va_range_free(va_handles[i]); 304 | + CU_ASSERT_EQUAL(r, 0); 305 | + } 306 | + 307 | + amdgpu_vprintf(" Testing to alloc SVM in all GPUs.\n"); 308 | + amdgpu_vprintf(" The svm_mcs are generally different by 0x1000000\n"); 309 | + for (i = 0; i < num_devices; i++) 310 | + if (drm_amdgpu[i] > 0) { 311 | + r = amdgpu_va_range_alloc(device_handles[i], 312 | + amdgpu_gpu_va_range_svm, 313 | + 0x1000000, 1, 0, &svm_mcs[i], 314 | + &va_handles[i], 0); 315 | + CU_ASSERT_EQUAL(r, 0); 316 | + amdgpu_vprintf(" card %d, svm_mc 0x%llx\n", i, svm_mcs[i]); 317 | + amdgpu_warning(svm_mcs[i] - svm_mcs[0] != 0x1000000 * i, 318 | + "The SVM from GPUs should be allocated sequentially."); 319 | + } 320 | + 321 | + for (i = 0; i < num_devices; i++) 322 | + if (drm_amdgpu[i] > 0) { 323 | + r = amdgpu_va_range_free(va_handles[i]); 324 | + CU_ASSERT_EQUAL(r, 0); 325 | + } 326 | + 327 | + for (i = 1; i < num_devices; i++) 328 | + if (drm_amdgpu[i] > 0) { 329 | + r = amdgpu_device_deinitialize(device_handles[i]); 330 | + CU_ASSERT_EQUAL(r, 0); 331 | + } 332 | +} 333 | -- 334 | 2.7.4 335 | 336 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0033-tests-amdgpu-Add-verbose-outputs-v2.patch: -------------------------------------------------------------------------------- 1 | From cb0741a52b97b4cf14a3407e74b5bf3973735a2f Mon Sep 17 00:00:00 2001 2 | From: Alex Xie 3 | Date: Tue, 3 Nov 2015 11:03:21 -0500 4 | Subject: [PATCH 033/117] tests/amdgpu: Add verbose outputs v2 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | 1. Add verbose output for information of compute rings. 10 | 2. Add verbose output for other hardware information, probably for test of harvesting. 11 | 3. Add verbose output for GPU information. This can provide information when reporting JIRA issue. 12 | 4. Add verbose output for firmware version. This can provide developer with firmware information. 13 | 14 | v2: Use 8 for the maximum ring number in function amd_query_hw_info_test 15 | 16 | Change-Id: I6e37332345007625456b33a20d7bfb8850eb53d5 17 | Signed-off-by: Alex Xie 18 | Reviewed-by:Jammy Zhou 19 | Acked-by:Christian König 20 | --- 21 | tests/amdgpu/amdgpu_test.c | 19 ++++++ 22 | tests/amdgpu/amdgpu_test.h | 1 + 23 | tests/amdgpu/basic_tests.c | 149 ++++++++++++++++++++++++++++++++++++++++++++- 24 | 3 files changed, 167 insertions(+), 2 deletions(-) 25 | 26 | diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c 27 | index 1e71fbf..46f55c7 100644 28 | --- a/tests/amdgpu/amdgpu_test.c 29 | +++ b/tests/amdgpu/amdgpu_test.c 30 | @@ -305,3 +305,22 @@ int amdgpu_num_devices() 31 | { 32 | return num_devices; 33 | } 34 | + 35 | +/* Translate HW IP type to name. */ 36 | +char * amdgpu_hw_ip_type_to_name(unsigned type) 37 | +{ 38 | + switch (type) { 39 | + case AMDGPU_HW_IP_GFX: 40 | + return "graphic"; 41 | + case AMDGPU_HW_IP_COMPUTE: 42 | + return "compute"; 43 | + case AMDGPU_HW_IP_DMA: 44 | + return "DMA"; 45 | + case AMDGPU_HW_IP_UVD: 46 | + return "UVD"; 47 | + case AMDGPU_HW_IP_VCE: 48 | + return "VCE"; 49 | + default: 50 | + return NULL; 51 | + } 52 | +} 53 | diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h 54 | index 5c47ba3..dd88eb5 100644 55 | --- a/tests/amdgpu/amdgpu_test.h 56 | +++ b/tests/amdgpu/amdgpu_test.h 57 | @@ -108,6 +108,7 @@ extern CU_TestInfo vce_tests[]; 58 | void amdgpu_vprintf(char *fmt, ...); 59 | void amdgpu_warning(bool condition, char *fmt, ...); 60 | int amdgpu_num_devices(); 61 | +char * amdgpu_hw_ip_type_to_name(unsigned type); 62 | 63 | static inline amdgpu_bo_handle gpu_mem_alloc( 64 | amdgpu_device_handle device_handle, 65 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 66 | index 23178e0..47c796e 100644 67 | --- a/tests/amdgpu/basic_tests.c 68 | +++ b/tests/amdgpu/basic_tests.c 69 | @@ -112,18 +112,161 @@ int suite_basic_tests_clean(void) 70 | return CUE_SCLEAN_FAILED; 71 | } 72 | 73 | -static void amdgpu_query_info_test(void) 74 | +static void amdgpu_query_hw_info_test(unsigned type) 75 | +{ 76 | + int r; 77 | + int i; 78 | + bool first_ring = true; 79 | + struct drm_amdgpu_info_hw_ip ip_info; 80 | + char *name; 81 | + 82 | + name = amdgpu_hw_ip_type_to_name(type); 83 | + CU_ASSERT_NOT_EQUAL(name, NULL); 84 | + 85 | + r = amdgpu_query_hw_ip_info(device_handle, type, 86 | + 0, &ip_info); 87 | + 88 | + CU_ASSERT_EQUAL(r, 0); 89 | + 90 | + amdgpu_vprintf("\n %s HW IP...\n", name); 91 | + amdgpu_vprintf(" major version:%d\n", ip_info.hw_ip_version_major); 92 | + amdgpu_vprintf(" minor version:%d\n", ip_info.hw_ip_version_minor); 93 | + amdgpu_vprintf(" capabilities_flags:0x%llx\n", 94 | + ip_info.capabilities_flags); 95 | + amdgpu_vprintf(" IB start alignment:%d\n", ip_info.ib_start_alignment); 96 | + amdgpu_vprintf(" IB size alignment:%d\n", ip_info.ib_size_alignment); 97 | + amdgpu_vprintf(" Following rings are supported: "); 98 | + for (i = 0; i < 8; i++) 99 | + if (ip_info.available_rings & 1 << i) { 100 | + if (first_ring) 101 | + first_ring = false; 102 | + else 103 | + amdgpu_vprintf(", "); 104 | + 105 | + amdgpu_vprintf("%d", i); 106 | + } 107 | + 108 | + amdgpu_vprintf(".\n"); 109 | +} 110 | + 111 | +static void amdgpu_query_gpu_info_test() 112 | { 113 | struct amdgpu_gpu_info gpu_info = {0}; 114 | - uint32_t version, feature; 115 | int r; 116 | + int i, j; 117 | 118 | r = amdgpu_query_gpu_info(device_handle, &gpu_info); 119 | CU_ASSERT_EQUAL(r, 0); 120 | 121 | + amdgpu_vprintf("\n GPU info...\n"); 122 | + 123 | + amdgpu_vprintf(" Asic id:"); 124 | + amdgpu_vprintf("0x%x\n", gpu_info.asic_id); 125 | + amdgpu_vprintf(" Chip revision:"); 126 | + amdgpu_vprintf("0x%x\n", gpu_info.chip_rev); 127 | + amdgpu_vprintf(" Chip external revision:"); 128 | + amdgpu_vprintf("0x%x\n", gpu_info.chip_external_rev); 129 | + amdgpu_vprintf(" Family ID:"); 130 | + amdgpu_vprintf("0x%x\n", gpu_info.family_id); 131 | + amdgpu_vprintf(" Special flags:"); 132 | + amdgpu_vprintf("0x%llx\n", gpu_info.ids_flags); 133 | + amdgpu_vprintf(" max engine clock:"); 134 | + amdgpu_vprintf("0x%llx\n", gpu_info.max_engine_clk); 135 | + amdgpu_vprintf(" max memory clock:"); 136 | + amdgpu_vprintf("0x%llx\n", gpu_info.max_memory_clk); 137 | + amdgpu_vprintf(" number of shader engines:"); 138 | + amdgpu_vprintf("0x%x\n", gpu_info.num_shader_engines); 139 | + amdgpu_vprintf(" number of shader arrays per engine:"); 140 | + amdgpu_vprintf("0x%x\n", gpu_info.num_shader_arrays_per_engine); 141 | + amdgpu_vprintf(" Number of available good shader pipes:"); 142 | + amdgpu_vprintf("0x%x\n", gpu_info.avail_quad_shader_pipes); 143 | + amdgpu_vprintf(" Max. number of shader pipes." 144 | + "(including good and bad pipes :"); 145 | + amdgpu_vprintf("0x%x\n", gpu_info.max_quad_shader_pipes); 146 | + amdgpu_vprintf(" Number of parameter cache entries per shader quad " 147 | + "pipe:"); 148 | + amdgpu_vprintf("0x%x\n", gpu_info.cache_entries_per_quad_pipe); 149 | + amdgpu_vprintf(" Number of available graphics context:"); 150 | + amdgpu_vprintf("0x%x\n", gpu_info.num_hw_gfx_contexts); 151 | + amdgpu_vprintf(" Number of render backend pipes:"); 152 | + amdgpu_vprintf("0x%x\n", gpu_info.rb_pipes); 153 | + amdgpu_vprintf(" Enabled render backend pipe mask:"); 154 | + amdgpu_vprintf("0x%x\n", gpu_info.enabled_rb_pipes_mask); 155 | + amdgpu_vprintf(" Frequency of GPU Counter:"); 156 | + amdgpu_vprintf("0x%x\n", gpu_info.gpu_counter_freq); 157 | + 158 | + amdgpu_vprintf(" CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE:\n"); 159 | + for (i = 0; i < 4; i++) 160 | + amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.backend_disable[i]); 161 | + 162 | + amdgpu_vprintf(" Value of MC_ARB_RAMCFG register:"); 163 | + amdgpu_vprintf("0x%x\n", gpu_info.mc_arb_ramcfg); 164 | + amdgpu_vprintf(" Value of GB_ADDR_CONFIG:"); 165 | + amdgpu_vprintf("0x%x\n", gpu_info.gb_addr_cfg); 166 | + 167 | + amdgpu_vprintf(" Values of the GB_TILE_MODE0..31 registers:\n"); 168 | + for (i = 0; i < 32; i++) 169 | + amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.gb_tile_mode[i]); 170 | + 171 | + amdgpu_vprintf(" Values of GB_MACROTILE_MODE0..15 registers:\n"); 172 | + for (i = 0; i < 16; i++) 173 | + amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.gb_macro_tile_mode[i]); 174 | + 175 | + amdgpu_vprintf(" Value of PA_SC_RASTER_CONFIG register per SE:\n"); 176 | + for (i = 0; i < 4; i++) 177 | + amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.pa_sc_raster_cfg[i]); 178 | + 179 | + amdgpu_vprintf(" Value of PA_SC_RASTER_CONFIG_1 register per SE:\n"); 180 | + for (i = 0; i < 4; i++) 181 | + amdgpu_vprintf(" [%d]=0x%x\n", i, gpu_info.pa_sc_raster_cfg1[i]); 182 | + 183 | + amdgpu_vprintf(" CU info (active number):"); 184 | + amdgpu_vprintf("0x%x\n", gpu_info.cu_active_number); 185 | + amdgpu_vprintf(" CU info (AU mask):"); 186 | + amdgpu_vprintf("0x%x\n", gpu_info.cu_ao_mask); 187 | + 188 | + amdgpu_vprintf(" CU info (AU bit map):"); 189 | + for (i = 0; i < 4; i++) { 190 | + amdgpu_vprintf("\n "); 191 | + for (j = 0; j < 4; j++) 192 | + amdgpu_vprintf(" [%d][%d]=0x%08x", i, j, gpu_info.cu_bitmap[i][j]); 193 | + } 194 | + amdgpu_vprintf("\n"); 195 | + 196 | + amdgpu_vprintf(" video memory type info:"); 197 | + amdgpu_vprintf("0x%x\n", gpu_info.vram_type); 198 | + amdgpu_vprintf(" video memory bit width:"); 199 | + amdgpu_vprintf("0x%x\n", gpu_info.vram_bit_width); 200 | + amdgpu_vprintf(" constant engine ram size:"); 201 | + amdgpu_vprintf("0x%x\n", gpu_info.ce_ram_size); 202 | + amdgpu_vprintf(" vce harvesting instance:"); 203 | + amdgpu_vprintf("0x%x\n", gpu_info.vce_harvest_config); 204 | + amdgpu_vprintf(" PCI revision ID:"); 205 | + amdgpu_vprintf("0x%x\n", gpu_info.pci_rev_id); 206 | +} 207 | + 208 | +static void amdgpu_query_firmware_info_test(void) 209 | +{ 210 | + uint32_t version, feature; 211 | + int r; 212 | + 213 | r = amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0, 214 | 0, &version, &feature); 215 | CU_ASSERT_EQUAL(r, 0); 216 | + amdgpu_vprintf("\n VCE firmware info...\n"); 217 | + amdgpu_vprintf(" vce version: 0x%x\n", version); 218 | + amdgpu_vprintf(" vce feature: 0x%x\n", feature); 219 | +} 220 | + 221 | +static void amdgpu_query_info_test(void) 222 | +{ 223 | + amdgpu_query_gpu_info_test(); 224 | + amdgpu_query_firmware_info_test(); 225 | + amdgpu_query_hw_info_test(AMDGPU_HW_IP_GFX); 226 | + amdgpu_query_hw_info_test(AMDGPU_HW_IP_COMPUTE); 227 | + amdgpu_query_hw_info_test(AMDGPU_HW_IP_DMA); 228 | + amdgpu_query_hw_info_test(AMDGPU_HW_IP_UVD); 229 | + amdgpu_query_hw_info_test(AMDGPU_HW_IP_VCE); 230 | } 231 | 232 | static void amdgpu_memory_alloc(void) 233 | @@ -491,7 +634,9 @@ static void amdgpu_command_submission_compute(void) 234 | r = amdgpu_cs_ctx_create(device_handle, &context_handle); 235 | CU_ASSERT_EQUAL(r, 0); 236 | 237 | + amdgpu_vprintf("\n"); 238 | for (instance = 0; instance < 8; instance++) { 239 | + amdgpu_vprintf(" Submit NOP command on ring %d.\n", instance); 240 | r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, 241 | AMDGPU_GEM_DOMAIN_GTT, 0, 242 | &ib_result_handle, &ib_result_cpu, 243 | -- 244 | 2.7.4 245 | 246 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0034-amdgpu-Free-uninit-vamgr_32-in-theoretically-correct.patch: -------------------------------------------------------------------------------- 1 | From e32955cf3b88b111e8d80a0c45e6e6d284d7d9a2 Mon Sep 17 00:00:00 2001 2 | From: Alex Xie 3 | Date: Tue, 3 Nov 2015 15:26:09 -0500 4 | Subject: [PATCH 034/117] amdgpu: Free/uninit vamgr_32 in theoretically correct 5 | order 6 | MIME-Version: 1.0 7 | Content-Type: text/plain; charset=UTF-8 8 | Content-Transfer-Encoding: 8bit 9 | 10 | vamgr_32 is a region inside general VAM range. It is better to free and deinitialize it before general VAM range. 11 | 12 | Change-Id: Iaafaf5c1be7f274e933f1295a8822d90c1c6200d 13 | Signed-off-by: Alex Xie 14 | Reviewed-by: Christian König 15 | --- 16 | amdgpu/amdgpu_device.c | 4 ++-- 17 | 1 file changed, 2 insertions(+), 2 deletions(-) 18 | 19 | diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c 20 | index eb71c44..a58a9d4 100644 21 | --- a/amdgpu/amdgpu_device.c 22 | +++ b/amdgpu/amdgpu_device.c 23 | @@ -131,10 +131,10 @@ static int amdgpu_get_auth(int fd, int *auth) 24 | static void amdgpu_device_free_internal(amdgpu_device_handle dev) 25 | { 26 | amdgpu_svm_vamgr_deinit(dev); 27 | - amdgpu_vamgr_deinit(dev->vamgr); 28 | - free(dev->vamgr); 29 | amdgpu_vamgr_deinit(dev->vamgr_32); 30 | free(dev->vamgr_32); 31 | + amdgpu_vamgr_deinit(dev->vamgr); 32 | + free(dev->vamgr); 33 | util_hash_table_destroy(dev->bo_flink_names); 34 | util_hash_table_destroy(dev->bo_handles); 35 | pthread_mutex_destroy(&dev->bo_table_mutex); 36 | -- 37 | 2.7.4 38 | 39 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0035-amdgpu-vamgr_32-can-be-a-struct-instead-of-a-pointer.patch: -------------------------------------------------------------------------------- 1 | From 98342e54c0e8d290a70bfea2b0631169ea414787 Mon Sep 17 00:00:00 2001 2 | From: Alex Xie 3 | Date: Tue, 3 Nov 2015 15:46:33 -0500 4 | Subject: [PATCH 035/117] amdgpu: vamgr_32 can be a struct instead of a pointer 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | vamgr_32 is an integral part of amdgpu_device. We don't need to callac and free it. 10 | This can save CPU time. Reduce heap fragment. 11 | 12 | Change-Id: I7b5797058e68d0b4c12705d628d32a996b2f3644 13 | Signed-off-by: Alex Xie 14 | Reviewed-by: Christian König 15 | --- 16 | amdgpu/amdgpu_device.c | 8 ++------ 17 | amdgpu/amdgpu_internal.h | 2 +- 18 | amdgpu/amdgpu_vamgr.c | 4 ++-- 19 | 3 files changed, 5 insertions(+), 9 deletions(-) 20 | 21 | diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c 22 | index a58a9d4..259c1cc 100644 23 | --- a/amdgpu/amdgpu_device.c 24 | +++ b/amdgpu/amdgpu_device.c 25 | @@ -131,8 +131,7 @@ static int amdgpu_get_auth(int fd, int *auth) 26 | static void amdgpu_device_free_internal(amdgpu_device_handle dev) 27 | { 28 | amdgpu_svm_vamgr_deinit(dev); 29 | - amdgpu_vamgr_deinit(dev->vamgr_32); 30 | - free(dev->vamgr_32); 31 | + amdgpu_vamgr_deinit(&dev->vamgr_32); 32 | amdgpu_vamgr_deinit(dev->vamgr); 33 | free(dev->vamgr); 34 | util_hash_table_destroy(dev->bo_flink_names); 35 | @@ -270,10 +269,7 @@ int amdgpu_device_initialize(int fd, 36 | if (start > 0xffffffff) 37 | goto free_va; /* shouldn't get here */ 38 | 39 | - dev->vamgr_32 = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); 40 | - if (dev->vamgr_32 == NULL) 41 | - goto free_va; 42 | - amdgpu_vamgr_init(dev->vamgr_32, start, max, 43 | + amdgpu_vamgr_init(&dev->vamgr_32, start, max, 44 | dev->dev_info.virtual_address_alignment); 45 | 46 | amdgpu_svm_vamgr_init(dev); 47 | diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h 48 | index 0506853..892b467 100644 49 | --- a/amdgpu/amdgpu_internal.h 50 | +++ b/amdgpu/amdgpu_internal.h 51 | @@ -91,7 +91,7 @@ struct amdgpu_device { 52 | /** The global VA manager for the whole virtual address space */ 53 | struct amdgpu_bo_va_mgr *vamgr; 54 | /** The VA manager for the 32bit address space */ 55 | - struct amdgpu_bo_va_mgr *vamgr_32; 56 | + struct amdgpu_bo_va_mgr vamgr_32; 57 | }; 58 | 59 | struct amdgpu_bo { 60 | diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c 61 | index 945b006..916eb9e 100644 62 | --- a/amdgpu/amdgpu_vamgr.c 63 | +++ b/amdgpu/amdgpu_vamgr.c 64 | @@ -256,7 +256,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, 65 | return -EINVAL; 66 | } 67 | else if (flags & AMDGPU_VA_RANGE_32_BIT) 68 | - vamgr = dev->vamgr_32; 69 | + vamgr = &dev->vamgr_32; 70 | else 71 | vamgr = dev->vamgr; 72 | 73 | @@ -269,7 +269,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, 74 | if (!(flags & AMDGPU_VA_RANGE_32_BIT) && 75 | (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { 76 | /* fallback to 32bit address */ 77 | - vamgr = dev->vamgr_32; 78 | + vamgr = &dev->vamgr_32; 79 | *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, 80 | va_base_alignment, va_base_required); 81 | } 82 | -- 83 | 2.7.4 84 | 85 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0036-amdgpu-vamgr-can-be-a-struct-instead-of-a-pointer.patch: -------------------------------------------------------------------------------- 1 | From 8326d0420e94fffc413eb9ef23de37074a20efeb Mon Sep 17 00:00:00 2001 2 | From: Alex Xie 3 | Date: Tue, 3 Nov 2015 15:52:57 -0500 4 | Subject: [PATCH 036/117] amdgpu: vamgr can be a struct instead of a pointer 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | vamgr is an integral part of amdgpu_device. We don't need to callac and free it. 10 | This can save CPU time. Reduce heap fragment. 11 | 12 | Change-Id: Ib5ca9e93d007370d2d746aea2c21c2f91aefa3c2 13 | Signed-off-by: Alex Xie 14 | Reviewed-by: Christian König 15 | --- 16 | amdgpu/amdgpu_device.c | 16 +++++----------- 17 | amdgpu/amdgpu_internal.h | 2 +- 18 | amdgpu/amdgpu_vamgr.c | 10 +++++----- 19 | 3 files changed, 11 insertions(+), 17 deletions(-) 20 | 21 | diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c 22 | index 259c1cc..b1a7182 100644 23 | --- a/amdgpu/amdgpu_device.c 24 | +++ b/amdgpu/amdgpu_device.c 25 | @@ -132,8 +132,7 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev) 26 | { 27 | amdgpu_svm_vamgr_deinit(dev); 28 | amdgpu_vamgr_deinit(&dev->vamgr_32); 29 | - amdgpu_vamgr_deinit(dev->vamgr); 30 | - free(dev->vamgr); 31 | + amdgpu_vamgr_deinit(&dev->vamgr); 32 | util_hash_table_destroy(dev->bo_flink_names); 33 | util_hash_table_destroy(dev->bo_handles); 34 | pthread_mutex_destroy(&dev->bo_table_mutex); 35 | @@ -254,16 +253,12 @@ int amdgpu_device_initialize(int fd, 36 | if (r) 37 | goto cleanup; 38 | 39 | - dev->vamgr = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); 40 | - if (dev->vamgr == NULL) 41 | - goto cleanup; 42 | - 43 | - amdgpu_vamgr_init(dev->vamgr, dev->dev_info.virtual_address_offset, 44 | + amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset, 45 | dev->dev_info.virtual_address_max, 46 | dev->dev_info.virtual_address_alignment); 47 | 48 | max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); 49 | - start = amdgpu_vamgr_find_va(dev->vamgr, 50 | + start = amdgpu_vamgr_find_va(&dev->vamgr, 51 | max - dev->dev_info.virtual_address_offset, 52 | dev->dev_info.virtual_address_alignment, 0); 53 | if (start > 0xffffffff) 54 | @@ -284,10 +279,9 @@ int amdgpu_device_initialize(int fd, 55 | 56 | free_va: 57 | r = -ENOMEM; 58 | - amdgpu_vamgr_free_va(dev->vamgr, start, 59 | + amdgpu_vamgr_free_va(&dev->vamgr, start, 60 | max - dev->dev_info.virtual_address_offset); 61 | - amdgpu_vamgr_deinit(dev->vamgr); 62 | - free(dev->vamgr); 63 | + amdgpu_vamgr_deinit(&dev->vamgr); 64 | 65 | cleanup: 66 | if (dev->fd >= 0) 67 | diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h 68 | index 892b467..caec2a2 100644 69 | --- a/amdgpu/amdgpu_internal.h 70 | +++ b/amdgpu/amdgpu_internal.h 71 | @@ -89,7 +89,7 @@ struct amdgpu_device { 72 | struct drm_amdgpu_info_device dev_info; 73 | struct amdgpu_gpu_info info; 74 | /** The global VA manager for the whole virtual address space */ 75 | - struct amdgpu_bo_va_mgr *vamgr; 76 | + struct amdgpu_bo_va_mgr vamgr; 77 | /** The VA manager for the 32bit address space */ 78 | struct amdgpu_bo_va_mgr vamgr_32; 79 | }; 80 | diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c 81 | index 916eb9e..64a3543 100644 82 | --- a/amdgpu/amdgpu_vamgr.c 83 | +++ b/amdgpu/amdgpu_vamgr.c 84 | @@ -258,7 +258,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, 85 | else if (flags & AMDGPU_VA_RANGE_32_BIT) 86 | vamgr = &dev->vamgr_32; 87 | else 88 | - vamgr = dev->vamgr; 89 | + vamgr = &dev->vamgr; 90 | 91 | va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); 92 | size = ALIGN(size, vamgr->va_alignment); 93 | @@ -337,7 +337,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 94 | if (!vamgr_svm.valid) 95 | return -ENOSPC; 96 | 97 | - start = amdgpu_vamgr_find_va(dev->vamgr, 98 | + start = amdgpu_vamgr_find_va(&dev->vamgr, 99 | vamgr_svm.va_max - vamgr_svm.va_min, 100 | dev->dev_info.virtual_address_alignment, vamgr_svm.va_min); 101 | 102 | @@ -367,7 +367,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 103 | */ 104 | for (base_required = end - size; base_required >= min_base_required; 105 | base_required -= step) { 106 | - start = amdgpu_vamgr_find_va(dev->vamgr, size, 107 | + start = amdgpu_vamgr_find_va(&dev->vamgr, size, 108 | dev->dev_info.virtual_address_alignment, base_required); 109 | if (start != base_required) 110 | continue; 111 | @@ -384,12 +384,12 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 112 | /* Probably there is no space in this process's address space for 113 | such size of SVM range. This is very rare for 64 bit CPU. 114 | */ 115 | - amdgpu_vamgr_free_va(dev->vamgr, start, size); 116 | + amdgpu_vamgr_free_va(&dev->vamgr, start, size); 117 | ret = -ENOMEM; 118 | break; 119 | } else { /* cpu_address != (void *)start */ 120 | /* This CPU VM address (start) is not available*/ 121 | - amdgpu_vamgr_free_va(dev->vamgr, start, size); 122 | + amdgpu_vamgr_free_va(&dev->vamgr, start, size); 123 | munmap(cpu_address, size); 124 | base_required -= step; 125 | } 126 | -- 127 | 2.7.4 128 | 129 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0037-tests-amdgpu-add-the-heap-info-for-query.patch: -------------------------------------------------------------------------------- 1 | From 30625ac043a1dd882df4f9d1feed4b08ebdd6371 Mon Sep 17 00:00:00 2001 2 | From: Jammy Zhou 3 | Date: Mon, 9 Nov 2015 13:40:41 +0800 4 | Subject: [PATCH 037/117] tests/amdgpu: add the heap info for query 5 | 6 | Change-Id: Icdaad4e373c316e0dde9a24cda4252ffd5163f1a 7 | Signed-off-by: Jammy Zhou 8 | Reviewed-by: Alex Deucher 9 | --- 10 | tests/amdgpu/basic_tests.c | 27 +++++++++++++++++++++++++++ 11 | 1 file changed, 27 insertions(+) 12 | 13 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 14 | index 47c796e..ec68dac 100644 15 | --- a/tests/amdgpu/basic_tests.c 16 | +++ b/tests/amdgpu/basic_tests.c 17 | @@ -258,6 +258,32 @@ static void amdgpu_query_firmware_info_test(void) 18 | amdgpu_vprintf(" vce feature: 0x%x\n", feature); 19 | } 20 | 21 | +static void amdgpu_query_heap_info_test(void) 22 | +{ 23 | + struct amdgpu_heap_info info; 24 | + uint64_t total_vram, total_vram_used; 25 | + 26 | + amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, 27 | + 0, &info); 28 | + total_vram = info.heap_size; 29 | + total_vram_used = info.heap_usage; 30 | + 31 | + amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, 32 | + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &info); 33 | + amdgpu_vprintf("\n Visible VRAM info...\n"); 34 | + amdgpu_vprintf(" size: 0x%x\n", info.heap_size); 35 | + amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); 36 | + amdgpu_vprintf("\n Invisible VRAM info...\n"); 37 | + amdgpu_vprintf(" size: 0x%x\n", total_vram - info.heap_size); 38 | + amdgpu_vprintf(" usage: 0x%x\n", total_vram_used - info.heap_usage); 39 | + 40 | + amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, 41 | + 0, &info); 42 | + amdgpu_vprintf("\n GTT info...\n"); 43 | + amdgpu_vprintf(" size: 0x%x\n", info.heap_size); 44 | + amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); 45 | +} 46 | + 47 | static void amdgpu_query_info_test(void) 48 | { 49 | amdgpu_query_gpu_info_test(); 50 | @@ -267,6 +293,7 @@ static void amdgpu_query_info_test(void) 51 | amdgpu_query_hw_info_test(AMDGPU_HW_IP_DMA); 52 | amdgpu_query_hw_info_test(AMDGPU_HW_IP_UVD); 53 | amdgpu_query_hw_info_test(AMDGPU_HW_IP_VCE); 54 | + amdgpu_query_heap_info_test(); 55 | } 56 | 57 | static void amdgpu_memory_alloc(void) 58 | -- 59 | 2.7.4 60 | 61 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0038-amdgpu-reserve-SVM-range-explicitly-by-clients-v3.patch: -------------------------------------------------------------------------------- 1 | From f639b2e37ecdcc49b4dbaf1dedac51ecabf7e20e Mon Sep 17 00:00:00 2001 2 | From: Jammy Zhou 3 | Date: Tue, 10 Nov 2015 21:17:22 +0800 4 | Subject: [PATCH 038/117] amdgpu: reserve SVM range explicitly by clients (v3) 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | The SVM range is only used by OCL 2.0 now, and it shouldn't be 10 | reserved when only other clients are used. With this change: 11 | 12 | amdgpu_svm_init() should be called to reserve the SVM range 13 | amdgpu_svm_deinit() should be called to unreserve this range 14 | 15 | v3: fix a typo 16 | v2: update the unit test as well 17 | 18 | Change-Id: Ia2495c3471a0c71c6b05fd81d84d5acfaf9a0a4c 19 | Signed-off-by: Jammy Zhou 20 | Reviewed-by: Michel Dänzer 21 | --- 22 | amdgpu/amdgpu.h | 21 +++++++++++++++++++++ 23 | amdgpu/amdgpu_device.c | 3 --- 24 | amdgpu/amdgpu_internal.h | 3 --- 25 | amdgpu/amdgpu_vamgr.c | 4 ++-- 26 | tests/amdgpu/basic_tests.c | 14 ++++++++++++++ 27 | 5 files changed, 37 insertions(+), 8 deletions(-) 28 | 29 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 30 | index 79314fb..1db47c3 100644 31 | --- a/amdgpu/amdgpu.h 32 | +++ b/amdgpu/amdgpu.h 33 | @@ -1240,6 +1240,27 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, 34 | uint32_t ops); 35 | 36 | /** 37 | + * Reserve the virtual address range for SVM support 38 | + * 39 | + * \param amdgpu_device_handle 40 | + * 41 | + * \return 0 on success\n 42 | + * <0 - Negative POSIX Error code 43 | + * 44 | +*/ 45 | +int amdgpu_svm_init(amdgpu_device_handle dev); 46 | + 47 | +/** 48 | + * Free the virtual address range for SVM support 49 | + * 50 | + * \param amdgpu_device_handle 51 | + * 52 | + * \return 53 | + * 54 | +*/ 55 | +void amdgpu_svm_deinit(amdgpu_device_handle dev); 56 | + 57 | +/** 58 | * Commit SVM allocation in a process 59 | * 60 | * \param va_range_handle - \c [in] Handle of SVM allocation 61 | diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c 62 | index b1a7182..b517b1a 100644 63 | --- a/amdgpu/amdgpu_device.c 64 | +++ b/amdgpu/amdgpu_device.c 65 | @@ -130,7 +130,6 @@ static int amdgpu_get_auth(int fd, int *auth) 66 | 67 | static void amdgpu_device_free_internal(amdgpu_device_handle dev) 68 | { 69 | - amdgpu_svm_vamgr_deinit(dev); 70 | amdgpu_vamgr_deinit(&dev->vamgr_32); 71 | amdgpu_vamgr_deinit(&dev->vamgr); 72 | util_hash_table_destroy(dev->bo_flink_names); 73 | @@ -267,8 +266,6 @@ int amdgpu_device_initialize(int fd, 74 | amdgpu_vamgr_init(&dev->vamgr_32, start, max, 75 | dev->dev_info.virtual_address_alignment); 76 | 77 | - amdgpu_svm_vamgr_init(dev); 78 | - 79 | *major_version = dev->major_version; 80 | *minor_version = dev->minor_version; 81 | *device_handle = dev; 82 | diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h 83 | index caec2a2..3760f94 100644 84 | --- a/amdgpu/amdgpu_internal.h 85 | +++ b/amdgpu/amdgpu_internal.h 86 | @@ -153,9 +153,6 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, 87 | drm_private void 88 | amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size); 89 | 90 | -int amdgpu_svm_vamgr_init(struct amdgpu_device *dev); 91 | -void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev); 92 | - 93 | drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); 94 | 95 | drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); 96 | diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c 97 | index 64a3543..973274d 100644 98 | --- a/amdgpu/amdgpu_vamgr.c 99 | +++ b/amdgpu/amdgpu_vamgr.c 100 | @@ -317,7 +317,7 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) 101 | * <0 - Negative POSIX Error code 102 | * 103 | */ 104 | -int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 105 | +int amdgpu_svm_init(amdgpu_device_handle dev) 106 | { 107 | uint64_t start; 108 | uint64_t end; 109 | @@ -401,7 +401,7 @@ int amdgpu_svm_vamgr_init(struct amdgpu_device *dev) 110 | return ret; 111 | } 112 | 113 | -void amdgpu_svm_vamgr_deinit(struct amdgpu_device *dev) 114 | +void amdgpu_svm_deinit(amdgpu_device_handle dev) 115 | { 116 | if (atomic_dec_and_test(&vamgr_svm.refcount)) { 117 | /* This is the last device referencing SVM. */ 118 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 119 | index ec68dac..408a432 100644 120 | --- a/tests/amdgpu/basic_tests.c 121 | +++ b/tests/amdgpu/basic_tests.c 122 | @@ -1265,6 +1265,9 @@ static void amdgpu_svm_test(void) 123 | uint64_t end; 124 | int i; 125 | 126 | + r = amdgpu_svm_init(device_handle); 127 | + CU_ASSERT_EQUAL(r, 0); 128 | + 129 | r = amdgpu_va_range_query(device_handle, 130 | amdgpu_gpu_va_range_svm, &start, &end); 131 | CU_ASSERT_EQUAL(r, 0); 132 | @@ -1299,6 +1302,8 @@ static void amdgpu_svm_test(void) 133 | r = amdgpu_va_range_free(va_handle[i]); 134 | CU_ASSERT_EQUAL(r, 0); 135 | } 136 | + 137 | + amdgpu_svm_deinit(device_handle); 138 | } 139 | 140 | static void amdgpu_multi_svm_test(void) 141 | @@ -1315,11 +1320,17 @@ static void amdgpu_multi_svm_test(void) 142 | device_handles[0] = device_handle; 143 | num_devices = amdgpu_num_devices(); 144 | 145 | + r = amdgpu_svm_init(device_handles[0]); 146 | + CU_ASSERT_EQUAL(r, 0); 147 | + 148 | for (i = 1; i < num_devices; i++) 149 | if (drm_amdgpu[i] > 0) { 150 | r = amdgpu_device_initialize(drm_amdgpu[i], &major_version, 151 | &minor_version, &device_handles[i]); 152 | CU_ASSERT_EQUAL(r, 0); 153 | + 154 | + r = amdgpu_svm_init(device_handles[i]); 155 | + CU_ASSERT_EQUAL(r, 0); 156 | } 157 | 158 | amdgpu_vprintf("\n"); 159 | @@ -1362,7 +1373,10 @@ static void amdgpu_multi_svm_test(void) 160 | 161 | for (i = 1; i < num_devices; i++) 162 | if (drm_amdgpu[i] > 0) { 163 | + amdgpu_svm_deinit(device_handles[i]); 164 | r = amdgpu_device_deinitialize(device_handles[i]); 165 | CU_ASSERT_EQUAL(r, 0); 166 | } 167 | + 168 | + amdgpu_svm_deinit(device_handles[0]); 169 | } 170 | -- 171 | 2.7.4 172 | 173 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0039-amdgpu-expose-the-AMDGPU_GEM_CREATE_NO_EVICT-flag.patch: -------------------------------------------------------------------------------- 1 | From 3fb478b00e1f3123f4c9b1efbd4a7e804679b64b Mon Sep 17 00:00:00 2001 2 | From: Jammy Zhou 3 | Date: Mon, 9 Nov 2015 12:42:52 +0800 4 | Subject: [PATCH 039/117] amdgpu: expose the AMDGPU_GEM_CREATE_NO_EVICT flag 5 | 6 | With this flag specified, the buffer will be pinned at allocation time. 7 | 8 | Change-Id: Ibb75f27dc79ca678e58590b188a749b762429fce 9 | Signed-off-by: Jammy Zhou 10 | Reviewed-by: Chunming Zhou 11 | --- 12 | include/drm/amdgpu_drm.h | 2 ++ 13 | 1 file changed, 2 insertions(+) 14 | 15 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 16 | index f97acd1..1df0d9c 100644 17 | --- a/include/drm/amdgpu_drm.h 18 | +++ b/include/drm/amdgpu_drm.h 19 | @@ -75,6 +75,8 @@ 20 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 21 | /* Flag that the memory should be in VRAM and cleared */ 22 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 23 | +/* Flag that the memory allocation should be pinned */ 24 | +#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 3) 25 | 26 | struct drm_amdgpu_gem_create_in { 27 | /** the requested memory size */ 28 | -- 29 | 2.7.4 30 | 31 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0040-amdgpu-add-query-amdgpu-capability-defination.patch: -------------------------------------------------------------------------------- 1 | From 813fc7d4532d77b0fc46c0f80813fb63c86e8097 Mon Sep 17 00:00:00 2001 2 | From: jimqu 3 | Date: Mon, 16 Nov 2015 15:13:00 +0800 4 | Subject: [PATCH 040/117] amdgpu: add query amdgpu capability defination 5 | 6 | Signed-off-by: JimQu 7 | 8 | Reviewed-by: Chunming Zhou 9 | Reviewed-by: Jammy Zhou 10 | 11 | Change-Id: Id615b06a59bc5a49aa8f7c7e658eb1bb1f318bd6 12 | --- 13 | include/drm/amdgpu_drm.h | 6 ++++++ 14 | 1 file changed, 6 insertions(+) 15 | 16 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 17 | index 1df0d9c..981b346 100644 18 | --- a/include/drm/amdgpu_drm.h 19 | +++ b/include/drm/amdgpu_drm.h 20 | @@ -508,6 +508,8 @@ struct drm_amdgpu_cs_chunk_data { 21 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 22 | /* virtual range */ 23 | #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 24 | +/* gpu capability */ 25 | +#define AMDGPU_INFO_CAPABILITY 0x50 26 | 27 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 28 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 29 | @@ -569,6 +571,10 @@ struct drm_amdgpu_info { 30 | uint32_t aperture; 31 | uint32_t _pad; 32 | } virtual_range; 33 | + 34 | + struct { 35 | + uint64_t type; 36 | + } query_capability; 37 | }; 38 | }; 39 | 40 | -- 41 | 2.7.4 42 | 43 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0041-amdgpu-add-query-amdgpu-pinning-memory-capability-de.patch: -------------------------------------------------------------------------------- 1 | From 231f4155aba4fcef48298c44d02047db111885ca Mon Sep 17 00:00:00 2001 2 | From: jimqu 3 | Date: Mon, 16 Nov 2015 15:15:14 +0800 4 | Subject: [PATCH 041/117] amdgpu: add query amdgpu pinning memory capability 5 | defination 6 | 7 | Signed-off-by: JimQu 8 | 9 | Change-Id: I5f0095ef0cb550fad67aca222009b71634d79b4b 10 | Reviewed-by: Chunming Zhou 11 | Reviewed-by: Jammy Zhou 12 | --- 13 | include/drm/amdgpu_drm.h | 2 ++ 14 | 1 file changed, 2 insertions(+) 15 | 16 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 17 | index 981b346..4ddb649 100644 18 | --- a/include/drm/amdgpu_drm.h 19 | +++ b/include/drm/amdgpu_drm.h 20 | @@ -510,6 +510,8 @@ struct drm_amdgpu_cs_chunk_data { 21 | #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 22 | /* gpu capability */ 23 | #define AMDGPU_INFO_CAPABILITY 0x50 24 | + /* query pin memory capability */ 25 | + #define AMDGPU_INFO_CAPABILITY_PIN_MEM 0x01 26 | 27 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 28 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 29 | -- 30 | 2.7.4 31 | 32 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0042-amdgpu-add-amdgpu_query_capability-interface.patch: -------------------------------------------------------------------------------- 1 | From 8b7c227c3cb6429e2c53fd8375c415021626886d Mon Sep 17 00:00:00 2001 2 | From: Chunming Zhou 3 | Date: Mon, 16 Nov 2015 18:06:16 +0800 4 | Subject: [PATCH 042/117] amdgpu: add amdgpu_query_capability interface 5 | 6 | Change-Id: Iffdd157e411c19f4d9980994dad6952b183ef1a5 7 | Signed-off-by: Chunming Zhou 8 | Reviewed-by: Jim Qu 9 | --- 10 | amdgpu/amdgpu.h | 18 ++++++++++++++++++ 11 | amdgpu/amdgpu_gpu_info.c | 6 ++++++ 12 | include/drm/amdgpu_drm.h | 8 +++----- 13 | 3 files changed, 27 insertions(+), 5 deletions(-) 14 | 15 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 16 | index 1db47c3..baae113 100644 17 | --- a/amdgpu/amdgpu.h 18 | +++ b/amdgpu/amdgpu.h 19 | @@ -62,6 +62,11 @@ struct drm_amdgpu_info_hw_ip; 20 | */ 21 | #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0) 22 | 23 | +/** 24 | + * Used in amdgpu_query_capability(), meaning if pin feature is enabled. 25 | + */ 26 | +#define AMDGPU_CAP_PIN_MEM (1 << 0) 27 | + 28 | /*--------------------------------------------------------------------------*/ 29 | /* ----------------------------- Enums ------------------------------------ */ 30 | /*--------------------------------------------------------------------------*/ 31 | @@ -1070,6 +1075,19 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 32 | unsigned size, void *value); 33 | 34 | /** 35 | + * Query hardware or driver capabilities. 36 | + * 37 | + * 38 | + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 39 | + * \param value - \c [out] Pointer to the return value. 40 | + * 41 | + * \return 0 on success\n 42 | + * <0 - Negative POSIX error code 43 | + * 44 | +*/ 45 | +int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value); 46 | + 47 | +/** 48 | * Query information about GDS 49 | * 50 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 51 | diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c 52 | index 73d8d11..133952d 100644 53 | --- a/amdgpu/amdgpu_gpu_info.c 54 | +++ b/amdgpu/amdgpu_gpu_info.c 55 | @@ -48,6 +48,12 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 56 | sizeof(struct drm_amdgpu_info)); 57 | } 58 | 59 | +int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value) 60 | +{ 61 | + return amdgpu_query_info(dev, AMDGPU_INFO_CAPABILITY, 62 | + sizeof(uint64_t), value); 63 | +} 64 | + 65 | int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 66 | int32_t *result) 67 | { 68 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 69 | index 4ddb649..050e7fe 100644 70 | --- a/include/drm/amdgpu_drm.h 71 | +++ b/include/drm/amdgpu_drm.h 72 | @@ -508,10 +508,11 @@ struct drm_amdgpu_cs_chunk_data { 73 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 74 | /* virtual range */ 75 | #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 76 | + 77 | /* gpu capability */ 78 | #define AMDGPU_INFO_CAPABILITY 0x50 79 | - /* query pin memory capability */ 80 | - #define AMDGPU_INFO_CAPABILITY_PIN_MEM 0x01 81 | +/* query pin memory capability */ 82 | +#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) 83 | 84 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 85 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 86 | @@ -574,9 +575,6 @@ struct drm_amdgpu_info { 87 | uint32_t _pad; 88 | } virtual_range; 89 | 90 | - struct { 91 | - uint64_t type; 92 | - } query_capability; 93 | }; 94 | }; 95 | 96 | -- 97 | 2.7.4 98 | 99 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0043-amdgpu-add-amdgpu_find_bo_by_cpu_mapping-interface.patch: -------------------------------------------------------------------------------- 1 | From c8b1ce6872eaf7793065b0e4ed308b2a92032f95 Mon Sep 17 00:00:00 2001 2 | From: Chunming Zhou 3 | Date: Thu, 26 Nov 2015 17:01:07 +0800 4 | Subject: [PATCH 043/117] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | userspace needs to know if the user memory is from BO or malloc. 10 | 11 | Change-Id: Ie2dbc13f1c02bc0a996f64f9db83a21da63c1d70 12 | Signed-off-by: Chunming Zhou 13 | Reviewed-by: Jammy Zhou 14 | Reviewed-by: Christian König 15 | --- 16 | amdgpu/amdgpu.h | 24 ++++++++++++++++++++++++ 17 | amdgpu/amdgpu_bo.c | 37 +++++++++++++++++++++++++++++++++++++ 18 | include/drm/amdgpu_drm.h | 12 ++++++++++++ 19 | 3 files changed, 73 insertions(+) 20 | 21 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 22 | index baae113..4925056 100644 23 | --- a/amdgpu/amdgpu.h 24 | +++ b/amdgpu/amdgpu.h 25 | @@ -672,6 +672,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, 26 | amdgpu_bo_handle *buf_handle); 27 | 28 | /** 29 | + * Validate if the user memory comes from BO 30 | + * 31 | + * \param dev - [in] Device handle. See #amdgpu_device_initialize() 32 | + * \param cpu - [in] CPU address of user allocated memory which we 33 | + * want to map to GPU address space (make GPU accessible) 34 | + * (This address must be correctly aligned). 35 | + * \param size - [in] Size of allocation (must be correctly aligned) 36 | + * \param buf_handle - [out] Buffer handle for the userptr memory 37 | + * if the user memory is not from BO, the buf_handle will be NULL. 38 | + * \param offset_in_bo - [out] offset in this BO for this user memory 39 | + * 40 | + * 41 | + * \return 0 on success\n 42 | + * <0 - Negative POSIX Error code 43 | + * 44 | +*/ 45 | +int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, 46 | + void *cpu, 47 | + uint64_t size, 48 | + amdgpu_bo_handle *buf_handle, 49 | + uint64_t *offset_in_bo); 50 | + 51 | + 52 | +/** 53 | * Free previosuly allocated memory 54 | * 55 | * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() 56 | diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c 57 | index d30fd1e..ff78039 100644 58 | --- a/amdgpu/amdgpu_bo.c 59 | +++ b/amdgpu/amdgpu_bo.c 60 | @@ -529,6 +529,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, 61 | } 62 | } 63 | 64 | +int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, 65 | + void *cpu, 66 | + uint64_t size, 67 | + amdgpu_bo_handle *buf_handle, 68 | + uint64_t *offset_in_bo) 69 | +{ 70 | + int r; 71 | + struct amdgpu_bo *bo; 72 | + struct drm_amdgpu_gem_find_bo args; 73 | + 74 | + args.addr = (uintptr_t)cpu; 75 | + args.size = size; 76 | + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_FIND_BO, 77 | + &args, sizeof(args)); 78 | + if (r) 79 | + return r; 80 | + if (args.handle == 0) 81 | + return -EINVAL; 82 | + bo = util_hash_table_get(dev->bo_handles, 83 | + (void*)(uintptr_t)args.handle); 84 | + if (!bo) { 85 | + bo = calloc(1, sizeof(struct amdgpu_bo)); 86 | + if (!bo) 87 | + return -ENOMEM; 88 | + atomic_set(&bo->refcount, 1); 89 | + bo->dev = dev; 90 | + bo->alloc_size = size; 91 | + bo->handle = args.handle; 92 | + } else 93 | + atomic_inc(&bo->refcount); 94 | + 95 | + *buf_handle = bo; 96 | + *offset_in_bo = args.offset; 97 | + return r; 98 | +} 99 | + 100 | + 101 | int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, 102 | void *cpu, 103 | uint64_t size, 104 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 105 | index 050e7fe..e07904c 100644 106 | --- a/include/drm/amdgpu_drm.h 107 | +++ b/include/drm/amdgpu_drm.h 108 | @@ -47,6 +47,7 @@ 109 | #define DRM_AMDGPU_GEM_OP 0x10 110 | #define DRM_AMDGPU_GEM_USERPTR 0x11 111 | #define DRM_AMDGPU_WAIT_FENCES 0x12 112 | +#define DRM_AMDGPU_GEM_FIND_BO 0x13 113 | 114 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 115 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 116 | @@ -61,6 +62,7 @@ 117 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 118 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 119 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 120 | +#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) 121 | 122 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 123 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 124 | @@ -201,6 +203,16 @@ struct drm_amdgpu_gem_userptr { 125 | uint32_t handle; 126 | }; 127 | 128 | +struct drm_amdgpu_gem_find_bo { 129 | + uint64_t addr; 130 | + uint64_t size; 131 | + uint32_t flags; 132 | + /* Resulting GEM handle */ 133 | + uint32_t handle; 134 | + /* offset in bo */ 135 | + uint64_t offset; 136 | +}; 137 | + 138 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 139 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 140 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 141 | -- 142 | 2.7.4 143 | 144 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0044-amdgpu-support-alloc-va-from-range.patch: -------------------------------------------------------------------------------- 1 | From 6cac1ca7faba752980ae58e4b10aef5b89c097dd Mon Sep 17 00:00:00 2001 2 | From: Flora Cui 3 | Date: Thu, 4 Feb 2016 09:42:45 +0800 4 | Subject: [PATCH 044/117] amdgpu: support alloc va from range 5 | 6 | Change-Id: Ib41ca6a99ce500fe783a1b1650f25be9cebec83a 7 | Signed-off-by: Flora Cui 8 | Reviewed-by: Ken Wang 9 | --- 10 | amdgpu/amdgpu.h | 51 +++++++++++++++ 11 | amdgpu/amdgpu_vamgr.c | 169 ++++++++++++++++++++++++++++++++++++++++++++++++++ 12 | 2 files changed, 220 insertions(+) 13 | 14 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 15 | index 4925056..455f388 100644 16 | --- a/amdgpu/amdgpu.h 17 | +++ b/amdgpu/amdgpu.h 18 | @@ -1226,6 +1226,57 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, 19 | uint64_t flags); 20 | 21 | /** 22 | + * Allocate virtual address range in client defined range 23 | + * 24 | + * \param dev - [in] Device handle. See #amdgpu_device_initialize() 25 | + * \param va_range_type - \c [in] Type of MC va range from which to allocate 26 | + * \param size - \c [in] Size of range. Size must be correctly* aligned. 27 | + * It is client responsibility to correctly aligned size based on the future 28 | + * usage of allocated range. 29 | + * \param va_base_alignment - \c [in] Overwrite base address alignment 30 | + * requirement for GPU VM MC virtual 31 | + * address assignment. Must be multiple of size alignments received as 32 | + * 'amdgpu_buffer_size_alignments'. 33 | + * If 0 use the default one. 34 | + * \param va_base_required - \c [in] Specified required va base address. 35 | + * If 0 then library choose available one between [va_base_min, va_base_max]. 36 | + * If !0 value will be passed and those value already "in use" then 37 | + * corresponding error status will be returned. 38 | + * \param va_base_min- \c [in] Specified required va range min address. 39 | + * valid if va_base_required is 0 40 | + * \param va_base_max - \c [in] Specified required va range max address. 41 | + * valid if va_base_required is 0 42 | + * \param va_base_allocated - \c [out] On return: Allocated VA base to be used 43 | + * by client. 44 | + * \param va_range_handle - \c [out] On return: Handle assigned to allocation 45 | + * \param flags - \c [in] flags for special VA range 46 | + * 47 | + * \return 0 on success\n 48 | + * >0 - AMD specific error code\n 49 | + * <0 - Negative POSIX Error code 50 | + * 51 | + * \notes \n 52 | + * It is client responsibility to correctly handle VA assignments and usage. 53 | + * Neither kernel driver nor libdrm_amdpgu are able to prevent and 54 | + * detect wrong va assignemnt. 55 | + * 56 | + * It is client responsibility to correctly handle multi-GPU cases and to pass 57 | + * the corresponding arrays of all devices handles where corresponding VA will 58 | + * be used. 59 | + * 60 | +*/ 61 | +int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, 62 | + enum amdgpu_gpu_va_range va_range_type, 63 | + uint64_t size, 64 | + uint64_t va_base_alignment, 65 | + uint64_t va_base_required, 66 | + uint64_t va_range_min, 67 | + uint64_t va_range_max, 68 | + uint64_t *va_base_allocated, 69 | + amdgpu_va_handle *va_range_handle, 70 | + uint64_t flags); 71 | + 72 | +/** 73 | * Free previously allocated virtual address range 74 | * 75 | * 76 | diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c 77 | index 973274d..82653e9 100644 78 | --- a/amdgpu/amdgpu_vamgr.c 79 | +++ b/amdgpu/amdgpu_vamgr.c 80 | @@ -169,6 +169,94 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, 81 | return offset; 82 | } 83 | 84 | +static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint64_t size, 85 | + uint64_t alignment, uint64_t range_min, uint64_t range_max) 86 | +{ 87 | + struct amdgpu_bo_va_hole *hole, *n; 88 | + uint64_t offset = 0, waste = 0; 89 | + 90 | + if (mgr->va_min >= range_max || 91 | + mgr->va_max <= range_min) 92 | + return AMDGPU_INVALID_VA_ADDRESS; 93 | + 94 | + alignment = MAX2(alignment, mgr->va_alignment); 95 | + size = ALIGN(size, mgr->va_alignment); 96 | + 97 | + pthread_mutex_lock(&mgr->bo_va_mutex); 98 | + /* TODO: using more appropriate way to track the holes */ 99 | + /* first look for a hole */ 100 | + LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { 101 | + if (hole->offset > range_max || 102 | + hole->offset + hole->size < range_min || 103 | + (hole->offset > range_min && hole->offset + size > range_max) || 104 | + (hole->offset < range_min && range_min + size > hole->offset + hole->size) || 105 | + hole->size < size) 106 | + continue; 107 | + offset = hole->offset; 108 | + waste = offset % alignment; 109 | + waste = waste ? alignment - waste : 0; 110 | + offset += waste; 111 | + if (offset >= (hole->offset + hole->size)) { 112 | + continue; 113 | + } 114 | + 115 | + if (!waste && hole->size == size) { 116 | + offset = hole->offset; 117 | + list_del(&hole->list); 118 | + free(hole); 119 | + pthread_mutex_unlock(&mgr->bo_va_mutex); 120 | + return offset; 121 | + } 122 | + if ((hole->size - waste) > size) { 123 | + if (waste) { 124 | + n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); 125 | + n->size = waste; 126 | + n->offset = hole->offset; 127 | + list_add(&n->list, &hole->list); 128 | + } 129 | + hole->size -= (size + waste); 130 | + hole->offset += size + waste; 131 | + pthread_mutex_unlock(&mgr->bo_va_mutex); 132 | + return offset; 133 | + } 134 | + if ((hole->size - waste) == size) { 135 | + hole->size = waste; 136 | + pthread_mutex_unlock(&mgr->bo_va_mutex); 137 | + return offset; 138 | + } 139 | + } 140 | + 141 | + if (mgr->va_offset > range_max) { 142 | + pthread_mutex_unlock(&mgr->bo_va_mutex); 143 | + return AMDGPU_INVALID_VA_ADDRESS; 144 | + } else if (mgr->va_offset > range_min) { 145 | + offset = mgr->va_offset; 146 | + waste = offset % alignment; 147 | + waste = waste ? alignment - waste : 0; 148 | + if (offset + waste + size > range_max) { 149 | + pthread_mutex_unlock(&mgr->bo_va_mutex); 150 | + return AMDGPU_INVALID_VA_ADDRESS; 151 | + } 152 | + } else { 153 | + offset = mgr->va_offset; 154 | + waste = range_min % alignment; 155 | + waste = waste ? alignment - waste : 0; 156 | + waste += range_min - offset ; 157 | + } 158 | + 159 | + if (waste) { 160 | + n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); 161 | + n->size = waste; 162 | + n->offset = offset; 163 | + list_add(&n->list, &mgr->va_holes); 164 | + } 165 | + 166 | + offset += waste; 167 | + mgr->va_offset = size + offset; 168 | + pthread_mutex_unlock(&mgr->bo_va_mutex); 169 | + return offset; 170 | +} 171 | + 172 | drm_private void 173 | amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, uint64_t size) 174 | { 175 | @@ -294,6 +382,87 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, 176 | return 0; 177 | } 178 | 179 | +static int _amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, 180 | + enum amdgpu_gpu_va_range va_range_type, 181 | + uint64_t size, 182 | + uint64_t va_base_alignment, 183 | + uint64_t va_range_min, 184 | + uint64_t va_range_max, 185 | + uint64_t *va_base_allocated, 186 | + amdgpu_va_handle *va_range_handle, 187 | + uint64_t flags) 188 | +{ 189 | + struct amdgpu_bo_va_mgr *vamgr; 190 | + 191 | + if (amdgpu_gpu_va_range_svm == va_range_type) { 192 | + vamgr = &vamgr_svm; 193 | + if (!vamgr->valid) 194 | + return -EINVAL; 195 | + } 196 | + else if (flags & AMDGPU_VA_RANGE_32_BIT) 197 | + vamgr = &dev->vamgr_32; 198 | + else 199 | + vamgr = &dev->vamgr; 200 | + 201 | + va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); 202 | + size = ALIGN(size, vamgr->va_alignment); 203 | + 204 | + *va_base_allocated = amdgpu_vamgr_find_va_in_range(vamgr, size, 205 | + va_base_alignment, va_range_min, va_range_max); 206 | + 207 | + if (!(flags & AMDGPU_VA_RANGE_32_BIT) && 208 | + (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { 209 | + /* fallback to 32bit address */ 210 | + vamgr = &dev->vamgr_32; 211 | + *va_base_allocated = amdgpu_vamgr_find_va_in_range(vamgr, size, 212 | + va_base_alignment, va_range_min, va_range_max); 213 | + } 214 | + 215 | + if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) { 216 | + struct amdgpu_va* va; 217 | + va = calloc(1, sizeof(struct amdgpu_va)); 218 | + if(!va){ 219 | + amdgpu_vamgr_free_va(vamgr, *va_base_allocated, size); 220 | + return -ENOMEM; 221 | + } 222 | + va->dev = dev; 223 | + va->address = *va_base_allocated; 224 | + va->size = size; 225 | + va->range = va_range_type; 226 | + va->vamgr = vamgr; 227 | + *va_range_handle = va; 228 | + } else { 229 | + return -EINVAL; 230 | + } 231 | + 232 | + return 0; 233 | +} 234 | + 235 | +int amdgpu_va_range_alloc_in_range(amdgpu_device_handle dev, 236 | + enum amdgpu_gpu_va_range va_range_type, 237 | + uint64_t size, 238 | + uint64_t va_base_alignment, 239 | + uint64_t va_base_required, 240 | + uint64_t va_range_min, 241 | + uint64_t va_range_max, 242 | + uint64_t *va_base_allocated, 243 | + amdgpu_va_handle *va_range_handle, 244 | + uint64_t flags) 245 | +{ 246 | + if (va_base_required) 247 | + return amdgpu_va_range_alloc(dev, va_range_type, 248 | + size, va_base_alignment, 249 | + va_base_required, va_base_allocated, 250 | + va_range_handle, flags); 251 | + else 252 | + return _amdgpu_va_range_alloc_in_range(dev, 253 | + va_range_type, size, 254 | + va_base_alignment, 255 | + va_range_min, va_range_max, 256 | + va_base_allocated, 257 | + va_range_handle, flags); 258 | +} 259 | + 260 | int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) 261 | { 262 | if(!va_range_handle || !va_range_handle->address) 263 | -- 264 | 2.7.4 265 | 266 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0045-tests-amdgpu-add-alloc-va-from-range-test.patch: -------------------------------------------------------------------------------- 1 | From 9622440df581fd23d8dbf5fb2188b1fdad524b6f Mon Sep 17 00:00:00 2001 2 | From: Flora Cui 3 | Date: Thu, 4 Feb 2016 09:54:32 +0800 4 | Subject: [PATCH 045/117] tests/amdgpu: add alloc va from range test 5 | 6 | Change-Id: I22fa0255ad8f0b7e881a6d4d2de6a054ce3572db 7 | Signed-off-by: Flora Cui 8 | Reviewed-by: Ken Wang 9 | --- 10 | tests/amdgpu/basic_tests.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 11 | 1 file changed, 54 insertions(+) 12 | 13 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 14 | index 408a432..78388a9 100644 15 | --- a/tests/amdgpu/basic_tests.c 16 | +++ b/tests/amdgpu/basic_tests.c 17 | @@ -51,6 +51,7 @@ static void amdgpu_userptr_test(void); 18 | static void amdgpu_semaphore_test(void); 19 | static void amdgpu_svm_test(void); 20 | static void amdgpu_multi_svm_test(void); 21 | +static void amdgpu_va_range_test(void); 22 | 23 | CU_TestInfo basic_tests[] = { 24 | { "Query Info Test", amdgpu_query_info_test }, 25 | @@ -63,6 +64,7 @@ CU_TestInfo basic_tests[] = { 26 | { "SW semaphore Test", amdgpu_semaphore_test }, 27 | { "SVM Test", amdgpu_svm_test }, 28 | { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, 29 | + { "VA range Test", amdgpu_va_range_test}, 30 | CU_TEST_INFO_NULL, 31 | }; 32 | #define BUFFER_SIZE (8 * 1024) 33 | @@ -1380,3 +1382,55 @@ static void amdgpu_multi_svm_test(void) 34 | 35 | amdgpu_svm_deinit(device_handles[0]); 36 | } 37 | + 38 | +#define VA_RANGE_TEST_CNT 66 39 | +#define VA_RANGE_TEST_INT_BEL_CNT 20 40 | +#define VA_RANGE_TEST_INT_ABO_CNT 20 41 | +static void amdgpu_va_range_test(void) 42 | +{ 43 | + amdgpu_va_handle va_handles[VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT]; 44 | + uint64_t va; 45 | + int i, r; 46 | + 47 | + amdgpu_vprintf("\n"); 48 | + amdgpu_vprintf(" Testing to alloc and free VA in user defined range.\n"); 49 | + memset(va_handles, 0, sizeof(va_handles)); 50 | + for (i = 0; i < VA_RANGE_TEST_CNT; i++) { 51 | + r = amdgpu_va_range_alloc_in_range(device_handle, 52 | + amdgpu_gpu_va_range_general, 53 | + 0x1000000, 9, 0, 54 | + 0x800000000, 0x840000000, 55 | + &va, &va_handles[i], 0); 56 | + amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); 57 | + if (!r) 58 | + amdgpu_vprintf(" alloc on addr %#llx\n", va); 59 | + CU_ASSERT_TRUE((r == 0) || 60 | + (r && i>=(0x840000000-0x800000000)/0x1000000)); 61 | + } 62 | + for (i = VA_RANGE_TEST_CNT; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT; i++) { 63 | + r = amdgpu_va_range_alloc_in_range(device_handle, 64 | + amdgpu_gpu_va_range_general, 65 | + 0x1000000, 9, 0, 66 | + 0x600000000, 0x840000000, 67 | + &va, &va_handles[i], 0); 68 | + amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); 69 | + if (!r) 70 | + amdgpu_vprintf(" alloc on addr %#llx\n", va); 71 | + CU_ASSERT_TRUE (r == 0 && va <=0x800000000); 72 | + } 73 | + for (i = VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT; i++) { 74 | + r = amdgpu_va_range_alloc_in_range(device_handle, 75 | + amdgpu_gpu_va_range_general, 76 | + 0x1000000, 9, 0, 77 | + 0x800000000, 0x940000000, 78 | + &va, &va_handles[i], 0); 79 | + amdgpu_vprintf(" test loop %d, alloc %s\n", i, (r==0)? "success" : "fail"); 80 | + if (!r) 81 | + amdgpu_vprintf(" alloc on addr %#llx\n", va); 82 | + CU_ASSERT_TRUE (r == 0 && va >= 0x840000000); 83 | + } 84 | + for (i = 0; i < VA_RANGE_TEST_CNT+VA_RANGE_TEST_INT_BEL_CNT+VA_RANGE_TEST_INT_ABO_CNT; i++) { 85 | + r = amdgpu_va_range_free(va_handles[i]); 86 | + CU_ASSERT_EQUAL(r, 0); 87 | + } 88 | +} 89 | -- 90 | 2.7.4 91 | 92 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0047-tests-amdgpu-move-va_range_test-above-svm_test.patch: -------------------------------------------------------------------------------- 1 | From c7c7f25b214b694541d69bc3fb1a096a1725d6fb Mon Sep 17 00:00:00 2001 2 | From: Flora Cui 3 | Date: Fri, 5 Feb 2016 13:20:27 +0800 4 | Subject: [PATCH 047/117] tests/amdgpu: move va_range_test above svm_test 5 | 6 | svm_test won't release va range at exit. va_range_test would fail as the 7 | desired range is occupied. 8 | 9 | Change-Id: I36bb3c23f185baa26a383e02a87a0b02f613e2d0 10 | Signed-off-by: Flora Cui 11 | --- 12 | tests/amdgpu/basic_tests.c | 2 +- 13 | 1 file changed, 1 insertion(+), 1 deletion(-) 14 | 15 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 16 | index 78388a9..b7e6270 100644 17 | --- a/tests/amdgpu/basic_tests.c 18 | +++ b/tests/amdgpu/basic_tests.c 19 | @@ -62,9 +62,9 @@ CU_TestInfo basic_tests[] = { 20 | { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, 21 | { "Command submission Test (Multi-fence)", amdgpu_command_submission_multi_fence }, 22 | { "SW semaphore Test", amdgpu_semaphore_test }, 23 | + { "VA range Test", amdgpu_va_range_test}, 24 | { "SVM Test", amdgpu_svm_test }, 25 | { "SVM Test (multi-GPUs)", amdgpu_multi_svm_test }, 26 | - { "VA range Test", amdgpu_va_range_test}, 27 | CU_TEST_INFO_NULL, 28 | }; 29 | #define BUFFER_SIZE (8 * 1024) 30 | -- 31 | 2.7.4 32 | 33 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0049-tests-amdgpu-remove-none-amdgpu-devices-for-hybrid-G.patch: -------------------------------------------------------------------------------- 1 | From de7234f8ae699b3c78043a19e32fc7a9596fbeac Mon Sep 17 00:00:00 2001 2 | From: Qiang Yu 3 | Date: Tue, 8 Mar 2016 17:57:06 +0800 4 | Subject: [PATCH 049/117] tests/amdgpu: remove none amdgpu devices for hybrid 5 | GPU platforms 6 | MIME-Version: 1.0 7 | Content-Type: text/plain; charset=UTF-8 8 | Content-Transfer-Encoding: 8bit 9 | 10 | Change-Id: I5991e74ddea212bde4954924de12b26c1ac54936 11 | Signed-off-by: Qiang Yu 12 | Reviewed-by: Christian König 13 | --- 14 | tests/amdgpu/amdgpu_test.c | 22 +++++++++++++++++++++- 15 | 1 file changed, 21 insertions(+), 1 deletion(-) 16 | 17 | diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c 18 | index 46f55c7..dccf221 100644 19 | --- a/tests/amdgpu/amdgpu_test.c 20 | +++ b/tests/amdgpu/amdgpu_test.c 21 | @@ -136,7 +136,7 @@ static const char options[] = "hlvws:t:"; 22 | int main(int argc, char **argv) 23 | { 24 | int c; /* Character received from getopt */ 25 | - int i = 0; 26 | + int i = 0, j = 0; 27 | int suite_id = -1; /* By default run everything */ 28 | int test_id = -1; /* By default run all tests in the suite */ 29 | CU_pSuite pSuite = NULL; 30 | @@ -210,6 +210,26 @@ int main(int argc, char **argv) 31 | } 32 | drmFreeDevices(devices, num_devices); 33 | 34 | + /* remove none amdgpu devices */ 35 | + for (i = 0; i < num_devices; i++) { 36 | + drmVersionPtr retval = drmGetVersion(drm_amdgpu[i]); 37 | + if (retval && !strcmp("amdgpu", retval->name)) { 38 | + if (i != j) { 39 | + drm_amdgpu[j] = drm_amdgpu[i]; 40 | + drm_amdgpu[i] = -1; 41 | + } 42 | + j++; 43 | + } 44 | + else { 45 | + close(drm_amdgpu[i]); 46 | + drm_amdgpu[i] = -1; 47 | + } 48 | + } 49 | + if (drm_amdgpu[0] < 0) { 50 | + perror("no amdgpu device found"); 51 | + exit(EXIT_FAILURE); 52 | + } 53 | + 54 | /** Display version of DRM driver */ 55 | drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); 56 | 57 | -- 58 | 2.7.4 59 | 60 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0056-amdgpu-change-max-allocation.patch: -------------------------------------------------------------------------------- 1 | From fca8e6d4d9638158770745d4da5870a131190b3e Mon Sep 17 00:00:00 2001 2 | From: Chunming Zhou 3 | Date: Wed, 23 Mar 2016 10:29:00 +0800 4 | Subject: [PATCH 056/117] amdgpu: change max allocation 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | Change-Id: I83f8f33140609d4d2c3e54954cc2dc96eeaec6ba 10 | Signed-off-by: Chunming Zhou 11 | Reviewed-by: Michel Dänzer 12 | Reviewed-by: Alex Deucher 13 | --- 14 | amdgpu/amdgpu_gpu_info.c | 4 ++-- 15 | 1 file changed, 2 insertions(+), 2 deletions(-) 16 | 17 | diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c 18 | index 133952d..037df32 100644 19 | --- a/amdgpu/amdgpu_gpu_info.c 20 | +++ b/amdgpu/amdgpu_gpu_info.c 21 | @@ -260,7 +260,7 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, 22 | else /* query total vram heap */ 23 | info->heap_size = vram_gtt_info.vram_size; 24 | 25 | - info->max_allocation = vram_gtt_info.vram_cpu_accessible_size; 26 | + info->max_allocation = vram_gtt_info.vram_size * 3 / 4; 27 | 28 | if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 29 | r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE, 30 | @@ -275,7 +275,7 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, 31 | break; 32 | case AMDGPU_GEM_DOMAIN_GTT: 33 | info->heap_size = vram_gtt_info.gtt_size; 34 | - info->max_allocation = vram_gtt_info.vram_cpu_accessible_size; 35 | + info->max_allocation = vram_gtt_info.gtt_size * 3 / 4; 36 | 37 | r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE, 38 | sizeof(info->heap_usage), 39 | -- 40 | 2.7.4 41 | 42 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0057-amdgpu-fix-print-format-error-V2.patch: -------------------------------------------------------------------------------- 1 | From 4dacb4b7d2f3ac211a485d088e7fcc1760af38db Mon Sep 17 00:00:00 2001 2 | From: Chunming Zhou 3 | Date: Mon, 28 Mar 2016 14:30:03 +0800 4 | Subject: [PATCH 057/117] amdgpu: fix print format error V2 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | V2: use "PRIx64" instead of llx 10 | 11 | Change-Id: Idf79d58abe165f26dc6bc900e10fca30ea740509 12 | Signed-off-by: Chunming Zhou 13 | Reviewed-By: Ken Wang (V1) 14 | Reviewed-by: Michel Dänzer (V2) 15 | 16 | Conflicts: 17 | tests/amdgpu/basic_tests.c 18 | --- 19 | tests/amdgpu/basic_tests.c | 13 +++++++------ 20 | 1 file changed, 7 insertions(+), 6 deletions(-) 21 | 22 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 23 | index b7e6270..f308e9a 100644 24 | --- a/tests/amdgpu/basic_tests.c 25 | +++ b/tests/amdgpu/basic_tests.c 26 | @@ -28,6 +28,7 @@ 27 | #include 28 | #include 29 | #include 30 | +#include 31 | #ifdef HAVE_ALLOCA_H 32 | # include 33 | #endif 34 | @@ -273,17 +274,17 @@ static void amdgpu_query_heap_info_test(void) 35 | amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, 36 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &info); 37 | amdgpu_vprintf("\n Visible VRAM info...\n"); 38 | - amdgpu_vprintf(" size: 0x%x\n", info.heap_size); 39 | - amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); 40 | + amdgpu_vprintf(" size: 0x%"PRIx64"\n", info.heap_size); 41 | + amdgpu_vprintf(" usage: 0x%"PRIx64"\n", info.heap_usage); 42 | amdgpu_vprintf("\n Invisible VRAM info...\n"); 43 | - amdgpu_vprintf(" size: 0x%x\n", total_vram - info.heap_size); 44 | - amdgpu_vprintf(" usage: 0x%x\n", total_vram_used - info.heap_usage); 45 | + amdgpu_vprintf(" size: 0x%"PRIx64"\n", total_vram - info.heap_size); 46 | + amdgpu_vprintf(" usage: 0x%"PRIx64"\n", total_vram_used - info.heap_usage); 47 | 48 | amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, 49 | 0, &info); 50 | amdgpu_vprintf("\n GTT info...\n"); 51 | - amdgpu_vprintf(" size: 0x%x\n", info.heap_size); 52 | - amdgpu_vprintf(" usage: 0x%x\n", info.heap_usage); 53 | + amdgpu_vprintf(" size: 0x%"PRIx64"\n", info.heap_size); 54 | + amdgpu_vprintf(" usage: 0x%"PRIx64"\n", info.heap_usage); 55 | } 56 | 57 | static void amdgpu_query_info_test(void) 58 | -- 59 | 2.7.4 60 | 61 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0061-amdgpu-add-bo-handle-to-hash-table-when-cpu-mapping.patch: -------------------------------------------------------------------------------- 1 | From e5512b2e226abad4e1719b4de4a7427900bc9317 Mon Sep 17 00:00:00 2001 2 | From: Chunming Zhou 3 | Date: Thu, 3 Dec 2015 16:52:33 +0800 4 | Subject: [PATCH 061/117] amdgpu: add bo handle to hash table when cpu mapping 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | Change-Id: Id79d98877c61510a1986d65befec6ce6713edae7 10 | Signed-off-by: Chunming Zhou 11 | Reviewed-by: Jammy Zhou 12 | Reviewed-by: Christian König 13 | --- 14 | amdgpu/amdgpu_bo.c | 2 +- 15 | 1 file changed, 1 insertion(+), 1 deletion(-) 16 | 17 | diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c 18 | index ff78039..aa0d001 100644 19 | --- a/amdgpu/amdgpu_bo.c 20 | +++ b/amdgpu/amdgpu_bo.c 21 | @@ -463,7 +463,7 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) 22 | pthread_mutex_unlock(&bo->cpu_access_mutex); 23 | return -errno; 24 | } 25 | - 26 | + amdgpu_add_handle_to_table(bo); 27 | bo->cpu_ptr = ptr; 28 | bo->cpu_map_count = 1; 29 | pthread_mutex_unlock(&bo->cpu_access_mutex); 30 | -- 31 | 2.7.4 32 | 33 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0062-amdgpu-cs_wait_fences-now-can-return-the-first-signa.patch: -------------------------------------------------------------------------------- 1 | From 52bf3cba5dcb9064c6c174e6a69c0d40cd064594 Mon Sep 17 00:00:00 2001 2 | From: "monk.liu" 3 | Date: Tue, 1 Dec 2015 17:48:18 +0800 4 | Subject: [PATCH 062/117] amdgpu: cs_wait_fences now can return the first 5 | signaled fence index 6 | 7 | Change-Id: Idf3d3bf0f2d2396a77341f97174d0a173fdd8932 8 | Signed-off-by: monk.liu 9 | --- 10 | amdgpu/amdgpu.h | 3 ++- 11 | amdgpu/amdgpu_cs.c | 12 +++++++++--- 12 | include/drm/amdgpu_drm.h | 3 ++- 13 | tests/amdgpu/basic_tests.c | 2 +- 14 | 4 files changed, 14 insertions(+), 6 deletions(-) 15 | 16 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 17 | index 5415bd0..693d841 100644 18 | --- a/amdgpu/amdgpu.h 19 | +++ b/amdgpu/amdgpu.h 20 | @@ -947,6 +947,7 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, 21 | * otherwise, wait at least one fence 22 | * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds 23 | * \param status - \c [out] '1' for signaled, '0' for timeout 24 | + * \param first - \c [out] the index of the first signaled fence from @fences 25 | * 26 | * \return 0 on success 27 | * <0 - Negative POSIX Error code 28 | @@ -958,7 +959,7 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 29 | uint32_t fence_count, 30 | bool wait_all, 31 | uint64_t timeout_ns, 32 | - uint32_t *status); 33 | + uint32_t *status, uint32_t *first); 34 | 35 | /* 36 | * Query / Info API 37 | diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c 38 | index 0c9bcc4..b29e8c9 100644 39 | --- a/amdgpu/amdgpu_cs.c 40 | +++ b/amdgpu/amdgpu_cs.c 41 | @@ -447,7 +447,8 @@ static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, 42 | uint32_t fence_count, 43 | bool wait_all, 44 | uint64_t timeout_ns, 45 | - uint32_t *status) 46 | + uint32_t *status, 47 | + uint32_t *first) 48 | { 49 | struct drm_amdgpu_fence *drm_fences; 50 | amdgpu_device_handle dev = fences[0].context->dev; 51 | @@ -475,6 +476,10 @@ static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, 52 | return -errno; 53 | 54 | *status = args.out.status; 55 | + 56 | + if (first) 57 | + *first = args.out.first_signaled; 58 | + 59 | return 0; 60 | } 61 | 62 | @@ -482,7 +487,8 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 63 | uint32_t fence_count, 64 | bool wait_all, 65 | uint64_t timeout_ns, 66 | - uint32_t *status) 67 | + uint32_t *status, 68 | + uint32_t *first) 69 | { 70 | uint32_t ioctl_status = 0; 71 | uint32_t i; 72 | @@ -507,7 +513,7 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, 73 | *status = 0; 74 | 75 | r = amdgpu_ioctl_wait_fences(fences, fence_count, wait_all, timeout_ns, 76 | - &ioctl_status); 77 | + &ioctl_status, first); 78 | 79 | if (!r) 80 | *status = ioctl_status; 81 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 82 | index e07904c..599c2e7 100644 83 | --- a/include/drm/amdgpu_drm.h 84 | +++ b/include/drm/amdgpu_drm.h 85 | @@ -330,7 +330,8 @@ struct drm_amdgpu_wait_fences_in { 86 | }; 87 | 88 | struct drm_amdgpu_wait_fences_out { 89 | - uint64_t status; 90 | + uint32_t status; 91 | + uint32_t first_signaled; 92 | }; 93 | 94 | union drm_amdgpu_wait_fences { 95 | diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c 96 | index f308e9a..e1aaffc 100644 97 | --- a/tests/amdgpu/basic_tests.c 98 | +++ b/tests/amdgpu/basic_tests.c 99 | @@ -1154,7 +1154,7 @@ static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) 100 | 101 | r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all, 102 | AMDGPU_TIMEOUT_INFINITE, 103 | - &expired); 104 | + &expired, NULL); 105 | CU_ASSERT_EQUAL(r, 0); 106 | 107 | r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 108 | -- 109 | 2.7.4 110 | 111 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0070-amdgpu-add-amdgpu_bo_inc_ref-function.patch: -------------------------------------------------------------------------------- 1 | From 056084ac47a9b6aab3c3815758b31ef961c1297f Mon Sep 17 00:00:00 2001 2 | From: Qiang Yu 3 | Date: Fri, 24 Jun 2016 12:05:22 +0800 4 | Subject: [PATCH 070/117] amdgpu: add amdgpu_bo_inc_ref() function. 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | Change-Id: Icdc00d3e22e48120ca6f4d73ffd05ba43551ad2c 10 | Signed-off-by: Qiang Yu 11 | Reviewed-by: Christian König 12 | --- 13 | amdgpu/amdgpu.h | 13 +++++++++++++ 14 | amdgpu/amdgpu_bo.c | 6 ++++++ 15 | 2 files changed, 19 insertions(+) 16 | 17 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 18 | index 693d841..d8c436f 100644 19 | --- a/amdgpu/amdgpu.h 20 | +++ b/amdgpu/amdgpu.h 21 | @@ -716,6 +716,19 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, 22 | int amdgpu_bo_free(amdgpu_bo_handle buf_handle); 23 | 24 | /** 25 | + * Increase the reference count of a buffer object 26 | + * 27 | + * \param bo - \c [in] Buffer object handle to increase the reference count 28 | + * 29 | + * \return 0 on success\n 30 | + * <0 - Negative POSIX Error code 31 | + * 32 | + * \sa amdgpu_bo_alloc(), amdgpu_bo_free() 33 | + * 34 | +*/ 35 | +int amdgpu_bo_inc_ref(amdgpu_bo_handle bo); 36 | + 37 | +/** 38 | * Request CPU access to GPU accessible memory 39 | * 40 | * \param buf_handle - \c [in] Buffer handle 41 | diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c 42 | index aa0d001..c3f5fb9 100644 43 | --- a/amdgpu/amdgpu_bo.c 44 | +++ b/amdgpu/amdgpu_bo.c 45 | @@ -424,6 +424,12 @@ int amdgpu_bo_free(amdgpu_bo_handle buf_handle) 46 | return 0; 47 | } 48 | 49 | +int amdgpu_bo_inc_ref(amdgpu_bo_handle bo) 50 | +{ 51 | + atomic_inc(&bo->refcount); 52 | + return 0; 53 | +} 54 | + 55 | int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) 56 | { 57 | union drm_amdgpu_gem_mmap args; 58 | -- 59 | 2.7.4 60 | 61 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0073-amdgpu-va-allocation-may-fall-to-the-range-outside-o.patch: -------------------------------------------------------------------------------- 1 | From 1f7873fb8c46e42b4b83110289ac1c9a40ed93dd Mon Sep 17 00:00:00 2001 2 | From: Junwei Zhang 3 | Date: Tue, 28 Jun 2016 17:38:05 +0800 4 | Subject: [PATCH 073/117] amdgpu: va allocation may fall to the range outside 5 | of requested [min,max] 6 | 7 | Change-Id: I3e1db613bdc7495a8968914d8560d5ea3aa6d76c 8 | Signed-off-by: David Mao 9 | Reviewed-by: Ken Wang 10 | --- 11 | amdgpu/amdgpu_vamgr.c | 8 +++++++- 12 | 1 file changed, 7 insertions(+), 1 deletion(-) 13 | 14 | diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c 15 | index 82653e9..f3e38f6 100644 16 | --- a/amdgpu/amdgpu_vamgr.c 17 | +++ b/amdgpu/amdgpu_vamgr.c 18 | @@ -192,10 +192,16 @@ static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint 19 | (hole->offset < range_min && range_min + size > hole->offset + hole->size) || 20 | hole->size < size) 21 | continue; 22 | - offset = hole->offset; 23 | + /* 24 | + * it is possible that the hole covers more than one range, 25 | + * thus we need to respect the range_min 26 | + */ 27 | + offset = MAX2(hole->offset, range_min); 28 | waste = offset % alignment; 29 | waste = waste ? alignment - waste : 0; 30 | offset += waste; 31 | + /* the gap between the range_min and hole->offset need to be covered as well */ 32 | + waste += offset - hole->offset; 33 | if (offset >= (hole->offset + hole->size)) { 34 | continue; 35 | } 36 | -- 37 | 2.7.4 38 | 39 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0074-drm-fix-a-bug-in-va-range-allocation.patch: -------------------------------------------------------------------------------- 1 | From 7508b82630fc31ab2f02e3613747da3a64e05f60 Mon Sep 17 00:00:00 2001 2 | From: Ken Wang 3 | Date: Thu, 30 Jun 2016 11:19:08 +0800 4 | Subject: [PATCH 074/117] drm: fix a bug in va range allocation 5 | 6 | Change-Id: Ic038990a14096ff12e3f309f68fd47d057d6bedd 7 | Signed-off-by: David Mao 8 | Reviewed-by: Ken Wang 9 | --- 10 | amdgpu/amdgpu_vamgr.c | 6 +++++- 11 | 1 file changed, 5 insertions(+), 1 deletion(-) 12 | 13 | diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c 14 | index f3e38f6..1518b7a 100644 15 | --- a/amdgpu/amdgpu_vamgr.c 16 | +++ b/amdgpu/amdgpu_vamgr.c 17 | @@ -201,11 +201,15 @@ static uint64_t amdgpu_vamgr_find_va_in_range(struct amdgpu_bo_va_mgr *mgr, uint 18 | waste = waste ? alignment - waste : 0; 19 | offset += waste; 20 | /* the gap between the range_min and hole->offset need to be covered as well */ 21 | - waste += offset - hole->offset; 22 | + waste = offset - hole->offset; 23 | if (offset >= (hole->offset + hole->size)) { 24 | continue; 25 | } 26 | 27 | + if (offset + size > range_max) { 28 | + continue; 29 | + } 30 | + 31 | if (!waste && hole->size == size) { 32 | offset = hole->offset; 33 | list_del(&hole->list); 34 | -- 35 | 2.7.4 36 | 37 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0077-amdgpu-Make-amdgpu_get_auth-to-non-static.patch: -------------------------------------------------------------------------------- 1 | From 56d1958975665c03e3b291e941402df9891d6a95 Mon Sep 17 00:00:00 2001 2 | From: jqdeng 3 | Date: Tue, 5 Jul 2016 15:46:37 +0800 4 | Subject: [PATCH 077/117] amdgpu: Make amdgpu_get_auth to non-static 5 | 6 | The amdgpu_get_auth will be used by another two functions amdgpu_get_fb_id 7 | and amdgpu_get_bo_from_fb_id, so make it to non-static, and 8 | add definition to amdgpu_internal.h. 9 | 10 | Signed-off-by: jqdeng 11 | Reviewed-by: Chunming Zhou 12 | --- 13 | amdgpu/amdgpu_device.c | 2 +- 14 | amdgpu/amdgpu_internal.h | 14 ++++++++++++++ 15 | 2 files changed, 15 insertions(+), 1 deletion(-) 16 | 17 | diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c 18 | index 8f1f781..e9ea39c 100644 19 | --- a/amdgpu/amdgpu_device.c 20 | +++ b/amdgpu/amdgpu_device.c 21 | @@ -113,7 +113,7 @@ static int fd_compare(void *key1, void *key2) 22 | * >0 - AMD specific error code\n 23 | * <0 - Negative POSIX Error code 24 | */ 25 | -static int amdgpu_get_auth(int fd, int *auth) 26 | +int amdgpu_get_auth(int fd, int *auth) 27 | { 28 | int r = 0; 29 | drm_client_t client = {}; 30 | diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h 31 | index 1160a12..f722ab5 100644 32 | --- a/amdgpu/amdgpu_internal.h 33 | +++ b/amdgpu/amdgpu_internal.h 34 | @@ -159,6 +159,20 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); 35 | drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); 36 | 37 | /** 38 | +* Get the authenticated form fd, 39 | +* 40 | +* \param fd - \c [in] File descriptor for AMD GPU device 41 | +* \param auth - \c [out] Pointer to output the fd is authenticated or not 42 | +* A render node fd, output auth = 0 43 | +* A legacy fd, get the authenticated for compatibility root 44 | +* 45 | +* \return 0 on success\n 46 | +* >0 - AMD specific error code\n 47 | +* <0 - Negative POSIX Error code 48 | +*/ 49 | +int amdgpu_get_auth(int fd, int *auth); 50 | + 51 | +/** 52 | * Inline functions. 53 | */ 54 | 55 | -- 56 | 2.7.4 57 | 58 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0078-amdgpu-Add-interface-amdgpu_get_fb_id.patch: -------------------------------------------------------------------------------- 1 | From 713485538f2f98590cd3e89ec10a8d9e77f304dc Mon Sep 17 00:00:00 2001 2 | From: jqdeng 3 | Date: Tue, 5 Jul 2016 15:43:37 +0800 4 | Subject: [PATCH 078/117] amdgpu: Add interface amdgpu_get_fb_id 5 | 6 | The amdgpu_get_fb_id is used to export the crtc's 7 | framebuffer's buffer id to OpenGL driver for capturing 8 | desktop to OpenGL texture. This is for linux rapidfire server. 9 | 10 | Signed-off-by: jqdeng 11 | Reviewed-by: Chunming Zhou 12 | --- 13 | amdgpu/amdgpu-symbol-check | 1 + 14 | amdgpu/amdgpu.h | 15 +++++++++++++++ 15 | amdgpu/amdgpu_bo.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++ 16 | 3 files changed, 64 insertions(+) 17 | 18 | diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check 19 | index 648db9b..e26ffe2 100755 20 | --- a/amdgpu/amdgpu-symbol-check 21 | +++ b/amdgpu/amdgpu-symbol-check 22 | @@ -48,6 +48,7 @@ amdgpu_read_mm_registers 23 | amdgpu_va_range_alloc 24 | amdgpu_va_range_free 25 | amdgpu_va_range_query 26 | +amdgpu_get_fb_id 27 | EOF 28 | done) 29 | 30 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 31 | index d8c436f..0f31100 100644 32 | --- a/amdgpu/amdgpu.h 33 | +++ b/amdgpu/amdgpu.h 34 | @@ -637,6 +637,21 @@ int amdgpu_bo_import(amdgpu_device_handle dev, 35 | struct amdgpu_bo_import_result *output); 36 | 37 | /** 38 | + * Allow others to get access to crtc's framebuffer 39 | + * 40 | + * \param dev - \c [in] Device handle. 41 | + * See #amdgpu_device_initialize() 42 | + * \param fb_id - \c [out] the first crtc's framebuffer's buffer_id 43 | + * 44 | + * \return 0 on success\n 45 | + * <0 - Negative POSIX Error code 46 | + * 47 | + * \sa amdgpu_get_fb_id() 48 | + * 49 | +*/ 50 | +int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id); 51 | + 52 | +/** 53 | * Request GPU access to user allocated memory e.g. via "malloc" 54 | * 55 | * \param dev - [in] Device handle. See #amdgpu_device_initialize() 56 | diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c 57 | index c3f5fb9..49b951b 100644 58 | --- a/amdgpu/amdgpu_bo.c 59 | +++ b/amdgpu/amdgpu_bo.c 60 | @@ -43,6 +43,7 @@ 61 | #include "amdgpu_internal.h" 62 | #include "util_hash_table.h" 63 | #include "util_math.h" 64 | +#include "xf86drmMode.h" 65 | 66 | static void amdgpu_close_kms_handle(amdgpu_device_handle dev, 67 | uint32_t handle) 68 | @@ -417,6 +418,53 @@ int amdgpu_bo_import(amdgpu_device_handle dev, 69 | return 0; 70 | } 71 | 72 | +/* Get the first use crtc's frame buffer's buffer_id. */ 73 | +int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) 74 | +{ 75 | + drmModeResPtr mode_res; 76 | + int count_crtcs; 77 | + drmModeCrtcPtr mode_crtc; 78 | + int current_id = 0; 79 | + drmModeFBPtr fbcur; 80 | + struct drm_amdgpu_gem_create_in bo_info = {}; 81 | + struct drm_amdgpu_gem_op gem_op = {}; 82 | + int r = 0; 83 | + int i; 84 | + struct amdgpu_bo *bo = NULL; 85 | + int flag_auth = 0; 86 | + int fd = dev->fd; 87 | + 88 | + amdgpu_get_auth(dev->fd, &flag_auth); 89 | + if (flag_auth) { 90 | + fd = dev->fd; 91 | + } else { 92 | + amdgpu_get_auth(dev->flink_fd, &flag_auth); 93 | + if (flag_auth) { 94 | + fd = dev->flink_fd; 95 | + } else { 96 | + fprintf(stderr, "amdgpu: amdgpu_get_fb_id, couldn't get the auth fd\n"); 97 | + return EINVAL; 98 | + } 99 | + } 100 | + 101 | + mode_res = drmModeGetResources(fd); 102 | + if (!mode_res) 103 | + return EFAULT; 104 | + 105 | + count_crtcs = mode_res->count_crtcs; 106 | + for (i = 0; i < mode_res->count_crtcs; i++) { 107 | + mode_crtc = drmModeGetCrtc(fd, mode_res->crtcs[i]); 108 | + if (mode_crtc->buffer_id) { 109 | + current_id = mode_crtc->buffer_id; 110 | + if (current_id != NULL) 111 | + break; 112 | + } 113 | + } 114 | + *fb_id = current_id; 115 | + 116 | + return r; 117 | +} 118 | + 119 | int amdgpu_bo_free(amdgpu_bo_handle buf_handle) 120 | { 121 | /* Just drop the reference. */ 122 | -- 123 | 2.7.4 124 | 125 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0079-amdgpu-Add-interface-amdgpu_get_bo_from_fb_id.patch: -------------------------------------------------------------------------------- 1 | From 562a5585d1c46a99b192c6cf080eb2aad582fa25 Mon Sep 17 00:00:00 2001 2 | From: jqdeng 3 | Date: Tue, 5 Jul 2016 15:44:51 +0800 4 | Subject: [PATCH 079/117] amdgpu: Add interface amdgpu_get_bo_from_fb_id 5 | 6 | The amdgpu_get_bo_from_fb_id is used to export the 7 | crtc's framebuffer's buffer object to OpenGL driver for capturing desktop to 8 | OpenGL texture.This is alse used by linux rapidfire server. 9 | 10 | Signed-off-by: jqdeng 11 | Reviewed-by: Chunming Zhou 12 | --- 13 | amdgpu/amdgpu-symbol-check | 1 + 14 | amdgpu/amdgpu.h | 17 +++++++++ 15 | amdgpu/amdgpu_bo.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++ 16 | 3 files changed, 110 insertions(+) 17 | 18 | diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check 19 | index e26ffe2..028ff78 100755 20 | --- a/amdgpu/amdgpu-symbol-check 21 | +++ b/amdgpu/amdgpu-symbol-check 22 | @@ -49,6 +49,7 @@ amdgpu_va_range_alloc 23 | amdgpu_va_range_free 24 | amdgpu_va_range_query 25 | amdgpu_get_fb_id 26 | +amdgpu_get_bo_from_fb_id 27 | EOF 28 | done) 29 | 30 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 31 | index 0f31100..08593ca 100644 32 | --- a/amdgpu/amdgpu.h 33 | +++ b/amdgpu/amdgpu.h 34 | @@ -652,6 +652,23 @@ int amdgpu_bo_import(amdgpu_device_handle dev, 35 | int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id); 36 | 37 | /** 38 | + * Get the framebuffer's bo by fb_id 39 | + * 40 | + * \param dev - \c [in] Device handle. 41 | + * See #amdgpu_device_initialize() 42 | + * \param fb_id - \c [in] the framebuffer's buffer_id 43 | + * 44 | + * \param output - \c [output] the bo of fb_id 45 | + * 46 | + * \return 0 on success\n 47 | + * <0 - Negative POSIX Error code 48 | + * 49 | + * \sa amdgpu_get_bo_from_fb_id() 50 | + * 51 | +*/ 52 | +int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struct amdgpu_bo_import_result *output); 53 | + 54 | +/** 55 | * Request GPU access to user allocated memory e.g. via "malloc" 56 | * 57 | * \param dev - [in] Device handle. See #amdgpu_device_initialize() 58 | diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c 59 | index 49b951b..f311b94 100644 60 | --- a/amdgpu/amdgpu_bo.c 61 | +++ b/amdgpu/amdgpu_bo.c 62 | @@ -465,6 +465,98 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) 63 | return r; 64 | } 65 | 66 | +/* Get the frame buffer's gem object handle by the fb_id. */ 67 | +int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struct amdgpu_bo_import_result *output) 68 | +{ 69 | + drmModeFBPtr fbcur; 70 | + struct drm_amdgpu_gem_create_in bo_info = {}; 71 | + struct drm_amdgpu_gem_op gem_op = {}; 72 | + int r = 0; 73 | + int i; 74 | + struct amdgpu_bo *bo = NULL; 75 | + int dma_fd; 76 | + int flag_auth = 0; 77 | + int fd = dev->fd; 78 | + 79 | + amdgpu_get_auth(dev->fd, &flag_auth); 80 | + if (flag_auth) { 81 | + fd = dev->fd; 82 | + } else { 83 | + amdgpu_get_auth(dev->flink_fd, &flag_auth); 84 | + if (flag_auth) { 85 | + fd = dev->flink_fd; 86 | + } else { 87 | + fprintf(stderr, "amdgpu: amdgpu_get_bo_from_fb_id, couldn't get the auth fd\n"); 88 | + return EINVAL; 89 | + } 90 | + } 91 | + 92 | + fbcur = drmModeGetFB(fd, fb_id); 93 | + 94 | + pthread_mutex_lock(&dev->bo_table_mutex); 95 | + if (fd != dev->fd) { 96 | + r = drmPrimeHandleToFD(fd, fbcur->handle, DRM_CLOEXEC, &dma_fd); 97 | + if (r) { 98 | + pthread_mutex_unlock(&dev->bo_table_mutex); 99 | + return r; 100 | + } 101 | + r = drmPrimeFDToHandle(dev->fd, dma_fd, &fbcur->handle ); 102 | + 103 | + close(dma_fd); 104 | + 105 | + if (r) { 106 | + pthread_mutex_unlock(&dev->bo_table_mutex); 107 | + return r; 108 | + } 109 | + } 110 | + bo = util_hash_table_get(dev->bo_handles, 111 | + (void*)(uintptr_t)fbcur->handle); 112 | + 113 | + if (bo) { 114 | + pthread_mutex_unlock(&dev->bo_table_mutex); 115 | + 116 | + /* The buffer already exists, just bump the refcount. */ 117 | + atomic_inc(&bo->refcount); 118 | + 119 | + output->buf_handle = bo; 120 | + output->alloc_size = bo->alloc_size; 121 | + return 0; 122 | + } 123 | + 124 | + bo = calloc(1, sizeof(struct amdgpu_bo)); 125 | + if (!bo) { 126 | + pthread_mutex_unlock(&dev->bo_table_mutex); 127 | + return -ENOMEM; 128 | + } 129 | + 130 | + /* Query buffer info. */ 131 | + gem_op.handle = fbcur->handle; 132 | + gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO; 133 | + gem_op.value = (uintptr_t)&bo_info; 134 | + 135 | + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_OP, 136 | + &gem_op, sizeof(gem_op)); 137 | + if (r) { 138 | + free(bo); 139 | + pthread_mutex_unlock(&dev->bo_table_mutex); 140 | + return r; 141 | + } 142 | + 143 | + /* Initialize it. */ 144 | + atomic_set(&bo->refcount, 1); 145 | + bo->handle = fbcur->handle; 146 | + bo->dev = dev; 147 | + bo->alloc_size = bo_info.bo_size; 148 | + output->buf_handle = bo; 149 | + pthread_mutex_init(&bo->cpu_access_mutex, NULL); 150 | + 151 | + util_hash_table_set(dev->bo_handles, (void*)(uintptr_t)bo->handle, bo); 152 | + pthread_mutex_unlock(&dev->bo_table_mutex); 153 | + 154 | + output->alloc_size = bo->alloc_size; 155 | + return r; 156 | +} 157 | + 158 | int amdgpu_bo_free(amdgpu_bo_handle buf_handle) 159 | { 160 | /* Just drop the reference. */ 161 | -- 162 | 2.7.4 163 | 164 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0080-amdgpu-tests-Add-the-test-case-for-amdgpu_get_fb_id-.patch: -------------------------------------------------------------------------------- 1 | From da3e76d7d0dacc732927990344dbe40e69abb8f0 Mon Sep 17 00:00:00 2001 2 | From: jqdeng 3 | Date: Tue, 5 Jul 2016 15:45:33 +0800 4 | Subject: [PATCH 080/117] amdgpu/tests: Add the test case for amdgpu_get_fb_id 5 | and amdgpu_get_bo_from_fb_id. 6 | 7 | Signed-off-by: jqdeng 8 | Reviewed-by: Chunming Zhou 9 | --- 10 | tests/amdgpu/bo_tests.c | 18 ++++++++++++++++++ 11 | 1 file changed, 18 insertions(+) 12 | 13 | diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c 14 | index 993895d..195667f 100644 15 | --- a/tests/amdgpu/bo_tests.c 16 | +++ b/tests/amdgpu/bo_tests.c 17 | @@ -46,6 +46,8 @@ static amdgpu_va_handle va_handle; 18 | static void amdgpu_bo_export_import(void); 19 | static void amdgpu_bo_metadata(void); 20 | static void amdgpu_bo_map_unmap(void); 21 | +static void amdgpu_get_fb_id_and_handle(void); 22 | + 23 | 24 | CU_TestInfo bo_tests[] = { 25 | { "Export/Import", amdgpu_bo_export_import }, 26 | @@ -53,6 +55,7 @@ CU_TestInfo bo_tests[] = { 27 | { "Metadata", amdgpu_bo_metadata }, 28 | #endif 29 | { "CPU map/unmap", amdgpu_bo_map_unmap }, 30 | + { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, 31 | CU_TEST_INFO_NULL, 32 | }; 33 | 34 | @@ -184,3 +187,18 @@ static void amdgpu_bo_map_unmap(void) 35 | r = amdgpu_bo_cpu_unmap(buffer_handle); 36 | CU_ASSERT_EQUAL(r, 0); 37 | } 38 | + 39 | +static void amdgpu_get_fb_id_and_handle(void) 40 | +{ 41 | + uint32_t *ptr; 42 | + int i, r; 43 | + unsigned int fb_id; 44 | + struct amdgpu_bo_import_result output; 45 | + 46 | + r = amdgpu_get_fb_id(device_handle, &fb_id); 47 | + CU_ASSERT_EQUAL(r, 0); 48 | + CU_ASSERT_NOT_EQUAL(fb_id, 0); 49 | + r = amdgpu_get_bo_from_fb_id(device_handle, fb_id, &output); 50 | + CU_ASSERT_EQUAL(r, 0); 51 | + CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); 52 | +} 53 | -- 54 | 2.7.4 55 | 56 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0082-amdgpu-Fix-memory-leak-in-amdgpu_get_fb_id.patch: -------------------------------------------------------------------------------- 1 | From 3edba3d8135eb76e45d6cac2681414a2af790b0c Mon Sep 17 00:00:00 2001 2 | From: jqdeng 3 | Date: Thu, 14 Jul 2016 17:33:13 +0800 4 | Subject: [PATCH 082/117] amdgpu: Fix memory leak in amdgpu_get_fb_id 5 | 6 | Signed-off-by: jqdeng 7 | Reviewed-by: Jim Qu 8 | --- 9 | amdgpu/amdgpu_bo.c | 10 +++++++--- 10 | 1 file changed, 7 insertions(+), 3 deletions(-) 11 | 12 | diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c 13 | index f311b94..ebfb7cf 100644 14 | --- a/amdgpu/amdgpu_bo.c 15 | +++ b/amdgpu/amdgpu_bo.c 16 | @@ -454,13 +454,17 @@ int amdgpu_get_fb_id(amdgpu_device_handle dev, unsigned int *fb_id) 17 | count_crtcs = mode_res->count_crtcs; 18 | for (i = 0; i < mode_res->count_crtcs; i++) { 19 | mode_crtc = drmModeGetCrtc(fd, mode_res->crtcs[i]); 20 | - if (mode_crtc->buffer_id) { 21 | - current_id = mode_crtc->buffer_id; 22 | - if (current_id != NULL) 23 | + if (mode_crtc) { 24 | + if (mode_crtc->buffer_id) { 25 | + current_id = mode_crtc->buffer_id; 26 | + drmModeFreeCrtc(mode_crtc); 27 | break; 28 | + } 29 | + drmModeFreeCrtc(mode_crtc); 30 | } 31 | } 32 | *fb_id = current_id; 33 | + drmModeFreeResources(mode_res); 34 | 35 | return r; 36 | } 37 | -- 38 | 2.7.4 39 | 40 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0083-amdgpu-Fix-memory-leak-in-amdgpu_get_bo_from_fb_id.patch: -------------------------------------------------------------------------------- 1 | From 2f5986c7208a9b8534f2fb0981fc5d5fd7c65e30 Mon Sep 17 00:00:00 2001 2 | From: jqdeng 3 | Date: Thu, 14 Jul 2016 17:32:27 +0800 4 | Subject: [PATCH 083/117] amdgpu: Fix memory leak in amdgpu_get_bo_from_fb_id 5 | 6 | Signed-off-by: jqdeng 7 | Reviewed-by: Jim Qu 8 | --- 9 | amdgpu/amdgpu_bo.c | 9 +++++++++ 10 | 1 file changed, 9 insertions(+) 11 | 12 | diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c 13 | index ebfb7cf..a07d0b5 100644 14 | --- a/amdgpu/amdgpu_bo.c 15 | +++ b/amdgpu/amdgpu_bo.c 16 | @@ -497,11 +497,15 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc 17 | 18 | fbcur = drmModeGetFB(fd, fb_id); 19 | 20 | + if (fbcur == NULL) 21 | + return EFAULT; 22 | + 23 | pthread_mutex_lock(&dev->bo_table_mutex); 24 | if (fd != dev->fd) { 25 | r = drmPrimeHandleToFD(fd, fbcur->handle, DRM_CLOEXEC, &dma_fd); 26 | if (r) { 27 | pthread_mutex_unlock(&dev->bo_table_mutex); 28 | + drmModeFreeFB(fbcur); 29 | return r; 30 | } 31 | r = drmPrimeFDToHandle(dev->fd, dma_fd, &fbcur->handle ); 32 | @@ -510,6 +514,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc 33 | 34 | if (r) { 35 | pthread_mutex_unlock(&dev->bo_table_mutex); 36 | + drmModeFreeFB(fbcur); 37 | return r; 38 | } 39 | } 40 | @@ -524,12 +529,14 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc 41 | 42 | output->buf_handle = bo; 43 | output->alloc_size = bo->alloc_size; 44 | + drmModeFreeFB(fbcur); 45 | return 0; 46 | } 47 | 48 | bo = calloc(1, sizeof(struct amdgpu_bo)); 49 | if (!bo) { 50 | pthread_mutex_unlock(&dev->bo_table_mutex); 51 | + drmModeFreeFB(fbcur); 52 | return -ENOMEM; 53 | } 54 | 55 | @@ -543,6 +550,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc 56 | if (r) { 57 | free(bo); 58 | pthread_mutex_unlock(&dev->bo_table_mutex); 59 | + drmModeFreeFB(fbcur); 60 | return r; 61 | } 62 | 63 | @@ -558,6 +566,7 @@ int amdgpu_get_bo_from_fb_id(amdgpu_device_handle dev, unsigned int fb_id, struc 64 | pthread_mutex_unlock(&dev->bo_table_mutex); 65 | 66 | output->alloc_size = bo->alloc_size; 67 | + drmModeFreeFB(fbcur); 68 | return r; 69 | } 70 | 71 | -- 72 | 2.7.4 73 | 74 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0104-drm-amdgpu-add-freesync-ioctl-defines.patch: -------------------------------------------------------------------------------- 1 | From bd51d57069011aef5372d68942cee32a13013108 Mon Sep 17 00:00:00 2001 2 | From: Hawking Zhang 3 | Date: Thu, 4 Aug 2016 14:26:51 +0800 4 | Subject: [PATCH 104/117] drm/amdgpu: add freesync ioctl defines 5 | 6 | Change-Id: Id5d607fee4ae119015ca685a508a2ee140a8e331 7 | Signed-off-by: Hawking Zhang 8 | Reviewed-by: Flora Cui 9 | --- 10 | include/drm/amdgpu_drm.h | 15 +++++++++++++++ 11 | 1 file changed, 15 insertions(+) 12 | 13 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 14 | index 9aa0420..7ffd26b 100644 15 | --- a/include/drm/amdgpu_drm.h 16 | +++ b/include/drm/amdgpu_drm.h 17 | @@ -48,6 +48,7 @@ 18 | #define DRM_AMDGPU_GEM_USERPTR 0x11 19 | #define DRM_AMDGPU_WAIT_FENCES 0x12 20 | #define DRM_AMDGPU_GEM_FIND_BO 0x13 21 | +#define DRM_AMDGPU_FREESYNC 0x14 22 | 23 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 24 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 25 | @@ -63,6 +64,7 @@ 26 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 27 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 28 | #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) 29 | +#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) 30 | 31 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 32 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 33 | @@ -708,4 +710,17 @@ struct drm_amdgpu_virtual_range { 34 | uint64_t start; 35 | uint64_t end; 36 | }; 37 | + 38 | +/* 39 | + * Definition of free sync enter and exit signals 40 | + * We may have more options in the future 41 | + */ 42 | +#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 43 | +#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 44 | + 45 | +struct drm_amdgpu_freesync { 46 | + __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ 47 | + /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ 48 | + __u32 spare[7]; 49 | +}; 50 | #endif 51 | -- 52 | 2.7.4 53 | 54 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0108-amdgpu-tests-add-Polaris12-support-for-cs-test.patch: -------------------------------------------------------------------------------- 1 | From 38ff3dfb8dee467e37c1416a5c6d1cd9891426fc Mon Sep 17 00:00:00 2001 2 | From: Junwei Zhang 3 | Date: Wed, 10 Aug 2016 13:49:04 +0800 4 | Subject: [PATCH 108/117] amdgpu/tests: add Polaris12 support for cs test 5 | 6 | Change-Id: Ida31ea85ad851dbe41599a4d791ad2cbd0a14ee5 7 | Signed-off-by: Junwei Zhang 8 | Reviewed-by: Ken Wang 9 | --- 10 | tests/amdgpu/cs_tests.c | 13 +++++++++---- 11 | 1 file changed, 9 insertions(+), 4 deletions(-) 12 | 13 | diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c 14 | index 2c9c1ae..6c4a915 100644 15 | --- a/tests/amdgpu/cs_tests.c 16 | +++ b/tests/amdgpu/cs_tests.c 17 | @@ -208,8 +208,10 @@ static void amdgpu_cs_uvd_create(void) 18 | if (family_id >= AMDGPU_FAMILY_VI) { 19 | ((uint8_t*)msg)[0x10] = 7; 20 | /* chip polaris 10/11 */ 21 | - if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { 22 | + if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A 23 | + || chip_id == chip_rev+0x64) { 24 | /* dpb size */ 25 | + printf("===> chip_rev = %d, chip_id = 0x%x\n", chip_rev, chip_id); 26 | ((uint8_t*)msg)[0x28] = 0x00; 27 | ((uint8_t*)msg)[0x29] = 0x94; 28 | ((uint8_t*)msg)[0x2A] = 0x6B; 29 | @@ -286,7 +288,8 @@ static void amdgpu_cs_uvd_decode(void) 30 | ptr[0x98] = 0x00; 31 | ptr[0x99] = 0x02; 32 | /* chip polaris10/11 */ 33 | - if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) { 34 | + if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A 35 | + || chip_id == chip_rev+0x64) { 36 | /*dpb size */ 37 | ptr[0x24] = 0x00; 38 | ptr[0x25] = 0x94; 39 | @@ -330,7 +333,8 @@ static void amdgpu_cs_uvd_decode(void) 40 | dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); 41 | 42 | if ((family_id >= AMDGPU_FAMILY_VI) && 43 | - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) { 44 | + (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A 45 | + || chip_id == chip_rev+0x64)) { 46 | ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); 47 | } 48 | 49 | @@ -344,7 +348,8 @@ static void amdgpu_cs_uvd_decode(void) 50 | uvd_cmd(bs_addr, 0x100, &i); 51 | if (family_id >= AMDGPU_FAMILY_VI) { 52 | uvd_cmd(it_addr, 0x204, &i); 53 | - if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) 54 | + if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || 55 | + chip_id == chip_rev+0x64) 56 | uvd_cmd(ctx_addr, 0x206, &i); 57 | } 58 | ib_cpu[i++] = 0x3BC6; 59 | -- 60 | 2.7.4 61 | 62 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0109-amdgpu-tests-remove-debug-info-in-cs-test.patch: -------------------------------------------------------------------------------- 1 | From 51f97fee7269b84d498899fac0a1649131c3d5cc Mon Sep 17 00:00:00 2001 2 | From: Junwei Zhang 3 | Date: Wed, 10 Aug 2016 15:16:43 +0800 4 | Subject: [PATCH 109/117] amdgpu/tests: remove debug info in cs test 5 | MIME-Version: 1.0 6 | Content-Type: text/plain; charset=UTF-8 7 | Content-Transfer-Encoding: 8bit 8 | 9 | Change-Id: Ic11256fe3f8fd6d80f4eefc85b9ea0ba665dc4fe 10 | Signed-off-by: Junwei Zhang 11 | Reviewed-by: Christian König 12 | --- 13 | tests/amdgpu/cs_tests.c | 1 - 14 | 1 file changed, 1 deletion(-) 15 | 16 | diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c 17 | index 6c4a915..ca741b7 100644 18 | --- a/tests/amdgpu/cs_tests.c 19 | +++ b/tests/amdgpu/cs_tests.c 20 | @@ -211,7 +211,6 @@ static void amdgpu_cs_uvd_create(void) 21 | if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A 22 | || chip_id == chip_rev+0x64) { 23 | /* dpb size */ 24 | - printf("===> chip_rev = %d, chip_id = 0x%x\n", chip_rev, chip_id); 25 | ((uint8_t*)msg)[0x28] = 0x00; 26 | ((uint8_t*)msg)[0x29] = 0x94; 27 | ((uint8_t*)msg)[0x2A] = 0x6B; 28 | -- 29 | 2.7.4 30 | 31 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0114-amdgpu-add-more-capability-query.patch: -------------------------------------------------------------------------------- 1 | From 7e00543c422f00a68edb4227eeb56ba48175b399 Mon Sep 17 00:00:00 2001 2 | From: Flora Cui 3 | Date: Thu, 11 Aug 2016 15:23:35 +0800 4 | Subject: [PATCH 114/117] amdgpu: add more capability query 5 | 6 | Change-Id: Ia77feea215a4eb7d0e41684fa5c9e44eedf7feb8 7 | Signed-off-by: Flora Cui 8 | --- 9 | amdgpu/amdgpu.h | 4 +++- 10 | amdgpu/amdgpu_gpu_info.c | 5 +++-- 11 | include/drm/amdgpu_drm.h | 12 ++++++++++-- 12 | 3 files changed, 16 insertions(+), 5 deletions(-) 13 | 14 | diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h 15 | index 08593ca..763a3a6 100644 16 | --- a/amdgpu/amdgpu.h 17 | +++ b/amdgpu/amdgpu.h 18 | @@ -38,6 +38,7 @@ 19 | #include 20 | 21 | struct drm_amdgpu_info_hw_ip; 22 | +struct drm_amdgpu_capability; 23 | 24 | /*--------------------------------------------------------------------------*/ 25 | /* --------------------------- Defines ------------------------------------ */ 26 | @@ -1155,7 +1156,8 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 27 | * <0 - Negative POSIX error code 28 | * 29 | */ 30 | -int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value); 31 | +int amdgpu_query_capability(amdgpu_device_handle dev, 32 | + struct drm_amdgpu_capability *cap); 33 | 34 | /** 35 | * Query information about GDS 36 | diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c 37 | index 037df32..406baf2 100644 38 | --- a/amdgpu/amdgpu_gpu_info.c 39 | +++ b/amdgpu/amdgpu_gpu_info.c 40 | @@ -48,10 +48,11 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, 41 | sizeof(struct drm_amdgpu_info)); 42 | } 43 | 44 | -int amdgpu_query_capability(amdgpu_device_handle dev, uint64_t *value) 45 | +int amdgpu_query_capability(amdgpu_device_handle dev, 46 | + struct drm_amdgpu_capability *cap) 47 | { 48 | return amdgpu_query_info(dev, AMDGPU_INFO_CAPABILITY, 49 | - sizeof(uint64_t), value); 50 | + sizeof(struct drm_amdgpu_capability), cap); 51 | } 52 | 53 | int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, 54 | diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h 55 | index cda8f36..14d800e 100644 56 | --- a/include/drm/amdgpu_drm.h 57 | +++ b/include/drm/amdgpu_drm.h 58 | @@ -530,8 +530,6 @@ struct drm_amdgpu_cs_chunk_data { 59 | 60 | /* gpu capability */ 61 | #define AMDGPU_INFO_CAPABILITY 0x50 62 | -/* query pin memory capability */ 63 | -#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) 64 | 65 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 66 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 67 | @@ -713,6 +711,16 @@ struct drm_amdgpu_virtual_range { 68 | uint64_t end; 69 | }; 70 | 71 | +/* query pin memory capability */ 72 | +#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) 73 | +/* query direct gma capability */ 74 | +#define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1) 75 | + 76 | +struct drm_amdgpu_capability { 77 | + uint32_t flag; 78 | + uint32_t direct_gma_size; 79 | +}; 80 | + 81 | /* 82 | * Definition of free sync enter and exit signals 83 | * We may have more options in the future 84 | -- 85 | 2.7.4 86 | 87 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/amd-patches/0116-tests-amdgpu-add-direct-gma-test.patch: -------------------------------------------------------------------------------- 1 | From 331577c5a8736f15fdf55a7606414efcf78a5dff Mon Sep 17 00:00:00 2001 2 | From: Flora Cui 3 | Date: Thu, 11 Aug 2016 15:26:16 +0800 4 | Subject: [PATCH 116/117] tests/amdgpu: add direct gma test 5 | 6 | Change-Id: Ib00252eff16a84f16f01039ff39f957bff903bae 7 | Signed-off-by: Flora Cui 8 | --- 9 | tests/amdgpu/bo_tests.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++- 10 | 1 file changed, 63 insertions(+), 1 deletion(-) 11 | 12 | diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c 13 | index 195667f..5d1f67b 100644 14 | --- a/tests/amdgpu/bo_tests.c 15 | +++ b/tests/amdgpu/bo_tests.c 16 | @@ -26,6 +26,7 @@ 17 | #endif 18 | 19 | #include 20 | +#include 21 | 22 | #include "CUnit/Basic.h" 23 | 24 | @@ -47,7 +48,7 @@ static void amdgpu_bo_export_import(void); 25 | static void amdgpu_bo_metadata(void); 26 | static void amdgpu_bo_map_unmap(void); 27 | static void amdgpu_get_fb_id_and_handle(void); 28 | - 29 | +static void amdgpu_bo_direct_gma(void); 30 | 31 | CU_TestInfo bo_tests[] = { 32 | { "Export/Import", amdgpu_bo_export_import }, 33 | @@ -56,6 +57,7 @@ CU_TestInfo bo_tests[] = { 34 | #endif 35 | { "CPU map/unmap", amdgpu_bo_map_unmap }, 36 | { "GET FB_ID AND FB_HANDLE", amdgpu_get_fb_id_and_handle }, 37 | + { "Direct GMA", amdgpu_bo_direct_gma }, 38 | CU_TEST_INFO_NULL, 39 | }; 40 | 41 | @@ -202,3 +204,63 @@ static void amdgpu_get_fb_id_and_handle(void) 42 | CU_ASSERT_EQUAL(r, 0); 43 | CU_ASSERT_NOT_EQUAL(output.buf_handle, 0); 44 | } 45 | + 46 | +#define TEST_LOOP 20 47 | +static void amdgpu_bo_direct_gma(void) 48 | +{ 49 | + amdgpu_bo_handle buf_handle[TEST_LOOP] = {0}; 50 | + amdgpu_bo_handle buf_handle_import[TEST_LOOP] = {0}; 51 | + uint32_t *ptr[TEST_LOOP] = {0}; 52 | + struct amdgpu_bo_alloc_request req = {0}; 53 | + struct drm_amdgpu_capability cap; 54 | + uint64_t size=4096, phys_addr, remain; 55 | + int i, j, r; 56 | + 57 | + amdgpu_query_capability(device_handle, &cap); 58 | + if(!(cap.flag & AMDGPU_CAPABILITY_DIRECT_GMA_FLAG)) 59 | + return; 60 | + 61 | + amdgpu_vprintf("direct_gma_size is %d MB\n", cap.direct_gma_size); 62 | + remain = cap.direct_gma_size << 20; 63 | + 64 | + req.preferred_heap = AMDGPU_GEM_DOMAIN_DGMA; 65 | + for (i = 0; i < TEST_LOOP; i++) { 66 | + req.alloc_size = size; 67 | + r = amdgpu_bo_alloc(device_handle, &req, &buf_handle[i]); 68 | + CU_ASSERT_EQUAL(r, 0); 69 | + 70 | + r = amdgpu_bo_get_phys_address(buf_handle[i], &phys_addr); 71 | + CU_ASSERT_EQUAL(r, 0); 72 | + amdgpu_vprintf("bo_size %"PRIx64" phys_addr %"PRIx64"\n", size, phys_addr); 73 | + r = amdgpu_create_bo_from_phys_mem(device_handle, phys_addr, size, &buf_handle_import[i]); 74 | + CU_ASSERT_EQUAL(r, 0); 75 | + r = amdgpu_bo_cpu_map(buf_handle_import[i], (void **)&ptr[i]); 76 | + CU_ASSERT_EQUAL(r, 0); 77 | + 78 | + for (j = 0; j < (size / 4); ++j) 79 | + ptr[i][j] = 0xdeadbeef; 80 | + remain -= size; 81 | + size <<= 1; 82 | + amdgpu_vprintf("test loop %d finished, remain %"PRIx64", try to alloc %"PRIx64"\n", i, remain, size); 83 | + if (remain < size) 84 | + break; 85 | + 86 | + } 87 | + 88 | + for (i = 0; i < TEST_LOOP; i++) { 89 | + if (ptr[i]) { 90 | + r = amdgpu_bo_cpu_unmap(buf_handle_import[i]); 91 | + CU_ASSERT_EQUAL(r, 0); 92 | + } 93 | + 94 | + if (buf_handle_import[i]) { 95 | + r = amdgpu_bo_free(buf_handle_import[i]); 96 | + CU_ASSERT_EQUAL(r, 0); 97 | + } 98 | + 99 | + if (buf_handle[i]) { 100 | + r = amdgpu_bo_free(buf_handle[i]); 101 | + CU_ASSERT_EQUAL(r, 0); 102 | + } 103 | + } 104 | +} 105 | -- 106 | 2.7.4 107 | 108 | -------------------------------------------------------------------------------- /x11-libs/libdrm/files/libdrm-2.4.74-liverpool.patch: -------------------------------------------------------------------------------- 1 | diff -urN libdrm-2.4.74-old/amdgpu/amdgpu_asic_id.h libdrm-2.4.74/amdgpu/amdgpu_asic_id.h 2 | --- libdrm-2.4.74-old/amdgpu/amdgpu_asic_id.h 2017-01-02 17:41:32.563295529 +0100 3 | +++ libdrm-2.4.74/amdgpu/amdgpu_asic_id.h 2017-01-02 17:49:47.470931471 +0100 4 | @@ -159,6 +159,7 @@ 5 | {0x9874, 0x87, "AMD Radeon R5 Graphics"}, 6 | {0x9874, 0x85, "AMD Radeon R6 Graphics"}, 7 | {0x9874, 0x84, "AMD Radeon R7 Graphics"}, 8 | + {0x9920, 0x0, "AMD Liverpool (PlayStation 4)"}, 9 | 10 | {0x0000, 0x0, "\0"}, 11 | }; 12 | diff -urN libdrm-2.4.74-old/radeon/r600_pci_ids.h libdrm-2.4.74/radeon/r600_pci_ids.h 13 | --- libdrm-2.4.74-old/radeon/r600_pci_ids.h 2017-01-02 17:41:32.548295669 +0100 14 | +++ libdrm-2.4.74/radeon/r600_pci_ids.h 2017-01-02 17:41:41.121216578 +0100 15 | @@ -450,6 +450,8 @@ 16 | CHIPSET(0x985E, MULLINS_985E, MULLINS) 17 | CHIPSET(0x985F, MULLINS_985F, MULLINS) 18 | 19 | +CHIPSET(0x9920, LIVERPOOL_9920, LIVERPOOL) 20 | + 21 | CHIPSET(0x1304, KAVERI_1304, KAVERI) 22 | CHIPSET(0x1305, KAVERI_1305, KAVERI) 23 | CHIPSET(0x1306, KAVERI_1306, KAVERI) 24 | diff -urN libdrm-2.4.74-old/radeon/radeon_surface.c libdrm-2.4.74/radeon/radeon_surface.c 25 | --- libdrm-2.4.74-old/radeon/radeon_surface.c 2017-01-02 17:41:32.549295660 +0100 26 | +++ libdrm-2.4.74/radeon/radeon_surface.c 2017-01-02 17:41:41.122216569 +0100 27 | @@ -90,6 +90,7 @@ 28 | CHIP_BONAIRE, 29 | CHIP_KAVERI, 30 | CHIP_KABINI, 31 | + CHIP_LIVERPOOL, 32 | CHIP_HAWAII, 33 | CHIP_MULLINS, 34 | CHIP_LAST, 35 | -------------------------------------------------------------------------------- /x11-libs/libdrm/libdrm-2.4.74.ebuild: -------------------------------------------------------------------------------- 1 | # Copyright 1999-2016 Gentoo Foundation 2 | # Distributed under the terms of the GNU General Public License v2 3 | # $Id$ 4 | 5 | EAPI=5 6 | 7 | XORG_MULTILIB=yes 8 | inherit xorg-2 9 | 10 | DESCRIPTION="X.Org libdrm library" 11 | HOMEPAGE="https://dri.freedesktop.org/" 12 | if [[ ${PV} = 9999* ]]; then 13 | EGIT_REPO_URI="git://anongit.freedesktop.org/git/mesa/drm" 14 | else 15 | SRC_URI="https://dri.freedesktop.org/${PN}/${P}.tar.bz2" 16 | fi 17 | 18 | KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~mips ~ppc ~ppc64 ~s390 ~sh ~sparc ~x86 ~amd64-fbsd ~x86-fbsd ~x64-freebsd ~x86-freebsd ~amd64-linux ~arm-linux ~x86-linux" 19 | VIDEO_CARDS="amdgpu exynos freedreno intel nouveau omap radeon tegra vc4 vivante vmware" 20 | for card in ${VIDEO_CARDS}; do 21 | IUSE_VIDEO_CARDS+=" video_cards_${card}" 22 | done 23 | 24 | IUSE="${IUSE_VIDEO_CARDS} libkms valgrind" 25 | RESTRICT="test" # see bug #236845 26 | 27 | RDEPEND=">=dev-libs/libpthread-stubs-0.3-r1:=[${MULTILIB_USEDEP}] 28 | video_cards_intel? ( >=x11-libs/libpciaccess-0.13.1-r1:=[${MULTILIB_USEDEP}] ) 29 | abi_x86_32? ( !app-emulation/emul-linux-x86-opengl[-abi_x86_32(-)] )" 30 | DEPEND="${RDEPEND} 31 | valgrind? ( dev-util/valgrind )" 32 | 33 | src_prepare() { 34 | if [[ ${PV} = 9999* ]]; then 35 | # tests are restricted, no point in building them 36 | sed -ie 's/tests //' "${S}"/Makefile.am 37 | fi 38 | EPATCH_SOURCE="${FILESDIR}/amd-patches" EPATCH_SUFFIX="patch" \ 39 | EPATCH_FORCE="yes" epatch 40 | epatch "${FILESDIR}/libdrm-2.4.74-liverpool.patch" 41 | xorg-2_src_prepare 42 | } 43 | 44 | src_configure() { 45 | XORG_CONFIGURE_OPTIONS=( 46 | # Udev is only used by tests now. 47 | --disable-udev 48 | --disable-cairo-tests 49 | $(use_enable video_cards_amdgpu amdgpu) 50 | $(use_enable video_cards_exynos exynos-experimental-api) 51 | $(use_enable video_cards_freedreno freedreno) 52 | $(use_enable video_cards_intel intel) 53 | $(use_enable video_cards_nouveau nouveau) 54 | $(use_enable video_cards_omap omap-experimental-api) 55 | $(use_enable video_cards_radeon radeon) 56 | $(use_enable video_cards_tegra tegra-experimental-api) 57 | $(use_enable video_cards_vc4 vc4) 58 | $(use_enable video_cards_vivante etnaviv-experimental-api) 59 | $(use_enable video_cards_vmware vmwgfx) 60 | $(use_enable libkms) 61 | # valgrind installs its .pc file to the pkgconfig for the primary arch 62 | --enable-valgrind=$(usex valgrind auto no) 63 | ) 64 | 65 | xorg-2_src_configure 66 | } 67 | -------------------------------------------------------------------------------- /x11-libs/libdrm/metadata.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | x11@gentoo.org 6 | X11 7 | 8 | 9 | Enable building of libkms, a library for applications to interface with KMS 10 | Compile in valgrind memory hints 11 | 12 | 13 | --------------------------------------------------------------------------------