├── modules ├── __init__.py ├── misc.py ├── subsampler.py ├── trigger.py ├── storage.py ├── la.py └── hspi.py ├── hw └── hydrasucrela │ ├── hydrasucrela.kicad_dru │ ├── fp-lib-table │ ├── fabrication-toolkit-options.json │ ├── sym-lib-table │ ├── hydrasucrela.kicad_prl │ ├── hydrasucrela_bom │ ├── hydrasucrela.kicad_sch │ ├── Library.pretty │ └── probe_connector.kicad_mod │ ├── hydrasucrela.kicad_pro │ └── power.kicad_sch ├── .gitmodules ├── Pipfile ├── software ├── boards │ └── hydrausb3 │ │ ├── config.h │ │ ├── usb_cmd.h │ │ ├── hydrausb3_usb_devbulk_vid_pid.h │ │ ├── uartbone_ch569_backend.c │ │ ├── usb_cmd.c │ │ ├── Makefile │ │ └── main.c └── libuartbone │ ├── Makefile │ ├── uartbone.h │ ├── uartbone.c │ ├── linux_cli.c │ └── uartbone_linux.c ├── README.md ├── .github └── workflows │ └── build.yml ├── sucrela.py └── Pipfile.lock /modules/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /hw/hydrasucrela/hydrasucrela.kicad_dru: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /modules/misc.py: -------------------------------------------------------------------------------- 1 | def core_layout(data_width): 2 | return [("data", data_width), ("hit", 1)] 3 | -------------------------------------------------------------------------------- /hw/hydrasucrela/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (version 7) 3 | (lib (name "Library")(type "KiCad")(uri "${KIPRJMOD}/Library.pretty")(options "")(descr "")) 4 | ) 5 | -------------------------------------------------------------------------------- /hw/hydrasucrela/fabrication-toolkit-options.json: -------------------------------------------------------------------------------- 1 | {"EXTRA_LAYERS": "", "ALL_ACTIVE_LAYERS": false, "EXTEND_EDGE_CUT": false, "ALTERNATIVE_EDGE_CUT": false, "AUTO TRANSLATE": true, "AUTO FILL": true, "EXCLUDE DNP": false} -------------------------------------------------------------------------------- /hw/hydrasucrela/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (version 7) 3 | (lib (name "Lattice_ECP5_FPGA")(type "Legacy")(uri "/home/ysionneau/dev/KiCad-Schematic-Symbol-Libraries/Lattice_ECP5_FPGA.lib")(options "")(descr "")) 4 | ) 5 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "wch-ch56x-bsp"] 2 | path = wch-ch56x-bsp 3 | url = git@github.com:fallen/wch-ch56x-bsp.git 4 | [submodule "software/host/libsigrok"] 5 | path = software/host/libsigrok 6 | url = https://github.com/fallen/libsigrok 7 | -------------------------------------------------------------------------------- /Pipfile: -------------------------------------------------------------------------------- 1 | [[source]] 2 | url = "https://pypi.org/simple" 3 | verify_ssl = true 4 | name = "pypi" 5 | 6 | [packages] 7 | litex = {git = "git+https://github.com/enjoy-digital/litex"} 8 | litedram = {git = "git+https://github.com/enjoy-digital/litedram"} 9 | litex-boards = {git = "git+https://github.com/litex-hub/litex-boards"} 10 | litescope = {git = "git+https://github.com/enjoy-digital/litescope"} 11 | crc = "*" 12 | dearpygui = "*" 13 | 14 | [dev-packages] 15 | 16 | [requires] 17 | python_version = "3.10" 18 | -------------------------------------------------------------------------------- /software/boards/hydrausb3/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_H_ 2 | #define _CONFIG_H_ 3 | 4 | /* UARTs settings */ 5 | #define UART1_BAUD 115200 6 | #define UART3_BAUD 115200 7 | 8 | /* HSPI Data width : 8 bits */ 9 | #define HSPI_DATA_WIDTH 0 10 | 11 | #define HSPI_RX_DMA_LENGTH 4096 12 | 13 | extern __attribute__((aligned(16))) volatile uint8_t HSPI_RX_Addr0[HSPI_RX_DMA_LENGTH] __attribute__((section(".DMADATA"))); 14 | extern __attribute__((aligned(16))) volatile uint8_t HSPI_RX_Addr1[HSPI_RX_DMA_LENGTH] __attribute__((section(".DMADATA"))); 15 | 16 | #endif -------------------------------------------------------------------------------- /software/boards/hydrausb3/usb_cmd.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : usb_cmd.h 3 | * Author : bvernoux 4 | * Version : V1.0 5 | * Date : 2022/08/20 6 | * Description : 7 | * Copyright (c) 2022 Benjamin VERNOUX 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #ifndef USB_CMD_H_ 11 | #define USB_CMD_H_ 12 | 13 | #ifdef __cplusplus 14 | extern "C" { 15 | #endif 16 | 17 | #include "CH56x_usb_devbulk_desc_cmd.h" 18 | 19 | #ifdef __cplusplus 20 | } 21 | #endif 22 | 23 | #endif /* USB_CMD_H_ */ 24 | -------------------------------------------------------------------------------- /software/libuartbone/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS=-fPIC 2 | 3 | all: uartbone_cli libuartbone.so 4 | 5 | uartbone_cli: LDLIBS=$(shell pkg-config --libs libusb-1.0) 6 | uartbone_cli: linux_cli.o uartbone.o uartbone_linux.o 7 | $(CC) -o $@ $^ $(LDFLAGS) $(LDLIBS) 8 | 9 | linux_cli.o: linux_cli.c 10 | 11 | uartbone.o: uartbone.c 12 | 13 | uartbone_linux.o: CFLAGS+=$(shell pkg-config --cflags libusb-1.0) 14 | uartbone_linux.o: uartbone_linux.c 15 | 16 | libuartbone.so: LDLIBS=$(shell pkg-config --libs libusb-1.0) 17 | libuartbone.so: LDFLAGS=-shared -fPIC 18 | libuartbone.so: uartbone.o uartbone_linux.o 19 | $(CC) -o $@ $^ $(LDFLAGS) $(LDLIBS) 20 | 21 | clean: 22 | rm -f linux_cli.o uartbone.o uartbone_linux.o uartbone_cli libuartbone.so 23 | 24 | .PHONY: clean all 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SucréLA (READ ONLY, MOVED TO GITLAB) 2 | 3 | This is an archived, out-of-date and read-only copy of the SucréLA project. 4 | 5 | The project is now hosted on **GitLab** => [https://gitlab.com/yannsionneau/SucreLA](https://gitlab.com/yannsionneau/SucreLA) 6 | 7 | ## Building 8 | 9 | The project Python's dependencies are handled using Pipenv. 10 | However, you must install [nextpnr-ecp5](https://github.com/YosysHQ/nextpnr) and [Yosys](https://github.com/YosysHQ/yosys) if you wish to build the 11 | projet from source. 12 | 13 | ``` 14 | pipenv install --ignore-pipfile 15 | pipenv run python3 ./sucrela.py --build 16 | ``` 17 | 18 | ## Flashing the OrangeCrab 19 | 20 | ``` 21 | pipenv run python3 ./sucrela.py --load 22 | ``` 23 | 24 | ## Runing simulation 25 | 26 | ``` 27 | pipenv run python3 ./sucrela.py --sim 28 | ``` 29 | -------------------------------------------------------------------------------- /modules/subsampler.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.genlib.cdc import MultiReg 3 | from litex.soc.interconnect.csr import AutoCSR, CSRStorage 4 | from litex.soc.interconnect import stream 5 | 6 | from modules.misc import core_layout 7 | 8 | 9 | class SubSampler(Module, AutoCSR): 10 | def __init__(self, data_width): 11 | self.sink = sink = stream.Endpoint(core_layout(data_width)) 12 | self.source = source = stream.Endpoint(core_layout(data_width)) 13 | 14 | self.value = CSRStorage(16) 15 | 16 | # # # 17 | 18 | value = Signal(16) 19 | self.specials += MultiReg(self.value.storage, value, "scope") 20 | 21 | counter = Signal(16) 22 | done = Signal() 23 | self.sync.scope += \ 24 | If(source.ready, 25 | If(done, 26 | counter.eq(0) 27 | ).Elif(sink.valid, 28 | counter.eq(counter + 1) 29 | ) 30 | ) 31 | 32 | self.comb += [ 33 | done.eq(counter == value), 34 | sink.connect(source, omit={"valid"}), 35 | source.valid.eq(sink.valid & done) 36 | ] 37 | -------------------------------------------------------------------------------- /software/boards/hydrausb3/hydrausb3_usb_devbulk_vid_pid.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : hydrausb3_usb_devbulk_vid_pid.h 3 | * Author : bvernoux 4 | * Version : V1.0 5 | * Date : 2022/08/20 6 | * Description : 7 | * Copyright (c) 2022 Benjamin VERNOUX 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | /* 11 | Use default USB PID/VID if not configured with usb_descriptor_set_usb_vid_pid() 12 | https://github.com/obdev/v-usb/blob/master/usbdrv/USB-IDs-for-free.txt 13 | PID dec (hex) | VID dec (hex) | Description of use 14 | ==============+===============+============================================ 15 | 1500 (0x05dc) | 5824 (0x16c0) | For Vendor Class devices with libusb 16 | */ 17 | // Default USB Vendor ID 18 | // Default VID 0x16C0 "Van Ooijen Technische Informatica" 19 | #define USB_VID_BYTE_MSB (0x16) 20 | #define USB_VID_BYTE_LSB (0xC0) 21 | #define USB_VID ((USB_VID_BYTE_MSB << 8) | USB_VID_BYTE_LSB) 22 | // Default USB Product ID 23 | // Default PID 0x05DC 24 | #define USB_PID_BYTE_MSB (0x05) 25 | #define USB_PID_BYTE_LSB (0xDC) 26 | #define USB_PID ((USB_PID_BYTE_MSB << 8) | USB_PID_BYTE_LSB) 27 | -------------------------------------------------------------------------------- /software/libuartbone/uartbone.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | /* 6 | * There can exist only 16 OUT endpoints and 16 IN endpoints 7 | * Bit 7 indicates IN vs OUT (1 = IN) 8 | * bits 0..3 indicate endpoint number 9 | * bits 4..6 should be 0, therefor -1 can be used to signify 10 | * "no endpoint" 11 | */ 12 | #define UARTBONE_NO_ENDPOINT (-1) 13 | 14 | enum uart_backend_type { 15 | UNIX_UART, 16 | CH569_UART, 17 | UNIX_USB 18 | }; 19 | 20 | struct uartbone_ctx; 21 | 22 | struct uart_backend { 23 | enum uart_backend_type type; 24 | int (*read)(struct uartbone_ctx *ctx, uint8_t *data, size_t len); 25 | void (*write)(struct uartbone_ctx *ctx, uint8_t *data, size_t len); 26 | void (*flush)(void); 27 | }; 28 | 29 | struct uartbone_ctx { 30 | unsigned int addr_width; 31 | unsigned int baudrate; 32 | int fd; 33 | struct uart_backend *uart; 34 | bool open; 35 | int error; 36 | uint16_t vendor_id; 37 | uint16_t product_id; 38 | unsigned char endpoint; 39 | void *usb_handle; 40 | }; 41 | 42 | int get_reg_addr(FILE *csv, char *reg_name, uint32_t *res); 43 | uint32_t uartbone_read(struct uartbone_ctx *ctx, uint64_t addr); 44 | void uartbone_unix_init(struct uartbone_ctx *ctx, char *file, unsigned int baudrate, unsigned int addr_width); 45 | void uartbone_write(struct uartbone_ctx *ctx, uint64_t addr, uint32_t val); 46 | 47 | static inline bool ctx_uses_usb(struct uartbone_ctx *ctx) { 48 | return ctx && ctx->uart && ctx->uart->type == UNIX_USB; 49 | } -------------------------------------------------------------------------------- /software/boards/hydrausb3/uartbone_ch569_backend.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "uartbone.h" 5 | #include "CH56x_uart.h" 6 | 7 | static void ch56x_uart_write(struct uartbone_ctx *ctx, uint8_t *data, size_t len) { 8 | switch (ctx->fd) { 9 | case 0: { 10 | UART0_SendString(data, len); 11 | break; 12 | } 13 | case 1: { 14 | UART1_SendString(data, len); 15 | break; 16 | } 17 | case 2: { 18 | UART2_SendString(data, len); 19 | break; 20 | } 21 | case 3: { 22 | UART3_SendString(data, len); 23 | break; 24 | } 25 | default: { 26 | printf("Only valid UARTs are 0/1/2/3\n\r"); 27 | abort(); 28 | } 29 | } 30 | } 31 | 32 | static int ch56x_uart_read(struct uartbone_ctx *ctx, uint8_t *data, size_t len) { 33 | switch (ctx->fd) { 34 | case 0: { 35 | UART0_Recv(data, len); 36 | break; 37 | } 38 | case 1: { 39 | UART1_Recv(data, len); 40 | break; 41 | } 42 | case 2: { 43 | UART2_Recv(data, len); 44 | break; 45 | } 46 | case 3: { 47 | UART3_Recv(data, len); 48 | break; 49 | } 50 | default: { 51 | printf("Only valid UARTs are 0/1/2/3\n\r"); 52 | abort(); 53 | } 54 | } 55 | return 0; 56 | } 57 | 58 | struct uart_backend ch56x_uart_backend = { 59 | .type = CH569_UART, 60 | .read = ch56x_uart_read, 61 | .write = ch56x_uart_write 62 | }; 63 | 64 | void uartbone_ch56x_init(struct uartbone_ctx *ctx, int uart_num, int baudrate, int addr_width) { 65 | ctx->addr_width = addr_width; 66 | ctx->baudrate = baudrate; 67 | ctx->fd = uart_num; 68 | ctx->open = true; 69 | ctx->error = 0; 70 | ctx->uart = &ch56x_uart_backend; 71 | } 72 | -------------------------------------------------------------------------------- /hw/hydrasucrela/hydrasucrela.kicad_prl: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "active_layer": 0, 4 | "active_layer_preset": "", 5 | "auto_track_width": false, 6 | "hidden_netclasses": [], 7 | "hidden_nets": [], 8 | "high_contrast_mode": 1, 9 | "net_color_mode": 2, 10 | "opacity": { 11 | "images": 0.6, 12 | "pads": 1.0, 13 | "tracks": 1.0, 14 | "vias": 1.0, 15 | "zones": 0.6 16 | }, 17 | "selection_filter": { 18 | "dimensions": true, 19 | "footprints": true, 20 | "graphics": true, 21 | "keepouts": true, 22 | "lockedItems": false, 23 | "otherItems": true, 24 | "pads": true, 25 | "text": true, 26 | "tracks": true, 27 | "vias": true, 28 | "zones": true 29 | }, 30 | "visible_items": [ 31 | 0, 32 | 1, 33 | 2, 34 | 3, 35 | 4, 36 | 5, 37 | 8, 38 | 9, 39 | 10, 40 | 12, 41 | 13, 42 | 15, 43 | 16, 44 | 17, 45 | 18, 46 | 19, 47 | 20, 48 | 21, 49 | 22, 50 | 23, 51 | 24, 52 | 25, 53 | 26, 54 | 27, 55 | 28, 56 | 29, 57 | 30, 58 | 32, 59 | 33, 60 | 34, 61 | 35, 62 | 36, 63 | 39, 64 | 40 65 | ], 66 | "visible_layers": "0001280_80000001", 67 | "zone_display_mode": 0 68 | }, 69 | "git": { 70 | "repo_password": "", 71 | "repo_type": "", 72 | "repo_username": "", 73 | "ssh_key": "" 74 | }, 75 | "meta": { 76 | "filename": "hydrasucrela.kicad_prl", 77 | "version": 3 78 | }, 79 | "project": { 80 | "files": [] 81 | } 82 | } 83 | -------------------------------------------------------------------------------- /hw/hydrasucrela/hydrasucrela_bom: -------------------------------------------------------------------------------- 1 | "Reference","Value","Datasheet","Footprint","Qty","DNP" 2 | "C1,C3,C4","10uF","~","Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder","3","" 3 | "C2","10pF","~","Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder","1","" 4 | "C5","4.7uF","~","Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder","1","" 5 | "C6","0.01uF","~","Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder","1","" 6 | "J1","Yxcon P125-1220A0BS116A1","https://www.lcsc.com/datasheet/lcsc_datasheet_2403231322_Yxcon-P125-1220A0BS116A1_C19190512.pdf","Connector_PinHeader_2.54mm:PinHeader_2x20_P2.54mm_Vertical","1","" 7 | "J2","Megastar ZX-PZ2.54-2-5PZZ","https://www.lcsc.com/datasheet/lcsc_datasheet_2311221544_Megastar-ZX-PZ2-54-2-5PZZ_C7501276.pdf","Connector_PinHeader_2.54mm:PinHeader_2x05_P2.54mm_Vertical","1","" 8 | "J3","Conn_02x05_Odd_Even","~","Connector_Harwin:Harwin_M20-7810545_2x05_P2.54mm_Vertical","1","" 9 | "J4","Conn_01x05","~","Connector_PinSocket_2.54mm:PinSocket_1x05_P2.54mm_Vertical","1","" 10 | "J5","Conn_02x20_Top_Bottom","~","Library:probe_connector","1","" 11 | "L1","2.2uH","~","Inductor_SMD:L_0603_1608Metric_Pad1.05x0.95mm_HandSolder","1","" 12 | "Q1","MMBTA06","https://diotec.com/request/datasheet/mmbta06.pdf","Package_TO_SOT_SMD:SOT-23","1","" 13 | "R1","10k","~","Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder","1","" 14 | "R2","100k","~","Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder","1","" 15 | "R3","120k","~","Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder","1","" 16 | "R4,R5,R6","4.7k","~","Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder","3","" 17 | "U1","ECP5U_25_CABGA381","","Package_BGA:Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD","1","" 18 | "U3","TLV62569DRL","http://www.ti.com/lit/ds/symlink/tlv62569.pdf","Package_TO_SOT_SMD:SOT-563","1","" 19 | "U4","NCP115CMX250TCG","https://www.onsemi.com/pub/Collateral/NCP115-D.PDF","Package_DFN_QFN:OnSemi_XDFN4-1EP_1.0x1.0mm_EP0.52x0.52mm","1","" 20 | "U5","XUY73","https://www.renesas.com/us/en/document/dst/xu-family-low-phase-noise-quartz-based-pll-oscillators-datasheet","Oscillator:Oscillator_SMD_IDT_JU6-6_7.0x5.0mm_P2.54mm","1","" 21 | "U6","MCP23S08-E/SO","http://ww1.microchip.com/downloads/en/DeviceDoc/MCP23008-MCP23S08-Data-Sheet-20001919F.pdf","Package_SO:SOIC-18W_7.5x11.6mm_P1.27mm","1","" 22 | -------------------------------------------------------------------------------- /modules/trigger.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.genlib.cdc import MultiReg 3 | from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStorage, CSRStatus 4 | from litex.soc.interconnect import stream 5 | from litex.gen.genlib.misc import WaitTimer 6 | 7 | from modules.misc import core_layout 8 | 9 | 10 | class Trigger(Module, AutoCSR): 11 | def __init__(self, data_width, depth=16): 12 | self.sink = sink = stream.Endpoint(core_layout(data_width)) 13 | self.source = source = stream.Endpoint(core_layout(data_width)) 14 | 15 | self.enable = CSRStorage() 16 | self.done = CSRStatus() 17 | 18 | self.mem_write = CSR() 19 | self.mem_mask = CSRStorage(data_width) 20 | self.mem_value = CSRStorage(data_width) 21 | self.mem_full = CSRStatus() 22 | 23 | # # # 24 | 25 | # Control re-synchronization 26 | enable = Signal() 27 | enable_d = Signal() 28 | self.specials += MultiReg(self.enable.storage, enable, "scope") 29 | self.sync.scope += enable_d.eq(enable) 30 | 31 | # Status re-synchronization 32 | done = Signal() 33 | self.specials += MultiReg(done, self.done.status) 34 | 35 | # Memory and configuration 36 | mem = stream.AsyncFIFO([("mask", data_width), ("value", data_width)], depth) 37 | mem = ClockDomainsRenamer({"write": "sys", "read": "scope"})(mem) 38 | self.submodules += mem 39 | self.comb += [ 40 | mem.sink.valid.eq(self.mem_write.re), 41 | mem.sink.mask.eq(self.mem_mask.storage), 42 | mem.sink.value.eq(self.mem_value.storage), 43 | self.mem_full.status.eq(~mem.sink.ready) 44 | ] 45 | 46 | # Hit and memory read/flush 47 | hit = Signal() 48 | flush = WaitTimer(2*depth) 49 | flush = ClockDomainsRenamer("scope")(flush) 50 | self.submodules += flush 51 | self.comb += [ 52 | flush.wait.eq(~(~enable & enable_d)), # flush when disabling 53 | hit.eq((sink.data & mem.source.mask) == (mem.source.value & mem.source.mask)), 54 | mem.source.ready.eq((enable & hit) | ~flush.done), 55 | ] 56 | 57 | # Output 58 | self.comb += [ 59 | sink.connect(source), 60 | # Done when all triggers have been consumed 61 | done.eq(~mem.source.valid), 62 | source.hit.eq(done) 63 | ] 64 | -------------------------------------------------------------------------------- /.github/workflows/build.yml: -------------------------------------------------------------------------------- 1 | name: CI 2 | run-name: Continuous Integration 3 | on: [push] 4 | jobs: 5 | CI: 6 | name: Continuous Integration 7 | runs-on: ubuntu-latest 8 | 9 | steps: 10 | - uses: actions/checkout@v4 11 | with: 12 | submodules: recursive 13 | - name: Fetch nextpnr-ecp5 and Yosys 14 | run: wget https://github.com/fallen/yosys_nextpnr_tools_for_ci/raw/main/tools.tar.gz 15 | - name: Install nextpnr-ecp5 and Yosys 16 | run: | 17 | echo "PATH=/opt/bin:$PATH" >> "$GITHUB_ENV" 18 | echo "LD_LIBRARY_PATH=/opt/lib:$LD_LIBRARY_PATH" >> "$GITHUB_ENV" 19 | sudo tar -C / -xzf $PWD/tools.tar.gz 20 | sudo apt-get -y install libboost-system1.74.0 libboost-python1.74.0 libboost-filesystem1.74.0 libboost-program-options1.74.0 libboost-thread1.74.0 libreadline8 libtcl8.6 libffi8 libexpat1 21 | - name: Install Python requirements 22 | run: | 23 | sudo apt-get -y install python3-pip 24 | sudo -H pip3 install --upgrade pip 25 | pip install pipenv 26 | pipenv install --ignore-pipfile 27 | - name: Build the FPGA bitstream 28 | run: | 29 | nextpnr-ecp5 --version 30 | yosys --version 31 | pipenv run python3 ./sucrela.py --build 32 | - name: Build the software 33 | run: | 34 | sudo apt-get -y install libusb-1.0-0-dev libusb-1.0-0 35 | cd software/libuartbone 36 | make 37 | ./uartbone_cli -h 38 | - name: Run Simulation tests 39 | run: | 40 | pipenv run python3 ./sucrela.py --sim 41 | - name: Fetch xpack RISC-V toolchain 42 | run: wget https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz 43 | - name: Unpack xpack RISC-V toolchain 44 | run: | 45 | sudo mkdir -p /opt 46 | sudo tar -C /opt -xzf $PWD/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz 47 | - name: Build SucreLA HydraUSB3 RISC-V firmware 48 | run: PATH=/opt/xpack-riscv-none-elf-gcc-13.2.0-2/bin:$PATH make -C software/boards/hydrausb3/ 49 | - name: Build libsigrok with SucréLA support 50 | run: | 51 | sudo apt-get -y install git-core gcc g++ make autoconf autoconf-archive \ 52 | automake libtool pkg-config libglib2.0-dev libglibmm-2.4-dev libzip-dev \ 53 | libusb-1.0-0-dev check doxygen 54 | cd software/host/libsigrok 55 | ./autogen.sh 56 | ./configure --enable-all-drivers=no --enable-sucrela 57 | make -j5 58 | sudo make install 59 | -------------------------------------------------------------------------------- /software/boards/hydrausb3/usb_cmd.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : usb_cmd.c 3 | * Author : bvernoux 4 | * Version : V1.0 5 | * Date : 2022/08/20 6 | * Description : 7 | * Copyright (c) 2022 Benjamin VERNOUX 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #include "CH56x_common.h" 11 | #include "CH56x_usb20_devbulk.h" 12 | #include "CH56x_usb30_devbulk.h" 13 | #include "CH56x_usb30_devbulk_LIB.h" 14 | 15 | #include "CH56x_debug_log.h" 16 | #include "usb_cmd.h" 17 | 18 | 19 | /******************************************************************************* 20 | * @fn usb_cmd_rx 21 | * 22 | * @brief Callback called by USB2 & USB3 endpoint 1 23 | * - For USB3 this usb_cmd_rx() is called from IRQ(USBHS_IRQHandler) 24 | * with rx_usb_dma_buff containing 4096 bytes (DEF_ENDP1_MAX_SIZE) 25 | * - For USB2 this usb_cmd_rx() is called from IRQ USB30_IRQHandler->EP1_OUT_Callback) 26 | * with rx_usb_dma_buff containing 4096 bytes (DEF_ENDP1_MAX_SIZE) 27 | * 28 | * @param usb_type: USB Type (USB2 HS or USB3 SS) 29 | * @param rx_usb_dma_buff: USB RX DMA buffer containing 4096 bytes of data 30 | * Data received from USB 31 | * @param tx_usb_dma_buff: USB TX DMA buffer containing 4096 bytes of data 32 | * Data to be transmitted over USB 33 | * 34 | * @return size of data to be sent to USB host 35 | */ 36 | 37 | 38 | #define RISCV_FENCE(p, s) \ 39 | __asm__ __volatile__ ("fence " #p "," #s : : : "memory") 40 | 41 | /* These barriers need to enforce ordering on both devices or memory. */ 42 | #define mb() RISCV_FENCE(iorw,iorw) 43 | #define rmb() RISCV_FENCE(ir,ir) 44 | #define wmb() RISCV_FENCE(ow,ow) 45 | 46 | extern volatile int usb_cmd_rxed; 47 | extern volatile uint8_t usb_cmd[11]; 48 | extern volatile uint8_t usb_cmd_len; 49 | extern volatile int ep1_out_nack; 50 | 51 | // return 1 for busy, 0 for OK 52 | int usb_cmd_rx(e_usb_type usb_type, uint8_t* rx_usb_dma_buff, uint8_t* tx_usb_dma_buff) 53 | { 54 | if (usb_cmd_rxed) { // already processing... 55 | ep1_out_nack++; 56 | return 1; 57 | } 58 | switch (rx_usb_dma_buff[0]) { 59 | case 'U': { 60 | if (rx_usb_dma_buff[1] == 'w') { 61 | usb_cmd_len = rx_usb_dma_buff[2]; 62 | memcpy(usb_cmd, &rx_usb_dma_buff[1], usb_cmd_len + 2); 63 | mb(); 64 | usb_cmd_rxed = 1; 65 | } 66 | if (rx_usb_dma_buff[1] == 'r') { 67 | usb_cmd_len = rx_usb_dma_buff[2]; 68 | usb_cmd[0] = 'r'; 69 | mb(); 70 | usb_cmd_rxed = 1; 71 | } 72 | if (rx_usb_dma_buff[1] != 'r' && rx_usb_dma_buff[1] != 'w') 73 | printf("Big PROTO error!\n"); 74 | break; 75 | } 76 | default: { 77 | printf("Big error!\n"); 78 | } 79 | } 80 | return 0; 81 | } 82 | -------------------------------------------------------------------------------- /software/libuartbone/uartbone.c: -------------------------------------------------------------------------------- 1 | #include // write(), read(), close() 2 | #include 3 | #include 4 | 5 | #if defined(__linux__) 6 | # include 7 | #elif defined(__FreeBSD__) || defined(__NetBSD__) 8 | # include 9 | #elif defined(__OpenBSD__) 10 | # include 11 | # define be16toh(x) betoh16(x) 12 | # define be32toh(x) betoh32(x) 13 | # define be64toh(x) betoh64(x) 14 | #elif defined(__riscv) // workaround for xpack newlib nano based toolchain 15 | #include 16 | #include 17 | #define htobe16(_x) __htons(_x) 18 | #define htobe32(_x) __htonl(_x) 19 | #define htobe64(_x) ({ printf("unsupported 64 bit endianness conversion\n"); abort(); 0; }) 20 | #define be32toh(_x) __ntohl(_x) 21 | #endif 22 | 23 | #include "uartbone.h" 24 | 25 | #define MAX_CMD_LENGTH 10 // max for 64 bit addresses + cmd code + burst length 26 | #define CMD_WRITE_BURST_INCR 1 27 | #define CMD_READ_BURST_INCR 2 28 | #define CMD_WRITE_BURST_FIXED 3 29 | #define CMD_READ_BURST_FIXED 4 30 | 31 | union wb_val_32 { 32 | uint32_t val; 33 | uint8_t buff[4]; 34 | }; 35 | 36 | union wb_val_64 { 37 | uint64_t val; 38 | uint8_t buff[8]; 39 | }; 40 | 41 | void uart_send(struct uartbone_ctx *ctx, uint8_t *buffer, size_t length) { 42 | ctx->uart->write(ctx, buffer, length); 43 | } 44 | 45 | void uart_recv(struct uartbone_ctx *ctx, uint8_t *buffer, size_t length) { 46 | ctx->uart->read(ctx, buffer, length); 47 | } 48 | 49 | void uartbone_flush(struct uartbone_ctx *ctx) { 50 | //ctx->uart->flush(); 51 | } 52 | 53 | uint64_t to_bigendian(struct uartbone_ctx *ctx, uint64_t val) { 54 | uint64_t newval; 55 | 56 | switch(ctx->addr_width) { 57 | case 1: 58 | newval = val; 59 | break; 60 | 61 | case 2: 62 | newval = htobe16(val); 63 | break; 64 | 65 | case 4: 66 | newval = htobe32(val); 67 | break; 68 | 69 | case 8: 70 | newval = htobe64(val); 71 | } 72 | 73 | return newval; 74 | } 75 | 76 | uint32_t uartbone_read(struct uartbone_ctx *ctx, uint64_t addr) { 77 | size_t cmd_length = ctx->addr_width + 2; 78 | unsigned char buffer[MAX_CMD_LENGTH]; 79 | union wb_val_32 wbval; 80 | union wb_val_64 wbaddr; 81 | 82 | buffer[0] = CMD_READ_BURST_FIXED; 83 | buffer[1] = 1; 84 | 85 | uartbone_flush(ctx); 86 | wbaddr.val = to_bigendian(ctx, addr >> 2); 87 | memcpy(&buffer[2], wbaddr.buff, ctx->addr_width); 88 | uart_send(ctx, buffer, cmd_length); 89 | uart_recv(ctx, wbval.buff, 4); 90 | wbval.val = be32toh(wbval.val); 91 | 92 | return wbval.val; 93 | } 94 | 95 | void uartbone_write(struct uartbone_ctx *ctx, uint64_t addr, uint32_t val) { 96 | size_t cmd_length = ctx->addr_width + 2; 97 | unsigned char buffer[MAX_CMD_LENGTH]; 98 | union wb_val_32 wbval; 99 | union wb_val_64 wbaddr; 100 | 101 | buffer[0] = CMD_WRITE_BURST_FIXED; 102 | buffer[1] = 1; 103 | 104 | uartbone_flush(ctx); 105 | wbval.val = to_bigendian(ctx, val);; 106 | wbaddr.val = to_bigendian(ctx, addr >> 2); // address must be shifted by 2 bits 107 | memcpy(&buffer[2], wbaddr.buff, ctx->addr_width); 108 | uart_send(ctx, buffer, cmd_length); 109 | uart_send(ctx, wbval.buff, 4); 110 | } 111 | -------------------------------------------------------------------------------- /modules/storage.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.genlib.cdc import MultiReg 3 | from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus 4 | from litex.soc.interconnect import stream 5 | from litex.gen.genlib.misc import WaitTimer 6 | 7 | from modules.misc import core_layout 8 | 9 | 10 | class Storage(Module, AutoCSR): 11 | def __init__(self, data_width, depth): 12 | self.sink = sink = stream.Endpoint(core_layout(data_width)) 13 | self.source = source = stream.Endpoint([("data", data_width)]) 14 | 15 | self.enable = CSRStorage() 16 | self.done = CSRStatus() 17 | self.fsm_state_r = CSRStatus() 18 | 19 | self.length = CSRStorage(bits_for(depth)) 20 | self.offset = CSRStorage(bits_for(depth)) 21 | 22 | read_width = min(32, data_width) 23 | self.mem_level = CSRStatus(bits_for(depth)) 24 | self.mem_data = CSRStatus(read_width) 25 | 26 | # # # 27 | 28 | # Control re-synchronization 29 | enable = Signal() 30 | enable_d = Signal() 31 | self.specials += MultiReg(self.enable.storage, enable, "scope") 32 | self.sync.scope += enable_d.eq(enable) 33 | 34 | length = Signal().like(self.length.storage) 35 | offset = Signal().like(self.offset.storage) 36 | self.specials += MultiReg(self.length.storage, length, "scope") 37 | self.specials += MultiReg(self.offset.storage, offset, "scope") 38 | 39 | # Status re-synchronization 40 | done = Signal() 41 | level = Signal().like(self.mem_level.status) 42 | self.specials += MultiReg(done, self.done.status) 43 | self.specials += MultiReg(level, self.mem_level.status) 44 | 45 | # Memory 46 | mem = stream.SyncFIFO([("data", data_width)], depth, buffered=True) 47 | mem = ClockDomainsRenamer("scope")(mem) 48 | self.submodules += mem 49 | 50 | self.comb += level.eq(mem.level) 51 | 52 | # Flush 53 | mem_flush = WaitTimer(depth) 54 | self.mem_flush = mem_flush = ClockDomainsRenamer("scope")(mem_flush) 55 | self.submodules += mem_flush 56 | 57 | self.fsm_state = Signal(max=3) 58 | self.specials += MultiReg(self.fsm_state, self.fsm_state_r.status) 59 | 60 | # FSM 61 | fsm = FSM(reset_state="IDLE") 62 | self.fsm = fsm = ClockDomainsRenamer("scope")(fsm) 63 | self.submodules += fsm 64 | fsm.act("IDLE", 65 | self.fsm_state.eq(0), 66 | done.eq(1), 67 | If(enable & ~enable_d, 68 | NextState("FLUSH") 69 | ), 70 | sink.ready.eq(1), 71 | ) 72 | fsm.act("FLUSH", 73 | self.fsm_state.eq(1), 74 | sink.ready.eq(1), 75 | mem_flush.wait.eq(1), 76 | mem.source.ready.eq(1), 77 | If(mem_flush.done, 78 | NextState("WAIT") 79 | ) 80 | ) 81 | fsm.act("WAIT", 82 | self.fsm_state.eq(2), 83 | sink.connect(mem.sink, omit={"hit"}), 84 | If(sink.valid & sink.hit, 85 | NextState("RUN") 86 | ), 87 | mem.source.ready.eq(mem.level >= offset) 88 | ) 89 | fsm.act("RUN", 90 | self.fsm_state.eq(3), 91 | sink.connect(mem.sink, omit={"hit"}), 92 | If((mem.level >= length) | (~enable & enable_d), 93 | NextState("IDLE"), 94 | ) 95 | ) 96 | 97 | self.comb += [ 98 | mem.source.connect(source) 99 | ] 100 | -------------------------------------------------------------------------------- /hw/hydrasucrela/hydrasucrela.kicad_sch: -------------------------------------------------------------------------------- 1 | (kicad_sch 2 | (version 20231120) 3 | (generator "eeschema") 4 | (generator_version "8.0") 5 | (uuid "7dca55fc-548f-4319-89ea-8fc153556669") 6 | (paper "A4") 7 | (title_block 8 | (title "HydraSucréLA") 9 | ) 10 | (lib_symbols) 11 | (sheet 12 | (at 109.22 59.69) 13 | (size 34.29 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| (color 0 0 0 0.0000) 173 | ) 174 | (uuid "dfe3b8f8-0591-4675-8a5e-9c3bb6092797") 175 | (property "Sheetname" "IO" 176 | (at 151.13 58.9784 0) 177 | (effects 178 | (font 179 | (size 1.27 1.27) 180 | ) 181 | (justify left bottom) 182 | ) 183 | ) 184 | (property "Sheetfile" "IO.kicad_sch" 185 | (at 151.13 76.7846 0) 186 | (effects 187 | (font 188 | (size 1.27 1.27) 189 | ) 190 | (justify left top) 191 | ) 192 | ) 193 | (instances 194 | (project "hydrasucrela" 195 | (path "/7dca55fc-548f-4319-89ea-8fc153556669" 196 | (page "6") 197 | ) 198 | ) 199 | ) 200 | ) 201 | (sheet_instances 202 | (path "/" 203 | (page "1") 204 | ) 205 | ) 206 | ) 207 | -------------------------------------------------------------------------------- /sucrela.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from migen import * 4 | 5 | from litex_boards.platforms.gsd_orangecrab import Platform, feather_serial 6 | from litex_boards.targets.gsd_orangecrab import BaseSoC 7 | from litex.build.generic_platform import * 8 | from litex.soc.integration.builder import * 9 | 10 | from litescope import LiteScopeAnalyzer 11 | 12 | from modules.la import LA, LATest 13 | 14 | feather_gpio = [ 15 | ("gpios", 0, Pins("GPIO:2 GPIO:3 GPIO:5 GPIO:6"), IOStandard("LVCMOS33") # C10 C9 B10 B9 aka SDA SCL 5 6 16 | ) 17 | ] 18 | 19 | feather_hspi = [ 20 | ("hspi", 0, 21 | Subsignal("clk", Pins("GPIO:9"), IOStandard("LVCMOS33")), # C8 aka 9 22 | Subsignal("req", Pins("GPIO:10"), IOStandard("LVCMOS33")), # B8 aka 10 23 | Subsignal("ready", Pins("GPIO:11"), IOStandard("LVCMOS33")), # A8 aka 11 24 | Subsignal("valid", Pins("GPIO:12"), IOStandard("LVCMOS33")), # H2 aka 12 25 | Subsignal("hd", Pins("GPIO:13 GPIO:14 GPIO:15 GPIO:16 GPIO:18 GPIO:19 GPIO:20 GPIO:21"), 26 | IOStandard("LVCMOS33")), # J2 N15 R17 N16 L4 N3 N4 H4 aka 13 MISO SCK MOSI A0 A1 A2 A3 27 | Subsignal("hract", Pins("GPIO:22"), IOStandard("LVCMOS33")), # G4 aka A4 28 | Subsignal("htack", Pins("GPIO:23"), IOStandard("LVCMOS33")), # T17 aka A5 29 | ) 30 | ] 31 | 32 | 33 | class LASoC(BaseSoC): 34 | def __init__(self, sys_clk_freq=48e6, **kwargs): 35 | BaseSoC.__init__(self, sys_clk_freq=sys_clk_freq, 36 | with_led_chaser=True, **kwargs) 37 | 38 | self.cd_hspi = ClockDomain() 39 | self.platform.add_extension(feather_serial) 40 | self.platform.add_extension(feather_gpio) 41 | self.platform.add_extension(feather_hspi) 42 | self.add_uartbone() 43 | ios = self.platform.request("gpios") 44 | hspi_pads = self.platform.request("hspi") 45 | self.crg.pll.create_clkout(self.cd_hspi, 4e6) # create 4 MHz clock for HSPI 46 | 47 | self.submodules.la = LA(ios, hspi_pads, depth=4096, clock_domain="hspi", samplerate=4e6, 48 | testing=kwargs['testing']) 49 | 50 | if kwargs['testing']: 51 | analyzer_signals = [hspi_pads.req, hspi_pads.ready, hspi_pads.valid, hspi_pads.hract, hspi_pads.htack, 52 | self.la.hspi_tx.hd.o, self.la.hspi_tx.hd.oe, self.cd_hspi.clk, 53 | self.la.hspi_tx.remaining_packets] 54 | self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 55 | depth=0x10000, 56 | clock_domain="sys", 57 | samplerate=sys_clk_freq, 58 | csr_csv="analyzer.csv", 59 | trigger_depth=64 60 | ) 61 | 62 | 63 | def main(): 64 | from litex.build.parser import LiteXArgumentParser 65 | parser = LiteXArgumentParser(platform=Platform, description="SucreLA on OrangeCrab.") 66 | parser.add_target_argument("--sys-clk-freq", default=48e6, type=float, help="System clock frequency.") 67 | parser.add_target_argument("--revision", default="0.2", help="Board Revision (0.1 or 0.2).") 68 | parser.add_target_argument("--device", default="85F", help="ECP5 device (25F, 45F or 85F).") 69 | parser.add_target_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).") 70 | parser.add_target_argument("--sim", action="store_true", help="run LA simulation testsuite") 71 | parser.add_target_argument("--testing", action="store_true", help="run LA with testing sample data") 72 | parser.set_defaults(no_uart=True, cpu_type="None") 73 | args = parser.parse_args() 74 | 75 | if args.sim: 76 | LATest(stop_via="hspi") 77 | LATest(stop_via="storage") 78 | LATest() 79 | exit(0) 80 | 81 | soc = LASoC(sys_clk_freq=args.sys_clk_freq, 82 | revision=args.revision, 83 | device=args.device, 84 | sdram_device=args.sdram_device, 85 | testing=args.testing, 86 | **parser.soc_argdict) 87 | 88 | builder = Builder(soc, **parser.builder_argdict) 89 | if args.build: 90 | builder.build(**parser.toolchain_argdict) 91 | 92 | if args.load: 93 | prog = soc.platform.create_programmer() 94 | prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) 95 | 96 | 97 | if __name__ == "__main__": 98 | main() 99 | -------------------------------------------------------------------------------- /software/libuartbone/linux_cli.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include "uartbone.h" 7 | 8 | void print_usage(char *prog_name) { 9 | printf("usage: %s [-u uart_port] [-V] [-b baudrate] [-r addr|reg_name] [-w addr|reg_name -v value] [-i] [-a addr_width]\n", prog_name); 10 | } 11 | 12 | int main(int argc, char **argv) { 13 | struct uartbone_ctx ctx; 14 | char ident_str[256]; 15 | char c; 16 | int i = 0; 17 | int opt; 18 | bool do_read = false; 19 | bool do_write = false; 20 | bool do_print_ident = false; 21 | bool verbose = false; 22 | unsigned int baudrate = 115200; 23 | unsigned int addr_width = 4; 24 | uint32_t addr; 25 | char *addr_string = NULL; 26 | uint32_t res, val; 27 | char *prog_name = argv[0]; 28 | char *uart_port = NULL; 29 | char *csv_file = NULL; 30 | FILE *csv; 31 | bool use_usb = false; 32 | 33 | while ((opt = getopt(argc, argv, ":w:r:b:a:v:c:u:Vih")) != -1) { 34 | switch (opt) { 35 | case 'r': 36 | char *endptr; 37 | 38 | do_read = true; 39 | addr = strtol(optarg, &endptr, 0); 40 | if (errno != 0 || endptr == optarg) 41 | addr_string = optarg; 42 | break; 43 | case 'w': 44 | 45 | do_write = true; 46 | addr = strtol(optarg, &endptr, 0); 47 | if (errno != 0 || endptr == optarg) 48 | addr_string = optarg; 49 | break; 50 | case 'i': 51 | do_print_ident = true; 52 | break; 53 | case 'b': 54 | baudrate = strtol(optarg, &endptr, 0); 55 | if (errno != 0 || endptr == optarg) 56 | goto err_print_usage; 57 | break; 58 | case 'a': 59 | addr_width = strtol(optarg, &endptr, 0); 60 | if (errno != 0 || endptr == optarg) 61 | goto err_print_usage; 62 | break; 63 | case 'c': 64 | csv_file = optarg; 65 | break; 66 | case 'u': 67 | uart_port = optarg; 68 | break; 69 | case 'V': 70 | verbose = true; 71 | break; 72 | case 'v': 73 | val = strtol(optarg, &endptr, 0); 74 | if (errno != 0 || endptr == optarg) 75 | goto err_print_usage; 76 | break; 77 | case 'h': 78 | print_usage(prog_name); 79 | return 0; 80 | break; 81 | case '?': 82 | default: 83 | err_print_usage: 84 | print_usage(prog_name); 85 | return -1; 86 | } 87 | } 88 | 89 | if (!uart_port) { 90 | printf("You must specify an uart or USB port using -u port\n"); 91 | printf("Syntax: -u /dev/ttyUSBxxx\n"); 92 | printf("Syntax: -u usb://vid:pid/EP\n"); 93 | print_usage(prog_name); 94 | return -1; 95 | } 96 | 97 | uartbone_unix_init(&ctx, uart_port, baudrate, addr_width); 98 | 99 | if (!ctx.open) { 100 | printf("opening device %s failed!\n", uart_port); 101 | return ctx.error; 102 | } 103 | 104 | if (verbose) { 105 | if (do_print_ident) 106 | printf("printing ident string\n"); 107 | if (do_read) 108 | printf("issuing Read\n"); 109 | if (do_write) 110 | printf("issuing Write\n"); 111 | printf("- %s: %s\n", ctx_uses_usb(&ctx) ? "usb" : "uart", uart_port); 112 | if (!ctx_uses_usb(&ctx)) 113 | printf("- baudrate: %d\n", baudrate); 114 | printf("- address width: %d\n", addr_width); 115 | if (csv_file) 116 | printf("- csv: %s\n", csv_file); 117 | printf("\n"); 118 | } 119 | 120 | // Let's open the CSV file 121 | if (do_print_ident || ((do_read || do_write) && addr_string)) { 122 | if (!csv_file) { 123 | printf("You must pass -c argument\n"); 124 | return -1; 125 | } 126 | csv = fopen(csv_file, "r"); 127 | if (!csv) { 128 | perror("fopen"); 129 | return errno; 130 | } 131 | } 132 | 133 | if (do_print_ident) { 134 | int ret; 135 | uint32_t ident_addr; 136 | 137 | ret = get_reg_addr(csv, "identifier_mem", &ident_addr); 138 | if (ret) { 139 | printf("Could not find 'identifier_mem' in CSV file\n"); 140 | return -1; 141 | } 142 | memset(ident_str, '\0', sizeof(ident_str)); 143 | do { 144 | c = uartbone_read(&ctx, ident_addr+i*4); 145 | ident_str[i++] = c; 146 | } while (c); 147 | printf("ident: %s\n", ident_str); 148 | } else if (do_read) { 149 | int ret; 150 | 151 | if (addr_string) { 152 | ret = get_reg_addr(csv, addr_string, &addr); 153 | if (ret) { 154 | printf("Could not find register '%s'\n", addr_string); 155 | return -1; 156 | } 157 | } 158 | val = uartbone_read(&ctx, addr); 159 | printf("Read 0x%08x @ 0x%08x\n", val, addr); 160 | } else if (do_write) { 161 | int ret; 162 | 163 | if (addr_string) { 164 | ret = get_reg_addr(csv, addr_string, &addr); 165 | if (ret) { 166 | printf("Could not find register '%s'\n", addr_string); 167 | return -1; 168 | } 169 | } 170 | uartbone_write(&ctx, addr, val); 171 | printf("Written 0x%08x @ 0x%08x\n", val, addr); 172 | } 173 | 174 | return 0; 175 | } 176 | -------------------------------------------------------------------------------- /software/boards/hydrausb3/Makefile: -------------------------------------------------------------------------------- 1 | RM := rm -rf 2 | 3 | # Check and choose riscv compiler either closed source from MounRiver Studio riscv-none-embed" or open source one GCC riscv-none-elf 4 | # For open source GCC riscv-none-elf see https://github.com/hydrausb3/riscv-none-elf-gcc-xpack/releases/ 5 | COMPILER_PREFIX := $(shell command -v riscv-none-embed-gcc >/dev/null 2>&1 && echo "riscv-none-embed" || true) 6 | COMPILER_PREFIX := $(if $(COMPILER_PREFIX),$(COMPILER_PREFIX),$(shell command -v riscv-none-elf-gcc >/dev/null 2>&1 && echo "riscv-none-elf" || true)) 7 | 8 | ifeq ($(COMPILER_PREFIX),riscv-none-embed) 9 | MARCH_OPT := -march=rv32imac 10 | else ifeq ($(COMPILER_PREFIX),riscv-none-elf) 11 | MARCH_OPT := -march=rv32imac_zicsr 12 | else 13 | $(error Unknown COMPILER_PREFIX: $(COMPILER_PREFIX)) 14 | endif 15 | 16 | # Define option(s) defined in pre-processor compiler option(s) 17 | DEFINE_OPTS = -DDEBUG=1 18 | # Optimisation option(s) 19 | OPTIM_OPTS = -O3 20 | # Debug option(s) 21 | DEBUG = -g 22 | 23 | BUILD_DIR = ./build 24 | 25 | PROJECT = $(BUILD_DIR)/sucrela_fw 26 | BSP_DIR = ../../../wch-ch56x-bsp 27 | 28 | RVMSIS_DIR = $(BSP_DIR)/rvmsis 29 | RVMSIS_SRCS = $(wildcard $(RVMSIS_DIR)/*.c) 30 | OBJS += $(patsubst $(RVMSIS_DIR)/%.c,$(BUILD_DIR)/%.o,$(RVMSIS_SRCS)) 31 | 32 | DRV_DIR = $(BSP_DIR)/drv 33 | DRV_SRCS = $(wildcard $(DRV_DIR)/*.c) 34 | OBJS += $(patsubst $(DRV_DIR)/%.c,$(BUILD_DIR)/%.o,$(DRV_SRCS)) 35 | 36 | BOARD_DIR = $(BSP_DIR)/board 37 | BOARD_SRCS = $(BOARD_DIR)/hydrausb3_v1.c 38 | OBJS += $(patsubst $(BOARD_DIR)/%.c,$(BUILD_DIR)/%.o,$(BOARD_SRCS)) 39 | 40 | USB_DIR = $(BSP_DIR)/usb/usb_devbulk 41 | USB_SRCS = $(wildcard $(USB_DIR)/*.c) 42 | OBJS += $(patsubst $(USB_DIR)/%.c,$(BUILD_DIR)/%.o,$(USB_SRCS)) 43 | 44 | USER_DIR = ./ 45 | USER_SRCS = $(wildcard $(USER_DIR)/*.c) 46 | OBJS += $(patsubst $(USER_DIR)/%.c,$(BUILD_DIR)/%.o,$(USER_SRCS)) 47 | 48 | # All of the sources participating in the build are defined here 49 | OBJS += $(BUILD_DIR)/startup_CH56x.o 50 | DEPS = $(subst .o,.d,$(OBJS)) 51 | LIBS = 52 | 53 | SOC_GENERATED_HEADERS = ../../../build/gsd_orangecrab/software/include 54 | UARTBONE_DIR = ../../libuartbone 55 | UARTBONE_SRCS = $(UARTBONE_DIR)/uartbone.c 56 | OBJS += $(patsubst $(UARTBONE_DIR)/%.c,$(BUILD_DIR)/%.o,$(UARTBONE_SRCS)) 57 | 58 | BASE_OPTS = $(MARCH_OPT) -mabi=ilp32 -msmall-data-limit=8 $(OPTIM_OPTS) -Wno-discarded-qualifiers -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections 59 | C_OPTS = $(BASE_OPTS) $(DEBUG) $(DEFINE_OPTS)\ 60 | $(INCLUDES) -std=gnu99 -MMD -MP -MT"$(@)" 61 | LD_OPTS = -T "$(BSP_DIR)/ld/.ld" -nostartfiles -Xlinker --gc-sections -Xlinker --print-memory-usage -Wl,-Map,"$(PROJECT).map" --specs=nano.specs --specs=nosys.specs 62 | 63 | INCLUDES = \ 64 | -I"$(RVMSIS_DIR)" \ 65 | -I"$(DRV_DIR)" \ 66 | -I"$(BOARD_DIR)" \ 67 | -I"$(USB_DIR)" \ 68 | -I"$(USER_DIR)" \ 69 | -I"$(BUILD_DIR)" \ 70 | -I"$(UARTBONE_DIR)" 71 | 72 | # Add inputs and outputs from these tool invocations to the build variables 73 | SECONDARY_FLASH += $(PROJECT).hex $(PROJECT).bin 74 | SECONDARY_LIST += $(PROJECT).lst 75 | SECONDARY_SIZE += $(PROJECT).siz 76 | SECONDARY_MAP += $(PROJECT).map 77 | 78 | SECONDARY_OUTPUTS = $(SECONDARY_FLASH) $(SECONDARY_LIST) $(SECONDARY_SIZE) $(SECONDARY_MAP) 79 | secondary-outputs: $(SECONDARY_OUTPUTS) 80 | 81 | # All Target 82 | all: $(PROJECT).elf secondary-outputs 83 | 84 | .PRECIOUS: $(BUILD_DIR)/. $(BUILD_DIR)%/. 85 | 86 | $(BUILD_DIR)/.: 87 | mkdir -p $@ 88 | 89 | $(BUILD_DIR)%/.: 90 | mkdir -p $@ 91 | 92 | .SECONDEXPANSION: 93 | 94 | $(BUILD_DIR)/startup_CH56x.o: $(BSP_DIR)/startup/startup_CH56x.S | $$(@D)/. 95 | @echo 'Building file: $<' 96 | $(COMPILER_PREFIX)-gcc $(C_OPTS) -x assembler -c -o "$@" "$<" 97 | @echo ' ' 98 | 99 | $(BUILD_DIR)/csr.h: $(SOC_GENERATED_HEADERS)/generated/csr.h 100 | grep 'define CSR_' $< > $@ 101 | 102 | $(BUILD_DIR)/%.o: $(USER_DIR)/%.c $(BUILD_DIR)/csr.h | $$(@D)/. 103 | @echo $(OBJS) 104 | @echo 'Building file: $<' 105 | $(COMPILER_PREFIX)-gcc $(C_OPTS) -c -o "$@" "$<" 106 | @echo ' ' 107 | 108 | $(BUILD_DIR)/%.o: $(UARTBONE_DIR)/%.c | $$(@D)/. 109 | @echo $(OBJS) 110 | @echo 'Building file: $<' 111 | $(COMPILER_PREFIX)-gcc $(C_OPTS) -c -o "$@" "$<" 112 | @echo ' ' 113 | 114 | $(BUILD_DIR)/%.o: $(RVMSIS_DIR)/%.c | $$(@D)/. 115 | @echo 'Building file: $<' 116 | $(COMPILER_PREFIX)-gcc $(C_OPTS) -c -o "$@" "$<" 117 | @echo ' ' 118 | 119 | $(BUILD_DIR)/%.o: $(DRV_DIR)/%.c | $$(@D)/. 120 | @echo 'Building file: $<' 121 | $(COMPILER_PREFIX)-gcc $(C_OPTS) -c -o "$@" "$<" 122 | @echo ' ' 123 | 124 | $(BUILD_DIR)/%.o: $(BOARD_DIR)/%.c | $$(@D)/. 125 | @echo 'Building file: $<' 126 | $(COMPILER_PREFIX)-gcc $(C_OPTS) -c -o "$@" "$<" 127 | @echo ' ' 128 | 129 | $(BUILD_DIR)/%.o: $(USB_DIR)/%.c | $$(@D)/. 130 | @echo 'Building file: $<' 131 | mkdir -p $(@D) 132 | $(COMPILER_PREFIX)-gcc $(C_OPTS) -c -o "$@" "$<" 133 | @echo ' ' 134 | 135 | # Tool invocations 136 | $(PROJECT).elf: $(OBJS) 137 | @echo 'Invoking: GNU RISC-V Cross C Linker' 138 | $(COMPILER_PREFIX)-gcc $(BASE_OPTS) $(LD_OPTS) -o "$(PROJECT).elf" $(OBJS) $(LIBS) 139 | @echo ' ' 140 | 141 | $(PROJECT).hex: $(PROJECT).elf 142 | @echo 'Invoking: GNU RISC-V Cross Create Flash Image' 143 | $(COMPILER_PREFIX)-objcopy -O ihex "$(PROJECT).elf" "$(PROJECT).hex" 144 | @echo ' ' 145 | 146 | $(PROJECT).bin: $(PROJECT).elf 147 | -@echo 'Create Flash Image BIN' 148 | -$(COMPILER_PREFIX)-objcopy -O binary "$(PROJECT).elf" "$(PROJECT).bin" 149 | -@echo ' ' 150 | 151 | $(PROJECT).lst: $(PROJECT).elf 152 | @echo 'Invoking: GNU RISC-V Cross Create Listing' 153 | $(COMPILER_PREFIX)-objdump --source --all-headers --demangle --line-numbers --wide "$(PROJECT).elf" > "$(PROJECT).lst" 154 | @echo ' ' 155 | 156 | $(PROJECT).siz: $(PROJECT).elf 157 | @echo 'Invoking: GNU RISC-V Cross Print Size' 158 | $(COMPILER_PREFIX)-size --format=berkeley "$(PROJECT).elf" 159 | @echo ' ' 160 | 161 | # Other Targets 162 | clean: 163 | -$(RM) $(OBJS) $(DEPS) $(SECONDARY_OUTPUTS) $(PROJECT).elf 164 | -@echo ' ' 165 | 166 | .PHONY: all clean dependents 167 | -------------------------------------------------------------------------------- /modules/la.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from litex.soc.interconnect.csr import AutoCSR, CSRStorage 3 | from litex.soc.interconnect import stream 4 | 5 | from modules.trigger import Trigger 6 | from modules.subsampler import SubSampler 7 | from modules.storage import Storage 8 | from modules.hspi import HSPITransmitter, HSPIPacket 9 | 10 | 11 | class LA(Module, AutoCSR): 12 | def __init__(self, ios, hspi_pads, depth, samplerate=1e12, clock_domain="sys", trigger_depth=16, register=False, 13 | csr_csv="analyzer.csv", testing=False): 14 | self.ios = ios 15 | self.depth = depth 16 | self.samplerate = int(samplerate) 17 | self.data_width = data_width = len(ios) 18 | self.fake_data = Signal(data_width) 19 | self.csr_csv = csr_csv 20 | assert len(ios) in [4, 8, 16] 21 | hspi_data_width = {4: 8, 22 | 8: 16, 23 | 16: 32}[len(ios)] 24 | 25 | # Frontend 26 | self.submodules.trigger = ClockDomainsRenamer({"scope": clock_domain})(Trigger(data_width, depth=trigger_depth)) 27 | self.submodules.subsampler = ClockDomainsRenamer({"scope": clock_domain})(SubSampler(data_width)) 28 | 29 | # Storage buffer 30 | self.submodules.storage = ClockDomainsRenamer({"scope": clock_domain})(Storage(data_width, depth)) 31 | 32 | # Upconverter 33 | self.submodules.converter = ClockDomainsRenamer(clock_domain)(stream.Converter(len(ios), hspi_data_width)) 34 | 35 | # SyncFIFO to buffer a HSPI packet 36 | self.submodules.hspi_packet_buffer = ClockDomainsRenamer(clock_domain)(stream.SyncFIFO([("data", 37 | hspi_data_width)], 38 | depth=0x2000)) 39 | # HSPI TX 40 | self.submodules.hspi_tx = ClockDomainsRenamer({"scope": clock_domain})(HSPITransmitter(hspi_pads, hspi_data_width)) 41 | 42 | scope_sync = getattr(self.sync, clock_domain) 43 | scope_sync += [ 44 | If(~self.hspi_tx.enable.storage, 45 | self.fake_data.eq(0) 46 | ).Else( 47 | self.fake_data.eq(self.fake_data + 1) 48 | ) 49 | ] 50 | 51 | self.comb += self.trigger.sink.valid.eq(1) 52 | 53 | if testing: 54 | self.comb += self.trigger.sink.data.eq(self.fake_data) 55 | else: 56 | self.comb += self.trigger.sink.data.eq(ios) 57 | 58 | # Pipeline 59 | self.submodules.pipeline = stream.Pipeline( 60 | self.trigger.source, 61 | self.subsampler, 62 | self.storage, 63 | self.converter, 64 | self.hspi_packet_buffer, 65 | ) 66 | 67 | self.packet_is_buffered = Signal() 68 | 69 | self.comb += [ 70 | self.packet_is_buffered.eq(~self.hspi_tx.fsm.ongoing("WAIT_INPUT") | 71 | (self.hspi_packet_buffer.level >= self.hspi_tx.max_packet_size.storage)), 72 | If(self.packet_is_buffered, 73 | self.pipeline.source.connect(self.hspi_tx.sink) 74 | ).Else( 75 | self.hspi_tx.sink.valid.eq(0) 76 | ) 77 | ] 78 | 79 | 80 | class LATest(Module): 81 | def __init__(self, stop_via="max_packet_size", inject_not_ready=False): 82 | hd_layout = [("oe", 1), ("o", 8), ("i", 8)] 83 | self.pads = Record([("hd", hd_layout), 84 | ("clk", 1), 85 | ("ready", 1), 86 | ("valid", 1), 87 | ("req", 1), 88 | ("hract", 1), 89 | ("htack", 1) 90 | ]) 91 | self.ios = Signal(4) 92 | self.submodules.la = LA(self.ios, self.pads, depth=64, clock_domain="sys", samplerate=48e6, testing=True) 93 | 94 | def handle_data(data, buffer): 95 | assert data in range(256) 96 | buffer.extend(data.to_bytes(1, "little")) 97 | 98 | def wait_for_tx_req(): 99 | while True: 100 | tx_req = yield self.pads.req 101 | if tx_req: 102 | print("Detected TX_REQ") 103 | break 104 | yield 105 | 106 | def simulate(): 107 | yield 108 | yield from self.la.storage.length.write(64) 109 | yield 110 | yield from self.la.hspi_tx.enable.write(1) 111 | yield 112 | yield from self.la.subsampler.value.write(0) 113 | yield 114 | yield from self.la.hspi_tx.max_packet_size.write(50) 115 | yield 116 | yield 117 | yield 118 | yield 119 | yield from self.la.storage.enable.write(1) 120 | yield from wait_for_tx_req() 121 | 122 | yield self.pads.ready.eq(1) 123 | for i in range(100): 124 | tx_valid = yield self.pads.valid 125 | if tx_valid == 1: 126 | print("Detected TX_VALID") 127 | break 128 | yield 129 | 130 | data_buffer = bytearray() 131 | for i in range(200): 132 | if i == 40: 133 | if stop_via == "hspi": 134 | yield self.la.hspi_tx.enable.storage.eq(0) 135 | elif stop_via == "storage": 136 | yield self.la.storage.enable.storage.eq(0) 137 | tx_valid = yield self.pads.valid 138 | tx_req = yield self.pads.req 139 | hd_oe = yield self.pads.hd.oe 140 | if (i == 42) and inject_not_ready: 141 | yield self.pads.ready.eq(0) 142 | if (i == 47) and inject_not_ready: 143 | yield self.pads.ready.eq(1) 144 | ready = yield self.pads.ready 145 | if tx_valid == 0: 146 | print("TX_VALID is gone (i={})!".format(i)) 147 | if ready == 0: 148 | print("RX_READY is gone (i={})!".format(i)) 149 | if hd_oe == 0: 150 | print("hd.oe is gone (i={})!".format(i)) 151 | if tx_valid & ready & hd_oe: 152 | data = yield self.pads.hd.o 153 | handle_data(data, data_buffer) 154 | print("{}: Transmitted 0x{:02x}".format(i, data)) 155 | if tx_req == 0: 156 | print("TX_REQ is gone (i={})!".format(i)) 157 | print("total buffer (len {}): {}".format(len(data_buffer), data_buffer)) 158 | break 159 | yield 160 | 161 | HSPIPacket(data_buffer) 162 | 163 | print("Running sim!") 164 | run_simulation(self, simulate(), vcd_name="sim.vcd") -------------------------------------------------------------------------------- /hw/hydrasucrela/Library.pretty/probe_connector.kicad_mod: -------------------------------------------------------------------------------- 1 | (footprint "probe_connector" 2 | (version 20240108) 3 | (generator "pcbnew") 4 | (generator_version "8.0") 5 | (layer "F.Cu") 6 | (property "Reference" "REF**" 7 | (at 0 -0.5 0) 8 | (unlocked yes) 9 | (layer "F.SilkS") 10 | (uuid "bdeded33-9f75-4158-afc6-220c7368537f") 11 | (effects 12 | (font 13 | (size 1 1) 14 | (thickness 0.1) 15 | ) 16 | ) 17 | ) 18 | (property "Value" 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"c7efe304-b337-4b0d-a93d-3537d4e16ef7") 338 | ) 339 | (pad "40" connect rect 340 | (at 12.1 -2.5 180) 341 | (size 0.76 2) 342 | (layers "B.Cu" "B.Mask") 343 | (uuid "8817d31c-c9aa-4e7f-b5c0-92de057fd85b") 344 | ) 345 | ) 346 | -------------------------------------------------------------------------------- /software/boards/hydrausb3/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | /* System clock and HSPI freq : 120 MHz */ 7 | #define FREQ_SYS (120000000) 8 | 9 | #include "core_riscv.h" 10 | #include "CH56x_bsp.h" 11 | #include "CH56x_uart.h" 12 | #include "CH56x_common.h" 13 | 14 | #include "config.h" 15 | #include "uartbone.h" 16 | #include "csr.h" // for FPGA SoC CSR register addresses 17 | 18 | #include "CH56x_usb30_devbulk.h" 19 | #include "CH56x_usb20_devbulk.h" 20 | #include "CH56x_usb30_devbulk_LIB.h" 21 | #include "CH56x_usb_devbulk_desc_cmd.h" 22 | 23 | #include "hydrausb3_usb_devbulk_vid_pid.h" 24 | 25 | #define RISCV_FENCE(p, s) \ 26 | __asm__ __volatile__ ("fence " #p "," #s : : : "memory") 27 | 28 | /* These barriers need to enforce ordering on both devices or memory. */ 29 | #define mb() RISCV_FENCE(iorw,iorw) 30 | #define rmb() RISCV_FENCE(ir,ir) 31 | #define wmb() RISCV_FENCE(ow,ow) 32 | 33 | __attribute__((aligned(16))) volatile uint8_t HSPI_RX_Addr0[HSPI_RX_DMA_LENGTH] __attribute__((section(".DMADATA"))); 34 | __attribute__((aligned(16))) volatile uint8_t HSPI_RX_Addr1[HSPI_RX_DMA_LENGTH] __attribute__((section(".DMADATA"))); 35 | 36 | /* Shared variables */ 37 | volatile int HSPI_TX_End_Flag; // Send completion flag 38 | volatile int HSPI_RX_End_Flag; // Receive completion flag 39 | volatile int HSPI_RX_End_Err; // 0=No Error else >0 Error code 40 | 41 | /* FLASH_ROMA Read Unique ID (8bytes/64bits) */ 42 | #define FLASH_ROMA_UID_ADDR (0x77fe4) 43 | usb_descriptor_serial_number_t unique_id; 44 | 45 | /* USB VID PID */ 46 | usb_descriptor_usb_vid_pid_t vid_pid = 47 | { 48 | .vid = USB_VID, 49 | .pid = USB_PID 50 | }; 51 | 52 | void uartbone_ch56x_init(struct uartbone_ctx *ctx, int uart_num, int baudrate, int addr_width); 53 | 54 | volatile int usb_cmd_rxed = 0; 55 | volatile uint8_t usb_cmd[11]; 56 | volatile uint8_t usb_cmd_len; 57 | extern volatile int EP1_to_be_sent; 58 | volatile int ep1_out_nack = 0; 59 | volatile unsigned int hspi_rx_packets = 0; 60 | volatile unsigned int hspi_first_error_packet = -1; 61 | 62 | static void USB_init(void) { 63 | R32_USB_CONTROL = 0; 64 | PFIC_EnableIRQ(USBSS_IRQn); 65 | PFIC_EnableIRQ(LINK_IRQn); 66 | PFIC_EnableIRQ(TMR0_IRQn); 67 | R8_TMR0_INTER_EN = RB_TMR_IE_CYC_END; 68 | TMR0_TimerInit(67000000); // USB3.0 connection failure timeout about 0.56 seconds 69 | 70 | /* USB Descriptor set String Serial Number with CH569 Unique ID */ 71 | usb_descriptor_set_string_serial_number(&unique_id); 72 | 73 | /* USB Descriptor set USB VID/PID */ 74 | usb_descriptor_set_usb_vid_pid(&vid_pid); 75 | 76 | /* USB3.0 initialization, make sure that the two USB3.0 interrupts are enabled before initialization */ 77 | USB30D_init(ENABLE); 78 | } 79 | 80 | #undef DEBUG 81 | 82 | int main(void) { 83 | struct uartbone_ctx ctx; 84 | int i = 0; 85 | char c; 86 | volatile uint8_t *hspi_rxed_bytes = (volatile uint8_t *)HSPI_RX_Addr0; 87 | bool print_done = false; 88 | 89 | bsp_gpio_init(); 90 | bsp_init(FREQ_SYS); 91 | memset(&unique_id, 0, sizeof(unique_id)); 92 | FLASH_ROMA_READ(FLASH_ROMA_UID_ADDR, (uint32_t*)&unique_id, sizeof(unique_id)); 93 | UART1_init(UART1_BAUD, FREQ_SYS); 94 | UART3_init(UART3_BAUD, FREQ_SYS); 95 | 96 | printf("\n\r"); 97 | printf("###########################\n\r"); 98 | printf("# SucreLA fw starting up! #\n\r"); 99 | printf("###########################\n\r\n\r"); 100 | 101 | printf("board: HydraUSB3\n\r"); 102 | printf("USB init..."); 103 | USB_init(); 104 | printf("done\n\r"); 105 | uartbone_ch56x_init(&ctx, 3, 115200, 4); 106 | printf("uartbone: initialized on UART3\n\r"); 107 | 108 | printf("Preparing HSPI RX interface...\n\r"); 109 | memset(HSPI_RX_Addr0, '\0', HSPI_RX_DMA_LENGTH); 110 | memset(HSPI_RX_Addr1, '\0', HSPI_RX_DMA_LENGTH); 111 | HSPI_RX_End_Flag = 0; // Receive completion flag 112 | HSPI_RX_End_Err = 0; // 0=No Error else >0 Error code 113 | HSPI_DoubleDMA_Init(HSPI_DEVICE, HSPI_DATA_WIDTH, (unsigned long int)HSPI_RX_Addr0, (unsigned long int)HSPI_RX_Addr1, 0); 114 | R8_HSPI_RX_SC = 0; 115 | 116 | while (1) { // infinite loop to handle uartbone over USB protocole 117 | if (usb_cmd_rxed) { 118 | mb(); 119 | #ifdef DEBUG 120 | printf("usb rx!\n\r"); 121 | #endif 122 | switch (usb_cmd[0]) { 123 | case 'w': { 124 | #ifdef DEBUG 125 | printf("uart sending: \n\r"); 126 | for (i = 2; i < usb_cmd_len+2; i++) 127 | printf("%02x ", usb_cmd[i]); 128 | printf("\n\r"); 129 | #endif 130 | UART3_SendString(&usb_cmd[2], usb_cmd_len); 131 | usb_cmd_len = 0; 132 | break; 133 | } 134 | case 'r': { 135 | UART3_Recv(usb_cmd, usb_cmd_len); 136 | #ifdef DEBUG 137 | printf("uart rx'ed: \n\r"); 138 | for (i = 0; i < usb_cmd_len; i++) 139 | printf("%02x ", usb_cmd[i]); 140 | printf("\n\r"); 141 | #endif 142 | memcpy(endp1Tbuff, usb_cmd, usb_cmd_len); 143 | mb(); 144 | EP1_to_be_sent = usb_cmd_len; 145 | USB30_IN_set(ENDP_1, ENABLE, ACK, 1, usb_cmd_len); // Set the endpoint to be able to send 1 packet 146 | USB30_send_ERDY(ENDP_1 | IN, 1); // Notify the host we are ready to receive 1 IN packet 147 | usb_cmd_len = 0; 148 | break; 149 | } 150 | default: { 151 | printf("buggy usb cmd: \n\r"); 152 | for (i = 0; i < usb_cmd_len + 1; i++) 153 | printf("%02x ", usb_cmd[i]); 154 | printf("\n\r"); 155 | } 156 | } 157 | usb_cmd_rxed = 0; // command completed, let's prepare for the next one. 158 | USB30_OUT_set(ENDP_1, ACK, 0); // Set EP1 to ACK next OUT packet, we can now receive a new command 159 | USB30_send_ERDY(ENDP_1 | OUT, 1); // Notify the host we are ready to receive 1 OUT packet 160 | } 161 | 162 | if (HSPI_RX_End_Flag) { 163 | if (!(hspi_rx_packets % 100)) 164 | printf("HSPI received %d packets!\n\r", hspi_rx_packets); 165 | HSPI_RX_End_Flag = 0; 166 | } 167 | 168 | if (HSPI_RX_End_Err && (!print_done)) { 169 | int start = 0; 170 | bool error_printed = false; 171 | uint8_t prev; 172 | printf("HSPI received %d packets!\n\r", hspi_rx_packets); 173 | if (HSPI_RX_End_Err) { 174 | if (HSPI_RX_End_Err & RB_HSPI_CRC_ERR) 175 | printf("HSPI CRC error\n\r"); 176 | printf("first error packet was num #%d\n\r", hspi_first_error_packet); 177 | } 178 | bsp_wait_us_delay(1); 179 | printf("Packet 0: \n\r"); 180 | while (hspi_rxed_bytes[start] == 0) { 181 | printf("%02x ", hspi_rxed_bytes[start]); 182 | start++; 183 | } 184 | prev = hspi_rxed_bytes[start] - 1; 185 | for (i = start; i < 4096 - start; i++) { 186 | if (!(i % 50)) 187 | printf("\n\r"); 188 | printf("%02x ", hspi_rxed_bytes[i]); 189 | prev = hspi_rxed_bytes[i]; 190 | } 191 | printf("\n\r"); 192 | printf("RX0 LEN = %08x RX1 LEN = %08x\n\r", R16_HSPI_RX_LEN0, R16_HSPI_RX_LEN1); 193 | printf("UDF0: %08x UDF1: %08x\n\r", R32_HSPI_UDF0, R32_HSPI_UDF1); 194 | printf("RX NUM seq %02x\n\r", R8_HSPI_RX_SC); 195 | printf("Packet 1: \n\r"); 196 | hspi_rxed_bytes = HSPI_RX_Addr1; 197 | start = 0; 198 | while (hspi_rxed_bytes[start] == 0) { 199 | printf("%02x ", hspi_rxed_bytes[start]); 200 | start++; 201 | } 202 | prev = hspi_rxed_bytes[start] - 1; 203 | for (i = start; i < 4096 - start; i++) { 204 | if (!(i % 50)) 205 | printf("\n\r"); 206 | printf("%02x ", hspi_rxed_bytes[i]); 207 | prev = hspi_rxed_bytes[i]; 208 | } 209 | printf("\n\r"); 210 | printf("RX0 LEN = %08x RX1 LEN = %08x\n\r", R16_HSPI_RX_LEN0, R16_HSPI_RX_LEN1); 211 | printf("UDF0: %08x UDF1: %08x\n\r", R32_HSPI_UDF0, R32_HSPI_UDF1); 212 | printf("RX NUM seq %02x\n\r", R8_HSPI_RX_SC); 213 | HSPI_RX_End_Err = 0; 214 | HSPI_RX_End_Flag = 0; 215 | print_done = true; 216 | } 217 | } 218 | 219 | return 0; 220 | } 221 | 222 | void HSPI_IRQHandler_ReInitRX(void) 223 | { 224 | R32_HSPI_RX_ADDR0 = (unsigned long int)HSPI_RX_Addr0; 225 | R32_HSPI_RX_ADDR1 = (unsigned long int)HSPI_RX_Addr1; 226 | } 227 | 228 | __attribute__((interrupt("WCH-Interrupt-fast"))) void HSPI_IRQHandler(void) 229 | { 230 | if (R8_HSPI_INT_FLAG & RB_HSPI_IF_R_DONE) // Single packet reception completed 231 | { 232 | bool error = false; 233 | R8_HSPI_INT_FLAG = RB_HSPI_IF_R_DONE; // Clear Interrupt 234 | hspi_rx_packets++; 235 | if (R8_HSPI_RX_SC & 0xf) 236 | R32_HSPI_RX_ADDR0 = (unsigned long int)HSPI_RX_Addr0; 237 | else 238 | R32_HSPI_RX_ADDR1 = (unsigned long int)HSPI_RX_Addr1; 239 | 240 | HSPI_RX_End_Flag = 1; 241 | if(R8_HSPI_RTX_STATUS & RB_HSPI_CRC_ERR) { 242 | HSPI_RX_End_Err |= RB_HSPI_CRC_ERR; 243 | error = true; 244 | } 245 | if(R8_HSPI_INT_FLAG & RB_HSPI_IF_FIFO_OV) { 246 | error = true; 247 | printf("HSPI FIFO overflow!\n\r"); 248 | R8_HSPI_INT_FLAG = RB_HSPI_IF_FIFO_OV; 249 | } 250 | if (R8_HSPI_RTX_STATUS & RB_HSPI_NUM_MIS) { 251 | error = true; 252 | printf("HSPI seq num mismatch\n\r"); 253 | HSPI_RX_End_Err |= RB_HSPI_NUM_MIS; 254 | } 255 | if (error) { 256 | printf("ERROR!!!\n\r"); 257 | if (hspi_first_error_packet == -1) 258 | hspi_first_error_packet = hspi_rx_packets; 259 | return; 260 | } 261 | USB30_IN_set(ENDP_2, ENABLE, ACK, DEF_ENDP2_IN_BURST_LEVEL, 1024); // Able to send 4x 1024-bytes packets 262 | USB30_send_ERDY(ENDP_2 | IN, DEF_ENDP2_IN_BURST_LEVEL); // Tell Host we can accept EP2 IN packets 263 | } 264 | } 265 | 266 | __attribute__((interrupt("WCH-Interrupt-fast"))) void HardFault_Handler(void) 267 | { 268 | printf("HardFault\n"); 269 | printf(" SP=0x%08X\n", __get_SP()); 270 | printf(" MIE=0x%08X\n", __get_MIE()); 271 | printf(" MSTATUS=0x%08X\n", __get_MSTATUS()); 272 | printf(" MCAUSE=0x%08X\n", __get_MCAUSE()); 273 | bsp_wait_ms_delay(1); 274 | } -------------------------------------------------------------------------------- /modules/hspi.py: -------------------------------------------------------------------------------- 1 | from migen import * 2 | from migen.genlib.cdc import MultiReg 3 | from litex.soc.interconnect import stream 4 | from litex.gen.genlib.misc import WaitTimer 5 | from litex.soc.interconnect.csr import * 6 | 7 | from modules.misc import core_layout 8 | 9 | import sys 10 | 11 | 12 | class CRC(Module): 13 | def __init__(self, polynomial, crc_size, datawidth, init=None, delay=False): 14 | if init is None: 15 | init = (1 << crc_size) - 1 16 | 17 | self.reset_in = Signal() 18 | self.enable_in = Signal() 19 | self.data_in = Signal(datawidth) 20 | self.crc_out = Signal(crc_size) 21 | 22 | crcreg = [Signal(crc_size, reset=init) for i in range(datawidth + 1)] 23 | 24 | for i in range(datawidth): 25 | inv = self.data_in[i] ^ crcreg[i][crc_size - 1] 26 | tmp = [] 27 | tmp.append(inv) 28 | for j in range(crc_size - 1): 29 | if((polynomial >> (j + 1)) & 1): 30 | tmp.append(crcreg[i][j] ^ inv) 31 | else: 32 | tmp.append(crcreg[i][j]) 33 | self.comb += crcreg[i + 1].eq(Cat(*tmp)) 34 | 35 | self.sync += [ 36 | If(self.reset_in, 37 | crcreg[0].eq(init) 38 | ).Elif(self.enable_in, 39 | crcreg[0].eq(crcreg[datawidth]) 40 | ) 41 | ] 42 | 43 | out_expr = self.crc_out.eq(crcreg[datawidth][::-1] ^ init) 44 | 45 | if delay: 46 | self.sync += out_expr 47 | else: 48 | self.comb += out_expr 49 | 50 | 51 | class HSPITransmitter(Module, AutoCSR): 52 | def __init__(self, pads, data_in_width, hd_width=None): 53 | self.sink = sink = stream.Endpoint(([("data", data_in_width)])) 54 | self.hd = hd = self.add_tristate(pads.hd) if not hasattr(pads.hd, "oe") else pads.hd 55 | self.hd_width = len(hd.o) if hd_width is None else hd_width 56 | assert self.hd_width <= len(hd.o) 57 | assert self.hd_width in [8, 16, 32] 58 | assert data_in_width in [4, 8, 16, 32] 59 | assert self.hd_width % data_in_width == 0 60 | assert self.hd_width >= data_in_width # TODO: allow more diverse configurations 61 | crc_size = 32 if self.hd_width == 32 else 16 62 | self.cd_scope = ClockDomain() 63 | 64 | crc = CRC(polynomial=0x8005, crc_size=crc_size, datawidth=self.hd_width, delay=False) 65 | self.crc = crc = ClockDomainsRenamer("scope")(crc) 66 | self.submodules.crc = crc 67 | 68 | header = Signal(32) 69 | header_reg = Signal(32) 70 | tll_2b_in = Signal(2, reset={8: 0, 16: 1, 32: 2}[self.hd_width]) 71 | sequence_nr_in = Signal(4, reset=0) 72 | user_id_in = Signal(26, reset=0xA5B6C7D8) 73 | word_index = Signal(max=4096) 74 | self.crc_r = Signal(crc_size) 75 | self.state = Signal(max=6) 76 | self.state_r = CSRStatus(len(self.state)) 77 | self.specials += MultiReg(self.state, self.state_r.status) 78 | self.enable = CSRStorage(write_from_dev=True) 79 | self.enable_r = Signal() 80 | self.enable_r_d = Signal() 81 | self.enable_dropped = Signal() 82 | self.specials += MultiReg(self.enable.storage, self.enable_r, "scope") 83 | self.max_packet_size_r = Signal(max=4097, reset=4096) 84 | self.max_packet_size = CSRStorage(len(self.max_packet_size_r), reset=4096) 85 | self.specials += MultiReg(self.max_packet_size.storage, self.max_packet_size_r, "scope") 86 | self.not_ready_happened = Signal() 87 | self.max_packet_num = Signal(16) 88 | self.max_packet_num_r = CSRStorage(16) 89 | self.remaining_packets = Signal(16) 90 | self.specials += MultiReg(self.max_packet_num_r.storage, self.max_packet_num, "scope") 91 | self.hspi_pads_debug = Signal(len(Cat(pads.req, pads.ready, pads.valid, hd.o, hd.oe, sink.valid, sink.ready, sink.last, sink.data))) 92 | self.hspi_pads_csr = CSRStatus(len(self.hspi_pads_debug)) 93 | self.specials += MultiReg(self.hspi_pads_debug, self.hspi_pads_csr.status) 94 | 95 | self.comb += [ 96 | pads.clk.eq(ClockSignal("scope")), 97 | header.eq(Cat(user_id_in, sequence_nr_in, tll_2b_in)), 98 | self.enable_dropped.eq(self.enable_r_d & ~self.enable_r), 99 | self.hspi_pads_debug.eq(Cat(pads.req, pads.ready, pads.valid, hd.o, hd.oe, sink.valid, sink.ready, sink.last, sink.data)) 100 | ] 101 | 102 | self.sync.scope += [ 103 | self.enable_r_d.eq(self.enable_r) 104 | ] 105 | 106 | self.header_timer = header_timer = ClockDomainsRenamer("scope")(WaitTimer((32 / self.hd_width) - 1)) 107 | self.crc_timer = crc_timer = ClockDomainsRenamer("scope")(WaitTimer(1 if crc_size > self.hd_width else 0)) 108 | self.submodules += header_timer, crc_timer 109 | self.header_reg = header_reg 110 | 111 | # FSM 112 | fsm = FSM(reset_state="WAIT_INPUT") 113 | self.fsm = fsm = ClockDomainsRenamer("scope")(fsm) 114 | self.submodules += fsm 115 | fsm.act("WAIT_INPUT", 116 | self.state.eq(0), 117 | If(~self.enable_r, 118 | NextValue(self.remaining_packets, self.max_packet_num) 119 | ), 120 | self.sink.ready.eq(0), 121 | pads.req.eq(0), 122 | NextValue(word_index, 0), 123 | If(pads.hract, 124 | pads.htack.eq(1) 125 | ), 126 | If(sink.valid & self.enable_r & ~pads.hract, 127 | pads.req.eq(1), 128 | NextValue(header_reg, header), 129 | NextState("WAIT_TX_READY") 130 | ) 131 | ) 132 | 133 | fsm.act("WAIT_TX_READY", 134 | self.state.eq(1), 135 | pads.req.eq(1), 136 | self.sink.ready.eq(0), 137 | If(pads.ready & sink.valid, 138 | NextState("TX_HEADER") 139 | ).Elif(~sink.valid, 140 | NextState("WAIT_INPUT") 141 | ) 142 | ) 143 | 144 | fsm.act("TX_HEADER", 145 | self.state.eq(2), 146 | self.header_timer.wait.eq(1), 147 | pads.req.eq(1), 148 | hd.oe.eq(1), 149 | hd.o.eq(header_reg[:self.hd_width]), 150 | pads.valid.eq(1), 151 | crc.data_in.eq(header_reg[:self.hd_width]), 152 | crc.enable_in.eq(1), 153 | self.sink.ready.eq(0), 154 | NextValue(header_reg, header_reg >> self.hd_width), 155 | If(~sink.valid, 156 | NextState("WAIT_INPUT") 157 | ).Elif(self.header_timer.done, 158 | NextState("TX_DATA") 159 | ) 160 | ) 161 | 162 | fsm.act("TX_DATA", 163 | self.state.eq(3), 164 | self.sink.ready.eq(pads.ready), 165 | pads.req.eq(1), 166 | crc.data_in.eq(sink.data), 167 | crc.enable_in.eq(sink.valid & pads.ready), 168 | pads.valid.eq(sink.valid), 169 | hd.o.eq(sink.data), 170 | hd.oe.eq(1), 171 | If(~pads.ready, 172 | NextValue(self.not_ready_happened, 1), 173 | ), 174 | If(sink.valid & pads.ready & self.enable_r, 175 | NextValue(word_index, word_index + 1) 176 | ), 177 | If((self.enable_dropped | sink.valid) & pads.ready, 178 | NextValue(self.crc_r, crc.crc_out), 179 | ), 180 | If(sink.last | (word_index == self.max_packet_size_r - 1) | ~sink.valid | ~self.enable_r, 181 | NextState("TX_CRC"), 182 | ) 183 | ) 184 | 185 | fsm.act("TX_CRC", 186 | self.state.eq(4), 187 | self.crc_timer.wait.eq(pads.ready), 188 | pads.req.eq(1), 189 | pads.valid.eq(1), 190 | self.sink.ready.eq(0), 191 | hd.o.eq(self.crc_r[:self.hd_width]), 192 | If(pads.ready, 193 | NextValue(self.crc_r, self.crc_r >> self.hd_width) 194 | ), 195 | hd.oe.eq(1), 196 | If(self.crc_timer.done, 197 | NextState("WAIT_TX_READY_OVER"), 198 | NextValue(self.remaining_packets, self.remaining_packets - 1) 199 | ) 200 | ) 201 | 202 | fsm.act("WAIT_TX_READY_OVER", 203 | self.state.eq(5), 204 | self.sink.ready.eq(0), 205 | pads.valid.eq(0), 206 | pads.req.eq(0), 207 | hd.oe.eq(0), 208 | crc.reset_in.eq(1), 209 | If(~pads.ready, 210 | pads.req.eq(0), 211 | NextValue(sequence_nr_in, sequence_nr_in + 1), 212 | If(~self.remaining_packets & self.max_packet_num, # max_packet_num of 0 means infinity 213 | self.enable.we.eq(1), 214 | self.enable.dat_w.eq(0), 215 | ), 216 | NextState("WAIT_INPUT") 217 | ) 218 | ) 219 | 220 | def add_tristate(self, pad): 221 | t = TSTriple(len(pad)) 222 | self.specials += t.get_tristate(pad) 223 | return t 224 | 225 | 226 | class HSPIPacket: 227 | def __init__(self, data, hd_width=8): 228 | # Complete data of the packet 229 | self.data = data 230 | self.hd_width = hd_width 231 | self.crc_len = 4 if hd_width == 32 else 2 232 | 233 | if len(data) < 7: 234 | print("Packet is buggy, it should be at least 7 bytes long!") 235 | return 236 | 237 | # Packet header 238 | self.header = data[:4] 239 | # Packet payload (without header nor CRC) 240 | self.payload = data[4:-self.crc_len] 241 | # Packet CRC 242 | self.crc = data[-self.crc_len:] 243 | # TX length low 2 bits 244 | self.tll2b = (self.header[0] & 0xc0) >> 6 # 2 MSB 245 | # TX sequence number 246 | self.tsqn = (self.header[0] & 0x3c) >> 2 # 4 following bits 247 | # User self defined field 248 | self.usdf = ((self.header[0] & 0x3) << 25) | int.from_bytes(self.header[1:], "big") # 26 following bits 249 | self.check_crc() 250 | self.check_payload() 251 | 252 | def check_crc(self): 253 | from crc import Configuration, Calculator 254 | if self.crc_len == 2: 255 | config = Configuration( 256 | width=16, 257 | polynomial=0x8005, 258 | init_value=0xffff, 259 | final_xor_value=0xffff, 260 | reverse_input=True, 261 | reverse_output=True, 262 | ) 263 | else: 264 | config = Configuration( 265 | width=32, 266 | polynomial=0x4C11DB7, 267 | init_value=0xffff, 268 | final_xor_value=0xffff, 269 | reverse_input=False, 270 | reverse_output=True, 271 | ) 272 | calculator = Calculator(config) 273 | correct = calculator.verify(self.data[:-self.crc_len], int.from_bytes(self.crc, "little")) 274 | real_crc = calculator.checksum(self.data[:-self.crc_len]) 275 | if correct: 276 | print("VALID CRC {} !".format(self.crc)) 277 | else: 278 | print("@@ INVALID CRC @@ {} instead of {}".format(self.crc, hex(real_crc))) 279 | sys.exit(1) 280 | 281 | def check_payload(self): 282 | prev = None 283 | for d in self.payload: 284 | assert (((d & 0xf) + 1) & 0xf) == ((d & 0xf0) >> 4) 285 | if not prev and d != 0: 286 | prev = ((d & 0xf) - 1) << 4 287 | if prev: 288 | assert (((prev & 0xf0) >> 4) + 1) & 0xf == d & 0xf 289 | prev = d 290 | print("VALID payload!") 291 | -------------------------------------------------------------------------------- /software/libuartbone/uartbone_linux.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include // Contains file controls like O_RDWR 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include // Contains POSIX terminal control definitions 8 | #include 9 | 10 | #include 11 | #if !defined(LIBUSB_API_VERSION) || (LIBUSB_API_VERSION < 0x0100010A) 12 | #define libusb_init_context(a, b, c) libusb_init(a) 13 | #endif 14 | 15 | #include "uartbone.h" 16 | 17 | int get_reg_addr(FILE *csv, char *reg_name, uint32_t *res) { 18 | char *line = NULL; 19 | char *tok; 20 | size_t len = 0; 21 | bool csr_base_found = false; 22 | bool csr_reg_found = false; 23 | uint32_t csr_base = 0; 24 | uint32_t reg_addr = 0; 25 | ssize_t nread; 26 | size_t reg_name_len = strlen(reg_name); 27 | 28 | if (!reg_name) 29 | return -1; 30 | 31 | while ((nread = getline(&line, &len, csv)) != -1) { 32 | 33 | // Find the csd_base address 34 | if (strncmp(line, "csr_base", strlen("csr_base")) == 0) { 35 | strtok(line, ","); 36 | tok = strtok(NULL, ","); 37 | if (tok && (strncmp(tok, reg_name, reg_name_len) == 0)) { 38 | if (tok[reg_name_len] != '\0') 39 | continue; 40 | 41 | tok = strtok(NULL, ","); 42 | if (tok) { 43 | csr_base = strtol(tok, NULL, 0); 44 | csr_base_found = true; 45 | } 46 | } 47 | } 48 | 49 | // Find the register address 50 | if (strncmp(line, "csr_register", strlen("csr_register")) == 0) { 51 | strtok(line, ","); 52 | tok = strtok(NULL, ","); 53 | 54 | if (tok && reg_name && (strncmp(tok, reg_name, reg_name_len) == 0)) { 55 | if (tok[reg_name_len] != '\0') 56 | continue; 57 | 58 | tok = strtok(NULL, ","); 59 | if (tok) { 60 | reg_addr = strtol(tok, NULL, 0); 61 | csr_reg_found = true; 62 | } 63 | } 64 | } 65 | } 66 | 67 | if (csr_reg_found) 68 | *res = reg_addr; 69 | else if (csr_base_found) 70 | *res = csr_base; 71 | else 72 | return -1; 73 | 74 | return 0; 75 | } 76 | 77 | static speed_t baudrate_to_speed(unsigned int baudrate) { 78 | switch (baudrate) { 79 | case 9600: 80 | return B9600; 81 | case 19200: 82 | return B19200; 83 | case 38400: 84 | return B38400; 85 | case 57600: 86 | return B57600; 87 | case 115200: 88 | return B115200; 89 | case 230400: 90 | return B230400; 91 | case 460800: 92 | return B460800; 93 | case 500000: 94 | return B500000; 95 | case 576000: 96 | return B576000; 97 | case 921600: 98 | return B921600; 99 | case 1000000: 100 | return B1000000; 101 | case 1152000: 102 | return B1152000; 103 | case 1500000: 104 | return B1500000; 105 | case 2000000: 106 | return B2000000; 107 | case 2500000: 108 | return B2500000; 109 | case 3000000: 110 | return B3000000; 111 | case 3500000: 112 | return B3500000; 113 | case 4000000: 114 | return B4000000; 115 | default: 116 | return B0; 117 | } 118 | } 119 | 120 | void uart_write(struct uartbone_ctx *ctx, uint8_t *data, size_t len) { 121 | ssize_t ret; 122 | size_t cur_pos = 0; 123 | 124 | while (cur_pos != len) { 125 | ret = write(ctx->fd, data + cur_pos, len - cur_pos); 126 | if (ret == -1) { 127 | perror("write"); 128 | return; 129 | } 130 | cur_pos += ret; 131 | } 132 | } 133 | 134 | int uart_read(struct uartbone_ctx *ctx, uint8_t *res, size_t len) { 135 | ssize_t ret; 136 | size_t cur_pos = 0; 137 | 138 | while (cur_pos != len) { 139 | ret = read(ctx->fd, res + cur_pos, len - cur_pos); 140 | if (ret <= 0) { 141 | perror("read"); 142 | return ret; 143 | } 144 | cur_pos += ret; 145 | } 146 | return ret; 147 | } 148 | 149 | void usb_write(struct uartbone_ctx *ctx, uint8_t *data, size_t len) { 150 | uint8_t *usb_buffer; 151 | int ret; 152 | int transferred; 153 | size_t usb_tx_len = len + 3; 154 | int i; 155 | 156 | #ifdef DEBUG 157 | printf("doing write to endpoint %d of size %zu: \n", ctx->endpoint, len); 158 | for (i = 0; i < len; i++) 159 | printf("%02x ", data[i]); 160 | printf("\n"); 161 | #endif 162 | 163 | usb_buffer = malloc(usb_tx_len); 164 | usb_buffer[0] = 'U'; // uartbone code 165 | usb_buffer[1] = 'w'; // uart write cmd 166 | usb_buffer[2] = len; // uart payload total size 167 | memcpy(&usb_buffer[3], data, len); 168 | 169 | ret = libusb_bulk_transfer((libusb_device_handle *)ctx->usb_handle, ctx->endpoint, usb_buffer, usb_tx_len, &transferred, 5000); 170 | free(usb_buffer); 171 | if (ret) 172 | printf("libusb_bulk_transfer error %d: %s\n", ret, libusb_error_name(ret)); 173 | 174 | if (transferred != usb_tx_len) 175 | printf("error, libusb_bulk_transfer transferred %d instead of %zu\n", transferred, usb_tx_len); 176 | } 177 | 178 | int usb_read(struct uartbone_ctx *ctx, uint8_t *res, size_t len) { 179 | uint8_t usb_buffer[1024]; 180 | int ret; 181 | int transferred; 182 | uint8_t tmpbuf[3] = {'U', 'r', len}; 183 | 184 | #ifdef DEBUG 185 | printf("doing read to endpoint %d of size %zu\n", ctx->endpoint, len); 186 | printf("sending Read command\n"); 187 | #endif 188 | 189 | ret = libusb_bulk_transfer((libusb_device_handle *)ctx->usb_handle, ctx->endpoint, tmpbuf, sizeof(tmpbuf), &transferred, 5000); 190 | if (ret) { 191 | printf("libusb_bulk_transfer error %d: %s\n", ret, libusb_error_name(ret)); 192 | return -1; 193 | } 194 | 195 | if (transferred != sizeof(tmpbuf)) { 196 | printf("error, libusb_bulk_transfer transferred %d instead of %zu\n", transferred, sizeof(tmpbuf)); 197 | return -1; 198 | } 199 | 200 | #ifdef DEBUG 201 | printf("Reading EP1 IN buffer\n"); 202 | #endif 203 | 204 | ret = libusb_bulk_transfer((libusb_device_handle *)ctx->usb_handle, ctx->endpoint | LIBUSB_ENDPOINT_IN, usb_buffer, 1024, &transferred, 5000); 205 | if (ret) { 206 | printf("libusb_bulk_transfer error %d: %s\n", ret, libusb_error_name(ret)); 207 | return -1; 208 | } 209 | 210 | if (transferred != len) { 211 | printf("error, libusb_bulk_transfer transferred %d instead of %zu\n", transferred, len); 212 | return -1; 213 | } 214 | 215 | memcpy(res, usb_buffer, len); 216 | 217 | return 0; 218 | } 219 | 220 | struct uart_backend serial_backend = { 221 | .type = UNIX_UART, 222 | .read = uart_read, 223 | .write = uart_write 224 | }; 225 | 226 | struct uart_backend usb_backend = { 227 | .type = UNIX_USB, 228 | .read = usb_read, 229 | .write = usb_write 230 | }; 231 | 232 | /* 233 | * parse USB scheme 234 | * must be of the form usb://vendor_id:product_id[/endpoint] 235 | * vendor_id and product_id can be expressed in hex but must 236 | * have a 0x prefix. 237 | * 238 | * The /endpoint at the end is optional. Of omitted endpoint is 239 | * considered to be OUT 0. 240 | * return -1 upon parsing error, 0 if SUCCESS 241 | */ 242 | int parse_usb_scheme(char *scheme, uint16_t *vid, uint16_t *pid, uint8_t *endpoint) { 243 | long res; 244 | char *endptr; 245 | char *tmp; 246 | 247 | /* minimum size usb device scheme: usb://x:y => 9 */ 248 | if ((strlen(scheme) < strlen("usb://x:y")) || (strncmp(scheme, "usb://", strlen("usb://")) != 0)) 249 | return -1; 250 | 251 | scheme += strlen("usb://"); 252 | errno = 0; 253 | res = strtol(scheme, &endptr, 0); 254 | if ((errno != 0) || (res > UINT16_MAX) || (scheme == endptr) || (*endptr == '\0')) 255 | return -1; 256 | 257 | *vid = res; 258 | endptr++; // skip the ':' char 259 | tmp = endptr; 260 | errno = 0; 261 | res = strtol(endptr, &endptr, 0); 262 | if ((errno != 0) || (res > UINT16_MAX) || (tmp == endptr)) 263 | return -1; 264 | 265 | *pid = res; 266 | if (*endptr != '/') { 267 | *endpoint = 0; 268 | return 0; 269 | } 270 | 271 | endptr++; // skip the '/' char 272 | if (*endptr == '\0') { 273 | *endpoint = 0; 274 | return 0; 275 | } 276 | tmp = endptr; 277 | errno = 0; 278 | res = strtol(endptr, &endptr, 0); 279 | if ((errno != 0) || (res > UINT8_MAX) || (tmp == endptr)) 280 | return -1; 281 | *endpoint = res; 282 | 283 | return 0; 284 | } 285 | 286 | void uartbone_unix_init(struct uartbone_ctx *ctx, char *file, unsigned int baudrate, unsigned int addr_width) { 287 | struct termios tty; 288 | int fd; 289 | bool use_usb = false; 290 | 291 | ctx->error = 0; 292 | ctx->open = false; 293 | ctx->addr_width = addr_width; 294 | 295 | if (!strncmp(file, "usb://", 6)) { 296 | int ret; 297 | libusb_device_handle *handle; 298 | 299 | if ((strlen(file) != strlen("usb://")) || !ctx->usb_handle) { 300 | ret = parse_usb_scheme(file, &ctx->vendor_id, &ctx->product_id, &ctx->endpoint); 301 | if (ret) 302 | return; 303 | printf("Using USB port: %s\n", file); 304 | printf("vid: %04x pid: %04x endpoint: %02x\n", ctx->vendor_id, ctx->product_id, ctx->endpoint); 305 | ret = libusb_init_context(NULL, NULL, 0); 306 | if (ret) { 307 | ctx->error = ret; 308 | printf("libusb_init_context error %d: %s\n", ret, libusb_error_name(ret)); 309 | return; 310 | } 311 | 312 | handle = libusb_open_device_with_vid_pid(NULL, ctx->vendor_id, ctx->product_id); 313 | if (!handle) { 314 | ctx->error = -1; 315 | printf("libusb_open_device_with_vid_pid error: Device not found!\n"); 316 | return; 317 | } 318 | ctx->usb_handle = handle; 319 | 320 | ret = libusb_set_auto_detach_kernel_driver(handle, 1); 321 | if (ret) { 322 | ctx->error = -1; 323 | printf("libusb_set_auto_detach_kernel_driver error %d: %s\n", ret, libusb_error_name(ret)); 324 | return; 325 | } 326 | if (libusb_kernel_driver_active(handle, 0) == 1) { 327 | printf("Kernel driver active!\n"); 328 | } 329 | ret = libusb_claim_interface(handle, 0); 330 | if (ret) { 331 | ctx->error = ret; 332 | printf("libusb_claim_interface error %d: %s\n", ret, libusb_error_name(ret)); 333 | return; 334 | } 335 | } 336 | 337 | use_usb = true; 338 | ctx->uart = &usb_backend; 339 | ctx->open = true; 340 | return; 341 | } 342 | 343 | ctx->uart = &serial_backend; 344 | fd = open(file, O_RDWR); 345 | 346 | if (fd == -1) { 347 | printf("Error %d could not open uart %s: %s\n", errno, file, strerror(errno)); 348 | ctx->error = errno; 349 | return; 350 | } 351 | 352 | ctx->fd = fd; 353 | 354 | if (tcgetattr(fd, &tty) != 0) { 355 | printf("Error %d from tcgetattr: %s\n", errno, strerror(errno)); 356 | ctx->error = errno; 357 | close(fd); 358 | return; 359 | } 360 | 361 | tty.c_cflag &= ~PARENB; // Clear parity bit, disabling parity (most common) 362 | tty.c_cflag &= ~CSTOPB; // Clear stop field, only one stop bit used in communication (most common) 363 | tty.c_cflag &= ~CSIZE; // Clear all bits that set the data size 364 | tty.c_cflag |= CS8; // 8 bits per byte (most common) 365 | tty.c_cflag &= ~CRTSCTS; // Disable RTS/CTS hardware flow control (most common) 366 | tty.c_cflag |= CREAD | CLOCAL; // Turn on READ & ignore ctrl lines (CLOCAL = 1) 367 | 368 | tty.c_lflag &= ~ICANON; 369 | tty.c_lflag &= ~ECHO; // Disable echo 370 | tty.c_lflag &= ~ECHOE; // Disable erasure 371 | tty.c_lflag &= ~ECHONL; // Disable new-line echo 372 | tty.c_lflag &= ~ISIG; // Disable interpretation of INTR, QUIT and SUSP 373 | tty.c_iflag &= ~(IXON | IXOFF | IXANY); // Turn off s/w flow ctrl 374 | tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP|INLCR|IGNCR|ICRNL); // Disable any special handling of received bytes 375 | 376 | tty.c_oflag &= ~OPOST; // Prevent special interpretation of output bytes (e.g. newline chars) 377 | tty.c_oflag &= ~ONLCR; // Prevent conversion of newline to carriage return/line feed 378 | 379 | tty.c_cc[VTIME] = 10; // Wait for up to 1s (10 deciseconds), returning as soon as any data is received. 380 | tty.c_cc[VMIN] = 0; 381 | 382 | // Set in/out baud rate 383 | cfsetispeed(&tty, baudrate_to_speed(baudrate)); 384 | cfsetospeed(&tty, baudrate_to_speed(baudrate)); 385 | 386 | // Save tty settings, also checking for error 387 | if (tcsetattr(fd, TCSANOW, &tty) != 0) { 388 | printf("Error %i from tcsetattr: %s\n", errno, strerror(errno)); 389 | ctx->error = errno; 390 | close(fd); 391 | return; 392 | } 393 | 394 | ctx->open = true; 395 | } 396 | -------------------------------------------------------------------------------- /hw/hydrasucrela/hydrasucrela.kicad_pro: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "3dviewports": [], 4 | "design_settings": { 5 | "defaults": { 6 | "apply_defaults_to_fp_fields": false, 7 | "apply_defaults_to_fp_shapes": false, 8 | "apply_defaults_to_fp_text": false, 9 | "board_outline_line_width": 0.05, 10 | "copper_line_width": 0.2, 11 | "copper_text_italic": false, 12 | "copper_text_size_h": 1.5, 13 | "copper_text_size_v": 1.5, 14 | "copper_text_thickness": 0.3, 15 | "copper_text_upright": false, 16 | "courtyard_line_width": 0.05, 17 | "dimension_precision": 4, 18 | "dimension_units": 3, 19 | "dimensions": { 20 | "arrow_length": 1270000, 21 | "extension_offset": 500000, 22 | "keep_text_aligned": true, 23 | "suppress_zeroes": false, 24 | "text_position": 0, 25 | "units_format": 1 26 | }, 27 | "fab_line_width": 0.1, 28 | "fab_text_italic": false, 29 | "fab_text_size_h": 1.0, 30 | "fab_text_size_v": 1.0, 31 | "fab_text_thickness": 0.15, 32 | "fab_text_upright": false, 33 | "other_line_width": 0.1, 34 | "other_text_italic": false, 35 | "other_text_size_h": 1.0, 36 | "other_text_size_v": 1.0, 37 | "other_text_thickness": 0.15, 38 | "other_text_upright": false, 39 | "pads": { 40 | "drill": 2.02, 41 | "height": 1.7, 42 | "width": 1.7 43 | }, 44 | "silk_line_width": 0.1, 45 | "silk_text_italic": false, 46 | "silk_text_size_h": 1.0, 47 | "silk_text_size_v": 1.0, 48 | "silk_text_thickness": 0.1, 49 | "silk_text_upright": false, 50 | "zones": { 51 | "min_clearance": 0.1 52 | } 53 | }, 54 | "diff_pair_dimensions": [ 55 | { 56 | "gap": 0.0, 57 | "via_gap": 0.0, 58 | "width": 0.0 59 | } 60 | ], 61 | "drc_exclusions": [], 62 | "meta": { 63 | "version": 2 64 | }, 65 | "rule_severities": { 66 | "annular_width": "error", 67 | "clearance": "error", 68 | "connection_width": "warning", 69 | "copper_edge_clearance": "error", 70 | "copper_sliver": "warning", 71 | "courtyards_overlap": "error", 72 | "diff_pair_gap_out_of_range": "error", 73 | "diff_pair_uncoupled_length_too_long": "error", 74 | "drill_out_of_range": "error", 75 | "duplicate_footprints": "warning", 76 | "extra_footprint": "warning", 77 | "footprint": "error", 78 | "footprint_symbol_mismatch": "warning", 79 | "footprint_type_mismatch": "ignore", 80 | "hole_clearance": "error", 81 | "hole_near_hole": "error", 82 | "holes_co_located": "warning", 83 | "invalid_outline": "error", 84 | "isolated_copper": "warning", 85 | "item_on_disabled_layer": "error", 86 | "items_not_allowed": "error", 87 | "length_out_of_range": "error", 88 | "lib_footprint_issues": "warning", 89 | "lib_footprint_mismatch": "warning", 90 | "malformed_courtyard": "error", 91 | "microvia_drill_out_of_range": "error", 92 | "missing_courtyard": "ignore", 93 | "missing_footprint": "warning", 94 | "net_conflict": "warning", 95 | "npth_inside_courtyard": "ignore", 96 | "padstack": "warning", 97 | "pth_inside_courtyard": "ignore", 98 | "shorting_items": "error", 99 | "silk_edge_clearance": "warning", 100 | "silk_over_copper": "warning", 101 | "silk_overlap": "warning", 102 | "skew_out_of_range": "error", 103 | "solder_mask_bridge": "error", 104 | "starved_thermal": "error", 105 | "text_height": "warning", 106 | "text_thickness": "warning", 107 | "through_hole_pad_without_hole": "error", 108 | "too_many_vias": "error", 109 | "track_dangling": "warning", 110 | "track_width": "error", 111 | "tracks_crossing": "error", 112 | "unconnected_items": "error", 113 | "unresolved_variable": "error", 114 | "via_dangling": "warning", 115 | "zones_intersect": "error" 116 | }, 117 | "rules": { 118 | "max_error": 0.005, 119 | "min_clearance": 0.09, 120 | "min_connection": 0.0, 121 | "min_copper_edge_clearance": 0.5, 122 | "min_hole_clearance": 0.1, 123 | "min_hole_to_hole": 0.25, 124 | "min_microvia_diameter": 0.2, 125 | "min_microvia_drill": 0.1, 126 | "min_resolved_spokes": 2, 127 | "min_silk_clearance": 0.0, 128 | "min_text_height": 0.8, 129 | "min_text_thickness": 0.08, 130 | "min_through_hole_diameter": 0.3, 131 | "min_track_width": 0.09, 132 | "min_via_annular_width": 0.0, 133 | "min_via_diameter": 0.5, 134 | "solder_mask_to_copper_clearance": 0.005, 135 | "use_height_for_length_calcs": true 136 | }, 137 | "teardrop_options": [ 138 | { 139 | "td_onpadsmd": true, 140 | "td_onroundshapesonly": false, 141 | "td_ontrackend": false, 142 | "td_onviapad": true 143 | } 144 | ], 145 | "teardrop_parameters": [ 146 | { 147 | "td_allow_use_two_tracks": true, 148 | "td_curve_segcount": 0, 149 | "td_height_ratio": 1.0, 150 | "td_length_ratio": 0.5, 151 | "td_maxheight": 2.0, 152 | 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