├── README ├── examples ├── instruction-decoder │ ├── Makefile │ ├── genram.c │ ├── instruction_decode.v │ ├── instruction_fetch.v │ ├── memory_controller.v │ ├── pipeline.v │ ├── ram.v │ └── top.v ├── instruction-fetcher │ ├── Makefile │ ├── genram.c │ ├── instruction_fetch.v │ ├── memory_controller.v │ ├── pipeline.v │ ├── ram.v │ └── top.v ├── memory-controller │ ├── Makefile │ ├── genram.c │ ├── memory_controller.v │ ├── ram.v │ └── top.v └── pipeline │ ├── Makefile │ ├── pipeline.v │ ├── stage_A.v │ ├── stage_B.v │ ├── stage_C.v │ └── top.v └── src ├── Makefile ├── d-cache.v ├── genram.c ├── i-cache.v ├── instruction_decode.v ├── instruction_execute.v ├── instruction_fetch.v ├── memory_controller.v ├── pipeline.v ├── ram.v ├── ram0.data ├── ram1.data ├── ram2.data ├── ram3.data └── top.v /README: -------------------------------------------------------------------------------- 1 | Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes. 2 | The primary goal is to be binary compatible with non-FPU MIPS32 architecture 3 | First release should be binary compatible with MIPS I architecture which is a subset of MIPS32. 4 | 5 | A few examples are using 8-bit wide registers and data-path. 6 | 7 | License of everything in this git repo : BSD 8 | 9 | Content : 10 | 11 | examples/pipeline : 3-stages pipeline implementation example, just a skeleton. 12 | examples/memory-controller : simple SRAM memory-controller, acts like a Round-Robin scheduler for memory accesses. 13 | examples/instruction-fetcher : a 1-stage pipeline featuring previous pipeline and memory-controller in order to fetch instructions from SRAM. 14 | examples/instruction-decoder : a 2-stages pipeline featuring previous pipeline, memory-controller and instruction fetcher in order to fetch, decode and execute 32 bits MIPS I instructions. 15 | The previous directory is a draft and a work in progress of a 32 bits MIPS I binary compatible softcore. 16 | -------------------------------------------------------------------------------- /examples/instruction-decoder/Makefile: -------------------------------------------------------------------------------- 1 | all: top ram0.data ram1.data ram2.data ram3.data 2 | 3 | run: all 4 | vvp top 5 | 6 | top: top.v pipeline.v instruction_fetch.v ram.v memory_controller.v instruction_decode.v 7 | iverilog -o $@ $^ 8 | 9 | %.data: genram 10 | ./genram 11 | chmod 640 ram*.data 12 | 13 | genram: genram.c 14 | $(CC) $(CFLAGS) $^ -o $@ 15 | 16 | clean: 17 | $(RM) -rf top genram 18 | 19 | top.vcd: top 20 | $(MAKE) run 21 | 22 | wave: top.vcd 23 | gtkwave top.vcd 24 | 25 | .PHONY: all clean wave 26 | -------------------------------------------------------------------------------- /examples/instruction-decoder/genram.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | int ram0, ram1, ram2, ram3; 7 | unsigned int max_temp = 1024; 8 | 9 | void write_to_ram(const char *op) { 10 | write(ram3, op, sizeof(const char)*2); 11 | write(ram3, "\n", sizeof(char)); 12 | 13 | write(ram2, op + sizeof(const char) * 2, sizeof(const char)*2); 14 | write(ram2, "\n", sizeof(char)); 15 | 16 | write(ram1, op + sizeof(const char) * 4, sizeof(const char)*2); 17 | write(ram1, "\n", sizeof(char)); 18 | 19 | write(ram0, op + sizeof(const char) * 6, sizeof(const char)*2); 20 | write(ram0, "\n", sizeof(char)); 21 | max_temp--; 22 | } 23 | 24 | int main(void) { 25 | 26 | unsigned int i = 0; 27 | unsigned int max; 28 | mode_t mode = S_IWGRP | S_IWOTH; 29 | umask(mode); 30 | 31 | ram0 = open("ram0.data", O_WRONLY | O_CREAT); 32 | ram1 = open("ram1.data", O_WRONLY | O_CREAT); 33 | ram2 = open("ram2.data", O_WRONLY | O_CREAT); 34 | ram3 = open("ram3.data", O_WRONLY | O_CREAT); 35 | 36 | write_to_ram("00430820"); 37 | write_to_ram("00431020"); 38 | write_to_ram("00221820"); 39 | write_to_ram("8C050014"); 40 | write_to_ram("AAAAAAAA"); 41 | write_to_ram("BBBBBBBB"); 42 | 43 | max = max_temp; 44 | for (i = 0 ; i < max ; ++i) 45 | write_to_ram("00000000"); 46 | 47 | close(ram0); 48 | close(ram1); 49 | close(ram2); 50 | close(ram3); 51 | 52 | return EXIT_SUCCESS; 53 | } 54 | -------------------------------------------------------------------------------- /examples/instruction-decoder/instruction_decode.v: -------------------------------------------------------------------------------- 1 | module instruction_decoder( 2 | input clk, 3 | input reset, 4 | /* Data Out Ready */ 5 | output DOR, 6 | /* Data In Ready */ 7 | input DIR, 8 | input ack_from_next, 9 | output ack_prev, 10 | input [31:0] data_in, 11 | output [31:0] data_out, 12 | 13 | output [31:0] mem_di, 14 | output mem_en, 15 | output [3:0] mem_bank_select, 16 | output [9:0] mem_addr, 17 | output mem_we, 18 | input [31:0] mem_do, 19 | input mem_do_ack 20 | ); 21 | 22 | /* values for the Finite State Machine of the decoder and executer */ 23 | parameter IDLE = 7'd0; 24 | parameter WAITING_ACK = 7'd1; 25 | parameter FETCH_REGISTERS = 7'd2; 26 | parameter INST_ADD = 7'd3; 27 | parameter INST_ADDU = 7'd4; 28 | parameter INST_SUB = 7'd5; 29 | parameter INST_ADDI = 7'd6; 30 | parameter INST_SUBU = 7'd7; 31 | parameter INST_AND = 7'd8; 32 | parameter INST_OR = 7'd9; 33 | parameter INST_XOR = 7'd10; 34 | parameter INST_NOR = 7'd11; 35 | parameter INST_SLT = 7'd12; 36 | parameter INST_SLL = 7'd13; 37 | parameter INST_SRL = 7'd14; 38 | parameter INST_SRA = 7'd15; 39 | parameter INST_LD = 7'd16; 40 | parameter FETCH_FROM_MEM = 7'd17; 41 | parameter FETCH_FROM_MEM_WAIT_ACK = 7'd18; 42 | parameter STORE_TO_MEM = 7'd19; 43 | parameter STORE_TO_MEM_WAIT_ACK = 7'd20; 44 | parameter WRITE_BACK = 7'd21; 45 | 46 | reg [6:0] state = IDLE; 47 | 48 | parameter INST_TYPE_R = 2'd0; 49 | parameter INST_TYPE_I = 2'd1; 50 | parameter INST_TYPE_J = 2'd2; 51 | 52 | reg [1:0] instruction_type = INST_TYPE_R; 53 | 54 | reg [31:0] data_out_reg = 32'd0; 55 | reg DOR_reg = 0; 56 | reg ack_prev_reg = 0; 57 | reg [31:0] instruction; 58 | reg [6:0] instruction_state; 59 | reg memory_load; 60 | reg signed_load; 61 | reg [3:0] access_width; 62 | reg [31:0] D, S, T; /* registers for instruction execution */ 63 | reg [15:0] C; /* 16-bits immediate value */ 64 | reg [15:0] address; 65 | 66 | reg [9:0] mem_addr_reg; 67 | reg mem_we_reg; 68 | reg mem_en_reg; 69 | reg [31:0] mem_di_reg; 70 | reg [3:0] mem_bank_select_reg; 71 | 72 | assign mem_addr = mem_addr_reg; 73 | assign mem_di = mem_di_reg; 74 | assign mem_we = mem_we_reg; 75 | assign mem_en = mem_en_reg; 76 | assign mem_bank_select = mem_bank_select_reg; 77 | 78 | assign data_out = data_out_reg; 79 | assign DOR = DOR_reg; 80 | assign ack_prev = ack_prev_reg; 81 | 82 | /* The MIPS32 registers */ 83 | reg [31:0] REG_AT = 32'd0, 84 | REG_V0 = 32'd0, 85 | REG_V1 = 32'd0, 86 | REG_A0 = 32'd0, 87 | REG_A1 = 32'd0, 88 | REG_A2 = 32'd0, 89 | REG_A3 = 32'd0, 90 | REG_T0 = 32'd0, 91 | REG_T1 = 32'd0, 92 | REG_T2 = 32'd0, 93 | REG_T3 = 32'd0, 94 | REG_T4 = 32'd0, 95 | REG_T5 = 32'd0, 96 | REG_T6 = 32'd0, 97 | REG_T7 = 32'd0, 98 | REG_S0 = 32'd0, 99 | REG_S1 = 32'd0, 100 | REG_S2 = 32'd0, 101 | REG_S3 = 32'd0, 102 | REG_S4 = 32'd0, 103 | REG_S5 = 32'd0, 104 | REG_S6 = 32'd0, 105 | REG_S7 = 32'd0, 106 | REG_T8 = 32'd0, 107 | REG_T9 = 32'd0, 108 | REG_K0 = 32'd0, 109 | REG_K1 = 32'd0, 110 | REG_GP = 32'd0, 111 | REG_SP = 32'd0, 112 | REG_FP = 32'd0, 113 | REG_RA = 32'd0; 114 | 115 | /* The decoder and executer FSM (Finite State Machine) */ 116 | always @(posedge clk) 117 | begin 118 | if (reset) 119 | begin 120 | state <= IDLE; 121 | data_out_reg <= 0; 122 | DOR_reg <= 0; 123 | ack_prev_reg <= 0; 124 | mem_addr_reg <= 10'd0; 125 | mem_di_reg <= 32'd0; 126 | mem_en_reg <= 0; 127 | mem_we_reg <= 0; 128 | signed_load <= 0; 129 | mem_bank_select_reg <= 4'b1111; 130 | end 131 | else 132 | begin 133 | case (state) 134 | 135 | IDLE: 136 | begin 137 | if (DIR) 138 | begin 139 | $display("instruction decoder receives input_data 0x%08X", data_in); 140 | ack_prev_reg <= 1; 141 | instruction <= data_in; 142 | if (data_in[31:26] == 6'd0) 143 | begin 144 | /* if instruction[31:27] == 000000 then it's a type R instruction */ 145 | case (data_in[5:0]) 146 | 147 | /* sll $d,$t,shamt*/ 148 | 6'd0: 149 | begin 150 | $display("We decode instruction : sll"); 151 | instruction_state <= INST_SLL; 152 | end 153 | 154 | /* srl $d,$t,shamt*/ 155 | 6'd2: 156 | begin 157 | $display("We decode instruction : srl"); 158 | instruction_state <= INST_SRL; 159 | end 160 | 161 | /* sra $d,$t,shamt*/ 162 | 6'd3: 163 | begin 164 | $display("We decode instruction : sra"); 165 | instruction_state <= INST_SRA; 166 | end 167 | 168 | /* add $d,$s,$t */ 169 | 6'h20: 170 | begin 171 | $display("We decode instruction : add"); 172 | instruction_state <= INST_ADD; 173 | end 174 | 175 | /* addu $d,$s,$t */ 176 | 6'h21: 177 | begin 178 | $display("We decode instruction : addu"); 179 | instruction_state <= INST_ADDU; 180 | end 181 | 182 | /* sub $d,$s,$t */ 183 | 6'h22: 184 | begin 185 | $display("We decode instruction : sub"); 186 | instruction_state <= INST_SUB; 187 | end 188 | 189 | /* subu $d,$s,$t */ 190 | 6'h23: 191 | begin 192 | $display("We decode instruction : subu"); 193 | instruction_state <= INST_SUBU; 194 | end 195 | 196 | /* and $d,$s,$t */ 197 | 6'h24: 198 | begin 199 | $display("We decode instruction : and"); 200 | instruction_state <= INST_AND; 201 | end 202 | 203 | /* or $d,$s,$t */ 204 | 6'h25: 205 | begin 206 | $display("We decode instruction : or"); 207 | instruction_state <= INST_OR; 208 | end 209 | 210 | /* xor $d,$s,$t */ 211 | 6'h26: 212 | begin 213 | $display("We decode instruction : xor"); 214 | instruction_state <= INST_XOR; 215 | end 216 | 217 | /* nor $d,$s,$t */ 218 | 6'h27: 219 | begin 220 | $display("We decode instruction : nor"); 221 | instruction_state <= INST_NOR; 222 | end 223 | 224 | /* slt $d,$s,$t */ 225 | 6'h2A: 226 | begin 227 | $display("We decode instruction : slt"); 228 | instruction_state <= INST_SLT; 229 | end 230 | 231 | endcase 232 | state <= FETCH_REGISTERS; 233 | instruction_type <= INST_TYPE_R; 234 | end 235 | else 236 | begin 237 | case (data_in[31:26]) 238 | /* 239 | * Most instructions here are type I except two type J. 240 | * since type J does not need to fetch any register, 241 | * let's flag every instruction as type I and process 242 | * type J instructions directly without going through the 243 | * FETCH_REGISTERS state of the FSM. 244 | */ 245 | 246 | /* ld $t,C($s) */ 247 | 6'h6: 248 | begin 249 | $display("We decode instruction : ld"); 250 | instruction_state <= INST_LD; 251 | memory_load <= 1; 252 | access_width <= 4'd8; 253 | signed_load <= 0; 254 | end 255 | 256 | /* addi $t,$s,C */ 257 | 6'h8: 258 | begin 259 | $display("We decode instruction : addi"); 260 | instruction_state <= INST_ADDI; 261 | signed_load <= 0; 262 | end 263 | 264 | /* lw $t,C($s) */ 265 | 6'h23: 266 | begin 267 | $display("We decode instruction : lw"); 268 | memory_load <= 1; 269 | access_width <= 4'd4; 270 | signed_load <= 0; 271 | end 272 | 273 | /* lh $t,C($s) */ 274 | 6'h21: 275 | begin 276 | $display("We decode instruction : lh"); 277 | memory_load <= 1; 278 | access_width <= 4'd2; 279 | signed_load <= 1; 280 | end 281 | 282 | /* lhu $t,C($s) */ 283 | 6'h21: 284 | begin 285 | $display("We decode instruction : lhu"); 286 | memory_load <= 1; 287 | access_width <= 4'd2; 288 | signed_load <= 0; 289 | end 290 | 291 | /* lb $t,C($s) */ 292 | // FIXME : This should be a SIGNED load 293 | 6'h20: 294 | begin 295 | $display("We decode instruction : lb"); 296 | memory_load <= 1; 297 | access_width <= 4'd1; 298 | signed_load <= 1; 299 | end 300 | 301 | /* lbu $t,C($s) */ 302 | 6'h24: 303 | begin 304 | $display("We decode instruction : lbu"); 305 | memory_load <= 1; 306 | access_width <= 4'd1; 307 | signed_load <= 0; 308 | end 309 | 310 | /* sw $t,C($s) */ 311 | 6'h2B: 312 | begin 313 | $display("We decode instruction : sw"); 314 | memory_load <= 0; 315 | access_width <= 4'd4; 316 | end 317 | 318 | /* sh $t,C($s) */ 319 | 6'h29: 320 | begin 321 | $display("We decode instruction : sh"); 322 | memory_load <= 0; 323 | access_width <= 4'd2; 324 | end 325 | 326 | /* sb $t,C($s) */ 327 | 6'h28: 328 | begin 329 | $display("We decode instruction : sb"); 330 | memory_load <= 0; 331 | access_width <= 4'd1; 332 | end 333 | endcase 334 | state <= FETCH_REGISTERS; 335 | instruction_type <= INST_TYPE_I; 336 | end 337 | end 338 | mem_we_reg <= 0; 339 | mem_en_reg <= 0; 340 | end 341 | 342 | FETCH_REGISTERS: 343 | begin 344 | case (instruction[25:21]) 345 | 346 | /* $zero (aka $0) is constant 0 */ 347 | 5'd0: S <= 32'd0; 348 | /* $at (aka $1) is assembler temporary */ 349 | 5'd1: S <= REG_AT; 350 | /* $v0 and $v1 (aka $2 an $3) are values for function returns and expression evaluation */ 351 | 5'd2: S <= REG_V0; 352 | 5'd3: S <= REG_V1; 353 | /* $a0 to $a3 (aka $4 to $7) are function argument registers */ 354 | 5'd4: S <= REG_A0; 355 | 5'd5: S <= REG_A1; 356 | 5'd6: S <= REG_A2; 357 | 5'd7: S <= REG_A3; 358 | /* $t0 to $t7 (aka $8 to $15) are temporary registers */ 359 | 5'd8: S <= REG_T0; 360 | 5'd9: S <= REG_T1; 361 | 5'd10: S <= REG_T2; 362 | 5'd11: S <= REG_T3; 363 | 5'd12: S <= REG_T4; 364 | 5'd13: S <= REG_T5; 365 | 5'd14: S <= REG_T6; 366 | 5'd15: S <= REG_T7; 367 | /* $s0 to $7 (aka $16 to $23) are saved temporary registers */ 368 | 5'd16: S <= REG_S0; 369 | 5'd17: S <= REG_S1; 370 | 5'd18: S <= REG_S2; 371 | 5'd19: S <= REG_S3; 372 | 5'd20: S <= REG_S4; 373 | 5'd21: S <= REG_S5; 374 | 5'd22: S <= REG_S6; 375 | 5'd23: S <= REG_S7; 376 | /* $t8 and $t9 (aka $24 and $25) are temporary registers */ 377 | 5'd24: S <= REG_T8; 378 | 5'd25: S <= REG_T9; 379 | /* $k0 and $k1 (aka $26 and $27) are reserved for OS kernel */ 380 | 5'd26: S <= REG_K0; 381 | 5'd27: S <= REG_K1; 382 | /* $gp (aka $28) is global pointer register */ 383 | 5'd28: S <= REG_GP; 384 | /* $sp (aka $29) is stack pointer register */ 385 | 5'd29: S <= REG_SP; 386 | /* $fp (aka $30) is frame pointer register */ 387 | 5'd30: S <= REG_FP; 388 | /* $ra (aka $31) is return address register */ 389 | 5'd31: S <= REG_RA; 390 | 391 | endcase 392 | 393 | case (instruction[20:16]) 394 | 395 | /* $zero (aka $0) is constant 0 */ 396 | 5'd0: T <= 32'd0; 397 | /* $at (aka $1) is assembler temporary */ 398 | 5'd1: T <= REG_AT; 399 | /* $v0 and $v1 (aka $2 an $3) are values for function returns and expression evaluation */ 400 | 5'd2: T <= REG_V0; 401 | 5'd3: T <= REG_V1; 402 | /* $a0 to $a3 (aka $4 to $7) are function argument registers */ 403 | 5'd4: T <= REG_A0; 404 | 5'd5: T <= REG_A1; 405 | 5'd6: T <= REG_A2; 406 | 5'd7: T <= REG_A3; 407 | /* $t0 to $t7 (aka $8 to $15) are temporary registers */ 408 | 5'd8: T <= REG_T0; 409 | 5'd9: T <= REG_T1; 410 | 5'd10: T <= REG_T2; 411 | 5'd11: T <= REG_T3; 412 | 5'd12: T <= REG_T4; 413 | 5'd13: T <= REG_T5; 414 | 5'd14: T <= REG_T6; 415 | 5'd15: T <= REG_T7; 416 | /* $s0 to $7 (aka $16 to $23) are saved temporary registers */ 417 | 5'd16: T <= REG_S0; 418 | 5'd17: T <= REG_S1; 419 | 5'd18: T <= REG_S2; 420 | 5'd19: T <= REG_S3; 421 | 5'd20: T <= REG_S4; 422 | 5'd21: T <= REG_S5; 423 | 5'd22: T <= REG_S6; 424 | 5'd23: T <= REG_S7; 425 | /* $t8 and $t9 (aka $24 and $25) are temporary registers */ 426 | 5'd24: T <= REG_T8; 427 | 5'd25: T <= REG_T9; 428 | /* $k0 and $k1 (aka $26 and $27) are reserved for OS kernel */ 429 | 5'd26: T <= REG_K0; 430 | 5'd27: T <= REG_K1; 431 | /* $gp (aka $28) is global pointer register */ 432 | 5'd28: T <= REG_GP; 433 | /* $sp (aka $29) is stack pointer register */ 434 | 5'd29: T <= REG_SP; 435 | /* $fp (aka $30) is frame pointer register */ 436 | 5'd30: T <= REG_FP; 437 | /* $ra (aka $31) is return address register */ 438 | 5'd31: T <= REG_RA; 439 | 440 | endcase 441 | 442 | case (instruction_type) 443 | INST_TYPE_R: 444 | begin 445 | state <= instruction_state; 446 | end 447 | 448 | INST_TYPE_I: 449 | begin 450 | if (memory_load) 451 | state <= FETCH_FROM_MEM; 452 | else 453 | begin 454 | state <= STORE_TO_MEM; 455 | end 456 | C <= instruction[15:0]; 457 | end 458 | 459 | INST_TYPE_J: 460 | begin 461 | state <= instruction_state; 462 | end 463 | 464 | endcase 465 | end 466 | 467 | FETCH_FROM_MEM: 468 | begin 469 | /* memory accesses are 4-bytes aligned */ 470 | mem_addr_reg <= { 2'd0, (S + C) >> 2 }; 471 | address <= S + C; 472 | mem_we_reg <= 0; 473 | mem_di_reg <= 32'd0; 474 | mem_en_reg <= 1; 475 | mem_bank_select_reg <= 4'b1111; 476 | $display("Fetching data from memory @ 0x%04X", (S + C)); 477 | state <= FETCH_FROM_MEM_WAIT_ACK; 478 | 479 | end 480 | 481 | STORE_TO_MEM: 482 | begin 483 | /* memory accesses are 4-bytes aligned */ 484 | mem_addr_reg <= { 2'd0, (S + C) >> 2 }; 485 | mem_we_reg <= 1; 486 | mem_di_reg <= T; 487 | mem_en_reg <= 1; 488 | $display("Storing data 0x%08X to memory @ 0x%04X", T, (S + C)); 489 | address <= S + C; 490 | state <= STORE_TO_MEM_WAIT_ACK; 491 | case ( S[1:0] ) 492 | 2'd0: 493 | begin 494 | case ( access_width ) 495 | 4'd1: mem_bank_select_reg <= 4'b1000; 496 | 4'd2: mem_bank_select_reg <= 4'b1100; 497 | 4'd4: mem_bank_select_reg <= 4'b1111; 498 | default: mem_bank_select_reg <= 4'd0; 499 | endcase 500 | end 501 | 2'd1: 502 | begin 503 | case ( access_width ) 504 | 4'd1: mem_bank_select_reg <= 4'b0100; 505 | default: mem_bank_select_reg <= 4'd0; 506 | endcase 507 | end 508 | 2'd2: 509 | begin 510 | case ( access_width ) 511 | 4'd1: mem_bank_select_reg <= 4'b0010; 512 | 4'd2: mem_bank_select_reg <= 4'b0011; 513 | default: mem_bank_select_reg <= 4'd0; 514 | endcase 515 | end 516 | 2'd3: 517 | begin 518 | case ( access_width ) 519 | 4'd1: mem_bank_select_reg <= 4'b0001; 520 | default: mem_bank_select_reg <= 4'd0; 521 | endcase 522 | end 523 | endcase 524 | 525 | end 526 | 527 | FETCH_FROM_MEM_WAIT_ACK: 528 | begin 529 | /* Here I save the result in D but it means T 530 | * I just wanted to avoid duplicating the 531 | * WRITE_BACK code for T register */ 532 | 533 | if (mem_do_ack) 534 | begin 535 | case (address[1:0]) 536 | 2'd0: 537 | begin 538 | case (access_width) 539 | 4'd1: D <= { signed_load ? {24{mem_do[31]}} : 24'd0, mem_do[31:24] }; 540 | 4'd2: D <= { signed_load ? {16{mem_do[31]}} : 16'd0, mem_do[31:16] }; 541 | 4'd4: D <= mem_do; 542 | endcase 543 | end 544 | 2'd1: D <= { signed_load ? {24{ mem_do[25]}} : 24'd0, mem_do[25:16] }; 545 | 2'd2: 546 | begin 547 | case (access_width) 548 | 4'd1: D <= { signed_load ? {24{mem_do[15]}} : 24'd0, mem_do[15:8] }; 549 | 4'd2: D <= { signed_load ? {16{mem_do[15]}} : 16'd0, mem_do[15:0] }; 550 | endcase 551 | end 552 | 2'd3: D <= { signed_load ? {24{mem_do[7]}} : 24'd0, mem_do[7:0] }; 553 | endcase 554 | $display("Fetched 0x%08X from memory @ 0x%04X", mem_do, address); 555 | mem_en_reg <= 0; 556 | mem_we_reg <= 0; 557 | mem_addr_reg <= 10'd0; 558 | state <= WRITE_BACK; 559 | end 560 | else 561 | begin 562 | state <= FETCH_FROM_MEM_WAIT_ACK; 563 | end 564 | end 565 | 566 | STORE_TO_MEM_WAIT_ACK: 567 | begin 568 | if (mem_do_ack) 569 | begin 570 | $display("Stored 0x%08X to memory @ 0x%04X", mem_do, address); 571 | mem_en_reg <= 0; 572 | mem_we_reg <= 0; 573 | mem_addr_reg <= 10'd0; 574 | state <= WRITE_BACK; 575 | end 576 | else 577 | begin 578 | state <= STORE_TO_MEM_WAIT_ACK; 579 | end 580 | end 581 | 582 | INST_ADD: 583 | begin 584 | $display("We execute add %d, %d", S, T); 585 | /* We need to execute a trap on overflow */ 586 | // FIXME : TRAP ON OVERFLOW NOT IMPLEMENTED YET 587 | D <= S + T; 588 | state <= WRITE_BACK; 589 | end 590 | 591 | INST_ADDU: 592 | begin 593 | $display("We execute addu %d, %d", S, T); 594 | D <= S + T; 595 | state <= WRITE_BACK; 596 | end 597 | 598 | INST_SUB: 599 | begin 600 | $display("We execute sub %d, %d", S, T); 601 | /* We need to execute a trap on overflow */ 602 | // FIXME : TRAP ON OVERFLOW NOT IMPLEMENTED YET 603 | D <= S + (~T) + 1; 604 | state <= WRITE_BACK; 605 | end 606 | 607 | INST_SUBU: 608 | begin 609 | $display("We execute subu %d, %d", S, T); 610 | D <= S + (~T) + 1; 611 | state <= WRITE_BACK; 612 | end 613 | 614 | INST_AND: 615 | begin 616 | $display("We execute and %d, %d", S, T); 617 | D <= S & T; 618 | state <= WRITE_BACK; 619 | end 620 | 621 | INST_OR: 622 | begin 623 | $display("We execute or %d, %d", S, T); 624 | D <= S | T; 625 | state <= WRITE_BACK; 626 | end 627 | 628 | INST_XOR: 629 | begin 630 | $display("We execute xor %d, %d", S, T); 631 | D <= S ^ T; 632 | state <= WRITE_BACK; 633 | end 634 | 635 | INST_NOR: 636 | begin 637 | $display("We execute nor %d, %d", S, T); 638 | D <= ~ (S | T); 639 | state <= WRITE_BACK; 640 | end 641 | 642 | INST_SLT: 643 | begin 644 | $display("We execute slt %d, %d", S, T); 645 | 646 | if (S < T) 647 | D <= 1; 648 | else 649 | D <= 0; 650 | 651 | state <= WRITE_BACK; 652 | end 653 | 654 | INST_SLL: 655 | begin 656 | $display("We execute sll $d, %d, %d", T, instruction[10:6]); 657 | D <= T << instruction[10:6]; 658 | state <= WRITE_BACK; 659 | end 660 | 661 | // FIXME : check SRL for compatibility with MIPS32 662 | INST_SRL: 663 | begin 664 | $display("We execute srl $d, %d, %d", T, instruction[10:6]); 665 | D <= T >> instruction[10:6]; 666 | state <= WRITE_BACK; 667 | end 668 | 669 | INST_SRA: 670 | begin 671 | $display("We execute sra $d, %d, %d", T, instruction[10:6]); 672 | D <= ~(~T >> instruction[10:6]); 673 | state <= WRITE_BACK; 674 | end 675 | 676 | WRITE_BACK: 677 | begin 678 | $display("We write back %d to %s", D, (instruction_type == INST_TYPE_R) ? "D" : "T"); 679 | case( (instruction_type == INST_TYPE_R) ? instruction[15:11] : instruction[20:16]) 680 | /* $zero (aka $0) is constant 0 */ 681 | 5'd0: $display("wtf ?"); 682 | /* $at (aka $1) is assembler temporary */ 683 | 5'd1: REG_AT <= D; 684 | /* $v0 and $v1 (aka $2 an $3) are values for function returns and expression evaluation */ 685 | 5'd2: REG_V0 <= D; 686 | 5'd3: REG_V1 <= D; 687 | /* $a0 to $a3 (aka $4 to $7) are function argument registers */ 688 | 5'd4: REG_A0 <= D; 689 | 5'd5: REG_A1 <= D; 690 | 5'd6: REG_A2 <= D; 691 | 5'd7: REG_A3 <= D; 692 | /* $t0 to $t7 (aka $8 to $15) are temporary registers */ 693 | 5'd8: REG_T0 <= D; 694 | 5'd9: REG_T1 <= D; 695 | 5'd10: REG_T2 <= D; 696 | 5'd11: REG_T3 <= D; 697 | 5'd12: REG_T4 <= D; 698 | 5'd13: REG_T5 <= D; 699 | 5'd14: REG_T6 <= D; 700 | 5'd15: REG_T7 <= D; 701 | /* $s0 to $7 (aka $16 to $23) are saved temporary registers */ 702 | 5'd16: REG_S0 <= D; 703 | 5'd17: REG_S1 <= D; 704 | 5'd18: REG_S2 <= D; 705 | 5'd19: REG_S3 <= D; 706 | 5'd20: REG_S4 <= D; 707 | 5'd21: REG_S5 <= D; 708 | 5'd22: REG_S6 <= D; 709 | 5'd23: REG_S7 <= D; 710 | /* $t8 and $t9 (aka $24 and $25) are temporary registers */ 711 | 5'd24: REG_T8 <= D; 712 | 5'd25: REG_T9 <= D; 713 | /* $k0 and $k1 (aka $26 and $27) are reserved for OS kernel */ 714 | 5'd26: REG_K0 <= D; 715 | 5'd27: REG_K1 <= D; 716 | /* $gp (aka $28) is global pointer register */ 717 | 5'd28: REG_GP <= D; 718 | /* $sp (aka $29) is stack pointer register */ 719 | 5'd29: REG_SP <= D; 720 | /* $fp (aka $30) is frame pointer register */ 721 | 5'd30: REG_FP <= D; 722 | /* $ra (aka $31) is return address register */ 723 | 5'd31: REG_RA <= D; 724 | 725 | endcase 726 | data_out_reg <= D; 727 | DOR_reg <= 1; 728 | state <= WAITING_ACK; 729 | end 730 | 731 | WAITING_ACK: 732 | begin 733 | if (ack_from_next) 734 | begin 735 | $display("instruction decoder got ACK form next stage"); 736 | DOR_reg <= 0; 737 | state <= IDLE; 738 | end 739 | else 740 | begin 741 | state <= WAITING_ACK; 742 | DOR_reg <= 1; 743 | end 744 | ack_prev_reg <= 0; 745 | end 746 | 747 | endcase 748 | end 749 | end 750 | 751 | endmodule 752 | -------------------------------------------------------------------------------- /examples/instruction-decoder/instruction_fetch.v: -------------------------------------------------------------------------------- 1 | module instruction_fetch( 2 | input clk, 3 | input reset, 4 | output DOR, 5 | input DIR, 6 | input ack_from_next, 7 | output ack_prev, 8 | input [31:0] data_in, 9 | output [31:0] data_out, 10 | 11 | output [31:0] mem_di, 12 | output mem_en, 13 | output [9:0] mem_addr, 14 | input [31:0] mem_do, 15 | input mem_do_ack 16 | ); 17 | 18 | parameter IDLE = 2'd0; 19 | parameter WAITING_ACK_FROM_MEMORY_CONTROLLER = 2'd1; 20 | parameter WAITING_ACK_FROM_NEXT_STAGE = 2'd2; 21 | 22 | reg [1:0] state = IDLE; 23 | reg [31:0] data_out_reg = 32'd0; 24 | reg DOR_reg = 0; 25 | reg ack_prev_reg = 0; 26 | reg [31:0] data_in_buffer; 27 | reg [9:0] mem_addr_reg = 9'd0; 28 | reg mem_en_reg = 0; 29 | reg [31:0] data_in_cached = 32'd0; 30 | 31 | 32 | assign data_out = data_out_reg; 33 | assign DOR = DOR_reg; 34 | assign ack_prev = ack_prev_reg; 35 | assign mem_addr = mem_addr_reg; 36 | assign mem_en = mem_en_reg; 37 | assign mem_di = 32'd0; 38 | 39 | always @(posedge clk) 40 | begin 41 | if (reset) 42 | begin 43 | state <= IDLE; 44 | data_out_reg <= 0; 45 | DOR_reg <= 0; 46 | ack_prev_reg <= 0; 47 | mem_addr_reg <= 9'd0; 48 | mem_en_reg <= 0; 49 | data_in_cached <= 32'd0; 50 | end 51 | else 52 | begin 53 | case (state) 54 | 55 | IDLE: 56 | begin 57 | if (DIR) 58 | begin 59 | $display("Fetching opcode @ PC = %02X", data_in); 60 | state <= WAITING_ACK_FROM_MEMORY_CONTROLLER; 61 | ack_prev_reg <= 1; 62 | mem_en_reg <= 1; 63 | DOR_reg <= 0; 64 | data_in_cached <= data_in; 65 | mem_addr_reg <= { 2'd0, data_in[9:2] }; 66 | end 67 | else 68 | begin 69 | mem_en_reg <= 0; 70 | DOR_reg <= 0; 71 | mem_addr_reg <= data_in; 72 | end 73 | end 74 | 75 | WAITING_ACK_FROM_MEMORY_CONTROLLER: 76 | begin 77 | if (mem_do_ack) 78 | begin 79 | $display("instruction fetcher fetched 0x%02X from PC = 0x%02X", mem_do, data_in_cached); 80 | data_out_reg <= mem_do; 81 | DOR_reg <= 1; 82 | mem_en_reg <= 0; 83 | state <= WAITING_ACK_FROM_NEXT_STAGE; 84 | end 85 | else 86 | begin 87 | state <= WAITING_ACK_FROM_MEMORY_CONTROLLER; 88 | DOR_reg <= 0; 89 | mem_en_reg <= 1; 90 | end 91 | ack_prev_reg <= 0; 92 | end 93 | 94 | WAITING_ACK_FROM_NEXT_STAGE: 95 | begin 96 | if (ack_from_next) 97 | begin 98 | $display("instruction_fetcher got ACK from next stage"); 99 | DOR_reg <= 0; 100 | mem_en_reg <= 0; 101 | state <= IDLE; 102 | end 103 | else 104 | begin 105 | DOR_reg <= 1; 106 | mem_en_reg <= 0; 107 | state <= WAITING_ACK_FROM_NEXT_STAGE; 108 | end 109 | end 110 | 111 | endcase 112 | end 113 | end 114 | 115 | endmodule 116 | -------------------------------------------------------------------------------- /examples/instruction-decoder/memory_controller.v: -------------------------------------------------------------------------------- 1 | module memory_controller(clk, 2 | reset, 3 | devices_burst_en, 4 | devices_mem_en, 5 | device_1_mem_addr, 6 | device_2_mem_addr, 7 | device_3_mem_addr, 8 | device_1_mem_di, 9 | device_2_mem_di, 10 | device_3_mem_di, 11 | device_1_bank_select, 12 | device_2_bank_select, 13 | device_3_bank_select, 14 | devices_mem_we, 15 | devices_do_ack, 16 | mem_do); 17 | 18 | input clk; 19 | input reset; 20 | input [2:0] devices_burst_en; 21 | input [2:0] devices_mem_en; 22 | input [9:0] device_1_mem_addr; 23 | input [9:0] device_2_mem_addr; 24 | input [9:0] device_3_mem_addr; 25 | input [31:0] device_1_mem_di; 26 | input [31:0] device_2_mem_di; 27 | input [31:0] device_3_mem_di; 28 | input [3:0] device_1_bank_select; 29 | input [3:0] device_2_bank_select; 30 | input [3:0] device_3_bank_select; 31 | input [2:0] devices_mem_we; 32 | output [2:0] devices_do_ack; 33 | output [31:0] mem_do; 34 | 35 | parameter DEVICE_1 = 3'd0; 36 | parameter DEVICE_2 = 3'd1; 37 | parameter DEVICE_3 = 3'd2; 38 | parameter NO_ONE = 3'b111; 39 | 40 | reg mem_enable = 0; 41 | reg [9:0] mem_addr = 10'd0; 42 | reg [31:0] mem_di = 32'd0; 43 | reg [2:0] current_slave = NO_ONE; 44 | reg [2:0] previous_slave = NO_ONE; 45 | reg mem_we = 0; 46 | reg [2:0] devices_do_ack = 3'd0; 47 | reg [3:0] mem_bank_select = 4'b1111; 48 | 49 | always @(posedge clk) 50 | begin 51 | if (reset) 52 | begin 53 | current_slave <= NO_ONE; 54 | end 55 | else 56 | begin 57 | case (current_slave) 58 | NO_ONE: 59 | begin 60 | if (devices_mem_en[0] && previous_slave != DEVICE_1) 61 | begin 62 | current_slave <= DEVICE_1; 63 | mem_bank_select <= device_1_bank_select; 64 | mem_addr <= device_1_mem_addr; 65 | mem_di <= device_1_mem_di; 66 | mem_we <= devices_mem_we[0]; 67 | end 68 | else if (devices_mem_en[1] && previous_slave != DEVICE_2) 69 | begin 70 | current_slave <= DEVICE_2; 71 | mem_bank_select <= device_2_bank_select; 72 | mem_addr <= device_2_mem_addr; 73 | mem_di <= device_2_mem_di; 74 | mem_we <= devices_mem_we[1]; 75 | end 76 | else if (devices_mem_en[2] && previous_slave != DEVICE_3) 77 | begin 78 | current_slave <= DEVICE_3; 79 | mem_bank_select <= device_3_bank_select; 80 | mem_addr <= device_3_mem_addr; 81 | mem_di <= device_3_mem_di; 82 | mem_we <= devices_mem_we[2]; 83 | end 84 | else 85 | begin 86 | current_slave <= NO_ONE; 87 | mem_bank_select <= 4'd0; 88 | mem_addr <= 10'd0; 89 | mem_di <= 32'd0; 90 | mem_we <= 0; 91 | end 92 | previous_slave <= NO_ONE; 93 | devices_do_ack <= 3'b000; 94 | end 95 | 96 | DEVICE_1: 97 | begin 98 | if (devices_mem_en[1]) 99 | begin 100 | current_slave <= DEVICE_2; 101 | mem_bank_select <= device_2_bank_select; 102 | mem_addr <= device_2_mem_addr; 103 | mem_di <= device_2_mem_di; 104 | mem_we <= devices_mem_we[1]; 105 | end 106 | else if (devices_mem_en[2]) 107 | begin 108 | current_slave <= DEVICE_3; 109 | mem_bank_select <= device_3_bank_select; 110 | mem_addr <= device_3_mem_addr; 111 | mem_di <= device_3_mem_di; 112 | mem_we <= devices_mem_we[2]; 113 | end 114 | else 115 | begin 116 | if (devices_burst_en[0] && devices_mem_en[0]) 117 | begin 118 | devices_do_ack <= 3'b001; 119 | mem_addr <= device_1_mem_addr + 4; 120 | mem_di <= device_1_mem_di; 121 | end 122 | else 123 | begin 124 | current_slave <= NO_ONE; 125 | mem_bank_select <= 4'd0; 126 | mem_addr <= 10'd0; 127 | mem_di <= 32'd0; 128 | mem_we <= 0; 129 | end 130 | end 131 | devices_do_ack <= 3'b001; 132 | previous_slave <= DEVICE_1; 133 | end 134 | 135 | DEVICE_2: 136 | begin 137 | if (devices_mem_en[2]) 138 | begin 139 | current_slave <= DEVICE_3; 140 | mem_bank_select <= device_3_bank_select; 141 | mem_addr <= device_3_mem_addr; 142 | mem_di <= device_3_mem_di; 143 | mem_we <= devices_mem_we[2]; 144 | end 145 | else if (devices_mem_en[0]) 146 | begin 147 | current_slave <= DEVICE_1; 148 | mem_bank_select <= device_1_bank_select; 149 | mem_addr <= device_1_mem_addr; 150 | mem_di <= device_1_mem_di; 151 | mem_we <= devices_mem_we[0]; 152 | end 153 | else 154 | begin 155 | current_slave <= NO_ONE; 156 | mem_bank_select <= 4'd0; 157 | mem_addr <= 10'd0; 158 | mem_di <= 32'd0; 159 | mem_we <= 0; 160 | end 161 | devices_do_ack <= 3'b010; 162 | previous_slave <= DEVICE_2; 163 | end 164 | 165 | DEVICE_3: 166 | begin 167 | if (devices_mem_en[0]) 168 | begin 169 | current_slave <= DEVICE_1; 170 | mem_bank_select <= device_1_bank_select; 171 | mem_addr <= device_1_mem_addr; 172 | mem_di <= device_1_mem_di; 173 | mem_we <= devices_mem_we[0]; 174 | end 175 | else if (devices_mem_en[1]) 176 | begin 177 | current_slave <= DEVICE_2; 178 | mem_bank_select <= device_2_bank_select; 179 | mem_addr <= device_2_mem_addr; 180 | mem_di <= device_2_mem_di; 181 | mem_we <= devices_mem_we[1]; 182 | end 183 | else 184 | begin 185 | current_slave <= NO_ONE; 186 | mem_bank_select <= 4'd0; 187 | mem_addr <= 10'd0; 188 | mem_di <= 32'd0; 189 | mem_we <= 0; 190 | end 191 | devices_do_ack <= 3'b100; 192 | previous_slave <= DEVICE_3; 193 | end 194 | endcase 195 | end 196 | end 197 | 198 | ram mem(clk, mem_bank_select, ~reset, mem_addr, mem_di, mem_do, mem_we); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /examples/instruction-decoder/pipeline.v: -------------------------------------------------------------------------------- 1 | module pipeline( 2 | input clk, 3 | input reset, 4 | output DOR, 5 | input DIR, 6 | input ack_to_pipeline, 7 | output ack_from_pipeline, 8 | input [31:0] data_in, 9 | output [31:0] data_out, 10 | 11 | output [9:0] device_1_mem_addr, 12 | output [31:0] device_1_mem_di, 13 | output [9:0] device_2_mem_addr, 14 | output [31:0] device_2_mem_di, 15 | output [3:0] device_2_bank_select, 16 | output [1:0] devices_burst_en, 17 | output [1:0] devices_mem_we, 18 | output [1:0] devices_mem_en, 19 | input [1:0] devices_do_ack, 20 | 21 | 22 | input [31:0] mem_do 23 | ); 24 | 25 | /* No burst access to ram allowed for now */ 26 | assign device_1_burst_en = 0; 27 | 28 | wire DOR_IF; /* Data Out Ready */ 29 | wire DIR_IF; 30 | 31 | wire ack_to_IF; 32 | wire ack_from_IF; 33 | 34 | wire ack_to_ID; 35 | wire ack_from_ID; 36 | 37 | wire DOR_ID; 38 | wire DIR_ID; 39 | 40 | wire [31:0] data_in_ID; 41 | wire [31:0] data_out_ID; 42 | 43 | wire [31:0] data_in_IF; 44 | wire [31:0] data_out_IF; 45 | 46 | assign DIR_IF = DIR; 47 | assign DIR_ID = DOR_IF; 48 | 49 | assign DOR = DOR_ID; 50 | 51 | assign data_in_IF = data_in; 52 | assign data_in_ID = data_out_IF; 53 | 54 | assign data_out = data_out_ID; 55 | 56 | assign ack_from_pipeline = ack_from_IF; 57 | assign ack_to_ID = ack_to_pipeline; 58 | 59 | assign ack_to_IF = ack_from_ID; 60 | 61 | assign devices_mem_we[0] = 0; 62 | 63 | instruction_fetch IF ( 64 | clk, 65 | reset, 66 | DOR_IF, 67 | DIR_IF, 68 | ack_to_IF, 69 | ack_from_IF, 70 | data_in_IF, 71 | data_out_IF, 72 | 73 | device_1_mem_di, 74 | devices_mem_en[0], 75 | device_1_mem_addr, 76 | mem_do, 77 | devices_do_ack[0] 78 | ); 79 | 80 | instruction_decoder ID ( 81 | clk, 82 | reset, 83 | DOR_ID, 84 | DIR_ID, 85 | ack_to_ID, 86 | ack_from_ID, 87 | data_in_ID, 88 | data_out_ID, 89 | 90 | device_2_mem_di, 91 | devices_mem_en[1], 92 | device_2_bank_select, 93 | device_2_mem_addr, 94 | devices_mem_we[1], 95 | mem_do, 96 | devices_do_ack[1] 97 | ); 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /examples/instruction-decoder/ram.v: -------------------------------------------------------------------------------- 1 | module ram(input clock, input [3:0] bank_select, input enable, input [9:0] addr, input [31:0] di, output [31:0] do, input we); 2 | 3 | reg [7:0] mem0 [1023:0]; 4 | reg [7:0] mem1 [1023:0]; 5 | reg [7:0] mem2 [1023:0]; 6 | reg [7:0] mem3 [1023:0]; 7 | reg [31:0] do; 8 | 9 | /* bank 0 */ 10 | always @(posedge clock) 11 | begin 12 | if (enable & bank_select[0]) 13 | begin 14 | if (we) 15 | begin 16 | mem0[addr] <= di[7:0]; 17 | end 18 | do[7:0] <= mem0[addr]; 19 | end 20 | end 21 | 22 | always @(posedge clock) 23 | begin 24 | if (enable & bank_select[1]) 25 | begin 26 | if (we) 27 | begin 28 | mem1[addr] <= di[15:8]; 29 | end 30 | do[15:8] <= mem1[addr]; 31 | end 32 | end 33 | 34 | always @(posedge clock) 35 | begin 36 | if (enable & bank_select[2]) 37 | begin 38 | if (we) 39 | begin 40 | mem2[addr] <= di[23:16]; 41 | end 42 | do[23:16] <= mem2[addr]; 43 | end 44 | end 45 | 46 | always @(posedge clock) 47 | begin 48 | if (enable & bank_select[3]) 49 | begin 50 | if (we) 51 | begin 52 | mem3[addr] <= di[31:24]; 53 | end 54 | do[31:24] <= mem3[addr]; 55 | end 56 | end 57 | 58 | initial 59 | begin 60 | $readmemh("ram0.data", mem0); 61 | $readmemh("ram1.data", mem1); 62 | $readmemh("ram2.data", mem2); 63 | $readmemh("ram3.data", mem3); 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /examples/instruction-decoder/top.v: -------------------------------------------------------------------------------- 1 | module top; 2 | 3 | parameter WAITING_ACK_FROM_PIPELINE = 0; 4 | parameter PIPELINE_ACKED = 1; 5 | 6 | parameter WAITING_DOR_FROM_PIPELINE = 0; 7 | parameter PIPELINE_IS_ACKED = 1; 8 | 9 | reg clk = 0; 10 | reg reset = 1; 11 | wire pipeline_DOR; 12 | reg ack_to_pipeline_reg = 0; 13 | reg [31:0] data_in = 32'd0; 14 | reg [31:0] data_out_reg = 32'd0; 15 | reg pipeline_DIR; 16 | wire [31:0] data_out; 17 | reg state = WAITING_ACK_FROM_PIPELINE; 18 | reg ack_state = WAITING_DOR_FROM_PIPELINE; 19 | wire [31:0] mem_do; 20 | 21 | wire [2:0] devices_mem_en; 22 | wire [2:0] devices_burst_en; 23 | wire [9:0] device_1_mem_addr; 24 | wire [9:0] device_2_mem_addr; 25 | reg [9:0] device_3_mem_addr = 9'd0; 26 | wire [31:0] device_1_mem_di; 27 | wire [31:0] device_2_mem_di; 28 | reg [31:0] device_3_mem_di = 32'd0; 29 | wire [3:0] device_2_bank_select; 30 | reg [3:0] device_3_bank_select = 4'd1; 31 | wire [2:0] devices_mem_we; 32 | wire [2:0] devices_do_ack; 33 | wire mem_en; 34 | 35 | reg [31:0] PC = 32'd0; 36 | 37 | always #5 clk = !clk; 38 | 39 | assign ack_to_pipeline = ack_to_pipeline_reg; 40 | assign devices_mem_en[2] = 0; 41 | assign devices_burst_en[2] = 0; 42 | assign devices_mem_we[2] = 0; 43 | assign devices_do_ack[2] = 0; 44 | 45 | initial 46 | begin 47 | $display("Starting Instruction Pipeline example"); 48 | $dumpfile("top.vcd"); 49 | $dumpvars(0, top); 50 | 51 | #20 52 | reset = 0; 53 | 54 | # 350 $stop; 55 | $finish; 56 | end 57 | 58 | memory_controller mem_cont(clk, 59 | reset, 60 | devices_burst_en, 61 | devices_mem_en, 62 | device_1_mem_addr, 63 | device_2_mem_addr, 64 | device_3_mem_addr, 65 | device_1_mem_di, 66 | device_2_mem_di, 67 | device_3_mem_di, 68 | 4'b1111, 69 | device_2_bank_select, 70 | device_3_bank_select, 71 | devices_mem_we, 72 | devices_do_ack, 73 | mem_do 74 | ); 75 | 76 | 77 | pipeline p( 78 | clk, 79 | reset, 80 | pipeline_DOR, 81 | pipeline_DIR, 82 | ack_to_pipeline, 83 | ack_from_pipeline, 84 | data_in, 85 | data_out, 86 | 87 | device_1_mem_addr, 88 | device_1_mem_di, 89 | device_2_mem_addr, 90 | device_2_mem_di, 91 | device_2_bank_select, 92 | devices_burst_en[1:0], 93 | devices_mem_we[1:0], 94 | devices_mem_en[1:0], 95 | devices_do_ack[1:0], 96 | mem_do 97 | ); 98 | 99 | always @(posedge clk) 100 | begin 101 | if (reset) 102 | begin 103 | state <= WAITING_ACK_FROM_PIPELINE; 104 | pipeline_DIR <= 0; 105 | data_in <= 0; 106 | PC <= 32'd0; 107 | end 108 | else 109 | begin 110 | case (state) 111 | 112 | WAITING_ACK_FROM_PIPELINE: 113 | begin 114 | if (ack_from_pipeline) 115 | begin 116 | pipeline_DIR <= 0; 117 | PC <= PC + 4; 118 | state <= PIPELINE_ACKED; 119 | end 120 | else 121 | begin 122 | data_in <= PC; 123 | pipeline_DIR <= 1; 124 | state <= WAITING_ACK_FROM_PIPELINE; 125 | end 126 | end 127 | 128 | PIPELINE_ACKED: 129 | begin 130 | if (ack_from_pipeline) 131 | begin 132 | state <= PIPELINE_ACKED; 133 | end 134 | else 135 | begin 136 | state <= WAITING_ACK_FROM_PIPELINE; 137 | end 138 | pipeline_DIR <= 0; 139 | end 140 | 141 | 142 | 143 | endcase 144 | end 145 | end 146 | 147 | always @(posedge clk) 148 | begin 149 | 150 | if (reset) 151 | begin 152 | ack_to_pipeline_reg <= 0; 153 | end 154 | else 155 | begin 156 | case (ack_state) 157 | 158 | WAITING_DOR_FROM_PIPELINE: 159 | begin 160 | if (pipeline_DOR) 161 | begin 162 | data_out_reg <= data_out; 163 | $display("Pipeline outputs %d", data_out); 164 | ack_to_pipeline_reg <= 1; 165 | ack_state <= PIPELINE_IS_ACKED; 166 | end 167 | else 168 | begin 169 | ack_state <= WAITING_DOR_FROM_PIPELINE; 170 | ack_to_pipeline_reg <= 0; 171 | end 172 | end 173 | 174 | PIPELINE_IS_ACKED: 175 | begin 176 | $display("We acked the pipeline"); 177 | ack_to_pipeline_reg <= 0; 178 | ack_state <= WAITING_DOR_FROM_PIPELINE; 179 | end 180 | 181 | endcase 182 | end 183 | end 184 | 185 | endmodule 186 | -------------------------------------------------------------------------------- /examples/instruction-fetcher/Makefile: -------------------------------------------------------------------------------- 1 | all: top ram.data 2 | 3 | run: all 4 | vvp top 5 | 6 | top: top.v pipeline.v instruction_fetch.v ram.v memory_controller.v 7 | iverilog -o $@ $^ 8 | 9 | ram.data: genram 10 | ./genram > ram.data 11 | 12 | genram: genram.c 13 | $(CC) $(CFLAGS) $^ -o $@ 14 | 15 | clean: 16 | $(RM) -rf top genram ram.data 17 | 18 | top.vcd: top 19 | $(MAKE) run 20 | 21 | wave: top.vcd 22 | gtkwave top.vcd 23 | 24 | .PHONY: all clean wave 25 | -------------------------------------------------------------------------------- /examples/instruction-fetcher/genram.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | int main(void) { 5 | 6 | unsigned int i; 7 | 8 | for (i = 0 ; i < 1024 ; ++i) 9 | printf("%d\n", i % 256); 10 | 11 | return EXIT_SUCCESS; 12 | } 13 | -------------------------------------------------------------------------------- /examples/instruction-fetcher/instruction_fetch.v: -------------------------------------------------------------------------------- 1 | module instruction_fetch( 2 | input clk, 3 | input reset, 4 | output DOR, 5 | input DIR, 6 | input ack_from_next, 7 | output ack_prev, 8 | input [7:0] data_in, 9 | output [7:0] data_out, 10 | 11 | output [7:0] mem_di, 12 | output mem_en, 13 | output [7:0] mem_addr, 14 | input [7:0] mem_do, 15 | input mem_do_ack 16 | ); 17 | 18 | parameter IDLE = 2'd0; 19 | parameter WAITING_ACK_FROM_MEMORY_CONTROLLER = 2'd1; 20 | parameter WAITING_ACK_FROM_NEXT_STAGE = 2'd2; 21 | 22 | reg [1:0] state = IDLE; 23 | reg [7:0] data_out_reg = 8'd0; 24 | reg DOR_reg = 0; 25 | reg ack_prev_reg = 0; 26 | reg [7:0] data_in_buffer; 27 | reg [7:0] mem_addr_reg = 8'd0; 28 | reg mem_en_reg = 0; 29 | reg [7:0] data_in_cached = 8'd0; 30 | 31 | 32 | assign data_out = data_out_reg; 33 | assign DOR = DOR_reg; 34 | assign ack_prev = ack_prev_reg; 35 | assign mem_addr = mem_addr_reg; 36 | assign mem_en = mem_en_reg; 37 | assign mem_di = 8'd0; 38 | 39 | always @(posedge clk) 40 | begin 41 | if (reset) 42 | begin 43 | state <= IDLE; 44 | data_out_reg <= 0; 45 | DOR_reg <= 0; 46 | ack_prev_reg <= 0; 47 | mem_addr_reg <= 8'd0; 48 | mem_en_reg <= 0; 49 | data_in_cached <= 8'd0; 50 | end 51 | else 52 | begin 53 | case (state) 54 | 55 | IDLE: 56 | begin 57 | if (DIR) 58 | begin 59 | $display("Fetching opcode @ PC = %02X", data_in); 60 | state <= WAITING_ACK_FROM_MEMORY_CONTROLLER; 61 | ack_prev_reg <= 1; 62 | mem_en_reg <= 1; 63 | DOR_reg <= 0; 64 | data_in_cached <= data_in; 65 | mem_addr_reg <= data_in; 66 | end 67 | else 68 | begin 69 | mem_en_reg <= 0; 70 | DOR_reg <= 0; 71 | mem_addr_reg <= data_in; 72 | end 73 | end 74 | 75 | WAITING_ACK_FROM_MEMORY_CONTROLLER: 76 | begin 77 | if (mem_do_ack) 78 | begin 79 | $display("instruction fetcher fetched 0x%02X from PC = 0x%02X", mem_do, data_in_cached); 80 | data_out_reg <= mem_do; 81 | DOR_reg <= 1; 82 | mem_en_reg <= 0; 83 | state <= WAITING_ACK_FROM_NEXT_STAGE; 84 | end 85 | else 86 | begin 87 | state <= WAITING_ACK_FROM_MEMORY_CONTROLLER; 88 | DOR_reg <= 0; 89 | mem_en_reg <= 1; 90 | end 91 | ack_prev_reg <= 0; 92 | end 93 | 94 | WAITING_ACK_FROM_NEXT_STAGE: 95 | begin 96 | if (ack_from_next) 97 | begin 98 | $display("instruction_fetcher got ACK from next stage"); 99 | DOR_reg <= 0; 100 | mem_en_reg <= 0; 101 | state <= IDLE; 102 | end 103 | else 104 | begin 105 | DOR_reg <= 1; 106 | mem_en_reg <= 0; 107 | state <= WAITING_ACK_FROM_NEXT_STAGE; 108 | end 109 | end 110 | 111 | endcase 112 | end 113 | end 114 | 115 | endmodule 116 | -------------------------------------------------------------------------------- /examples/instruction-fetcher/memory_controller.v: -------------------------------------------------------------------------------- 1 | module memory_controller(clk, 2 | reset, 3 | devices_burst_en, 4 | devices_mem_en, 5 | device_1_mem_addr, 6 | device_2_mem_addr, 7 | device_3_mem_addr, 8 | device_1_mem_di, 9 | device_2_mem_di, 10 | device_3_mem_di, 11 | devices_mem_we, 12 | devices_do_ack, 13 | mem_do); 14 | 15 | input clk; 16 | input reset; 17 | input [2:0] devices_burst_en; 18 | input [2:0] devices_mem_en; 19 | input [7:0] device_1_mem_addr; 20 | input [7:0] device_2_mem_addr; 21 | input [7:0] device_3_mem_addr; 22 | input [7:0] device_1_mem_di; 23 | input [7:0] device_2_mem_di; 24 | input [7:0] device_3_mem_di; 25 | input [2:0] devices_mem_we; 26 | output [2:0] devices_do_ack; 27 | output [7:0] mem_do; 28 | 29 | parameter DEVICE_1 = 3'd0; 30 | parameter DEVICE_2 = 3'd1; 31 | parameter DEVICE_3 = 3'd2; 32 | parameter NO_ONE = 3'b111; 33 | 34 | reg mem_enable = 0; 35 | reg [7:0] mem_addr = 7'd0; 36 | reg [7:0] mem_di = 7'd0; 37 | reg [2:0] current_slave = NO_ONE; 38 | reg [2:0] previous_slave = NO_ONE; 39 | reg mem_we = 0; 40 | reg [2:0] devices_do_ack = 3'd0; 41 | 42 | always @(posedge clk) 43 | begin 44 | if (reset) 45 | begin 46 | current_slave <= NO_ONE; 47 | end 48 | else 49 | begin 50 | case (current_slave) 51 | NO_ONE: 52 | begin 53 | if (devices_mem_en[0] && previous_slave != DEVICE_1) 54 | begin 55 | current_slave <= DEVICE_1; 56 | mem_addr <= device_1_mem_addr; 57 | mem_di <= device_1_mem_di; 58 | mem_we <= devices_mem_we[0]; 59 | end 60 | else if (devices_mem_en[1] && previous_slave != DEVICE_2) 61 | begin 62 | current_slave <= DEVICE_2; 63 | mem_addr <= device_2_mem_addr; 64 | mem_di <= device_2_mem_di; 65 | mem_we <= devices_mem_we[1]; 66 | end 67 | else if (devices_mem_en[2] && previous_slave != DEVICE_3) 68 | begin 69 | current_slave <= DEVICE_3; 70 | mem_addr <= device_3_mem_addr; 71 | mem_di <= device_3_mem_di; 72 | mem_we <= devices_mem_we[2]; 73 | end 74 | else 75 | begin 76 | current_slave <= NO_ONE; 77 | mem_addr <= 7'd0; 78 | mem_di <= 7'd0; 79 | mem_we <= 0; 80 | end 81 | previous_slave <= NO_ONE; 82 | devices_do_ack <= 3'b000; 83 | end 84 | 85 | DEVICE_1: 86 | begin 87 | if (devices_mem_en[1]) 88 | begin 89 | current_slave <= DEVICE_2; 90 | mem_addr <= device_2_mem_addr; 91 | mem_di <= device_2_mem_di; 92 | mem_we <= devices_mem_we[1]; 93 | end 94 | else if (devices_mem_en[2]) 95 | begin 96 | current_slave <= DEVICE_3; 97 | mem_addr <= device_3_mem_addr; 98 | mem_di <= device_3_mem_di; 99 | mem_we <= devices_mem_we[2]; 100 | end 101 | else 102 | begin 103 | if (devices_burst_en[0] && devices_mem_en[0]) 104 | begin 105 | devices_do_ack <= 3'b001; 106 | mem_addr <= device_1_mem_addr + 1; 107 | mem_di <= device_1_mem_di; 108 | end 109 | else 110 | begin 111 | current_slave <= NO_ONE; 112 | mem_addr <= 7'd0; 113 | mem_di <= 7'd0; 114 | mem_we <= 0; 115 | end 116 | end 117 | devices_do_ack <= 3'b001; 118 | previous_slave <= DEVICE_1; 119 | end 120 | 121 | DEVICE_2: 122 | begin 123 | if (devices_mem_en[2]) 124 | begin 125 | current_slave <= DEVICE_3; 126 | mem_addr <= device_3_mem_addr; 127 | mem_di <= device_3_mem_di; 128 | mem_we <= devices_mem_we[2]; 129 | end 130 | else if (devices_mem_en[0]) 131 | begin 132 | current_slave <= DEVICE_1; 133 | mem_addr <= device_1_mem_addr; 134 | mem_di <= device_1_mem_di; 135 | mem_we <= devices_mem_we[0]; 136 | end 137 | else 138 | begin 139 | current_slave <= NO_ONE; 140 | mem_addr <= 7'd0; 141 | mem_di <= 7'd0; 142 | mem_we <= 0; 143 | end 144 | devices_do_ack <= 3'b010; 145 | previous_slave <= DEVICE_2; 146 | end 147 | 148 | DEVICE_3: 149 | begin 150 | if (devices_mem_en[0]) 151 | begin 152 | current_slave <= DEVICE_1; 153 | mem_addr <= device_1_mem_addr; 154 | mem_di <= device_1_mem_di; 155 | mem_we <= devices_mem_we[0]; 156 | end 157 | else if (devices_mem_en[1]) 158 | begin 159 | current_slave <= DEVICE_2; 160 | mem_addr <= device_2_mem_addr; 161 | mem_di <= device_2_mem_di; 162 | mem_we <= devices_mem_we[1]; 163 | end 164 | else 165 | begin 166 | current_slave <= NO_ONE; 167 | mem_addr <= 7'd0; 168 | mem_di <= 7'd0; 169 | mem_we <= 0; 170 | end 171 | devices_do_ack <= 3'b100; 172 | previous_slave <= DEVICE_3; 173 | end 174 | endcase 175 | end 176 | end 177 | 178 | ram mem(clk, ~reset, mem_addr, mem_di, mem_do, mem_we); 179 | 180 | endmodule 181 | -------------------------------------------------------------------------------- /examples/instruction-fetcher/pipeline.v: -------------------------------------------------------------------------------- 1 | module pipeline( 2 | input clk, 3 | input reset, 4 | output DOR, 5 | input DIR, 6 | input ack_to_A, 7 | output ack_from_A, 8 | input [7:0] data_in, 9 | output [7:0] data_out_A, 10 | 11 | output [7:0] device_1_mem_addr, 12 | output [7:0] device_1_mem_di, 13 | output device_1_burst_en, 14 | output device_1_mem_en, 15 | input device_1_do_ack, 16 | input [7:0] mem_do 17 | ); 18 | 19 | /* No burst access to ram allowed for now */ 20 | assign device_1_burst_en = 0; 21 | 22 | wire DOR_A; /* Data Out Ready */ 23 | wire ack_to_A; 24 | 25 | assign DOR = DOR_A; 26 | assign DIR_A = DIR; 27 | 28 | wire [7:0] data_out_A; 29 | 30 | instruction_fetch IF ( 31 | clk, 32 | reset, 33 | DOR_A, 34 | DIR, 35 | ack_to_A, 36 | ack_from_A, 37 | data_in, 38 | data_out_A, 39 | 40 | device_1_mem_di, 41 | device_1_mem_en, 42 | device_1_mem_addr, 43 | mem_do, 44 | device_1_do_ack 45 | ); 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /examples/instruction-fetcher/ram.v: -------------------------------------------------------------------------------- 1 | module ram(input clock, input enable, input [7:0] addr, input [7:0] di, output [7:0] do, input we); 2 | 3 | reg [7:0] mem [1023:0]; 4 | reg [7:0] do; 5 | 6 | always @(posedge clock) 7 | begin 8 | if (enable) 9 | begin 10 | if (we) 11 | begin 12 | mem[addr] <= di; 13 | end 14 | do <= mem[addr]; 15 | end 16 | end 17 | 18 | initial 19 | begin 20 | $readmemh("ram.data", mem); 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /examples/instruction-fetcher/top.v: -------------------------------------------------------------------------------- 1 | module top; 2 | 3 | parameter WAITING_ACK_FROM_PIPELINE = 0; 4 | parameter PIPELINE_HAS_ACKED = 1; 5 | 6 | parameter WAITING_DOR_FROM_PIPELINE = 0; 7 | parameter PIPELINE_IS_ACKED = 1; 8 | 9 | reg clk = 0; 10 | reg reset = 1; 11 | wire pipeline_DOR; 12 | reg ack_to_pipeline_reg = 0; 13 | reg [7:0] data_in = 8'd0; 14 | reg [7:0] data_out_reg = 8'd0; 15 | reg pipeline_DIR; 16 | wire [7:0] data_out; 17 | reg state = WAITING_ACK_FROM_PIPELINE; 18 | reg ack_state = WAITING_DOR_FROM_PIPELINE; 19 | wire [7:0] mem_do; 20 | 21 | wire [2:0] devices_mem_en; 22 | wire [2:0] devices_burst_en; 23 | wire [7:0] device_1_mem_addr; 24 | reg [7:0] device_2_mem_addr = 8'd0; 25 | reg [7:0] device_3_mem_addr = 8'd0; 26 | wire [7:0] device_1_mem_di; 27 | reg [7:0] device_2_mem_di = 8'd0; 28 | reg [7:0] device_3_mem_di = 8'd0; 29 | reg [2:0] devices_mem_we = 3'd0; 30 | wire [2:0] devices_do_ack; 31 | wire mem_en; 32 | 33 | reg [7:0] PC = 8'd1; 34 | 35 | always #5 clk = !clk; 36 | 37 | assign ack_to_pipeline = ack_to_pipeline_reg; 38 | assign devices_mem_en[2:1] = 2'b00; 39 | assign devices_burst_en[2:1] = 2'b00; 40 | 41 | initial 42 | begin 43 | $display("Starting Instruction Pipeline example"); 44 | $dumpfile("top.vcd"); 45 | $dumpvars(0, top); 46 | 47 | #20 48 | reset = 0; 49 | 50 | # 200 $stop; 51 | $finish; 52 | end 53 | 54 | memory_controller mem_cont(clk, 55 | reset, 56 | devices_burst_en, 57 | devices_mem_en, 58 | device_1_mem_addr, 59 | device_2_mem_addr, 60 | device_3_mem_addr, 61 | device_1_mem_di, 62 | device_2_mem_di, 63 | device_3_mem_di, 64 | devices_mem_we, 65 | devices_do_ack, 66 | mem_do); 67 | 68 | 69 | pipeline p( 70 | clk, 71 | reset, 72 | pipeline_DOR, 73 | pipeline_DIR, 74 | ack_to_pipeline, 75 | ack_from_pipeline, 76 | data_in, 77 | data_out, 78 | 79 | device_1_mem_addr, 80 | device_1_mem_di, 81 | devices_burst_en[0], 82 | devices_mem_en[0], 83 | devices_do_ack[0], 84 | mem_do 85 | ); 86 | 87 | always @(posedge clk) 88 | begin 89 | if (reset) 90 | begin 91 | state <= WAITING_ACK_FROM_PIPELINE; 92 | ack_to_pipeline_reg <= 0; 93 | pipeline_DIR <= 0; 94 | data_in <= 0; 95 | PC <= 8'd1; 96 | end 97 | else 98 | begin 99 | case (state) 100 | 101 | WAITING_ACK_FROM_PIPELINE: 102 | begin 103 | if (ack_from_pipeline) 104 | begin 105 | pipeline_DIR <= 0; 106 | PC <= PC + 1; 107 | state <= PIPELINE_HAS_ACKED; 108 | end 109 | else 110 | begin 111 | data_in <= PC; 112 | pipeline_DIR <= 1; 113 | state <= WAITING_ACK_FROM_PIPELINE; 114 | end 115 | end 116 | 117 | PIPELINE_HAS_ACKED: 118 | begin 119 | if (ack_from_pipeline) 120 | begin 121 | state <= PIPELINE_HAS_ACKED; 122 | end 123 | else 124 | begin 125 | state <= WAITING_ACK_FROM_PIPELINE; 126 | end 127 | pipeline_DIR <= 0; 128 | end 129 | 130 | 131 | 132 | endcase 133 | end 134 | end 135 | 136 | always @(posedge clk) 137 | begin 138 | 139 | case (ack_state) 140 | 141 | WAITING_DOR_FROM_PIPELINE: 142 | begin 143 | if (pipeline_DOR) 144 | begin 145 | data_out_reg <= data_out; 146 | $display("Pipeline outputs %d", data_out); 147 | ack_to_pipeline_reg <= 1; 148 | ack_state <= PIPELINE_IS_ACKED; 149 | end 150 | else 151 | begin 152 | ack_state <= WAITING_DOR_FROM_PIPELINE; 153 | ack_to_pipeline_reg <= 0; 154 | end 155 | end 156 | 157 | PIPELINE_IS_ACKED: 158 | begin 159 | $display("We acked the pipeline"); 160 | ack_to_pipeline_reg <= 0; 161 | ack_state <= WAITING_DOR_FROM_PIPELINE; 162 | end 163 | endcase 164 | end 165 | 166 | endmodule 167 | -------------------------------------------------------------------------------- /examples/memory-controller/Makefile: -------------------------------------------------------------------------------- 1 | all: top ram.data 2 | 3 | run: all 4 | vvp top 5 | 6 | top: top.v ram.v memory_controller.v 7 | iverilog -o $@ $^ 8 | 9 | ram.data: genram 10 | ./genram > ram.data 11 | 12 | genram: genram.c 13 | $(CC) $(CFLAGS) $^ -o $@ 14 | 15 | clean: 16 | $(RM) -rf top genram ram.data 17 | 18 | top.vcd: top 19 | $(MAKE) run 20 | 21 | wave: top.vcd 22 | gtkwave top.vcd 23 | 24 | .PHONY: all clean wave 25 | -------------------------------------------------------------------------------- /examples/memory-controller/genram.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | int main(void) { 5 | 6 | unsigned int i; 7 | 8 | for (i = 0 ; i < 1024 ; ++i) 9 | printf("%d\n", i % 256); 10 | 11 | return EXIT_SUCCESS; 12 | } 13 | -------------------------------------------------------------------------------- /examples/memory-controller/memory_controller.v: -------------------------------------------------------------------------------- 1 | module memory_controller(clk, 2 | reset, 3 | devices_mem_en, 4 | device_1_mem_addr, 5 | device_2_mem_addr, 6 | device_3_mem_addr, 7 | device_1_mem_di, 8 | device_2_mem_di, 9 | device_3_mem_di, 10 | devices_mem_we, 11 | devices_do_ack, 12 | mem_do); 13 | 14 | input clk; 15 | input reset; 16 | input [2:0] devices_mem_en; 17 | input [7:0] device_1_mem_addr; 18 | input [7:0] device_2_mem_addr; 19 | input [7:0] device_3_mem_addr; 20 | input [7:0] device_1_mem_di; 21 | input [7:0] device_2_mem_di; 22 | input [7:0] device_3_mem_di; 23 | input [2:0] devices_mem_we; 24 | output [2:0] devices_do_ack; 25 | output [7:0] mem_do; 26 | 27 | parameter DEVICE_1 = 3'd0; 28 | parameter DEVICE_2 = 3'd1; 29 | parameter DEVICE_3 = 3'd2; 30 | parameter NO_ONE = 3'b111; 31 | 32 | reg mem_enable = 0; 33 | reg [7:0] mem_addr = 7'd0; 34 | reg [7:0] mem_di = 7'd0; 35 | reg [2:0] current_slave = NO_ONE; 36 | reg mem_we = 0; 37 | reg [2:0] serving_slave = 2'd0; 38 | reg [2:0] devices_do_ack = 3'd0; 39 | reg local_reset = 0; 40 | reg local_reset2 = 0; 41 | 42 | always @(posedge clk) 43 | begin 44 | local_reset <= reset; 45 | local_reset2 <= local_reset; 46 | end 47 | 48 | always @(posedge clk) 49 | begin 50 | if (reset) 51 | begin 52 | current_slave <= NO_ONE; 53 | end 54 | else 55 | begin 56 | case (current_slave) 57 | NO_ONE: 58 | begin 59 | if (devices_mem_en[0]) 60 | begin 61 | current_slave <= DEVICE_1; 62 | mem_addr <= device_1_mem_addr; 63 | mem_di <= device_1_mem_di; 64 | mem_we <= devices_mem_we[0]; 65 | end 66 | else if (devices_mem_en[1]) 67 | begin 68 | current_slave <= DEVICE_2; 69 | mem_addr <= device_2_mem_addr; 70 | mem_di <= device_2_mem_di; 71 | mem_we <= devices_mem_we[1]; 72 | end 73 | else if (devices_mem_en[2]) 74 | begin 75 | current_slave <= DEVICE_3; 76 | mem_addr <= device_3_mem_addr; 77 | mem_di <= device_3_mem_di; 78 | mem_we <= devices_mem_we[2]; 79 | end 80 | else 81 | begin 82 | current_slave <= NO_ONE; 83 | mem_addr <= 7'd0; 84 | mem_di <= 7'd0; 85 | mem_we <= 0; 86 | end 87 | devices_do_ack <= 3'b000; 88 | end 89 | 90 | DEVICE_1: 91 | begin 92 | if (devices_mem_en[1]) 93 | begin 94 | current_slave <= DEVICE_2; 95 | mem_addr <= device_2_mem_addr; 96 | mem_di <= device_2_mem_di; 97 | mem_we <= devices_mem_we[1]; 98 | end 99 | else if (devices_mem_en[2]) 100 | begin 101 | current_slave <= DEVICE_3; 102 | mem_addr <= device_3_mem_addr; 103 | mem_di <= device_3_mem_di; 104 | mem_we <= devices_mem_we[2]; 105 | end 106 | else 107 | begin 108 | current_slave <= NO_ONE; 109 | mem_addr <= 7'd0; 110 | mem_di <= 7'd0; 111 | mem_we <= 0; 112 | end 113 | devices_do_ack <= 3'b001; 114 | end 115 | 116 | DEVICE_2: 117 | begin 118 | if (devices_mem_en[2]) 119 | begin 120 | current_slave <= DEVICE_3; 121 | mem_addr <= device_3_mem_addr; 122 | mem_di <= device_3_mem_di; 123 | mem_we <= devices_mem_we[2]; 124 | end 125 | else if (devices_mem_en[0]) 126 | begin 127 | current_slave <= DEVICE_1; 128 | mem_addr <= device_1_mem_addr; 129 | mem_di <= device_1_mem_di; 130 | mem_we <= devices_mem_we[0]; 131 | end 132 | else 133 | begin 134 | current_slave <= NO_ONE; 135 | mem_addr <= 7'd0; 136 | mem_di <= 7'd0; 137 | mem_we <= 0; 138 | end 139 | devices_do_ack <= 3'b010; 140 | end 141 | 142 | DEVICE_3: 143 | begin 144 | if (devices_mem_en[0]) 145 | begin 146 | current_slave <= DEVICE_1; 147 | mem_addr <= device_1_mem_addr; 148 | mem_di <= device_1_mem_di; 149 | mem_we <= devices_mem_we[0]; 150 | end 151 | else if (devices_mem_en[1]) 152 | begin 153 | current_slave <= DEVICE_2; 154 | mem_addr <= device_2_mem_addr; 155 | mem_di <= device_2_mem_di; 156 | mem_we <= devices_mem_we[1]; 157 | end 158 | else 159 | begin 160 | current_slave <= NO_ONE; 161 | mem_addr <= 7'd0; 162 | mem_di <= 7'd0; 163 | mem_we <= 0; 164 | end 165 | devices_do_ack <= 3'b100; 166 | end 167 | endcase 168 | end 169 | end 170 | 171 | ram mem(clk, ~reset, mem_addr, mem_di, mem_do, mem_we); 172 | 173 | endmodule 174 | -------------------------------------------------------------------------------- /examples/memory-controller/ram.v: -------------------------------------------------------------------------------- 1 | module ram(input clock, input enable, input [7:0] addr, input [7:0] di, output [7:0] do, input we); 2 | 3 | reg [7:0] mem [1023:0]; 4 | reg [7:0] do; 5 | 6 | always @(posedge clock) 7 | begin 8 | if (enable) 9 | begin 10 | if (we) 11 | begin 12 | mem[addr] <= di; 13 | end 14 | do <= mem[addr]; 15 | end 16 | end 17 | 18 | initial 19 | begin 20 | $readmemh("ram.data", mem); 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /examples/memory-controller/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module top; 3 | 4 | reg clk = 0; 5 | reg reset = 1; 6 | 7 | always #5 clk <= !clk; 8 | 9 | reg [2:0] devices_mem_en = 3'd0; 10 | reg [7:0] device_1_mem_addr = 7'd0; 11 | reg [7:0] device_2_mem_addr = 7'd0; 12 | reg [7:0] device_3_mem_addr = 7'd0; 13 | reg [7:0] device_1_mem_di = 7'd0; 14 | reg [7:0] device_2_mem_di = 7'd0; 15 | reg [7:0] device_3_mem_di = 7'd0; 16 | reg [2:0] devices_mem_we = 3'd0; 17 | wire [2:0] devices_do_ack; 18 | wire [7:0] mem_do; 19 | 20 | initial 21 | begin 22 | $display("Starting memory_controller example"); 23 | /* $monitor("devices_do_ack == %b at %0d", devices_do_ack, $time); */ 24 | $dumpfile("top.vcd"); 25 | $dumpvars(0, top); 26 | # 10 reset <= 0; 27 | 28 | /* All 3 slaves are issuing parallel READ */ 29 | # 10 30 | device_1_mem_addr = 7'd5; 31 | device_2_mem_addr = 7'd7; 32 | device_3_mem_addr = 7'd9; 33 | devices_mem_en = 3'b111; 34 | 35 | /* Suddenly slave 1 stops accessing SRAM */ 36 | # 60 37 | devices_mem_en = 3'b101; 38 | 39 | /* Then all 3 slaves are issuing parallel WRITE */ 40 | # 60 41 | device_1_mem_addr = 7'h0A; 42 | device_2_mem_addr = 7'h0B; 43 | device_3_mem_addr = 7'h0C; 44 | device_1_mem_di = 7'd42; 45 | device_2_mem_di = 7'd43; 46 | device_3_mem_di = 7'd44; 47 | devices_mem_we = 3'b111; 48 | devices_mem_en = 3'b111; 49 | 50 | # 60 51 | devices_mem_we = 3'd0; 52 | devices_mem_en = 3'b001; 53 | 54 | # 20 55 | devices_mem_en = 3'b001; 56 | 57 | # 20 58 | devices_mem_en = 3'b010; 59 | 60 | # 20 61 | devices_mem_en = 3'b100; 62 | 63 | # 20 $stop; 64 | $finish; 65 | end 66 | 67 | memory_controller mem_cont(clk, 68 | reset, 69 | devices_mem_en, 70 | device_1_mem_addr, 71 | device_2_mem_addr, 72 | device_3_mem_addr, 73 | device_1_mem_di, 74 | device_2_mem_di, 75 | device_3_mem_di, 76 | devices_mem_we, 77 | devices_do_ack, 78 | mem_do); 79 | 80 | always @(posedge clk) 81 | begin 82 | if (devices_do_ack[0]) 83 | $display("Device_1's transaction done, mem_do = %d, devices_do_ack = %b", mem_do, devices_do_ack); 84 | else if (devices_do_ack[1]) 85 | $display("Device_2's transaction done, mem_do = %d, devices_do_ack = %b", mem_do, devices_do_ack); 86 | else if (devices_do_ack[2]) 87 | $display("Device_3's transaction done, mem_do = %d, devices_do_ack = %b", mem_do, devices_do_ack); 88 | else 89 | $display("WHAT ?! devices_do_ack = %b", devices_do_ack); 90 | end 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /examples/pipeline/Makefile: -------------------------------------------------------------------------------- 1 | all: top 2 | 3 | run: all 4 | vvp top 5 | 6 | top: top.v pipeline.v stage_A.v stage_B.v stage_C.v 7 | iverilog -o $@ $^ 8 | 9 | clean: 10 | $(RM) -rf top top.vcd 11 | 12 | top.vcd: top 13 | $(MAKE) run 14 | 15 | wave: top.vcd 16 | gtkwave top.vcd 17 | 18 | .PHONY: all clean wave run 19 | -------------------------------------------------------------------------------- /examples/pipeline/pipeline.v: -------------------------------------------------------------------------------- 1 | module pipeline(input clk, input reset, output DOR, input DIR, input ack_to_C, output ack_from_A, input [7:0] data_in, output [7:0] data_out); 2 | 3 | wire DOR_A; /* Data Out Ready */ 4 | wire DOR_B; 5 | 6 | wire DIR_B; /* Data In Ready */ 7 | wire DIR_C; 8 | 9 | wire ack_to_A; 10 | wire ack_to_B; 11 | wire ack_from_B; 12 | wire ack_from_C; 13 | 14 | wire [7:0] data_out_A; 15 | wire [7:0] data_out_B; 16 | 17 | wire [7:0] data_in_B; 18 | wire [7:0] data_in_C; 19 | 20 | assign DIR_B = DOR_A; 21 | assign DIR_C = DOR_B; 22 | 23 | assign data_in_B = data_out_A; 24 | assign data_in_C = data_out_B; 25 | 26 | assign ack_to_A = ack_from_B; 27 | assign ack_to_B = ack_from_C; 28 | 29 | stage_A sA (clk, reset, DOR_A, DIR, ack_to_A, ack_from_A, data_in, data_out_A); 30 | stage_B sB (clk, reset, DOR_B, DIR_B, ack_to_B, ack_from_B, data_in_B, data_out_B); 31 | stage_C sC (clk, reset, DOR, DIR_C, ack_to_C, ack_from_C, data_in_C, data_out); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /examples/pipeline/stage_A.v: -------------------------------------------------------------------------------- 1 | module stage_A(input clk, input reset, output DOR, input DIR, input ack_from_next, output ack_prev, input [7:0] data_in, output [7:0] data_out); 2 | 3 | parameter IDLE = 1'd0; 4 | parameter WAITING_ACK = 1'd1; 5 | 6 | reg state = IDLE; 7 | reg [7:0] data_out_reg = 8'd0; 8 | reg DOR_reg = 0; 9 | reg ack_prev_reg = 0; 10 | reg [7:0] data_in_buffer; 11 | 12 | assign data_out = data_out_reg; 13 | assign DOR = DOR_reg; 14 | assign ack_prev = ack_prev_reg; 15 | 16 | always @(posedge clk) 17 | begin 18 | if (reset) 19 | begin 20 | state <= IDLE; 21 | data_out_reg <= 0; 22 | DOR_reg <= 0; 23 | ack_prev_reg <= 0; 24 | end 25 | else 26 | begin 27 | case (state) 28 | 29 | IDLE: 30 | begin 31 | if (DIR) 32 | begin 33 | $display("stage_A receives input_data %d", data_in); 34 | state <= WAITING_ACK; 35 | ack_prev_reg <= 1; 36 | DOR_reg <= 1; 37 | end 38 | data_in_buffer <= data_in; 39 | data_out_reg <= data_in + 1; 40 | end 41 | 42 | WAITING_ACK: 43 | begin 44 | if (ack_from_next) 45 | begin 46 | $display("stage_A got ACK form stage_B"); 47 | DOR_reg <= 0; 48 | state <= IDLE; 49 | end 50 | else 51 | begin 52 | $display("stage_A waits for ACK from stage_B"); 53 | state <= WAITING_ACK; 54 | DOR_reg <= 1; 55 | end 56 | 57 | data_out_reg <= data_in + 1; 58 | ack_prev_reg <= 0; 59 | end 60 | 61 | endcase 62 | end 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /examples/pipeline/stage_B.v: -------------------------------------------------------------------------------- 1 | module stage_B(input clk, input reset, output DOR, input DIR, input ack_from_next, output ack_prev, input [7:0] data_in, output [7:0] data_out); 2 | 3 | parameter IDLE = 1'd0; 4 | parameter WAITING_ACK = 1'd1; 5 | 6 | reg state = IDLE; 7 | reg [7:0] data_out_reg = 8'd0; 8 | reg DOR_reg = 0; 9 | reg ack_prev_reg = 0; 10 | reg [7:0] data_in_buffer; 11 | 12 | assign data_out = data_out_reg; 13 | assign DOR = DOR_reg; 14 | assign ack_prev = ack_prev_reg; 15 | 16 | always @(posedge clk) 17 | begin 18 | if (reset) 19 | begin 20 | state <= IDLE; 21 | data_out_reg <= 0; 22 | DOR_reg <= 0; 23 | ack_prev_reg <= 0; 24 | end 25 | else 26 | begin 27 | case (state) 28 | 29 | IDLE: 30 | begin 31 | if (DIR) 32 | begin 33 | $display("stage_B receives input_data %d", data_in); 34 | state <= WAITING_ACK; 35 | ack_prev_reg <= 1; 36 | DOR_reg <= 1; 37 | end 38 | data_in_buffer <= data_in; 39 | data_out_reg <= data_in + 1; 40 | end 41 | 42 | WAITING_ACK: 43 | begin 44 | if (ack_from_next) 45 | begin 46 | $display("stage_B got ACK form stage_C"); 47 | DOR_reg <= 0; 48 | state <= IDLE; 49 | end 50 | else 51 | begin 52 | $display("stage_B waits for ACK from stage_C"); 53 | state <= WAITING_ACK; 54 | DOR_reg <= 1; 55 | end 56 | 57 | data_out_reg <= data_in + 1; 58 | ack_prev_reg <= 0; 59 | end 60 | 61 | endcase 62 | end 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /examples/pipeline/stage_C.v: -------------------------------------------------------------------------------- 1 | module stage_C(input clk, input reset, output DOR, input DIR, input ack_from_next, output ack_prev, input [7:0] data_in, output [7:0] data_out); 2 | 3 | parameter IDLE = 1'd0; 4 | parameter WAITING_ACK = 1'd1; 5 | 6 | reg state = IDLE; 7 | reg [7:0] data_out_reg = 8'd0; 8 | reg DOR_reg = 0; 9 | reg ack_prev_reg = 0; 10 | reg [7:0] data_in_buffer; 11 | 12 | assign data_out = data_out_reg; 13 | assign DOR = DOR_reg; 14 | assign ack_prev = ack_prev_reg; 15 | 16 | always @(posedge clk) 17 | begin 18 | if (reset) 19 | begin 20 | state <= IDLE; 21 | data_out_reg <= 0; 22 | DOR_reg <= 0; 23 | ack_prev_reg <= 0; 24 | end 25 | else 26 | begin 27 | case (state) 28 | 29 | IDLE: 30 | begin 31 | if (DIR) 32 | begin 33 | $display("stage_C receives input_data %d", data_in); 34 | state <= WAITING_ACK; 35 | ack_prev_reg <= 1; 36 | DOR_reg <= 1; 37 | end 38 | data_in_buffer <= data_in; 39 | data_out_reg <= data_in + 1; 40 | end 41 | 42 | WAITING_ACK: 43 | begin 44 | if (ack_from_next) 45 | begin 46 | $display("stage_C got ACK form stage_B"); 47 | DOR_reg <= 0; 48 | state <= IDLE; 49 | end 50 | else 51 | begin 52 | $display("stage_C waits for ACK from stage_B"); 53 | state <= WAITING_ACK; 54 | DOR_reg <= 1; 55 | end 56 | 57 | data_out_reg <= data_in + 1; 58 | ack_prev_reg <= 0; 59 | end 60 | 61 | endcase 62 | end 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /examples/pipeline/top.v: -------------------------------------------------------------------------------- 1 | module top; 2 | 3 | parameter IDLE = 1'd0; 4 | parameter PIPELINE_IS_ACKED = 1'd1; 5 | 6 | reg clk = 0; 7 | reg reset = 1; 8 | wire pipeline_DOR; 9 | reg ack_to_pipeline_reg = 0; 10 | reg [7:0] data_in = 8'd42; 11 | reg [7:0] data_out_reg = 8'd0; 12 | reg pipeline_DIR; 13 | wire [7:0] data_out; 14 | reg state = IDLE; 15 | 16 | always #5 clk = !clk; 17 | 18 | assign ack_to_pipeline = ack_to_pipeline_reg; 19 | 20 | initial 21 | begin 22 | $display("Starting pipeline example"); 23 | $dumpfile("top.vcd"); 24 | $dumpvars(0, top); 25 | # 10 reset = 0; 26 | # 20 pipeline_DIR = 1; 27 | # 30 pipeline_DIR = 0; 28 | # 200 $stop; 29 | $finish; 30 | end 31 | 32 | pipeline p(clk, reset, pipeline_DOR, pipeline_DIR, ack_to_pipeline, ack_from_pipeline, data_in, data_out); 33 | 34 | always @(posedge clk) 35 | begin 36 | if (reset) 37 | begin 38 | state <= IDLE; 39 | ack_to_pipeline_reg <= 0; 40 | end 41 | else 42 | begin 43 | case (state) 44 | 45 | IDLE: 46 | begin 47 | if (pipeline_DOR) 48 | begin 49 | data_out_reg <= data_out; 50 | $display("Pipeline outputs %d", data_out); 51 | ack_to_pipeline_reg <= 1; 52 | state <= PIPELINE_IS_ACKED; 53 | end 54 | else 55 | begin 56 | state <= IDLE; 57 | ack_to_pipeline_reg <= 0; 58 | end 59 | end 60 | 61 | PIPELINE_IS_ACKED: 62 | begin 63 | $display("We acked the pipeline"); 64 | ack_to_pipeline_reg <= 0; 65 | state <= IDLE; 66 | end 67 | 68 | endcase 69 | end 70 | end 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /src/Makefile: -------------------------------------------------------------------------------- 1 | all: top ram0.data ram1.data ram2.data ram3.data 2 | 3 | run: all 4 | vvp top 5 | 6 | top: top.v pipeline.v instruction_fetch.v ram.v memory_controller.v instruction_decode.v instruction_execute.v i-cache.v d-cache.v 7 | iverilog -o $@ $^ 8 | 9 | %.data: genram 10 | ./genram 11 | chmod 640 ram*.data 12 | 13 | genram: genram.c 14 | $(CC) $(CFLAGS) $^ -o $@ 15 | 16 | clean: 17 | $(RM) -rf top genram 18 | 19 | top.vcd: top 20 | $(MAKE) run 21 | 22 | wave: top.vcd 23 | gtkwave top.vcd 24 | 25 | .PHONY: all clean wave 26 | -------------------------------------------------------------------------------- /src/d-cache.v: -------------------------------------------------------------------------------- 1 | /* 2 | * This is the L1 Data Cache for TinyCPU 3 | * Author : Yann Sionneau 4 | */ 5 | module dcache( 6 | input clk, 7 | input reset, 8 | 9 | input [15:0] addr, // 64 kB of total memory 10 | input en, 11 | input we, 12 | 13 | output [31:0] cache_do, 14 | output ack, 15 | 16 | output [15:0] main_memory_addr, 17 | output main_memory_en, 18 | output main_memory_we, 19 | output [31:0] main_memory_di, 20 | input main_memory_ack, 21 | input [31:0] main_memory_do 22 | ); 23 | 24 | /* 25 | * D-Cache size is 8 kB 26 | * 1024 lines of 2 words ( 64 bits ) 27 | */ 28 | 29 | parameter IDLE = 2'd0; 30 | parameter CACHE_MISS = 2'd1; 31 | 32 | reg [1:0] state; 33 | 34 | reg [63:0] do; 35 | reg [2:0] tag_do; 36 | reg [63:0] icache[1023:0]; 37 | reg [2:0] tag[1023:0]; 38 | 39 | reg update_cache; 40 | reg ack_reg; 41 | 42 | reg main_memory_en_reg; 43 | reg main_memory_we_reg; 44 | reg main_memory_addr_reg; 45 | reg cache_do_reg; 46 | 47 | assign main_memory_en = main_memory_en_reg; 48 | assign main_memory_we = main_memory_we_reg; 49 | assign main_memory_addr = main_memory_addr_reg; 50 | assign ack = ack_reg; 51 | assign cache_do = cache_do_reg; 52 | 53 | always @(posedge clk) 54 | begin 55 | if ( ~reset ) 56 | begin 57 | if (update_cache) 58 | icache[ addr[12:3] ] <= main_memory_do; 59 | 60 | do <= icache[ addr[12:3] ]; 61 | end 62 | end 63 | 64 | always @(posedge clk) 65 | begin 66 | if ( ~reset ) 67 | begin 68 | if (update_cache) 69 | tag[ addr[12:3] ] <= addr[15:13]; 70 | 71 | tag_do <= tag[ addr[12:3] ]; 72 | end 73 | end 74 | 75 | 76 | always @(posedge clk) 77 | begin 78 | 79 | if (reset) 80 | begin 81 | state <= IDLE; 82 | ack_reg <= 0; 83 | main_memory_en_reg <= 0; 84 | main_memory_we_reg <= 0; 85 | end 86 | else 87 | begin 88 | 89 | case ( state ) 90 | IDLE: 91 | begin 92 | if (en) 93 | begin 94 | if (addr[15:13] == tag_do) 95 | begin 96 | state <= CACHE_MISS; 97 | main_memory_addr_reg <= addr; 98 | main_memory_en_reg <= 1; 99 | main_memory_we_reg <= 0; 100 | ack_reg <= 0; 101 | end 102 | else 103 | begin 104 | ack_reg <= 1; 105 | state <= IDLE; 106 | if (addr[1]) 107 | cache_do_reg <= do[31:0]; 108 | else 109 | cache_do_reg <= do[63:32]; 110 | end 111 | end 112 | else 113 | begin 114 | ack_reg <= 0; 115 | state <= IDLE; 116 | end 117 | end 118 | 119 | CACHE_MISS: 120 | begin 121 | if (main_memory_ack) 122 | begin 123 | cache_do_reg <= main_memory_do; 124 | ack_reg <= 1; 125 | state <= IDLE; 126 | end 127 | else 128 | begin 129 | state <= CACHE_MISS; // waiting for slow main memory to answer 130 | ack_reg <= 0; 131 | end 132 | end 133 | endcase 134 | 135 | end 136 | end 137 | 138 | endmodule 139 | -------------------------------------------------------------------------------- /src/genram.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | int ram0, ram1, ram2, ram3; 7 | unsigned int max_temp = 1024; 8 | 9 | void write_to_ram(const char *op) { 10 | write(ram3, op, sizeof(const char)*2); 11 | write(ram3, "\n", sizeof(char)); 12 | 13 | write(ram2, op + sizeof(const char) * 2, sizeof(const char)*2); 14 | write(ram2, "\n", sizeof(char)); 15 | 16 | write(ram1, op + sizeof(const char) * 4, sizeof(const char)*2); 17 | write(ram1, "\n", sizeof(char)); 18 | 19 | write(ram0, op + sizeof(const char) * 6, sizeof(const char)*2); 20 | write(ram0, "\n", sizeof(char)); 21 | max_temp--; 22 | } 23 | 24 | int main(void) { 25 | 26 | unsigned int i = 0; 27 | unsigned int max; 28 | mode_t mode = S_IWGRP | S_IWOTH; 29 | umask(mode); 30 | 31 | ram0 = open("ram0.data", O_WRONLY | O_CREAT); 32 | ram1 = open("ram1.data", O_WRONLY | O_CREAT); 33 | ram2 = open("ram2.data", O_WRONLY | O_CREAT); 34 | ram3 = open("ram3.data", O_WRONLY | O_CREAT); 35 | 36 | write_to_ram("00430820"); 37 | write_to_ram("00431020"); 38 | write_to_ram("00221820"); 39 | write_to_ram("8C050014"); 40 | write_to_ram("AAAAAAAA"); 41 | write_to_ram("BBBBBBBB"); 42 | 43 | max = max_temp; 44 | for (i = 0 ; i < max ; ++i) 45 | write_to_ram("00000000"); 46 | 47 | close(ram0); 48 | close(ram1); 49 | close(ram2); 50 | close(ram3); 51 | 52 | return EXIT_SUCCESS; 53 | } 54 | -------------------------------------------------------------------------------- /src/i-cache.v: -------------------------------------------------------------------------------- 1 | /* 2 | * This is the L1 Instruction Cache for TinyCPU 3 | * Author : Yann Sionneau 4 | */ 5 | module icache( 6 | input clk, 7 | input reset, 8 | 9 | input [15:0] addr, // 64 kB of total memory 10 | input en, 11 | 12 | output [31:0] cache_do, 13 | output ack, 14 | 15 | output [15:0] main_memory_addr, 16 | output main_memory_en, 17 | input main_memory_ack, 18 | input [31:0] main_memory_do 19 | ); 20 | 21 | /* 22 | * I-Cache size is 8 kB 23 | * 1024 lines of 2 words ( 64 bits ) 24 | */ 25 | 26 | parameter IDLE = 2'd0; 27 | parameter CACHE_MISS = 2'd1; 28 | 29 | reg [1:0] state; 30 | 31 | reg [63:0] do; 32 | reg [2:0] tag_do; 33 | reg [63:0] icache[1023:0]; 34 | reg [2:0] tag[1023:0]; 35 | 36 | reg update_cache; 37 | reg ack_reg; 38 | 39 | reg main_memory_en_reg; 40 | reg main_memory_we_reg; 41 | reg main_memory_addr_reg; 42 | reg cache_do_reg; 43 | 44 | assign main_memory_en = main_memory_en_reg; 45 | assign main_memory_we = main_memory_we_reg; 46 | assign main_memory_addr = main_memory_addr_reg; 47 | assign ack = ack_reg; 48 | assign cache_do = cache_do_reg; 49 | 50 | always @(posedge clk) 51 | begin 52 | if ( ~reset ) 53 | begin 54 | if (update_cache) 55 | icache[ addr[12:3] ] <= main_memory_do; 56 | 57 | do <= icache[ addr[12:3] ]; 58 | end 59 | end 60 | 61 | always @(posedge clk) 62 | begin 63 | if ( ~reset ) 64 | begin 65 | if (update_cache) 66 | tag[ addr[12:3] ] <= addr[15:13]; 67 | 68 | tag_do <= tag[ addr[12:3] ]; 69 | end 70 | end 71 | 72 | 73 | always @(posedge clk) 74 | begin 75 | 76 | if (reset) 77 | begin 78 | state <= IDLE; 79 | ack_reg <= 0; 80 | main_memory_en_reg <= 0; 81 | main_memory_we_reg <= 0; 82 | end 83 | else 84 | begin 85 | 86 | case ( state ) 87 | IDLE: 88 | begin 89 | if (en) 90 | begin 91 | if (addr[15:13] == tag_do) 92 | begin 93 | state <= CACHE_MISS; 94 | main_memory_addr_reg <= addr; 95 | main_memory_en_reg <= 1; 96 | main_memory_we_reg <= 0; 97 | ack_reg <= 0; 98 | end 99 | else 100 | begin 101 | ack_reg <= 1; 102 | state <= IDLE; 103 | if (addr[1]) 104 | cache_do_reg <= do[31:0]; 105 | else 106 | cache_do_reg <= do[63:32]; 107 | end 108 | end 109 | else 110 | begin 111 | ack_reg <= 0; 112 | state <= IDLE; 113 | end 114 | end 115 | 116 | CACHE_MISS: 117 | begin 118 | if (main_memory_ack) 119 | begin 120 | cache_do_reg <= main_memory_do; 121 | ack_reg <= 1; 122 | state <= IDLE; 123 | end 124 | else 125 | begin 126 | state <= CACHE_MISS; // waiting for slow main memory to answer 127 | ack_reg <= 0; 128 | end 129 | end 130 | endcase 131 | 132 | end 133 | end 134 | 135 | endmodule 136 | -------------------------------------------------------------------------------- /src/instruction_decode.v: -------------------------------------------------------------------------------- 1 | module instruction_decoder( 2 | input clk, 3 | input reset, 4 | /* Data Out Ready */ 5 | output DOR, 6 | /* Data In Ready */ 7 | input DIR, 8 | input ack_from_next, 9 | output ack_prev, 10 | input [31:0] data_in, 11 | output [31:0] data_out_instruction, 12 | output [31:0] data_out_S, 13 | output [31:0] data_out_T 14 | ); 15 | 16 | /* values for the Finite State Machine of the decoder and executer */ 17 | parameter IDLE = 0; 18 | parameter WAITING_ACK = 1; 19 | 20 | reg state = IDLE; 21 | 22 | parameter INST_TYPE_R = 2'd0; 23 | parameter INST_TYPE_I = 2'd1; 24 | parameter INST_TYPE_J = 2'd2; 25 | 26 | reg [1:0] instruction_type = INST_TYPE_R; 27 | 28 | reg [31:0] data_out_reg = 32'd0; 29 | reg DOR_reg = 0; 30 | reg ack_prev_reg = 0; 31 | reg [31:0] instruction; 32 | reg [31:0] D, S, T; /* registers for instruction execution */ 33 | reg [15:0] C; /* 16-bits immediate value */ 34 | reg [15:0] address; 35 | 36 | reg [15:0] mem_addr_reg; 37 | reg mem_we_reg; 38 | reg mem_en_reg; 39 | reg [31:0] mem_di_reg; 40 | reg [3:0] mem_bank_select_reg; 41 | 42 | assign mem_addr = mem_addr_reg; 43 | assign mem_di = mem_di_reg; 44 | assign mem_we = mem_we_reg; 45 | assign mem_en = mem_en_reg; 46 | assign mem_bank_select = mem_bank_select_reg; 47 | 48 | assign data_out = data_out_reg; 49 | assign DOR = DOR_reg; 50 | assign ack_prev = ack_prev_reg; 51 | 52 | /* The MIPS32 registers */ 53 | reg [31:0] regs[31:0]; 54 | reg [31:0] regs_do1; 55 | reg [31:0] regs_do2; 56 | wire [31:0] regs_di1; 57 | wire [31:0] regs_di2; 58 | wire [4:0] regs_index1; 59 | wire [4:0] regs_index2; 60 | wire regs_we1; 61 | wire regs_we2; 62 | reg regs_we1_reg; 63 | reg regs_we2_reg; 64 | reg [4:0] regs_index1_reg; 65 | reg [4:0] regs_index2_reg; 66 | 67 | always @(posedge clk) 68 | begin 69 | if ( ~reset ) 70 | begin 71 | if (regs_we1) 72 | regs[ regs_index1 ] <= regs_di1; 73 | regs_do1 <= regs[ regs_index1 ]; 74 | end 75 | end 76 | 77 | always @(posedge clk) 78 | begin 79 | if ( ~reset ) 80 | begin 81 | if (regs_we2) 82 | regs[ regs_index2 ] <= regs_di2; 83 | regs_do2 <= regs[ regs_index2 ]; 84 | end 85 | end 86 | 87 | assign regs_index1 = regs_index1_reg; 88 | assign regs_index2 = regs_index2_reg; 89 | assign regs_we1 = regs_we1_reg; 90 | assign regs_we2 = regs_we2_reg; 91 | 92 | /* The decoder and executer FSM (Finite State Machine) */ 93 | always @(posedge clk) 94 | begin 95 | if (reset) 96 | begin 97 | state <= IDLE; 98 | data_out_reg <= 0; 99 | DOR_reg <= 0; 100 | ack_prev_reg <= 0; 101 | mem_addr_reg <= 16'd0; 102 | mem_di_reg <= 32'd0; 103 | mem_en_reg <= 0; 104 | mem_we_reg <= 0; 105 | mem_bank_select_reg <= 4'b1111; 106 | regs_we1_reg <= 0; 107 | regs_we2_reg <= 0; 108 | end 109 | else 110 | begin 111 | case (state) 112 | 113 | IDLE: 114 | begin 115 | if (DIR) 116 | begin 117 | $display("instruction decoder receives input_data 0x%08X", data_in); 118 | ack_prev_reg <= 1; 119 | case ( data_in[31:26] ) 120 | 121 | 6'd0: 122 | begin 123 | regs_index1_reg <= data_in[25:21]; 124 | regs_index2_reg <= data_in[20:16]; 125 | C <= data_in[15:0]; 126 | instruction_type <= INST_TYPE_R; 127 | end 128 | 129 | 6'd2: 130 | begin 131 | instruction_type <= INST_TYPE_J; 132 | end 133 | 134 | 6'd3: 135 | begin 136 | instruction_type <= INST_TYPE_J; 137 | end 138 | 139 | 140 | default: 141 | begin 142 | instruction_type <= INST_TYPE_I; 143 | end 144 | 145 | 146 | endcase 147 | state <= WAITING_ACK; 148 | end 149 | end 150 | 151 | WAITING_ACK: 152 | begin 153 | if (ack_from_next) 154 | begin 155 | $display("instruction decoder got ACK form next stage"); 156 | DOR_reg <= 0; 157 | state <= IDLE; 158 | end 159 | else 160 | begin 161 | S <= regs_do1; 162 | T <= regs_do2; 163 | state <= WAITING_ACK; 164 | DOR_reg <= 1; 165 | end 166 | ack_prev_reg <= 0; 167 | end 168 | 169 | endcase 170 | end 171 | end 172 | 173 | endmodule 174 | -------------------------------------------------------------------------------- /src/instruction_execute.v: -------------------------------------------------------------------------------- 1 | module instruction_executer( 2 | input clk, 3 | input reset, 4 | output DOR, 5 | input DIR, 6 | input ack_from_next, 7 | output ack_prev, 8 | input [31:0] data_in, 9 | output [31:0] data_out, 10 | 11 | output cache_en, 12 | output [15:0] cache_addr, 13 | input [31:0] cache_do, 14 | input cache_ack 15 | ); 16 | 17 | parameter IDLE = 2'd0; 18 | parameter WAITING_ACK_FROM_MEMORY_CONTROLLER = 2'd1; 19 | parameter WAITING_ACK_FROM_NEXT_STAGE = 2'd2; 20 | 21 | reg [1:0] state = IDLE; 22 | reg [31:0] data_out_reg = 32'd0; 23 | reg DOR_reg = 0; 24 | reg ack_prev_reg = 0; 25 | reg [31:0] data_in_buffer; 26 | reg [15:0] cache_addr_reg = 16'd0; 27 | reg cache_en_reg = 0; 28 | reg [31:0] data_in_cached = 32'd0; 29 | 30 | 31 | assign data_out = data_out_reg; 32 | assign DOR = DOR_reg; 33 | assign ack_prev = ack_prev_reg; 34 | assign cache_addr = cache_addr_reg; 35 | assign cache_en = cache_en_reg; 36 | assign cache_di = 32'd0; 37 | 38 | always @(posedge clk) 39 | begin 40 | if (reset) 41 | begin 42 | state <= IDLE; 43 | data_out_reg <= 0; 44 | DOR_reg <= 0; 45 | ack_prev_reg <= 0; 46 | cache_addr_reg <= 16'd0; 47 | cache_en_reg <= 0; 48 | data_in_cached <= 32'd0; 49 | end 50 | else 51 | begin 52 | case (state) 53 | 54 | IDLE: 55 | begin 56 | if (DIR) 57 | begin 58 | $display("Executing instruction %08X", data_in); 59 | state <= WAITING_ACK_FROM_MEMORY_CONTROLLER; 60 | ack_prev_reg <= 1; 61 | cache_en_reg <= 1; 62 | DOR_reg <= 0; 63 | data_in_cached <= data_in; 64 | cache_addr_reg <= { 2'd0, data_in[13:2] }; 65 | end 66 | else 67 | begin 68 | cache_en_reg <= 0; 69 | DOR_reg <= 0; 70 | cache_addr_reg <= data_in; 71 | end 72 | end 73 | 74 | WAITING_ACK_FROM_MEMORY_CONTROLLER: 75 | begin 76 | if (cache_ack) 77 | begin 78 | $display("instruction fetcher fetched 0x%02X from PC = 0x%02X", cache_do, data_in_cached); 79 | data_out_reg <= cache_do; 80 | DOR_reg <= 1; 81 | cache_en_reg <= 0; 82 | state <= WAITING_ACK_FROM_NEXT_STAGE; 83 | end 84 | else 85 | begin 86 | state <= WAITING_ACK_FROM_MEMORY_CONTROLLER; 87 | DOR_reg <= 0; 88 | cache_en_reg <= 1; 89 | end 90 | ack_prev_reg <= 0; 91 | end 92 | 93 | WAITING_ACK_FROM_NEXT_STAGE: 94 | begin 95 | if (ack_from_next) 96 | begin 97 | $display("instruction_fetcher got ACK from next stage"); 98 | DOR_reg <= 0; 99 | cache_en_reg <= 0; 100 | state <= IDLE; 101 | end 102 | else 103 | begin 104 | DOR_reg <= 1; 105 | cache_en_reg <= 0; 106 | state <= WAITING_ACK_FROM_NEXT_STAGE; 107 | end 108 | end 109 | 110 | endcase 111 | end 112 | end 113 | 114 | endmodule 115 | -------------------------------------------------------------------------------- /src/instruction_fetch.v: -------------------------------------------------------------------------------- 1 | module instruction_fetch( 2 | input clk, 3 | input reset, 4 | output DOR, 5 | input DIR, 6 | input ack_from_next, 7 | output ack_prev, 8 | input [31:0] data_in, 9 | output [31:0] data_out, 10 | 11 | output cache_en, 12 | output [15:0] cache_addr, 13 | input [31:0] cache_do, 14 | input cache_do_ack 15 | ); 16 | 17 | parameter IDLE = 2'd0; 18 | parameter WAITING_ACK_FROM_I_CACHE = 2'd1; 19 | parameter WAITING_ACK_FROM_NEXT_STAGE = 2'd2; 20 | 21 | reg [1:0] state = IDLE; 22 | reg [31:0] data_out_reg = 32'd0; 23 | reg DOR_reg = 0; 24 | reg ack_prev_reg = 0; 25 | reg [31:0] data_in_buffer; 26 | reg [15:0] cache_addr_reg = 16'd0; 27 | reg cache_en_reg = 0; 28 | reg [31:0] data_in_cached = 32'd0; 29 | 30 | 31 | assign data_out = data_out_reg; 32 | assign DOR = DOR_reg; 33 | assign ack_prev = ack_prev_reg; 34 | assign cache_addr = cache_addr_reg; 35 | assign cache_en = cache_en_reg; 36 | 37 | always @(posedge clk) 38 | begin 39 | if (reset) 40 | begin 41 | state <= IDLE; 42 | data_out_reg <= 0; 43 | DOR_reg <= 0; 44 | ack_prev_reg <= 0; 45 | cache_addr_reg <= 16'd0; 46 | cache_en_reg <= 0; 47 | data_in_cached <= 32'd0; 48 | end 49 | else 50 | begin 51 | case (state) 52 | 53 | IDLE: 54 | begin 55 | if (DIR) 56 | begin 57 | $display("Fetching opcode @ PC = %02X", data_in); 58 | state <= WAITING_ACK_FROM_I_CACHE; 59 | ack_prev_reg <= 1; 60 | cache_en_reg <= 1; 61 | DOR_reg <= 0; 62 | data_in_cached <= data_in; 63 | cache_addr_reg <= { 2'd0, data_in[9:2] }; 64 | end 65 | else 66 | begin 67 | cache_en_reg <= 0; 68 | DOR_reg <= 0; 69 | cache_addr_reg <= data_in; 70 | end 71 | end 72 | 73 | WAITING_ACK_FROM_I_CACHE: 74 | begin 75 | if (cache_do_ack) 76 | begin 77 | $display("instruction fetcher fetched 0x%02X from PC = 0x%02X", cache_do, data_in_cached); 78 | data_out_reg <= cache_do; 79 | DOR_reg <= 1; 80 | cache_en_reg <= 0; 81 | state <= WAITING_ACK_FROM_NEXT_STAGE; 82 | end 83 | else 84 | begin 85 | state <= WAITING_ACK_FROM_I_CACHE; 86 | DOR_reg <= 0; 87 | cache_en_reg <= 1; 88 | end 89 | ack_prev_reg <= 0; 90 | end 91 | 92 | WAITING_ACK_FROM_NEXT_STAGE: 93 | begin 94 | if (ack_from_next) 95 | begin 96 | $display("instruction_fetcher got ACK from next stage"); 97 | DOR_reg <= 0; 98 | cache_en_reg <= 0; 99 | state <= IDLE; 100 | end 101 | else 102 | begin 103 | DOR_reg <= 1; 104 | cache_en_reg <= 0; 105 | state <= WAITING_ACK_FROM_NEXT_STAGE; 106 | end 107 | end 108 | 109 | endcase 110 | end 111 | end 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /src/memory_controller.v: -------------------------------------------------------------------------------- 1 | module memory_controller(clk, 2 | reset, 3 | devices_burst_en, 4 | devices_mem_en, 5 | device_1_mem_addr, 6 | device_2_mem_addr, 7 | device_3_mem_addr, 8 | device_1_mem_di, 9 | device_2_mem_di, 10 | device_3_mem_di, 11 | device_1_bank_select, 12 | device_2_bank_select, 13 | device_3_bank_select, 14 | devices_mem_we, 15 | devices_do_ack, 16 | mem_do); 17 | 18 | input clk; 19 | input reset; 20 | input [2:0] devices_burst_en; 21 | input [2:0] devices_mem_en; 22 | input [15:0] device_1_mem_addr; 23 | input [15:0] device_2_mem_addr; 24 | input [15:0] device_3_mem_addr; 25 | input [31:0] device_1_mem_di; 26 | input [31:0] device_2_mem_di; 27 | input [31:0] device_3_mem_di; 28 | input [3:0] device_1_bank_select; 29 | input [3:0] device_2_bank_select; 30 | input [3:0] device_3_bank_select; 31 | input [2:0] devices_mem_we; 32 | output [2:0] devices_do_ack; 33 | output [31:0] mem_do; 34 | 35 | parameter DEVICE_1 = 3'd0; 36 | parameter DEVICE_2 = 3'd1; 37 | parameter DEVICE_3 = 3'd2; 38 | parameter NO_ONE = 3'b111; 39 | 40 | reg mem_enable = 0; 41 | reg [15:0] mem_addr = 16'd0; 42 | reg [31:0] mem_di = 32'd0; 43 | reg [2:0] current_slave = NO_ONE; 44 | reg [2:0] previous_slave = NO_ONE; 45 | reg mem_we = 0; 46 | reg [2:0] devices_do_ack = 3'd0; 47 | reg [3:0] mem_bank_select = 4'b1111; 48 | 49 | always @(posedge clk) 50 | begin 51 | if (reset) 52 | begin 53 | current_slave <= NO_ONE; 54 | end 55 | else 56 | begin 57 | case (current_slave) 58 | NO_ONE: 59 | begin 60 | if (devices_mem_en[0] && previous_slave != DEVICE_1) 61 | begin 62 | current_slave <= DEVICE_1; 63 | mem_bank_select <= device_1_bank_select; 64 | mem_addr <= device_1_mem_addr; 65 | mem_di <= device_1_mem_di; 66 | mem_we <= devices_mem_we[0]; 67 | end 68 | else if (devices_mem_en[1] && previous_slave != DEVICE_2) 69 | begin 70 | current_slave <= DEVICE_2; 71 | mem_bank_select <= device_2_bank_select; 72 | mem_addr <= device_2_mem_addr; 73 | mem_di <= device_2_mem_di; 74 | mem_we <= devices_mem_we[1]; 75 | end 76 | else if (devices_mem_en[2] && previous_slave != DEVICE_3) 77 | begin 78 | current_slave <= DEVICE_3; 79 | mem_bank_select <= device_3_bank_select; 80 | mem_addr <= device_3_mem_addr; 81 | mem_di <= device_3_mem_di; 82 | mem_we <= devices_mem_we[2]; 83 | end 84 | else 85 | begin 86 | current_slave <= NO_ONE; 87 | mem_bank_select <= 4'd0; 88 | mem_addr <= 16'd0; 89 | mem_di <= 32'd0; 90 | mem_we <= 0; 91 | end 92 | previous_slave <= NO_ONE; 93 | devices_do_ack <= 3'b000; 94 | end 95 | 96 | DEVICE_1: 97 | begin 98 | if (devices_mem_en[1]) 99 | begin 100 | current_slave <= DEVICE_2; 101 | mem_bank_select <= device_2_bank_select; 102 | mem_addr <= device_2_mem_addr; 103 | mem_di <= device_2_mem_di; 104 | mem_we <= devices_mem_we[1]; 105 | end 106 | else if (devices_mem_en[2]) 107 | begin 108 | current_slave <= DEVICE_3; 109 | mem_bank_select <= device_3_bank_select; 110 | mem_addr <= device_3_mem_addr; 111 | mem_di <= device_3_mem_di; 112 | mem_we <= devices_mem_we[2]; 113 | end 114 | else 115 | begin 116 | if (devices_burst_en[0] && devices_mem_en[0]) 117 | begin 118 | devices_do_ack <= 3'b001; 119 | mem_addr <= device_1_mem_addr + 4; 120 | mem_di <= device_1_mem_di; 121 | end 122 | else 123 | begin 124 | current_slave <= NO_ONE; 125 | mem_bank_select <= 4'd0; 126 | mem_addr <= 16'd0; 127 | mem_di <= 32'd0; 128 | mem_we <= 0; 129 | end 130 | end 131 | devices_do_ack <= 3'b001; 132 | previous_slave <= DEVICE_1; 133 | end 134 | 135 | DEVICE_2: 136 | begin 137 | if (devices_mem_en[2]) 138 | begin 139 | current_slave <= DEVICE_3; 140 | mem_bank_select <= device_3_bank_select; 141 | mem_addr <= device_3_mem_addr; 142 | mem_di <= device_3_mem_di; 143 | mem_we <= devices_mem_we[2]; 144 | end 145 | else if (devices_mem_en[0]) 146 | begin 147 | current_slave <= DEVICE_1; 148 | mem_bank_select <= device_1_bank_select; 149 | mem_addr <= device_1_mem_addr; 150 | mem_di <= device_1_mem_di; 151 | mem_we <= devices_mem_we[0]; 152 | end 153 | else 154 | begin 155 | current_slave <= NO_ONE; 156 | mem_bank_select <= 4'd0; 157 | mem_addr <= 16'd0; 158 | mem_di <= 32'd0; 159 | mem_we <= 0; 160 | end 161 | devices_do_ack <= 3'b010; 162 | previous_slave <= DEVICE_2; 163 | end 164 | 165 | DEVICE_3: 166 | begin 167 | if (devices_mem_en[0]) 168 | begin 169 | current_slave <= DEVICE_1; 170 | mem_bank_select <= device_1_bank_select; 171 | mem_addr <= device_1_mem_addr; 172 | mem_di <= device_1_mem_di; 173 | mem_we <= devices_mem_we[0]; 174 | end 175 | else if (devices_mem_en[1]) 176 | begin 177 | current_slave <= DEVICE_2; 178 | mem_bank_select <= device_2_bank_select; 179 | mem_addr <= device_2_mem_addr; 180 | mem_di <= device_2_mem_di; 181 | mem_we <= devices_mem_we[1]; 182 | end 183 | else 184 | begin 185 | current_slave <= NO_ONE; 186 | mem_bank_select <= 4'd0; 187 | mem_addr <= 16'd0; 188 | mem_di <= 32'd0; 189 | mem_we <= 0; 190 | end 191 | devices_do_ack <= 3'b100; 192 | previous_slave <= DEVICE_3; 193 | end 194 | endcase 195 | end 196 | end 197 | 198 | ram mem(clk, mem_bank_select, ~reset, mem_addr, mem_di, mem_do, mem_we); 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /src/pipeline.v: -------------------------------------------------------------------------------- 1 | module pipeline( 2 | input clk, 3 | input reset, 4 | output DOR, 5 | input DIR, 6 | input ack_to_pipeline, 7 | output ack_from_pipeline, 8 | input [31:0] data_in, 9 | output [31:0] data_out, 10 | 11 | output [15:0] device_1_mem_addr, 12 | output [31:0] device_1_mem_di, 13 | output [15:0] device_2_mem_addr, 14 | output [31:0] device_2_mem_di, 15 | output [3:0] device_2_bank_select, 16 | output [1:0] devices_burst_en, 17 | output [1:0] devices_mem_we, 18 | output [1:0] devices_mem_en, 19 | input [1:0] devices_do_ack, 20 | 21 | input [31:0] mem_do 22 | ); 23 | 24 | /* No burst access to ram allowed for now */ 25 | assign device_1_burst_en = 0; 26 | 27 | assign device_1_mem_di = 32'd0; 28 | 29 | wire DOR_IF; /* Data Out Ready */ 30 | wire DIR_IF; 31 | 32 | wire ack_to_IF; 33 | wire ack_from_IF; 34 | 35 | wire ack_to_ID; 36 | wire ack_from_ID; 37 | 38 | wire DOR_ID; 39 | wire DIR_ID; 40 | 41 | wire [31:0] data_in_ID; 42 | wire [31:0] data_out_ID; 43 | 44 | wire [31:0] data_in_IF; 45 | wire [31:0] data_out_IF; 46 | wire [31:0] data_out_instruction_ID; 47 | wire [31:0] data_out_S_ID; 48 | wire [31:0] data_out_T_ID; 49 | 50 | wire [31:0] data_in_EX; 51 | wire [31:0] data_out_EX; 52 | 53 | assign DIR_IF = DIR; 54 | assign DIR_ID = DOR_IF; 55 | assign DIR_EX = DOR_ID; 56 | assign DOR = DOR_EX; 57 | 58 | assign data_in_IF = data_in; 59 | assign data_in_ID = data_out_IF; 60 | 61 | assign data_in_instruction_EX = data_out_instruction_ID; 62 | assign data_in_S_EX = data_out_S_ID; 63 | assign data_in_T_EX = data_out_T_ID; 64 | 65 | assign data_out = data_out_EX; 66 | 67 | assign ack_from_pipeline = ack_from_IF; 68 | assign ack_to_EX = ack_to_pipeline; 69 | assign ack_to_ID = ack_from_EX; 70 | assign ack_to_IF = ack_from_ID; 71 | 72 | assign devices_mem_we[0] = 0; 73 | 74 | wire [31:0] icache_do; 75 | wire [31:0] dcache_do; 76 | wire [15:0] if_addr; 77 | wire [15:0] ex_addr; 78 | wire if_en; 79 | wire if_ack; 80 | wire ex_en; 81 | wire ex_ack; 82 | 83 | icache i_cache( 84 | clk, 85 | reset, 86 | 87 | if_addr, 88 | if_en, 89 | icache_do, 90 | if_ack, 91 | 92 | device_1_mem_addr, 93 | devices_mem_en[0], 94 | devices_do_ack[0], 95 | mem_do 96 | ); 97 | 98 | instruction_fetch IF ( 99 | clk, 100 | reset, 101 | DOR_IF, 102 | DIR_IF, 103 | ack_to_IF, 104 | ack_from_IF, 105 | data_in_IF, 106 | data_out_IF, 107 | 108 | if_en, 109 | if_addr, 110 | icache_do, 111 | if_ack 112 | ); 113 | 114 | instruction_decoder ID ( 115 | clk, 116 | reset, 117 | DOR_ID, 118 | DIR_ID, 119 | ack_to_ID, 120 | ack_from_ID, 121 | data_in_ID, 122 | data_out_instruction_ID, 123 | data_out_S_ID, 124 | data_out_T_ID 125 | ); 126 | 127 | dcache d_cache( 128 | clk, 129 | reset, 130 | 131 | ex_addr, 132 | ex_en, 133 | ex_we, 134 | dcache_do, 135 | ex_ack, 136 | 137 | device_2_mem_addr, 138 | devices_mem_en[1], 139 | devices_mem_we[1], 140 | device_2_mem_di, 141 | devices_do_ack[1], 142 | mem_do 143 | ); 144 | 145 | instruction_executer EX ( 146 | clk, 147 | reset, 148 | DOR_EX, 149 | DIR_EX, 150 | ack_to_EX, 151 | ack_from_EX, 152 | data_in_EX, 153 | data_out_EX, 154 | 155 | ex_en, 156 | ex_addr, 157 | dcache_do, 158 | ex_ack 159 | ); 160 | 161 | endmodule 162 | -------------------------------------------------------------------------------- /src/ram.v: -------------------------------------------------------------------------------- 1 | module ram(input clock, input [3:0] bank_select, input enable, input [15:0] addr, input [31:0] di, output [31:0] do, input we); 2 | 3 | reg [7:0] mem0 [1023:0]; 4 | reg [7:0] mem1 [1023:0]; 5 | reg [7:0] mem2 [1023:0]; 6 | reg [7:0] mem3 [1023:0]; 7 | reg [31:0] do; 8 | 9 | /* bank 0 */ 10 | always @(posedge clock) 11 | begin 12 | if (enable & bank_select[0]) 13 | begin 14 | if (we) 15 | begin 16 | mem0[addr] <= di[7:0]; 17 | end 18 | do[7:0] <= mem0[addr]; 19 | end 20 | end 21 | 22 | always @(posedge clock) 23 | begin 24 | if (enable & bank_select[1]) 25 | begin 26 | if (we) 27 | begin 28 | mem1[addr] <= di[15:8]; 29 | end 30 | do[15:8] <= mem1[addr]; 31 | end 32 | end 33 | 34 | always @(posedge clock) 35 | begin 36 | if (enable & bank_select[2]) 37 | begin 38 | if (we) 39 | begin 40 | mem2[addr] <= di[23:16]; 41 | end 42 | do[23:16] <= mem2[addr]; 43 | end 44 | end 45 | 46 | always @(posedge clock) 47 | begin 48 | if (enable & bank_select[3]) 49 | begin 50 | if (we) 51 | begin 52 | mem3[addr] <= di[31:24]; 53 | end 54 | do[31:24] <= mem3[addr]; 55 | end 56 | end 57 | 58 | initial 59 | begin 60 | $readmemh("ram0.data", mem0); 61 | $readmemh("ram1.data", mem1); 62 | $readmemh("ram2.data", mem2); 63 | $readmemh("ram3.data", mem3); 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /src/ram0.data: -------------------------------------------------------------------------------- 1 | 20 2 | 20 3 | 20 4 | 14 5 | AA 6 | BB 7 | 00 8 | 00 9 | 00 10 | 00 11 | 00 12 | 00 13 | 00 14 | 00 15 | 00 16 | 00 17 | 00 18 | 00 19 | 00 20 | 00 21 | 00 22 | 00 23 | 00 24 | 00 25 | 00 26 | 00 27 | 00 28 | 00 29 | 00 30 | 00 31 | 00 32 | 00 33 | 00 34 | 00 35 | 00 36 | 00 37 | 00 38 | 00 39 | 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00 931 | 00 932 | 00 933 | 00 934 | 00 935 | 00 936 | 00 937 | 00 938 | 00 939 | 00 940 | 00 941 | 00 942 | 00 943 | 00 944 | 00 945 | 00 946 | 00 947 | 00 948 | 00 949 | 00 950 | 00 951 | 00 952 | 00 953 | 00 954 | 00 955 | 00 956 | 00 957 | 00 958 | 00 959 | 00 960 | 00 961 | 00 962 | 00 963 | 00 964 | 00 965 | 00 966 | 00 967 | 00 968 | 00 969 | 00 970 | 00 971 | 00 972 | 00 973 | 00 974 | 00 975 | 00 976 | 00 977 | 00 978 | 00 979 | 00 980 | 00 981 | 00 982 | 00 983 | 00 984 | 00 985 | 00 986 | 00 987 | 00 988 | 00 989 | 00 990 | 00 991 | 00 992 | 00 993 | 00 994 | 00 995 | 00 996 | 00 997 | 00 998 | 00 999 | 00 1000 | 00 1001 | 00 1002 | 00 1003 | 00 1004 | 00 1005 | 00 1006 | 00 1007 | 00 1008 | 00 1009 | 00 1010 | 00 1011 | 00 1012 | 00 1013 | 00 1014 | 00 1015 | 00 1016 | 00 1017 | 00 1018 | 00 1019 | 00 1020 | 00 1021 | 00 1022 | 00 1023 | 00 1024 | 00 1025 | -------------------------------------------------------------------------------- /src/top.v: -------------------------------------------------------------------------------- 1 | module top; 2 | 3 | parameter WAITING_ACK_FROM_PIPELINE = 0; 4 | parameter PIPELINE_ACKED = 1; 5 | 6 | parameter WAITING_DOR_FROM_PIPELINE = 0; 7 | parameter PIPELINE_IS_ACKED = 1; 8 | 9 | reg clk = 0; 10 | reg reset = 1; 11 | wire pipeline_DOR; 12 | reg ack_to_pipeline_reg = 0; 13 | reg [31:0] data_in = 32'd0; 14 | reg [31:0] data_out_reg = 32'd0; 15 | reg pipeline_DIR; 16 | wire [31:0] data_out; 17 | reg state = WAITING_ACK_FROM_PIPELINE; 18 | reg ack_state = WAITING_DOR_FROM_PIPELINE; 19 | wire [31:0] mem_do; 20 | 21 | wire [2:0] devices_mem_en; 22 | wire [2:0] devices_burst_en; 23 | wire [15:0] device_1_mem_addr; 24 | wire [15:0] device_2_mem_addr; 25 | reg [15:0] device_3_mem_addr = 16'd0; 26 | wire [31:0] device_1_mem_di; 27 | wire [31:0] device_2_mem_di; 28 | reg [31:0] device_3_mem_di = 32'd0; 29 | wire [3:0] device_2_bank_select; 30 | reg [3:0] device_3_bank_select = 4'd1; 31 | wire [2:0] devices_mem_we; 32 | wire [2:0] devices_do_ack; 33 | wire mem_en; 34 | 35 | reg [31:0] PC = 32'd0; 36 | 37 | always #5 clk = !clk; 38 | 39 | assign ack_to_pipeline = ack_to_pipeline_reg; 40 | assign devices_mem_en[2] = 0; 41 | assign devices_burst_en[2] = 0; 42 | assign devices_mem_we[2] = 0; 43 | assign devices_do_ack[2] = 0; 44 | 45 | initial 46 | begin 47 | $display("Starting Instruction Pipeline example"); 48 | $dumpfile("top.vcd"); 49 | $dumpvars(0, top); 50 | 51 | #20 52 | reset = 0; 53 | 54 | # 350 $stop; 55 | $finish; 56 | end 57 | 58 | memory_controller mem_cont(clk, 59 | reset, 60 | devices_burst_en, 61 | devices_mem_en, 62 | device_1_mem_addr, 63 | device_2_mem_addr, 64 | device_3_mem_addr, 65 | device_1_mem_di, 66 | device_2_mem_di, 67 | device_3_mem_di, 68 | 4'b1111, 69 | device_2_bank_select, 70 | device_3_bank_select, 71 | devices_mem_we, 72 | devices_do_ack, 73 | mem_do 74 | ); 75 | 76 | 77 | pipeline p( 78 | clk, 79 | reset, 80 | pipeline_DOR, 81 | pipeline_DIR, 82 | ack_to_pipeline, 83 | ack_from_pipeline, 84 | data_in, 85 | data_out, 86 | 87 | device_1_mem_addr, 88 | device_1_mem_di, 89 | device_2_mem_addr, 90 | device_2_mem_di, 91 | device_2_bank_select, 92 | devices_burst_en[1:0], 93 | devices_mem_we[1:0], 94 | devices_mem_en[1:0], 95 | devices_do_ack[1:0], 96 | mem_do 97 | ); 98 | 99 | always @(posedge clk) 100 | begin 101 | if (reset) 102 | begin 103 | state <= WAITING_ACK_FROM_PIPELINE; 104 | pipeline_DIR <= 0; 105 | data_in <= 0; 106 | PC <= 32'd0; 107 | end 108 | else 109 | begin 110 | case (state) 111 | 112 | WAITING_ACK_FROM_PIPELINE: 113 | begin 114 | if (ack_from_pipeline) 115 | begin 116 | pipeline_DIR <= 0; 117 | PC <= PC + 4; 118 | state <= PIPELINE_ACKED; 119 | end 120 | else 121 | begin 122 | data_in <= PC; 123 | pipeline_DIR <= 1; 124 | state <= WAITING_ACK_FROM_PIPELINE; 125 | end 126 | end 127 | 128 | PIPELINE_ACKED: 129 | begin 130 | if (ack_from_pipeline) 131 | begin 132 | state <= PIPELINE_ACKED; 133 | end 134 | else 135 | begin 136 | state <= WAITING_ACK_FROM_PIPELINE; 137 | end 138 | pipeline_DIR <= 0; 139 | end 140 | 141 | 142 | 143 | endcase 144 | end 145 | end 146 | 147 | always @(posedge clk) 148 | begin 149 | 150 | if (reset) 151 | begin 152 | ack_to_pipeline_reg <= 0; 153 | end 154 | else 155 | begin 156 | case (ack_state) 157 | 158 | WAITING_DOR_FROM_PIPELINE: 159 | begin 160 | if (pipeline_DOR) 161 | begin 162 | data_out_reg <= data_out; 163 | $display("Pipeline outputs %d", data_out); 164 | ack_to_pipeline_reg <= 1; 165 | ack_state <= PIPELINE_IS_ACKED; 166 | end 167 | else 168 | begin 169 | ack_state <= WAITING_DOR_FROM_PIPELINE; 170 | ack_to_pipeline_reg <= 0; 171 | end 172 | end 173 | 174 | PIPELINE_IS_ACKED: 175 | begin 176 | $display("We acked the pipeline"); 177 | ack_to_pipeline_reg <= 0; 178 | ack_state <= WAITING_DOR_FROM_PIPELINE; 179 | end 180 | 181 | endcase 182 | end 183 | end 184 | 185 | endmodule 186 | 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