├── .gitignore ├── LICENSE ├── README.md ├── impl └── artyz7.xdc ├── makefile ├── rtl ├── uart.vhd ├── uart_rx.vhd └── uart_tx.vhd └── sim ├── tb_uart_axis_lb.vhd ├── tb_uart_rt_lb.vhd ├── tb_uart_rx.vhd └── tb_uart_tx.vhd /.gitignore: -------------------------------------------------------------------------------- 1 | debug/ -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/README.md -------------------------------------------------------------------------------- /impl/artyz7.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/impl/artyz7.xdc -------------------------------------------------------------------------------- /makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/makefile -------------------------------------------------------------------------------- /rtl/uart.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/rtl/uart.vhd -------------------------------------------------------------------------------- /rtl/uart_rx.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/rtl/uart_rx.vhd -------------------------------------------------------------------------------- /rtl/uart_tx.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/rtl/uart_tx.vhd -------------------------------------------------------------------------------- /sim/tb_uart_axis_lb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/sim/tb_uart_axis_lb.vhd -------------------------------------------------------------------------------- /sim/tb_uart_rt_lb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/sim/tb_uart_rt_lb.vhd -------------------------------------------------------------------------------- /sim/tb_uart_rx.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/sim/tb_uart_rx.vhd -------------------------------------------------------------------------------- /sim/tb_uart_tx.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fcayci/vhdl-axis-uart/HEAD/sim/tb_uart_tx.vhd --------------------------------------------------------------------------------