├── .gitignore ├── license ├── Readme.md └── vivadoLicence.lic ├── docs └── HowContribute.md ├── boards └── EGo1资料文档 │ ├── EGo1-板卡文件 │ └── EGo1 │ │ └── 1.0 │ │ └── board_part.xml │ └── EGo1-引脚约束文件 │ └── EGo1.xdc └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store -------------------------------------------------------------------------------- /license/Readme.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fengjixuchui/FPGA-1/HEAD/license/Readme.md -------------------------------------------------------------------------------- /license/vivadoLicence.lic: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fengjixuchui/FPGA-1/HEAD/license/vivadoLicence.lic -------------------------------------------------------------------------------- /docs/HowContribute.md: -------------------------------------------------------------------------------- 1 |

如何为本项目提交Pull Request

2 | 3 | [GitHub的 Pull Request 是指什么](zhihu.com/question/21682976) 4 | 5 | **图片等到项目创立再传** 6 | 7 | 一、Fork一份该项目到自己的仓库中。 8 | 9 | ![](http://leiblog.wang/static/image/2020/6/7DUigv.png) 10 | 11 | 二、进到自己fork的项目中，Clone或者Download Zip 下载到本地。 12 | 13 | ![](http://leiblog.wang/static/image/2020/6/w0YuFz.png) 14 | 15 | 三、在主分支或者自己创建一个新的分支(比较推荐新建分支)，修改，递交。 16 | 17 | 四、在自己的仓库里找到New Pull Request、递交分支。 18 | ![](http://leiblog.wang/static/image/2020/6/99mRa7.png) 19 | ![](http://leiblog.wang/static/image/2020/6/iqfVQt.png) 20 | 21 | 五、我来Review你的递交，决定是否合并。 22 | 23 | > 如果有PDF图书或其他资源需要上传，可以联系我上传 24 | > 25 | > CONTACT: 26 | > 27 | > QQ: 2230647190 28 | > 29 | > Wechat: wanglei199901 30 | > 31 | > E-mail:2230647190@qq.com -------------------------------------------------------------------------------- /boards/EGo1资料文档/EGo1-板卡文件/EGo1/1.0/board_part.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 |

FPGA Tutorial

2 | 3 | 本项目旨在**帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目**。 4 | 5 | [一起为本项目作出贡献](#github) 6 | 7 |

零、镜像下载

8 | 9 | - [Vivado 多版本安装包百度网盘](https://pan.baidu.com/s/1op98YUPNqSfqAN2UeywlNA)（提取码：DZKR） 10 | - [Vivado License](https://github.com/LeiWang1999/FPGA/tree/master/license) 11 | - [PetaLinux 2017.4](https://pan.baidu.com/s/1xZVsQVMPowDfQhBysLQ-1A)(提取码：rlcv) 12 | - [pynq_rootfs-arm_v2.4-2.5](https://pan.baidu.com/s/1JFgg0Pezk0mBub8zMdcYyA)（提取码：rn0h） 13 | - [Ubuntu-16.04.2-minimal-armhf-2017-06-18](https://pan.baidu.com/s/1mMWF8H2xEtbE5ayJ7pdGTw)(提取码：nckh) 14 | 15 |

一、入门资料

16 | 17 |

FPGA相关门户网站

18 | 19 | - [Xilinx](https://www.xilinx.com/) 20 | - [Xilinx Wiki](https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview) 21 | - [Xilinx Forums](https://forums.xilinx.com/) 22 | - [Xilinx Open Hardware](http://www.openhw.org/) 23 | - [电子创新网Xilinx社区](http://xilinx.eetrend.com/) 24 | - [Altera](https://www.intel.cn/content/www/cn/zh/products/programmable.html) 25 | - [Digilent 中国](http://www.digilent.com.cn/) 26 | - [米联客](https://www.uisrc.com/portal.php) 27 | - [opencores 开源硬件IP站](https://opencores.org/) 28 | - [FPGA FOR FUN](https://www.fpga4fun.com/CrossClockDomain.html) 29 | - [HDLBits](https://hdlbits.01xz.net/wiki/Main_Page) 30 | 31 |

每个人都应该会使用GitHub

32 | 33 | - [廖雪峰的Git教程]( https://www.liaoxuefeng.com/wiki/896043488029600 ) 34 | - [Github Guides](https://guides.github.com/activities/hello-world/) 35 | - [如何参与到本项目的建设](docs/HowContribute.md) 36 | 37 |

数字电路

38 | 39 | 数字电路是学习FPGA的前提。 40 | 41 | 如果没有学习过数字电路，先选择一本数字电路教程(下面的数字电路课本中选一本，或者用手头的数字电路课本),再选择一本Verilog教程。用Verilog实现一遍数字电路里的加法器等等，是很好的入门经历。 42 | 43 | - [电子技术基础数字部分 (康华光.第5版)](http://leiblog.wang/static/FPGA/books/电子技术基础.数字部分.(康华光.第5版).pdf) 44 | 45 |

Verilog HDL入门

46 | 47 | > HDL是硬件描述语言(Hardware Design Language)，使用这门语言的时候我们像是在**建模**，这点区别于编程语言，这往往是新手首先需要绕过来的难关！ 48 | > 49 | > Xilinx和Altera是我们主要使用到的FPGA芯片厂商，此外还有国产的紫光、安陆等。对我们用户来说，他们的区别主要在于EDA软件的不同，比如Xilinx使用的是Vivado、Altera使用的是Quatus... 50 | > 51 | > 我个人认为Vivado的功能最强大，最好用，但缺点在于综合、生成等步骤的速度慢，你需要一台好的电脑！ 52 | > 53 | > 虽然对于学习Verilog来说他们没有差别，但学习FPGA的时候手上最好要有一块板卡，上板验证会有更多的成就感。所以，用什么家的板卡，就用什么软件。 54 | 55 | - 经典图书 56 | - [搭建你的数字积木](https://book.douban.com/subject/30242443/) 57 | - Xilinx大学计划书目，比较推荐，但是没找到PDF,并且还有配套的Basys3/EGO1例程([仓库地址](https://github.com/xupsh/Digital-Design-Lab)) 58 | - [Verilog数字系统设计教程夏宇闻](http://leiblog.wang/static/FPGA/books/Verilog数字系统设计教程夏宇闻.pdf) 59 | - [Verilog经典教程夏宇闻](http://leiblog.wang/static/FPGA/books/夏宇闻-Verilog经典教程.pdf) 60 | - [深入浅出FPGA](http://leiblog.wang/static/FPGA/books/深入浅出FPGA.pdf) 61 | - [Vivado使用误区与进阶](https://leiblog.wang/static/FPGA/books/Vivado使用误区与进阶.pdf) 62 | - [Xilinx应用进阶调用IP核详解和设计开发](https://leiblog.wang/static/FPGA/books/Xilinx%20FPGA%E5%BA%94%E7%94%A8%E8%BF%9B%E9%98%B6%20%20%E9%80%9A%E7%94%A8IP%E6%A0%B8%E8%AF%A6%E8%A7%A3%E5%92%8C%E8%AE%BE%E8%AE%A1%E5%BC%80%E5%8F%91%20[%E9%BB%84%E4%B8%87%E4%BC%9F%E7%BC%96%E8%91%97][%E7%94%B5%E5%AD%90%E5%B7%A5%E4%B8%9A%E5%87%BA%E7%89%88%E7%A4%BE][2014.08][274%E9%A1%B5].pdf) 63 | 64 | - 网路上生动的大神教程 65 | - [Artix7修炼秘籍](http://leiblog.wang/static/FPGA/books/00《Artix7修炼秘籍》-MIA701第一季.pdf) 66 | - [Verilog那些事儿](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/) 67 | - [驱动篇](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/02Veilog那些事儿-驱动篇I.pdf) 68 | - [时续篇](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/03Verilog_HDL_那些事儿_时序篇v2.pdf) 69 | - [建模篇](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/04VerilogHDL那些事儿_建模篇.pdf) 70 | - [整合篇](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/05VerilogHDL那些事儿-整合篇.pdf) 71 | - [Xilinx原语的使用方法](http://leiblog.wang/static/FPGA/books/xilinx原语的使用方法.pdf) 72 | - [FPGA自学笔记-设计与验证](http://leiblog.wang/static/FPGA/books/FPGA自学笔记——设计与验证公开版.pdf) 73 | - [Verilog开发经验总结](http://leiblog.wang/static/FPGA/books/Verilog开发经验总结.pdf) 74 | - [猫叔的FPGA时序约束教程](https://leiblog.wang/static/FPGA/books/%E7%8C%AB%E5%8F%94%E7%9A%84FPGA%E6%97%B6%E5%BA%8F%E7%BA%A6%E6%9D%9F%E6%95%99%E7%A8%8B.pdf) 75 | - [Xilinx系列FPGA芯片IP核详解](https://leiblog.wang/static/FPGA/books/Xilinx%E7%B3%BB%E5%88%97FPGA%E8%8A%AF%E7%89%87IP%E6%A0%B8%E8%AF%A6%E8%A7%A3_%E5%88%98%E4%B8%9C%E5%8D%8E%E7%BC%96%E8%91%97.pdf) 76 | - [数字集成电路静态时序分析基础](https://www.bilibili.com/video/BV1if4y1p7Dq) 77 | - [综合与Design Compiler](http://leiblog.wang/static/FPGA/books/综合与DesignCompiler.pdf) 78 | - 官方pdf文档 79 | - [Vivado从此开始](http://leiblog.wang/static/FPGA/books/Vivado从此开始/) 80 | - [Verilog HDL程序设计与实践 Xilinx大学计划](http://leiblog.wang/static/FPGA/books/VerilogHDL程序设计与实践.pdf) 81 | - Xilinx 入门视频 82 | - [Digilent Basys3 手把手教学](https://space.bilibili.com/511019924/channel/detail?cid=134957) 83 | - 顺便学一下Vivado如何使用 84 | - [Vivado SDK工程移植到Vitis](https://forums.xilinx.com/t5/Xilinx-%E4%BA%A7%E5%93%81%E8%AE%BE%E8%AE%A1%E4%B8%8E%E5%8A%9F%E8%83%BD%E8%B0%83%E8%AF%95%E6%8A%80%E5%B7%A7/%E5%B0%86%E8%B5%9B%E7%81%B5%E6%80%9D-SDK-%E5%B7%A5%E7%A8%8B%E7%A7%BB%E6%A4%8D%E5%88%B0-Vitis-%E7%9A%84%E5%88%86%E6%AD%A5%E6%8C%87%E5%8D%97/ba-p/1066332) 85 | - Altera 入门视频 86 | - [正点原子 FPGA教学](https://www.bilibili.com/video/BV1Mb411E7gd?from=search&seid=11737352508875302131) 87 | - 如果买的是正点原子家的FPGA，可以白嫖很多项目。 88 | - 别家的FPGA，学习语法、驱动，也是没问题的。 89 | - [芯航线 FPGA从零到入门](https://www.bilibili.com/video/BV1tW411v78j?from=search&seid=11737352508875302131) 90 | 91 |

飞速提升开发效率✈️

92 | 93 | - [VsCode取代Vivado自带编辑器](https://editor.csdn.net/md/?articleId=84668833) 94 | - [使用板卡文件自动配置环境(板卡芯片、DDR等)](https://www.bilibili.com/s/video/BV1zg4y1q7Jd) 95 | - [EGO1板卡文件]( https://github.com/LeiWang1999/FPGA/boards) 96 | - [Digilent Boards 全家桶]( https://github.com/Digilent/vivado-boards) 97 | - [ModelSim与Matlab搭建图像仿真环境(无需上板即可验证Verilog算法!)](http://leiblog.wang/technicaldetail/5e397c7937a947e1fa893314) 98 | - [Python实现Vivado和ModelSim仿真自动化](https://mp.weixin.qq.com/s/LvmzGJt4ywOUXO7TfyPtcg) 99 | - [SystemVerilog与功能验证](https://leiblog.wang/static/FPGA/books/SystemVerilog%E4%B8%8E%E5%8A%9F%E8%83%BD%E9%AA%8C%E8%AF%81%C2%81.pdf) 100 | 101 |

规范你的工程🌟

102 | 103 | - [华为verilog编程规范](http://leiblog.wang/static/FPGA/books/standard/华为verilog编程规范.pdf) 104 | - [IEEE_Verilog](http://leiblog.wang/static/FPGA/books/standard/IEEE_Verilog.pdf) 105 | 106 |

商业报告

107 | 108 | - [电子设备-电子行业专题报告：国产FPGA研究框架-方正证券](https://leiblog.wang/static/FPGA/books/%E7%94%B5%E5%AD%90%E8%AE%BE%E5%A4%87-%E7%94%B5%E5%AD%90%E8%A1%8C%E4%B8%9A%E4%B8%93%E9%A2%98%E6%8A%A5%E5%91%8A%EF%BC%9A%E5%9B%BD%E4%BA%A7FPGA%E7%A0%94%E7%A9%B6%E6%A1%86%E6%9E%B6-%E6%96%B9%E6%AD%A3%E8%AF%81%E5%88%B8[%E9%99%88%E6%9D%AD]-20201018%E3%80%90113%E9%A1%B5%E3%80%91.pdf) 109 | 110 |

二、进阶资料

111 |

SOC System on Chip

112 | 113 | > Xilinx系列最全最详细的文档其实是官方提供的 [Xilinx Docnav](https://china.xilinx.com/support/documentation-navigation/overview.html) 114 | > 115 | > https://www.zhihu.com/question/56596019 116 | 117 | - [MicroBlaze](https://china.xilinx.com/products/design-tools/microblaze.html) 118 | 119 | - ZYNQ 120 | - [UG 585 最权威的官方文档](https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) 121 | - [The ZYNQ Book](http://www.zynqbook.com/) 122 | - [The ZYNQ Book 中文版](http://leiblog.wang/static/FPGA/books/The_Zynq_Book_ebook_chinese.pdf) 123 | - [MicroZed 300多篇教学博客](http://adiuvoengineering.com/microzed-chronicles/?tdsourcetag=s_pctim_aiomsg) 124 | - [米联客 SOC 修炼秘籍](http://leiblog.wang/static/FPGA/books/ZYNQ/%E7%B1%B3%E8%81%94%E3%80%8AZYNQ%20SOC%E4%BF%AE%E7%82%BC%E7%A7%98%E7%B1%8D%E3%80%8B.pdf) 125 | 126 | - [PYNQ](http://www.pynq.io/) 127 | - [Github](https://github.com/Xilinx/Pynq) 128 | - [xupsh pynqdoc](https://github.com/xupsh/pynqdoc) 129 | - [Docs](https://pynq.readthedocs.io/en/v2.5.1/) 130 | - [DIscuss](https://discuss.pynq.io/) 131 | - [PYNQ Z1 Digilent 中文指导手册](https://digilent-china.gitbook.io/) 132 | - [PYNQ 镜像制作](https://pynq.readthedocs.io/en/latest/pynq_sd_card.html#prepare-the-building-environment) 133 | 134 |

HLS 高层次综合

135 | 136 | - [Xilinx 官方教程](http://xilinx.eetop.cn/list-83-1.html) 137 | 138 | - [FPGA 并行编程](https://github.com/xupsh/pp4fpgas-cn) 139 | 140 | - [Vivado HLS 基本应用与图像处理](https://www.bilibili.com/video/BV11b411e7m3) 141 | 142 | 143 |

计算机体系结构

144 | 145 | - [Chisel 学习路线](https://blog.csdn.net/qq_34291505/article/details/86744581) 146 | 147 | - [Chisel Book Chinese](http://www.imm.dtu.dk/~masca/chisel-book-chinese.pdf) 148 | 149 | - [Chisel 入门资料](https://zhuanlan.zhihu.com/p/98097268) 150 | 151 | - [CPU自制入门](http://leiblog.wang/static/FPGA/books/CPU自制入门.pdf) 152 | 153 | - [手把手教你设计CPU——RISC-V处理器篇](https://leiblog.wang/static/FPGA/books/%E3%80%8A%E6%89%8B%E6%8A%8A%E6%89%8B%E6%95%99%E4%BD%A0%E8%AE%BE%E8%AE%A1CPU%E2%80%94%E2%80%94RISC-V%E5%A4%84%E7%90%86%E5%99%A8%E7%AF%87%E3%80%8B.pdf) 154 | 155 | - [riscv-soc-book](https://github.com/cnrv/riscv-soc-book) 156 | 157 | - [RISC-V 2020 Digilent](http://www.digilent.com.cn/community/697.html) 158 | 159 |

深度神经网络加速器

160 | 161 | - [PYNQ_Classification](https://leiblog.wang/static/FPGA/books/Accelerator/PYNQ_CLASSIFICATION.pdf) 162 | 163 | - [深度学习加速器设计与实验](https://www.bilibili.com/video/BV1ih411o7Yy?from=search&seid=3168767736458572847) 164 | 165 | - [NVDLA](http://nvdla.org/) 166 | 167 | - [VTA](https://tvm.apache.org/docs/vta/) 168 | 169 |

硬件驱动

170 | 171 | - [AC620以太网驱动芯航线](http://leiblog.wang/static/FPGA/books/HardwareDriver/AC620以太网设计与应用教程V1.0.pdf) 172 | 173 | - [Video Series 教你如何搭建视频通路](https://forums.xilinx.com/t5/Video-and-Audio/Xilinx-Video-Series/td-p/849583) 174 | 175 | - [UART](https://mp.weixin.qq.com/s?__biz=MzI4NjE3MzUwMA==&mid=2652138569&idx=1&sn=0fd5b6a75dd563bcc0a4480c8d095179&chksm=f0003c1ac777b50cff872bb53840fdc52a6f53bcef523cb5ecdf94aa3371fc398edfdf1b7807&token=1263105418&lang=zh_CN&scene=21#wechat_redirect) 176 | 177 | - [IIC](https://mp.weixin.qq.com/s?__biz=MzI4NjE3MzUwMA==&mid=2652139704&idx=1&sn=817b2e70e4dc7ac3dd20db5306271ccd&chksm=f00020ebc777a9fda8234e95fd00d1c1fdc64fbbac4af9b03b63dbb2df8573fb8ac40a189810&scene=21#wechat_redirect) 178 | 179 | - [SPI](https://mp.weixin.qq.com/s?__biz=MzI4NjE3MzUwMA==&mid=2652139702&idx=1&sn=c4b450e0913083e6e4d5db29a410924f&chksm=f00020e5c777a9f356ebd73fe9c0699c606f346d8c82d54e67e036d94a57f90edbce37fa5039&scene=21#wechat_redirect) 180 | 181 | - [CAN](https://mp.weixin.qq.com/s?__biz=MzI4NjE3MzUwMA==&mid=2652138778&idx=1&sn=144a45d6f49f51613a399eac5ff7a257&chksm=f0003d49c777b45fa9dc06810638906f5fead6acc311b450c96d541f3cd44f35869809d722fd&token=272554766&lang=zh_CN&scene=21#wechat_redirect) 182 | 183 |

操作系统

184 | 185 | - [Petalinux 中文文档](https://china.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/c_ug1144-petalinux-tools-reference-guide.pdf) 186 | 187 |

三、优秀项目

188 |

官方开源项目

189 | 190 | - [ADI 超多开源HDL库](https://github.com/analogdevicesinc/hdl) 191 | 192 | - [ALINX 黑金官方仓库 (包含OV系列摄像头驱动、DDR驱动等)](https://github.com/alinxalinx) 193 | - [AC616](https://github.com/alinxalinx/AC616) 194 | - [AX4010](https://github.com/alinxalinx/AX4010) 195 | - [AX7035](https://github.com/alinxalinx/AX7035) 196 | - [AX309](https://github.com/alinxalinx/AX309) 197 | - [AX7101](https://github.com/alinxalinx/AX7101) 198 | - [AX7102](https://github.com/alinxalinx/AX7102) 199 | - [AX7103](https://github.com/alinxalinx/AX7103) 200 | - [AX7021](https://github.com/alinxalinx/AX7021) 201 | - [AX7010](https://github.com/alinxalinx/AX7010) 202 | - [AX301](https://github.com/alinxalinx/AX301) 203 | - [AX7020](https://github.com/alinxalinx/AX7020) 204 | - [AX7015](https://github.com/alinxalinx/AX7015) 205 | - [Digilent 官方仓库](https://github.com/Digilent) 206 | - [vivado-library 很多好用的IP-VGA、HDMI等](https://github.com/Digilent/vivado-library) 207 | - [vivado-boards Digilent开发板的板卡文件](https://github.com/Digilent/vivado-boards) 208 | - [使用板卡文件，让你的设计事半功倍](https://www.bilibili.com/s/video/BV1zg4y1q7Jd) 209 | - [Digilent 大神用户们的项目](http://www.digilent.com.cn/project/all/open.html) 210 | - [赛灵思中文学习资料和开源设计](https://github.com/xupsh) 211 | - [74LSXX 芯片IP](https://github.com/xupsh/Digital-Design-Reference-Design/tree/dd239f50d5117917479b7a3b51eeb8a0d6945cc9/Library/74LSXX_Lib) 212 | 213 |

优秀开源项目 - 初级

优秀开源项目 - 中级

优秀开源项目 - 高级

245 | 246 | - [PYNQ集群类脑计算](https://github.com/OpenHEC/SNN-simulator-on-PYNQcluster) 247 | - 板卡:`PYNQ` 248 | - 全国大学生FPGA创新设计作品 249 | 250 |

四、推荐群组

251 | 252 | 1. 253 | - 类型：QQ群 254 | - 群号：915880054 255 | - 备注：碎碎思大佬的群，主要是分享资料的，进群可以转微信群，那边很活跃。 256 | 257 | 2. 258 | - 类型：QQ群 259 | - 群号：361820636 260 | - 备注：群主几百年没有出现过了，也没有管理员，时常有广告 261 | 262 | 3. 263 | - 类型：QQ群 264 | - 群号：1140582958 265 | - 备注：1000人大群 266 | 267 | 4. <摸鱼范式-2022届数字IC> 268 | - 类型：QQ群 269 | - 群号：1060380138 270 | - 备注：“摸鱼范式”公众号的群，2000人群 271 | -------------------------------------------------------------------------------- /boards/EGo1资料文档/EGo1-引脚约束文件/EGo1.xdc: -------------------------------------------------------------------------------- 1 | /////////////////////////////系统时钟和复位//////////////////////////////////// 2 | set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in ] 3 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n ] 4 | 5 | /////////////////////////////串口///////////////////////////////////////////// 6 | set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] 7 | set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] 8 | 9 | ////////////////////////////////蓝牙/////////////////////////////////////////// 10 | set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] 11 | set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] 12 | 13 | set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] 14 | set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] 15 | set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] 16 | set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] 17 | set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] 18 | 19 | set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] 20 | 21 | ///////////////////////////////音频接口//////////////////////////////////////// 22 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] 23 | set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] 24 | 25 | //////////////////////////////////iic//////////////////////////////////////////// 26 | set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] 27 | set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] 28 | 29 | //////////////////////////////////XADC模数转换/////////////////////////////////// 30 | set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n ] 31 | set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p ] 32 | set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] 33 | set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] 34 | 35 | /////////////////////////////////////5个按键////////////////////////////////////// 36 | set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports {btn_pin[0]}] 37 | set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {btn_pin[1]}] 38 | set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {btn_pin[2]}] 39 | set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports {btn_pin[3]}] 40 | set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports {btn_pin[4]}] 41 | 42 | ///////////////////////////////////拨码开关sw0~sw7//////////////////////////////// 43 | set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] 44 | set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] 45 | set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] 46 | set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] 47 | set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] 48 | set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] 49 | set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] 50 | set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] 51 | 52 | //////////////////////////////////拨码开关sw8~sw15///////////////////////////// 53 | set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] 54 | set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] 55 | set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] 56 | set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] 57 | set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] 58 | set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] 59 | set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] 60 | set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] 61 | 62 | 63 | //////////////////////////////////////LED0~LED15//////////////////////////////// 64 | set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] 65 | set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] 66 | set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] 67 | set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] 68 | set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] 69 | set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] 70 | set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] 71 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] 72 | 73 | set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] 74 | set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] 75 | set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] 76 | set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] 77 | set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] 78 | set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] 79 | set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] 80 | set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] 81 | 82 | ///////////////////////////////8个数码管位选信号///////////////////////////////// 83 | set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] 84 | set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] 85 | set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] 86 | set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] 87 | set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] 88 | set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] 89 | set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] 90 | set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] 91 | 92 | ///////////////////////////////////数码管段选信号////////////////////////////////// 93 | set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] 94 | set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] 95 | set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] 96 | set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] 97 | set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] 98 | set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] 99 | set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] 100 | set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] 101 | 102 | set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] 103 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] 104 | set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] 105 | set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] 106 | set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] 107 | set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] 108 | set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] 109 | set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] 110 | 111 | ////////////////////////////////////VGA行同步场同步信号/////////////////////////////// 112 | set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] 113 | set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] 114 | 115 | ///////////////////////////////////////VGA红绿蓝信号////////////////////////////////// 116 | set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] 117 | set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] 118 | set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] 119 | set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] 120 | set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] 121 | set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] 122 | set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] 123 | set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] 124 | set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] 125 | set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] 126 | set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] 127 | set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] 128 | 129 | /////////////////////////////////////////DAC数模转换////////////////////////////////// 130 | set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] 131 | set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] 132 | set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] 133 | set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] 134 | set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] 135 | 136 | set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] 137 | set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] 138 | set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] 139 | set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] 140 | set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] 141 | set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] 142 | set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] 143 | set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] 144 | 145 | ////////////////////////////////////////PS2///////////////////////////////////// 146 | set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk ] 147 | set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data ] 148 | 149 | 150 | /////////////////////////////////////////SDRAM////////////////////////////////////// 151 | set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] 152 | set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] 153 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] 154 | set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] 155 | set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] 156 | set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] 157 | set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] 158 | set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] 159 | set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] 160 | set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] 161 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] 162 | set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] 163 | set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] 164 | set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] 165 | set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] 166 | set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] 167 | set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] 168 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] 169 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] 170 | 171 | set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] 172 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] 173 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] 174 | set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] 175 | set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] 176 | 177 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] 178 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] 179 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] 180 | set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] 181 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] 182 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] 183 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] 184 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] 185 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] 186 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] 187 | set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] 188 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] 189 | set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] 190 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] 191 | set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] 192 | set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] 193 | 194 | //////////////////////////////////32个pmod接口////////////////////////////////////// 195 | set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]} ] 196 | set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]} ] 197 | set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]} ] 198 | set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]} ] 199 | set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]} ] 200 | set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]} ] 201 | set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]} ] 202 | set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]} ] 203 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]} ] 204 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]} ] 205 | set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] 206 | set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] 207 | set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] 208 | set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] 209 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] 210 | set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] 211 | 212 | set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] 213 | set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] 214 | set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] 215 | set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] 216 | set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] 217 | set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] 218 | set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] 219 | set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] 220 | set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] 221 | set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] 222 | set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] 223 | set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] 224 | set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] 225 | set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] 226 | set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] 227 | set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] --------------------------------------------------------------------------------