├── 2023319-108mhz ├── .ci-scripts │ ├── bits.tcl │ └── run-linter.py ├── .gitignore ├── .gitlab-ci.yml ├── .gitmodules ├── README.md ├── asm │ ├── Makefile │ └── user-sample.s ├── thinpad_top.srcs │ ├── constrs_1 │ │ └── new │ │ │ └── thinpad_top.xdc │ ├── sim_1 │ │ ├── imports │ │ │ ├── CFImemory64Mb_bottom.mem │ │ │ └── CFImemory64Mb_top.mem │ │ ├── new │ │ │ ├── 28F640P30.v │ │ │ ├── clock.v │ │ │ ├── cpld_model.v │ │ │ ├── flag_sync_cpld.v │ │ │ ├── include │ │ │ │ ├── BankLib.h │ │ │ │ ├── CUIcommandData.h │ │ │ │ ├── TimingData.h │ │ │ │ ├── UserData.h │ │ │ │ ├── data.h │ │ │ │ └── def.h │ │ │ ├── sram_model.v │ │ │ └── tb.sv │ │ └── tmp │ │ │ └── supervisor_v2.01 │ │ │ ├── .dockerfiles │ │ │ ├── Dockerfile │ │ │ └── Dockerfile.with.HW │ │ │ ├── .gitignore │ │ │ ├── .test-script │ │ │ ├── .travis.yml │ │ │ ├── LICENSE │ │ │ ├── README.md │ │ │ ├── kernel │ │ │ ├── .gdbinit │ │ │ ├── Makefile │ │ │ ├── debug │ │ │ ├── include │ │ │ │ ├── exception.h │ │ │ │ ├── mipsregs.h │ │ │ │ ├── regdef.h │ │ │ │ ├── shell.h │ │ │ │ └── unistd.h │ │ │ └── kern │ │ │ │ ├── evec.S │ │ │ │ ├── init.S │ │ │ │ ├── kernel.ld │ │ │ │ ├── shell.S │ │ │ │ ├── test.S │ │ │ │ └── utils.S │ │ │ ├── term │ │ │ ├── .gitignore │ │ │ └── term.py │ │ │ └── utility │ │ │ ├── gen_matrix.py │ │ │ ├── matrix.in │ │ │ └── matrix.out │ └── sources_1 │ │ ├── ip │ │ └── pll_example │ │ │ ├── doc │ │ │ └── clk_wiz_v6_0_changelog.txt │ │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ │ ├── mmcm_pll_drp_func_us_plus_pll.vh │ │ │ ├── pll_example.v │ │ │ ├── pll_example.xci │ │ │ ├── pll_example.xdc │ │ │ ├── pll_example.xml │ │ │ ├── pll_example_board.xdc │ │ │ ├── pll_example_clk_wiz.v │ │ │ └── pll_example_ooc.xdc │ │ ├── mycpu │ │ ├── SRAM_UART_ctrl.v │ │ ├── ctrl.v │ │ ├── dcache.v │ │ ├── defines.v │ │ ├── ex.v │ │ ├── ex_mem.v │ │ ├── icache.v │ │ ├── id.v │ │ ├── id_ex.v │ │ ├── if_id.v │ │ ├── mem.v │ │ ├── mem_wb.v │ │ ├── mycpu.v │ │ ├── pc_reg.v │ │ └── regfile.v │ │ └── new │ │ ├── SEG7_LUT.v │ │ ├── async.v │ │ ├── thinpad_top.v │ │ └── vga.v ├── thinpad_top.xpr ├── vivado_pid10052.str ├── vivado_pid14036.str ├── vivado_pid17968.str ├── vivado_pid24972.str ├── vivado_pid31640.str ├── vivado_pid31908.str ├── vivado_pid33688.debug ├── vivado_pid33688.str ├── vivado_pid43256.str ├── vivado_pid51304.str ├── vivado_pid9356.str └── 设计报告.pdf ├── 2023龙芯杯竞赛总结.pdf └── README.md /2023319-108mhz/.ci-scripts/bits.tcl: -------------------------------------------------------------------------------- 1 | update_compile_order -fileset sources_1 2 | 3 | # If IP cores are used 4 | if { [llength [get_ips]] != 0} { 5 | upgrade_ip [get_ips] 6 | 7 | foreach ip [get_ips] { 8 | create_ip_run [get_ips $ip] 9 | } 10 | 11 | set ip_runs [get_runs -filter {SRCSET != sources_1 && IS_SYNTHESIS && NEEDS_REFRESH}] 12 | 13 | if { [llength $ip_runs] != 0} { 14 | launch_runs -quiet -jobs 2 {*}$ip_runs 15 | 16 | foreach r $ip_runs { 17 | wait_on_run $r 18 | } 19 | } 20 | 21 | } 22 | 23 | reset_run impl_1 24 | reset_run synth_1 25 | launch_runs -jobs 2 impl_1 -to_step write_bitstream 26 | wait_on_run impl_1 27 | 28 | exit -------------------------------------------------------------------------------- /2023319-108mhz/.ci-scripts/run-linter.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | from lxml import etree 3 | import chardet 4 | import sys 5 | import os 6 | from pathlib import Path 7 | from typing import Tuple, List, Set 8 | import shutil 9 | import subprocess 10 | import traceback 11 | 12 | def is_header(f: Path): 13 | with f.open('rb') as fd: 14 | return -1 == fd.read().find(b'endmodule') 15 | 16 | def transcoding(src: Path, target: Path): 17 | with src.open("rb") as fd: 18 | rawdata = fd.read() 19 | res = chardet.detect(rawdata) 20 | encoding = res['encoding'] if res['confidence'] > 0.5 else "GBK" 21 | try: 22 | s = rawdata.decode(encoding) 23 | except: 24 | print("Transcoding", src, ':') 25 | traceback.print_exc() 26 | s = rawdata.decode(encoding, 'replace') 27 | with target.open("wb") as wfd: 28 | wfd.write(s.encode('utf-8')) 29 | 30 | def parse_project(xpr: Path) -> Tuple[str, Set[str], Set[str]]: 31 | prjname = os.path.splitext(xpr.name)[0] 32 | prjdir = xpr.parent 33 | srcdir = prjdir / (prjname + ".srcs") 34 | topname = '' 35 | target = prjdir / '.lint' 36 | 37 | tree = etree.parse(str(xpr)) 38 | srclist = set() 39 | inclist = set() 40 | for fileset in tree.xpath("/Project/FileSets/FileSet"): 41 | if fileset.attrib['Type'] != 'DesignSrcs' and \ 42 | fileset.attrib['Type'] != 'BlockSrcs': 43 | continue 44 | for child in fileset: 45 | if child.tag == 'File': 46 | tmp = child.attrib['Path'] 47 | tmp = tmp.replace('$PSRCDIR', str(srcdir)) 48 | tmp = tmp.replace('$PPRDIR', str(prjdir)) 49 | tmp = tmp.replace(".xci", '_stub.v') 50 | vlog = Path(tmp) 51 | if not vlog.is_file(): 52 | print("Source file", vlog, "does not exist") 53 | continue 54 | vlog_target = target / vlog.relative_to(prjdir) 55 | vlog_target.parent.mkdir(exist_ok=True, parents=True) 56 | # shutil.copy(vlog, vlog_target) 57 | transcoding(vlog, vlog_target) 58 | inclist.add(str(vlog_target.parent)) 59 | if not is_header(vlog_target): 60 | srclist.add(str(vlog_target)) 61 | elif child.tag == 'Config' and fileset.attrib['Type'] == 'DesignSrcs': 62 | topname = child.xpath("./Option[@Name='TopModule']")[0].attrib['Val'] 63 | 64 | return (topname, srclist, inclist) 65 | 66 | def run_linter(prjdir: Path, topname: str, srclist: Set[str], inclist: Set[str]): 67 | linter_log = prjdir / "linter.log" 68 | args = ["verilator","--lint-only","-Wall","-Wno-DECLFILENAME","-Wno-PINCONNECTEMPTY","-Wno-UNUSED"] 69 | args += ['--top-module', topname] 70 | incargs = [ '-I' + i for i in inclist] 71 | args += incargs 72 | args += srclist 73 | # print(args) 74 | res = subprocess.run(args) 75 | if res.returncode != 0: 76 | print("Return code of verilator is", res.returncode) 77 | 78 | if __name__ == "__main__": 79 | try: 80 | xpr = Path(sys.argv[1]) 81 | topname, srclist, inclist = parse_project(xpr) 82 | run_linter(xpr.parent, topname, srclist, inclist) 83 | except: 84 | traceback.print_exc() 85 | 86 | -------------------------------------------------------------------------------- /2023319-108mhz/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.o 3 | *.elf 4 | ipshared/ 5 | *_netlist.* 6 | *_stub.* 7 | *.dcp 8 | *.veo 9 | *.vho 10 | *.hwh 11 | *.hdf 12 | thinpad_top.tmp/ 13 | thinpad_top.cache/ 14 | thinpad_top.hw/ 15 | thinpad_top.ip_user_files/ 16 | thinpad_top.runs/ 17 | thinpad_top.sim/sim_1/behav/xsim/ 18 | .Xil/ 19 | *.jou 20 | *.log 21 | *.dcp 22 | /.lint/ -------------------------------------------------------------------------------- /2023319-108mhz/.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | variables: 2 | GIT_SUBMODULE_STRATEGY: recursive 3 | 4 | stages: 5 | - build 6 | 7 | bitstream: 8 | stage: build 9 | image: nscscc:2019.2 10 | before_script: 11 | - source /opt/Xilinx/Vivado/2019.2/settings64.sh 12 | - export PATH=/opt/mips-mti-elf/2016.05-06/bin:${PATH} 13 | script: 14 | - make -C asm 15 | - python3 ./.ci-scripts/run-linter.py thinpad_top.xpr 2>linter.log 16 | - str="thinpad_top.srcs" 17 | - diff="" 18 | - echo ${CI_COMMIT_BEFORE_SHA} 19 | - git config --global --add safe.directory $(pwd) 20 | - > 21 | if [ "${CI_COMMIT_BEFORE_SHA}" == "0000000000000000000000000000000000000000" ] 22 | then vivado -mode tcl -source .ci-scripts/bits.tcl thinpad_top.xpr 23 | else 24 | diff=$(git diff --name-only ${CI_COMMIT_BEFORE_SHA} ${CI_COMMIT_SHA}) 25 | fi 26 | - echo $diff 27 | - > 28 | if [[ $diff =~ $str ]] 29 | then vivado -mode tcl -source .ci-scripts/bits.tcl thinpad_top.xpr 30 | fi 31 | - test -f thinpad_top.runs/impl_1/*.bit || vivado -mode tcl -source .ci-scripts/bits.tcl thinpad_top.xpr 32 | - test -f thinpad_top.runs/impl_1/*.bit 33 | cache: 34 | key : bit 35 | paths : 36 | - thinpad_top.runs/impl_1/*.bit 37 | 38 | artifacts: 39 | name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME" 40 | when: always 41 | paths: 42 | - asm/*.bin 43 | - thinpad_top.runs/impl_1/*.bit 44 | - thinpad_top.runs/*/runme.log 45 | - linter.log 46 | -------------------------------------------------------------------------------- /2023319-108mhz/.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ffhh927/NSCSCC-2023-mips/f18f8622deb8dafd87bf5efc892f344fb0ea94a3/2023319-108mhz/.gitmodules -------------------------------------------------------------------------------- /2023319-108mhz/README.md: -------------------------------------------------------------------------------- 1 | Thinpad 模板工程 2 | --------------- 3 | 4 | 工程包含示例代码和所有引脚约束，可以直接编译。 5 | 6 | 代码中包含中文注释，Vivado下可能出现乱码问题，为了保证显示正确 7 | Windows平台请使用GBK编码的文件，Linux平台请使用UTF-8编码的文件。 8 | -------------------------------------------------------------------------------- /2023319-108mhz/asm/Makefile: -------------------------------------------------------------------------------- 1 | GCCPREFIX?=mips-mti-elf- 2 | 3 | override CFLAGS += -mips32r2 -mno-abicalls -mno-shared -EL -nostdlib -nostdinc -g 4 | override LDFLAGS += -nostdlib -EL -static 5 | 6 | CC :=$(GCCPREFIX)gcc 7 | LD := $(GCCPREFIX)ld 8 | AR := $(GCCPREFIX)ar 9 | OBJCOPY := $(GCCPREFIX)objcopy 10 | OBJDUMP := $(GCCPREFIX)objdump 11 | 12 | SRC := $(wildcard *.s) 13 | BINS := $(patsubst %.s, %.bin, $(SRC)) 14 | 15 | all: $(BINS) 16 | 17 | %.bin: %.elf 18 | $(OBJCOPY) -j .text -O binary $^ $@ 19 | 20 | %.elf: %.o 21 | $(LD) $(LDFLAGS) -Ttext 0x80100000 -o $@ $^ 22 | 23 | %.o: %.s 24 | $(CC) $(CFLAGS) -x assembler-with-cpp -c -o $@ $^ 25 | -------------------------------------------------------------------------------- /2023319-108mhz/asm/user-sample.s: -------------------------------------------------------------------------------- 1 | .set noreorder 2 | .set noat 3 | .globl __start 4 | .section text 5 | 6 | __start: 7 | .text 8 | ori $t0, $zero, 0x1 # t0 = 1 9 | ori $t1, $zero, 0x1 # t1 = 1 10 | xor $v0, $v0, $v0 # v0 = 0 11 | ori $v1, $zero, 8 # v1 = 8 12 | lui $a0, 0x8040 # a0 = 0x80400000 13 | 14 | loop: 15 | addu $t2, $t0, $t1 # t2 = t0+t1 16 | ori $t0, $t1, 0x0 # t0 = t1 17 | ori $t1, $t2, 0x0 # t1 = t2 18 | sw $t1, 0($a0) 19 | addiu $a0, $a0, 4 # a0 += 4 20 | addiu $v0, $v0, 1 # v0 += 1 21 | 22 | bne $v0, $v1, loop 23 | ori $zero, $zero, 0 # nop 24 | 25 | jr $ra 26 | ori $zero, $zero, 0 # nop 27 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/imports/CFImemory64Mb_bottom.mem: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | @00010 22 | 23 | 0101_0001 24 | 25 | 0101_0010 26 | 27 | 0101_1001 28 | 29 | @00013 30 | 31 | 0000_0001 32 | 33 | 0000_0000 34 | 35 | @00015 36 | 37 | 0000_1010 38 | 39 | 0000_0001 40 | 41 | @00017 42 | 43 | 0000_0000 44 | 45 | 0000_0000 46 | 47 | @00019 48 | 49 | 0000_0000 50 | 51 | 52 | @0001A 53 | 54 | 0000_0000 55 | 56 | 57 | @0001B 58 | 0001_0111 59 | 60 | @0001C 61 | 0010_0000 62 | 63 | @0001D 64 | 65 | 1000_0101 66 | 67 | @0001E 68 | 1001_0101 69 | 70 | @0001F 71 | 0000_0110 72 | 73 | @00020 74 | 75 | 0000_1000 76 | 77 | @00021 78 | 0000_1001 79 | 80 | @00022 81 | 0000_0000 82 | 83 | @00023 84 | 0000_0010 85 | 86 | 87 | 88 | @00024 89 | 0000_0011 90 | 91 | @00025 92 | 0000_0011 93 | 94 | @00026 95 | 0000_0000 96 | 97 | @00027 98 | 0001_1000 99 | 100 | @00028 101 | 0000_0001 102 | 103 | @00029 104 | 0000_0000 105 | 106 | @0002A 107 | 0000_1001 108 | 109 | @0002B 110 | 0000_0000 111 | 112 | @0002C 113 | 0000_0010 114 | 115 | @0002D 116 | 0000_0011 //bottom 117 | 118 | @0002E 119 | 0000_0000 120 | 121 | @0002F 122 | 1000_0000 //bottom 123 | 124 | @00030 125 | 0000_0000 //bottom 126 | 127 | @00031 128 | 0011_1110 //bottom 129 | 130 | @00032 131 | 0000_0000 132 | 133 | @00033 134 | 0000_0000 //bottom 135 | 136 | @00034 137 | 0000_0010 //bottom 138 | 139 | @00035 140 | 0000_0000 141 | 142 | @00036 143 | 0000_0000 144 | 145 | @00037 146 | 0000_0000 147 | 148 | @00038 149 | 0000_0000 150 | 151 | @0010A 152 | 0101_0000 153 | 154 | @0010B 155 | 0101_0010 156 | 157 | @0010C 158 | 0010_1001 159 | 160 | @0010D 161 | 0011_0001 162 | 163 | @0010E 164 | 0011_0101 165 | 166 | @0010F 167 | 1110_0110 168 | 169 | @00110 170 | 0000_0001 171 | 172 | @00111 173 | 0000_0000 174 | 175 | @00112 176 | 0000_0000 177 | 178 | @00113 179 | 0000_0001 180 | 181 | @00114 182 | 0000_0011 183 | 184 | @00115 185 | 0000_0000 186 | 187 | @00116 188 | 0001_1000 189 | 190 | @00117 191 | 1001_0000 192 | 193 | @00118 194 | 0000_0010 195 | 196 | @00119 197 | 1000_0000 198 | 199 | @0011A 200 | 0000_0000 201 | 202 | @0011B 203 | 0000_0011 204 | 205 | @0011C 206 | 0000_0011 207 | 208 | @0011D 209 | 1000_1001 210 | 211 | @0011E 212 | 0000_0000 213 | 214 | @0011F 215 | 0000_0000 216 | 217 | @00120 218 | 0000_0000 219 | 220 | @00121 221 | 0000_0000 222 | 223 | @00122 224 | 0000_0000 225 | 226 | @00123 227 | 0000_0000 228 | 229 | @00124 230 | 0001_0000 231 | 232 | @00125 233 | 0000_0000 234 | 235 | @00126 236 | 0000_0100 237 | 238 | @00127 239 | 0000_0100 240 | 241 | @00128 242 | 0000_0100 243 | 244 | @00129 245 | 0000_0001 246 | 247 | @0012A 248 | 0000_0010 249 | 250 | @0012B 251 | 0000_0011 252 | 253 | @0012C 254 | 0000_0111 255 | 256 | @0012D 257 | 0000_0001 258 | 259 | @0012E 260 | 0010_0100 261 | 262 | @0012F 263 | 0000_0000 264 | 265 | @00130 266 | 0000_0001 267 | 268 | @00131 269 | 0000_0000 270 | 271 | @00132 272 | 0001_0001 273 | 274 | @00133 275 | 0000_0000 276 | 277 | @00134 278 | 0000_0000 279 | 280 | @00135 281 | 0000_0010 282 | 283 | @00136 284 | 0000_0011 //bottom 285 | 286 | @00137 287 | 0000_0000 288 | 289 | @00138 290 | 1000_0000 //bottom 291 | 292 | @00139 293 | 0000_0000 //bottom 294 | 295 | @0013A 296 | 0110_0100 297 | 298 | @0013B 299 | 0000_0000 300 | 301 | @0013C 302 | 0000_0010 303 | 304 | @0013D 305 | 0000_0011 306 | 307 | @0013E 308 | 0000_0000 309 | 310 | @0013F 311 | 1000_0000 312 | 313 | @00140 314 | 0000_0000 315 | 316 | @00141 317 | 0000_0000 318 | 319 | @00142 320 | 0000_0000 321 | 322 | @00143 323 | 1000_0000 324 | 325 | @00144 326 | 0111_1110 //bottom 327 | 328 | @00145 329 | 0000_0000 330 | 331 | @00146 332 | 0000_0000 //bottom 333 | 334 | @00147 335 | 0000_0010 //bottom 336 | 337 | @00148 338 | 0110_0100 339 | 340 | @00149 341 | 0000_0000 342 | 343 | @0014A 344 | 0000_0010 345 | 346 | @0014B 347 | 0000_0011 348 | 349 | @0014C 350 | 0000_0000 351 | 352 | @0014D 353 | 1000_0000 354 | 355 | @0014E 356 | 0000_0000 357 | 358 | @0014F 359 | 0000_0000 360 | 361 | @00150 362 | 0000_0000 363 | 364 | @00151 365 | 1000_0000 366 | 367 | @00152 368 | 1111_1111 369 | 370 | @00153 371 | 1111_1111 372 | 373 | @00154 374 | 1111_1111 375 | 376 | @00155 377 | 1111_1111 378 | 379 | @00156 380 | 1111_1111 381 | 382 | 383 | 384 | 385 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/imports/CFImemory64Mb_top.mem: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | @00010 22 | 23 | 0101_0001 24 | 25 | 0101_0010 26 | 27 | 0101_1001 28 | 29 | @00013 30 | 31 | 0000_0001 32 | 33 | 0000_0000 34 | 35 | @00015 36 | 37 | 0000_1010 38 | 39 | 0000_0001 40 | 41 | @00017 42 | 43 | 0000_0000 44 | 45 | 0000_0000 46 | 47 | @00019 48 | 49 | 0000_0000 50 | 51 | 52 | @0001A 53 | 54 | 0000_0000 55 | 56 | @0001B 57 | 0001_0111 58 | 59 | @0001C 60 | 0010_0000 61 | 62 | @0001D 63 | 64 | 1000_0101 65 | 66 | @0001E 67 | 1001_0101 68 | 69 | @0001F 70 | 0000_0110 71 | 72 | @00020 73 | 74 | 0000_1000 75 | 76 | @00021 77 | 0000_1001 78 | 79 | @00022 80 | 0000_0000 81 | 82 | @00023 83 | 0000_0010 84 | 85 | 86 | 87 | @00024 88 | 0000_0011 89 | 90 | @00025 91 | 0000_0011 92 | 93 | @00026 94 | 0000_0000 95 | 96 | @00027 97 | 0001_1000 //top 98 | 99 | @00028 100 | 0000_0001 101 | 102 | @00029 103 | 0000_0000 104 | 105 | @0002A 106 | 0000_1001 107 | 108 | @0002B 109 | 0000_0000 110 | 111 | @0002C 112 | 0000_0010 113 | 114 | @0002D 115 | 0111_1110 //top 116 | 117 | @0002E 118 | 0000_0000 119 | 120 | @0002F 121 | 0000_0000 //top 122 | 123 | @00030 124 | 0000_0010 //top 125 | 126 | @00031 127 | 0000_0011 //top 128 | 129 | @00032 130 | 0000_0000 131 | 132 | @00033 133 | 1000_0000 //top 134 | 135 | @00034 136 | 0000_0000 //top 137 | 138 | @00035 139 | 0000_0000 140 | 141 | @00036 142 | 0000_0000 143 | 144 | @00037 145 | 0000_0000 146 | 147 | @00038 148 | 0000_0000 149 | 150 | @0010A 151 | 0101_0000 152 | 153 | @0010B 154 | 0101_0010 155 | 156 | @0010C 157 | 0100_1001 158 | 159 | @0010D 160 | 0011_0001 161 | 162 | @0010E 163 | 0011_0101 164 | 165 | @0010F 166 | 1110_0110 167 | 168 | @00110 169 | 0000_0001 170 | 171 | @00111 172 | 0000_0000 173 | 174 | @00112 175 | 0000_0000 176 | 177 | @00113 178 | 0000_0001 179 | 180 | @00114 181 | 0000_0011 182 | 183 | @00115 184 | 0000_0000 185 | 186 | @00116 187 | 0001_1000 188 | 189 | @00117 190 | 1001_0000 191 | 192 | @00118 193 | 0000_0010 194 | 195 | @00119 196 | 1000_0000 197 | 198 | @0011A 199 | 0000_0000 200 | 201 | @0011B 202 | 0000_0011 203 | 204 | @0011C 205 | 0000_0011 206 | 207 | @0011D 208 | 1000_1001 209 | 210 | @0011E 211 | 0000_0000 212 | 213 | @0011F 214 | 0000_0000 215 | 216 | @00120 217 | 0000_0000 218 | 219 | @00121 220 | 0000_0000 221 | 222 | @00122 223 | 0000_0000 224 | 225 | @00123 226 | 0000_0000 227 | 228 | @00124 229 | 0001_0000 230 | 231 | @00125 232 | 0000_0000 233 | 234 | @00126 235 | 0000_0100 236 | 237 | @00127 238 | 0000_0100 239 | 240 | @00128 241 | 0000_0100 242 | 243 | @00129 244 | 0000_0001 245 | 246 | @0012A 247 | 0000_0010 248 | 249 | @0012B 250 | 0000_0011 251 | 252 | @0012C 253 | 0000_0111 254 | 255 | @0012D 256 | 0000_0001 257 | 258 | @0012E 259 | 0010_0100 260 | 261 | @0012F 262 | 0000_0000 263 | 264 | @00130 265 | 0000_0001 266 | 267 | @00131 268 | 0000_0000 269 | 270 | @00132 271 | 0001_0001 272 | 273 | @00133 274 | 0000_0000 275 | 276 | @00134 277 | 0000_0000 278 | 279 | @00135 280 | 0000_0010 281 | 282 | @00136 283 | 0111_1110 //top 284 | 285 | @00137 286 | 0000_0000 287 | 288 | @00138 289 | 0000_0000 //top 290 | 291 | @00139 292 | 0000_0010 //top 293 | 294 | @0013A 295 | 0110_0100 296 | 297 | @0013B 298 | 0000_0000 299 | 300 | @0013C 301 | 0000_0010 302 | 303 | @0013D 304 | 0000_0011 305 | 306 | @0013E 307 | 0000_0000 308 | 309 | @0013F 310 | 1000_0000 311 | 312 | @00140 313 | 0000_0000 314 | 315 | @00141 316 | 0000_0000 317 | 318 | @00142 319 | 0000_0000 320 | 321 | @00143 322 | 1000_0000 323 | 324 | @00144 325 | 0000_0011 //top 326 | 327 | @00145 328 | 0000_0000 329 | 330 | @00146 331 | 1000_0000 //top 332 | 333 | @00147 334 | 0000_0000 //top 335 | 336 | @00148 337 | 0110_0100 338 | 339 | @00149 340 | 0000_0000 341 | 342 | @0014A 343 | 0000_0010 344 | 345 | @0014B 346 | 0000_0011 347 | 348 | @0014C 349 | 0000_0000 350 | 351 | @0014D 352 | 1000_0000 353 | 354 | @0014E 355 | 0000_0000 356 | 357 | @0014F 358 | 0000_0000 359 | 360 | @00150 361 | 0000_0000 362 | 363 | @00151 364 | 1000_0000 365 | 366 | @00152 367 | 1111_1111 368 | 369 | @00153 370 | 1111_1111 371 | 372 | @00154 373 | 1111_1111 374 | 375 | @00155 376 | 1111_1111 377 | 378 | @00156 379 | 1111_1111 380 | 381 | 382 | 383 | 384 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/new/clock.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 1ps 2 | 3 | module clock ( 4 | output reg clk_50M, 5 | output reg clk_11M0592 6 | ); 7 | 8 | initial begin 9 | clk_50M = 0; 10 | clk_11M0592 = 0; 11 | end 12 | 13 | always #(90422/2) clk_11M0592 = ~clk_11M0592; 14 | always #(20000/2) clk_50M = ~clk_50M; 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/new/cpld_model.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module cpld_model( 3 | input wire clk_uart, //内部串口时钟 4 | input wire uart_rdn, //读串口信号，低有效 5 | input wire uart_wrn, //写串口信号，低有效 6 | output reg uart_dataready, //串口数据准备好 7 | output reg uart_tbre, //发送数据标志 8 | output reg uart_tsre, //数据发送完毕标志 9 | inout wire [7:0]data 10 | ); 11 | reg bus_analyze_clk = 0; 12 | reg clk_out2_rst_n = 0, bus_analyze_clk_rst_n = 0; 13 | wire clk_out2; 14 | 15 | reg [7:0] TxD_data,TxD_data0,TxD_data1; 16 | reg [2:0] cpld_emu_wrn_sync; 17 | reg [2:0] cpld_emu_rdn_sync; 18 | reg [7:0] uart_rx_data; 19 | wire uart_rx_flag; 20 | reg wrn_rise; 21 | 22 | assign data = uart_rdn ? 8'bz : uart_rx_data; 23 | assign #3 clk_out2 = clk_uart; 24 | 25 | initial begin 26 | uart_tsre = 1; 27 | uart_tbre = 1; 28 | uart_dataready = 0; 29 | repeat(2) @(negedge clk_out2); 30 | clk_out2_rst_n = 1; 31 | @(negedge bus_analyze_clk); 32 | bus_analyze_clk_rst_n = 1; 33 | end 34 | 35 | always #2 bus_analyze_clk = ~bus_analyze_clk; 36 | 37 | always @(posedge bus_analyze_clk) begin : proc_Tx 38 | TxD_data0 <= data[7:0]; 39 | TxD_data1 <= TxD_data0; 40 | 41 | cpld_emu_rdn_sync <= {cpld_emu_rdn_sync[1:0],uart_rdn}; 42 | cpld_emu_wrn_sync <= {cpld_emu_wrn_sync[1:0],uart_wrn}; 43 | 44 | if(~cpld_emu_wrn_sync[1] & cpld_emu_wrn_sync[2]) 45 | TxD_data <= TxD_data1; 46 | wrn_rise <= cpld_emu_wrn_sync[1] & ~cpld_emu_wrn_sync[2]; 47 | 48 | if(~cpld_emu_rdn_sync[1] & cpld_emu_rdn_sync[2]) //rdn_fall 49 | uart_dataready <= 1'b0; 50 | else if(uart_rx_flag) 51 | uart_dataready <= 1'b1; 52 | end 53 | 54 | reg [7:0] TxD_data_sync; 55 | wire tx_en; 56 | reg rx_ack = 0; 57 | 58 | always @(posedge clk_out2) begin 59 | TxD_data_sync <= TxD_data; 60 | end 61 | 62 | always @(posedge clk_out2 or negedge uart_wrn) begin : proc_tbre 63 | if(~uart_wrn) begin 64 | uart_tbre <= 0; 65 | end else if(!uart_tsre) begin 66 | uart_tbre <= 1; 67 | end 68 | end 69 | 70 | flag_sync_cpld tx_flag( 71 | .clkA (bus_analyze_clk), 72 | .clkB (clk_out2), 73 | .FlagIn_clkA (wrn_rise), 74 | .FlagOut_clkB(tx_en), 75 | .a_rst_n (bus_analyze_clk_rst_n), 76 | .b_rst_n (clk_out2_rst_n) 77 | ); 78 | 79 | flag_sync_cpld rx_flag( 80 | .clkA (clk_out2), 81 | .clkB (bus_analyze_clk), 82 | .FlagIn_clkA (rx_ack), 83 | .FlagOut_clkB(uart_rx_flag), 84 | .a_rst_n (bus_analyze_clk_rst_n), 85 | .b_rst_n (clk_out2_rst_n) 86 | ); 87 | 88 | always begin 89 | wait(tx_en == 1); 90 | repeat(2) 91 | @(posedge clk_out2); 92 | uart_tsre = 0; 93 | #10000 // 实际串口发送时间更长，为了加快仿真，等待时间较短 94 | $display("send: 0x%02x", TxD_data_sync); 95 | uart_tsre = 1; 96 | end 97 | 98 | task pc_send_byte; 99 | input [7:0] arg; 100 | begin 101 | uart_rx_data = arg; 102 | @(negedge clk_out2); 103 | rx_ack = 1; 104 | @(negedge clk_out2); 105 | rx_ack = 0; 106 | end 107 | endtask 108 | endmodule -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/new/flag_sync_cpld.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module flag_sync_cpld(/*autoport*/ 3 | //output 4 | FlagOut_clkB, 5 | //input 6 | a_rst_n, 7 | b_rst_n, 8 | clkA, 9 | FlagIn_clkA, 10 | clkB); 11 | 12 | input wire a_rst_n; 13 | input wire b_rst_n; 14 | input wire clkA; 15 | input wire FlagIn_clkA; 16 | input wire clkB; 17 | output wire FlagOut_clkB; 18 | 19 | // this changes level when the FlagIn_clkA is seen in clkA 20 | reg FlagToggle_clkA; 21 | always @(posedge clkA or negedge a_rst_n) 22 | begin 23 | if(!a_rst_n) 24 | FlagToggle_clkA <= 1'b0; 25 | else 26 | FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA; 27 | end 28 | 29 | // which can then be sync-ed to clkB 30 | reg [2:0] SyncA_clkB; 31 | always @(posedge clkB or negedge b_rst_n) 32 | begin 33 | if(!b_rst_n) 34 | SyncA_clkB <= 3'b0; 35 | else 36 | SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA}; 37 | end 38 | 39 | // and recreate the flag in clkB 40 | assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]); 41 | /* 42 | 43 | always #20 clkA = ~clkA; 44 | always #3 clkB = ~clkB; 45 | initial begin 46 | clkB=0; 47 | clkA=0; 48 | FlagToggle_clkA=0; 49 | SyncA_clkB=0; 50 | FlagIn_clkA=0; 51 | @(negedge clkA); 52 | FlagIn_clkA=1; 53 | @(negedge clkA); 54 | FlagIn_clkA=0; 55 | 56 | repeat(5) 57 | @(negedge clkA); 58 | FlagIn_clkA=1; 59 | @(negedge clkA); 60 | FlagIn_clkA=0; 61 | end 62 | 63 | */ 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/new/include/BankLib.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | 22 | // **************************************************** 23 | // 24 | // Block Library : 25 | // 26 | // define the architecture of the blocks and banks 27 | // 28 | // **************************************************** 29 | 30 | `include "def.h" 31 | `include "data.h" 32 | `include "UserData.h" 33 | 34 | 35 | 36 | `ifdef x128P30B 37 | `define BLOCK_dim 131 38 | `elsif x128P30T 39 | `define BLOCK_dim 131 40 | `elsif x64P30B 41 | `define BLOCK_dim 67 42 | `elsif x64P30T 43 | `define BLOCK_dim 67 44 | `endif 45 | 46 | 47 | 48 | 49 | 50 | //! `define BLOCK_dim 131 51 | `define BLOCKDIM_range 0 : `BLOCK_dim - 1 52 | `define BLOCKADDR_dim 16 53 | `define BLOCKADDR_range `BLOCKADDR_dim - 1 : 0 54 | 55 | // ********* 56 | // 57 | // Parameter Block & Main Block 58 | 59 | // 60 | // ********* 61 | 62 | `define ParameterBlock_num 4 63 | `define ParameterBlock_size 16 // Size of Parameter Block (Kword) 64 | 65 | `ifdef x128P30B 66 | 67 | `define MainBlock_num 127 68 | 69 | `elsif x128P30T 70 | 71 | `define MainBlock_num 127 72 | 73 | `elsif x64P30B 74 | 75 | `define MainBlock_num 63 76 | 77 | `elsif x64P30T 78 | 79 | `define MainBlock_num 63 80 | 81 | `endif 82 | 83 | 84 | `define MainBlock_size 64 // Size of Main Block (Kword) 85 | 86 | 87 | 88 | module BankLib; 89 | 90 | integer BlockBoundaryStartAddr [`BLOCK_dim - 1 : 0]; // Block Boundary Start Address 91 | integer BlockBoundaryEndAddr [`BLOCK_dim - 1 : 0]; // Block Boundary End Address 92 | 93 | integer count; 94 | 95 | initial 96 | begin 97 | 98 | begin: block_building 99 | for (count = 0; count <= `BLOCK_dim - 1; count = count + 1) 100 | BuildBlockBoundary(`organization, count, BlockBoundaryStartAddr[count], BlockBoundaryEndAddr[count]); 101 | 102 | end 103 | 104 | end 105 | 106 | 107 | // ****************************************************************** 108 | // 109 | // TASK BuildBlockBoundary: Build the Blocks Boundaries in two arrays 110 | // 111 | // ****************************************************************** 112 | 113 | task BuildBlockBoundary; 114 | 115 | input organize; 116 | input n_block; 117 | output StartAddr; 118 | output EndAddr; 119 | 120 | reg [8*6:1] organize; 121 | integer n_block; 122 | integer StartAddr; 123 | integer EndAddr; 124 | 125 | begin 126 | 127 | if (organize == "top") begin 128 | 129 | if (n_block == 0) EndAddr = - 1; 130 | 131 | if (n_block > `MainBlock_num - 1 && n_block <= `MainBlock_num + `ParameterBlock_num - 1) // parameter block 132 | begin 133 | StartAddr = EndAddr + 1; 134 | EndAddr = StartAddr + `ParameterBlock_size * `Kword - 1; 135 | 136 | end 137 | 138 | else // Main block 139 | begin 140 | StartAddr = EndAddr + 1; 141 | EndAddr = StartAddr + `MainBlock_size * `Kword - 1; 142 | end 143 | 144 | end else begin // organize = "bottom" 145 | 146 | if (n_block == 0) EndAddr = - 1; 147 | 148 | if (n_block > `ParameterBlock_num - 1) 149 | begin 150 | StartAddr = (`ParameterBlock_num * `ParameterBlock_size * `Kword ) + 151 | (n_block - `ParameterBlock_num) * `MainBlock_size * `Kword; 152 | EndAddr = StartAddr + `MainBlock_size * `Kword - 1; 153 | end 154 | //! 155 | else // parameter block 156 | begin 157 | StartAddr = EndAddr + 1; 158 | EndAddr = StartAddr + `ParameterBlock_size * `Kword - 1; 159 | end 160 | 161 | end 162 | 163 | end 164 | endtask 165 | 166 | 167 | 168 | // ********************************************* 169 | // module work.MemoryModule:module (updated) 170 | // FUNCTION getBlock : return block from address 171 | // 172 | // ********************************************* 173 | 174 | function [`INTEGER] getBlock; // BLOCK_dim in binary is 9 bit size 175 | 176 | input address; 177 | 178 | reg [`ADDRBUS_dim - 1 : 0] address; 179 | reg found; 180 | integer count; 181 | 182 | begin 183 | 184 | count = 0; 185 | found = 0; 186 | while ((count <= `BLOCK_dim) && (! found)) 187 | begin 188 | 189 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) found= 1; 190 | else count = count + 1; 191 | 192 | end 193 | 194 | if (!found) $display("%t !Error in Block Library : specified block address is out of range",$time); 195 | 196 | getBlock= count; 197 | 198 | end 199 | endfunction 200 | 201 | 202 | // *************************** 203 | // 204 | // FUNCTION getBlockAddress : 205 | // return the block address 206 | // 207 | // *************************** 208 | 209 | function [`ADDRBUS_dim - 1 : 0] getBlockAddress; 210 | 211 | input block; 212 | 213 | integer block; 214 | 215 | begin 216 | 217 | getBlockAddress = BlockBoundaryStartAddr[block]; 218 | 219 | end 220 | endfunction 221 | 222 | 223 | // ********************************************* 224 | // 225 | // FUNCTION isParameterBlock : 226 | // return true if the address 227 | // is in a parameter block 228 | // 229 | // ********************************************* 230 | 231 | function isParameterBlock; 232 | 233 | input address; 234 | 235 | 236 | reg [`ADDRBUS_dim - 1 : 0] address; 237 | reg prm; 238 | integer count; 239 | 240 | begin 241 | 242 | prm = `FALSE; 243 | if (`organization=="bottom") begin 244 | 245 | for (count = 0; count <= `ParameterBlock_num - 1; count = count + 1) begin: cycle 246 | 247 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) 248 | begin 249 | prm= `TRUE; 250 | disable cycle; 251 | end 252 | end 253 | end else begin 254 | for (count = `BLOCK_dim - `ParameterBlock_num + 1; count <= `BLOCK_dim - 1; count = count + 1) begin: cycle1 255 | 256 | 257 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) 258 | begin 259 | prm= `TRUE; 260 | disable cycle1; 261 | end 262 | end 263 | end 264 | 265 | isParameterBlock = prm; 266 | 267 | end 268 | endfunction 269 | 270 | 271 | // ********************************************* 272 | // 273 | // FUNCTION isMainBlock : 274 | // return true if the address is in a main block 275 | // 276 | // ********************************************* 277 | 278 | function isMainBlock; 279 | 280 | input address; 281 | 282 | reg [`ADDRBUS_dim - 1 : 0] address; 283 | reg main; 284 | integer count; 285 | 286 | begin 287 | 288 | main = `FALSE; 289 | 290 | if (`organization=="bottom") begin 291 | for (count = `BLOCK_dim - 1; count >= `BLOCK_dim - `ParameterBlock_num + 1; count = count - 1) begin: cycle2 292 | 293 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) 294 | begin 295 | main = `TRUE; 296 | disable cycle2; 297 | end 298 | 299 | end 300 | end else begin 301 | for (count = 0; count <= `MainBlock_num - 1; count = count + 1) begin: cycle3 302 | 303 | 304 | if ((BlockBoundaryStartAddr[count] <= address) && (address <= BlockBoundaryEndAddr[count])) 305 | begin 306 | main = `TRUE; 307 | disable cycle3; 308 | end 309 | end 310 | end 311 | isMainBlock = main; 312 | end 313 | endfunction 314 | 315 | 316 | endmodule 317 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/new/include/CUIcommandData.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | 22 | // ********************** 23 | // 24 | // COMMAND USER INTERFACE 25 | // 26 | // ********************** 27 | 28 | // Read Commands 29 | 30 | `define RD_cmd 8'hFF // Read Memory Array 31 | `define RSR_cmd 8'h70 // Read Status Register 32 | `define RSIG_cmd 8'h90 // Read Electronic Signature 33 | `define RCFI_cmd 8'h98 // Read CFI 34 | 35 | 36 | // Program/Erase Commands 37 | 38 | `define PG_cmd 8'h40 // Program 39 | `define PES_cmd 8'hB0 // Program/Erase Suspend 40 | `define PER_cmd 8'hD0 // Program/Erase Resume 41 | `define BLKEE_cmd 8'h20 // Block Erase 42 | `define BLKEEconfirm_cmd 8'hD0 // Block Erase Confirm 43 | `define CLRSR_cmd 8'h50 // Clear Status Register 44 | `define PRREG_cmd 8'hC0 // Protection Register Program //verificare se va bene x OTP register program setup 45 | 46 | 47 | // Protect Commands 48 | 49 | `define BL_cmd 8'h60 // Block Lock //setup?? 50 | `define BUL_cmd 8'h60 // Block UnLock 51 | `define BLD_cmd 8'h60 // Block lock-down 52 | `define BLDconfirm_cmd 8'h2F // Block Lock-down confirm 53 | `define BLconfirm_cmd 8'h01 // Block Lock Confirm 54 | `define BULconfirm_cmd 8'hD0 // Block unLock Confirm 55 | 56 | 57 | // Additional Features Commands 58 | 59 | `define PB_cmd 8'hE8 // Program Buffer 60 | `define PBcfm_cmd 8'hD0 // Close Sequence of Program Buffer Command 61 | 62 | 63 | // Configuration Register 64 | 65 | `define SCR_cmd 8'h60 // Set Configuration Register 66 | `define SCRconfirm_cmd 8'h03 // Set Configuration Register confirm 67 | 68 | // Additional Features Commands //aggiunto 69 | `define BLNKCHK_cmd 8'hBC // Blank Check Command 70 | `define BLNKCHKconfirm_cmd 8'hD0 // Blank Check Confirm 71 | 72 | 73 | // Factory Program Commands 74 | `define BuffEnhProgram_cmd 8'h80 // Enhanced Setup Command 75 | `define BuffEnhProgramCfrm_cmd 8'hD0 // Enhanced Setup confirm 76 | 77 | `define EnhSetup_cmd 8'h80 // Enhanced Setup Command 78 | `define EnhSetup_cfrm 8'hD0 // Enhanced Setup confirm 79 | 80 | 81 | // CUI Status 82 | 83 | // Read Bus Status Operation 84 | 85 | `define ReadArray_bus 2'b00 // Read Memory Array 86 | `define ReadSignature_bus 2'b01 // Read Electronic Signature 87 | `define ReadStatusReg_bus 2'b10 // Read Status Register 88 | `define ReadCFI_bus 2'b11 // Read CFI 89 | 90 | 91 | // Program/Erase Controller Status 92 | 93 | `define Free_pes 0 // No Operation 94 | `define Program_pes 1 // Programming 95 | `define BlockErase_pes 2 // Erasing Block 96 | `define ChipErase_pes 3 // Chip Erasing 97 | `define BlockEraseSuspend_pes 4 // Block Erase Suspend 98 | `define ProgramEraseSuspend_pes 5 // Program/Erase Resume 99 | `define ProgramEraseWait_pes 6 // Program/Erase Wait 100 | `define Reset_pes 10 // Reset status 101 | 102 | 103 | 104 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/new/include/TimingData.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | `include "data.h" 22 | `include "UserData.h" 23 | 24 | `define Reset_time 300000 25 | 26 | // ********************************************* 27 | // 28 | // Table 29 29 | // Program/Erase Characteristics 30 | // 31 | // ********************************************* 32 | 33 | // Vpp = VppL 34 | 35 | `define ParameterBlockErase_time 400000000// 0.4 sec 36 | `define MainBlockErase_time 500000000 37 | 38 | `define WordProgram_time 40000 // 40 us 39 | `define ParameterBlockProgram_time 64000 // 40 | `define MainBlockProgram_time 256000 // 41 | 42 | `define ProgramSuspendLatency_time 15000 // 15 us 43 | `define EraseSuspendLatency_time 15000 // 15 us 44 | `define MainBlankCheck_time 3200000 45 | // Vpp = VppH 46 | 47 | `define FastParameterBlockErase_time 800000000 // 0.8 sec 48 | `define FastMainBlockErase_time 800000000 // 0.8 sec 49 | `define FastWordProgram_time 40000 50 | `define FastParameterBlockProgram_time 64000 51 | `define FastMainBlockProgram_time 256000 52 | 53 | `define BlockProtect_time 1800 54 | `define BlockUnProtect_time 5000000 55 | 56 | `define ProgramBuffer_time 700000 57 | 58 | 59 | `define EnhBuffProgram_time 512000 // 60 | `define EnhBuffProgramSetupPhase_time 5000 61 | 62 | 63 | 64 | // ********************** 65 | // 66 | // Timing Data Module : 67 | // set timing values 68 | // 69 | // ********************** 70 | 71 | module TimingDataModule; 72 | 73 | // ************************************ 74 | // 75 | // AC Read Specifications 76 | // 77 | // Table 27 78 | // 79 | // ************************************ 80 | 81 | integer tAVAV; // Address Valid to Next Address Valid 82 | integer tAVQV; // Address Valid to Output Valid (Random) 83 | integer tAVQV1; // Address Valid to Output Valid (Page) 84 | integer tELTV; // Chip Enable Low to Wait Valid 85 | integer tELQV; // Chip Enable Low to Output Valid 86 | integer tELQX; // Chip Enable Low to Output Transition 87 | integer tEHTZ; // Chip Enable High to Wait Hi-Z 88 | integer tEHQX;//tOH // Chip Enable High to Output Transition 89 | integer tEHQZ; // Chip Enable High to Output Hi-Z 90 | integer tGLQV; // Output Enable Low to Output Valid 91 | integer tGLQX; // Output Enable Low to Output Transition 92 | integer tGHQZ; // Output Enable High to Output Hi-Z 93 | integer tAVLH;//tAVVH // Address Valid to (ADV#) Latch Enable High 94 | integer tELLH; //tELVH // Chip Enable Low to Latch Enable High 95 | integer tLHAX; //tVHAX // Latch Enable High to Address Transition 96 | integer tLLLH; //tVLVH // Latch Enable Low to Latch Enable High 97 | integer tLLQV; //tVLQV // Latch Enable Low to Output Valid 98 | 99 | integer tGLTV; //// Output Enable Low to Wait Valid 100 | integer tGLTX; //// Output Enable Low to Wait Transition 101 | integer tGHTZ; //// Output Enable high to Wait Hi-Z 102 | 103 | 104 | 105 | 106 | 107 | integer tAVKH; //tAVCH/L // Address Valid to Clock High 108 | integer tELKH; //tELCH // Chip Enable Low to Clock High 109 | integer tEHEL;// tEHEL // Chip Enable High to Chip Enable Low (reading) 110 | integer tKHAX;//tCHAX // Clock High to Address Transition 111 | integer tKHQV; //tCHQV // Clock High to Output Enable Valid 112 | integer tKHTV; //tCHTV // Clock High to Wait Valid 113 | integer tKHQX; //tCHQX // Clock High to Output Enable Transition 114 | integer tKHTX; //tCHTX // Clock High to Wait Transition 115 | integer tLLKH; //tVLCH/L // Latch Enable Low to Clock High 116 | integer tLLKL; //tVLCH/L // Latch Enable Low to Clock High 117 | integer tKHLL; //tCHVL //Clock valid to ADV# setup 118 | integer tKHKH; //tCLK // Clock Period 119 | integer tKHKL; //tCH/CL // Clock High to Clock Low 120 | integer tKLKH; // Clock Low to Clock High 121 | integer tCK_fall; //R203 // Clock Fall Time 122 | integer tCK_rise; // Clock Rise Time 123 | 124 | 125 | // ************************************************* 126 | // 127 | // AC Write Specifications 128 | // 129 | // Table 28 130 | // 131 | // ************************************************* 132 | 133 | integer tAVWH; // Address Valid to Write Enable High 134 | integer tDVWH; // Data Valid to Write Enable High 135 | integer tELWL; // Chip Enable Low to Write Enable Low 136 | integer tWHAV; //W18 // Write Enable High to Address Valid 137 | integer tWHAX; // Write Enable High to Address Transition 138 | integer tWHDX; // Write Enable High to Data Transition 139 | integer tWHEH; // Write Enable High to Chip Enable High 140 | integer tWHGL; // Write Enable High to Output Enable High 141 | integer tWHLL; //W28 tWHVL // Write Enable High to Latch Enable Low 142 | integer tWHWL; // Write Enable High to Latch Enable Low 143 | integer tWHQV; // Write Enable High to Output Enable Valid 144 | integer tWLWH; // Write Enable Low to Write Enable High 145 | integer tQVVPL; //tQVVL // Output (Status Register) Valid to Vpp Low 146 | integer tQVWPL; //tQVBL // Output (Status Register) Valid to Write Protect Low 147 | integer tVPHWH; // Vpp High to Write Enable High 148 | integer tWPHWH; //tBHWH // Write Protect High to Write Enable High 149 | 150 | 151 | integer tELEH; // Chip Enable Low to Chip Enable High 152 | 153 | 154 | //!// ************************************* 155 | //!// 156 | //!// Power and Reset 157 | //!// 158 | //!// Table 20 159 | //!// 160 | //!// ************************************** 161 | 162 | integer tPHWL; //W1 // Reset High to Write Enable Low 163 | integer tPLPH;//P1 // Reset High to Reset Low 164 | 165 | integer tVDHPH; //tVCCPH // Supply voltages High to Reset High 166 | 167 | 168 | 169 | initial begin 170 | 171 | setTiming(`t_access); 172 | 173 | end 174 | 175 | // ********************** 176 | // 177 | // FUNCTION getTime : 178 | // return time value 179 | // 180 | // ********************** 181 | 182 | function getTime; 183 | 184 | input [8*31 : 0] time_str; 185 | 186 | begin 187 | 188 | 189 | 190 | end 191 | endfunction 192 | 193 | // ********************** 194 | // 195 | // Task setTiming : 196 | // set timing values 197 | // 198 | // ********************** 199 | 200 | task setTiming; 201 | 202 | input time_access; 203 | 204 | integer time_access; 205 | 206 | begin 207 | 208 | // *********************************************** 209 | // 210 | // AC Read Specifications 211 | // 212 | // Table 27 213 | // 214 | // *********************************************** 215 | 216 | tELQX = 0; 217 | tEHQX = 0; 218 | tGLQX = 0; 219 | tGHQZ = 15; 220 | tELLH = 10; 221 | 222 | tAVAV = time_access; 223 | tAVQV = time_access; 224 | tELQV = time_access; 225 | tLLQV = time_access; 226 | 227 | tEHTZ = 20; 228 | tAVQV1 = 25; 229 | tELTV = 17; 230 | 231 | tEHEL = 17; 232 | tCK_fall = 3; 233 | tCK_rise = 3; 234 | tEHQZ = 20; 235 | tGLQV = 25; 236 | tAVLH = 10; 237 | tLHAX = 9; 238 | tLLLH = 10; 239 | 240 | tAVKH = 9; 241 | tELKH = 9; 242 | tKHAX = 10; 243 | tKHQV = 17; 244 | tKHTV = 17; 245 | tKHQX = 3; 246 | tKHTX = 3; 247 | tLLKH = 9; 248 | tLLKL = 9; 249 | tKHLL = 3; 250 | tKHKH = 19.2; 251 | tKHKL = 5; 252 | tKLKH = 5; 253 | tGLTV = 17; 254 | tGLTX = 0; 255 | tGHTZ = 20; 256 | 257 | // ************************************************* 258 | // 259 | // AC Write Specifications 260 | // 261 | // Table 28 262 | // 263 | // ************************************************* 264 | 265 | tELWL = 0; 266 | tWHAV = 0; 267 | tWHAX = 0; 268 | tWHDX = 0; 269 | tWHEH = 0; 270 | tWHGL = 0; 271 | tWHLL = 7; 272 | tQVVPL = 0; 273 | tQVWPL = 0; 274 | tVPHWH = 200; 275 | tWPHWH = 200; 276 | tAVWH = 50; 277 | 278 | tDVWH = 50; 279 | tWHWL = 20; 280 | tWHQV = tAVQV + 35; //tAVQV+35 281 | tWLWH = 50; 282 | tELEH = 50; 283 | 284 | // ************************************* 285 | // 286 | // Power and Reset 287 | // 288 | // Table 20 289 | // 290 | // ************************************** 291 | 292 | tPHWL = 150; 293 | tPLPH = 100; 294 | tVDHPH = 60; 295 | 296 | 297 | end 298 | endtask 299 | 300 | endmodule 301 | 302 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/new/include/UserData.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | 22 | // ************************************ 23 | // 24 | // User Data definition file : 25 | // 26 | // here are defined all parameters 27 | // that the user can change 28 | // 29 | // ************************************ 30 | 31 | //`define x128P30T // Select the device. Possible value are: x128P30B, x128P30T 32 | `define x64P30T // x64P30B, x64P30T 33 | 34 | 35 | //!`define organization "top" // top or bottom 36 | `define BLOCKPROTECT "on" // if on the blocks are locked at power-up 37 | `define TimingChecks "on" // on for checking timing constraints 38 | `define t_access 65 // Access Time 65 ns, 75 ns 39 | `define FILENAME_mem "flash_content.mem" // Memory File Name 40 | 41 | 42 | 43 | 44 | `ifdef x128P30B 45 | `define organization "bottom" 46 | `elsif x128P30T 47 | `define organization "top" // top, bottom 48 | `elsif x64P30B 49 | `define organization "bottom" 50 | `elsif x64P30T 51 | `define organization "top" 52 | `else 53 | `define organization "bottom" 54 | `endif 55 | 56 | 57 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/new/include/data.h: -------------------------------------------------------------------------------- 1 | // _/ _/_/ 2 | // _/_/ _/_/_/ 3 | // _/_/_/_/ _/_/_/ 4 | // _/_/_/_/_/ _/_/_/ ____________________________________________ 5 | // _/_/_/_/_/ _/_/_/ / / 6 | // _/_/_/_/_/ _/_/_/ / 28F640P30 / 7 | // _/_/_/_/_/ _/_/_/ / / 8 | // _/_/_/_/_/_/ _/_/_/ / 128Mbit / 9 | // _/_/_/_/_/_/ _/_/_/ / Single bit per Cell / 10 | // _/_/_/ _/_/_/ _/_/_/ / / 11 | // _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model / 12 | // _/_/_/ _/_/_/ _/_/_/ / Version 1.1 / 13 | // _/_/_/ _/_/_/ _/_/_/ / / 14 | // _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. / 15 | // _/_/_/ _/_/_/_/_/ /___________________________________________/ 16 | // _/_/_/ _/_/_/_/ 17 | // _/_/ _/_/_/ 18 | // 19 | // 20 | // NUMONYX 21 | `include "UserData.h" 22 | // ****** 23 | // 24 | // data.h 25 | // 26 | // ****** 27 | 28 | // ******************** 29 | // 30 | // Main Characteristics 31 | // 32 | // ******************** 33 | 34 | `ifdef x128P30B 35 | 36 | `define ADDRBUS_dim 23 // - Address Bus pin numbers 37 | 38 | `elsif x128P30T 39 | 40 | `define ADDRBUS_dim 23 41 | 42 | `else 43 | 44 | `define ADDRBUS_dim 22 45 | 46 | `endif 47 | 48 | `define DATABUS_dim 16 // - Data Bus pin numbers 49 | `define MEMORY_dim 1 << `ADDRBUS_dim // - Memory Dimension 50 | `define LAST_ADDR (`MEMORY_dim) - 1 // - Last Address 51 | 52 | // ******************** 53 | // 54 | // Address & Data range 55 | // 56 | // ******************** 57 | 58 | `define ADDRBUS_range `ADDRBUS_dim - 1 : 0 59 | `define DATABUS_range `DATABUS_dim - 1 : 0 60 | 61 | // ***************** 62 | // 63 | // Init Memory Files 64 | // 65 | // ***************** 66 | 67 | `define CFI_dim 9'h157 68 | `define CFI_range `CFI_dim - 1:9'h10 69 | // ******************* 70 | // 71 | // Protection Register 72 | // 73 | // ******************* 74 | 75 | 76 | `define REG_addrStart 16'h0 77 | `define REG_addrEnd 16'h15 78 | 79 | `define REGSTART_addr 9'h80 // Protection Register Start Address 80 | `define REGEND_addr 9'h109 // Protection Register End Address 81 | `define REG_dim `REGEND_addr - `REGSTART_addr + 1 82 | 83 | `define REG_addrRange `REG_addrEnd:`REG_addrStart 84 | 85 | `define REG_addrbitStart 8'd0 86 | `define REG_addrbitEnd 8'd8 87 | `define REG_addrbitRange `REG_addrbitEnd:`REG_addrbitStart 88 | 89 | `define PROTECTREGLOCK_addr 9'h80 // Protection Register Lock Address 90 | 91 | 92 | `define UDNREGSTART_addr 9'h81 93 | `define UDNREGEND_addr 9'h84 94 | `define UDNprotect_bit 8'hFE 95 | 96 | `define UPREGSTART_addr 9'h85 97 | `define UPREGEND_addr 9'h88 98 | `define UPprotect_bit 8'hFD // serve ad indentificare quale bit deve essere 0 nel lock regi 99 | `define PRL_default 16'h0002 // Protection Register Lock default definito anche in def 100 | 101 | // ***************************** 102 | // 103 | // Extended User OTP 104 | // 105 | // ***************************** 106 | 107 | `define ExtREG_dim 8'h20 108 | 109 | 110 | `define ExtREG_regiondim 8'h8 111 | `define ExtREGSTART_regionaddr 9'h8A // Ext Protection Register Start Address 112 | `define ExtREGEND_regionaddr 9'h109 // Ext Protection Register End Address 113 | 114 | `define ExtPROTECTREGLOCK_addr 9'h89 // Ext Protection Register Lock Address 115 | `define ExtPRL_default 16'hFFFF // Protection Register Lock default 116 | 117 | 118 | 119 | // *********************** 120 | // 121 | // Voltage Characteristics 122 | // 123 | // *********************** 124 | `define Voltage_range 35:0 125 | `define VDDmin 36'd02300 126 | `define VDDmax 36'd03600 127 | `define VDDQmin 36'd02300 128 | `define VDDQmax 36'd03600 129 | `define VPPmin 36'd00900 130 | `define VPPmax 36'd03600 131 | `define VPPHmin 36'd08500 132 | `define VPPHmax 36'd09500 133 | 134 | // ********************** 135 | // 136 | // Configuration Register 137 | // 138 | // ********************** 139 | 140 | `define ConfigurationReg_dim 16 141 | `define ConfigReg_default 16'hBBCF 142 | 143 | // ******************** 144 | // 145 | // Electronic Signature 146 | // 147 | // ******************** 148 | 149 | `define ManufacturerCode 8'h89 150 | 151 | `ifdef x128P30B 152 | 153 | `define TopDeviceCode 8'h18 154 | `define BottomDeviceCode 8'h1B 155 | 156 | `elsif x128P30T 157 | `define TopDeviceCode 8'h18 158 | `define BottomDeviceCode 8'h1B 159 | 160 | `else 161 | `define TopDeviceCode 8'h17 162 | `define BottomDeviceCode 8'h1A 163 | 164 | `endif 165 | 166 | 167 | 168 | `define SignAddress_dim 9 169 | `define SignAddress_range `SignAddress_dim - 1 : 0 170 | 171 | 172 | 173 | // ********************* 174 | // 175 | // Write Buffer constant 176 | // 177 | // ********************* 178 | 179 | 180 | `define ProgramBuffer_addrDim 8 // Program Buffer address dimension 181 | `define ProgramBuffer_addrRange `ProgramBuffer_addrDim - 1:0 182 | `define ProgramBuffer_dim 256 // Buffer Size= 2 ^ ProgramBuffer_addrDim 183 | `define ProgramBuffer_range `ProgramBuffer_dim - 1:0 184 | 185 | // ********************* 186 | // 187 | // Buffer Enhanced Program constant 188 | // 189 | // ********************* 190 | 191 | `define BuffEnhProgramBuffer_dim 256 192 | `define BuffEnhProgramBuffer_range `BuffEnhProgramBuffer_dim - 1 : 0 193 | `define BuffEnhProgramBuffer_addrDim 8 194 | `define BuffEnhProgramBuffer_addrRange `BuffEnhProgramBuffer_addrDim - 1:0 195 | 196 | 197 | // Warning and Error Messages 198 | 199 | `define NoError_msg 0 // No Error Found 200 | `define CmdSeq_msg 1 // Sequence Command Unknown 201 | `define SuspCmd_msg 2 // Cannot execute this command during suspend 202 | `define SuspAcc_msg 3 // Cannot access this address due to suspend 203 | `define AddrRange_msg 4 // Address out of range 204 | `define AddrTog_msg 5 // Cannot change block address during command sequence 205 | `define SuspAccWarn_msg 6 // It isn't possible access this address due to suspend 206 | `define InvVDD_msg 7 // Voltage Supply must be: VDD>VDDmin or VDDVDDmin or VDD>~/.bashrc 12 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/.gitignore: -------------------------------------------------------------------------------- 1 | *.mp4 2 | kernel/kernel.elf 3 | kernel/kernel.bin 4 | kernel/.config_* 5 | */obj/* 6 | *.test 7 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/.test-script: -------------------------------------------------------------------------------- 1 | #!/usr/bin/expect 2 | 3 | set timeout 5 4 | spawn term/term.py -t 127.0.0.1:6666 5 | 6 | expect "MONITOR for MIPS32 - initialized." {} timeout {exit 1} 7 | 8 | expect ">>" 9 | send "R\n" 10 | 11 | expect ">>" 12 | send "R\n" 13 | 14 | expect ">>" 15 | send "A\n" 16 | send "80100000\n" 17 | expect "one instruction per line" 18 | expect "]" 19 | send "addiu \$2,\$0,1\n" 20 | expect "]" 21 | send "addu \$3,\$2,\$2\n" 22 | expect "]" 23 | send "jr \$31\n" 24 | expect "]" 25 | send "nop\n" 26 | expect "]" 27 | send "\n" 28 | 29 | expect ">>" 30 | send "D\n" 31 | send "80100000\n" 32 | send "16\n" 33 | expect -re "0x80100000: +0x24020001" {} timeout {exit 1} 34 | 35 | expect ">>" 36 | send "U\n" 37 | send "80100000\n" 38 | send "16\n" 39 | 40 | expect ">>" 41 | send "G\n" 42 | send "80100000\n" 43 | expect "elapsed time" {} timeout {exit 1} 44 | 45 | expect ">>" 46 | send "R\n" 47 | expect -re "R3.+0x00000002" {} timeout {exit 1} 48 | 49 | # TLB required 50 | expect ">>" 51 | send "G\n" 52 | send "0\n" 53 | expect "elapsed time" {} timeout {exit 1} 54 | 55 | expect ">>" 56 | send "T\n" 57 | send " -1\n" 58 | expect -re "00000_000 +00100_000 +0 +1 +1 +1" {} timeout {exit 1} 59 | 60 | expect ">>" 61 | send "D\n" 62 | send "0\n" 63 | send "16\n" 64 | expect -re "0x00000000: +0x24020001" {} timeout {exit 1} 65 | 66 | expect ">>" 67 | send "Q\n" 68 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/.travis.yml: -------------------------------------------------------------------------------- 1 | language: c 2 | before_install: 3 | - sudo apt-get install -yy qemu-system-mips expect python3-pip 4 | - sudo pip3 install pyserial 5 | - curl -sc /tmp/gcokie 'https://drive.google.com/uc?export=download&id=1Mo5hGcCg1zm8Ca0KQB-G5PNI3fXfAAmR' 6 | - getcode="$(awk '/_warning_/ {print $NF}' /tmp/gcokie)" 7 | - curl -s -C - -LOJb /tmp/gcokie "https://drive.google.com/uc?export=download&confirm=${getcode}&id=1Mo5hGcCg1zm8Ca0KQB-G5PNI3fXfAAmR" 8 | - tar -xf Codescape.GNU.Tools.Package.2016.05-06.for.MIPS.MTI.Bare.Metal.CentOS-5.x86_64.tar.gz 9 | script: 10 | - export PATH=$PATH:$PWD/mips-mti-elf/2016.05-06/bin 11 | - make GCCPREFIX=mips-mti-elf- ON_FPGA=y -C kernel/ all show-utest 12 | - | 13 | if [[ -n "$TRAVIS_TAG" ]]; then 14 | mkdir "$TRAVIS_TAG/kernel" 15 | cp kernel/kernel.bin "$TRAVIS_TAG/kernel/kernel-fpga.bin" 16 | cp kernel/kernel.elf "$TRAVIS_TAG/kernel/kernel-fpga.elf" 17 | fi 18 | - make GCCPREFIX=mips-mti-elf- ON_FPGA=n EN_INT=y EN_TLB=y -C kernel/ 19 | - | 20 | if [[ -n "$TRAVIS_TAG" ]]; then 21 | cp kernel/kernel.elf "$TRAVIS_TAG/kernel/kernel-qemu-int-tlb.elf" 22 | fi 23 | - travis_wait 1 make EN_INT=y EN_TLB=y sim -C kernel || true 24 | - "./.test-script" 25 | addons: 26 | apt: 27 | update: true 28 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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/2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/README.md: -------------------------------------------------------------------------------- 1 | # supervisor-32： 32位监控程序（“龙芯杯”个人赛） 2 | 3 | [查看最新版本](https://github.com/z4yx/supervisor-mips32/tree/simplified) 4 | 5 | ## 介绍 6 | 7 | 本监控程序能够接受用户命令，支持输入汇编指令并运行，查看寄存器及内存状态等功能。监控程序可在学生实现的 32 位 MIPS CPU 上运行，一方面可以帮助学生理解、掌握 MIPS 指令系统及其软件开发，另一方面可以作为验证学生 CPU 功能正确性的标准。 8 | 9 | 监控程序分为两个部分，Kernel 和 Term。其中 Kernel 使用 MIPS32 汇编语言编写，运行在 FPGA 上学生实现的 CPU 中，用于管理硬件资源；Term 是上位机程序，使用 Python 语言编写，有基于命令行的用户界面，达到与用户交互的目的。Kernel 和 Term 直接通过串口通信，即用户在 Term 界面中输入的命令、代码经过 Term 处理后，通过串口传输给 Kernel 程序；反过来，Kernel 输出的信息也会通过串口传输到 Term，并展示给用户。 10 | 11 | ## Kernel 使用说明 12 | 13 | Kernel 使用汇编语言编写，使用到的指令有20余条，均符合 MIPS32 Release2 规范。为了在硬件上运行 Kernel 程序，我们首先要对 Kernel 的汇编代码进行编译。 14 | 15 | Linux环境在编译时须使用MTI Bare Metal工具链：[Linux版下载](https://cloud.tsinghua.edu.cn/f/16dde018b00749a4a4de/) 。将下载的压缩包解压到任意目录后，设置环境变量 `GCCPREFIX` 以便 make 工具找到编译器，例如压缩包解压到`/opt`： 16 | 17 | `export GCCPREFIX=/opt/mips-mti-elf/2016.05-06/bin/mips-mti-elf-` 18 | 19 | 下面是编译监控程序的过程。在`kernel`文件夹下面，有汇编代码和 Makefile 文件，我们可以使用 make 工具编译 Kernel 程序。假设当前目录为 `kernel` ，目标版本为基础版本，我们在终端中运行命令 20 | 21 | `make ON_FPGA=n` 22 | 23 | 即可开始编译流程。如果顺利结束，将生成 `kernel.elf` 和 `kernel.bin` 文件，即可执行文件。要在模拟器中运行它，可以使用命令 24 | 25 | `make sim` 26 | 27 | 它会在 QEMU 中启动监控程序，并等待 Term 程序连接。本文后续章节介绍了如何使用 Term 连接模拟器。 28 | 29 | 若要在编译硬件上运行的 kernel（与 QEMU 版本的区别是串口外设不同），首先用 `make clean` 清除之前编译的结果，最后用命令 30 | 31 | `make ON_FPGA=y` 32 | 33 | 编译用于硬件的 `kernel.bin`。使用开发板提供的工具，将 `kernel.bin` 写入内存 0 地址（物理地址）位置，并让处理器复位从 0x8000000 地址（MIPS32中对应物理地址为0的虚地址）处开始执行，Kernel 就运行起来了。 34 | 35 | Kernel 运行后会先通过串口输出版本号，该功能可作为检验其正常运行的标志。之后 Kernel 将等待 Term 从串口发来的命令，关于 Term 的使用将在后续章节描述。 36 | 37 | 接下来我们分别说明三个档次的监控程序对于硬件的要求，及简要的设计思想。 38 | 39 | ### 指令集 40 | 41 | 基础版本的 Kernel 共使用了22条不同的指令，它们是： 42 | 43 | 1. `ADDIU` 001001ssssstttttiiiiiiiiiiiiiiii 44 | 1. `ADDU` 000000ssssstttttddddd00000100001 45 | 1. `AND` 000000ssssstttttddddd00000100100 46 | 1. `ANDI` 001100ssssstttttiiiiiiiiiiiiiiii 47 | 1. `BEQ` 000100ssssstttttoooooooooooooooo 48 | 1. `BGTZ` 000111sssss00000oooooooooooooooo 49 | 1. `BNE` 000101ssssstttttoooooooooooooooo 50 | 1. `J` 000010iiiiiiiiiiiiiiiiiiiiiiiiii 51 | 1. `JAL` 000011iiiiiiiiiiiiiiiiiiiiiiiiii 52 | 1. `JR` 000000sssss0000000000hhhhh001000 53 | 1. `LB` 100000bbbbbtttttoooooooooooooooo 54 | 1. `LUI` 00111100000tttttiiiiiiiiiiiiiiii 55 | 1. `LW` 100011bbbbbtttttoooooooooooooooo 56 | 1. `MUL` 011100ssssstttttddddd00000000010 57 | 1. `OR` 000000ssssstttttddddd00000100101 58 | 1. `ORI` 001101ssssstttttiiiiiiiiiiiiiiii 59 | 1. `SB` 101000bbbbbtttttoooooooooooooooo 60 | 1. `SLL` 00000000000tttttdddddaaaaa000000 61 | 1. `SRL` 00000000000tttttdddddaaaaa000010 62 | 1. `SW` 101011bbbbbtttttoooooooooooooooo 63 | 1. `XOR` 000000ssssstttttddddd00000100110 64 | 1. `XORI` 001110ssssstttttiiiiiiiiiiiiiiii 65 | 66 | 根据 MIPS32 规范（在参考文献中）正确实现这些指令后，程序才能正常工作。 67 | 68 | CPU 须支持延迟槽，不需要实现CP0、HI、LO寄存器，不需要实现异常、中断，不需要实现TLB。 69 | 70 | ### 内存映射 71 | 72 | 监控程序使用了 8 MB 的内存空间，其中约 1 MB 由 Kernel 使用，剩下的空间留给用户程序。此外，为了支持串口通信，还设置了一个内存以外的地址区域，用于串口收发。具体内存地址的分配方法如下表所示： 73 | 74 | 75 | | 虚地址区间 | 说明 | 76 | | --- | --- | 77 | | 0x80000000-0x800FFFFF | 监控程序代码 | 78 | | 0x80100000-0x803FFFFF | 用户代码空间 | 79 | | 0x80400000-0x807EFFFF | 用户数据空间 | 80 | | 0x807F0000-0x807FFFFF | 监控程序数据 | 81 | | 0xBFD003F8-0xBFD003FD | 串口数据及状态| 82 | 83 | 串口控制器访问的代码位于`kern/utils.S`，其数据格式为： 84 | 85 | | 地址 | 位 | 说明 | 86 | | --- | --- |--- | 87 | | 0xBFD003F8| [7:0] | 串口数据，读、写地址分别表示串口接收、发送一个字节| 88 | | 0xBFD003FC| [0] | 只读，为1时表示串口空闲，可发送数据| 89 | | 0xBFD003FC| [1] | 只读，为1时表示串口收到数据| 90 | 91 | Kernel 的入口地址为 0x80000000，对应汇编代码`kern/evec.S`中的 `INITLOCATE:`标签。在完成必要的初始化流程后，Kernel 输出版本信息，随后进入 shell 线程，与用户交互。shell 线程会等待串口输入，执行输入的命令，并通过串口返回结果，如此往复运行。 92 | 93 | 当收到启动用户程序的命令后，用户线程代替 shell 线程的活动。用户程序的寄存器，保存在从 0x807F0000 到 0x807F0077 的连续120字节中，依次对应 \$1 到 \$30 用户寄存器，每次启动用户程序时从上述地址装载寄存器值，用户程序运行结束后保存到上述地址。 94 | 95 | 96 | ## Term 使用说明 97 | 98 | Term 程序运行在实验者的电脑上，提供监控程序和人交互的界面。Term 支持7种命令，它们分别是 99 | 100 | - R：按照\$1至\$30的顺序返回用户程序寄存器值。 101 | - D：显示从指定地址开始的一段内存区域中的数据。 102 | - A：用户输入汇编指令或者数据，并放置到指定地址上。输入行只有数值时视为数据，否则为指令。 103 | - F：从文件读入汇编指令或者数据，并放置到指定地址上，格式与 A 命令相同。 104 | - U：从指定地址读取一定长度的数据，并显示反汇编结果。 105 | - G：执行指定地址的用户程序。 106 | - Q：退出 Term 107 | 108 | 利用这些命令，实验者可以输入一段汇编程序，检查数据是否正确写入，并让程序在处理器上运行验证。 109 | 110 | Term 程序位于`term`文件夹中，可执行文件为`term.py`，运行前需要安装Python程序。 111 | 112 | 由于Term程序会调用汇编器，如果是Linux环境，在使用时须设置环境变量 `GCCPREFIX`，设置方法与编译 Kernel 时的配置相同，例如： 113 | 114 | `export GCCPREFIX=/opt/mips-mti-elf/2016.05-06/bin/mips-mti-elf-` 115 | 116 | 设置好环境后，即可连接远程实验平台串口或者 QEMU 模拟器。启动时使用 `-t` 选项指定 IP 和端口。例如连接模拟器时： 117 | 118 | `python term.py -t 127.0.0.1:6666` 119 | 120 | ### 测试程序 121 | 122 | 监控程序附带了几个测试程序，代码见`kern/test.S`。Kernel在编译时会显示测试程序入口地址。 123 | 124 | 记下这些地址，并在 Term 中使用G命令运行它们。 125 | 126 | ### 用户程序编写 127 | 128 | 根据监控程序设计，用户程序的代码区为0x80100000-0x803FFFFF，实验时需要把用户程序写入这一区域。用户程序的最后需要以`jr $31`结束，从而保证正确返回监控程序。 129 | 130 | 在输入用户程序的过程中，既可以用汇编指令，也可以直接写16进制的数据（机器码）。空行表示输入结束。 131 | 132 | 以下是一次输入用户程序并运行的过程演示： 133 | 134 | MONITOR for MIPS32 - initialized. 135 | >> a 136 | >>addr: 0x80100000 137 | one instruction per line, empty line to end. 138 | [0x80100000] ori $v0,$0,5 139 | [0x80100004] xor $t0,$t0,$t0 140 | [0x80100008] xor $t1,$t1,$t1 141 | [0x8010000c] loop: 142 | [0x8010000c] addu $t1,$t1,$t0 143 | [0x80100010] addiu $t0,$t0,1 144 | [0x80100014] bne $v0,$t0,loop 145 | [0x80100018] nop 146 | [0x8010001c] jr $ra 147 | [0x80100020] nop 148 | [0x80100024] 149 | >> u 150 | >>addr: 0x80100000 151 | >>num: 64 152 | 0x80100000: li v0,0x5 153 | 0x80100004: xor t0,t0,t0 154 | 0x80100008: xor t1,t1,t1 155 | 0x8010000c: addu t1,t1,t0 156 | 0x80100010: addiu t0,t0,1 157 | 0x80100014: bne v0,t0,0x8010000c 158 | 0x80100018: nop 159 | 0x8010001c: jr ra 160 | 0x80100020: nop 161 | 0x80100024: nop 162 | 0x80100028: nop 163 | 0x8010002c: nop 164 | 0x80100030: nop 165 | 0x80100034: nop 166 | 0x80100038: nop 167 | 0x8010003c: nop 168 | >> g 169 | >>addr: 0x80100000 170 | 171 | elapsed time: 0.000s 172 | >> r 173 | R1 (AT) = 0x00000000 174 | R2 (v0) = 0x00000005 175 | R3 (v1) = 0x00000000 176 | R4 (a0) = 0x00000000 177 | R5 (a1) = 0x00000000 178 | R6 (a2) = 0x00000000 179 | R7 (a3) = 0x00000000 180 | R8 (t0) = 0x00000005 181 | R9 (t1) = 0x0000000a 182 | R10(t2) = 0x00000000 183 | R11(t3) = 0x00000000 184 | R12(t4) = 0x00000000 185 | R13(t5) = 0x00000000 186 | R14(t6) = 0x00000000 187 | R15(t7) = 0x00000000 188 | R16(s0) = 0x00000000 189 | R17(s1) = 0x00000000 190 | R18(s2) = 0x00000000 191 | R19(s3) = 0x00000000 192 | R20(s4) = 0x00000000 193 | R21(s5) = 0x00000000 194 | R22(s6) = 0x00000000 195 | R23(s7) = 0x00000000 196 | R24(t8) = 0x00000000 197 | R25(t9/jp) = 0x00000000 198 | R26(k0) = 0x00000000 199 | R27(k1) = 0x00000000 200 | R28(gp) = 0x00000000 201 | R29(sp) = 0x807f0000 202 | R30(fp/s8) = 0x807f0000 203 | >> q 204 | 205 | ## 参考文献 206 | 207 | - CPU采用的MIPS32指令集标准：MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set 208 | - MIPS32中断及TLB等特权态资源：MIPS32® Architecture For Programmers Volume III: The MIPS32® Privileged Resource Architecture 209 | 210 | ## 项目作者 211 | 212 | - 初始版本：韦毅龙，李成杰，孟子焯 213 | - 后续维护：张宇翔，董豪宇 214 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/kernel/.gdbinit: -------------------------------------------------------------------------------- 1 | set endian little 2 | set mipsfpu none 3 | target remote 127.0.0.1:1234 4 | symbol-file kernel.elf 5 | #add-symbol-file boot/loader 0xbfc00000 6 | 7 | layout split 8 | until START 9 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/kernel/Makefile: -------------------------------------------------------------------------------- 1 | RM := rm -f 2 | ifeq ($(OS),Windows_NT) 3 | # Windows Host 4 | GCCPREFIX ?= mips-mti-elf- 5 | else 6 | #GCCPREFIX := mipsel-linux-gnu- 7 | GCCPREFIX ?= mips-mti-elf- 8 | endif 9 | QEMU := qemu-system-mipsel 10 | LD := $(GCCPREFIX)ld 11 | CC := $(GCCPREFIX)gcc 12 | MODULE := init 13 | OBJDIR := obj 14 | INCLUDE := include 15 | SRCDIR := kern 16 | LDSCRIPT := kern/kernel.ld 17 | SRC := $(foreach sdir, $(SRCDIR), $(wildcard $(sdir)/*.S)) 18 | OBJ := $(patsubst $(SRCDIR)/%.S, $(OBJDIR)/%.o, $(SRC)) 19 | TARGET := kernel.elf 20 | ASFLAG := -D__ASSEMBLY__ -EL -g -mips32r2 -mno-abicalls -mno-shared 21 | 22 | override ON_FPGA ?= n 23 | 24 | ifeq ($(ON_FPGA), y) 25 | MACH_DEF = -DMACH_FPGA 26 | else 27 | MACH_DEF = -DMACH_QEMU 28 | endif 29 | ASFLAG += $(MACH_DEF) 30 | 31 | 32 | CONFIG_FILE := .config_$(ON_FPGA)_$(EN_INT)_$(EN_TLB) 33 | 34 | .PHONY: all clean checkdirs show-utest commits-num sim 35 | 36 | all: $(TARGET) kernel.bin show-utest 37 | 38 | $(CONFIG_FILE): 39 | @rm -f .config_* 40 | touch $@ 41 | 42 | $(TARGET): checkdirs $(OBJ) $(LDSCRIPT) 43 | $(LD) $(OBJ) -T$(LDSCRIPT) 44 | 45 | $(OBJ): $(OBJDIR)/%.o : $(SRCDIR)/%.S $(CONFIG_FILE) 46 | $(CC) -o $@ $< -c -I$(INCLUDE) $(ASFLAG) 47 | 48 | 49 | checkdirs: $(OBJDIR) 50 | 51 | $(OBJDIR): 52 | test -d $@ || mkdir $@ 53 | 54 | kernel.bin: $(TARGET) 55 | @$(GCCPREFIX)objcopy -j .text -O binary -v $< kernel.bin 56 | 57 | show-utest: $(TARGET) 58 | @$(GCCPREFIX)objdump -D $< | grep "^[0-9a-f]\{8\} 4 | 5 | #define PAGE_SIZE 0x1000 // 4KB页 6 | #define RAM0UBASE 0x80100000 7 | #define RAM1BASE 0x80400000 8 | #define RAM1KBASE 0x807F0000 9 | #define KSEG0_BASE 0x80000000 10 | #define PTECODE_SIZE ((RAM1BASE - RAM0UBASE) / 0x1000 * 8) 11 | #define PTESTACK_SIZE ((RAM1KBASE - RAM1BASE) / 0x1000 * 8) 12 | 13 | #define PRAM0UBASE 0x00100000 14 | #define PRAM1BASE 0x00400000 15 | 16 | #define KSEG2PAGE0 0xC0000000 // kseg2中页表的第一页位置 17 | 18 | /* for EntryLo0-1 */ 19 | #define ELO_GLOBALB 0 20 | #define ELO_GLOBALF (_ULCAST_(1) << 0) 21 | #define ELO_VALIDB 1 22 | #define ELO_VALIDF (_ULCAST_(1) << 1) 23 | #define ELO_DIRTYB 2 24 | #define ELO_DIRTYF (_ULCAST_(1) << 2) 25 | 26 | #define SYSCALL_BASE 0x80 27 | 28 | /* syscall number */ 29 | #define SYS_exit 1 30 | #define SYS_fork 2 31 | #define SYS_wait 3 32 | #define SYS_exec 4 33 | #define SYS_clone 5 34 | #define SYS_yield 10 35 | #define SYS_sleep 11 36 | #define SYS_kill 12 37 | #define SYS_gettime 17 38 | #define SYS_getpid 18 39 | #define SYS_mmap 20 40 | #define SYS_munmap 21 41 | #define SYS_shmem 22 42 | #define SYS_putc 30 43 | #define SYS_pgdir 31 44 | #define SYS_open 100 45 | #define SYS_close 101 46 | #define SYS_read 102 47 | #define SYS_write 103 48 | #define SYS_seek 104 49 | #define SYS_fstat 110 50 | #define SYS_fsync 111 51 | #define SYS_getcwd 121 52 | #define SYS_getdirentry 128 53 | #define SYS_dup 130 54 | 55 | /* fetch program from serial bus */ 56 | #define SYS_fetchrun 241 // a prime number :) 57 | 58 | #define SYS_redraw_console 242 59 | 60 | /* OLNY FOR LAB6 */ 61 | #define SYS_lab6_set_priority 255 62 | 63 | /* SYS_fork flags */ 64 | #define CLONE_VM 0x00000100 // set if VM shared between processes 65 | #define CLONE_THREAD 0x00000200 // thread group 66 | #define CLONE_FS 0x00000800 // set if shared between processes 67 | 68 | /* VFS flags */ 69 | // flags for open: choose one of these 70 | #define O_RDONLY 0 // open for reading only 71 | #define O_WRONLY 1 // open for writing only 72 | #define O_RDWR 2 // open for reading and writing 73 | // then or in any of these: 74 | #define O_CREAT 0x00000004 // create file if it does not exist 75 | #define O_EXCL 0x00000008 // error if O_CREAT and the file exists 76 | #define O_TRUNC 0x00000010 // truncate file upon open 77 | #define O_APPEND 0x00000020 // append on each write 78 | // additonal related definition 79 | #define O_ACCMODE 3 // mask for O_RDONLY / O_WRONLY / O_RDWR 80 | 81 | #define NO_FD -0x9527 // invalid fd 82 | 83 | /* lseek codes */ 84 | #define LSEEK_SET 0 // seek relative to beginning of file 85 | #define LSEEK_CUR 1 // seek relative to current position in file 86 | #define LSEEK_END 2 // seek relative to end of file 87 | 88 | #define FS_MAX_DNAME_LEN 31 89 | #define FS_MAX_FNAME_LEN 255 90 | #define FS_MAX_FPATH_LEN 4095 91 | 92 | #define EXEC_MAX_ARG_NUM 32 93 | #define EXEC_MAX_ARG_LEN 4095 94 | 95 | #endif /* !__LIBS_UNISTD_H__ */ 96 | 97 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/kernel/kern/evec.S: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | 5 | .set noreorder 6 | .set noat 7 | .p2align 2 8 | .section .text.init 9 | .global INITLOCATE 10 | INITLOCATE: // 定位启动程序 11 | lui k0, %hi(START) 12 | addiu k0, %lo(START) 13 | jr k0 14 | nop 15 | 16 | .set reorder 17 | .set at 18 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/kernel/kern/init.S: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | .set noreorder 7 | .set noat 8 | 9 | .section .bss 10 | .p2align 2 11 | .global TCBT // thread control block table 12 | TCBT: 13 | .long 0 14 | .long 0 15 | .global current // current thread TCB address 16 | current: 17 | .long 0 18 | 19 | .text 20 | .p2align 2 21 | monitor_version: 22 | .asciz "MONITOR for MIPS32 - initialized." 23 | 24 | 25 | /* start address for the .bss section. defined in linker script */ 26 | .word _sbss 27 | /* end address for the .bss section. defined in linker script */ 28 | .word _ebss 29 | .global START 30 | START: // kernel init 31 | lui k0, %hi(_sbss) 32 | addiu k0, %lo(_sbss) 33 | lui k1, %hi(_ebss) 34 | addiu k1, %lo(_ebss) 35 | bss_init: 36 | beq k0, k1, bss_init_done 37 | nop 38 | sw zero, 0(k0) 39 | addiu k0, k0, 4 40 | b bss_init 41 | nop 42 | 43 | bss_init_done: 44 | 45 | lui sp, %hi(KERNEL_STACK_INIT) // 设置内核栈 46 | addiu sp, %lo(KERNEL_STACK_INIT) 47 | or fp, sp, zero 48 | lui t0, %hi(USER_STACK_INIT) // 设置用户栈 49 | addiu t0, %lo(USER_STACK_INIT) 50 | lui t1, %hi(uregs_sp) // 写入用户空间备份 51 | sw t0, %lo(uregs_sp)(t1) 52 | lui t1, %hi(uregs_fp) 53 | sw t0, %lo(uregs_fp)(t1) 54 | 55 | /* init serial */ 56 | #ifdef MACH_QEMU // QEMU模拟器特有的串口初始化过程 57 | /* see ucore/kern/driver/console.c */ 58 | lui t0, 0xBFD0 // NOTE: all COM_* share high 16 bits 59 | // 0xBFD0 should be %hi(COM1) but can not be used 60 | // due to a compiler bug (bugzilla/20649) 61 | sb zero, %lo(COM_FCR)(t0) // console.c:54 62 | ori t1, zero, %lo(COM_LCR_DLAB) 63 | sb t1, %lo(COM_LCR)(t0) // :57 64 | ori t1, zero, %lo(COM_DLL_VAL) 65 | sb t1, %lo(COM_DLL)(t0) // :58 66 | sb zero, %lo(COM_DLM)(t0) // :59 67 | ori t1, zero, %lo(COM_LCR_CONFIG) 68 | sb t1, %lo(COM_LCR)(t0) // :62 69 | sb zero, %lo(COM_MCR)(t0) // :65 70 | ori t1, zero, %lo(COM_IER_RDI) 71 | sb t1, %lo(COM_IER)(t0) // :67 72 | #endif 73 | 74 | ori t0, zero, TF_SIZE / 4 // 计数器 75 | .LC0: 76 | addiu t0, t0, -1 // 滚动计数器 77 | addiu sp, sp, -4 // 移动栈指针 78 | sw zero, 0(sp) // 初始化栈空间 79 | bne t0, zero, .LC0 // 初始化循环 80 | nop 81 | lui t0, %hi(TCBT) 82 | addiu t0, %lo(TCBT) // 载入TCBT地址 83 | sw sp, 0(t0) // thread0(idle)的中断帧地址设置 84 | or t6, sp, zero // t6保存idle中断帧位置 85 | 86 | ori t0, zero, TF_SIZE / 4 // 计数器 87 | .LC1: 88 | addiu t0, t0, -1 // 滚动计数器 89 | addiu sp, sp, -4 // 移动栈指针 90 | sw zero, 0(sp) // 初始化栈空间 91 | bne t0, zero, .LC1 // 初始化循环 92 | nop 93 | lui t0, %hi(TCBT) 94 | addiu t0, %lo(TCBT) // 载入TCBT地址 95 | sw sp, 4(t0) // thread1(shell/user)的中断帧地址设置 96 | sw sp, TF_sp(t6) // 设置idle线程栈指针(调试用?) 97 | 98 | lui t2, %hi(TCBT + 4) 99 | addiu t2, %lo(TCBT + 4) 100 | lw t2, 0(t2) // 取得thread1的TCB地址 101 | lui t1, %hi(current) 102 | sw t2, %lo(current)(t1) // 设置当前线程为thread1 103 | 104 | j WELCOME // 进入主线程 105 | nop 106 | 107 | 108 | 109 | WELCOME: 110 | lui s0, %hi(monitor_version) // 装入启动信息 111 | addiu s0, %lo(monitor_version) 112 | lb a0, 0(s0) 113 | .Loop0: 114 | addiu s0, s0, 0x1 115 | jal WRITESERIAL // 调用串口写函数 116 | nop 117 | lb a0, 0(s0) 118 | bne a0, zero, .Loop0 // 打印循环至0结束符 119 | nop 120 | j SHELL // 开始交互 121 | nop 122 | 123 | 124 | 125 | IDLELOOP: 126 | nop 127 | nop 128 | nop 129 | nop 130 | nop 131 | nop 132 | nop 133 | nop 134 | nop 135 | nop 136 | j IDLELOOP 137 | nop 138 | 139 | 140 | .set at 141 | .set reorder 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | // vim: syntax=asm 150 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/kernel/kern/kernel.ld: -------------------------------------------------------------------------------- 1 | ENTRY(INITLOCATE) 2 | OUTPUT("kernel.elf") 3 | OUTPUT_ARCH("mips:isa32r2") 4 | OUTPUT_FORMAT("elf32-tradlittlemips") 5 | 6 | PROVIDE(SerialData = 0xBFD003F8); 7 | PROVIDE(SerialStat = 0xBFD003FC); 8 | 9 | /* Qemu serial constants */ 10 | PROVIDE(COM1 = 0xBFD003F8); 11 | PROVIDE(COM_LSR = COM1 + 5); 12 | PROVIDE(COM_LSR_DATA = 0x01); 13 | PROVIDE(COM_FCR = COM1 + 2); 14 | PROVIDE(COM_LCR = COM1 + 3); 15 | PROVIDE(COM_LCR_DLAB = 0x80); 16 | PROVIDE(COM_DLL = COM1 + 0); 17 | PROVIDE(COM_DLL_VAL = 115200 / 9600); 18 | PROVIDE(COM_DLM = COM1 + 1); 19 | PROVIDE(COM_LCR_WLEN8 = 0x03); 20 | PROVIDE(COM_LCR_CONFIG = COM_LCR_WLEN8 & ~(COM_LCR_DLAB)); 21 | PROVIDE(COM_MCR = COM1 + 4); 22 | PROVIDE(COM_IER = COM1 + 1); 23 | PROVIDE(COM_IER_RDI = 0x01); 24 | 25 | PROVIDE(KERNEL_STACK_INIT = 0x80800000); 26 | PROVIDE(USER_STACK_INIT = 0x807F0000); 27 | SECTIONS 28 | { 29 | . = 0x807F0000; 30 | .bss : { 31 | _sbss = .; /* define a global symbol at bss start */ 32 | *(.bss.uregs) 33 | *(.bss) 34 | *(.bss.ptes) 35 | . = ALIGN(4); 36 | _ebss = .; /* define a global symbol at bss end */ 37 | } 38 | .rodata : { 39 | *(.rodata) 40 | } 41 | PROVIDE(uregs_sp = uregs + (29 - 1) * 4); 42 | PROVIDE(uregs_fp = uregs + (30 - 1) * 4); 43 | . = 0x80000000; 44 | .text : { 45 | *(.text.init) 46 | . = 0x1000; 47 | *(.text.ebase) 48 | . = 0x1180; 49 | *(.text.ebase180) 50 | . = ALIGN(0x1000); 51 | *(.text) 52 | . = ALIGN(0x1000); /* "fixed" utest address */ 53 | *(.text.utest) 54 | } 55 | } 56 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/kernel/kern/shell.S: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | .set noreorder 6 | .set noat 7 | 8 | .section .bss.uregs 9 | .p2align 2 10 | .global uregs 11 | uregs: 12 | .rept 32 // 第31个为用户程序入口地址临时保存 13 | .long 0 14 | .endr 15 | 16 | .text 17 | .p2align 2 18 | .global SHELL 19 | 20 | /* 21 | * SHELL: 监控程序交互模块 22 | * 23 | * 用户空间寄存器：$1-$30依次保存在0x807F0000连续120字节 24 | * 用户程序入口临时存储：0x807F0078 25 | */ 26 | SHELL: 27 | jal READSERIAL // 读操作符 28 | nop 29 | 30 | ori t0, zero, SH_OP_R 31 | beq v0, t0, .OP_R 32 | nop 33 | ori t0, zero, SH_OP_D 34 | beq v0, t0, .OP_D 35 | nop 36 | ori t0, zero, SH_OP_A 37 | beq v0, t0, .OP_A 38 | nop 39 | ori t0, zero, SH_OP_G 40 | beq v0, t0, .OP_G 41 | nop 42 | j .DONE // 错误的操作符，默认忽略 43 | nop 44 | 45 | 46 | .OP_R: // 操作 - 打印用户空间寄存器 47 | addiu sp, sp, -8 // 保存s0,s1 48 | sw s0, 0(sp) 49 | sw s1, 4(sp) 50 | 51 | lui s0, %hi(uregs) 52 | ori s1, zero, 120 // 计数器，打印120字节 53 | .LC0: 54 | lb a0, %lo(uregs)(s0) // 读取字节 55 | addiu s1, s1, -1 // 滚动计数器 56 | jal WRITESERIAL // 写入串口 57 | nop 58 | addiu s0, s0, 0x1 // 移动打印指针 59 | bne s1, zero, .LC0 // 打印循环 60 | nop 61 | 62 | lw s0, 0(sp) // 恢复s0,s1 63 | lw s1, 4(sp) 64 | addiu sp, sp, 8 65 | j .DONE 66 | nop 67 | 68 | .OP_D: // 操作 - 打印内存num字节 69 | addiu sp, sp, -8 // 保存s0,s1 70 | sw s0, 0(sp) 71 | sw s1, 4(sp) 72 | 73 | jal READSERIALWORD 74 | nop 75 | or s0, v0, zero // 获得addr 76 | jal READSERIALWORD 77 | nop 78 | or s1, v0, zero // 获得num 79 | 80 | .LC1: 81 | lb a0, 0(s0) // 读取字节 82 | addiu s1, s1, -1 // 滚动计数器 83 | jal WRITESERIAL // 写入串口 84 | nop 85 | addiu s0, s0, 0x1 // 移动打印指针 86 | bne s1, zero, .LC1 // 打印循环 87 | nop 88 | 89 | lw s0, 0(sp) // 恢复s0,s1 90 | lw s1, 4(sp) 91 | addiu sp, sp, 8 92 | j .DONE 93 | nop 94 | 95 | .OP_A: // 操作 - 写入内存num字节，num为4的倍数 96 | addiu sp, sp, -8 // 保存s0,s1 97 | sw s0, 0(sp) 98 | sw s1, 4(sp) 99 | 100 | jal READSERIALWORD 101 | nop 102 | or s0, v0, zero // 获得addr 103 | jal READSERIALWORD 104 | nop 105 | or s1, v0, zero // 获得num 106 | srl s1, s1, 2 // num除4，获得字数 107 | .LC2: // 每次写入一字 108 | jal READSERIALWORD // 从串口读入一字 109 | nop 110 | sw v0, 0(s0) // 写内存一字 111 | addiu s1, s1, -1 // 滚动计数器 112 | addiu s0, s0, 4 // 移动写指针 113 | bne s1, zero, .LC2 // 写循环 114 | nop 115 | 116 | lw s0, 0(sp) // 恢复s0,s1 117 | lw s1, 4(sp) 118 | addiu sp, sp, 8 119 | j .DONE 120 | nop 121 | 122 | .OP_G: 123 | jal READSERIALWORD // 获取addr 124 | nop 125 | 126 | ori a0, zero, TIMERSET // 写TIMERSET(0x06)信号 127 | jal WRITESERIAL // 告诉终端用户程序开始运行 128 | nop 129 | 130 | or k0, v0, zero 131 | 132 | lui ra, %hi(uregs) // 定位用户空间寄存器备份地址 133 | addiu ra, %lo(uregs) 134 | sw v0, PUTREG(31)(ra) // 保存用户程序入口 135 | sw sp, PUTREG(32)(ra) // 保存栈指针 136 | 137 | lw $1, PUTREG(1)(ra) // 装入$1-$30 138 | lw $2, PUTREG(2)(ra) 139 | lw $3, PUTREG(3)(ra) 140 | lw $4, PUTREG(4)(ra) 141 | lw $5, PUTREG(5)(ra) 142 | lw $6, PUTREG(6)(ra) 143 | lw $7, PUTREG(7)(ra) 144 | lw $8, PUTREG(8)(ra) 145 | lw $9, PUTREG(9)(ra) 146 | lw $10, PUTREG(10)(ra) 147 | lw $11, PUTREG(11)(ra) 148 | lw $12, PUTREG(12)(ra) 149 | lw $13, PUTREG(13)(ra) 150 | lw $14, PUTREG(14)(ra) 151 | lw $15, PUTREG(15)(ra) 152 | lw $16, PUTREG(16)(ra) 153 | lw $17, PUTREG(17)(ra) 154 | lw $18, PUTREG(18)(ra) 155 | lw $19, PUTREG(19)(ra) 156 | lw $20, PUTREG(20)(ra) 157 | lw $21, PUTREG(21)(ra) 158 | lw $22, PUTREG(22)(ra) 159 | lw $23, PUTREG(23)(ra) 160 | lw $24, PUTREG(24)(ra) 161 | lw $25, PUTREG(25)(ra) 162 | //lw $26, PUTREG(26)(ra) 163 | //lw $27, PUTREG(27)(ra) 164 | lw $28, PUTREG(28)(ra) 165 | lw $29, PUTREG(29)(ra) 166 | lw $30, PUTREG(30)(ra) 167 | 168 | lui ra, %hi(.USERRET2) // ra写入返回地址 169 | addiu ra, %lo(.USERRET2) 170 | nop 171 | jr k0 172 | nop 173 | .USERRET2: 174 | nop 175 | 176 | lui ra, %hi(uregs) // 定位用户空间寄存器备份地址 177 | addiu ra, %lo(uregs) 178 | 179 | sw $1, PUTREG(1)(ra) // 备份$1-$30 180 | sw $2, PUTREG(2)(ra) 181 | sw $3, PUTREG(3)(ra) 182 | sw $4, PUTREG(4)(ra) 183 | sw $5, PUTREG(5)(ra) 184 | sw $6, PUTREG(6)(ra) 185 | sw $7, PUTREG(7)(ra) 186 | sw $8, PUTREG(8)(ra) 187 | sw $9, PUTREG(9)(ra) 188 | sw $10, PUTREG(10)(ra) 189 | sw $11, PUTREG(11)(ra) 190 | sw $12, PUTREG(12)(ra) 191 | sw $13, PUTREG(13)(ra) 192 | sw $14, PUTREG(14)(ra) 193 | sw $15, PUTREG(15)(ra) 194 | sw $16, PUTREG(16)(ra) 195 | sw $17, PUTREG(17)(ra) 196 | sw $18, PUTREG(18)(ra) 197 | sw $19, PUTREG(19)(ra) 198 | sw $20, PUTREG(20)(ra) 199 | sw $21, PUTREG(21)(ra) 200 | sw $22, PUTREG(22)(ra) 201 | sw $23, PUTREG(23)(ra) 202 | sw $24, PUTREG(24)(ra) 203 | sw $25, PUTREG(25)(ra) 204 | //sw $26, PUTREG(26)(ra) 205 | //sw $27, PUTREG(27)(ra) 206 | sw $28, PUTREG(28)(ra) 207 | sw $29, PUTREG(29)(ra) 208 | sw $30, PUTREG(30)(ra) 209 | 210 | lw sp, PUTREG(32)(ra) 211 | ori a0, zero, TIMETOKEN // 发送TIMETOKEN(0x07)信号 212 | jal WRITESERIAL // 告诉终端用户程序结束运行 213 | nop 214 | 215 | j .DONE 216 | nop 217 | 218 | .DONE: 219 | j SHELL // 交互循环 220 | nop 221 | 222 | 223 | 224 | 225 | .set reorder 226 | .set at 227 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/kernel/kern/test.S: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | 7 | /*============================================================== 8 | * TEST for MONITOR 9 | * Built-in test program 10 | * Entry symbol prefix 'UTEST_' 11 | *==============================================================*/ 12 | 13 | 14 | .set noreorder 15 | .set noat 16 | .section .text.utest 17 | .p2align 2 18 | 19 | /* Simple test program 20 | * Write integer 1 to register v0 21 | */ 22 | UTEST_SIMPLE: 23 | addiu v0, v0, 0x1 24 | jr ra 25 | nop 26 | /* End of test */ 27 | 28 | /* STREAM test program 29 | * Continous memory read/write 30 | */ 31 | UTEST_STREAM: 32 | li a0, 0x80100000 33 | li a1, 0x80400000 34 | li a2, 0x00300000 35 | addu a2,a0,a2 36 | stream_next: 37 | beq a0,a2,stream_end 38 | addiu a1,a1,4 39 | 40 | lw v0,0(a0) 41 | sw v0,-4(a1) 42 | beq $0,$0,stream_next 43 | addiu a0,a0,4 44 | 45 | stream_end: 46 | jr ra 47 | nop 48 | /* End of test */ 49 | 50 | /* MATRIX test program 51 | * Matrix multiplication 52 | * Reference C code: 53 | void matrix(int a[128][128],int b[128][128],int c[128][128],unsigned int n) { 54 | unsigned int i,j,k; 55 | for (k=0; k!=n; k++) { 56 | for (i=0; i!=n; i++) { 57 | int r = a[i][k]; 58 | for (j=0; j!=n; j++) 59 | c[i][j] += r * b[k][j]; 60 | } 61 | } 62 | } 63 | */ 64 | UTEST_MATRIX: 65 | // set arguments 66 | li a0, 0x80400000 67 | li a1, 0x80410000 68 | li a2, 0x80420000 69 | li a3, 96 70 | // a0 -> a 71 | // a1 -> b 72 | // a2 -> c 73 | // a3 -> n 74 | // v1 -> k 75 | // t1 -> i 76 | // t3 -> j 77 | // t7 -> r 78 | or v1,$0,$0 79 | loop1: 80 | beq v1,a3,loop1end 81 | sll t0,v1,2 82 | 83 | sll t2,v1,9 84 | addu t0,a0,t0 85 | addu t2,a1,t2 86 | or t1,$0,$0 87 | loop2: 88 | beq t1,a3,loop2end 89 | sll v0,t1,9 90 | 91 | lw t7,0(t0) 92 | addu v0,a2,v0 93 | or t4,t2,$0 94 | or t3,$0,$0 95 | loop3: 96 | beq t3,a3,loop3end 97 | addiu t3,t3,1 98 | 99 | lw t5,0(t4) 100 | lw t6,0(v0) 101 | mul t5,t7,t5 102 | addiu v0,v0,4 103 | addiu t4,t4,4 104 | addu t5,t6,t5 105 | beq $0,$0,loop3 106 | sw t5,-4(v0) 107 | 108 | loop3end: 109 | addiu t1,t1,1 110 | beq $0,$0,loop2 111 | addiu t0,t0,512 112 | 113 | loop2end: 114 | beq $0,$0,loop1 115 | addiu v1,v1,1 116 | 117 | loop1end: 118 | jr ra 119 | nop 120 | /* End of test */ 121 | 122 | /* CryptoNight test program 123 | * Run simplified CryptoNight memory-hard loop 124 | * Reference C code: 125 | void crn(int pad[],unsigned int a,unsigned int b,unsigned int n) { 126 | unsigned int k; 127 | for (k=0; k!=0x80000; k++) 128 | pad[k] = k; 129 | for (k=0; k!=n; k++) { 130 | unsigned int t, addr1, addr2; 131 | addr1 = a & 0x7FFFF; 132 | t = (a >> 1) ^ (pad[addr1] << 1); // Replace the AES step 133 | pad[addr1] = t ^ b; 134 | addr2 = t & 0x7FFFF; 135 | b = t; 136 | t = pad[addr2]; 137 | a += b * t; 138 | pad[addr2] = a; 139 | a ^= t; 140 | } 141 | } 142 | */ 143 | UTEST_CRYPTONIGHT: 144 | // a0 -> pad 145 | // a1 -> a 146 | // a2 -> b 147 | // a3 -> n 148 | li a0, 0x80400000 149 | li a1, 0xdeadbeef 150 | li a2, 0xfaceb00c 151 | li a3, 0x100000 152 | or v1,$0,a0 153 | or v0,$0,$0 154 | li t0,0x80000 155 | fill_next: 156 | sw v0,0(v1) 157 | addiu v0,v0,1 158 | bne v0,t0,fill_next 159 | addiu v1,v1,4 160 | 161 | or t1,$0,$0 162 | li t2,0x7ffff 163 | crn_hext: 164 | and t0,a1,t2 165 | sll t0,t0,2 166 | addu t0,a0,t0 167 | lw v0,0(t0) 168 | srl v1,a1,1 169 | sll v0,v0,1 170 | xor v0,v0,v1 171 | and v1,v0,t2 172 | xor a2,v0,a2 173 | sll v1,v1,2 174 | sw a2,0(t0) 175 | addu v1,a0,v1 176 | lw t0,0(v1) 177 | or a2,$0,v0 178 | mul v0,v0,t0 179 | addiu t1,t1,1 180 | addu a1,v0,a1 181 | sw a1,0(v1) 182 | bne a3,t1,crn_hext 183 | xor a1,t0,a1 184 | crn_end: 185 | jr ra 186 | nop 187 | /* End of test */ 188 | 189 | 190 | 191 | #define TESTLOOP64 0x04000000 /* 64M约6.7千万次 */ 192 | #define TESTLOOP32 0x02000000 /* 32M约3.4千万次 */ 193 | #define TESTLOOP16 0x01000000 /* 16M约1.7千万次 */ 194 | 195 | /* 性能标定程序(1) 196 | * 这段程序一般没有数据冲突和结构冲突，可作为性能标定。 197 | * 若执行延迟槽，执行这段程序需至少384M指令，384M/time可算得频率。 198 | * 不执行延迟槽，执行这段程序需至少320M指令，320M/time可算得频率。 199 | */ 200 | UTEST_1PTB: 201 | lui t0, %hi(TESTLOOP64) // 装入64M 202 | nop 203 | nop 204 | nop 205 | .LC0: 206 | addiu t0, t0, -1 // 滚动计数器 207 | ori t1, zero, 0 208 | ori t2, zero, 1 209 | ori t3, zero, 2 210 | bne t0, zero, .LC0 211 | nop 212 | nop 213 | jr ra 214 | nop 215 | 216 | 217 | /* 运算数据冲突的效率测试(2) 218 | * 这段程序含有大量数据冲突，可测试数据冲突对效率的影响。 219 | * 执行延迟槽，执行这段程序需至少192M指令。 220 | * 不执行延迟槽，执行这段程序需至少176M指令。 221 | */ 222 | UTEST_2DCT: 223 | lui t0, %hi(TESTLOOP16) // 装入16M 224 | ori t1, zero, 1 225 | ori t2, zero, 2 226 | ori t3, zero, 3 227 | .LC1: 228 | xor t2, t2, t1 // 交换t1,t2 229 | xor t1, t1, t2 230 | xor t2, t2, t1 231 | xor t3, t3, t2 // 交换t2,t3 232 | xor t2, t2, t3 233 | xor t3, t3, t2 234 | xor t1, t1, t3 // 交换t3,t1 235 | xor t3, t3, t1 236 | xor t1, t1, t3 237 | addiu t0, t0, -1 238 | bne t0, zero, .LC1 239 | nop 240 | jr ra 241 | nop 242 | 243 | 244 | /* 控制指令冲突测试(3) 245 | * 这段程序有大量控制冲突。 246 | * 无延迟槽执行需要至少256M指令； 247 | * 有延迟槽需要224M指令。 248 | */ 249 | UTEST_3CCT: 250 | lui t0, %hi(TESTLOOP64) // 装入64M 251 | .LC2_0: 252 | bne t0, zero, .LC2_1 253 | nop 254 | jr ra 255 | nop 256 | .LC2_1: 257 | j .LC2_2 258 | nop 259 | .LC2_2: 260 | addiu t0, t0, -1 261 | j .LC2_0 262 | addiu t0, t0, -1 263 | nop 264 | 265 | 266 | /* 访存相关数据冲突测试(4) 267 | * 这段程序反复对内存进行有数据冲突的读写。 268 | * 不执行延迟槽需要至少192M指令。 269 | * 执行延迟槽，需要至少224M指令。 270 | */ 271 | UTEST_4MDCT: 272 | lui t0, %hi(TESTLOOP32) // 装入32M 273 | addiu sp, sp, -4 274 | .LC3: 275 | sw t0, 0(sp) 276 | lw t1, 0(sp) 277 | addiu t1, t1, -1 278 | sw t1, 0(sp) 279 | lw t0, 0(sp) 280 | bne t0, zero, .LC3 281 | nop 282 | addiu sp, sp, 4 283 | jr ra 284 | nop 285 | 286 | 287 | // 测试程序扩展 288 | 289 | 290 | 291 | .set reorder 292 | .set at 293 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/kernel/kern/utils.S: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | .set noreorder 6 | .set noat 7 | .p2align 2 8 | .text 9 | .global WRITESERIAL 10 | .global READSERIAL 11 | .global READSERIALWORD 12 | 13 | WRITESERIAL: // 写串口：将a0的低八位写入串口 14 | #ifdef MACH_FPGA 15 | lui t1, %hi(SerialStat) 16 | .TESTW: 17 | lb t0, %lo(SerialStat)(t1) // 查看串口状态 18 | andi t0, t0, 0x0001 // 截取写状态位 19 | bne t0, zero, .WSERIAL // 状态位非零可写进入写 20 | nop 21 | j .TESTW // 检测验证，忙等待 22 | nop 23 | .WSERIAL: 24 | lui t1, %hi(SerialData) 25 | sb a0, %lo(SerialData)(t1) // 写入 26 | jr ra 27 | nop 28 | #else // QEMU模拟器上的写串口操作 29 | lui t1, %hi(COM1) 30 | sb a0, %lo(COM1)(t1) 31 | jr ra 32 | nop 33 | #endif 34 | 35 | READSERIAL: // 读串口：将读到的数据写入v0低八位 36 | #ifdef MACH_FPGA 37 | lui t1, %hi(SerialStat) 38 | .TESTR: 39 | lb t0, %lo(SerialStat)(t1) // 查看串口状态 40 | andi t0, t0, 0x0002 // 截取读状态位 41 | bne t0, zero, .RSERIAL // 状态位非零可读进入读 42 | nop 43 | j .TESTR // 检测验证 44 | nop 45 | .RSERIAL: 46 | lui t1, %hi(SerialData) 47 | lb v0, %lo(SerialData)(t1) // 读出 48 | jr ra 49 | nop 50 | #else //ifdef MACH_FPGA // QEMU模拟器上的读串口操作 51 | lui t1, %hi(COM1) 52 | .TESTR: 53 | lb t0, %lo(COM_LSR)(t1) 54 | andi t0, t0, COM_LSR_DATA 55 | bne t0, zero, .RSERIAL 56 | nop 57 | j .TESTR 58 | nop 59 | .RSERIAL: 60 | lui t1, %hi(COM1) 61 | lb v0, %lo(COM1)(t1) 62 | jr ra 63 | nop 64 | #endif //ifdef MACH_FPGA 65 | 66 | READSERIALWORD: 67 | addiu sp, sp, -0x14 // 保存ra,s0 68 | sw ra, 0x0(sp) 69 | sw s0, 0x4(sp) 70 | sw s1, 0x8(sp) 71 | sw s2, 0xC(sp) 72 | sw s3, 0x10(sp) 73 | 74 | jal READSERIAL // 读串口获得八个比特 75 | nop 76 | or s0, zero, v0 // 结果存入s0 77 | jal READSERIAL // 读串口获得八个比特 78 | nop 79 | or s1, zero, v0 // 结果存入s1 80 | jal READSERIAL // 读串口获得八个比特 81 | nop 82 | or s2, zero, v0 // 结果存入s2 83 | jal READSERIAL // 读串口获得八个比特 84 | nop 85 | or s3, zero, v0 // 结果存入s3 86 | 87 | andi s0, s0, 0x00FF // 截取低八位 88 | andi s3, s3, 0x00FF 89 | andi s2, s2, 0x00FF 90 | andi s1, s1, 0x00FF 91 | or v0, zero, s3 // 存高八位 92 | sll v0, v0, 8 // 左移 93 | or v0, v0, s2 // 存八位 94 | sll v0, v0, 8 // 左移 95 | or v0, v0, s1 // 存八位 96 | sll v0, v0, 8 // 左移 97 | or v0, v0, s0 // 存低八位 98 | 99 | lw ra, 0x0(sp) // 恢复ra,s0 100 | lw s0, 0x4(sp) 101 | lw s1, 0x8(sp) 102 | lw s2, 0xC(sp) 103 | lw s3, 0x10(sp) 104 | addiu sp, sp, 0x14 105 | jr ra 106 | nop 107 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/term/.gitignore: -------------------------------------------------------------------------------- 1 | t.in 2 | t.out 3 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/term/term.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # -*- encoding=utf-8 -*- 3 | 4 | import argparse 5 | import math 6 | import os 7 | import platform 8 | import re 9 | import select 10 | import socket 11 | import string 12 | import struct 13 | import subprocess 14 | import sys 15 | import tempfile 16 | from timeit import default_timer as timer 17 | 18 | try: 19 | import readline 20 | except: 21 | pass 22 | try: type(raw_input) 23 | except NameError: raw_input = input 24 | 25 | CCPREFIX = "mips-mti-elf-" 26 | if 'GCCPREFIX' in os.environ: 27 | CCPREFIX=os.environ['GCCPREFIX'] 28 | CMD_ASSEMBLER = CCPREFIX + 'as' 29 | CMD_DISASSEMBLER = CCPREFIX + 'objdump' 30 | CMD_BINARY_COPY = CCPREFIX + 'objcopy' 31 | 32 | Reg_alias = ['zero', 'AT', 'v0', 'v1', 'a0', 'a1', 'a2', 'a3', 't0', 't1', 't2', 't3', 't4', 't5', 't6', 't7', 's0', 33 | 's1', 's2', 's3', 's4', 's5', 's6', 's7', 't8', 't9/jp', 'k0', 'k1', 'gp', 'sp', 'fp/s8', 'ra'] 34 | 35 | def test_programs(): 36 | tmp = tempfile.NamedTemporaryFile() 37 | for prog in [CMD_ASSEMBLER, CMD_DISASSEMBLER, CMD_BINARY_COPY]: 38 | try: 39 | subprocess.check_call([prog, '--version'], stdout=tmp) 40 | except: 41 | print("Couldn't run", prog) 42 | print("Please check your PATH env", os.environ["PATH"].split(os.pathsep)) 43 | tmp.close() 44 | return False 45 | tmp.close() 46 | return True 47 | 48 | def output_binary(binary): 49 | if hasattr(sys.stdout,'buffer'): # Python 3 50 | sys.stdout.buffer.write(binary) 51 | else: 52 | sys.stdout.write(binary) 53 | 54 | # convert 32-bit int to byte string of length 4, from LSB to MSB 55 | def int_to_byte_string(val): 56 | return struct.pack('8x}'.format( 171 | str(i).ljust(2), 172 | '(' + Reg_alias[i] + ')', 173 | val, 174 | )) 175 | 176 | 177 | def run_D(addr, num): 178 | if num % 4 != 0: 179 | print("num % 4 should be zero") 180 | return 181 | outp.write(b'D') 182 | outp.write(int_to_byte_string(addr)) 183 | outp.write(int_to_byte_string(num)) 184 | counter = 0 185 | while counter < num: 186 | val_raw = inp.read(4) 187 | counter = counter + 4 188 | val = byte_string_to_int(val_raw) 189 | print('0x%08x: 0x%08x' % (addr,val)) 190 | addr = addr + 4 191 | 192 | 193 | def run_U(addr, num): 194 | if num % 4 != 0: 195 | print("num % 4 should be zero") 196 | return 197 | outp.write(b'D') 198 | outp.write(int_to_byte_string(addr)) 199 | outp.write(int_to_byte_string(num)) 200 | counter = 0 201 | while counter < num: 202 | val_raw = inp.read(4) 203 | print('0x%08x: %s' % (addr,single_line_disassmble(val_raw, addr))) 204 | counter = counter + 4 205 | addr = addr + 4 206 | 207 | def run_G(addr): 208 | outp.write(b'G') 209 | outp.write(int_to_byte_string(addr)) 210 | class TrapError(Exception): 211 | pass 212 | try: 213 | ret = inp.read(1) 214 | if ret == b'\x80': 215 | raise TrapError() 216 | if ret != b'\x06': 217 | print("start mark should be 0x06") 218 | time_start = timer() 219 | while True: 220 | ret = inp.read(1) 221 | if ret == b'\x07': 222 | break 223 | elif ret == b'\x80': 224 | raise TrapError() 225 | output_binary(ret) 226 | print('') #just a new line 227 | elapse = timer() - time_start 228 | print('elapsed time: %.3fs' % (elapse)) 229 | except TrapError: 230 | print('supervisor reported an exception during execution') 231 | 232 | 233 | def MainLoop(): 234 | while True: 235 | try: 236 | cmd = raw_input('>> ').strip().upper() 237 | except EOFError: 238 | print('') 239 | break 240 | EmptyBuf() 241 | try: 242 | if cmd == 'Q': 243 | break 244 | elif cmd == 'A': 245 | addr = raw_input('>>addr: 0x') 246 | run_A(int(addr, 16)) 247 | elif cmd == 'F': 248 | file_name = raw_input('>>file name: ') 249 | addr = raw_input('>>addr: 0x') 250 | run_F(int(addr, 16), file_name) 251 | elif cmd == 'R': 252 | run_R() 253 | elif cmd == 'D': 254 | addr = raw_input('>>addr: 0x') 255 | num = raw_input('>>num: ') 256 | run_D(int(addr, 16), int(num)) 257 | elif cmd == 'U': 258 | addr = raw_input('>>addr: 0x') 259 | num = raw_input('>>num: ') 260 | run_U(int(addr, 16), int(num)) 261 | elif cmd == 'G': 262 | addr = raw_input('>>addr: 0x') 263 | run_G(int(addr, 16)) 264 | else: 265 | print("Invalid command") 266 | except ValueError as e: 267 | print(e) 268 | 269 | def InitializeSerial(pipe_path, baudrate): 270 | try: 271 | import serial 272 | except: 273 | print("Please install pyserial") 274 | exit(1) 275 | global outp, inp 276 | tty = serial.Serial(port=pipe_path, baudrate=baudrate) 277 | tty.reset_input_buffer() 278 | inp = tty 279 | outp = tty 280 | return True 281 | 282 | def Main(welcome_message=True): 283 | #debug 284 | # welcome_message = False 285 | if welcome_message: 286 | output_binary(inp.read(33)) 287 | print('') 288 | MainLoop() 289 | 290 | class tcp_wrapper: 291 | 292 | def __init__(self, sock=None): 293 | if sock is None: 294 | self.sock = socket.socket( 295 | socket.AF_INET, socket.SOCK_STREAM) 296 | else: 297 | self.sock = sock 298 | 299 | def connect(self, host, port): 300 | self.sock.connect((host, port)) 301 | 302 | def write(self, msg): 303 | totalsent = 0 304 | MSGLEN = len(msg) 305 | while totalsent < MSGLEN: 306 | sent = self.sock.send(msg[totalsent:]) 307 | if sent == 0: 308 | raise RuntimeError("socket connection broken") 309 | totalsent = totalsent + sent 310 | 311 | def flush(self): # dummy 312 | pass 313 | 314 | def read(self, MSGLEN): 315 | chunks = [] 316 | bytes_recd = 0 317 | while bytes_recd < MSGLEN: 318 | chunk = self.sock.recv(min(MSGLEN - bytes_recd, 2048)) 319 | # print 'read:...', list(map(lambda c: hex(ord(c)), chunk)) 320 | if chunk == b'': 321 | raise RuntimeError("socket connection broken") 322 | chunks.append(chunk) 323 | bytes_recd = bytes_recd + len(chunk) 324 | return b''.join(chunks) 325 | 326 | def reset_input_buffer(self): 327 | local_input = [self.sock] 328 | while True: 329 | inputReady, o, e = select.select(local_input, [], [], 0.0) 330 | if len(inputReady) == 0: 331 | break 332 | for s in inputReady: 333 | s.recv(1) 334 | 335 | def EmptyBuf(): 336 | inp.reset_input_buffer() 337 | 338 | def InitializeTCP(host_port): 339 | 340 | ValidIpAddressRegex = re.compile("^((([0-9]|[1-9][0-9]|1[0-9]{2}|2[0-4][0-9]|25[0-5])\.){3}([0-9]|[1-9][0-9]|1[0-9]{2}|2[0-4][0-9]|25[0-5])):(\d+)$"); 341 | ValidHostnameRegex = re.compile("^((([a-zA-Z0-9]|[a-zA-Z0-9][a-zA-Z0-9\-]*[a-zA-Z0-9])\.)*([A-Za-z0-9]|[A-Za-z0-9][A-Za-z0-9\-]*[A-Za-z0-9])):(\d+)$"); 342 | 343 | if ValidIpAddressRegex.search(host_port) is None and \ 344 | ValidHostnameRegex.search(host_port) is None: 345 | return False 346 | 347 | match = ValidIpAddressRegex.search(host_port) or ValidHostnameRegex.search(host_port) 348 | groups = match.groups() 349 | ser = tcp_wrapper() 350 | host, port = groups[0], groups[4] 351 | sys.stdout.write("connecting to %s:%s..." % (host, port)) 352 | sys.stdout.flush() 353 | ser.connect(host, int(port)) 354 | print("connected") 355 | 356 | global outp, inp 357 | outp = ser 358 | inp = ser 359 | return True 360 | 361 | if __name__ == "__main__": 362 | # para = '127.0.0.1:6666' if len(sys.argv) != 2 else sys.argv[1] 363 | 364 | parser = argparse.ArgumentParser(description = 'Term for mips32 expirence.') 365 | parser.add_argument('-c', '--continued', action='store_true', help='Term will not wait for welcome if this flag is set') 366 | parser.add_argument('-t', '--tcp', default=None, help='TCP server address:port for communication') 367 | parser.add_argument('-s', '--serial', default=None, help='Serial port name (e.g. /dev/ttyACM0, COM3)') 368 | parser.add_argument('-b', '--baud', default=9600, help='Serial port baudrate (9600 by default)') 369 | args = parser.parse_args() 370 | 371 | if args.tcp: 372 | if not InitializeTCP(args.tcp): 373 | print('Failed to establish TCP connection') 374 | exit(1) 375 | elif args.serial: 376 | if not InitializeSerial(args.serial, args.baud): 377 | print('Failed to open serial port') 378 | exit(1) 379 | else: 380 | parser.print_help() 381 | exit(1) 382 | if not test_programs(): 383 | exit(1) 384 | Main(not args.continued) 385 | 386 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sim_1/tmp/supervisor_v2.01/utility/gen_matrix.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # -*- encoding=utf-8 -*- 3 | import numpy as np 4 | 5 | # addr = 0x80400000 6 | # length = 128*128*4 7 | n = 96 8 | z = np.zeros((128,128), dtype=np.int32) 9 | a = z.copy() 10 | a[:n, :n] = np.random.randint(-1000, 1000, size=(n,n)) 11 | b = z.copy() 12 | b[:n, :n] = np.random.randint(-1000, 1000, size=(n,n)) 13 | c = a @ b 14 | print(a) 15 | print(b) 16 | print(c) 17 | 18 | def printHex(f, i): 19 | if i < 0: 20 | i += 0x100000000 21 | f.write(f"{i:08x}\n") 22 | 23 | with open("matrix.in", "w") as f: 24 | # addr += 16 25 | # printHex(f, addr) # address of a 26 | # printHex(f, addr+length) # address of b 27 | # printHex(f, addr+length*2) # address of c 28 | # printHex(f, n) 29 | # value of a 30 | for row in a: 31 | for col in row: 32 | printHex(f, col) 33 | # value of b 34 | for row in b: 35 | for col in row: 36 | printHex(f, col) 37 | # initial value of c (all zeros) 38 | for row in z: 39 | for col in row: 40 | printHex(f, col) 41 | with open("matrix.out", "w") as f: 42 | # value of c 43 | for row in c: 44 | for col in row: 45 | printHex(f, col) 46 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/ip/pll_example/doc/clk_wiz_v6_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2019.2: 2 | * Version 6.0 (Rev. 4) 3 | * Bug Fix: Internal GUI fixes 4 | * Other: CR Fixes 5 | 6 | 2019.1.3: 7 | * Version 6.0 (Rev. 3) 8 | * No changes 9 | 10 | 2019.1.2: 11 | * Version 6.0 (Rev. 3) 12 | * No changes 13 | 14 | 2019.1.1: 15 | * Version 6.0 (Rev. 3) 16 | * No changes 17 | 18 | 2019.1: 19 | * Version 6.0 (Rev. 3) 20 | * Bug Fix: Internal GUI fixes 21 | * Other: New family support added 22 | 23 | 2018.3.1: 24 | * Version 6.0 (Rev. 2) 25 | * No changes 26 | 27 | 2018.3: 28 | * Version 6.0 (Rev. 2) 29 | * Bug Fix: Made input source independent for primary and secondary clock 30 | * Other: New family support added 31 | 32 | 2018.2: 33 | * Version 6.0 (Rev. 1) 34 | * Bug Fix: Removed vco freq check when Primitive is None 35 | * Other: New family support added 36 | 37 | 2018.1: 38 | * Version 6.0 39 | * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature 40 | * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI 41 | * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals. 42 | * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support 43 | * Other: DRCs added for invalid input values in Override mode 44 | 45 | 2017.4: 46 | * Version 5.4 (Rev. 3) 47 | * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL 48 | * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 49 | 50 | 2017.3: 51 | * Version 5.4 (Rev. 2) 52 | * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices 53 | 54 | 2017.2: 55 | * Version 5.4 (Rev. 1) 56 | * General: Internal GUI changes. No effect on the customer design. 57 | 58 | 2017.1: 59 | * Version 5.4 60 | * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices. 61 | * Other: Added support for new zynq ultrascale plus devices. 62 | 63 | 2016.4: 64 | * Version 5.3 (Rev. 3) 65 | * Bug Fix: Internal GUI issues are fixed. 66 | 67 | 2016.3: 68 | * Version 5.3 (Rev. 2) 69 | * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs. 70 | * Feature Enhancement: Added Matched Routing Option for better timing solutions. 71 | * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list. 72 | * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user 73 | * Other: Added support for Spartan7 devices. 74 | 75 | 2016.2: 76 | * Version 5.3 (Rev. 1) 77 | * Internal register bit update, no effect on customer designs. 78 | 79 | 2016.1: 80 | * Version 5.3 81 | * Added Clock Monitor Feature as part of clocking wizard 82 | * DRP registers can be directly written through AXI without resource utilization 83 | * Changes to HDL library management to support Vivado IP simulation library 84 | 85 | 2015.4.2: 86 | * Version 5.2 (Rev. 1) 87 | * No changes 88 | 89 | 2015.4.1: 90 | * Version 5.2 (Rev. 1) 91 | * No changes 92 | 93 | 2015.4: 94 | * Version 5.2 (Rev. 1) 95 | * Internal device family change, no functional changes 96 | 97 | 2015.3: 98 | * Version 5.2 99 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 100 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 101 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 102 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 103 | * Example design and simulation files are delivered in verilog only 104 | 105 | 2015.2.1: 106 | * Version 5.1 (Rev. 6) 107 | * No changes 108 | 109 | 2015.2: 110 | * Version 5.1 (Rev. 6) 111 | * No changes 112 | 113 | 2015.1: 114 | * Version 5.1 (Rev. 6) 115 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 116 | * Supported devices and production status are now determined automatically, to simplify support for future devices 117 | 118 | 2014.4.1: 119 | * Version 5.1 (Rev. 5) 120 | * No changes 121 | 122 | 2014.4: 123 | * Version 5.1 (Rev. 5) 124 | * Internal device family change, no functional changes 125 | * updates related to the source selection based on board interface for zed board 126 | 127 | 2014.3: 128 | * Version 5.1 (Rev. 4) 129 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 130 | 131 | 2014.2: 132 | * Version 5.1 (Rev. 3) 133 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 134 | 135 | 2014.1: 136 | * Version 5.1 (Rev. 2) 137 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 138 | * Internal device family name change, no functional changes 139 | 140 | 2013.4: 141 | * Version 5.1 (Rev. 1) 142 | * Added support for Ultrascale devices 143 | * Updated Board Flow GUI to select the clock interfaces 144 | * Fixed issue with Stub file parameter error for BUFR output driver 145 | 146 | 2013.3: 147 | * Version 5.1 148 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 149 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 150 | * Fixed precision issues between displayed and actual frequencies 151 | * Added tool tips to GUI 152 | * Added Jitter and Phase error values to IP properties 153 | * Added support for Cadence IES and Synopsys VCS simulators 154 | * Reduced warnings in synthesis and simulation 155 | * Enhanced support for IP Integrator 156 | 157 | 2013.2: 158 | * Version 5.0 (Rev. 1) 159 | * Fixed issue with clock constraints for multiple instances of clocking wizard 160 | * Updated Life-Cycle status of devices 161 | 162 | 2013.1: 163 | * Version 5.0 164 | * Lower case ports for Verilog 165 | * Added Safe Clock Startup and Clock Sequencing 166 | 167 | (c) Copyright 2008 - 2019 Xilinx, Inc. All rights reserved. 168 | 169 | This file contains confidential and proprietary information 170 | of Xilinx, Inc. and is protected under U.S. and 171 | international copyright and other intellectual property 172 | laws. 173 | 174 | DISCLAIMER 175 | This disclaimer is not a license and does not grant any 176 | rights to the materials distributed herewith. Except as 177 | otherwise provided in a valid license issued to you by 178 | Xilinx, and to the maximum extent permitted by applicable 179 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 180 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 181 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 182 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 183 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 184 | (2) Xilinx shall not be liable (whether in contract or tort, 185 | including negligence, or under any other theory of 186 | liability) for any loss or damage of any kind or nature 187 | related to, arising under or in connection with these 188 | materials, including for any direct, or any indirect, 189 | special, incidental, or consequential loss or damage 190 | (including loss of data, profits, goodwill, or any type of 191 | loss or damage suffered as a result of any action brought 192 | by a third party) even if such damage or loss was 193 | reasonably foreseeable or Xilinx had been advised of the 194 | possibility of the same. 195 | 196 | CRITICAL APPLICATIONS 197 | Xilinx products are not designed or intended to be fail- 198 | safe, or for use in any application requiring fail-safe 199 | performance, such as life-support or safety devices or 200 | systems, Class III medical devices, nuclear facilities, 201 | applications related to the deployment of airbags, or any 202 | other applications that could lead to death, personal 203 | injury, or severe property or environmental damage 204 | (individually and collectively, "Critical 205 | Applications"). Customer assumes the sole risk and 206 | liability of any use of Xilinx products in Critical 207 | Applications, subject only to applicable laws and 208 | regulations governing limitations on product liability. 209 | 210 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 211 | PART OF THIS FILE AT ALL TIMES. 212 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.v: -------------------------------------------------------------------------------- 1 | 2 | // file: pll_example.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1__107.50000______0.000______50.0______202.759____231.057 60 | // clk_out2__89.58333______0.000______50.0______208.075____231.057 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary______________50____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | (* CORE_GENERATION_INFO = "pll_example,clk_wiz_v6_0_4_0_0,{component_name=pll_example,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=20.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 70 | 71 | module pll_example 72 | ( 73 | // Clock out ports 74 | output clk_out1, 75 | output clk_out2, 76 | // Status and control signals 77 | input reset, 78 | output locked, 79 | // Clock in ports 80 | input clk_in1 81 | ); 82 | 83 | pll_example_clk_wiz inst 84 | ( 85 | // Clock out ports 86 | .clk_out1(clk_out1), 87 | .clk_out2(clk_out2), 88 | // Status and control signals 89 | .reset(reset), 90 | .locked(locked), 91 | // Clock in ports 92 | .clk_in1(clk_in1) 93 | ); 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: pll_example.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 20.000 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.2 58 | 59 | 60 | set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] 61 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/ip/pll_example/pll_example_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/ip/pll_example/pll_example_clk_wiz.v: -------------------------------------------------------------------------------- 1 | 2 | // file: pll_example.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1__107.50000______0.000______50.0______202.759____231.057 60 | // clk_out2__89.58333______0.000______50.0______208.075____231.057 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary______________50____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | module pll_example_clk_wiz 70 | 71 | (// Clock in ports 72 | // Clock out ports 73 | output clk_out1, 74 | output clk_out2, 75 | // Status and control signals 76 | input reset, 77 | output locked, 78 | input clk_in1 79 | ); 80 | // Input buffering 81 | //------------------------------------ 82 | wire clk_in1_pll_example; 83 | wire clk_in2_pll_example; 84 | IBUF clkin1_ibufg 85 | (.O (clk_in1_pll_example), 86 | .I (clk_in1)); 87 | 88 | 89 | 90 | 91 | // Clocking PRIMITIVE 92 | //------------------------------------ 93 | 94 | // Instantiation of the MMCM PRIMITIVE 95 | // * Unused inputs are tied off 96 | // * Unused outputs are labeled unused 97 | 98 | wire clk_out1_pll_example; 99 | wire clk_out2_pll_example; 100 | wire clk_out3_pll_example; 101 | wire clk_out4_pll_example; 102 | wire clk_out5_pll_example; 103 | wire clk_out6_pll_example; 104 | wire clk_out7_pll_example; 105 | 106 | wire [15:0] do_unused; 107 | wire drdy_unused; 108 | wire psdone_unused; 109 | wire locked_int; 110 | wire clkfbout_pll_example; 111 | wire clkfbout_buf_pll_example; 112 | wire clkfboutb_unused; 113 | wire clkout2_unused; 114 | wire clkout3_unused; 115 | wire clkout4_unused; 116 | wire clkout5_unused; 117 | wire clkout6_unused; 118 | wire clkfbstopped_unused; 119 | wire clkinstopped_unused; 120 | wire reset_high; 121 | 122 | PLLE2_ADV 123 | #(.BANDWIDTH ("OPTIMIZED"), 124 | .COMPENSATION ("ZHOLD"), 125 | .STARTUP_WAIT ("FALSE"), 126 | .DIVCLK_DIVIDE (2), 127 | .CLKFBOUT_MULT (43), 128 | .CLKFBOUT_PHASE (0.000), 129 | .CLKOUT0_DIVIDE (10), 130 | .CLKOUT0_PHASE (0.000), 131 | .CLKOUT0_DUTY_CYCLE (0.500), 132 | .CLKOUT1_DIVIDE (12), 133 | .CLKOUT1_PHASE (0.000), 134 | .CLKOUT1_DUTY_CYCLE (0.500), 135 | .CLKIN1_PERIOD (20.000)) 136 | plle2_adv_inst 137 | // Output clocks 138 | ( 139 | .CLKFBOUT (clkfbout_pll_example), 140 | .CLKOUT0 (clk_out1_pll_example), 141 | .CLKOUT1 (clk_out2_pll_example), 142 | .CLKOUT2 (clkout2_unused), 143 | .CLKOUT3 (clkout3_unused), 144 | .CLKOUT4 (clkout4_unused), 145 | .CLKOUT5 (clkout5_unused), 146 | // Input clock control 147 | .CLKFBIN (clkfbout_buf_pll_example), 148 | .CLKIN1 (clk_in1_pll_example), 149 | .CLKIN2 (1'b0), 150 | // Tied to always select the primary input clock 151 | .CLKINSEL (1'b1), 152 | // Ports for dynamic reconfiguration 153 | .DADDR (7'h0), 154 | .DCLK (1'b0), 155 | .DEN (1'b0), 156 | .DI (16'h0), 157 | .DO (do_unused), 158 | .DRDY (drdy_unused), 159 | .DWE (1'b0), 160 | // Other control and status signals 161 | .LOCKED (locked_int), 162 | .PWRDWN (1'b0), 163 | .RST (reset_high)); 164 | assign reset_high = reset; 165 | 166 | assign locked = locked_int; 167 | // Clock Monitor clock assigning 168 | //-------------------------------------- 169 | // Output buffering 170 | //----------------------------------- 171 | 172 | BUFG clkf_buf 173 | (.O (clkfbout_buf_pll_example), 174 | .I (clkfbout_pll_example)); 175 | 176 | 177 | 178 | 179 | 180 | 181 | BUFG clkout1_buf 182 | (.O (clk_out1), 183 | .I (clk_out1_pll_example)); 184 | 185 | 186 | BUFG clkout2_buf 187 | (.O (clk_out2), 188 | .I (clk_out2_pll_example)); 189 | 190 | 191 | 192 | endmodule 193 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/ip/pll_example/pll_example_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: pll_example_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 20.000 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/mycpu/SRAM_UART_ctrl.v: -------------------------------------------------------------------------------- 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[6:0] oSEG; 5 | 6 | always @(iDIG) 7 | begin 8 | case(iDIG) 9 | 4'h1: oSEG = 7'b1110110; // ---t---- 10 | 4'h2: oSEG = 7'b0100001; // | | 11 | 4'h3: oSEG = 7'b0100100; // lt rt 12 | 4'h4: oSEG = 7'b0010110; // | | 13 | 4'h5: oSEG = 7'b0001100; // ---m---- 14 | 4'h6: oSEG = 7'b0001000; // | | 15 | 4'h7: oSEG = 7'b1100110; // lb rb 16 | 4'h8: oSEG = 7'b0000000; // | | 17 | 4'h9: oSEG = 7'b0000110; // ---b---- 18 | 4'ha: oSEG = 7'b0000010; 19 | 4'hb: oSEG = 7'b0011000; 20 | 4'hc: oSEG = 7'b1001001; 21 | 4'hd: oSEG = 7'b0110000; 22 | 4'he: oSEG = 7'b0001001; 23 | 4'hf: oSEG = 7'b0001011; 24 | 4'h0: oSEG = 7'b1000000; 25 | endcase 26 | end 27 | 28 | assign oSEG1 = {~oSEG,1'b0}; 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/new/async.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////// 2 | // RS-232 RX and TX module 3 | // (c) fpga4fun.com & KNJN LLC - 2003 to 2016 4 | 5 | // The RS-232 settings are fixed 6 | // TX: 8-bit data, 2 stop, no-parity 7 | // RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course) 8 | 9 | //`define SIMULATION // in this mode, TX outputs one bit per clock cycle 10 | // and RX receives one bit per clock cycle (for fast simulations) 11 | 12 | //////////////////////////////////////////////////////// 13 | 14 | module async_transmitter( 15 | input wire clk, 16 | input wire TxD_start, 17 | input wire [7:0] TxD_data, 18 | output wire TxD, 19 | output wire TxD_busy 20 | ); 21 | 22 | // Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data 23 | // TxD_data is latched so that it doesn't have to stay valid while it is being sent 24 | 25 | parameter ClkFrequency = 25000000; // 25MHz 26 | parameter Baud = 115200; 27 | 28 | // generate 29 | // if(ClkFrequency> 1); 52 | 53 | case(TxD_state) 54 | 4'b0000: if(TxD_start) TxD_state <= 4'b0100; 55 | 4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit 56 | 4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0 57 | 4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1 58 | 4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2 59 | 4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3 60 | 4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4 61 | 4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5 62 | 4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6 63 | 4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7 64 | 4'b0010: if(BitTick) TxD_state <= 4'b0000; // stop1 65 | //4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2 66 | default: if(BitTick) TxD_state <= 4'b0000; 67 | endcase 68 | end 69 | 70 | assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits 71 | endmodule 72 | 73 | 74 | //////////////////////////////////////////////////////// 75 | module async_receiver( 76 | input wire clk, 77 | input wire RxD, 78 | output reg RxD_data_ready, 79 | input wire RxD_clear, 80 | output reg [7:0] RxD_data // data received, valid only (for one clock cycle) when RxD_data_ready is asserted 81 | ); 82 | 83 | parameter ClkFrequency = 25000000; // 25MHz 84 | parameter Baud = 115200; 85 | 86 | parameter Oversampling = 8; // needs to be a power of 2 87 | // we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time 88 | // 8 times oversampling by default, use 16 for higher quality reception 89 | 90 | // generate 91 | // if(ClkFrequency>log2) log2=log2+1; end endfunction 136 | localparam l2o = log2(Oversampling); 137 | reg [l2o-2:0] OversamplingCnt = 0; 138 | always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1; 139 | wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1); 140 | `endif 141 | 142 | // now we can accumulate the RxD bits in a shift-register 143 | always @(posedge clk) 144 | case(RxD_state) 145 | 4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found? 146 | 4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow 147 | 4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0 148 | 4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1 149 | 4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2 150 | 4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3 151 | 4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4 152 | 4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5 153 | 4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6 154 | 4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7 155 | 4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit 156 | default: RxD_state <= 4'b0000; 157 | endcase 158 | 159 | always @(posedge clk) 160 | if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]}; 161 | 162 | //reg RxD_data_error = 0; 163 | always @(posedge clk) 164 | begin 165 | if(RxD_clear) 166 | RxD_data_ready <= 0; 167 | else 168 | RxD_data_ready <= RxD_data_ready | (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received 169 | //RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received 170 | end 171 | 172 | `ifdef SIMULATION 173 | assign RxD_idle = 0; 174 | `else 175 | reg [l2o+1:0] GapCnt = 0; 176 | always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1; 177 | assign RxD_idle = GapCnt[l2o+1]; 178 | always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0]; 179 | `endif 180 | 181 | endmodule 182 | 183 | 184 | //////////////////////////////////////////////////////// 185 | // dummy module used to be able to raise an assertion in Verilog 186 | module ASSERTION_ERROR(); 187 | endmodule 188 | 189 | 190 | //////////////////////////////////////////////////////// 191 | module BaudTickGen( 192 | input wire clk, enable, 193 | output wire tick // generate a tick at the specified baud rate * oversampling 194 | ); 195 | parameter ClkFrequency = 25000000; 196 | parameter Baud = 115200; 197 | parameter Oversampling = 1; 198 | 199 | function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction 200 | localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte 201 | reg [AccWidth:0] Acc = 0; 202 | localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow 203 | localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter); 204 | always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0]; 205 | assign tick = Acc[AccWidth]; 206 | endmodule 207 | 208 | 209 | //////////////////////////////////////////////////////// 210 | -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/new/thinpad_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ffhh927/NSCSCC-2023-mips/f18f8622deb8dafd87bf5efc892f344fb0ea94a3/2023319-108mhz/thinpad_top.srcs/sources_1/new/thinpad_top.v -------------------------------------------------------------------------------- /2023319-108mhz/thinpad_top.srcs/sources_1/new/vga.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // 3 | // WIDTH: bits in register hdata & vdata 4 | // HSIZE: horizontal size of visible field 5 | // HFP: horizontal front of pulse 6 | // HSP: horizontal stop of pulse 7 | // HMAX: horizontal max size of value 8 | // VSIZE: vertical size of visible field 9 | // VFP: vertical front of pulse 10 | // VSP: vertical stop of pulse 11 | // VMAX: vertical max size of value 12 | // HSPP: horizontal synchro pulse polarity (0 - negative, 1 - positive) 13 | // VSPP: vertical synchro pulse polarity (0 - negative, 1 - positive) 14 | // 15 | module vga 16 | #(parameter WIDTH = 0, HSIZE = 0, HFP = 0, HSP = 0, HMAX = 0, VSIZE = 0, VFP = 0, VSP = 0, VMAX = 0, HSPP = 0, VSPP = 0) 17 | ( 18 | input wire clk, 19 | output wire hsync, 20 | output wire vsync, 21 | output reg [WIDTH - 1:0] hdata, 22 | output reg [WIDTH - 1:0] vdata, 23 | output wire data_enable 24 | ); 25 | 26 | // hdata 27 | always @ (posedge clk) 28 | begin 29 | if (hdata == (HMAX - 1)) 30 | hdata <= 0; 31 | else 32 | hdata <= hdata + 1; 33 | end 34 | 35 | // vdata 36 | always @ (posedge clk) 37 | begin 38 | if (hdata == (HMAX - 1)) 39 | begin 40 | if (vdata == (VMAX - 1)) 41 | vdata <= 0; 42 | else 43 | vdata <= vdata + 1; 44 | end 45 | end 46 | 47 | // hsync & vsync & blank 48 | assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP; 49 | assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP; 50 | assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE)); 51 | 52 | endmodule -------------------------------------------------------------------------------- /2023319-108mhz/vivado_pid10052.str: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ffhh927/NSCSCC-2023-mips/f18f8622deb8dafd87bf5efc892f344fb0ea94a3/2023319-108mhz/vivado_pid10052.str -------------------------------------------------------------------------------- /2023319-108mhz/vivado_pid24972.str: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Xilinx Vivado v2019.2 (64-bit) [Major: 2019, Minor: 2] 4 | SW Build: 2708876 on Wed Nov 6 21:40:23 MST 2019 5 | IP Build: 2700528 on Thu Nov 7 00:09:20 MST 2019 6 | 7 | Process ID (PID): 24972 8 | License: Customer 9 | 10 | Current time: Thu Aug 17 21:50:14 GMT+08:00 2023 11 | Time zone: GMT+08:00 (GMT+08:00) 12 | 13 | OS: Windows 10 14 | OS Version: 10.0 15 | OS Architecture: amd64 16 | Available processors (cores): 8 17 | 18 | Screen size: 1920x1080 19 | Screen resolution (DPI): 125 20 | Available screens: 1 21 | Available disk space: 48 GB 22 | Default font: family=Dialog,name=Dialog,style=plain,size=15 23 | 24 | Java version: 9.0.4 64-bit 25 | Java home: D:/vivado/Vivado/2019.2/tps/win64/jre9.0.4 26 | Java executable location: D:/vivado/Vivado/2019.2/tps/win64/jre9.0.4/bin/java.exe 27 | Java initial memory (-Xms): 128 MB 28 | Java maximum memory (-Xmx): 3 GB 29 | 30 | 31 | User name: HP 32 | User home directory: C:/Users/HP 33 | User working directory: E:/cpu/test 34 | User country: CN 35 | User language: zh 36 | User locale: zh_CN 37 | 38 | RDI_BASEROOT: D:/vivado/Vivado 39 | HDI_APPROOT: D:/vivado/Vivado/2019.2 40 | RDI_DATADIR: D:/vivado/Vivado/2019.2/data 41 | RDI_BINDIR: D:/vivado/Vivado/2019.2/bin 42 | 43 | Vivado preferences file location: C:/Users/HP/AppData/Roaming/Xilinx/Vivado/2019.2/vivado.xml 44 | Vivado preferences directory: C:/Users/HP/AppData/Roaming/Xilinx/Vivado/2019.2/ 45 | Vivado layouts directory: C:/Users/HP/AppData/Roaming/Xilinx/Vivado/2019.2/layouts 46 | PlanAhead jar file location: D:/vivado/Vivado/2019.2/lib/classes/planAhead.jar 47 | Vivado log file location: E:/cpu/test/vivado.log 48 | Vivado journal file location: E:/cpu/test/vivado.jou 49 | Engine tmp dir: E:/cpu/test/.Xil/Vivado-24972-LAPTOP-7OB1NM4U 50 | 51 | Xilinx Environment Variables 52 | ---------------------------- 53 | XILINX: D:/vivado/Vivado/2019.2/ids_lite/ISE 54 | XILINX_DSP: D:/vivado/Vivado/2019.2/ids_lite/ISE 55 | XILINX_PLANAHEAD: D:/vivado/Vivado/2019.2 56 | XILINX_VIVADO: D:/vivado/Vivado/2019.2 57 | XILINX_VIVADO_HLS: D:/vivado/Vivado/2019.2 58 | 59 | 60 | GUI allocated memory: 154 MB 61 | GUI max memory: 3,072 MB 62 | Engine allocated memory: 643 MB 63 | 64 | Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 65 | 66 | */ 67 | 68 | // TclEventType: START_GUI 69 | // Tcl Message: start_gui 70 | // TclEventType: PROJECT_OPEN_DIALOG 71 | // bB (cr): Open Project : addNotify 72 | // Opening Vivado Project: E:\cpu\test\thinpad_top.xpr. Version: Vivado v2019.2 73 | // TclEventType: DEBUG_PROBE_SET_CHANGE 74 | // Tcl Message: open_project E:/cpu/test/thinpad_top.xpr 75 | // TclEventType: MSGMGR_MOVEMSG 76 | // TclEventType: FILESET_TARGET_UCF_CHANGE 77 | // TclEventType: FILE_SET_NEW 78 | // TclEventType: RUN_COMPLETED 79 | // TclEventType: RUN_STATUS_CHANGE 80 | // TclEventType: FILESET_TARGET_UCF_CHANGE 81 | // TclEventType: RUN_COMPLETED 82 | // TclEventType: RUN_STATUS_CHANGE 83 | // TclEventType: FILESET_TARGET_UCF_CHANGE 84 | // TclEventType: RUN_CURRENT 85 | // TclEventType: PROJECT_DASHBOARD_NEW 86 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 87 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 88 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 89 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 90 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 91 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 92 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 93 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 94 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 95 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 96 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 97 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 98 | // TclEventType: FILE_SET_CHANGE 99 | // TclEventType: PROJECT_NEW 100 | // [GUI Memory]: 80 MB (+81319kb) [00:00:12] 101 | // [Engine Memory]: 736 MB (+620550kb) [00:00:12] 102 | // [GUI Memory]: 97 MB (+13609kb) [00:00:13] 103 | // [GUI Memory]: 121 MB (+20580kb) [00:00:13] 104 | // [Engine Memory]: 774 MB (+739kb) [00:00:15] 105 | // WARNING: HEventQueue.dispatchEvent() is taking 3892 ms. 106 | // Tcl Message: open_project E:/cpu/test/thinpad_top.xpr 107 | // Tcl Message: Scanning sources... Finished scanning sources 108 | // Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/vivado/Vivado/2019.2/data/ip'. 109 | // HMemoryUtils.trashcanNow. Engine heap size: 776 MB. GUI used memory: 58 MB. Current time: 8/17/23, 9:50:19 PM GMT+08:00 110 | // Tcl Message: open_project: Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 803.246 ; gain = 158.898 111 | // Project name: thinpad_top; location: E:/cpu/test; part: xc7a200tfbg676-2 112 | dismissDialog("Open Project"); // bB (cr) 113 | // a (cr): Critical Messages: addNotify 114 | // [Engine Memory]: 821 MB (+8662kb) [00:00:18] 115 | // Tcl Message: update_compile_order -fileset sources_1 116 | selectButton(PAResourceAtoD.CmdMsgDialog_OK, "OK"); // f (a) 117 | dismissDialog("Critical Messages"); // a (cr) 118 | // Elapsed time: 36 seconds 119 | expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v)]", 3); // B (F, cr) 120 | // PAPropertyPanels.initPanels (pll_example.xci) elapsed time: 0.2s 121 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), clock_gen : pll_example (pll_example.xci)]", 4, false); // B (F, cr) 122 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), clock_gen : pll_example (pll_example.xci)]", 4, false, false, false, false, false, true); // B (F, cr) - Double Click 123 | // Run Command: PAResourceCommand.PACommandNames_RECUSTOMIZE_CORE 124 | // TclEventType: LOAD_FEATURE 125 | // O (cr): Re-customize IP : addNotify 126 | // HMemoryUtils.trashcanNow. Engine heap size: 929 MB. GUI used memory: 58 MB. Current time: 8/17/23, 9:51:06 PM GMT+08:00 127 | // [Engine Memory]: 1,002 MB (+147442kb) [00:01:08] 128 | // r (cr): Re-customize IP: addNotify 129 | // WARNING: HEventQueue.dispatchEvent() is taking 1694 ms. 130 | dismissDialog("Re-customize IP"); // O (cr) 131 | selectTab(PAResourceTtoZ.XPG_TabbedPane_TABBED_PANE, (HResource) null, "Output Clocks", 1); // cU (E, r) 132 | setText("CLKOUT1 REQUESTED OUT FREQ", "108"); // D (cV, r) 133 | selectButton(RDIResource.BaseDialog_OK, "OK"); // a (r) 134 | // TclEventType: PACKAGER_OBJECT_ADD 135 | // TclEventType: PACKAGER_OBJECT_CHANGE 136 | dismissDialog("Re-customize IP"); // r (cr) 137 | // TclEventType: DG_GRAPH_STALE 138 | // TclEventType: FILE_SET_CHANGE 139 | // TclEventType: PACKAGER_OBJECT_ADD 140 | // TclEventType: PACKAGER_OBJECT_CHANGE 141 | // TclEventType: FILE_SET_CHANGE 142 | // r (cr): Re-customize IP: addNotify 143 | // TclEventType: FILESET_UPDATE_IP 144 | // bB (r): Re-customize IP : addNotify 145 | // TclEventType: FILESET_UPDATE_IP 146 | // Tcl Message: set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {108} CONFIG.MMCM_CLKFBOUT_MULT_F {43} CONFIG.MMCM_CLKOUT0_DIVIDE_F {10} CONFIG.MMCM_CLKOUT1_DIVIDE {12} CONFIG.CLKOUT1_JITTER {202.759} CONFIG.CLKOUT1_PHASE_ERROR {231.057} CONFIG.CLKOUT2_JITTER {208.075} CONFIG.CLKOUT2_PHASE_ERROR {231.057}] [get_ips pll_example] 147 | // aI (cr): Generate Output Products: addNotify 148 | dismissDialog("Re-customize IP"); // bB (r) 149 | // TclEventType: FILE_SET_CHANGE 150 | // [GUI Memory]: 131 MB (+3143kb) [00:01:20] 151 | selectButton(PAResourceQtoS.SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY, "Generate"); // a (aI) 152 | // HOptionPane Warning: 'A background task is running. Please wait until it completes and try again. (Background Task)' 153 | selectButton("OptionPane.button", "OK"); // JButton (A, H) 154 | selectButton(PAResourceQtoS.SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY, "Generate"); // a (aI) 155 | // bB (cr): Managing Output Products : addNotify 156 | // Tcl Message: generate_target all [get_files E:/cpu/test/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xci] 157 | // Tcl Message: INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'pll_example'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'pll_example'... 158 | // TclEventType: DG_GRAPH_STALE 159 | // TclEventType: FILE_SET_CHANGE 160 | // Tcl Message: INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'pll_example'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'pll_example'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'pll_example'... 161 | // TclEventType: FILE_SET_CHANGE 162 | // TclEventType: OOC_IP_CACHE_USED 163 | // TclEventType: PROJ_DESIGN_MODE_SET 164 | // Tcl Message: catch { config_ip_cache -export [get_ips -all pll_example] } 165 | // Tcl Message: INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP pll_example, cache-ID = 4ac263c60276aa96; cache size = 29.050 MB. 166 | // TclEventType: PROJ_DESIGN_MODE_SET 167 | // Tcl Message: export_ip_user_files -of_objects [get_files E:/cpu/test/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xci] -no_script -sync -force -quiet 168 | // Tcl Message: create_ip_run [get_files -of_objects [get_fileset sources_1] E:/cpu/test/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xci] 169 | // Tcl Message: INFO: [Vivado 12-3453] The given sub-design is up-to-date, no action was taken. If a run is still desired, use the '-force' option for the file:'E:/cpu/test/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xci' 170 | // TclEventType: FILE_SET_CHANGE 171 | // TclEventType: PROJECT_CHANGE 172 | // TclEventType: FILE_SET_CHANGE 173 | // TclEventType: PROJECT_CHANGE 174 | // TclEventType: FILE_SET_CHANGE 175 | // TclEventType: PROJECT_CHANGE 176 | // Tcl Message: export_simulation -of_objects [get_files E:/cpu/test/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xci] -directory E:/cpu/test/thinpad_top.ip_user_files/sim_scripts -ip_user_files_dir E:/cpu/test/thinpad_top.ip_user_files -ipstatic_source_dir E:/cpu/test/thinpad_top.ip_user_files/ipstatic -lib_map_path [list {modelsim=E:/cpu/test/thinpad_top.cache/compile_simlib/modelsim} {questa=E:/cpu/test/thinpad_top.cache/compile_simlib/questa} {riviera=E:/cpu/test/thinpad_top.cache/compile_simlib/riviera} {activehdl=E:/cpu/test/thinpad_top.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet 177 | // TclEventType: FILE_SET_CHANGE 178 | // TclEventType: PROJECT_CHANGE 179 | // TclEventType: FILE_SET_CHANGE 180 | // TclEventType: PROJECT_CHANGE 181 | // TclEventType: FILE_SET_CHANGE 182 | // TclEventType: PROJECT_CHANGE 183 | // TclEventType: FILE_SET_CHANGE 184 | // TclEventType: PROJECT_CHANGE 185 | // TclEventType: FILE_SET_CHANGE 186 | // TclEventType: PROJECT_CHANGE 187 | // TclEventType: PACKAGER_MESSAGE_RESET 188 | // TclEventType: PACKAGER_UNLOAD_CORE 189 | // HMemoryUtils.trashcanNow. Engine heap size: 1,032 MB. GUI used memory: 73 MB. Current time: 8/17/23, 9:51:41 PM GMT+08:00 190 | selectButton("OptionPane.button", "OK"); // JButton (A, G) 191 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v)]", 3, true); // B (F, cr) - Node 192 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v)]", 3, true, false, false, false, false, true); // B (F, cr) - Double Click - Node 193 | expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v)]", 3); // B (F, cr) 194 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), SRAM_UART_ctrl_1 : SRAM_UART_ctrl (SRAM_UART_ctrl.v)]", 8, true); // B (F, cr) - Node 195 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), SRAM_UART_ctrl_1 : SRAM_UART_ctrl (SRAM_UART_ctrl.v), ext_uart_r : async_receiver (async.v)]", 9, true, false, false, false, false, true); // B (F, cr) - Double Click - Node 196 | selectCodeEditor("SRAM_UART_ctrl.v", 270, 84); // ch (w, cr) 197 | selectCodeEditor("SRAM_UART_ctrl.v", 294, 277); // ch (w, cr) 198 | selectCodeEditor("SRAM_UART_ctrl.v", 108, 180); // ch (w, cr) 199 | // TclEventType: DG_GRAPH_STALE 200 | // TclEventType: FILE_SET_CHANGE 201 | selectCodeEditor("SRAM_UART_ctrl.v", 120, 239); // ch (w, cr) 202 | selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 20, false); // u (O, cr) 203 | // Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN 204 | // A (cr): Synthesis is Out-of-date: addNotify 205 | selectButton(RDIResource.BaseDialog_YES, "Yes"); // a (A) 206 | // bB (cr): Resetting Runs : addNotify 207 | // TclEventType: RUN_MODIFY 208 | dismissDialog("Synthesis is Out-of-date"); // A (cr) 209 | // TclEventType: RUN_RESET 210 | // TclEventType: RUN_STATUS_CHANGE 211 | // TclEventType: RUN_RESET 212 | // TclEventType: RUN_STATUS_CHANGE 213 | // TclEventType: RUN_RESET 214 | // TclEventType: RUN_MODIFY 215 | // Tcl Message: reset_run synth_1 216 | // f (cr): Launch Runs: addNotify 217 | selectButton(RDIResource.BaseDialog_OK, "OK"); // a (f) 218 | // TclEventType: FILESET_TARGET_UCF_CHANGE 219 | dismissDialog("Launch Runs"); // f (cr) 220 | // [Engine Memory]: 1,053 MB (+164kb) [00:02:12] 221 | // TclEventType: RUN_LAUNCH 222 | // TclEventType: FILESET_TARGET_UCF_CHANGE 223 | // TclEventType: RUN_LAUNCH 224 | // bB (cr): Generate Bitstream : addNotify 225 | // TclEventType: RUN_MODIFY 226 | // HMemoryUtils.trashcanNow. Engine heap size: 1,058 MB. GUI used memory: 76 MB. Current time: 8/17/23, 9:52:16 PM GMT+08:00 227 | // Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 8 228 | // Tcl Message: INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'E:/cpu/test/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xci' is already up-to-date 229 | // Tcl Message: [Thu Aug 17 21:52:16 2023] Launched synth_1... Run output will be captured here: E:/cpu/test/thinpad_top.runs/synth_1/runme.log [Thu Aug 17 21:52:16 2023] Launched impl_1... Run output will be captured here: E:/cpu/test/thinpad_top.runs/impl_1/runme.log 230 | dismissDialog("Generate Bitstream"); // bB (cr) 231 | // TclEventType: RUN_STATUS_CHANGE 232 | // TclEventType: RUN_COMPLETED 233 | // TclEventType: RUN_STATUS_CHANGE 234 | // TclEventType: RUN_STEP_COMPLETED 235 | // TclEventType: RUN_STATUS_CHANGE 236 | // TclEventType: RUN_STEP_COMPLETED 237 | // TclEventType: RUN_COMPLETED 238 | // TclEventType: RUN_STATUS_CHANGE 239 | // aj (cr): Bitstream Generation Completed: addNotify 240 | -------------------------------------------------------------------------------- /2023319-108mhz/vivado_pid31640.str: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Xilinx Vivado v2019.2 (64-bit) [Major: 2019, Minor: 2] 4 | SW Build: 2708876 on Wed Nov 6 21:40:23 MST 2019 5 | IP Build: 2700528 on Thu Nov 7 00:09:20 MST 2019 6 | 7 | Process ID (PID): 31640 8 | License: Customer 9 | 10 | Current time: Wed Aug 02 23:47:31 GMT+08:00 2023 11 | Time zone: GMT+08:00 (GMT+08:00) 12 | 13 | OS: Windows 10 14 | OS Version: 10.0 15 | OS Architecture: amd64 16 | Available processors (cores): 8 17 | 18 | Screen size: 1920x1080 19 | Screen resolution (DPI): 125 20 | Available screens: 1 21 | Available disk space: 38 GB 22 | Default font: family=Dialog,name=Dialog,style=plain,size=15 23 | 24 | Java version: 9.0.4 64-bit 25 | Java home: D:/vivado/Vivado/2019.2/tps/win64/jre9.0.4 26 | Java executable location: D:/vivado/Vivado/2019.2/tps/win64/jre9.0.4/bin/java.exe 27 | Java initial memory (-Xms): 128 MB 28 | Java maximum memory (-Xmx): 3 GB 29 | 30 | 31 | User name: HP 32 | User home directory: C:/Users/HP 33 | User working directory: E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0 34 | User country: CN 35 | User language: zh 36 | User locale: zh_CN 37 | 38 | RDI_BASEROOT: D:/vivado/Vivado 39 | HDI_APPROOT: D:/vivado/Vivado/2019.2 40 | RDI_DATADIR: D:/vivado/Vivado/2019.2/data 41 | RDI_BINDIR: D:/vivado/Vivado/2019.2/bin 42 | 43 | Vivado preferences file location: C:/Users/HP/AppData/Roaming/Xilinx/Vivado/2019.2/vivado.xml 44 | Vivado preferences directory: C:/Users/HP/AppData/Roaming/Xilinx/Vivado/2019.2/ 45 | Vivado layouts directory: C:/Users/HP/AppData/Roaming/Xilinx/Vivado/2019.2/layouts 46 | PlanAhead jar file location: D:/vivado/Vivado/2019.2/lib/classes/planAhead.jar 47 | Vivado log file location: E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0/vivado.log 48 | Vivado journal file location: E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0/vivado.jou 49 | Engine tmp dir: E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0/.Xil/Vivado-31640-LAPTOP-7OB1NM4U 50 | 51 | Xilinx Environment Variables 52 | ---------------------------- 53 | XILINX: D:/vivado/Vivado/2019.2/ids_lite/ISE 54 | XILINX_DSP: D:/vivado/Vivado/2019.2/ids_lite/ISE 55 | XILINX_PLANAHEAD: D:/vivado/Vivado/2019.2 56 | XILINX_VIVADO: D:/vivado/Vivado/2019.2 57 | XILINX_VIVADO_HLS: D:/vivado/Vivado/2019.2 58 | 59 | 60 | GUI allocated memory: 154 MB 61 | GUI max memory: 3,072 MB 62 | Engine allocated memory: 644 MB 63 | 64 | Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 65 | 66 | */ 67 | 68 | // TclEventType: START_GUI 69 | // Tcl Message: start_gui 70 | // TclEventType: PROJECT_OPEN_DIALOG 71 | // bB (cr): Open Project : addNotify 72 | // Opening Vivado Project: E:\cpu\a_pass\icache_success\fpga_template_mips_utf8_v1.0\thinpad_top.xpr. Version: Vivado v2019.2 73 | // TclEventType: DEBUG_PROBE_SET_CHANGE 74 | // Tcl Message: open_project E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0/thinpad_top.xpr 75 | // TclEventType: MSGMGR_MOVEMSG 76 | // TclEventType: FILESET_TARGET_UCF_CHANGE 77 | // TclEventType: FILE_SET_NEW 78 | // TclEventType: RUN_STATUS_CHANGE 79 | // TclEventType: FILESET_TARGET_UCF_CHANGE 80 | // TclEventType: RUN_COMPLETED 81 | // TclEventType: RUN_STATUS_CHANGE 82 | // TclEventType: RUN_COMPLETED 83 | // TclEventType: RUN_STATUS_CHANGE 84 | // TclEventType: FILESET_TARGET_UCF_CHANGE 85 | // TclEventType: RUN_CURRENT 86 | // TclEventType: PROJECT_DASHBOARD_NEW 87 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 88 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 89 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 90 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 91 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 92 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 93 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 94 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 95 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 96 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 97 | // TclEventType: PROJECT_DASHBOARD_GADGET_NEW 98 | // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE 99 | // TclEventType: FILE_SET_CHANGE 100 | // TclEventType: PROJECT_NEW 101 | // [GUI Memory]: 122 MB (+125883kb) [00:00:13] 102 | // [Engine Memory]: 724 MB (+607574kb) [00:00:13] 103 | // [Engine Memory]: 777 MB (+17747kb) [00:00:15] 104 | // WARNING: HEventQueue.dispatchEvent() is taking 3970 ms. 105 | // Tcl Message: open_project E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0/thinpad_top.xpr 106 | // Tcl Message: INFO: [Project 1-313] Project file moved from 'E:/cpu/a_pass/3/fpga_template_mips_utf8_v5.0' since last save. 107 | // Tcl Message: Scanning sources... Finished scanning sources 108 | // Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/vivado/Vivado/2019.2/data/ip'. 109 | // HMemoryUtils.trashcanNow. Engine heap size: 779 MB. GUI used memory: 57 MB. Current time: 8/2/23, 11:47:36 PM GMT+08:00 110 | // Tcl Message: open_project: Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 803.824 ; gain = 142.348 111 | // Project name: thinpad_top; location: E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0; part: xc7a200tfbg676-2 112 | dismissDialog("Open Project"); // bB (cr) 113 | // TclEventType: FILE_SET_CHANGE 114 | // Tcl Message: update_compile_order -fileset sources_1 115 | // HMemoryUtils.trashcanNow. Engine heap size: 806 MB. GUI used memory: 56 MB. Current time: 8/2/23, 11:48:08 PM GMT+08:00 116 | // Elapsed time: 163 seconds 117 | selectButton(PAResourceQtoS.SyntheticaStateMonitor_CANCEL, "Cancel"); // h (Q, cr) 118 | // bB (cr): Resetting Runs : addNotify 119 | selectButton("OptionPane.button", "Cancel Process"); // JButton (A, G) 120 | // TclEventType: RUN_MODIFY 121 | // TclEventType: RUN_RESET 122 | // Tcl Message: reset_run synth_1 123 | // TclEventType: RUN_RESET 124 | // TclEventType: RUN_STATUS_CHANGE 125 | // TclEventType: RUN_RESET 126 | // TclEventType: RUN_STATUS_CHANGE 127 | // TclEventType: RUN_RESET 128 | // TclEventType: RUN_MODIFY 129 | dismissDialog("Resetting Runs"); // bB (cr) 130 | // PAPropertyPanels.initPanels (fifo_generator_0.xci) elapsed time: 0.2s 131 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, fifo_generator_0 (fifo_generator_0.xci)]", 4, false); // B (F, cr) 132 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, fifo_generator_0 (fifo_generator_0.xci)]", 4, false, false, false, false, false, true); // B (F, cr) - Double Click 133 | // Run Command: PAResourceCommand.PACommandNames_RECUSTOMIZE_CORE 134 | // TclEventType: LOAD_FEATURE 135 | // O (cr): Re-customize IP : addNotify 136 | // r (cr): Re-customize IP: addNotify 137 | // [Engine Memory]: 829 MB (+13621kb) [00:03:08] 138 | // WARNING: HEventQueue.dispatchEvent() is taking 1929 ms. 139 | // HMemoryUtils.trashcanNow. Engine heap size: 829 MB. GUI used memory: 70 MB. Current time: 8/2/23, 11:50:29 PM GMT+08:00 140 | dismissDialog("Re-customize IP"); // O (cr) 141 | dismissDialog("Re-customize IP"); // r (cr) 142 | expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v)]", 2); // B (F, cr) 143 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), clock_gen : pll_example (pll_example.xci)]", 3, false); // B (F, cr) 144 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), clock_gen : pll_example (pll_example.xci)]", 3, false); // B (F, cr) 145 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), clock_gen : pll_example (pll_example.xci)]", 3, false, false, false, false, false, true); // B (F, cr) - Double Click 146 | // Run Command: PAResourceCommand.PACommandNames_RECUSTOMIZE_CORE 147 | // O (cr): Re-customize IP : addNotify 148 | // r (cr): Re-customize IP: addNotify 149 | // [Engine Memory]: 997 MB (+132971kb) [00:03:21] 150 | // WARNING: HEventQueue.dispatchEvent() is taking 1311 ms. 151 | dismissDialog("Re-customize IP"); // O (cr) 152 | selectTab(PAResourceTtoZ.XPG_TabbedPane_TABBED_PANE, (HResource) null, "Output Clocks", 1); // cU (E, r) 153 | dismissDialog("Re-customize IP"); // r (cr) 154 | selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 20, false); // u (O, cr) 155 | // Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN 156 | // A (cr): No Implementation Results Available: addNotify 157 | selectButton(RDIResource.BaseDialog_YES, "Yes"); // a (A) 158 | // bB (cr): Resetting Runs : addNotify 159 | // f (cr): Launch Runs: addNotify 160 | dismissDialog("No Implementation Results Available"); // A (cr) 161 | selectButton(RDIResource.BaseDialog_OK, "OK"); // a (f) 162 | // TclEventType: FILESET_TARGET_UCF_CHANGE 163 | // [GUI Memory]: 139 MB (+11450kb) [00:03:28] 164 | dismissDialog("Launch Runs"); // f (cr) 165 | // TclEventType: FILESET_TARGET_UCF_CHANGE 166 | // Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 8 167 | // TclEventType: RUN_LAUNCH 168 | // TclEventType: FILESET_TARGET_UCF_CHANGE 169 | // TclEventType: RUN_LAUNCH 170 | // bB (cr): Generate Bitstream : addNotify 171 | // TclEventType: RUN_MODIFY 172 | // TclEventType: RUN_STATUS_CHANGE 173 | // TclEventType: RUN_MODIFY 174 | // TclEventType: RUN_STATUS_CHANGE 175 | // TclEventType: RUN_MODIFY 176 | // TclEventType: RUN_STATUS_CHANGE 177 | // Tcl Message: [Wed Aug 2 23:50:49 2023] Launched synth_1... Run output will be captured here: E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0/thinpad_top.runs/synth_1/runme.log [Wed Aug 2 23:50:49 2023] Launched impl_1... Run output will be captured here: E:/cpu/a_pass/icache_success/fpga_template_mips_utf8_v1.0/thinpad_top.runs/impl_1/runme.log 178 | dismissDialog("Generate Bitstream"); // bB (cr) 179 | // TclEventType: RUN_STATUS_CHANGE 180 | // TclEventType: RUN_COMPLETED 181 | // TclEventType: RUN_STATUS_CHANGE 182 | // TclEventType: RUN_STEP_COMPLETED 183 | // TclEventType: RUN_STATUS_CHANGE 184 | // Elapsed time: 97 seconds 185 | expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), mycpu_1 : mycpu (mycpu.v)]", 6); // B (F, cr) 186 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), mycpu_1 : mycpu (mycpu.v), icache0 : icache (icache.v)]", 8, false); // B (F, cr) 187 | selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, thinpad_top (thinpad_top.v), mycpu_1 : mycpu (mycpu.v), icache0 : icache (icache.v)]", 8, false, false, false, false, false, true); // B (F, cr) - Double Click 188 | // TclEventType: RUN_STEP_COMPLETED 189 | // TclEventType: RUN_COMPLETED 190 | // TclEventType: RUN_STATUS_CHANGE 191 | // WARNING: HTimer (ExpRunMgr Pending Runs Timer) is taking 533ms to process. Increasing delay to 3000 ms. 192 | // aj (cr): Bitstream Generation Completed: addNotify 193 | // Elapsed time: 478 seconds 194 | dismissDialog("Bitstream Generation Completed"); // aj (cr) 195 | -------------------------------------------------------------------------------- /2023319-108mhz/vivado_pid33688.debug: -------------------------------------------------------------------------------- 1 | #-------------------------------------------------------------------------- 2 | # Xilinx Vivado v2019.2 (64-bit) 3 | # SW Build: 2708876 on Wed Nov 6 21:40:23 MST 2019 4 | # IP Build: 2700528 on Thu Nov 7 00:09:20 MST 2019 5 | # Current time: Sun Jul 30 21:22:54 GMT+08:00 2023 6 | # Process ID (PID): 33688 7 | # User: HP 8 | # OS: Windows 10 9 | # 10 | # This file is an indication that an internal application error occurred. 11 | # This information is useful for debugging. Please open a case with Xilinx. 12 | # Technical Support with this file and a testcase attached. 13 | #-------------------------------------------------------------------------- 14 | Sun Jul 30 21:22:54 GMT+08:00 2023 15 | ui.utils.e: ui.frmwork.CommandFailedException: Unknown exception occurred ui.frmwork.CommandFailedException: Unknown exception occurred 16 | at ui.views.simulator.executive.simulationi.SimulationExecutive_getCallStacksData(Native Method) 17 | at ui.views.O.c.a.gzr(SourceFile:1302) 18 | at ui.views.O.a.B.reset(SourceFile:393) 19 | at ui.views.O.a.B.a(SourceFile:328) 20 | at ui.views.O.a.A.reset(SourceFile:274) 21 | at ui.views.O.a.x.reset(SourceFile:67) 22 | at ui.views.O.a.D.reset(SourceFile:124) 23 | at ui.views.O.a.D.a(SourceFile:114) 24 | at ui.frmwork.b.l.d(SourceFile:42) 25 | at ui.frmwork.G.i(SourceFile:253) 26 | at ui.frmwork.G.fireTclEvent(SourceFile:350) 27 | at ui.views.simulator.executive.simulationi.SimulationExecutive_setTreeWindowTreeHeight(Native Method) 28 | at ui.views.O.c.a.b(SourceFile:674) 29 | at ui.views.O.i.f.gzG(SourceFile:116) 30 | at ui.views.O.i.i.componentResized(SourceFile:139) 31 | at java.desktop/java.awt.Component.processComponentEvent(Unknown Source) 32 | at java.desktop/java.awt.Component.processEvent(Unknown Source) 33 | at java.desktop/java.awt.Container.processEvent(Unknown Source) 34 | at java.desktop/java.awt.Component.dispatchEventImpl(Unknown Source) 35 | at java.desktop/java.awt.Container.dispatchEventImpl(Unknown Source) 36 | at java.desktop/java.awt.Component.dispatchEvent(Unknown Source) 37 | at java.desktop/java.awt.EventQueue.dispatchEventImpl(Unknown Source) 38 | at java.desktop/java.awt.EventQueue.access$500(Unknown Source) 39 | at java.desktop/java.awt.EventQueue$3.run(Unknown Source) 40 | at java.desktop/java.awt.EventQueue$3.run(Unknown Source) 41 | at java.base/java.security.AccessController.doPrivileged(Native Method) 42 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 43 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 44 | at java.desktop/java.awt.EventQueue$4.run(Unknown Source) 45 | at java.desktop/java.awt.EventQueue$4.run(Unknown Source) 46 | at java.base/java.security.AccessController.doPrivileged(Native Method) 47 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 48 | at java.desktop/java.awt.EventQueue.dispatchEvent(Unknown Source) 49 | at ui.frmwork.b.d.dispatchEvent(SourceFile:88) 50 | at java.desktop/java.awt.EventDispatchThread.pumpOneEventForFilters(Unknown Source) 51 | at java.desktop/java.awt.EventDispatchThread.pumpEventsForFilter(Unknown Source) 52 | at java.desktop/java.awt.EventDispatchThread.pumpEventsForFilter(Unknown Source) 53 | at java.desktop/java.awt.WaitDispatchSupport$2.run(Unknown Source) 54 | at java.desktop/java.awt.WaitDispatchSupport$4.run(Unknown Source) 55 | at java.desktop/java.awt.WaitDispatchSupport$4.run(Unknown Source) 56 | at java.base/java.security.AccessController.doPrivileged(Native Method) 57 | at java.desktop/java.awt.WaitDispatchSupport.enter(Unknown Source) 58 | at java.desktop/java.awt.Dialog.show(Unknown Source) 59 | at java.desktop/java.awt.Component.show(Unknown Source) 60 | at java.desktop/java.awt.Component.setVisible(Unknown Source) 61 | at java.desktop/java.awt.Window.setVisible(Unknown Source) 62 | at java.desktop/java.awt.Dialog.setVisible(Unknown Source) 63 | at ui.b.c.g.setVisible(SourceFile:919) 64 | at ui.b.c.bB.showDialog(SourceFile:978) 65 | at ui.b.c.bI.actionPerformed(SourceFile:1120) 66 | at ui.b.c.bB.cSz(SourceFile:1079) 67 | at ui.views.c.t.b.a.run(SourceFile:81) 68 | at ui.frmwork.a.epE(SourceFile:132) 69 | at ui.frmwork.Y.erq(SourceFile:66) 70 | at ui.bm.actionPerformed(SourceFile:547) 71 | at java.desktop/javax.swing.AbstractButton.fireActionPerformed(Unknown Source) 72 | at ui.utils.p.b.E.fireActionPerformed(SourceFile:243) 73 | at java.desktop/javax.swing.AbstractButton$Handler.actionPerformed(Unknown Source) 74 | at java.desktop/javax.swing.DefaultButtonModel.fireActionPerformed(Unknown Source) 75 | at java.desktop/javax.swing.DefaultButtonModel.setPressed(Unknown Source) 76 | at java.desktop/javax.swing.plaf.basic.BasicButtonListener.mouseReleased(Unknown Source) 77 | at com.jidesoft.plaf.basic.BasicJideButtonListener.mouseReleased(Unknown Source) 78 | at java.desktop/java.awt.AWTEventMulticaster.mouseReleased(Unknown Source) 79 | at java.desktop/java.awt.AWTEventMulticaster.mouseReleased(Unknown Source) 80 | at java.desktop/java.awt.AWTEventMulticaster.mouseReleased(Unknown Source) 81 | at java.desktop/java.awt.AWTEventMulticaster.mouseReleased(Unknown Source) 82 | at java.desktop/java.awt.Component.processMouseEvent(Unknown Source) 83 | at java.desktop/javax.swing.JComponent.processMouseEvent(Unknown Source) 84 | at java.desktop/java.awt.Component.processEvent(Unknown Source) 85 | at java.desktop/java.awt.Container.processEvent(Unknown Source) 86 | at java.desktop/java.awt.Component.dispatchEventImpl(Unknown Source) 87 | at java.desktop/java.awt.Container.dispatchEventImpl(Unknown Source) 88 | at java.desktop/java.awt.Component.dispatchEvent(Unknown Source) 89 | at java.desktop/java.awt.LightweightDispatcher.retargetMouseEvent(Unknown Source) 90 | at java.desktop/java.awt.LightweightDispatcher.processMouseEvent(Unknown Source) 91 | at java.desktop/java.awt.LightweightDispatcher.dispatchEvent(Unknown Source) 92 | at java.desktop/java.awt.Container.dispatchEventImpl(Unknown Source) 93 | at java.desktop/java.awt.Window.dispatchEventImpl(Unknown Source) 94 | at java.desktop/java.awt.Component.dispatchEvent(Unknown Source) 95 | at java.desktop/java.awt.EventQueue.dispatchEventImpl(Unknown Source) 96 | at java.desktop/java.awt.EventQueue.access$500(Unknown Source) 97 | at java.desktop/java.awt.EventQueue$3.run(Unknown Source) 98 | at java.desktop/java.awt.EventQueue$3.run(Unknown Source) 99 | at java.base/java.security.AccessController.doPrivileged(Native Method) 100 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 101 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 102 | at java.desktop/java.awt.EventQueue$4.run(Unknown Source) 103 | at java.desktop/java.awt.EventQueue$4.run(Unknown Source) 104 | at java.base/java.security.AccessController.doPrivileged(Native Method) 105 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 106 | at java.desktop/java.awt.EventQueue.dispatchEvent(Unknown Source) 107 | at ui.frmwork.b.d.dispatchEvent(SourceFile:88) 108 | at java.desktop/java.awt.EventDispatchThread.pumpOneEventForFilters(Unknown Source) 109 | at java.desktop/java.awt.EventDispatchThread.pumpEventsForFilter(Unknown Source) 110 | at java.desktop/java.awt.EventDispatchThread.pumpEventsForHierarchy(Unknown Source) 111 | at java.desktop/java.awt.EventDispatchThread.pumpEvents(Unknown Source) 112 | at java.desktop/java.awt.EventDispatchThread.pumpEvents(Unknown Source) 113 | at java.desktop/java.awt.EventDispatchThread.run(Unknown Source) 114 | 115 | at ui.utils.d.c.f(SourceFile:845) 116 | at ui.utils.d.c.debug(SourceFile:240) 117 | at ui.utils.o.debug(SourceFile:229) 118 | at ui.frmwork.G.fireTclEvent(SourceFile:353) 119 | at ui.views.simulator.executive.simulationi.SimulationExecutive_setTreeWindowTreeHeight(Native Method) 120 | at ui.views.O.c.a.b(SourceFile:674) 121 | at ui.views.O.i.f.gzG(SourceFile:116) 122 | at ui.views.O.i.i.componentResized(SourceFile:139) 123 | at java.desktop/java.awt.Component.processComponentEvent(Unknown Source) 124 | at java.desktop/java.awt.Component.processEvent(Unknown Source) 125 | at java.desktop/java.awt.Container.processEvent(Unknown Source) 126 | at java.desktop/java.awt.Component.dispatchEventImpl(Unknown Source) 127 | at java.desktop/java.awt.Container.dispatchEventImpl(Unknown Source) 128 | at java.desktop/java.awt.Component.dispatchEvent(Unknown Source) 129 | at java.desktop/java.awt.EventQueue.dispatchEventImpl(Unknown Source) 130 | at java.desktop/java.awt.EventQueue.access$500(Unknown Source) 131 | at java.desktop/java.awt.EventQueue$3.run(Unknown Source) 132 | at java.desktop/java.awt.EventQueue$3.run(Unknown Source) 133 | at java.base/java.security.AccessController.doPrivileged(Native Method) 134 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 135 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 136 | at java.desktop/java.awt.EventQueue$4.run(Unknown Source) 137 | at java.desktop/java.awt.EventQueue$4.run(Unknown Source) 138 | at java.base/java.security.AccessController.doPrivileged(Native Method) 139 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 140 | at java.desktop/java.awt.EventQueue.dispatchEvent(Unknown Source) 141 | at ui.frmwork.b.d.dispatchEvent(SourceFile:88) 142 | at java.desktop/java.awt.EventDispatchThread.pumpOneEventForFilters(Unknown Source) 143 | at java.desktop/java.awt.EventDispatchThread.pumpEventsForFilter(Unknown Source) 144 | at java.desktop/java.awt.EventDispatchThread.pumpEventsForFilter(Unknown Source) 145 | at java.desktop/java.awt.WaitDispatchSupport$2.run(Unknown Source) 146 | at java.desktop/java.awt.WaitDispatchSupport$4.run(Unknown Source) 147 | at java.desktop/java.awt.WaitDispatchSupport$4.run(Unknown Source) 148 | at java.base/java.security.AccessController.doPrivileged(Native Method) 149 | at java.desktop/java.awt.WaitDispatchSupport.enter(Unknown Source) 150 | at java.desktop/java.awt.Dialog.show(Unknown Source) 151 | at java.desktop/java.awt.Component.show(Unknown Source) 152 | at java.desktop/java.awt.Component.setVisible(Unknown Source) 153 | at java.desktop/java.awt.Window.setVisible(Unknown Source) 154 | at java.desktop/java.awt.Dialog.setVisible(Unknown Source) 155 | at ui.b.c.g.setVisible(SourceFile:919) 156 | at ui.b.c.bB.showDialog(SourceFile:978) 157 | at ui.b.c.bI.actionPerformed(SourceFile:1120) 158 | at ui.b.c.bB.cSz(SourceFile:1079) 159 | at ui.views.c.t.b.a.run(SourceFile:81) 160 | at ui.frmwork.a.epE(SourceFile:132) 161 | at ui.frmwork.Y.erq(SourceFile:66) 162 | at ui.bm.actionPerformed(SourceFile:547) 163 | at java.desktop/javax.swing.AbstractButton.fireActionPerformed(Unknown Source) 164 | at ui.utils.p.b.E.fireActionPerformed(SourceFile:243) 165 | at java.desktop/javax.swing.AbstractButton$Handler.actionPerformed(Unknown Source) 166 | at java.desktop/javax.swing.DefaultButtonModel.fireActionPerformed(Unknown Source) 167 | at java.desktop/javax.swing.DefaultButtonModel.setPressed(Unknown Source) 168 | at java.desktop/javax.swing.plaf.basic.BasicButtonListener.mouseReleased(Unknown Source) 169 | at com.jidesoft.plaf.basic.BasicJideButtonListener.mouseReleased(Unknown Source) 170 | at java.desktop/java.awt.AWTEventMulticaster.mouseReleased(Unknown Source) 171 | at java.desktop/java.awt.AWTEventMulticaster.mouseReleased(Unknown Source) 172 | at java.desktop/java.awt.AWTEventMulticaster.mouseReleased(Unknown Source) 173 | at java.desktop/java.awt.AWTEventMulticaster.mouseReleased(Unknown Source) 174 | at java.desktop/java.awt.Component.processMouseEvent(Unknown Source) 175 | at java.desktop/javax.swing.JComponent.processMouseEvent(Unknown Source) 176 | at java.desktop/java.awt.Component.processEvent(Unknown Source) 177 | at java.desktop/java.awt.Container.processEvent(Unknown Source) 178 | at java.desktop/java.awt.Component.dispatchEventImpl(Unknown Source) 179 | at java.desktop/java.awt.Container.dispatchEventImpl(Unknown Source) 180 | at java.desktop/java.awt.Component.dispatchEvent(Unknown Source) 181 | at java.desktop/java.awt.LightweightDispatcher.retargetMouseEvent(Unknown Source) 182 | at java.desktop/java.awt.LightweightDispatcher.processMouseEvent(Unknown Source) 183 | at java.desktop/java.awt.LightweightDispatcher.dispatchEvent(Unknown Source) 184 | at java.desktop/java.awt.Container.dispatchEventImpl(Unknown Source) 185 | at java.desktop/java.awt.Window.dispatchEventImpl(Unknown Source) 186 | at java.desktop/java.awt.Component.dispatchEvent(Unknown Source) 187 | at java.desktop/java.awt.EventQueue.dispatchEventImpl(Unknown Source) 188 | at java.desktop/java.awt.EventQueue.access$500(Unknown Source) 189 | at java.desktop/java.awt.EventQueue$3.run(Unknown Source) 190 | at java.desktop/java.awt.EventQueue$3.run(Unknown Source) 191 | at java.base/java.security.AccessController.doPrivileged(Native Method) 192 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 193 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 194 | at java.desktop/java.awt.EventQueue$4.run(Unknown Source) 195 | at java.desktop/java.awt.EventQueue$4.run(Unknown Source) 196 | at java.base/java.security.AccessController.doPrivileged(Native Method) 197 | at java.base/java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(Unknown Source) 198 | at java.desktop/java.awt.EventQueue.dispatchEvent(Unknown Source) 199 | at ui.frmwork.b.d.dispatchEvent(SourceFile:88) 200 | at java.desktop/java.awt.EventDispatchThread.pumpOneEventForFilters(Unknown Source) 201 | at java.desktop/java.awt.EventDispatchThread.pumpEventsForFilter(Unknown Source) 202 | at java.desktop/java.awt.EventDispatchThread.pumpEventsForHierarchy(Unknown Source) 203 | at java.desktop/java.awt.EventDispatchThread.pumpEvents(Unknown Source) 204 | at java.desktop/java.awt.EventDispatchThread.pumpEvents(Unknown Source) 205 | at java.desktop/java.awt.EventDispatchThread.run(Unknown Source) 206 | 207 | -------------------------------------------------------------------------------- /2023319-108mhz/vivado_pid33688.str: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ffhh927/NSCSCC-2023-mips/f18f8622deb8dafd87bf5efc892f344fb0ea94a3/2023319-108mhz/vivado_pid33688.str -------------------------------------------------------------------------------- /2023319-108mhz/设计报告.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ffhh927/NSCSCC-2023-mips/f18f8622deb8dafd87bf5efc892f344fb0ea94a3/2023319-108mhz/设计报告.pdf -------------------------------------------------------------------------------- /2023龙芯杯竞赛总结.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ffhh927/NSCSCC-2023-mips/f18f8622deb8dafd87bf5efc892f344fb0ea94a3/2023龙芯杯竞赛总结.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2023年龙芯杯mips赛道 2 | 3 | 成绩0.074，0.109，0.260 --------------------------------------------------------------------------------