├── .gitignore ├── README.md ├── bt_can_spp ├── Makefile ├── main │ ├── bt_can_spp.c │ ├── component.mk │ ├── shared_gpio.c │ ├── shared_gpio.h │ ├── sl_can_proto.c │ └── sl_can_proto.h ├── sdkconfig ├── sdkconfig.defaults └── sdkconfig.old └── mcp2515 ├── MCP2515.c ├── MCP2515.h ├── can.h ├── component.mk ├── spi_routine.c └── spi_routine.h /.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | kicad 3 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ESP32 BT SLCAN implementation 2 | ======================= 3 | 4 | WTF 5 | --- 6 | 7 | esp32 firmware for handling SLCAN protocol. Need additional hw - MCP2515 + TJA1050. 8 | _______________________ 9 | 10 | Not implemented 11 | --------------- 12 | - ~~BT SPP~~ 13 | - ~~Init~~ 14 | - ~~Usual CAN frames~~ 15 | - ~~Extended CAN frames~~ 16 | - Rtr frames 17 | - Direct BTR0/1 write 18 | - Status flags 19 | - Filters 20 | -------------------------------------------------------------------------------- /bt_can_spp/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT_NAME := bt_can_spp 2 | 3 | COMPONENT_ADD_INCLUDEDIRS := components/include 4 | 5 | EXTRA_COMPONENT_DIRS = $(PROJECT_PATH)/../mcp2515 6 | 7 | include $(IDF_PATH)/make/project.mk 8 | -------------------------------------------------------------------------------- /bt_can_spp/main/bt_can_spp.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | 7 | #include "nvs.h" 8 | #include "nvs_flash.h" 9 | #include "freertos/FreeRTOS.h" 10 | #include "freertos/task.h" 11 | #include "esp_log.h" 12 | #include "esp_bt.h" 13 | #include "esp_bt_main.h" 14 | #include "esp_gap_bt_api.h" 15 | #include "esp_bt_device.h" 16 | #include "esp_spp_api.h" 17 | #include "esp_system.h" 18 | #include "esp_event_loop.h" 19 | 20 | 21 | #include "time.h" 22 | #include "sys/time.h" 23 | 24 | #include "soc/gpio_struct.h" 25 | #include "driver/gpio.h" 26 | 27 | #include "shared_gpio.h" 28 | #include "spi_routine.h" 29 | #include "MCP2515.h" 30 | #include "can.h" 31 | #include "sl_can_proto.h" 32 | 33 | #define MAIN_TAG "MAIN" 34 | #define SPP_TAG "SPP_ACCEPTOR" 35 | #define SPP_SERVER_NAME "SPP_SERVER" 36 | #define EXAMPLE_DEVICE_NAME "CAN_ESP_IF" 37 | 38 | xQueueHandle can_frame_queue = NULL; 39 | SemaphoreHandle_t cdc_mtx; 40 | xQueueHandle can_irq_quee = NULL; 41 | 42 | uint32_t handle = 0; 43 | 44 | static const esp_spp_mode_t esp_spp_mode = ESP_SPP_MODE_CB; 45 | static const esp_spp_sec_t sec_mask = ESP_SPP_SEC_NONE; 46 | static const esp_spp_role_t role_slave = ESP_SPP_ROLE_SLAVE; 47 | 48 | static void esp_spp_cb(esp_spp_cb_event_t event, esp_spp_cb_param_t *param) { 49 | switch (event) { 50 | case ESP_SPP_INIT_EVT: 51 | ESP_LOGI(SPP_TAG, "ESP_SPP_INIT_EVT"); 52 | esp_bt_dev_set_device_name(EXAMPLE_DEVICE_NAME); 53 | esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE); 54 | esp_spp_start_srv(sec_mask,role_slave, 0, SPP_SERVER_NAME); 55 | break; 56 | case ESP_SPP_DISCOVERY_COMP_EVT: 57 | ESP_LOGI(SPP_TAG, "ESP_SPP_DISCOVERY_COMP_EVT"); 58 | break; 59 | case ESP_SPP_OPEN_EVT: 60 | ESP_LOGI(SPP_TAG, "ESP_SPP_OPEN_EVT"); 61 | break; 62 | case ESP_SPP_CLOSE_EVT: 63 | reset_mcp(); 64 | ESP_LOGI(SPP_TAG, "ESP_SPP_CLOSE_EVT"); 65 | break; 66 | case ESP_SPP_START_EVT: 67 | ESP_LOGI(SPP_TAG, "ESP_SPP_START_EVT"); 68 | break; 69 | case ESP_SPP_CL_INIT_EVT: 70 | ESP_LOGI(SPP_TAG, "ESP_SPP_CL_INIT_EVT"); 71 | break; 72 | case ESP_SPP_DATA_IND_EVT: 73 | ESP_LOGI(SPP_TAG, "ESP_SPP_DATA_IND_EVT len=%d handle=%d", 74 | param->data_ind.len, param->data_ind.handle); 75 | receive_cmd(param->data_ind.data, param->data_ind.len); 76 | break; 77 | case ESP_SPP_CONG_EVT: 78 | ESP_LOGI(SPP_TAG, "ESP_SPP_CONG_EVT"); 79 | break; 80 | case ESP_SPP_WRITE_EVT: 81 | ESP_LOGI(SPP_TAG, "ESP_SPP_WRITE_EVT"); 82 | break; 83 | case ESP_SPP_SRV_OPEN_EVT: 84 | handle = param->write.handle; 85 | ESP_LOGI(SPP_TAG, "ESP_SPP_SRV_OPEN_EVT"); 86 | break; 87 | default: 88 | break; 89 | } 90 | } 91 | 92 | void app_main() { 93 | esp_err_t ret; 94 | can_frame_queue = xQueueCreate(10, sizeof(uint32_t)); 95 | can_irq_quee = xQueueCreate(10, sizeof(uint32_t)); 96 | cdc_mtx = xSemaphoreCreateMutex(); 97 | 98 | // cdc_response_queue = xQueueCreate(10, sizeof(uint32_t)); 99 | 100 | ret = nvs_flash_init(); 101 | if (ret == ESP_ERR_NVS_NO_FREE_PAGES) { 102 | ESP_ERROR_CHECK(nvs_flash_erase()); 103 | ret = nvs_flash_init(); 104 | } 105 | ESP_ERROR_CHECK(ret); 106 | 107 | 108 | esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); 109 | if ((ret = esp_bt_controller_init(&bt_cfg)) != ESP_OK) { 110 | ESP_LOGE(SPP_TAG, "%s initialize controller failed: %s\n", __func__, esp_err_to_name(ret)); 111 | return; 112 | } 113 | 114 | if ((ret = esp_bt_controller_enable(ESP_BT_MODE_CLASSIC_BT)) != ESP_OK) { 115 | ESP_LOGE(SPP_TAG, "%s enable controller failed: %s\n", __func__, esp_err_to_name(ret)); 116 | return; 117 | } 118 | 119 | if ((ret = esp_bluedroid_init()) != ESP_OK) { 120 | ESP_LOGE(SPP_TAG, "%s initialize bluedroid failed: %s\n", __func__, esp_err_to_name(ret)); 121 | return; 122 | } 123 | 124 | if ((ret = esp_bluedroid_enable()) != ESP_OK) { 125 | ESP_LOGE(SPP_TAG, "%s enable bluedroid failed: %s\n", __func__, esp_err_to_name(ret)); 126 | return; 127 | } 128 | 129 | if ((ret = esp_spp_register_callback(esp_spp_cb)) != ESP_OK) { 130 | ESP_LOGE(SPP_TAG, "%s spp register failed: %s\n", __func__, esp_err_to_name(ret)); 131 | return; 132 | } 133 | 134 | if ((ret = esp_spp_init(esp_spp_mode)) != ESP_OK) { 135 | ESP_LOGE(SPP_TAG, "%s spp init failed: %s\n", __func__, esp_err_to_name(ret)); 136 | return; 137 | } 138 | 139 | init_gpio(); 140 | init_sl_can(); 141 | 142 | ret = init_spi(); 143 | if (ret) { 144 | ESP_LOGE(MAIN_TAG, "%s initialize spi failed\n", __func__); 145 | return; 146 | } 147 | bootstrap_mcp(); 148 | 149 | // ret = init_spi(); 150 | // if (ret) { 151 | // ESP_LOGE(MAIN_TAG, "%s initialize spi failed\n", __func__); 152 | // return; 153 | // } 154 | 155 | } 156 | 157 | -------------------------------------------------------------------------------- /bt_can_spp/main/component.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fido-node/esp32_can/17edd996024fd36565224b7b103a2694445e4242/bt_can_spp/main/component.mk -------------------------------------------------------------------------------- /bt_can_spp/main/shared_gpio.c: -------------------------------------------------------------------------------- 1 | #include "shared_gpio.h" 2 | #include "driver/gpio.h" 3 | 4 | void init_gpio() { 5 | gpio_set_direction(GPIO_LED, GPIO_MODE_INPUT_OUTPUT); 6 | } 7 | 8 | void tgl_led() { 9 | gpio_set_level(GPIO_LED, 1 - gpio_get_level(GPIO_LED)); 10 | } 11 | 12 | void led_on() { 13 | gpio_set_level(GPIO_LED, 1); 14 | } 15 | 16 | void led_off() { 17 | gpio_set_level(GPIO_LED, 0); 18 | } 19 | 20 | // void p_on(uint8_t id) { 21 | // gpio_set_level(id, 1); 22 | // } 23 | 24 | // void p_off(uint8_t id) { 25 | // gpio_set_level(id, 0); 26 | // } 27 | 28 | // void p_tg(uint8_t id) { 29 | // uint8_t state = gpio_get_level(id); 30 | // gpio_set_level(id, 1 - state); 31 | // } -------------------------------------------------------------------------------- /bt_can_spp/main/shared_gpio.h: -------------------------------------------------------------------------------- 1 | #ifndef SHARED_GPIO_H 2 | #define SHARED_GPIO_H 3 | #include "esp_err.h" 4 | 5 | #define GPIO_LED 2 6 | 7 | #define GPIO_OUTPUT_PIN_SEL (1< 4 | 5 | #include "freertos/FreeRTOS.h" 6 | #include "freertos/task.h" 7 | #include "freertos/event_groups.h" 8 | #include "freertos/queue.h" 9 | #include "freertos/semphr.h" 10 | 11 | #include "esp_log.h" 12 | #include "esp_spp_api.h" 13 | 14 | #include "MCP2515.h" 15 | 16 | #define MAIN_TAG "SL_CAN_PROTO" 17 | 18 | // extern xQueueHandle cdc_response_queue; 19 | 20 | long baud = (long)100E3; 21 | 22 | extern uint32_t handle; 23 | 24 | char* SLCAN_VERSION = "V0101\r"; 25 | char* SLCAN_DEV = "vSTM32\r"; 26 | char* OK_R = "\r"; 27 | 28 | extern SemaphoreHandle_t cdc_mtx; 29 | 30 | void send_to_cdc(char *resp, uint32_t len) { 31 | 32 | uint8_t taken = xSemaphoreTake(cdc_mtx, portMAX_DELAY); 33 | while(taken != 1) { 34 | taken = xSemaphoreTake(cdc_mtx, portMAX_DELAY); 35 | } 36 | 37 | esp_spp_write(handle, len, (uint8_t *)resp); 38 | if (resp != SLCAN_VERSION && resp != SLCAN_DEV && resp != OK_R) { 39 | free(resp); 40 | } 41 | 42 | xSemaphoreGive(cdc_mtx); 43 | } 44 | 45 | void frame_tx_cb(uint8_t *cmd, uint32_t len) { 46 | if (len > 6) { 47 | 48 | struct CanFrame *f = malloc(sizeof(struct CanFrame)); 49 | memset(f, 0, sizeof(struct CanFrame)); 50 | if (f != NULL) { 51 | char* id_s = malloc(4); 52 | char* dlc_s = malloc(2); 53 | char* byte_s = malloc(3); 54 | // t0221FF 55 | strncpy(id_s, (char *)cmd + 1, 3); 56 | strncpy(dlc_s, (char *)cmd + 4, 1); 57 | f->IsExt = false; 58 | f->CanId =(uint32_t) strtoul((char *) id_s, NULL, 16); 59 | f->DLC = atoi(dlc_s); 60 | for (uint8_t i = 0; i < f->DLC; i++) { 61 | strncpy(byte_s, (char *)cmd + (5 + (2 * i)), 2); 62 | f->Data[i] = (uint8_t) strtoul((char *) byte_s, NULL, 16); 63 | } 64 | 65 | free(id_s); 66 | free(dlc_s); 67 | free(byte_s); 68 | send_frame(f); 69 | free(f); 70 | } 71 | } 72 | } 73 | 74 | void frame_ext_tx_cb(uint8_t *cmd, uint32_t len) { 75 | if (len > 11) { 76 | 77 | struct CanFrame *f = malloc(sizeof(struct CanFrame)); 78 | memset(f, 0, sizeof(struct CanFrame)); 79 | if (f != NULL) { 80 | char* id_s = malloc(9); 81 | char* dlc_s = malloc(2); 82 | char* byte_s = malloc(3); 83 | // T000099994DEABBABA 84 | strncpy(id_s, (char *)cmd + 1, 8); 85 | strncpy(dlc_s, (char *)cmd + 9, 1); 86 | f->IsExt = true; 87 | f->CanId =(uint32_t) strtoul((char *) id_s, NULL, 16); 88 | f->DLC = atoi(dlc_s); 89 | for (uint8_t i = 0; i < f->DLC; i++) { 90 | strncpy(byte_s, (char *)cmd + (10 + (2 * i)), 2); 91 | f->Data[i] = (uint8_t) strtoul((char *) byte_s, NULL, 16); 92 | } 93 | 94 | free(id_s); 95 | free(dlc_s); 96 | free(byte_s); 97 | send_frame(f); 98 | free(f); 99 | } 100 | } 101 | } 102 | 103 | void frame_rx_cb(struct CanFrame *f) { 104 | char* str = NULL; 105 | uint8_t char_len = 6; 106 | if (!f->IsExt) { 107 | 108 | char_len = char_len + (f->DLC * 2) + 1; 109 | 110 | str = malloc(char_len); 111 | memset(str, 0, sizeof(char_len)); 112 | if (str != NULL) { 113 | switch (f->DLC) { 114 | case 0: 115 | sprintf(str, "t%03x%d\r", f->CanId, f->DLC); 116 | break; 117 | case 1: 118 | sprintf(str, "t%03x%d%02x\r", f->CanId, f->DLC, f->Data[0]); 119 | break; 120 | case 2: 121 | sprintf(str, "t%03x%d%02x%02x\r", f->CanId, f->DLC, 122 | f->Data[0], f->Data[1]); 123 | break; 124 | case 3: 125 | sprintf(str, "t%03x%d%02x%02x%02x\r", f->CanId, f->DLC, 126 | f->Data[0], f->Data[1], f->Data[2]); 127 | break; 128 | case 4: 129 | sprintf(str, "t%03x%d%02x%02x%02x%02x\r", f->CanId, 130 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3]); 131 | break; 132 | case 5: 133 | sprintf(str, "t%03x%d%02x%02x%02x%02x%02x\r" , f->CanId, 134 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3], 135 | f->Data[4]); 136 | break; 137 | case 6: 138 | sprintf(str, "t%03x%d%02x%02x%02x%02x%02x%02x\r", f->CanId, 139 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3], 140 | f->Data[4], f->Data[5]); 141 | break; 142 | case 7: 143 | sprintf(str, "t%03x%d%02x%02x%02x%02x%02x%02x%02x\r", f->CanId, 144 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3], 145 | f->Data[4], f->Data[5], f->Data[6]); 146 | break; 147 | case 8: 148 | sprintf(str, "t%03x%d%02x%02x%02x%02x%02x%02x%02x%02x\r", f->CanId, 149 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3], 150 | f->Data[4], f->Data[5], f->Data[6], f->Data[7]); 151 | break; 152 | } 153 | } 154 | } else { 155 | char_len = 11; 156 | char_len = char_len + (f->DLC * 2) + 1; 157 | 158 | str = malloc(char_len); 159 | memset(str, 0, sizeof(char_len)); 160 | if (str != NULL) { 161 | switch (f->DLC) { 162 | case 0: 163 | sprintf(str, "T%08x%d\r", f->CanId, f->DLC); 164 | break; 165 | case 1: 166 | sprintf(str, "T%08x%d%02x\r", f->CanId, f->DLC, f->Data[0]); 167 | break; 168 | case 2: 169 | sprintf(str, "T%08x%d%02x%02x\r", f->CanId, f->DLC, 170 | f->Data[0], f->Data[1]); 171 | break; 172 | case 3: 173 | sprintf(str, "T%08x%d%02x%02x%02x\r", f->CanId, f->DLC, 174 | f->Data[0], f->Data[1], f->Data[2]); 175 | break; 176 | case 4: 177 | sprintf(str, "T%08x%d%02x%02x%02x%02x\r", f->CanId, 178 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3]); 179 | break; 180 | case 5: 181 | sprintf(str, "T%08x%d%02x%02x%02x%02x%02x\r" , f->CanId, 182 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3], 183 | f->Data[4]); 184 | break; 185 | case 6: 186 | sprintf(str, "T%08x%d%02x%02x%02x%02x%02x%02x\r", f->CanId, 187 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3], 188 | f->Data[4], f->Data[5]); 189 | break; 190 | case 7: 191 | sprintf(str, "T%08x%d%02x%02x%02x%02x%02x%02x%02x\r", f->CanId, 192 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3], 193 | f->Data[4], f->Data[5], f->Data[6]); 194 | break; 195 | case 8: 196 | sprintf(str, "T%08x%d%02x%02x%02x%02x%02x%02x%02x%02x\r", f->CanId, 197 | f->DLC, f->Data[0], f->Data[1], f->Data[2], f->Data[3], 198 | f->Data[4], f->Data[5], f->Data[6], f->Data[7]); 199 | break; 200 | } 201 | } 202 | } 203 | if (str != NULL) { 204 | // ESP_LOGI(MAIN_TAG, "%s", str); 205 | send_to_cdc(str, char_len - 1); 206 | } 207 | } 208 | 209 | void init_sl_can() { 210 | set_cb(&frame_rx_cb); 211 | } 212 | 213 | void sl_set_speed(char num) { 214 | switch (num) { 215 | case '0': 216 | baud = (long)10E3; 217 | break; 218 | case '1': 219 | baud = (long)20E3; 220 | break; 221 | case '2': 222 | baud = (long)50E3; 223 | break; 224 | case '3': 225 | baud = (long)100E3; 226 | break; 227 | case '4': 228 | baud = (long)125E3; 229 | break; 230 | case '5': 231 | baud = (long)250E3; 232 | break; 233 | case '6': 234 | baud = (long)500E3; 235 | break; 236 | case '7': 237 | baud = (long)800E3; 238 | break; 239 | case '8': 240 | baud = (long)1000E3; 241 | break; 242 | } 243 | } 244 | 245 | void receive_cmd(uint8_t *cmd, uint32_t len) { 246 | switch (cmd[0]) { 247 | case 'V': 248 | send_to_cdc(SLCAN_VERSION, 5); 249 | ESP_LOGI(MAIN_TAG, "V"); 250 | break; 251 | case 'v': 252 | ESP_LOGI(MAIN_TAG, "v"); 253 | send_to_cdc(SLCAN_DEV, 7); 254 | break; 255 | case 'S': 256 | ESP_LOGI(MAIN_TAG, "S"); 257 | send_to_cdc(OK_R, 1); 258 | sl_set_speed(cmd[1]); 259 | break; 260 | case 'O': 261 | ESP_LOGI(MAIN_TAG, "O"); 262 | send_to_cdc(OK_R, 1); 263 | init_mcp(baud, OPEN_MODE); 264 | break; 265 | case 'L': 266 | ESP_LOGI(MAIN_TAG, "L"); 267 | send_to_cdc(OK_R, 1); 268 | init_mcp(baud, LOOPBACK_MODE); 269 | break; 270 | case 'C': 271 | ESP_LOGI(MAIN_TAG, "C"); 272 | send_to_cdc(OK_R, 1); 273 | reset_mcp(); 274 | break; 275 | case 't': 276 | ESP_LOGI(MAIN_TAG, "t"); 277 | send_to_cdc(OK_R, 1); 278 | frame_tx_cb(cmd, len); 279 | case 'T': 280 | ESP_LOGI(MAIN_TAG, "T"); 281 | send_to_cdc(OK_R, 1); 282 | frame_ext_tx_cb(cmd, len); 283 | break; 284 | default: 285 | send_to_cdc(OK_R, 1); 286 | } 287 | } 288 | 289 | -------------------------------------------------------------------------------- /bt_can_spp/main/sl_can_proto.h: -------------------------------------------------------------------------------- 1 | #ifndef SL_CAN_PROTO_H__ 2 | #define SL_CAN_PROTO_H__ 3 | 4 | #include 5 | #include 6 | #include "esp_err.h" 7 | 8 | typedef struct CDCResponse { 9 | uint32_t length; 10 | char *response; 11 | } cdc_response; 12 | 13 | 14 | void receive_cmd(uint8_t *cmd, uint32_t len); 15 | void init_sl_can(); 16 | 17 | #endif -------------------------------------------------------------------------------- /bt_can_spp/sdkconfig: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated file; DO NOT EDIT. 3 | # Espressif IoT Development Framework Configuration 4 | # 5 | 6 | # 7 | # SDK tool configuration 8 | # 9 | CONFIG_TOOLPREFIX="xtensa-esp32-elf-" 10 | CONFIG_PYTHON="python2" 11 | CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y 12 | 13 | # 14 | # Bootloader config 15 | # 16 | CONFIG_LOG_BOOTLOADER_LEVEL_NONE= 17 | CONFIG_LOG_BOOTLOADER_LEVEL_ERROR= 18 | CONFIG_LOG_BOOTLOADER_LEVEL_WARN= 19 | CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y 20 | CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG= 21 | CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE= 22 | CONFIG_LOG_BOOTLOADER_LEVEL=3 23 | CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V= 24 | CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y 25 | CONFIG_BOOTLOADER_FACTORY_RESET= 26 | CONFIG_BOOTLOADER_APP_TEST= 27 | 28 | # 29 | # Security features 30 | # 31 | CONFIG_SECURE_BOOT_ENABLED= 32 | CONFIG_FLASH_ENCRYPTION_ENABLED= 33 | 34 | # 35 | # Serial flasher config 36 | # 37 | CONFIG_ESPTOOLPY_PORT="/dev/ttyUSB0" 38 | CONFIG_ESPTOOLPY_BAUD_115200B=y 39 | CONFIG_ESPTOOLPY_BAUD_230400B= 40 | CONFIG_ESPTOOLPY_BAUD_921600B= 41 | CONFIG_ESPTOOLPY_BAUD_2MB= 42 | CONFIG_ESPTOOLPY_BAUD_OTHER= 43 | CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 44 | CONFIG_ESPTOOLPY_BAUD=115200 45 | CONFIG_ESPTOOLPY_COMPRESSED=y 46 | CONFIG_FLASHMODE_QIO= 47 | CONFIG_FLASHMODE_QOUT= 48 | CONFIG_FLASHMODE_DIO=y 49 | CONFIG_FLASHMODE_DOUT= 50 | CONFIG_ESPTOOLPY_FLASHMODE="dio" 51 | CONFIG_ESPTOOLPY_FLASHFREQ_80M= 52 | CONFIG_ESPTOOLPY_FLASHFREQ_40M=y 53 | CONFIG_ESPTOOLPY_FLASHFREQ_26M= 54 | CONFIG_ESPTOOLPY_FLASHFREQ_20M= 55 | CONFIG_ESPTOOLPY_FLASHFREQ="40m" 56 | CONFIG_ESPTOOLPY_FLASHSIZE_1MB= 57 | CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y 58 | CONFIG_ESPTOOLPY_FLASHSIZE_4MB= 59 | CONFIG_ESPTOOLPY_FLASHSIZE_8MB= 60 | CONFIG_ESPTOOLPY_FLASHSIZE_16MB= 61 | CONFIG_ESPTOOLPY_FLASHSIZE="2MB" 62 | CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y 63 | CONFIG_ESPTOOLPY_BEFORE_RESET=y 64 | CONFIG_ESPTOOLPY_BEFORE_NORESET= 65 | CONFIG_ESPTOOLPY_BEFORE="default_reset" 66 | CONFIG_ESPTOOLPY_AFTER_RESET=y 67 | CONFIG_ESPTOOLPY_AFTER_NORESET= 68 | CONFIG_ESPTOOLPY_AFTER="hard_reset" 69 | CONFIG_MONITOR_BAUD_9600B= 70 | CONFIG_MONITOR_BAUD_57600B= 71 | CONFIG_MONITOR_BAUD_115200B=y 72 | CONFIG_MONITOR_BAUD_230400B= 73 | CONFIG_MONITOR_BAUD_921600B= 74 | CONFIG_MONITOR_BAUD_2MB= 75 | CONFIG_MONITOR_BAUD_OTHER= 76 | CONFIG_MONITOR_BAUD_OTHER_VAL=115200 77 | CONFIG_MONITOR_BAUD=115200 78 | 79 | # 80 | # Partition Table 81 | # 82 | CONFIG_PARTITION_TABLE_SINGLE_APP=y 83 | CONFIG_PARTITION_TABLE_TWO_OTA= 84 | CONFIG_PARTITION_TABLE_CUSTOM= 85 | CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" 86 | CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" 87 | CONFIG_PARTITION_TABLE_OFFSET=0x8000 88 | CONFIG_PARTITION_TABLE_MD5=y 89 | 90 | # 91 | # Compiler options 92 | # 93 | CONFIG_OPTIMIZATION_LEVEL_DEBUG= 94 | CONFIG_OPTIMIZATION_LEVEL_RELEASE=y 95 | CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y 96 | CONFIG_OPTIMIZATION_ASSERTIONS_SILENT= 97 | CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED= 98 | CONFIG_CXX_EXCEPTIONS= 99 | CONFIG_STACK_CHECK_NONE=y 100 | CONFIG_STACK_CHECK_NORM= 101 | CONFIG_STACK_CHECK_STRONG= 102 | CONFIG_STACK_CHECK_ALL= 103 | CONFIG_STACK_CHECK= 104 | CONFIG_WARN_WRITE_STRINGS= 105 | 106 | # 107 | # Component config 108 | # 109 | 110 | # 111 | # Application Level Tracing 112 | # 113 | CONFIG_ESP32_APPTRACE_DEST_TRAX= 114 | CONFIG_ESP32_APPTRACE_DEST_NONE=y 115 | CONFIG_ESP32_APPTRACE_ENABLE= 116 | CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y 117 | CONFIG_AWS_IOT_SDK= 118 | 119 | # 120 | # Bluetooth 121 | # 122 | CONFIG_BT_ENABLED=y 123 | CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_0=y 124 | CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_1= 125 | CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 126 | CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y 127 | CONFIG_BTDM_CONTROLLER_HCI_MODE_UART_H4= 128 | 129 | # 130 | # MODEM SLEEP Options 131 | # 132 | CONFIG_BTDM_CONTROLLER_MODEM_SLEEP= 133 | CONFIG_BLUEDROID_ENABLED=y 134 | CONFIG_BLUEDROID_PINNED_TO_CORE_0=y 135 | CONFIG_BLUEDROID_PINNED_TO_CORE_1= 136 | CONFIG_BLUEDROID_PINNED_TO_CORE=0 137 | CONFIG_BTC_TASK_STACK_SIZE=3072 138 | CONFIG_BLUEDROID_MEM_DEBUG= 139 | CONFIG_CLASSIC_BT_ENABLED=y 140 | CONFIG_A2DP_ENABLE= 141 | CONFIG_BT_SPP_ENABLED=y 142 | CONFIG_HFP_ENABLE= 143 | CONFIG_GATTS_ENABLE=y 144 | CONFIG_GATTC_ENABLE=y 145 | CONFIG_GATTC_CACHE_NVS_FLASH= 146 | CONFIG_BLE_SMP_ENABLE=y 147 | CONFIG_BT_STACK_NO_LOG= 148 | 149 | # 150 | # BT DEBUG LOG LEVEL 151 | # 152 | CONFIG_HCI_TRACE_LEVEL_NONE= 153 | CONFIG_HCI_TRACE_LEVEL_ERROR= 154 | CONFIG_HCI_TRACE_LEVEL_WARNING=y 155 | CONFIG_HCI_TRACE_LEVEL_API= 156 | CONFIG_HCI_TRACE_LEVEL_EVENT= 157 | CONFIG_HCI_TRACE_LEVEL_DEBUG= 158 | CONFIG_HCI_TRACE_LEVEL_VERBOSE= 159 | CONFIG_HCI_INITIAL_TRACE_LEVEL=2 160 | CONFIG_BTM_TRACE_LEVEL_NONE= 161 | CONFIG_BTM_TRACE_LEVEL_ERROR= 162 | CONFIG_BTM_TRACE_LEVEL_WARNING=y 163 | CONFIG_BTM_TRACE_LEVEL_API= 164 | CONFIG_BTM_TRACE_LEVEL_EVENT= 165 | CONFIG_BTM_TRACE_LEVEL_DEBUG= 166 | CONFIG_BTM_TRACE_LEVEL_VERBOSE= 167 | CONFIG_BTM_INITIAL_TRACE_LEVEL=2 168 | CONFIG_L2CAP_TRACE_LEVEL_NONE= 169 | CONFIG_L2CAP_TRACE_LEVEL_ERROR= 170 | CONFIG_L2CAP_TRACE_LEVEL_WARNING=y 171 | CONFIG_L2CAP_TRACE_LEVEL_API= 172 | CONFIG_L2CAP_TRACE_LEVEL_EVENT= 173 | CONFIG_L2CAP_TRACE_LEVEL_DEBUG= 174 | CONFIG_L2CAP_TRACE_LEVEL_VERBOSE= 175 | CONFIG_L2CAP_INITIAL_TRACE_LEVEL=2 176 | CONFIG_RFCOMM_TRACE_LEVEL_NONE= 177 | CONFIG_RFCOMM_TRACE_LEVEL_ERROR= 178 | CONFIG_RFCOMM_TRACE_LEVEL_WARNING=y 179 | CONFIG_RFCOMM_TRACE_LEVEL_API= 180 | CONFIG_RFCOMM_TRACE_LEVEL_EVENT= 181 | CONFIG_RFCOMM_TRACE_LEVEL_DEBUG= 182 | CONFIG_RFCOMM_TRACE_LEVEL_VERBOSE= 183 | CONFIG_RFCOMM_INITIAL_TRACE_LEVEL=2 184 | CONFIG_SDP_TRACE_LEVEL_NONE= 185 | CONFIG_SDP_TRACE_LEVEL_ERROR= 186 | CONFIG_SDP_TRACE_LEVEL_WARNING=y 187 | CONFIG_SDP_TRACE_LEVEL_API= 188 | CONFIG_SDP_TRACE_LEVEL_EVENT= 189 | CONFIG_SDP_TRACE_LEVEL_DEBUG= 190 | CONFIG_SDP_TRACE_LEVEL_VERBOSE= 191 | CONFIG_SDP_INITIAL_TRACE_LEVEL=2 192 | CONFIG_GAP_TRACE_LEVEL_NONE= 193 | CONFIG_GAP_TRACE_LEVEL_ERROR= 194 | CONFIG_GAP_TRACE_LEVEL_WARNING=y 195 | CONFIG_GAP_TRACE_LEVEL_API= 196 | CONFIG_GAP_TRACE_LEVEL_EVENT= 197 | CONFIG_GAP_TRACE_LEVEL_DEBUG= 198 | CONFIG_GAP_TRACE_LEVEL_VERBOSE= 199 | CONFIG_GAP_INITIAL_TRACE_LEVEL=2 200 | CONFIG_BNEP_TRACE_LEVEL_NONE= 201 | CONFIG_BNEP_TRACE_LEVEL_ERROR= 202 | CONFIG_BNEP_TRACE_LEVEL_WARNING=y 203 | CONFIG_BNEP_TRACE_LEVEL_API= 204 | CONFIG_BNEP_TRACE_LEVEL_EVENT= 205 | CONFIG_BNEP_TRACE_LEVEL_DEBUG= 206 | CONFIG_BNEP_TRACE_LEVEL_VERBOSE= 207 | CONFIG_BNEP_INITIAL_TRACE_LEVEL=2 208 | CONFIG_PAN_TRACE_LEVEL_NONE= 209 | CONFIG_PAN_TRACE_LEVEL_ERROR= 210 | CONFIG_PAN_TRACE_LEVEL_WARNING=y 211 | CONFIG_PAN_TRACE_LEVEL_API= 212 | CONFIG_PAN_TRACE_LEVEL_EVENT= 213 | CONFIG_PAN_TRACE_LEVEL_DEBUG= 214 | CONFIG_PAN_TRACE_LEVEL_VERBOSE= 215 | CONFIG_PAN_INITIAL_TRACE_LEVEL=2 216 | CONFIG_A2D_TRACE_LEVEL_NONE= 217 | CONFIG_A2D_TRACE_LEVEL_ERROR= 218 | CONFIG_A2D_TRACE_LEVEL_WARNING=y 219 | CONFIG_A2D_TRACE_LEVEL_API= 220 | CONFIG_A2D_TRACE_LEVEL_EVENT= 221 | CONFIG_A2D_TRACE_LEVEL_DEBUG= 222 | CONFIG_A2D_TRACE_LEVEL_VERBOSE= 223 | CONFIG_A2D_INITIAL_TRACE_LEVEL=2 224 | CONFIG_AVDT_TRACE_LEVEL_NONE= 225 | CONFIG_AVDT_TRACE_LEVEL_ERROR= 226 | CONFIG_AVDT_TRACE_LEVEL_WARNING=y 227 | CONFIG_AVDT_TRACE_LEVEL_API= 228 | CONFIG_AVDT_TRACE_LEVEL_EVENT= 229 | CONFIG_AVDT_TRACE_LEVEL_DEBUG= 230 | CONFIG_AVDT_TRACE_LEVEL_VERBOSE= 231 | CONFIG_AVDT_INITIAL_TRACE_LEVEL=2 232 | CONFIG_AVCT_TRACE_LEVEL_NONE= 233 | CONFIG_AVCT_TRACE_LEVEL_ERROR= 234 | CONFIG_AVCT_TRACE_LEVEL_WARNING=y 235 | CONFIG_AVCT_TRACE_LEVEL_API= 236 | CONFIG_AVCT_TRACE_LEVEL_EVENT= 237 | CONFIG_AVCT_TRACE_LEVEL_DEBUG= 238 | CONFIG_AVCT_TRACE_LEVEL_VERBOSE= 239 | CONFIG_AVCT_INITIAL_TRACE_LEVEL=2 240 | CONFIG_AVRC_TRACE_LEVEL_NONE= 241 | CONFIG_AVRC_TRACE_LEVEL_ERROR= 242 | CONFIG_AVRC_TRACE_LEVEL_WARNING=y 243 | CONFIG_AVRC_TRACE_LEVEL_API= 244 | CONFIG_AVRC_TRACE_LEVEL_EVENT= 245 | CONFIG_AVRC_TRACE_LEVEL_DEBUG= 246 | CONFIG_AVRC_TRACE_LEVEL_VERBOSE= 247 | CONFIG_AVRC_INITIAL_TRACE_LEVEL=2 248 | CONFIG_MCA_TRACE_LEVEL_NONE= 249 | CONFIG_MCA_TRACE_LEVEL_ERROR= 250 | CONFIG_MCA_TRACE_LEVEL_WARNING=y 251 | CONFIG_MCA_TRACE_LEVEL_API= 252 | CONFIG_MCA_TRACE_LEVEL_EVENT= 253 | CONFIG_MCA_TRACE_LEVEL_DEBUG= 254 | CONFIG_MCA_TRACE_LEVEL_VERBOSE= 255 | CONFIG_MCA_INITIAL_TRACE_LEVEL=2 256 | CONFIG_HID_TRACE_LEVEL_NONE= 257 | CONFIG_HID_TRACE_LEVEL_ERROR= 258 | CONFIG_HID_TRACE_LEVEL_WARNING=y 259 | CONFIG_HID_TRACE_LEVEL_API= 260 | CONFIG_HID_TRACE_LEVEL_EVENT= 261 | CONFIG_HID_TRACE_LEVEL_DEBUG= 262 | CONFIG_HID_TRACE_LEVEL_VERBOSE= 263 | CONFIG_HID_INITIAL_TRACE_LEVEL=2 264 | CONFIG_APPL_TRACE_LEVEL_NONE= 265 | CONFIG_APPL_TRACE_LEVEL_ERROR= 266 | CONFIG_APPL_TRACE_LEVEL_WARNING=y 267 | CONFIG_APPL_TRACE_LEVEL_API= 268 | CONFIG_APPL_TRACE_LEVEL_EVENT= 269 | CONFIG_APPL_TRACE_LEVEL_DEBUG= 270 | CONFIG_APPL_TRACE_LEVEL_VERBOSE= 271 | CONFIG_APPL_INITIAL_TRACE_LEVEL=2 272 | CONFIG_GATT_TRACE_LEVEL_NONE= 273 | CONFIG_GATT_TRACE_LEVEL_ERROR= 274 | CONFIG_GATT_TRACE_LEVEL_WARNING=y 275 | CONFIG_GATT_TRACE_LEVEL_API= 276 | CONFIG_GATT_TRACE_LEVEL_EVENT= 277 | CONFIG_GATT_TRACE_LEVEL_DEBUG= 278 | CONFIG_GATT_TRACE_LEVEL_VERBOSE= 279 | CONFIG_GATT_INITIAL_TRACE_LEVEL=2 280 | CONFIG_SMP_TRACE_LEVEL_NONE= 281 | CONFIG_SMP_TRACE_LEVEL_ERROR= 282 | CONFIG_SMP_TRACE_LEVEL_WARNING=y 283 | CONFIG_SMP_TRACE_LEVEL_API= 284 | CONFIG_SMP_TRACE_LEVEL_EVENT= 285 | CONFIG_SMP_TRACE_LEVEL_DEBUG= 286 | CONFIG_SMP_TRACE_LEVEL_VERBOSE= 287 | CONFIG_SMP_INITIAL_TRACE_LEVEL=2 288 | CONFIG_BTIF_TRACE_LEVEL_NONE= 289 | CONFIG_BTIF_TRACE_LEVEL_ERROR= 290 | CONFIG_BTIF_TRACE_LEVEL_WARNING=y 291 | CONFIG_BTIF_TRACE_LEVEL_API= 292 | CONFIG_BTIF_TRACE_LEVEL_EVENT= 293 | CONFIG_BTIF_TRACE_LEVEL_DEBUG= 294 | CONFIG_BTIF_TRACE_LEVEL_VERBOSE= 295 | CONFIG_BTIF_INITIAL_TRACE_LEVEL=2 296 | CONFIG_BTC_TRACE_LEVEL_NONE= 297 | CONFIG_BTC_TRACE_LEVEL_ERROR= 298 | CONFIG_BTC_TRACE_LEVEL_WARNING=y 299 | CONFIG_BTC_TRACE_LEVEL_API= 300 | CONFIG_BTC_TRACE_LEVEL_EVENT= 301 | CONFIG_BTC_TRACE_LEVEL_DEBUG= 302 | CONFIG_BTC_TRACE_LEVEL_VERBOSE= 303 | CONFIG_BTC_INITIAL_TRACE_LEVEL=2 304 | CONFIG_OSI_TRACE_LEVEL_NONE= 305 | CONFIG_OSI_TRACE_LEVEL_ERROR= 306 | CONFIG_OSI_TRACE_LEVEL_WARNING=y 307 | CONFIG_OSI_TRACE_LEVEL_API= 308 | CONFIG_OSI_TRACE_LEVEL_EVENT= 309 | CONFIG_OSI_TRACE_LEVEL_DEBUG= 310 | CONFIG_OSI_TRACE_LEVEL_VERBOSE= 311 | CONFIG_OSI_INITIAL_TRACE_LEVEL=2 312 | CONFIG_BLUFI_TRACE_LEVEL_NONE= 313 | CONFIG_BLUFI_TRACE_LEVEL_ERROR= 314 | CONFIG_BLUFI_TRACE_LEVEL_WARNING=y 315 | CONFIG_BLUFI_TRACE_LEVEL_API= 316 | CONFIG_BLUFI_TRACE_LEVEL_EVENT= 317 | CONFIG_BLUFI_TRACE_LEVEL_DEBUG= 318 | CONFIG_BLUFI_TRACE_LEVEL_VERBOSE= 319 | CONFIG_BLUFI_INITIAL_TRACE_LEVEL=2 320 | CONFIG_BT_ACL_CONNECTIONS=4 321 | CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST= 322 | CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY= 323 | CONFIG_BLE_SCAN_DUPLICATE=y 324 | CONFIG_DUPLICATE_SCAN_CACHE_SIZE=20 325 | CONFIG_BLE_MESH_SCAN_DUPLICATE_EN= 326 | CONFIG_SMP_ENABLE=y 327 | CONFIG_BT_RESERVE_DRAM=0x10000 328 | 329 | # 330 | # Driver configurations 331 | # 332 | 333 | # 334 | # ADC configuration 335 | # 336 | CONFIG_ADC_FORCE_XPD_FSM= 337 | CONFIG_ADC2_DISABLE_DAC=y 338 | 339 | # 340 | # SPI master configuration 341 | # 342 | CONFIG_SPI_MASTER_IN_IRAM= 343 | CONFIG_SPI_MASTER_ISR_IN_IRAM=y 344 | 345 | # 346 | # ESP32-specific 347 | # 348 | CONFIG_ESP32_DEFAULT_CPU_FREQ_80= 349 | CONFIG_ESP32_DEFAULT_CPU_FREQ_160= 350 | CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y 351 | CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 352 | CONFIG_SPIRAM_SUPPORT= 353 | CONFIG_MEMMAP_TRACEMEM= 354 | CONFIG_MEMMAP_TRACEMEM_TWOBANKS= 355 | CONFIG_ESP32_TRAX= 356 | CONFIG_TRACEMEM_RESERVE_DRAM=0x0 357 | CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH= 358 | CONFIG_ESP32_ENABLE_COREDUMP_TO_UART= 359 | CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y 360 | CONFIG_ESP32_ENABLE_COREDUMP= 361 | CONFIG_TWO_UNIVERSAL_MAC_ADDRESS= 362 | CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y 363 | CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 364 | CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 365 | CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 366 | CONFIG_MAIN_TASK_STACK_SIZE=3584 367 | CONFIG_IPC_TASK_STACK_SIZE=1024 368 | CONFIG_TIMER_TASK_STACK_SIZE=3584 369 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y 370 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF= 371 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR= 372 | CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF= 373 | CONFIG_NEWLIB_STDIN_LINE_ENDING_LF= 374 | CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y 375 | CONFIG_NEWLIB_NANO_FORMAT= 376 | CONFIG_CONSOLE_UART_DEFAULT=y 377 | CONFIG_CONSOLE_UART_CUSTOM= 378 | CONFIG_CONSOLE_UART_NONE= 379 | CONFIG_CONSOLE_UART_NUM=0 380 | CONFIG_CONSOLE_UART_BAUDRATE=115200 381 | CONFIG_ULP_COPROC_ENABLED= 382 | CONFIG_ULP_COPROC_RESERVE_MEM=0 383 | CONFIG_ESP32_PANIC_PRINT_HALT= 384 | CONFIG_ESP32_PANIC_PRINT_REBOOT=y 385 | CONFIG_ESP32_PANIC_SILENT_REBOOT= 386 | CONFIG_ESP32_PANIC_GDBSTUB= 387 | CONFIG_ESP32_DEBUG_OCDAWARE=y 388 | CONFIG_ESP32_DEBUG_STUBS_ENABLE=y 389 | CONFIG_INT_WDT=y 390 | CONFIG_INT_WDT_TIMEOUT_MS=300 391 | CONFIG_INT_WDT_CHECK_CPU1=y 392 | CONFIG_TASK_WDT=y 393 | CONFIG_TASK_WDT_PANIC= 394 | CONFIG_TASK_WDT_TIMEOUT_S=5 395 | CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y 396 | CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y 397 | CONFIG_BROWNOUT_DET=y 398 | CONFIG_BROWNOUT_DET_LVL_SEL_0=y 399 | CONFIG_BROWNOUT_DET_LVL_SEL_1= 400 | CONFIG_BROWNOUT_DET_LVL_SEL_2= 401 | CONFIG_BROWNOUT_DET_LVL_SEL_3= 402 | CONFIG_BROWNOUT_DET_LVL_SEL_4= 403 | CONFIG_BROWNOUT_DET_LVL_SEL_5= 404 | CONFIG_BROWNOUT_DET_LVL_SEL_6= 405 | CONFIG_BROWNOUT_DET_LVL_SEL_7= 406 | CONFIG_BROWNOUT_DET_LVL=0 407 | CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y 408 | CONFIG_ESP32_TIME_SYSCALL_USE_RTC= 409 | CONFIG_ESP32_TIME_SYSCALL_USE_FRC1= 410 | CONFIG_ESP32_TIME_SYSCALL_USE_NONE= 411 | CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y 412 | CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL= 413 | CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 414 | CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 415 | CONFIG_ESP32_XTAL_FREQ_40=y 416 | CONFIG_ESP32_XTAL_FREQ_26= 417 | CONFIG_ESP32_XTAL_FREQ_AUTO= 418 | CONFIG_ESP32_XTAL_FREQ=40 419 | CONFIG_DISABLE_BASIC_ROM_CONSOLE= 420 | CONFIG_ESP_TIMER_PROFILING= 421 | CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= 422 | CONFIG_ESP_ERR_TO_NAME_LOOKUP=y 423 | 424 | # 425 | # Wi-Fi 426 | # 427 | CONFIG_SW_COEXIST_ENABLE=y 428 | CONFIG_SW_COEXIST_PREFERENCE_WIFI= 429 | CONFIG_SW_COEXIST_PREFERENCE_BT= 430 | CONFIG_SW_COEXIST_PREFERENCE_BALANCE=y 431 | CONFIG_SW_COEXIST_PREFERENCE_VALUE=2 432 | CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 433 | CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 434 | CONFIG_ESP32_WIFI_STATIC_TX_BUFFER= 435 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y 436 | CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 437 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 438 | CONFIG_ESP32_WIFI_CSI_ENABLED= 439 | CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y 440 | CONFIG_ESP32_WIFI_TX_BA_WIN=6 441 | CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y 442 | CONFIG_ESP32_WIFI_RX_BA_WIN=6 443 | CONFIG_ESP32_WIFI_NVS_ENABLED=y 444 | CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y 445 | CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1= 446 | 447 | # 448 | # PHY 449 | # 450 | CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y 451 | CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION= 452 | CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 453 | CONFIG_ESP32_PHY_MAX_TX_POWER=20 454 | 455 | # 456 | # Power Management 457 | # 458 | CONFIG_PM_ENABLE= 459 | 460 | # 461 | # ADC-Calibration 462 | # 463 | CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y 464 | CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y 465 | CONFIG_ADC_CAL_LUT_ENABLE=y 466 | 467 | # 468 | # ESP HTTP client 469 | # 470 | CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y 471 | 472 | # 473 | # Ethernet 474 | # 475 | CONFIG_DMA_RX_BUF_NUM=10 476 | CONFIG_DMA_TX_BUF_NUM=10 477 | CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE= 478 | CONFIG_EMAC_TASK_PRIORITY=20 479 | 480 | # 481 | # FAT Filesystem support 482 | # 483 | CONFIG_FATFS_CODEPAGE_DYNAMIC= 484 | CONFIG_FATFS_CODEPAGE_437=y 485 | CONFIG_FATFS_CODEPAGE_720= 486 | CONFIG_FATFS_CODEPAGE_737= 487 | CONFIG_FATFS_CODEPAGE_771= 488 | CONFIG_FATFS_CODEPAGE_775= 489 | CONFIG_FATFS_CODEPAGE_850= 490 | CONFIG_FATFS_CODEPAGE_852= 491 | CONFIG_FATFS_CODEPAGE_855= 492 | CONFIG_FATFS_CODEPAGE_857= 493 | CONFIG_FATFS_CODEPAGE_860= 494 | CONFIG_FATFS_CODEPAGE_861= 495 | CONFIG_FATFS_CODEPAGE_862= 496 | CONFIG_FATFS_CODEPAGE_863= 497 | CONFIG_FATFS_CODEPAGE_864= 498 | CONFIG_FATFS_CODEPAGE_865= 499 | CONFIG_FATFS_CODEPAGE_866= 500 | CONFIG_FATFS_CODEPAGE_869= 501 | CONFIG_FATFS_CODEPAGE_932= 502 | CONFIG_FATFS_CODEPAGE_936= 503 | CONFIG_FATFS_CODEPAGE_949= 504 | CONFIG_FATFS_CODEPAGE_950= 505 | CONFIG_FATFS_CODEPAGE=437 506 | CONFIG_FATFS_LFN_NONE=y 507 | CONFIG_FATFS_LFN_HEAP= 508 | CONFIG_FATFS_LFN_STACK= 509 | CONFIG_FATFS_FS_LOCK=0 510 | CONFIG_FATFS_TIMEOUT_MS=10000 511 | CONFIG_FATFS_PER_FILE_CACHE=y 512 | 513 | # 514 | # FreeRTOS 515 | # 516 | CONFIG_FREERTOS_UNICORE= 517 | CONFIG_FREERTOS_CORETIMER_0=y 518 | CONFIG_FREERTOS_CORETIMER_1= 519 | CONFIG_FREERTOS_HZ=1000 520 | CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y 521 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE= 522 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL= 523 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y 524 | CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK= 525 | CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y 526 | CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 527 | CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y 528 | CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE= 529 | CONFIG_FREERTOS_ASSERT_DISABLE= 530 | CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 531 | CONFIG_FREERTOS_ISR_STACKSIZE=1536 532 | CONFIG_FREERTOS_LEGACY_HOOKS= 533 | CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 534 | CONFIG_SUPPORT_STATIC_ALLOCATION= 535 | CONFIG_TIMER_TASK_PRIORITY=1 536 | CONFIG_TIMER_TASK_STACK_DEPTH=2048 537 | CONFIG_TIMER_QUEUE_LENGTH=10 538 | CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 539 | CONFIG_FREERTOS_USE_TRACE_FACILITY= 540 | CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS= 541 | CONFIG_FREERTOS_DEBUG_INTERNALS= 542 | 543 | # 544 | # Heap memory debugging 545 | # 546 | CONFIG_HEAP_POISONING_DISABLED=y 547 | CONFIG_HEAP_POISONING_LIGHT= 548 | CONFIG_HEAP_POISONING_COMPREHENSIVE= 549 | CONFIG_HEAP_TRACING= 550 | 551 | # 552 | # libsodium 553 | # 554 | CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y 555 | 556 | # 557 | # Log output 558 | # 559 | CONFIG_LOG_DEFAULT_LEVEL_NONE= 560 | CONFIG_LOG_DEFAULT_LEVEL_ERROR= 561 | CONFIG_LOG_DEFAULT_LEVEL_WARN= 562 | CONFIG_LOG_DEFAULT_LEVEL_INFO=y 563 | CONFIG_LOG_DEFAULT_LEVEL_DEBUG= 564 | CONFIG_LOG_DEFAULT_LEVEL_VERBOSE= 565 | CONFIG_LOG_DEFAULT_LEVEL=3 566 | CONFIG_LOG_COLORS=y 567 | 568 | # 569 | # LWIP 570 | # 571 | CONFIG_L2_TO_L3_COPY= 572 | CONFIG_LWIP_IRAM_OPTIMIZATION= 573 | CONFIG_LWIP_MAX_SOCKETS=10 574 | CONFIG_USE_ONLY_LWIP_SELECT= 575 | CONFIG_LWIP_SO_REUSE=y 576 | CONFIG_LWIP_SO_REUSE_RXTOALL=y 577 | CONFIG_LWIP_SO_RCVBUF= 578 | CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 579 | CONFIG_LWIP_IP_FRAG= 580 | CONFIG_LWIP_IP_REASSEMBLY= 581 | CONFIG_LWIP_STATS= 582 | CONFIG_LWIP_ETHARP_TRUST_IP_MAC=y 583 | CONFIG_TCPIP_RECVMBOX_SIZE=32 584 | CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y 585 | 586 | # 587 | # DHCP server 588 | # 589 | CONFIG_LWIP_DHCPS_LEASE_UNIT=60 590 | CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 591 | CONFIG_LWIP_AUTOIP= 592 | CONFIG_LWIP_NETIF_LOOPBACK=y 593 | CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 594 | 595 | # 596 | # TCP 597 | # 598 | CONFIG_LWIP_MAX_ACTIVE_TCP=16 599 | CONFIG_LWIP_MAX_LISTENING_TCP=16 600 | CONFIG_TCP_MAXRTX=12 601 | CONFIG_TCP_SYNMAXRTX=6 602 | CONFIG_TCP_MSS=1436 603 | CONFIG_TCP_MSL=60000 604 | CONFIG_TCP_SND_BUF_DEFAULT=5744 605 | CONFIG_TCP_WND_DEFAULT=5744 606 | CONFIG_TCP_RECVMBOX_SIZE=6 607 | CONFIG_TCP_QUEUE_OOSEQ=y 608 | CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES= 609 | CONFIG_TCP_OVERSIZE_MSS=y 610 | CONFIG_TCP_OVERSIZE_QUARTER_MSS= 611 | CONFIG_TCP_OVERSIZE_DISABLE= 612 | 613 | # 614 | # UDP 615 | # 616 | CONFIG_LWIP_MAX_UDP_PCBS=16 617 | CONFIG_UDP_RECVMBOX_SIZE=6 618 | CONFIG_TCPIP_TASK_STACK_SIZE=2048 619 | CONFIG_PPP_SUPPORT= 620 | 621 | # 622 | # ICMP 623 | # 624 | CONFIG_LWIP_MULTICAST_PING= 625 | CONFIG_LWIP_BROADCAST_PING= 626 | 627 | # 628 | # LWIP RAW API 629 | # 630 | CONFIG_LWIP_MAX_RAW_PCBS=16 631 | 632 | # 633 | # mbedTLS 634 | # 635 | CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 636 | CONFIG_MBEDTLS_DEBUG= 637 | CONFIG_MBEDTLS_HARDWARE_AES=y 638 | CONFIG_MBEDTLS_HARDWARE_MPI= 639 | CONFIG_MBEDTLS_HARDWARE_SHA= 640 | CONFIG_MBEDTLS_HAVE_TIME=y 641 | CONFIG_MBEDTLS_HAVE_TIME_DATE= 642 | CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y 643 | CONFIG_MBEDTLS_TLS_SERVER_ONLY= 644 | CONFIG_MBEDTLS_TLS_CLIENT_ONLY= 645 | CONFIG_MBEDTLS_TLS_DISABLED= 646 | CONFIG_MBEDTLS_TLS_SERVER=y 647 | CONFIG_MBEDTLS_TLS_CLIENT=y 648 | CONFIG_MBEDTLS_TLS_ENABLED=y 649 | 650 | # 651 | # TLS Key Exchange Methods 652 | # 653 | CONFIG_MBEDTLS_PSK_MODES= 654 | CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y 655 | CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y 656 | CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y 657 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y 658 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y 659 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y 660 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y 661 | CONFIG_MBEDTLS_SSL_RENEGOTIATION=y 662 | CONFIG_MBEDTLS_SSL_PROTO_SSL3= 663 | CONFIG_MBEDTLS_SSL_PROTO_TLS1=y 664 | CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y 665 | CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y 666 | CONFIG_MBEDTLS_SSL_PROTO_DTLS= 667 | CONFIG_MBEDTLS_SSL_ALPN=y 668 | CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y 669 | 670 | # 671 | # Symmetric Ciphers 672 | # 673 | CONFIG_MBEDTLS_AES_C=y 674 | CONFIG_MBEDTLS_CAMELLIA_C= 675 | CONFIG_MBEDTLS_DES_C= 676 | CONFIG_MBEDTLS_RC4_DISABLED=y 677 | CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT= 678 | CONFIG_MBEDTLS_RC4_ENABLED= 679 | CONFIG_MBEDTLS_BLOWFISH_C= 680 | CONFIG_MBEDTLS_XTEA_C= 681 | CONFIG_MBEDTLS_CCM_C=y 682 | CONFIG_MBEDTLS_GCM_C=y 683 | CONFIG_MBEDTLS_RIPEMD160_C= 684 | 685 | # 686 | # Certificates 687 | # 688 | CONFIG_MBEDTLS_PEM_PARSE_C=y 689 | CONFIG_MBEDTLS_PEM_WRITE_C=y 690 | CONFIG_MBEDTLS_X509_CRL_PARSE_C=y 691 | CONFIG_MBEDTLS_X509_CSR_PARSE_C=y 692 | CONFIG_MBEDTLS_ECP_C=y 693 | CONFIG_MBEDTLS_ECDH_C=y 694 | CONFIG_MBEDTLS_ECDSA_C=y 695 | CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y 696 | CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y 697 | CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y 698 | CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y 699 | CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y 700 | CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y 701 | CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y 702 | CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y 703 | CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y 704 | CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y 705 | CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y 706 | CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y 707 | CONFIG_MBEDTLS_ECP_NIST_OPTIM=y 708 | 709 | # 710 | # OpenSSL 711 | # 712 | CONFIG_OPENSSL_DEBUG= 713 | CONFIG_OPENSSL_ASSERT_DO_NOTHING=y 714 | CONFIG_OPENSSL_ASSERT_EXIT= 715 | 716 | # 717 | # PThreads 718 | # 719 | CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 720 | CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 721 | 722 | # 723 | # SPI Flash driver 724 | # 725 | CONFIG_SPI_FLASH_VERIFY_WRITE= 726 | CONFIG_SPI_FLASH_ENABLE_COUNTERS= 727 | CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y 728 | CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y 729 | CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS= 730 | CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED= 731 | 732 | # 733 | # SPIFFS Configuration 734 | # 735 | CONFIG_SPIFFS_MAX_PARTITIONS=3 736 | 737 | # 738 | # SPIFFS Cache Configuration 739 | # 740 | CONFIG_SPIFFS_CACHE=y 741 | CONFIG_SPIFFS_CACHE_WR=y 742 | CONFIG_SPIFFS_CACHE_STATS= 743 | CONFIG_SPIFFS_PAGE_CHECK=y 744 | CONFIG_SPIFFS_GC_MAX_RUNS=10 745 | CONFIG_SPIFFS_GC_STATS= 746 | CONFIG_SPIFFS_PAGE_SIZE=256 747 | CONFIG_SPIFFS_OBJ_NAME_LEN=32 748 | CONFIG_SPIFFS_USE_MAGIC=y 749 | CONFIG_SPIFFS_USE_MAGIC_LENGTH=y 750 | CONFIG_SPIFFS_META_LENGTH=4 751 | CONFIG_SPIFFS_USE_MTIME=y 752 | 753 | # 754 | # Debug Configuration 755 | # 756 | CONFIG_SPIFFS_DBG= 757 | CONFIG_SPIFFS_API_DBG= 758 | CONFIG_SPIFFS_GC_DBG= 759 | CONFIG_SPIFFS_CACHE_DBG= 760 | CONFIG_SPIFFS_CHECK_DBG= 761 | CONFIG_SPIFFS_TEST_VISUALISATION= 762 | 763 | # 764 | # tcpip adapter 765 | # 766 | CONFIG_IP_LOST_TIMER_INTERVAL=120 767 | 768 | # 769 | # Virtual file system 770 | # 771 | CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y 772 | 773 | # 774 | # Wear Levelling 775 | # 776 | CONFIG_WL_SECTOR_SIZE_512= 777 | CONFIG_WL_SECTOR_SIZE_4096=y 778 | CONFIG_WL_SECTOR_SIZE=4096 779 | -------------------------------------------------------------------------------- /bt_can_spp/sdkconfig.defaults: -------------------------------------------------------------------------------- 1 | # Override some defaults so BT stack is enabled 2 | # and WiFi disabled by default in this example 3 | CONFIG_BT_ENABLED=y 4 | CONFIG_CLASSIC_BT_ENABLED=y 5 | CONFIG_WIFI_ENABLED=n 6 | CONFIG_BT_SPP_ENABLED=y -------------------------------------------------------------------------------- /bt_can_spp/sdkconfig.old: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated file; DO NOT EDIT. 3 | # Espressif IoT Development Framework Configuration 4 | # 5 | 6 | # 7 | # SDK tool configuration 8 | # 9 | CONFIG_TOOLPREFIX="xtensa-esp32-elf-" 10 | CONFIG_PYTHON="python2" 11 | CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y 12 | 13 | # 14 | # Bootloader config 15 | # 16 | CONFIG_LOG_BOOTLOADER_LEVEL_NONE= 17 | CONFIG_LOG_BOOTLOADER_LEVEL_ERROR= 18 | CONFIG_LOG_BOOTLOADER_LEVEL_WARN= 19 | CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y 20 | CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG= 21 | CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE= 22 | CONFIG_LOG_BOOTLOADER_LEVEL=3 23 | CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V= 24 | CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y 25 | CONFIG_BOOTLOADER_FACTORY_RESET= 26 | CONFIG_BOOTLOADER_APP_TEST= 27 | 28 | # 29 | # Security features 30 | # 31 | CONFIG_SECURE_BOOT_ENABLED= 32 | CONFIG_FLASH_ENCRYPTION_ENABLED= 33 | 34 | # 35 | # Serial flasher config 36 | # 37 | CONFIG_ESPTOOLPY_PORT="/dev/ttyUSB0" 38 | CONFIG_ESPTOOLPY_BAUD_115200B=y 39 | CONFIG_ESPTOOLPY_BAUD_230400B= 40 | CONFIG_ESPTOOLPY_BAUD_921600B= 41 | CONFIG_ESPTOOLPY_BAUD_2MB= 42 | CONFIG_ESPTOOLPY_BAUD_OTHER= 43 | CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 44 | CONFIG_ESPTOOLPY_BAUD=115200 45 | CONFIG_ESPTOOLPY_COMPRESSED=y 46 | CONFIG_FLASHMODE_QIO= 47 | CONFIG_FLASHMODE_QOUT= 48 | CONFIG_FLASHMODE_DIO=y 49 | CONFIG_FLASHMODE_DOUT= 50 | CONFIG_ESPTOOLPY_FLASHMODE="dio" 51 | CONFIG_ESPTOOLPY_FLASHFREQ_80M= 52 | CONFIG_ESPTOOLPY_FLASHFREQ_40M=y 53 | CONFIG_ESPTOOLPY_FLASHFREQ_26M= 54 | CONFIG_ESPTOOLPY_FLASHFREQ_20M= 55 | CONFIG_ESPTOOLPY_FLASHFREQ="40m" 56 | CONFIG_ESPTOOLPY_FLASHSIZE_1MB= 57 | CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y 58 | CONFIG_ESPTOOLPY_FLASHSIZE_4MB= 59 | CONFIG_ESPTOOLPY_FLASHSIZE_8MB= 60 | CONFIG_ESPTOOLPY_FLASHSIZE_16MB= 61 | CONFIG_ESPTOOLPY_FLASHSIZE="2MB" 62 | CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y 63 | CONFIG_ESPTOOLPY_BEFORE_RESET=y 64 | CONFIG_ESPTOOLPY_BEFORE_NORESET= 65 | CONFIG_ESPTOOLPY_BEFORE="default_reset" 66 | CONFIG_ESPTOOLPY_AFTER_RESET=y 67 | CONFIG_ESPTOOLPY_AFTER_NORESET= 68 | CONFIG_ESPTOOLPY_AFTER="hard_reset" 69 | CONFIG_MONITOR_BAUD_9600B= 70 | CONFIG_MONITOR_BAUD_57600B= 71 | CONFIG_MONITOR_BAUD_115200B=y 72 | CONFIG_MONITOR_BAUD_230400B= 73 | CONFIG_MONITOR_BAUD_921600B= 74 | CONFIG_MONITOR_BAUD_2MB= 75 | CONFIG_MONITOR_BAUD_OTHER= 76 | CONFIG_MONITOR_BAUD_OTHER_VAL=115200 77 | CONFIG_MONITOR_BAUD=115200 78 | 79 | # 80 | # Partition Table 81 | # 82 | CONFIG_PARTITION_TABLE_SINGLE_APP=y 83 | CONFIG_PARTITION_TABLE_TWO_OTA= 84 | CONFIG_PARTITION_TABLE_CUSTOM= 85 | CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" 86 | CONFIG_PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET=0x10000 87 | CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" 88 | CONFIG_APP_OFFSET=0x10000 89 | CONFIG_PARTITION_TABLE_MD5=y 90 | 91 | # 92 | # Compiler options 93 | # 94 | CONFIG_OPTIMIZATION_LEVEL_DEBUG= 95 | CONFIG_OPTIMIZATION_LEVEL_RELEASE=y 96 | CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y 97 | CONFIG_OPTIMIZATION_ASSERTIONS_SILENT= 98 | CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED= 99 | CONFIG_CXX_EXCEPTIONS= 100 | CONFIG_STACK_CHECK_NONE=y 101 | CONFIG_STACK_CHECK_NORM= 102 | CONFIG_STACK_CHECK_STRONG= 103 | CONFIG_STACK_CHECK_ALL= 104 | CONFIG_STACK_CHECK= 105 | CONFIG_WARN_WRITE_STRINGS= 106 | 107 | # 108 | # Component config 109 | # 110 | 111 | # 112 | # Application Level Tracing 113 | # 114 | CONFIG_ESP32_APPTRACE_DEST_TRAX= 115 | CONFIG_ESP32_APPTRACE_DEST_NONE=y 116 | CONFIG_ESP32_APPTRACE_ENABLE= 117 | CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y 118 | CONFIG_AWS_IOT_SDK= 119 | 120 | # 121 | # Bluetooth 122 | # 123 | CONFIG_BT_ENABLED=y 124 | CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_0=y 125 | CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_1= 126 | CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 127 | CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y 128 | CONFIG_BTDM_CONTROLLER_HCI_MODE_UART_H4= 129 | 130 | # 131 | # MODEM SLEEP Options 132 | # 133 | CONFIG_BTDM_CONTROLLER_MODEM_SLEEP= 134 | CONFIG_BLUEDROID_ENABLED=y 135 | CONFIG_BLUEDROID_PINNED_TO_CORE_0=y 136 | CONFIG_BLUEDROID_PINNED_TO_CORE_1= 137 | CONFIG_BLUEDROID_PINNED_TO_CORE=0 138 | CONFIG_BTC_TASK_STACK_SIZE=3072 139 | CONFIG_BLUEDROID_MEM_DEBUG= 140 | CONFIG_CLASSIC_BT_ENABLED=y 141 | CONFIG_A2DP_ENABLE= 142 | CONFIG_BT_SPP_ENABLED=y 143 | CONFIG_HFP_ENABLE= 144 | CONFIG_GATTS_ENABLE=y 145 | CONFIG_GATTC_ENABLE=y 146 | CONFIG_GATTC_CACHE_NVS_FLASH= 147 | CONFIG_BLE_SMP_ENABLE=y 148 | CONFIG_BT_STACK_NO_LOG= 149 | 150 | # 151 | # BT DEBUG LOG LEVEL 152 | # 153 | CONFIG_HCI_TRACE_LEVEL_NONE= 154 | CONFIG_HCI_TRACE_LEVEL_ERROR= 155 | CONFIG_HCI_TRACE_LEVEL_WARNING=y 156 | CONFIG_HCI_TRACE_LEVEL_API= 157 | CONFIG_HCI_TRACE_LEVEL_EVENT= 158 | CONFIG_HCI_TRACE_LEVEL_DEBUG= 159 | CONFIG_HCI_TRACE_LEVEL_VERBOSE= 160 | CONFIG_HCI_INITIAL_TRACE_LEVEL=2 161 | CONFIG_BTM_TRACE_LEVEL_NONE= 162 | CONFIG_BTM_TRACE_LEVEL_ERROR= 163 | CONFIG_BTM_TRACE_LEVEL_WARNING=y 164 | CONFIG_BTM_TRACE_LEVEL_API= 165 | CONFIG_BTM_TRACE_LEVEL_EVENT= 166 | CONFIG_BTM_TRACE_LEVEL_DEBUG= 167 | CONFIG_BTM_TRACE_LEVEL_VERBOSE= 168 | CONFIG_BTM_INITIAL_TRACE_LEVEL=2 169 | CONFIG_L2CAP_TRACE_LEVEL_NONE= 170 | CONFIG_L2CAP_TRACE_LEVEL_ERROR= 171 | CONFIG_L2CAP_TRACE_LEVEL_WARNING=y 172 | CONFIG_L2CAP_TRACE_LEVEL_API= 173 | CONFIG_L2CAP_TRACE_LEVEL_EVENT= 174 | CONFIG_L2CAP_TRACE_LEVEL_DEBUG= 175 | CONFIG_L2CAP_TRACE_LEVEL_VERBOSE= 176 | CONFIG_L2CAP_INITIAL_TRACE_LEVEL=2 177 | CONFIG_RFCOMM_TRACE_LEVEL_NONE= 178 | CONFIG_RFCOMM_TRACE_LEVEL_ERROR= 179 | CONFIG_RFCOMM_TRACE_LEVEL_WARNING=y 180 | CONFIG_RFCOMM_TRACE_LEVEL_API= 181 | CONFIG_RFCOMM_TRACE_LEVEL_EVENT= 182 | CONFIG_RFCOMM_TRACE_LEVEL_DEBUG= 183 | CONFIG_RFCOMM_TRACE_LEVEL_VERBOSE= 184 | CONFIG_RFCOMM_INITIAL_TRACE_LEVEL=2 185 | CONFIG_SDP_TRACE_LEVEL_NONE= 186 | CONFIG_SDP_TRACE_LEVEL_ERROR= 187 | CONFIG_SDP_TRACE_LEVEL_WARNING=y 188 | CONFIG_SDP_TRACE_LEVEL_API= 189 | CONFIG_SDP_TRACE_LEVEL_EVENT= 190 | CONFIG_SDP_TRACE_LEVEL_DEBUG= 191 | CONFIG_SDP_TRACE_LEVEL_VERBOSE= 192 | CONFIG_SDP_INITIAL_TRACE_LEVEL=2 193 | CONFIG_GAP_TRACE_LEVEL_NONE= 194 | CONFIG_GAP_TRACE_LEVEL_ERROR= 195 | CONFIG_GAP_TRACE_LEVEL_WARNING=y 196 | CONFIG_GAP_TRACE_LEVEL_API= 197 | CONFIG_GAP_TRACE_LEVEL_EVENT= 198 | CONFIG_GAP_TRACE_LEVEL_DEBUG= 199 | CONFIG_GAP_TRACE_LEVEL_VERBOSE= 200 | CONFIG_GAP_INITIAL_TRACE_LEVEL=2 201 | CONFIG_BNEP_TRACE_LEVEL_NONE= 202 | CONFIG_BNEP_TRACE_LEVEL_ERROR= 203 | CONFIG_BNEP_TRACE_LEVEL_WARNING=y 204 | CONFIG_BNEP_TRACE_LEVEL_API= 205 | CONFIG_BNEP_TRACE_LEVEL_EVENT= 206 | CONFIG_BNEP_TRACE_LEVEL_DEBUG= 207 | CONFIG_BNEP_TRACE_LEVEL_VERBOSE= 208 | CONFIG_BNEP_INITIAL_TRACE_LEVEL=2 209 | CONFIG_PAN_TRACE_LEVEL_NONE= 210 | CONFIG_PAN_TRACE_LEVEL_ERROR= 211 | CONFIG_PAN_TRACE_LEVEL_WARNING=y 212 | CONFIG_PAN_TRACE_LEVEL_API= 213 | CONFIG_PAN_TRACE_LEVEL_EVENT= 214 | CONFIG_PAN_TRACE_LEVEL_DEBUG= 215 | CONFIG_PAN_TRACE_LEVEL_VERBOSE= 216 | CONFIG_PAN_INITIAL_TRACE_LEVEL=2 217 | CONFIG_A2D_TRACE_LEVEL_NONE= 218 | CONFIG_A2D_TRACE_LEVEL_ERROR= 219 | CONFIG_A2D_TRACE_LEVEL_WARNING=y 220 | CONFIG_A2D_TRACE_LEVEL_API= 221 | CONFIG_A2D_TRACE_LEVEL_EVENT= 222 | CONFIG_A2D_TRACE_LEVEL_DEBUG= 223 | CONFIG_A2D_TRACE_LEVEL_VERBOSE= 224 | CONFIG_A2D_INITIAL_TRACE_LEVEL=2 225 | CONFIG_AVDT_TRACE_LEVEL_NONE= 226 | CONFIG_AVDT_TRACE_LEVEL_ERROR= 227 | CONFIG_AVDT_TRACE_LEVEL_WARNING=y 228 | CONFIG_AVDT_TRACE_LEVEL_API= 229 | CONFIG_AVDT_TRACE_LEVEL_EVENT= 230 | CONFIG_AVDT_TRACE_LEVEL_DEBUG= 231 | CONFIG_AVDT_TRACE_LEVEL_VERBOSE= 232 | CONFIG_AVDT_INITIAL_TRACE_LEVEL=2 233 | CONFIG_AVCT_TRACE_LEVEL_NONE= 234 | CONFIG_AVCT_TRACE_LEVEL_ERROR= 235 | CONFIG_AVCT_TRACE_LEVEL_WARNING=y 236 | CONFIG_AVCT_TRACE_LEVEL_API= 237 | CONFIG_AVCT_TRACE_LEVEL_EVENT= 238 | CONFIG_AVCT_TRACE_LEVEL_DEBUG= 239 | CONFIG_AVCT_TRACE_LEVEL_VERBOSE= 240 | CONFIG_AVCT_INITIAL_TRACE_LEVEL=2 241 | CONFIG_AVRC_TRACE_LEVEL_NONE= 242 | CONFIG_AVRC_TRACE_LEVEL_ERROR= 243 | CONFIG_AVRC_TRACE_LEVEL_WARNING=y 244 | CONFIG_AVRC_TRACE_LEVEL_API= 245 | CONFIG_AVRC_TRACE_LEVEL_EVENT= 246 | CONFIG_AVRC_TRACE_LEVEL_DEBUG= 247 | CONFIG_AVRC_TRACE_LEVEL_VERBOSE= 248 | CONFIG_AVRC_INITIAL_TRACE_LEVEL=2 249 | CONFIG_MCA_TRACE_LEVEL_NONE= 250 | CONFIG_MCA_TRACE_LEVEL_ERROR= 251 | CONFIG_MCA_TRACE_LEVEL_WARNING=y 252 | CONFIG_MCA_TRACE_LEVEL_API= 253 | CONFIG_MCA_TRACE_LEVEL_EVENT= 254 | CONFIG_MCA_TRACE_LEVEL_DEBUG= 255 | CONFIG_MCA_TRACE_LEVEL_VERBOSE= 256 | CONFIG_MCA_INITIAL_TRACE_LEVEL=2 257 | CONFIG_HID_TRACE_LEVEL_NONE= 258 | CONFIG_HID_TRACE_LEVEL_ERROR= 259 | CONFIG_HID_TRACE_LEVEL_WARNING=y 260 | CONFIG_HID_TRACE_LEVEL_API= 261 | CONFIG_HID_TRACE_LEVEL_EVENT= 262 | CONFIG_HID_TRACE_LEVEL_DEBUG= 263 | CONFIG_HID_TRACE_LEVEL_VERBOSE= 264 | CONFIG_HID_INITIAL_TRACE_LEVEL=2 265 | CONFIG_APPL_TRACE_LEVEL_NONE= 266 | CONFIG_APPL_TRACE_LEVEL_ERROR= 267 | CONFIG_APPL_TRACE_LEVEL_WARNING=y 268 | CONFIG_APPL_TRACE_LEVEL_API= 269 | CONFIG_APPL_TRACE_LEVEL_EVENT= 270 | CONFIG_APPL_TRACE_LEVEL_DEBUG= 271 | CONFIG_APPL_TRACE_LEVEL_VERBOSE= 272 | CONFIG_APPL_INITIAL_TRACE_LEVEL=2 273 | CONFIG_GATT_TRACE_LEVEL_NONE= 274 | CONFIG_GATT_TRACE_LEVEL_ERROR= 275 | CONFIG_GATT_TRACE_LEVEL_WARNING=y 276 | CONFIG_GATT_TRACE_LEVEL_API= 277 | CONFIG_GATT_TRACE_LEVEL_EVENT= 278 | CONFIG_GATT_TRACE_LEVEL_DEBUG= 279 | CONFIG_GATT_TRACE_LEVEL_VERBOSE= 280 | CONFIG_GATT_INITIAL_TRACE_LEVEL=2 281 | CONFIG_SMP_TRACE_LEVEL_NONE= 282 | CONFIG_SMP_TRACE_LEVEL_ERROR= 283 | CONFIG_SMP_TRACE_LEVEL_WARNING=y 284 | CONFIG_SMP_TRACE_LEVEL_API= 285 | CONFIG_SMP_TRACE_LEVEL_EVENT= 286 | CONFIG_SMP_TRACE_LEVEL_DEBUG= 287 | CONFIG_SMP_TRACE_LEVEL_VERBOSE= 288 | CONFIG_SMP_INITIAL_TRACE_LEVEL=2 289 | CONFIG_BTIF_TRACE_LEVEL_NONE= 290 | CONFIG_BTIF_TRACE_LEVEL_ERROR= 291 | CONFIG_BTIF_TRACE_LEVEL_WARNING=y 292 | CONFIG_BTIF_TRACE_LEVEL_API= 293 | CONFIG_BTIF_TRACE_LEVEL_EVENT= 294 | CONFIG_BTIF_TRACE_LEVEL_DEBUG= 295 | CONFIG_BTIF_TRACE_LEVEL_VERBOSE= 296 | CONFIG_BTIF_INITIAL_TRACE_LEVEL=2 297 | CONFIG_BTC_TRACE_LEVEL_NONE= 298 | CONFIG_BTC_TRACE_LEVEL_ERROR= 299 | CONFIG_BTC_TRACE_LEVEL_WARNING=y 300 | CONFIG_BTC_TRACE_LEVEL_API= 301 | CONFIG_BTC_TRACE_LEVEL_EVENT= 302 | CONFIG_BTC_TRACE_LEVEL_DEBUG= 303 | CONFIG_BTC_TRACE_LEVEL_VERBOSE= 304 | CONFIG_BTC_INITIAL_TRACE_LEVEL=2 305 | CONFIG_OSI_TRACE_LEVEL_NONE= 306 | CONFIG_OSI_TRACE_LEVEL_ERROR= 307 | CONFIG_OSI_TRACE_LEVEL_WARNING=y 308 | CONFIG_OSI_TRACE_LEVEL_API= 309 | CONFIG_OSI_TRACE_LEVEL_EVENT= 310 | CONFIG_OSI_TRACE_LEVEL_DEBUG= 311 | CONFIG_OSI_TRACE_LEVEL_VERBOSE= 312 | CONFIG_OSI_INITIAL_TRACE_LEVEL=2 313 | CONFIG_BLUFI_TRACE_LEVEL_NONE= 314 | CONFIG_BLUFI_TRACE_LEVEL_ERROR= 315 | CONFIG_BLUFI_TRACE_LEVEL_WARNING=y 316 | CONFIG_BLUFI_TRACE_LEVEL_API= 317 | CONFIG_BLUFI_TRACE_LEVEL_EVENT= 318 | CONFIG_BLUFI_TRACE_LEVEL_DEBUG= 319 | CONFIG_BLUFI_TRACE_LEVEL_VERBOSE= 320 | CONFIG_BLUFI_INITIAL_TRACE_LEVEL=2 321 | CONFIG_BT_ACL_CONNECTIONS=4 322 | CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST= 323 | CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY= 324 | CONFIG_BLE_SCAN_DUPLICATE=y 325 | CONFIG_DUPLICATE_SCAN_CACHE_SIZE=20 326 | CONFIG_BLE_MESH_SCAN_DUPLICATE_EN= 327 | CONFIG_SMP_ENABLE=y 328 | CONFIG_BT_RESERVE_DRAM=0x10000 329 | 330 | # 331 | # ADC configuration 332 | # 333 | CONFIG_ADC_FORCE_XPD_FSM= 334 | CONFIG_ADC2_DISABLE_DAC=y 335 | 336 | # 337 | # ESP32-specific 338 | # 339 | CONFIG_ESP32_DEFAULT_CPU_FREQ_80= 340 | CONFIG_ESP32_DEFAULT_CPU_FREQ_160= 341 | CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y 342 | CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240 343 | CONFIG_SPIRAM_SUPPORT= 344 | CONFIG_MEMMAP_TRACEMEM= 345 | CONFIG_MEMMAP_TRACEMEM_TWOBANKS= 346 | CONFIG_ESP32_TRAX= 347 | CONFIG_TRACEMEM_RESERVE_DRAM=0x0 348 | CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH= 349 | CONFIG_ESP32_ENABLE_COREDUMP_TO_UART= 350 | CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y 351 | CONFIG_ESP32_ENABLE_COREDUMP= 352 | CONFIG_TWO_UNIVERSAL_MAC_ADDRESS= 353 | CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y 354 | CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 355 | CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 356 | CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 357 | CONFIG_MAIN_TASK_STACK_SIZE=3584 358 | CONFIG_IPC_TASK_STACK_SIZE=1024 359 | CONFIG_TIMER_TASK_STACK_SIZE=3584 360 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y 361 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF= 362 | CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR= 363 | CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF= 364 | CONFIG_NEWLIB_STDIN_LINE_ENDING_LF= 365 | CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y 366 | CONFIG_NEWLIB_NANO_FORMAT= 367 | CONFIG_CONSOLE_UART_DEFAULT=y 368 | CONFIG_CONSOLE_UART_CUSTOM= 369 | CONFIG_CONSOLE_UART_NONE= 370 | CONFIG_CONSOLE_UART_NUM=0 371 | CONFIG_CONSOLE_UART_BAUDRATE=115200 372 | CONFIG_ULP_COPROC_ENABLED= 373 | CONFIG_ULP_COPROC_RESERVE_MEM=0 374 | CONFIG_ESP32_PANIC_PRINT_HALT= 375 | CONFIG_ESP32_PANIC_PRINT_REBOOT=y 376 | CONFIG_ESP32_PANIC_SILENT_REBOOT= 377 | CONFIG_ESP32_PANIC_GDBSTUB= 378 | CONFIG_ESP32_DEBUG_OCDAWARE=y 379 | CONFIG_ESP32_DEBUG_STUBS_ENABLE=y 380 | CONFIG_INT_WDT=y 381 | CONFIG_INT_WDT_TIMEOUT_MS=300 382 | CONFIG_INT_WDT_CHECK_CPU1=y 383 | CONFIG_TASK_WDT=y 384 | CONFIG_TASK_WDT_PANIC= 385 | CONFIG_TASK_WDT_TIMEOUT_S=5 386 | CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y 387 | CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y 388 | CONFIG_BROWNOUT_DET=y 389 | CONFIG_BROWNOUT_DET_LVL_SEL_0=y 390 | CONFIG_BROWNOUT_DET_LVL_SEL_1= 391 | CONFIG_BROWNOUT_DET_LVL_SEL_2= 392 | CONFIG_BROWNOUT_DET_LVL_SEL_3= 393 | CONFIG_BROWNOUT_DET_LVL_SEL_4= 394 | CONFIG_BROWNOUT_DET_LVL_SEL_5= 395 | CONFIG_BROWNOUT_DET_LVL_SEL_6= 396 | CONFIG_BROWNOUT_DET_LVL_SEL_7= 397 | CONFIG_BROWNOUT_DET_LVL=0 398 | CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y 399 | CONFIG_ESP32_TIME_SYSCALL_USE_RTC= 400 | CONFIG_ESP32_TIME_SYSCALL_USE_FRC1= 401 | CONFIG_ESP32_TIME_SYSCALL_USE_NONE= 402 | CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y 403 | CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL= 404 | CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 405 | CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 406 | CONFIG_ESP32_XTAL_FREQ_40=y 407 | CONFIG_ESP32_XTAL_FREQ_26= 408 | CONFIG_ESP32_XTAL_FREQ_AUTO= 409 | CONFIG_ESP32_XTAL_FREQ=40 410 | CONFIG_DISABLE_BASIC_ROM_CONSOLE= 411 | CONFIG_ESP_TIMER_PROFILING= 412 | CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS= 413 | CONFIG_ESP_ERR_TO_NAME_LOOKUP=y 414 | 415 | # 416 | # Wi-Fi 417 | # 418 | CONFIG_SW_COEXIST_ENABLE=y 419 | CONFIG_SW_COEXIST_PREFERENCE_WIFI= 420 | CONFIG_SW_COEXIST_PREFERENCE_BT= 421 | CONFIG_SW_COEXIST_PREFERENCE_BALANCE=y 422 | CONFIG_SW_COEXIST_PREFERENCE_VALUE=2 423 | CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 424 | CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 425 | CONFIG_ESP32_WIFI_STATIC_TX_BUFFER= 426 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y 427 | CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 428 | CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 429 | CONFIG_ESP32_WIFI_CSI_ENABLED= 430 | CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y 431 | CONFIG_ESP32_WIFI_TX_BA_WIN=6 432 | CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y 433 | CONFIG_ESP32_WIFI_RX_BA_WIN=6 434 | CONFIG_ESP32_WIFI_NVS_ENABLED=y 435 | CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y 436 | CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1= 437 | 438 | # 439 | # PHY 440 | # 441 | CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y 442 | CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION= 443 | CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 444 | CONFIG_ESP32_PHY_MAX_TX_POWER=20 445 | 446 | # 447 | # Power Management 448 | # 449 | CONFIG_PM_ENABLE= 450 | 451 | # 452 | # ADC-Calibration 453 | # 454 | CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y 455 | CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y 456 | CONFIG_ADC_CAL_LUT_ENABLE=y 457 | 458 | # 459 | # ESP HTTP client 460 | # 461 | CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y 462 | 463 | # 464 | # Ethernet 465 | # 466 | CONFIG_DMA_RX_BUF_NUM=10 467 | CONFIG_DMA_TX_BUF_NUM=10 468 | CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE= 469 | CONFIG_EMAC_TASK_PRIORITY=20 470 | 471 | # 472 | # FAT Filesystem support 473 | # 474 | CONFIG_FATFS_CODEPAGE_DYNAMIC= 475 | CONFIG_FATFS_CODEPAGE_437=y 476 | CONFIG_FATFS_CODEPAGE_720= 477 | CONFIG_FATFS_CODEPAGE_737= 478 | CONFIG_FATFS_CODEPAGE_771= 479 | CONFIG_FATFS_CODEPAGE_775= 480 | CONFIG_FATFS_CODEPAGE_850= 481 | CONFIG_FATFS_CODEPAGE_852= 482 | CONFIG_FATFS_CODEPAGE_855= 483 | CONFIG_FATFS_CODEPAGE_857= 484 | CONFIG_FATFS_CODEPAGE_860= 485 | CONFIG_FATFS_CODEPAGE_861= 486 | CONFIG_FATFS_CODEPAGE_862= 487 | CONFIG_FATFS_CODEPAGE_863= 488 | CONFIG_FATFS_CODEPAGE_864= 489 | CONFIG_FATFS_CODEPAGE_865= 490 | CONFIG_FATFS_CODEPAGE_866= 491 | CONFIG_FATFS_CODEPAGE_869= 492 | CONFIG_FATFS_CODEPAGE_932= 493 | CONFIG_FATFS_CODEPAGE_936= 494 | CONFIG_FATFS_CODEPAGE_949= 495 | CONFIG_FATFS_CODEPAGE_950= 496 | CONFIG_FATFS_CODEPAGE=437 497 | CONFIG_FATFS_LFN_NONE=y 498 | CONFIG_FATFS_LFN_HEAP= 499 | CONFIG_FATFS_LFN_STACK= 500 | CONFIG_FATFS_FS_LOCK=0 501 | CONFIG_FATFS_TIMEOUT_MS=10000 502 | CONFIG_FATFS_PER_FILE_CACHE=y 503 | 504 | # 505 | # FreeRTOS 506 | # 507 | CONFIG_FREERTOS_UNICORE= 508 | CONFIG_FREERTOS_CORETIMER_0=y 509 | CONFIG_FREERTOS_CORETIMER_1= 510 | CONFIG_FREERTOS_HZ=1000 511 | CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y 512 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE= 513 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL= 514 | CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y 515 | CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK= 516 | CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y 517 | CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 518 | CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y 519 | CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE= 520 | CONFIG_FREERTOS_ASSERT_DISABLE= 521 | CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 522 | CONFIG_FREERTOS_ISR_STACKSIZE=1536 523 | CONFIG_FREERTOS_LEGACY_HOOKS= 524 | CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 525 | CONFIG_SUPPORT_STATIC_ALLOCATION= 526 | CONFIG_TIMER_TASK_PRIORITY=1 527 | CONFIG_TIMER_TASK_STACK_DEPTH=2048 528 | CONFIG_TIMER_QUEUE_LENGTH=10 529 | CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 530 | CONFIG_FREERTOS_USE_TRACE_FACILITY= 531 | CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS= 532 | CONFIG_FREERTOS_DEBUG_INTERNALS= 533 | 534 | # 535 | # Heap memory debugging 536 | # 537 | CONFIG_HEAP_POISONING_DISABLED=y 538 | CONFIG_HEAP_POISONING_LIGHT= 539 | CONFIG_HEAP_POISONING_COMPREHENSIVE= 540 | CONFIG_HEAP_TRACING= 541 | 542 | # 543 | # libsodium 544 | # 545 | CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y 546 | 547 | # 548 | # Log output 549 | # 550 | CONFIG_LOG_DEFAULT_LEVEL_NONE= 551 | CONFIG_LOG_DEFAULT_LEVEL_ERROR= 552 | CONFIG_LOG_DEFAULT_LEVEL_WARN= 553 | CONFIG_LOG_DEFAULT_LEVEL_INFO=y 554 | CONFIG_LOG_DEFAULT_LEVEL_DEBUG= 555 | CONFIG_LOG_DEFAULT_LEVEL_VERBOSE= 556 | CONFIG_LOG_DEFAULT_LEVEL=3 557 | CONFIG_LOG_COLORS=y 558 | 559 | # 560 | # LWIP 561 | # 562 | CONFIG_L2_TO_L3_COPY= 563 | CONFIG_LWIP_IRAM_OPTIMIZATION= 564 | CONFIG_LWIP_MAX_SOCKETS=10 565 | CONFIG_USE_ONLY_LWIP_SELECT= 566 | CONFIG_LWIP_SO_REUSE=y 567 | CONFIG_LWIP_SO_REUSE_RXTOALL=y 568 | CONFIG_LWIP_SO_RCVBUF= 569 | CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 570 | CONFIG_LWIP_IP_FRAG= 571 | CONFIG_LWIP_IP_REASSEMBLY= 572 | CONFIG_LWIP_STATS= 573 | CONFIG_LWIP_ETHARP_TRUST_IP_MAC=y 574 | CONFIG_TCPIP_RECVMBOX_SIZE=32 575 | CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y 576 | 577 | # 578 | # DHCP server 579 | # 580 | CONFIG_LWIP_DHCPS_LEASE_UNIT=60 581 | CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 582 | CONFIG_LWIP_AUTOIP= 583 | CONFIG_LWIP_NETIF_LOOPBACK=y 584 | CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 585 | 586 | # 587 | # TCP 588 | # 589 | CONFIG_LWIP_MAX_ACTIVE_TCP=16 590 | CONFIG_LWIP_MAX_LISTENING_TCP=16 591 | CONFIG_TCP_MAXRTX=12 592 | CONFIG_TCP_SYNMAXRTX=6 593 | CONFIG_TCP_MSS=1436 594 | CONFIG_TCP_MSL=60000 595 | CONFIG_TCP_SND_BUF_DEFAULT=5744 596 | CONFIG_TCP_WND_DEFAULT=5744 597 | CONFIG_TCP_RECVMBOX_SIZE=6 598 | CONFIG_TCP_QUEUE_OOSEQ=y 599 | CONFIG_TCP_OVERSIZE_MSS=y 600 | CONFIG_TCP_OVERSIZE_QUARTER_MSS= 601 | CONFIG_TCP_OVERSIZE_DISABLE= 602 | 603 | # 604 | # UDP 605 | # 606 | CONFIG_LWIP_MAX_UDP_PCBS=16 607 | CONFIG_UDP_RECVMBOX_SIZE=6 608 | CONFIG_TCPIP_TASK_STACK_SIZE=2048 609 | CONFIG_PPP_SUPPORT= 610 | 611 | # 612 | # ICMP 613 | # 614 | CONFIG_LWIP_MULTICAST_PING= 615 | CONFIG_LWIP_BROADCAST_PING= 616 | 617 | # 618 | # LWIP RAW API 619 | # 620 | CONFIG_LWIP_MAX_RAW_PCBS=16 621 | 622 | # 623 | # mbedTLS 624 | # 625 | CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 626 | CONFIG_MBEDTLS_DEBUG= 627 | CONFIG_MBEDTLS_HARDWARE_AES=y 628 | CONFIG_MBEDTLS_HARDWARE_MPI= 629 | CONFIG_MBEDTLS_HARDWARE_SHA= 630 | CONFIG_MBEDTLS_HAVE_TIME=y 631 | CONFIG_MBEDTLS_HAVE_TIME_DATE= 632 | CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y 633 | CONFIG_MBEDTLS_TLS_SERVER_ONLY= 634 | CONFIG_MBEDTLS_TLS_CLIENT_ONLY= 635 | CONFIG_MBEDTLS_TLS_DISABLED= 636 | CONFIG_MBEDTLS_TLS_SERVER=y 637 | CONFIG_MBEDTLS_TLS_CLIENT=y 638 | CONFIG_MBEDTLS_TLS_ENABLED=y 639 | 640 | # 641 | # TLS Key Exchange Methods 642 | # 643 | CONFIG_MBEDTLS_PSK_MODES= 644 | CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y 645 | CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y 646 | CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y 647 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y 648 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y 649 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y 650 | CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y 651 | CONFIG_MBEDTLS_SSL_RENEGOTIATION=y 652 | CONFIG_MBEDTLS_SSL_PROTO_SSL3= 653 | CONFIG_MBEDTLS_SSL_PROTO_TLS1=y 654 | CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y 655 | CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y 656 | CONFIG_MBEDTLS_SSL_PROTO_DTLS= 657 | CONFIG_MBEDTLS_SSL_ALPN=y 658 | CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y 659 | 660 | # 661 | # Symmetric Ciphers 662 | # 663 | CONFIG_MBEDTLS_AES_C=y 664 | CONFIG_MBEDTLS_CAMELLIA_C= 665 | CONFIG_MBEDTLS_DES_C= 666 | CONFIG_MBEDTLS_RC4_DISABLED=y 667 | CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT= 668 | CONFIG_MBEDTLS_RC4_ENABLED= 669 | CONFIG_MBEDTLS_BLOWFISH_C= 670 | CONFIG_MBEDTLS_XTEA_C= 671 | CONFIG_MBEDTLS_CCM_C=y 672 | CONFIG_MBEDTLS_GCM_C=y 673 | CONFIG_MBEDTLS_RIPEMD160_C= 674 | 675 | # 676 | # Certificates 677 | # 678 | CONFIG_MBEDTLS_PEM_PARSE_C=y 679 | CONFIG_MBEDTLS_PEM_WRITE_C=y 680 | CONFIG_MBEDTLS_X509_CRL_PARSE_C=y 681 | CONFIG_MBEDTLS_X509_CSR_PARSE_C=y 682 | CONFIG_MBEDTLS_ECP_C=y 683 | CONFIG_MBEDTLS_ECDH_C=y 684 | CONFIG_MBEDTLS_ECDSA_C=y 685 | CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y 686 | CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y 687 | CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y 688 | CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y 689 | CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y 690 | CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y 691 | CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y 692 | CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y 693 | CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y 694 | CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y 695 | CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y 696 | CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y 697 | CONFIG_MBEDTLS_ECP_NIST_OPTIM=y 698 | 699 | # 700 | # OpenSSL 701 | # 702 | CONFIG_OPENSSL_DEBUG= 703 | CONFIG_OPENSSL_ASSERT_DO_NOTHING=y 704 | CONFIG_OPENSSL_ASSERT_EXIT= 705 | 706 | # 707 | # PThreads 708 | # 709 | CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 710 | CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 711 | 712 | # 713 | # SPI Flash driver 714 | # 715 | CONFIG_SPI_FLASH_VERIFY_WRITE= 716 | CONFIG_SPI_FLASH_ENABLE_COUNTERS= 717 | CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y 718 | CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y 719 | CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS= 720 | CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED= 721 | 722 | # 723 | # SPIFFS Configuration 724 | # 725 | CONFIG_SPIFFS_MAX_PARTITIONS=3 726 | 727 | # 728 | # SPIFFS Cache Configuration 729 | # 730 | CONFIG_SPIFFS_CACHE=y 731 | CONFIG_SPIFFS_CACHE_WR=y 732 | CONFIG_SPIFFS_CACHE_STATS= 733 | CONFIG_SPIFFS_PAGE_CHECK=y 734 | CONFIG_SPIFFS_GC_MAX_RUNS=10 735 | CONFIG_SPIFFS_GC_STATS= 736 | CONFIG_SPIFFS_PAGE_SIZE=256 737 | CONFIG_SPIFFS_OBJ_NAME_LEN=32 738 | CONFIG_SPIFFS_USE_MAGIC=y 739 | CONFIG_SPIFFS_USE_MAGIC_LENGTH=y 740 | CONFIG_SPIFFS_META_LENGTH=4 741 | CONFIG_SPIFFS_USE_MTIME=y 742 | 743 | # 744 | # Debug Configuration 745 | # 746 | CONFIG_SPIFFS_DBG= 747 | CONFIG_SPIFFS_API_DBG= 748 | CONFIG_SPIFFS_GC_DBG= 749 | CONFIG_SPIFFS_CACHE_DBG= 750 | CONFIG_SPIFFS_CHECK_DBG= 751 | CONFIG_SPIFFS_TEST_VISUALISATION= 752 | 753 | # 754 | # tcpip adapter 755 | # 756 | CONFIG_IP_LOST_TIMER_INTERVAL=120 757 | 758 | # 759 | # Virtual file system 760 | # 761 | CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y 762 | 763 | # 764 | # Wear Levelling 765 | # 766 | CONFIG_WL_SECTOR_SIZE_512= 767 | CONFIG_WL_SECTOR_SIZE_4096=y 768 | CONFIG_WL_SECTOR_SIZE=4096 769 | -------------------------------------------------------------------------------- /mcp2515/MCP2515.c: -------------------------------------------------------------------------------- 1 | #include "MCP2515.h" 2 | #include 3 | #include "freertos/FreeRTOS.h" 4 | #include "freertos/task.h" 5 | #include "freertos/event_groups.h" 6 | #include "freertos/queue.h" 7 | #include "freertos/semphr.h" 8 | #include "soc/gpio_struct.h" 9 | 10 | #include "esp_log.h" 11 | 12 | #include "spi_routine.h" 13 | 14 | #include "driver/gpio.h" 15 | #include "esp_err.h" 16 | 17 | #define REG_BFPCTRL 0x0c 18 | #define REG_TXRTSCTRL 0x0d 19 | 20 | #define REG_CANCTRL 0x0f 21 | 22 | #define REG_CNF3 0x28 23 | #define REG_CNF2 0x29 24 | #define REG_CNF1 0x2a 25 | 26 | #define REG_CANINTE 0x2b 27 | #define REG_CANINTF 0x2c 28 | 29 | #define FLAG_RXnIE(n) (0x01 << n) 30 | #define FLAG_RXnIF(n) (0x01 << n) 31 | #define FLAG_TXnIF(n) (0x04 << n) 32 | 33 | #define REG_RXFnSIDH(n) (0x00 + (n * 4)) 34 | #define REG_RXFnSIDL(n) (0x01 + (n * 4)) 35 | #define REG_RXFnEID8(n) (0x02 + (n * 4)) 36 | #define REG_RXFnEID0(n) (0x03 + (n * 4)) 37 | 38 | #define REG_RXMnSIDH(n) (0x20 + (n * 0x04)) 39 | #define REG_RXMnSIDL(n) (0x21 + (n * 0x04)) 40 | #define REG_RXMnEID8(n) (0x22 + (n * 0x04)) 41 | #define REG_RXMnEID0(n) (0x23 + (n * 0x04)) 42 | 43 | #define REG_TXBnCTRL(n) (0x30 + (n * 0x10)) 44 | #define REG_TXBnSIDH(n) (0x31 + (n * 0x10)) 45 | #define REG_TXBnSIDL(n) (0x32 + (n * 0x10)) 46 | #define REG_TXBnEID8(n) (0x33 + (n * 0x10)) 47 | #define REG_TXBnEID0(n) (0x34 + (n * 0x10)) 48 | #define REG_TXBnDLC(n) (0x35 + (n * 0x10)) 49 | #define REG_TXBnD0(n) (0x36 + (n * 0x10)) 50 | 51 | #define REG_RXBnCTRL(n) (0x60 + (n * 0x10)) 52 | #define REG_RXBnSIDH(n) (0x61 + (n * 0x10)) 53 | #define REG_RXBnSIDL(n) (0x62 + (n * 0x10)) 54 | #define REG_RXBnEID8(n) (0x63 + (n * 0x10)) 55 | #define REG_RXBnEID0(n) (0x64 + (n * 0x10)) 56 | #define REG_RXBnDLC(n) (0x65 + (n * 0x10)) 57 | #define REG_RXBnD0(n) (0x66 + (n * 0x10)) 58 | 59 | #define FLAG_IDE 0x08 60 | #define FLAG_SRR 0x10 61 | #define FLAG_RTR 0x40 62 | #define FLAG_EXIDE 0x08 63 | 64 | #define FLAG_RXM0 0x20 65 | #define FLAG_RXM1 0x40 66 | 67 | #define TXB_ABTF 0x40 68 | #define TXB_MLOA 0x20 69 | #define TXB_TXERR 0x10 70 | #define TXB_TXREQ 0x08 71 | #define TXB_TXIE 0x04 72 | #define TXB_TXP 0x03 73 | 74 | #define BLUE_LED 2 75 | #define RX_LED 21 76 | #define TX_LED 19 77 | 78 | 79 | extern xQueueHandle can_frame_queue; 80 | extern xQueueHandle can_irq_quee; 81 | 82 | #define MCP "MCP" 83 | 84 | const struct { 85 | long clockFrequency; 86 | long baudRate; 87 | uint8_t cnf[3]; 88 | } CNF_MAPPER[] = { 89 | { (long)8E6, (long)1000E3, { 0x00, 0x80, 0x00 } }, 90 | { (long)8E6, (long)500E3, { 0x00, 0x90, 0x02 } }, 91 | { (long)8E6, (long)250E3, { 0x00, 0xb1, 0x05 } }, 92 | { (long)8E6, (long)200E3, { 0x00, 0xb4, 0x06 } }, 93 | { (long)8E6, (long)125E3, { 0x01, 0xb1, 0x05 } }, 94 | { (long)8E6, (long)100E3, { 0x01, 0xb4, 0x06 } }, 95 | { (long)8E6, (long)80E3, { 0x01, 0xbf, 0x07 } }, 96 | { (long)8E6, (long)50E3, { 0x03, 0xb4, 0x06 } }, 97 | { (long)8E6, (long)40E3, { 0x03, 0xbf, 0x07 } }, 98 | { (long)8E6, (long)20E3, { 0x07, 0xbf, 0x07 } }, 99 | { (long)8E6, (long)10E3, { 0x0f, 0xbf, 0x07 } }, 100 | { (long)8E6, (long)5E3, { 0x1f, 0xbf, 0x07 } }, 101 | }; 102 | 103 | uint8_t data = 0xC0; 104 | char inited = 0; 105 | bool has_irq = false; 106 | 107 | uint8_t current_mode = CONFIG_MODE; 108 | 109 | SemaphoreHandle_t mtx; 110 | 111 | void(*callback)(struct CanFrame *) = NULL; 112 | 113 | void gpio_isr_handler(void* arg) { 114 | xQueueSendFromISR(can_irq_quee, &data, NULL); 115 | } 116 | 117 | void set_cb(void(*cb)(struct CanFrame *)) { 118 | callback = cb; 119 | } 120 | 121 | void remove_cb() { 122 | callback = NULL; 123 | } 124 | 125 | uint8_t is_available_mode() { 126 | return current_mode == OPEN_MODE || current_mode == LOOPBACK_MODE; 127 | } 128 | 129 | void _tgl_led(uint8_t LED) { 130 | gpio_set_level(LED, 1 - gpio_get_level(LED)); 131 | } 132 | 133 | void _led_on(uint8_t LED) { 134 | gpio_set_level(LED, 1); 135 | } 136 | 137 | void _led_off(uint8_t LED) { 138 | gpio_set_level(LED, 0); 139 | } 140 | 141 | void log_rcv(void* arg) { 142 | struct CanFrame *fp = NULL; 143 | for(;;) { 144 | if(xQueueReceive(can_frame_queue, &fp, 1/portTICK_PERIOD_MS)) { 145 | if (callback != NULL) { 146 | callback(fp); 147 | } 148 | free(fp); 149 | } 150 | taskYIELD (); 151 | } 152 | } 153 | 154 | void read_frame_tsk() { 155 | struct CanFrame *io_num = NULL; 156 | for(;;) { 157 | if(xQueueReceive(can_irq_quee, &io_num, 1/portTICK_PERIOD_MS)) { 158 | uint8_t taken = xSemaphoreTake(mtx, 1/portTICK_PERIOD_MS); 159 | 160 | while(taken != 1) { 161 | taken = xSemaphoreTake(mtx, 1/portTICK_PERIOD_MS); 162 | } 163 | 164 | int n = 0; 165 | _tgl_led(RX_LED); 166 | if ( read_reg(REG_CANINTF) != 0) { 167 | uint8_t intf = read_reg(REG_CANINTF); 168 | if (intf & FLAG_RXnIF(0)) { 169 | n = 0; 170 | } else if (intf & FLAG_RXnIF(1)) { 171 | n = 1; 172 | } 173 | 174 | long int id = -1; 175 | bool isExt = (read_reg(REG_RXBnSIDL(n)) & FLAG_IDE) ? true : false; 176 | int dlc = 0; 177 | uint8_t data[8]; 178 | memset(&data, 0, sizeof(data)); 179 | uint32_t idA = ((read_reg(REG_RXBnSIDH(n)) << 3) & 0x07f8) | ((read_reg(REG_RXBnSIDL(n)) >> 5) & 0x07); 180 | if (isExt) { 181 | uint32_t idB = (((uint32_t)(read_reg(REG_RXBnSIDL(n)) & 0x03) << 16) & 0x30000) | ((read_reg(REG_RXBnEID8(n)) << 8) & 0xff00) | read_reg(REG_RXBnEID0(n)); 182 | id = (idA << 18) | idB; 183 | } else { 184 | id = idA; 185 | } 186 | dlc = read_reg(REG_RXBnDLC(n)) & 0x0f; 187 | 188 | for (int i = 0; i < dlc; i++) { 189 | data[i] = read_reg(REG_RXBnD0(n) + i); 190 | } 191 | if (is_available_mode()) { 192 | struct CanFrame *frame; 193 | frame = malloc(sizeof(struct CanFrame)); 194 | if (frame != NULL) { 195 | frame->IsExt = isExt; 196 | frame->CanId = id; 197 | frame->DLC = dlc; 198 | memcpy(&frame->Data, &data, sizeof(data)); 199 | xQueueSend(can_frame_queue, &frame, 10); 200 | } 201 | } 202 | mod_register(REG_CANINTF, FLAG_RXnIF(n), 0x00); 203 | } 204 | has_irq = false; 205 | xSemaphoreGive(mtx); 206 | } 207 | taskYIELD (); 208 | } 209 | } 210 | 211 | void on_irq_reg() { 212 | write_register(REG_CANINTE, FLAG_RXnIE(1) | FLAG_RXnIE(0)); 213 | write_register(REG_BFPCTRL, 0x00); 214 | write_register(REG_TXRTSCTRL, 0x00); 215 | write_register(REG_RXBnCTRL(0), FLAG_RXM1 | FLAG_RXM0); 216 | write_register(REG_RXBnCTRL(1), FLAG_RXM1 | FLAG_RXM0); 217 | } 218 | 219 | void init_interrupt_handler() { 220 | gpio_intr_disable(CAN_INT); 221 | gpio_pulldown_en(CAN_INT); 222 | gpio_set_intr_type(CAN_INT, GPIO_INTR_NEGEDGE); 223 | gpio_install_isr_service(( ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LOWMED)); 224 | gpio_isr_handler_add(CAN_INT, &gpio_isr_handler, (void*) CAN_INT); 225 | } 226 | 227 | void init_rcv_task() { 228 | xTaskCreate(&read_frame_tsk, "read_frame", 2048, NULL, 10, NULL); 229 | xTaskCreate(&log_rcv, "log_rcv", 2048, NULL, 10, NULL); 230 | } 231 | 232 | int set_mode(uint8_t mode) { 233 | write_register(REG_CANCTRL, mode); 234 | vTaskDelay(10); 235 | uint8_t real_reg = read_reg(REG_CANCTRL); 236 | if (real_reg != mode) { 237 | ESP_LOGE(MCP, "Try to set %x, real state %x", mode, real_reg); 238 | return 1; 239 | } 240 | current_mode = mode; 241 | return 0; 242 | } 243 | 244 | int _reset_mcp() { 245 | uint8_t err = send_data(&data, 1); 246 | if (err) { 247 | ESP_LOGE(MCP, "Send 0xc0 err"); 248 | return err; 249 | } 250 | vTaskDelay(100); 251 | set_mode(CONFIG_MODE); 252 | _led_off(BLUE_LED); 253 | _led_off(RX_LED); 254 | _led_off(TX_LED); 255 | return err; 256 | } 257 | 258 | int reset_mcp() { 259 | uint8_t taken = xSemaphoreTake(mtx, portMAX_DELAY); 260 | 261 | while(taken != 1) { 262 | taken = xSemaphoreTake(mtx, portMAX_DELAY); 263 | } 264 | uint8_t err = _reset_mcp(); 265 | xSemaphoreGive(mtx); 266 | return err; 267 | } 268 | 269 | int set_speed(long baudRate) { 270 | const uint8_t* cnf = NULL; 271 | 272 | for (unsigned int i = 0; i < (sizeof(CNF_MAPPER) / sizeof(CNF_MAPPER[0])); i++) { 273 | if (CNF_MAPPER[i].baudRate == baudRate) { 274 | cnf = CNF_MAPPER[i].cnf; 275 | break; 276 | } 277 | } 278 | 279 | if (cnf == NULL) { 280 | return 1; 281 | } 282 | write_register(REG_CNF1, cnf[0]); 283 | write_register(REG_CNF2, cnf[1]); 284 | write_register(REG_CNF3, cnf[2]); 285 | return 0; 286 | } 287 | 288 | void init_once() { 289 | if (!inited) { 290 | mtx = xSemaphoreCreateMutex(); 291 | init_rcv_task(); 292 | init_interrupt_handler(); 293 | gpio_intr_enable(CAN_INT); 294 | } 295 | inited = 1; 296 | } 297 | 298 | void bootstrap_mcp() { 299 | gpio_set_direction(BLUE_LED, GPIO_MODE_INPUT_OUTPUT); 300 | gpio_set_direction(RX_LED, GPIO_MODE_INPUT_OUTPUT); 301 | gpio_set_direction(TX_LED, GPIO_MODE_INPUT_OUTPUT); 302 | _led_off(BLUE_LED); 303 | _led_off(RX_LED); 304 | _led_off(TX_LED); 305 | init_once(); 306 | } 307 | 308 | esp_err_t init_mcp(long baudRate, int mode) { 309 | esp_err_t err; 310 | init_once(); 311 | 312 | uint8_t taken = xSemaphoreTake(mtx, portMAX_DELAY); 313 | 314 | while(taken != 1) { 315 | taken = xSemaphoreTake(mtx, portMAX_DELAY); 316 | } 317 | 318 | err = _reset_mcp(); 319 | 320 | err = set_speed(baudRate); 321 | if (err) { 322 | ESP_LOGE(MCP, "set speed err"); 323 | return err; 324 | }; 325 | 326 | err = set_mode(mode); 327 | if (err) { 328 | ESP_LOGE(MCP, "set mode err"); 329 | return err; 330 | }; 331 | on_irq_reg(); 332 | 333 | ESP_LOGI(MCP, "finish init"); 334 | xSemaphoreGive(mtx); 335 | _led_on(BLUE_LED); 336 | return 0; 337 | } 338 | 339 | 340 | int _send_frame(struct CanFrame *frame, uint8_t n) { 341 | if (frame->IsExt) { 342 | write_register(REG_TXBnSIDH(n), frame->CanId >> 21); 343 | write_register(REG_TXBnSIDL(n), (((frame->CanId >> 18) & 0x07) << 5) | FLAG_EXIDE | ((frame->CanId >> 16) & 0x03)); 344 | write_register(REG_TXBnEID8(n), (frame->CanId >> 8) & 0xff); 345 | write_register(REG_TXBnEID0(n), frame->CanId & 0xff); 346 | } else { 347 | write_register(REG_TXBnSIDH(n), frame->CanId >> 3); 348 | write_register(REG_TXBnSIDL(n), frame->CanId << 5); 349 | write_register(REG_TXBnEID8(n), 0x00); 350 | write_register(REG_TXBnEID0(n), 0x00); 351 | } 352 | write_register(REG_TXBnDLC(n), frame->DLC); 353 | 354 | for (int i = 0; i < frame->DLC; i++) { 355 | write_register(REG_TXBnD0(n) + i, frame->Data[i]); 356 | } 357 | 358 | write_register(REG_TXBnCTRL(n), TXB_TXREQ); 359 | return 0; 360 | } 361 | 362 | int send_frame(struct CanFrame *frame) { 363 | if (is_available_mode()) { 364 | uint8_t taken = xSemaphoreTake(mtx, 1/portTICK_PERIOD_MS); 365 | 366 | while(taken != 1) { 367 | taken = xSemaphoreTake(mtx, 1/portTICK_PERIOD_MS); 368 | } 369 | 370 | _tgl_led(TX_LED); 371 | 372 | int result = 1; 373 | 374 | for (int i = 0; i < 3; i++) { 375 | if ((read_reg(REG_TXBnCTRL(i)) & TXB_TXREQ) == 0) { 376 | ESP_LOGI(MCP, "USE %d buffer", i); 377 | result = _send_frame(frame, i); 378 | break; 379 | } 380 | } 381 | if (result) { 382 | ESP_LOGE(MCP, "No empty buffer"); 383 | } 384 | 385 | 386 | xSemaphoreGive(mtx); 387 | return result; 388 | } 389 | return 0; 390 | } 391 | -------------------------------------------------------------------------------- /mcp2515/MCP2515.h: -------------------------------------------------------------------------------- 1 | #ifndef MCP2515_H 2 | #define MCP2515_H 3 | #include "esp_err.h" 4 | #include "can.h" 5 | 6 | #define CAN_INT 17 7 | #define OPEN_MODE 0x00 8 | #define LOOPBACK_MODE 0x40 9 | #define CONFIG_MODE 0x80 10 | 11 | 12 | esp_err_t init_mcp(long baudRate, int mode); 13 | esp_err_t send_frame(struct CanFrame *frame); 14 | 15 | esp_err_t reset_mcp(); 16 | 17 | void set_cb(void(*cb)(struct CanFrame *)); 18 | 19 | void remove_cb(); 20 | 21 | void bootstrap_mcp(); 22 | 23 | #endif -------------------------------------------------------------------------------- /mcp2515/can.h: -------------------------------------------------------------------------------- 1 | #ifndef CAN_H 2 | #define CAN_H 3 | #include 4 | 5 | typedef struct CanFrame { 6 | 7 | uint8_t IsExt; 8 | 9 | uint32_t CanId; /*!< Specifies the standard identifier. 10 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 11 | uint8_t DLC; /*!< Specifies the length of the frame that will be received. 12 | This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ 13 | uint8_t Data[8]; /*!< Contains the data to be received. 14 | This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ 15 | } can_frame_t; 16 | 17 | 18 | #endif -------------------------------------------------------------------------------- /mcp2515/component.mk: -------------------------------------------------------------------------------- 1 | COMPONENT_ADD_INCLUDEDIRS := . 2 | -------------------------------------------------------------------------------- /mcp2515/spi_routine.c: -------------------------------------------------------------------------------- 1 | #include "spi_routine.h" 2 | #include 3 | #include "esp_system.h" 4 | #include "esp_err.h" 5 | 6 | #include "esp_log.h" 7 | 8 | #include "freertos/FreeRTOS.h" 9 | #include "freertos/task.h" 10 | #include "freertos/event_groups.h" 11 | 12 | #include "driver/spi_master.h" 13 | #include "soc/gpio_struct.h" 14 | #include "driver/gpio.h" 15 | 16 | #define PIN_NUM_MISO 12 17 | #define PIN_NUM_MOSI 13 18 | #define PIN_NUM_CLK 14 19 | #define PIN_NUM_CS 15 20 | 21 | #define MCP "SPI" 22 | 23 | static spi_device_handle_t spi; 24 | 25 | esp_err_t init_spi() { 26 | esp_err_t ret; 27 | 28 | spi_bus_config_t buscfg={ 29 | .miso_io_num=PIN_NUM_MISO, 30 | .mosi_io_num=PIN_NUM_MOSI, 31 | .sclk_io_num=PIN_NUM_CLK, 32 | .quadwp_io_num=-1, 33 | .quadhd_io_num=-1, 34 | .max_transfer_sz=4096 35 | }; 36 | spi_device_interface_config_t devcfg={ 37 | .clock_speed_hz=10*1000*1000, //Clock out at 10 MHz 38 | .mode=0, //SPI mode 0 39 | .spics_io_num=PIN_NUM_CS, //CS pin 40 | .queue_size=7, 41 | // .pre_cb=lcd_spi_pre_transfer_callback, 42 | }; 43 | 44 | //Initialize the SPI bus 45 | ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); 46 | ESP_ERROR_CHECK(ret); 47 | //Attach the LCD to the SPI bus 48 | ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi); 49 | ESP_ERROR_CHECK(ret); 50 | return ret; 51 | } 52 | 53 | esp_err_t write_register(uint8_t addr, uint8_t val) { 54 | esp_err_t ret; 55 | spi_transaction_t t; 56 | 57 | uint8_t data[3]; 58 | data[0]=0x02; 59 | data[1]=addr; 60 | data[2]=val; 61 | 62 | memset(&t, 0, sizeof(t)); 63 | t.length=24; 64 | t.tx_buffer=&data; 65 | ret=spi_device_transmit(spi, &t); 66 | return ret; 67 | } 68 | 69 | esp_err_t mod_register(uint8_t addr, uint8_t mask, uint8_t val) { 70 | spi_transaction_t t; 71 | esp_err_t ret; 72 | 73 | uint8_t data[4]; 74 | data[0]=0x05; 75 | data[1]=addr; 76 | data[2]=mask; 77 | data[3]=val; 78 | 79 | memset(&t, 0, sizeof(t)); 80 | t.length=32; 81 | t.tx_buffer=&data; 82 | ret=spi_device_transmit(spi, &t); 83 | return ret; 84 | } 85 | 86 | uint8_t read_reg(uint8_t addr) { 87 | spi_transaction_t r; 88 | 89 | uint8_t data[2]; 90 | data[0]=0x03; 91 | data[1]=addr; 92 | 93 | memset(&r, 0, sizeof(r)); 94 | r.length=8*4; 95 | r.tx_buffer=&data; 96 | r.flags = SPI_TRANS_USE_RXDATA; 97 | 98 | spi_device_transmit(spi, &r); 99 | // ESP_LOGE(MCP, "r: [%02x, %02x, %02x, %02x]", 100 | // r.rx_data[0], r.rx_data[1], r.rx_data[2], r.rx_data[3]); 101 | return r.rx_data[2]; 102 | } 103 | 104 | esp_err_t send_data(const uint8_t *data, int len) { 105 | esp_err_t ret; 106 | spi_transaction_t t; 107 | if (len==0) return 0; 108 | memset(&t, 0, sizeof(t)); 109 | t.length=len*8; 110 | t.tx_buffer=data; 111 | ret=spi_device_transmit(spi, &t); 112 | return ret; 113 | } 114 | -------------------------------------------------------------------------------- /mcp2515/spi_routine.h: -------------------------------------------------------------------------------- 1 | #ifndef SPI_ROUTINE_H 2 | #define SPI_ROUTINE_H 3 | #include "esp_err.h" 4 | 5 | esp_err_t init_spi(); 6 | esp_err_t send_data(const uint8_t *data, int len); 7 | 8 | esp_err_t write_register(uint8_t addr, uint8_t val); 9 | esp_err_t mod_register(uint8_t addr, uint8_t mask, uint8_t val); 10 | esp_err_t read_register(uint8_t addr, uint8_t (*val)[4]); 11 | uint8_t read_reg(uint8_t addr); 12 | 13 | #endif --------------------------------------------------------------------------------