├── .gitignore ├── .settings └── com.atollic.truestudio.debug.hardware_device.prefs ├── README.md ├── LICENSE ├── Inc ├── STM32_EEPROM_SPI.h ├── stm32f1xx_it.h ├── main.h ├── FreeRTOSConfig.h └── stm32f1xx_hal_conf.h ├── Src ├── freertos.c ├── stm32f1xx_hal_timebase_TIM.c ├── stm32f1xx_hal_timebase_tim.c ├── stm32f1xx_it.c ├── stm32f1xx_hal_msp.c ├── STM32_EEPROM_SPI.c ├── main.c └── system_stm32f1xx.c ├── STM32F103C8_FLASH.ld ├── F103-EEPROM.elf.launch ├── syscalls.c ├── F103-EEPROM.ioc ├── .project ├── startup └── startup_stm32f103xb.s ├── .mxproject └── .cproject /.gitignore: -------------------------------------------------------------------------------- 1 | *.axf 2 | *.htm 3 | *.Inp 4 | *.map 5 | *.tra 6 | *.dep 7 | *.__i 8 | *.crf 9 | *.d 10 | *.o 11 | *.lst 12 | *.lnp 13 | *.bak 14 | *.Vishwas 15 | *.bin 16 | *.fed 17 | *._2i 18 | *.l1p 19 | *.l2p 20 | *.iex 21 | .#* 22 | *.uvgui.* 23 | *.uvopt 24 | -------------------------------------------------------------------------------- /.settings/com.atollic.truestudio.debug.hardware_device.prefs: -------------------------------------------------------------------------------- 1 | BOARD=None 2 | CODE_LOCATION=FLASH 3 | ENDIAN=Little-endian 4 | MCU=STM32F103C8 5 | MCU_VENDOR=STMicroelectronics 6 | MODEL=Lite 7 | PROBE=ST-LINK 8 | PROJECT_FORMAT_VERSION=2 9 | TARGET=ARM\u00AE 10 | VERSION=4.1.0 11 | eclipse.preferences.version=1 12 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | STM32 libriary for SPI EEPROM ST M95xxx 2 | ----------------------------------- 3 | 4 | This libriary is consists of two files: 5 | 6 | - *Inc/STM32_EEPROM_SPI.h* 7 | - *Src/STM32_EEPROM_SPI.c* 8 | 9 | Lib is tested with STM32F103C8T6 and M95640-W. 10 | You can use configured STM32CubeMX configuration from *F103-EEPROM.ioc*. 11 | 12 | ---------- 13 | 14 | TODO: 15 | ----- 16 | 17 | - Add "Cycling with Error Correction Code" 18 | - Add Hold condition 19 | - Add Write Protect condition 20 | 21 | **You are welcome to review the code and update it.** 22 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 Nikita Bulaev 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Inc/STM32_EEPROM_SPI.h: -------------------------------------------------------------------------------- 1 | /* Copyright 2017-2019 Nikita Bulaev 2 | * 3 | */ 4 | 5 | 6 | #ifndef _STM32_EEPROM_SPI_H 7 | #define _STM32_EEPROM_SPI_H 8 | 9 | /* C++ detection */ 10 | #ifdef __cplusplus 11 | extern "C" { 12 | #endif 13 | 14 | #include "main.h" 15 | #include "cmsis_os.h" 16 | 17 | /* M95040 SPI EEPROM defines */ 18 | #define EEPROM_WREN 0x06 /*!< Write Enable */ 19 | #define EEPROM_WRDI 0x04 /*!< Write Disable */ 20 | #define EEPROM_RDSR 0x05 /*!< Read Status Register */ 21 | #define EEPROM_WRSR 0x01 /*!< Write Status Register */ 22 | #define EEPROM_READ 0x03 /*!< Read from Memory Array */ 23 | #define EEPROM_WRITE 0x02 /*!< Write to Memory Array */ 24 | 25 | #define EEPROM_WIP_FLAG 0x01 /*!< Write In Progress (WIP) flag */ 26 | 27 | #define EEPROM_PAGESIZE 32 /*!< Pagesize according to documentation */ 28 | #define EEPROM_BUFFER_SIZE 32 /*!< EEPROM Buffer size. Setup to your needs */ 29 | 30 | #define EEPROM_CS_HIGH() HAL_GPIO_WritePin(EEPROM_CS_GPIO_Port, EEPROM_CS_Pin, GPIO_PIN_SET) 31 | #define EEPROM_CS_LOW() HAL_GPIO_WritePin(EEPROM_CS_GPIO_Port, EEPROM_CS_Pin, GPIO_PIN_RESET) 32 | 33 | /** 34 | * @brief EEPROM Operations statuses 35 | */ 36 | typedef enum { 37 | EEPROM_STATUS_PENDING, 38 | EEPROM_STATUS_COMPLETE, 39 | EEPROM_STATUS_ERROR 40 | } EepromOperations; 41 | 42 | void EEPROM_SPI_INIT(SPI_HandleTypeDef * hspi); 43 | EepromOperations EEPROM_SPI_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); 44 | EepromOperations EEPROM_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); 45 | EepromOperations EEPROM_SPI_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead); 46 | uint8_t EEPROM_SPI_WaitStandbyState(void); 47 | 48 | /* Low layer functions */ 49 | uint8_t EEPROM_SendByte(uint8_t byte); 50 | void sEE_WriteEnable(void); 51 | void sEE_WriteDisable(void); 52 | void sEE_WriteStatusRegister(uint8_t regval); 53 | uint8_t sEE_ReadStatusRegister(void); 54 | 55 | void EEPROM_SPI_SendInstruction(uint8_t *instruction, uint8_t size); 56 | void EEPROM_SPI_ReadStatusByte(SPI_HandleTypeDef SPIe, uint8_t *statusByte ); 57 | 58 | #ifdef __cplusplus 59 | } 60 | #endif 61 | 62 | #endif // _STM32_EEPROM_SPI_H 63 | -------------------------------------------------------------------------------- /Inc/stm32f1xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * 8 | * COPYRIGHT(c) 2019 STMicroelectronics 9 | * 10 | * Redistribution and use in source and binary forms, with or without modification, 11 | * are permitted provided that the following conditions are met: 12 | * 1. Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 2. Redistributions in binary form must reproduce the above copyright notice, 15 | * this list of conditions and the following disclaimer in the documentation 16 | * and/or other materials provided with the distribution. 17 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 18 | * may be used to endorse or promote products derived from this software 19 | * without specific prior written permission. 20 | * 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 25 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 28 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 | * 32 | ****************************************************************************** 33 | */ 34 | /* USER CODE END Header */ 35 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ 37 | #ifndef __STM32F1xx_IT_H 38 | #define __STM32F1xx_IT_H 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | /* Private includes ----------------------------------------------------------*/ 45 | /* USER CODE BEGIN Includes */ 46 | 47 | /* USER CODE END Includes */ 48 | 49 | /* Exported types ------------------------------------------------------------*/ 50 | /* USER CODE BEGIN ET */ 51 | 52 | /* USER CODE END ET */ 53 | 54 | /* Exported constants --------------------------------------------------------*/ 55 | /* USER CODE BEGIN EC */ 56 | 57 | /* USER CODE END EC */ 58 | 59 | /* Exported macro ------------------------------------------------------------*/ 60 | /* USER CODE BEGIN EM */ 61 | 62 | /* USER CODE END EM */ 63 | 64 | /* Exported functions prototypes ---------------------------------------------*/ 65 | void NMI_Handler(void); 66 | void HardFault_Handler(void); 67 | void MemManage_Handler(void); 68 | void BusFault_Handler(void); 69 | void UsageFault_Handler(void); 70 | void DebugMon_Handler(void); 71 | void TIM2_IRQHandler(void); 72 | /* USER CODE BEGIN EFP */ 73 | 74 | /* USER CODE END EFP */ 75 | 76 | #ifdef __cplusplus 77 | } 78 | #endif 79 | 80 | #endif /* __STM32F1xx_IT_H */ 81 | 82 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 83 | -------------------------------------------------------------------------------- /Src/freertos.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * File Name : freertos.c 5 | * Description : Code for freertos applications 6 | ****************************************************************************** 7 | * This notice applies to any and all portions of this file 8 | * that are not between comment pairs USER CODE BEGIN and 9 | * USER CODE END. Other portions of this file, whether 10 | * inserted by the user or by software development tools 11 | * are owned by their respective copyright owners. 12 | * 13 | * Copyright (c) 2019 STMicroelectronics International N.V. 14 | * All rights reserved. 15 | * 16 | * Redistribution and use in source and binary forms, with or without 17 | * modification, are permitted, provided that the following conditions are met: 18 | * 19 | * 1. Redistribution of source code must retain the above copyright notice, 20 | * this list of conditions and the following disclaimer. 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, 22 | * this list of conditions and the following disclaimer in the documentation 23 | * and/or other materials provided with the distribution. 24 | * 3. Neither the name of STMicroelectronics nor the names of other 25 | * contributors to this software may be used to endorse or promote products 26 | * derived from this software without specific written permission. 27 | * 4. This software, including modifications and/or derivative works of this 28 | * software, must execute solely and exclusively on microcontroller or 29 | * microprocessor devices manufactured by or for STMicroelectronics. 30 | * 5. Redistribution and use of this software other than as permitted under 31 | * this license is void and will automatically terminate your rights under 32 | * this license. 33 | * 34 | * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 35 | * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 36 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 37 | * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY 38 | * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 39 | * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 40 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 42 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 43 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 44 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 45 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 | * 47 | ****************************************************************************** 48 | */ 49 | /* USER CODE END Header */ 50 | 51 | /* Includes ------------------------------------------------------------------*/ 52 | #include "FreeRTOS.h" 53 | #include "task.h" 54 | #include "main.h" 55 | 56 | /* Private includes ----------------------------------------------------------*/ 57 | /* USER CODE BEGIN Includes */ 58 | 59 | /* USER CODE END Includes */ 60 | 61 | /* Private typedef -----------------------------------------------------------*/ 62 | /* USER CODE BEGIN PTD */ 63 | 64 | /* USER CODE END PTD */ 65 | 66 | /* Private define ------------------------------------------------------------*/ 67 | /* USER CODE BEGIN PD */ 68 | 69 | /* USER CODE END PD */ 70 | 71 | /* Private macro -------------------------------------------------------------*/ 72 | /* USER CODE BEGIN PM */ 73 | 74 | /* USER CODE END PM */ 75 | 76 | /* Private variables ---------------------------------------------------------*/ 77 | /* USER CODE BEGIN Variables */ 78 | 79 | /* USER CODE END Variables */ 80 | 81 | /* Private function prototypes -----------------------------------------------*/ 82 | /* USER CODE BEGIN FunctionPrototypes */ 83 | 84 | /* USER CODE END FunctionPrototypes */ 85 | 86 | /* Private application code --------------------------------------------------*/ 87 | /* USER CODE BEGIN Application */ 88 | 89 | /* USER CODE END Application */ 90 | 91 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 92 | -------------------------------------------------------------------------------- /Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * This notice applies to any and all portions of this file 9 | * that are not between comment pairs USER CODE BEGIN and 10 | * USER CODE END. Other portions of this file, whether 11 | * inserted by the user or by software development tools 12 | * are owned by their respective copyright owners. 13 | * 14 | * Copyright (c) 2019 STMicroelectronics International N.V. 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted, provided that the following conditions are met: 19 | * 20 | * 1. Redistribution of source code must retain the above copyright notice, 21 | * this list of conditions and the following disclaimer. 22 | * 2. Redistributions in binary form must reproduce the above copyright notice, 23 | * this list of conditions and the following disclaimer in the documentation 24 | * and/or other materials provided with the distribution. 25 | * 3. Neither the name of STMicroelectronics nor the names of other 26 | * contributors to this software may be used to endorse or promote products 27 | * derived from this software without specific written permission. 28 | * 4. This software, including modifications and/or derivative works of this 29 | * software, must execute solely and exclusively on microcontroller or 30 | * microprocessor devices manufactured by or for STMicroelectronics. 31 | * 5. Redistribution and use of this software other than as permitted under 32 | * this license is void and will automatically terminate your rights under 33 | * this license. 34 | * 35 | * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 36 | * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 37 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 38 | * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY 39 | * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 40 | * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 41 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 43 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 44 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 45 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 46 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 | * 48 | ****************************************************************************** 49 | */ 50 | /* USER CODE END Header */ 51 | 52 | /* Define to prevent recursive inclusion -------------------------------------*/ 53 | #ifndef __MAIN_H 54 | #define __MAIN_H 55 | 56 | #ifdef __cplusplus 57 | extern "C" { 58 | #endif 59 | 60 | /* Includes ------------------------------------------------------------------*/ 61 | #include "stm32f1xx_hal.h" 62 | 63 | /* Private includes ----------------------------------------------------------*/ 64 | /* USER CODE BEGIN Includes */ 65 | 66 | /* USER CODE END Includes */ 67 | 68 | /* Exported types ------------------------------------------------------------*/ 69 | /* USER CODE BEGIN ET */ 70 | 71 | /* USER CODE END ET */ 72 | 73 | /* Exported constants --------------------------------------------------------*/ 74 | /* USER CODE BEGIN EC */ 75 | 76 | /* USER CODE END EC */ 77 | 78 | /* Exported macro ------------------------------------------------------------*/ 79 | /* USER CODE BEGIN EM */ 80 | 81 | /* USER CODE END EM */ 82 | 83 | /* Exported functions prototypes ---------------------------------------------*/ 84 | void Error_Handler(void); 85 | 86 | /* USER CODE BEGIN EFP */ 87 | 88 | /* USER CODE END EFP */ 89 | 90 | /* Private defines -----------------------------------------------------------*/ 91 | #define EEPROM_CS_Pin GPIO_PIN_0 92 | #define EEPROM_CS_GPIO_Port GPIOB 93 | #define EEPROM_WP_Pin GPIO_PIN_1 94 | #define EEPROM_WP_GPIO_Port GPIOB 95 | #define EEPROM_HOLD_Pin GPIO_PIN_10 96 | #define EEPROM_HOLD_GPIO_Port GPIOB 97 | /* USER CODE BEGIN Private defines */ 98 | typedef enum { 99 | true, 100 | false 101 | } bool; 102 | /* USER CODE END Private defines */ 103 | 104 | #ifdef __cplusplus 105 | } 106 | #endif 107 | 108 | #endif /* __MAIN_H */ 109 | 110 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 111 | -------------------------------------------------------------------------------- /STM32F103C8_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ***************************************************************************** 3 | ** 4 | 5 | ** File : stm32_flash.ld 6 | ** 7 | ** Abstract : Linker script for STM32F103C8 Device with 8 | ** 64KByte FLASH, 20KByte RAM 9 | ** 10 | ** Set heap size, stack size and stack location according 11 | ** to application requirements. 12 | ** 13 | ** Set memory bank area and size if external memory is used. 14 | ** 15 | ** Target : STMicroelectronics STM32 16 | ** 17 | ** Environment : Atollic TrueSTUDIO(R) 18 | ** 19 | ** Distribution: The file is distributed as is, without any warranty 20 | ** of any kind. 21 | ** 22 | ** (c)Copyright Atollic AB. 23 | ** You may use this file as-is or modify it according to the needs of your 24 | ** project. This file may only be built (assembled or compiled and linked) 25 | ** using the Atollic TrueSTUDIO(R) product. The use of this file together 26 | ** with other tools than Atollic TrueSTUDIO(R) is not permitted. 27 | ** 28 | ***************************************************************************** 29 | */ 30 | 31 | /* Entry Point */ 32 | ENTRY(Reset_Handler) 33 | 34 | /* Highest address of the user mode stack */ 35 | _estack = 0x20005000; /* end of RAM */ 36 | /* Generate a link error if heap and stack don't fit into RAM */ 37 | _Min_Heap_Size = 0x200; /* required amount of heap */ 38 | _Min_Stack_Size = 0x400; /* required amount of stack */ 39 | 40 | /* Specify the memory areas */ 41 | MEMORY 42 | { 43 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K 44 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K 45 | } 46 | 47 | /* Define output sections */ 48 | SECTIONS 49 | { 50 | /* The startup code goes first into FLASH */ 51 | .isr_vector : 52 | { 53 | . = ALIGN(4); 54 | KEEP(*(.isr_vector)) /* Startup code */ 55 | . = ALIGN(4); 56 | } >FLASH 57 | 58 | /* The program code and other data goes into FLASH */ 59 | .text : 60 | { 61 | . = ALIGN(4); 62 | *(.text) /* .text sections (code) */ 63 | *(.text*) /* .text* sections (code) */ 64 | *(.glue_7) /* glue arm to thumb code */ 65 | *(.glue_7t) /* glue thumb to arm code */ 66 | *(.eh_frame) 67 | 68 | KEEP (*(.init)) 69 | KEEP (*(.fini)) 70 | 71 | . = ALIGN(4); 72 | _etext = .; /* define a global symbols at end of code */ 73 | } >FLASH 74 | 75 | /* Constant data goes into FLASH */ 76 | .rodata : 77 | { 78 | . = ALIGN(4); 79 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 80 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 81 | . = ALIGN(4); 82 | } >FLASH 83 | 84 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH 85 | .ARM : { 86 | __exidx_start = .; 87 | *(.ARM.exidx*) 88 | __exidx_end = .; 89 | } >FLASH 90 | 91 | .preinit_array : 92 | { 93 | PROVIDE_HIDDEN (__preinit_array_start = .); 94 | KEEP (*(.preinit_array*)) 95 | PROVIDE_HIDDEN (__preinit_array_end = .); 96 | } >FLASH 97 | .init_array : 98 | { 99 | PROVIDE_HIDDEN (__init_array_start = .); 100 | KEEP (*(SORT(.init_array.*))) 101 | KEEP (*(.init_array*)) 102 | PROVIDE_HIDDEN (__init_array_end = .); 103 | } >FLASH 104 | .fini_array : 105 | { 106 | PROVIDE_HIDDEN (__fini_array_start = .); 107 | KEEP (*(SORT(.fini_array.*))) 108 | KEEP (*(.fini_array*)) 109 | PROVIDE_HIDDEN (__fini_array_end = .); 110 | } >FLASH 111 | 112 | /* used by the startup to initialize data */ 113 | _sidata = LOADADDR(.data); 114 | 115 | /* Initialized data sections goes into RAM, load LMA copy after code */ 116 | .data : 117 | { 118 | . = ALIGN(4); 119 | _sdata = .; /* create a global symbol at data start */ 120 | *(.data) /* .data sections */ 121 | *(.data*) /* .data* sections */ 122 | 123 | . = ALIGN(4); 124 | _edata = .; /* define a global symbol at data end */ 125 | } >RAM AT> FLASH 126 | 127 | 128 | /* Uninitialized data section */ 129 | . = ALIGN(4); 130 | .bss : 131 | { 132 | /* This is used by the startup in order to initialize the .bss secion */ 133 | _sbss = .; /* define a global symbol at bss start */ 134 | __bss_start__ = _sbss; 135 | *(.bss) 136 | *(.bss*) 137 | *(COMMON) 138 | 139 | . = ALIGN(4); 140 | _ebss = .; /* define a global symbol at bss end */ 141 | __bss_end__ = _ebss; 142 | } >RAM 143 | 144 | /* User_heap_stack section, used to check that there is enough RAM left */ 145 | ._user_heap_stack : 146 | { 147 | . = ALIGN(4); 148 | PROVIDE ( end = . ); 149 | PROVIDE ( _end = . ); 150 | . = . + _Min_Heap_Size; 151 | . = . + _Min_Stack_Size; 152 | . = ALIGN(4); 153 | } >RAM 154 | 155 | 156 | 157 | /* Remove information from the standard libraries */ 158 | /DISCARD/ : 159 | { 160 | libc.a ( * ) 161 | libm.a ( * ) 162 | libgcc.a ( * ) 163 | } 164 | 165 | .ARM.attributes 0 : { *(.ARM.attributes) } 166 | } 167 | 168 | 169 | -------------------------------------------------------------------------------- /F103-EEPROM.elf.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | -------------------------------------------------------------------------------- /syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ***************************************************************************** 3 | ** 4 | ** File : syscalls.c 5 | ** 6 | ** Abstract : System Workbench Minimal System calls file 7 | ** 8 | ** For more information about which c-functions 9 | ** need which of these lowlevel functions 10 | ** please consult the Newlib libc-manual 11 | ** 12 | ** Environment : System Workbench for MCU 13 | ** 14 | ** Distribution: The file is distributed as is without any warranty 15 | ** of any kind. 16 | ** 17 | ***************************************************************************** 18 | ** 19 | **

© COPYRIGHT(c) 2014 Ac6

20 | ** 21 | ** Redistribution and use in source and binary forms, with or without modification, 22 | ** are permitted provided that the following conditions are met: 23 | ** 1. Redistributions of source code must retain the above copyright notice, 24 | ** this list of conditions and the following disclaimer. 25 | ** 2. Redistributions in binary form must reproduce the above copyright notice, 26 | ** this list of conditions and the following disclaimer in the documentation 27 | ** and/or other materials provided with the distribution. 28 | ** 3. Neither the name of Ac6 nor the names of its contributors 29 | ** may be used to endorse or promote products derived from this software 30 | ** without specific prior written permission. 31 | ** 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 | ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 | ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 36 | ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 | ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 38 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 39 | ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 40 | ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | ** 43 | ***************************************************************************** 44 | */ 45 | 46 | /* Includes */ 47 | #include 48 | #include 49 | #include 50 | #include 51 | #include 52 | #include 53 | #include 54 | #include 55 | 56 | 57 | /* Variables */ 58 | //#undef errno 59 | extern int errno; 60 | extern int __io_putchar(int ch) __attribute__((weak)); 61 | extern int __io_getchar(void) __attribute__((weak)); 62 | 63 | register char * stack_ptr asm("sp"); 64 | 65 | char *__env[1] = { 0 }; 66 | char **environ = __env; 67 | 68 | 69 | /* Functions */ 70 | void initialise_monitor_handles() 71 | { 72 | } 73 | 74 | int _getpid(void) 75 | { 76 | return 1; 77 | } 78 | 79 | int _kill(int pid, int sig) 80 | { 81 | errno = EINVAL; 82 | return -1; 83 | } 84 | 85 | void _exit (int status) 86 | { 87 | _kill(status, -1); 88 | while (1) {} /* Make sure we hang here */ 89 | } 90 | 91 | int _read (int file, char *ptr, int len) 92 | { 93 | int DataIdx; 94 | 95 | for (DataIdx = 0; DataIdx < len; DataIdx++) 96 | { 97 | *ptr++ = __io_getchar(); 98 | } 99 | 100 | return len; 101 | } 102 | 103 | int _write(int file, char *ptr, int len) 104 | { 105 | int DataIdx; 106 | 107 | for (DataIdx = 0; DataIdx < len; DataIdx++) 108 | { 109 | __io_putchar(*ptr++); 110 | } 111 | return len; 112 | } 113 | 114 | caddr_t _sbrk(int incr) 115 | { 116 | extern char end asm("end"); 117 | static char *heap_end; 118 | char *prev_heap_end; 119 | 120 | if (heap_end == 0) 121 | heap_end = &end; 122 | 123 | prev_heap_end = heap_end; 124 | if (heap_end + incr > stack_ptr) 125 | { 126 | // write(1, "Heap and stack collision\n", 25); 127 | // abort(); 128 | errno = ENOMEM; 129 | return (caddr_t) -1; 130 | } 131 | 132 | heap_end += incr; 133 | 134 | return (caddr_t) prev_heap_end; 135 | } 136 | 137 | int _close(int file) 138 | { 139 | return -1; 140 | } 141 | 142 | 143 | int _fstat(int file, struct stat *st) 144 | { 145 | st->st_mode = S_IFCHR; 146 | return 0; 147 | } 148 | 149 | int _isatty(int file) 150 | { 151 | return 1; 152 | } 153 | 154 | int _lseek(int file, int ptr, int dir) 155 | { 156 | return 0; 157 | } 158 | 159 | int _open(char *path, int flags, ...) 160 | { 161 | /* Pretend like we always fail */ 162 | return -1; 163 | } 164 | 165 | int _wait(int *status) 166 | { 167 | errno = ECHILD; 168 | return -1; 169 | } 170 | 171 | int _unlink(char *name) 172 | { 173 | errno = ENOENT; 174 | return -1; 175 | } 176 | 177 | int _times(struct tms *buf) 178 | { 179 | return -1; 180 | } 181 | 182 | int _stat(char *file, struct stat *st) 183 | { 184 | st->st_mode = S_IFCHR; 185 | return 0; 186 | } 187 | 188 | int _link(char *old, char *new) 189 | { 190 | errno = EMLINK; 191 | return -1; 192 | } 193 | 194 | int _fork(void) 195 | { 196 | errno = EAGAIN; 197 | return -1; 198 | } 199 | 200 | int _execve(char *name, char **argv, char **env) 201 | { 202 | errno = ENOMEM; 203 | return -1; 204 | } 205 | -------------------------------------------------------------------------------- /F103-EEPROM.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | FREERTOS.INCLUDE_xTaskAbortDelay=0 3 | FREERTOS.INCLUDE_xTaskGetHandle=0 4 | FREERTOS.IPParameters=Tasks01,MEMORY_ALLOCATION,configUSE_DAEMON_TASK_STARTUP_HOOK,INCLUDE_xTaskAbortDelay,INCLUDE_xTaskGetHandle 5 | FREERTOS.MEMORY_ALLOCATION=0 6 | FREERTOS.Tasks01=defaultTask,0,128,StartDefaultTask,Default,NULL 7 | FREERTOS.configUSE_DAEMON_TASK_STARTUP_HOOK=0 8 | File.Version=6 9 | KeepUserPlacement=false 10 | Mcu.Family=STM32F1 11 | Mcu.IP0=FREERTOS 12 | Mcu.IP1=IWDG 13 | Mcu.IP2=NVIC 14 | Mcu.IP3=RCC 15 | Mcu.IP4=RTC 16 | Mcu.IP5=SPI1 17 | Mcu.IP6=SYS 18 | Mcu.IPNb=7 19 | Mcu.Name=STM32F103C(8-B)Tx 20 | Mcu.Package=LQFP48 21 | Mcu.Pin0=PC14-OSC32_IN 22 | Mcu.Pin1=PC15-OSC32_OUT 23 | Mcu.Pin10=PB4 24 | Mcu.Pin11=PB5 25 | Mcu.Pin12=VP_FREERTOS_VS_ENABLE 26 | Mcu.Pin13=VP_IWDG_VS_IWDG 27 | Mcu.Pin14=VP_RTC_VS_RTC_Activate 28 | Mcu.Pin15=VP_RTC_VS_RTC_Calendar 29 | Mcu.Pin16=VP_SYS_VS_tim2 30 | Mcu.Pin2=PD0-OSC_IN 31 | Mcu.Pin3=PD1-OSC_OUT 32 | Mcu.Pin4=PB0 33 | Mcu.Pin5=PB1 34 | Mcu.Pin6=PB10 35 | Mcu.Pin7=PA13 36 | Mcu.Pin8=PA14 37 | Mcu.Pin9=PB3 38 | Mcu.PinsNb=17 39 | Mcu.ThirdPartyNb=0 40 | Mcu.UserConstants= 41 | Mcu.UserName=STM32F103C8Tx 42 | MxCube.Version=5.0.1 43 | MxDb.Version=DB.5.0.1 44 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true 45 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:true 46 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true 47 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:true 48 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true 49 | NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true 50 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 51 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:true 52 | NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:true 53 | NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:false\:true 54 | NVIC.TimeBase=TIM2_IRQn 55 | NVIC.TimeBaseIP=TIM2 56 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true 57 | PA13.Mode=Serial_Wire 58 | PA13.Signal=SYS_JTMS-SWDIO 59 | PA14.Mode=Serial_Wire 60 | PA14.Signal=SYS_JTCK-SWCLK 61 | PB0.GPIOParameters=GPIO_Speed,PinState,GPIO_Label 62 | PB0.GPIO_Label=EEPROM_CS 63 | PB0.GPIO_Speed=GPIO_SPEED_FREQ_HIGH 64 | PB0.Locked=true 65 | PB0.PinState=GPIO_PIN_SET 66 | PB0.Signal=GPIO_Output 67 | PB1.GPIOParameters=GPIO_Speed,PinState,GPIO_Label 68 | PB1.GPIO_Label=EEPROM_WP 69 | PB1.GPIO_Speed=GPIO_SPEED_FREQ_LOW 70 | PB1.Locked=true 71 | PB1.PinState=GPIO_PIN_SET 72 | PB1.Signal=GPIO_Output 73 | PB10.GPIOParameters=PinState,GPIO_Label 74 | PB10.GPIO_Label=EEPROM_HOLD 75 | PB10.Locked=true 76 | PB10.PinState=GPIO_PIN_SET 77 | PB10.Signal=GPIO_Output 78 | PB3.Locked=true 79 | PB3.Mode=Full_Duplex_Master 80 | PB3.Signal=SPI1_SCK 81 | PB4.Locked=true 82 | PB4.Mode=Full_Duplex_Master 83 | PB4.Signal=SPI1_MISO 84 | PB5.Locked=true 85 | PB5.Mode=Full_Duplex_Master 86 | PB5.Signal=SPI1_MOSI 87 | PC14-OSC32_IN.Mode=LSE-External-Oscillator 88 | PC14-OSC32_IN.Signal=RCC_OSC32_IN 89 | PC15-OSC32_OUT.Mode=LSE-External-Oscillator 90 | PC15-OSC32_OUT.Signal=RCC_OSC32_OUT 91 | PCC.Checker=false 92 | PCC.Line=STM32F103 93 | PCC.MCU=STM32F103C(8-B)Tx 94 | PCC.PartNumber=STM32F103C8Tx 95 | PCC.Seq0=0 96 | PCC.Series=STM32F1 97 | PCC.Temperature=25 98 | PCC.Vdd=3.3 99 | PD0-OSC_IN.Mode=HSE-External-Oscillator 100 | PD0-OSC_IN.Signal=RCC_OSC_IN 101 | PD1-OSC_OUT.Mode=HSE-External-Oscillator 102 | PD1-OSC_OUT.Signal=RCC_OSC_OUT 103 | PinOutPanel.RotationAngle=0 104 | ProjectManager.AskForMigrate=true 105 | ProjectManager.BackupPrevious=false 106 | ProjectManager.CompilerOptimize=2 107 | ProjectManager.ComputerToolchain=false 108 | ProjectManager.CoupleFile=false 109 | ProjectManager.CustomerFirmwarePackage= 110 | ProjectManager.DefaultFWLocation=true 111 | ProjectManager.DeletePrevious=true 112 | ProjectManager.DeviceId=STM32F103C8Tx 113 | ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.7.0 114 | ProjectManager.FreePins=false 115 | ProjectManager.HalAssertFull=false 116 | ProjectManager.HeapSize=0x200 117 | ProjectManager.KeepUserCode=true 118 | ProjectManager.LastFirmware=true 119 | ProjectManager.LibraryCopy=2 120 | ProjectManager.MainLocation=Src 121 | ProjectManager.NoMain=false 122 | ProjectManager.PreviousToolchain=TrueSTUDIO 123 | ProjectManager.ProjectBuild=false 124 | ProjectManager.ProjectFileName=F103-EEPROM.ioc 125 | ProjectManager.ProjectName=F103-EEPROM 126 | ProjectManager.StackSize=0x400 127 | ProjectManager.TargetToolchain=TrueSTUDIO 128 | ProjectManager.ToolChainLocation= 129 | ProjectManager.UnderRoot=true 130 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-true,3-MX_IWDG_Init-IWDG-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true 131 | RCC.ADCFreqValue=36000000 132 | RCC.AHBFreq_Value=72000000 133 | RCC.APB1CLKDivider=RCC_HCLK_DIV2 134 | RCC.APB1Freq_Value=36000000 135 | RCC.APB1TimFreq_Value=72000000 136 | RCC.APB2Freq_Value=72000000 137 | RCC.APB2TimFreq_Value=72000000 138 | RCC.FCLKCortexFreq_Value=72000000 139 | RCC.FamilyName=M 140 | RCC.HCLKFreq_Value=72000000 141 | RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value 142 | RCC.MCOFreq_Value=72000000 143 | RCC.PLLCLKFreq_Value=72000000 144 | RCC.PLLMCOFreq_Value=36000000 145 | RCC.PLLMUL=RCC_PLL_MUL9 146 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE 147 | RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE 148 | RCC.RTCFreq_Value=32768 149 | RCC.SYSCLKFreq_VALUE=72000000 150 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 151 | RCC.TimSysFreq_Value=72000000 152 | RCC.USBFreq_Value=72000000 153 | RCC.VCOOutput2Freq_Value=8000000 154 | SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8 155 | SPI1.CalculateBaudRate=9.0 MBits/s 156 | SPI1.Direction=SPI_DIRECTION_2LINES 157 | SPI1.IPParameters=Mode,CalculateBaudRate,BaudRatePrescaler,VirtualType,Direction 158 | SPI1.Mode=SPI_MODE_MASTER 159 | SPI1.VirtualType=VM_MASTER 160 | VP_FREERTOS_VS_ENABLE.Mode=Enabled 161 | VP_FREERTOS_VS_ENABLE.Signal=FREERTOS_VS_ENABLE 162 | VP_IWDG_VS_IWDG.Mode=IWDG_Activate 163 | VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG 164 | VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled 165 | VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate 166 | VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar 167 | VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar 168 | VP_SYS_VS_tim2.Mode=TIM2 169 | VP_SYS_VS_tim2.Signal=SYS_VS_tim2 170 | board=F103-EEPROM 171 | -------------------------------------------------------------------------------- /Src/stm32f1xx_hal_timebase_TIM.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_timebase_TIM.c 4 | * @brief HAL time base based on the hardware TIM. 5 | ****************************************************************************** 6 | * 7 | * Copyright (c) 2017 STMicroelectronics International N.V. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted, provided that the following conditions are met: 12 | * 13 | * 1. Redistribution of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 3. Neither the name of STMicroelectronics nor the names of other 19 | * contributors to this software may be used to endorse or promote products 20 | * derived from this software without specific written permission. 21 | * 4. This software, including modifications and/or derivative works of this 22 | * software, must execute solely and exclusively on microcontroller or 23 | * microprocessor devices manufactured by or for STMicroelectronics. 24 | * 5. Redistribution and use of this software other than as permitted under 25 | * this license is void and will automatically terminate your rights under 26 | * this license. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 29 | * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 31 | * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY 32 | * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 33 | * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 36 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 37 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 38 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 39 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 | * 41 | ****************************************************************************** 42 | */ 43 | 44 | /* Includes ------------------------------------------------------------------*/ 45 | #include "stm32f1xx_hal.h" 46 | #include "stm32f1xx_hal_tim.h" 47 | /** @addtogroup STM32F7xx_HAL_Examples 48 | * @{ 49 | */ 50 | 51 | /** @addtogroup HAL_TimeBase 52 | * @{ 53 | */ 54 | 55 | /* Private typedef -----------------------------------------------------------*/ 56 | /* Private define ------------------------------------------------------------*/ 57 | /* Private macro -------------------------------------------------------------*/ 58 | /* Private variables ---------------------------------------------------------*/ 59 | TIM_HandleTypeDef htim2; 60 | uint32_t uwIncrementState = 0; 61 | /* Private function prototypes -----------------------------------------------*/ 62 | /* Private functions ---------------------------------------------------------*/ 63 | 64 | /** 65 | * @brief This function configures the TIM2 as a time base source. 66 | * The time source is configured to have 1ms time base with a dedicated 67 | * Tick interrupt priority. 68 | * @note This function is called automatically at the beginning of program after 69 | * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 70 | * @param TickPriority: Tick interrupt priorty. 71 | * @retval HAL status 72 | */ 73 | HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) 74 | { 75 | RCC_ClkInitTypeDef clkconfig; 76 | uint32_t uwTimclock = 0; 77 | uint32_t uwPrescalerValue = 0; 78 | uint32_t pFLatency; 79 | 80 | /*Configure the TIM2 IRQ priority */ 81 | HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0); 82 | 83 | /* Enable the TIM2 global Interrupt */ 84 | HAL_NVIC_EnableIRQ(TIM2_IRQn); 85 | 86 | /* Enable TIM2 clock */ 87 | __HAL_RCC_TIM2_CLK_ENABLE(); 88 | 89 | /* Get clock configuration */ 90 | HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 91 | 92 | /* Compute TIM2 clock */ 93 | uwTimclock = 2*HAL_RCC_GetPCLK1Freq(); 94 | 95 | /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ 96 | uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); 97 | 98 | /* Initialize TIM2 */ 99 | htim2.Instance = TIM2; 100 | 101 | /* Initialize TIMx peripheral as follow: 102 | + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base. 103 | + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. 104 | + ClockDivision = 0 105 | + Counter direction = Up 106 | */ 107 | htim2.Init.Period = (1000000 / 1000) - 1; 108 | htim2.Init.Prescaler = uwPrescalerValue; 109 | htim2.Init.ClockDivision = 0; 110 | htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 111 | if(HAL_TIM_Base_Init(&htim2) == HAL_OK) 112 | { 113 | /* Start the TIM time Base generation in interrupt mode */ 114 | return HAL_TIM_Base_Start_IT(&htim2); 115 | } 116 | 117 | /* Return function status */ 118 | return HAL_ERROR; 119 | } 120 | 121 | /** 122 | * @brief Suspend Tick increment. 123 | * @note Disable the tick increment by disabling TIM2 update interrupt. 124 | * @param None 125 | * @retval None 126 | */ 127 | void HAL_SuspendTick(void) 128 | { 129 | /* Disable TIM2 update Interrupt */ 130 | __HAL_TIM_DISABLE_IT(&htim2, TIM_IT_UPDATE); 131 | } 132 | 133 | /** 134 | * @brief Resume Tick increment. 135 | * @note Enable the tick increment by Enabling TIM2 update interrupt. 136 | * @param None 137 | * @retval None 138 | */ 139 | void HAL_ResumeTick(void) 140 | { 141 | /* Enable TIM2 Update interrupt */ 142 | __HAL_TIM_ENABLE_IT(&htim2, TIM_IT_UPDATE); 143 | } 144 | 145 | /** 146 | * @} 147 | */ 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 154 | -------------------------------------------------------------------------------- /Src/stm32f1xx_hal_timebase_tim.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_hal_timebase_TIM.c 5 | * @brief HAL time base based on the hardware TIM. 6 | ****************************************************************************** 7 | * This notice applies to any and all portions of this file 8 | * that are not between comment pairs USER CODE BEGIN and 9 | * USER CODE END. Other portions of this file, whether 10 | * inserted by the user or by software development tools 11 | * are owned by their respective copyright owners. 12 | * 13 | * Copyright (c) 2019 STMicroelectronics International N.V. 14 | * All rights reserved. 15 | * 16 | * Redistribution and use in source and binary forms, with or without 17 | * modification, are permitted, provided that the following conditions are met: 18 | * 19 | * 1. Redistribution of source code must retain the above copyright notice, 20 | * this list of conditions and the following disclaimer. 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, 22 | * this list of conditions and the following disclaimer in the documentation 23 | * and/or other materials provided with the distribution. 24 | * 3. Neither the name of STMicroelectronics nor the names of other 25 | * contributors to this software may be used to endorse or promote products 26 | * derived from this software without specific written permission. 27 | * 4. This software, including modifications and/or derivative works of this 28 | * software, must execute solely and exclusively on microcontroller or 29 | * microprocessor devices manufactured by or for STMicroelectronics. 30 | * 5. Redistribution and use of this software other than as permitted under 31 | * this license is void and will automatically terminate your rights under 32 | * this license. 33 | * 34 | * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 35 | * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 36 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 37 | * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY 38 | * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 39 | * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 40 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 42 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 43 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 44 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 45 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 | * 47 | ****************************************************************************** 48 | */ 49 | /* USER CODE END Header */ 50 | 51 | /* Includes ------------------------------------------------------------------*/ 52 | #include "stm32f1xx_hal.h" 53 | #include "stm32f1xx_hal_tim.h" 54 | 55 | /* Private typedef -----------------------------------------------------------*/ 56 | /* Private define ------------------------------------------------------------*/ 57 | /* Private macro -------------------------------------------------------------*/ 58 | /* Private variables ---------------------------------------------------------*/ 59 | TIM_HandleTypeDef htim2; 60 | /* Private function prototypes -----------------------------------------------*/ 61 | /* Private functions ---------------------------------------------------------*/ 62 | 63 | /** 64 | * @brief This function configures the TIM2 as a time base source. 65 | * The time source is configured to have 1ms time base with a dedicated 66 | * Tick interrupt priority. 67 | * @note This function is called automatically at the beginning of program after 68 | * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 69 | * @param TickPriority: Tick interrupt priority. 70 | * @retval HAL status 71 | */ 72 | HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) 73 | { 74 | RCC_ClkInitTypeDef clkconfig; 75 | uint32_t uwTimclock = 0; 76 | uint32_t uwPrescalerValue = 0; 77 | uint32_t pFLatency; 78 | 79 | /*Configure the TIM2 IRQ priority */ 80 | HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0); 81 | 82 | /* Enable the TIM2 global Interrupt */ 83 | HAL_NVIC_EnableIRQ(TIM2_IRQn); 84 | 85 | /* Enable TIM2 clock */ 86 | __HAL_RCC_TIM2_CLK_ENABLE(); 87 | 88 | /* Get clock configuration */ 89 | HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 90 | 91 | /* Compute TIM2 clock */ 92 | uwTimclock = 2*HAL_RCC_GetPCLK1Freq(); 93 | 94 | /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ 95 | uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); 96 | 97 | /* Initialize TIM2 */ 98 | htim2.Instance = TIM2; 99 | 100 | /* Initialize TIMx peripheral as follow: 101 | + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base. 102 | + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. 103 | + ClockDivision = 0 104 | + Counter direction = Up 105 | */ 106 | htim2.Init.Period = (1000000 / 1000) - 1; 107 | htim2.Init.Prescaler = uwPrescalerValue; 108 | htim2.Init.ClockDivision = 0; 109 | htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 110 | if(HAL_TIM_Base_Init(&htim2) == HAL_OK) 111 | { 112 | /* Start the TIM time Base generation in interrupt mode */ 113 | return HAL_TIM_Base_Start_IT(&htim2); 114 | } 115 | 116 | /* Return function status */ 117 | return HAL_ERROR; 118 | } 119 | 120 | /** 121 | * @brief Suspend Tick increment. 122 | * @note Disable the tick increment by disabling TIM2 update interrupt. 123 | * @param None 124 | * @retval None 125 | */ 126 | void HAL_SuspendTick(void) 127 | { 128 | /* Disable TIM2 update Interrupt */ 129 | __HAL_TIM_DISABLE_IT(&htim2, TIM_IT_UPDATE); 130 | } 131 | 132 | /** 133 | * @brief Resume Tick increment. 134 | * @note Enable the tick increment by Enabling TIM2 update interrupt. 135 | * @param None 136 | * @retval None 137 | */ 138 | void HAL_ResumeTick(void) 139 | { 140 | /* Enable TIM2 Update interrupt */ 141 | __HAL_TIM_ENABLE_IT(&htim2, TIM_IT_UPDATE); 142 | } 143 | 144 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 145 | -------------------------------------------------------------------------------- /Src/stm32f1xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * 8 | * COPYRIGHT(c) 2019 STMicroelectronics 9 | * 10 | * Redistribution and use in source and binary forms, with or without modification, 11 | * are permitted provided that the following conditions are met: 12 | * 1. Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 2. Redistributions in binary form must reproduce the above copyright notice, 15 | * this list of conditions and the following disclaimer in the documentation 16 | * and/or other materials provided with the distribution. 17 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 18 | * may be used to endorse or promote products derived from this software 19 | * without specific prior written permission. 20 | * 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 25 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 28 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 | * 32 | ****************************************************************************** 33 | */ 34 | /* USER CODE END Header */ 35 | 36 | /* Includes ------------------------------------------------------------------*/ 37 | #include "main.h" 38 | #include "stm32f1xx_it.h" 39 | #include "cmsis_os.h" 40 | /* Private includes ----------------------------------------------------------*/ 41 | /* USER CODE BEGIN Includes */ 42 | /* USER CODE END Includes */ 43 | 44 | /* Private typedef -----------------------------------------------------------*/ 45 | /* USER CODE BEGIN TD */ 46 | 47 | /* USER CODE END TD */ 48 | 49 | /* Private define ------------------------------------------------------------*/ 50 | /* USER CODE BEGIN PD */ 51 | 52 | /* USER CODE END PD */ 53 | 54 | /* Private macro -------------------------------------------------------------*/ 55 | /* USER CODE BEGIN PM */ 56 | 57 | /* USER CODE END PM */ 58 | 59 | /* Private variables ---------------------------------------------------------*/ 60 | /* USER CODE BEGIN PV */ 61 | 62 | /* USER CODE END PV */ 63 | 64 | /* Private function prototypes -----------------------------------------------*/ 65 | /* USER CODE BEGIN PFP */ 66 | 67 | /* USER CODE END PFP */ 68 | 69 | /* Private user code ---------------------------------------------------------*/ 70 | /* USER CODE BEGIN 0 */ 71 | 72 | /* USER CODE END 0 */ 73 | 74 | /* External variables --------------------------------------------------------*/ 75 | extern TIM_HandleTypeDef htim2; 76 | 77 | /* USER CODE BEGIN EV */ 78 | 79 | /* USER CODE END EV */ 80 | 81 | /******************************************************************************/ 82 | /* Cortex-M3 Processor Interruption and Exception Handlers */ 83 | /******************************************************************************/ 84 | /** 85 | * @brief This function handles Non maskable interrupt. 86 | */ 87 | void NMI_Handler(void) { 88 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 89 | 90 | /* USER CODE END NonMaskableInt_IRQn 0 */ 91 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 92 | 93 | /* USER CODE END NonMaskableInt_IRQn 1 */ 94 | } 95 | 96 | /** 97 | * @brief This function handles Hard fault interrupt. 98 | */ 99 | void HardFault_Handler(void) { 100 | /* USER CODE BEGIN HardFault_IRQn 0 */ 101 | 102 | /* USER CODE END HardFault_IRQn 0 */ 103 | while (1) { 104 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 105 | /* USER CODE END W1_HardFault_IRQn 0 */ 106 | } 107 | } 108 | 109 | /** 110 | * @brief This function handles Memory management fault. 111 | */ 112 | void MemManage_Handler(void) { 113 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 114 | 115 | /* USER CODE END MemoryManagement_IRQn 0 */ 116 | while (1) { 117 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 118 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 119 | } 120 | } 121 | 122 | /** 123 | * @brief This function handles Prefetch fault, memory access fault. 124 | */ 125 | void BusFault_Handler(void) { 126 | /* USER CODE BEGIN BusFault_IRQn 0 */ 127 | 128 | /* USER CODE END BusFault_IRQn 0 */ 129 | while (1) { 130 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 131 | /* USER CODE END W1_BusFault_IRQn 0 */ 132 | } 133 | } 134 | 135 | /** 136 | * @brief This function handles Undefined instruction or illegal state. 137 | */ 138 | void UsageFault_Handler(void) { 139 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 140 | 141 | /* USER CODE END UsageFault_IRQn 0 */ 142 | while (1) { 143 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 144 | /* USER CODE END W1_UsageFault_IRQn 0 */ 145 | } 146 | } 147 | 148 | /** 149 | * @brief This function handles Debug monitor. 150 | */ 151 | void DebugMon_Handler(void) { 152 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 153 | 154 | /* USER CODE END DebugMonitor_IRQn 0 */ 155 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 156 | 157 | /* USER CODE END DebugMonitor_IRQn 1 */ 158 | } 159 | 160 | /******************************************************************************/ 161 | /* STM32F1xx Peripheral Interrupt Handlers */ 162 | /* Add here the Interrupt Handlers for the used peripherals. */ 163 | /* For the available peripheral interrupt handler names, */ 164 | /* please refer to the startup file (startup_stm32f1xx.s). */ 165 | /******************************************************************************/ 166 | 167 | /** 168 | * @brief This function handles TIM2 global interrupt. 169 | */ 170 | void TIM2_IRQHandler(void) { 171 | /* USER CODE BEGIN TIM2_IRQn 0 */ 172 | 173 | /* USER CODE END TIM2_IRQn 0 */ 174 | HAL_TIM_IRQHandler(&htim2); 175 | /* USER CODE BEGIN TIM2_IRQn 1 */ 176 | 177 | /* USER CODE END TIM2_IRQn 1 */ 178 | } 179 | 180 | /* USER CODE BEGIN 1 */ 181 | 182 | /* USER CODE END 1 */ 183 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 184 | -------------------------------------------------------------------------------- /Src/stm32f1xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * File Name : stm32f1xx_hal_msp.c 5 | * Description : This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * This notice applies to any and all portions of this file 9 | * that are not between comment pairs USER CODE BEGIN and 10 | * USER CODE END. Other portions of this file, whether 11 | * inserted by the user or by software development tools 12 | * are owned by their respective copyright owners. 13 | * 14 | * Copyright (c) 2019 STMicroelectronics International N.V. 15 | * All rights reserved. 16 | * 17 | * Redistribution and use in source and binary forms, with or without 18 | * modification, are permitted, provided that the following conditions are met: 19 | * 20 | * 1. Redistribution of source code must retain the above copyright notice, 21 | * this list of conditions and the following disclaimer. 22 | * 2. Redistributions in binary form must reproduce the above copyright notice, 23 | * this list of conditions and the following disclaimer in the documentation 24 | * and/or other materials provided with the distribution. 25 | * 3. Neither the name of STMicroelectronics nor the names of other 26 | * contributors to this software may be used to endorse or promote products 27 | * derived from this software without specific written permission. 28 | * 4. This software, including modifications and/or derivative works of this 29 | * software, must execute solely and exclusively on microcontroller or 30 | * microprocessor devices manufactured by or for STMicroelectronics. 31 | * 5. Redistribution and use of this software other than as permitted under 32 | * this license is void and will automatically terminate your rights under 33 | * this license. 34 | * 35 | * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 36 | * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 37 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 38 | * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY 39 | * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 40 | * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 41 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 43 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 44 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 45 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 46 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 | * 48 | ****************************************************************************** 49 | */ 50 | /* USER CODE END Header */ 51 | 52 | /* Includes ------------------------------------------------------------------*/ 53 | #include "main.h" 54 | /* USER CODE BEGIN Includes */ 55 | 56 | /* USER CODE END Includes */ 57 | 58 | /* Private typedef -----------------------------------------------------------*/ 59 | /* USER CODE BEGIN TD */ 60 | 61 | /* USER CODE END TD */ 62 | 63 | /* Private define ------------------------------------------------------------*/ 64 | /* USER CODE BEGIN Define */ 65 | 66 | /* USER CODE END Define */ 67 | 68 | /* Private macro -------------------------------------------------------------*/ 69 | /* USER CODE BEGIN Macro */ 70 | 71 | /* USER CODE END Macro */ 72 | 73 | /* Private variables ---------------------------------------------------------*/ 74 | /* USER CODE BEGIN PV */ 75 | 76 | /* USER CODE END PV */ 77 | 78 | /* Private function prototypes -----------------------------------------------*/ 79 | /* USER CODE BEGIN PFP */ 80 | 81 | /* USER CODE END PFP */ 82 | 83 | /* External functions --------------------------------------------------------*/ 84 | /* USER CODE BEGIN ExternalFunctions */ 85 | 86 | /* USER CODE END ExternalFunctions */ 87 | 88 | /* USER CODE BEGIN 0 */ 89 | 90 | /* USER CODE END 0 */ 91 | /** 92 | * Initializes the Global MSP. 93 | */ 94 | void HAL_MspInit(void) 95 | { 96 | /* USER CODE BEGIN MspInit 0 */ 97 | 98 | /* USER CODE END MspInit 0 */ 99 | 100 | __HAL_RCC_AFIO_CLK_ENABLE(); 101 | __HAL_RCC_PWR_CLK_ENABLE(); 102 | 103 | /* System interrupt init*/ 104 | /* PendSV_IRQn interrupt configuration */ 105 | HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 106 | 107 | /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled 108 | */ 109 | __HAL_AFIO_REMAP_SWJ_NOJTAG(); 110 | 111 | /* USER CODE BEGIN MspInit 1 */ 112 | 113 | /* USER CODE END MspInit 1 */ 114 | } 115 | 116 | /** 117 | * @brief RTC MSP Initialization 118 | * This function configures the hardware resources used in this example 119 | * @param hrtc: RTC handle pointer 120 | * @retval None 121 | */ 122 | void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) 123 | { 124 | 125 | if(hrtc->Instance==RTC) 126 | { 127 | /* USER CODE BEGIN RTC_MspInit 0 */ 128 | 129 | /* USER CODE END RTC_MspInit 0 */ 130 | HAL_PWR_EnableBkUpAccess(); 131 | /* Enable BKP CLK enable for backup registers */ 132 | __HAL_RCC_BKP_CLK_ENABLE(); 133 | /* Peripheral clock enable */ 134 | __HAL_RCC_RTC_ENABLE(); 135 | /* USER CODE BEGIN RTC_MspInit 1 */ 136 | 137 | /* USER CODE END RTC_MspInit 1 */ 138 | } 139 | 140 | } 141 | 142 | /** 143 | * @brief RTC MSP De-Initialization 144 | * This function freeze the hardware resources used in this example 145 | * @param hrtc: RTC handle pointer 146 | * @retval None 147 | */ 148 | 149 | void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) 150 | { 151 | 152 | if(hrtc->Instance==RTC) 153 | { 154 | /* USER CODE BEGIN RTC_MspDeInit 0 */ 155 | 156 | /* USER CODE END RTC_MspDeInit 0 */ 157 | /* Peripheral clock disable */ 158 | __HAL_RCC_RTC_DISABLE(); 159 | /* USER CODE BEGIN RTC_MspDeInit 1 */ 160 | 161 | /* USER CODE END RTC_MspDeInit 1 */ 162 | } 163 | 164 | } 165 | 166 | /** 167 | * @brief SPI MSP Initialization 168 | * This function configures the hardware resources used in this example 169 | * @param hspi: SPI handle pointer 170 | * @retval None 171 | */ 172 | void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) 173 | { 174 | 175 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 176 | if(hspi->Instance==SPI1) 177 | { 178 | /* USER CODE BEGIN SPI1_MspInit 0 */ 179 | 180 | /* USER CODE END SPI1_MspInit 0 */ 181 | /* Peripheral clock enable */ 182 | __HAL_RCC_SPI1_CLK_ENABLE(); 183 | 184 | __HAL_RCC_GPIOB_CLK_ENABLE(); 185 | /**SPI1 GPIO Configuration 186 | PB3 ------> SPI1_SCK 187 | PB4 ------> SPI1_MISO 188 | PB5 ------> SPI1_MOSI 189 | */ 190 | GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; 191 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 192 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 193 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 194 | 195 | GPIO_InitStruct.Pin = GPIO_PIN_4; 196 | GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 197 | GPIO_InitStruct.Pull = GPIO_NOPULL; 198 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 199 | 200 | __HAL_AFIO_REMAP_SPI1_ENABLE(); 201 | 202 | /* USER CODE BEGIN SPI1_MspInit 1 */ 203 | 204 | /* USER CODE END SPI1_MspInit 1 */ 205 | } 206 | 207 | } 208 | 209 | /** 210 | * @brief SPI MSP De-Initialization 211 | * This function freeze the hardware resources used in this example 212 | * @param hspi: SPI handle pointer 213 | * @retval None 214 | */ 215 | 216 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) 217 | { 218 | 219 | if(hspi->Instance==SPI1) 220 | { 221 | /* USER CODE BEGIN SPI1_MspDeInit 0 */ 222 | 223 | /* USER CODE END SPI1_MspDeInit 0 */ 224 | /* Peripheral clock disable */ 225 | __HAL_RCC_SPI1_CLK_DISABLE(); 226 | 227 | /**SPI1 GPIO Configuration 228 | PB3 ------> SPI1_SCK 229 | PB4 ------> SPI1_MISO 230 | PB5 ------> SPI1_MOSI 231 | */ 232 | HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); 233 | 234 | /* USER CODE BEGIN SPI1_MspDeInit 1 */ 235 | 236 | /* USER CODE END SPI1_MspDeInit 1 */ 237 | } 238 | 239 | } 240 | 241 | /* USER CODE BEGIN 1 */ 242 | 243 | /* USER CODE END 1 */ 244 | 245 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 246 | -------------------------------------------------------------------------------- /Inc/FreeRTOSConfig.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /* 3 | FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. 4 | All rights reserved 5 | 6 | VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. 7 | 8 | This file is part of the FreeRTOS distribution. 9 | 10 | FreeRTOS is free software; you can redistribute it and/or modify it under 11 | the terms of the GNU General Public License (version 2) as published by the 12 | Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. 13 | 14 | *************************************************************************** 15 | >>! NOTE: The modification to the GPL is included to allow you to !<< 16 | >>! distribute a combined work that includes FreeRTOS without being !<< 17 | >>! obliged to provide the source code for proprietary components !<< 18 | >>! outside of the FreeRTOS kernel. !<< 19 | *************************************************************************** 20 | 21 | FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY 22 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 23 | FOR A PARTICULAR PURPOSE. Full license text is available on the following 24 | link: http://www.freertos.org/a00114.html 25 | 26 | *************************************************************************** 27 | * * 28 | * FreeRTOS provides completely free yet professionally developed, * 29 | * robust, strictly quality controlled, supported, and cross * 30 | * platform software that is more than just the market leader, it * 31 | * is the industry's de facto standard. * 32 | * * 33 | * Help yourself get started quickly while simultaneously helping * 34 | * to support the FreeRTOS project by purchasing a FreeRTOS * 35 | * tutorial book, reference manual, or both: * 36 | * http://www.FreeRTOS.org/Documentation * 37 | * * 38 | *************************************************************************** 39 | 40 | http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading 41 | the FAQ page "My application does not run, what could be wrong?". Have you 42 | defined configASSERT()? 43 | 44 | http://www.FreeRTOS.org/support - In return for receiving this top quality 45 | embedded software for free we request you assist our global community by 46 | participating in the support forum. 47 | 48 | http://www.FreeRTOS.org/training - Investing in training allows your team to 49 | be as productive as possible as early as possible. Now you can receive 50 | FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers 51 | Ltd, and the world's leading authority on the world's leading RTOS. 52 | 53 | http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, 54 | including FreeRTOS+Trace - an indispensable productivity tool, a DOS 55 | compatible FAT file system, and our tiny thread aware UDP/IP stack. 56 | 57 | http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. 58 | Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. 59 | 60 | http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High 61 | Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS 62 | licenses offer ticketed support, indemnification and commercial middleware. 63 | 64 | http://www.SafeRTOS.com - High Integrity Systems also provide a safety 65 | engineered and independently SIL3 certified version for use in safety and 66 | mission critical applications that require provable dependability. 67 | 68 | 1 tab == 4 spaces! 69 | */ 70 | /* USER CODE END Header */ 71 | 72 | #ifndef FREERTOS_CONFIG_H 73 | #define FREERTOS_CONFIG_H 74 | 75 | /*----------------------------------------------------------- 76 | * Application specific definitions. 77 | * 78 | * These definitions should be adjusted for your particular hardware and 79 | * application requirements. 80 | * 81 | * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE 82 | * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 83 | * 84 | * See http://www.freertos.org/a00110.html. 85 | *----------------------------------------------------------*/ 86 | 87 | /* USER CODE BEGIN Includes */ 88 | /* Section where include file can be added */ 89 | /* USER CODE END Includes */ 90 | 91 | /* Ensure stdint is only used by the compiler, and not the assembler. */ 92 | #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) 93 | #include 94 | extern uint32_t SystemCoreClock; 95 | #endif 96 | 97 | #define configUSE_PREEMPTION 1 98 | #define configSUPPORT_STATIC_ALLOCATION 0 99 | #define configSUPPORT_DYNAMIC_ALLOCATION 1 100 | #define configUSE_IDLE_HOOK 0 101 | #define configUSE_TICK_HOOK 0 102 | #define configCPU_CLOCK_HZ ( SystemCoreClock ) 103 | #define configTICK_RATE_HZ ((TickType_t)1000) 104 | #define configMAX_PRIORITIES ( 7 ) 105 | #define configMINIMAL_STACK_SIZE ((uint16_t)128) 106 | #define configTOTAL_HEAP_SIZE ((size_t)3072) 107 | #define configMAX_TASK_NAME_LEN ( 16 ) 108 | #define configUSE_16_BIT_TICKS 0 109 | #define configUSE_MUTEXES 1 110 | #define configQUEUE_REGISTRY_SIZE 8 111 | #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 112 | 113 | /* Co-routine definitions. */ 114 | #define configUSE_CO_ROUTINES 0 115 | #define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) 116 | 117 | /* Set the following definitions to 1 to include the API function, or zero 118 | to exclude the API function. */ 119 | #define INCLUDE_vTaskPrioritySet 1 120 | #define INCLUDE_uxTaskPriorityGet 1 121 | #define INCLUDE_vTaskDelete 1 122 | #define INCLUDE_vTaskCleanUpResources 0 123 | #define INCLUDE_vTaskSuspend 1 124 | #define INCLUDE_vTaskDelayUntil 0 125 | #define INCLUDE_vTaskDelay 1 126 | #define INCLUDE_xTaskGetSchedulerState 1 127 | 128 | /* Cortex-M specific definitions. */ 129 | #ifdef __NVIC_PRIO_BITS 130 | /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ 131 | #define configPRIO_BITS __NVIC_PRIO_BITS 132 | #else 133 | #define configPRIO_BITS 4 134 | #endif 135 | 136 | /* The lowest interrupt priority that can be used in a call to a "set priority" 137 | function. */ 138 | #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 139 | 140 | /* The highest interrupt priority that can be used by any interrupt service 141 | routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL 142 | INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER 143 | PRIORITY THAN THIS! (higher priorities are lower numeric values. */ 144 | #define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 145 | 146 | /* Interrupt priorities used by the kernel port layer itself. These are generic 147 | to all Cortex-M ports, and do not rely on any particular library functions. */ 148 | #define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) 149 | /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! 150 | See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ 151 | #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) 152 | 153 | /* Normal assert() semantics without relying on the provision of an assert.h 154 | header file. */ 155 | /* USER CODE BEGIN 1 */ 156 | #define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} 157 | /* USER CODE END 1 */ 158 | 159 | /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS 160 | standard names. */ 161 | #define vPortSVCHandler SVC_Handler 162 | #define xPortPendSVHandler PendSV_Handler 163 | 164 | /* IMPORTANT: This define is commented when used with STM32Cube firmware, when timebase is systick, 165 | to prevent overwriting SysTick_Handler defined within STM32Cube HAL */ 166 | #define xPortSysTickHandler SysTick_Handler 167 | 168 | /* USER CODE BEGIN Defines */ 169 | /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ 170 | /* USER CODE END Defines */ 171 | 172 | #endif /* FREERTOS_CONFIG_H */ 173 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | F103-EEPROM 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | ?children? 14 | ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| 15 | 16 | 17 | ?name? 18 | 19 | 20 | 21 | org.eclipse.cdt.make.core.append_environment 22 | true 23 | 24 | 25 | org.eclipse.cdt.make.core.buildArguments 26 | 27 | 28 | 29 | org.eclipse.cdt.make.core.buildCommand 30 | make 31 | 32 | 33 | org.eclipse.cdt.make.core.buildLocation 34 | ${workspace_loc:/STM32100B-EVAL/Debug} 35 | 36 | 37 | org.eclipse.cdt.make.core.contents 38 | org.eclipse.cdt.make.core.activeConfigSettings 39 | 40 | 41 | org.eclipse.cdt.make.core.enableAutoBuild 42 | false 43 | 44 | 45 | org.eclipse.cdt.make.core.enableCleanBuild 46 | true 47 | 48 | 49 | org.eclipse.cdt.make.core.enableFullBuild 50 | true 51 | 52 | 53 | org.eclipse.cdt.make.core.stopOnError 54 | true 55 | 56 | 57 | org.eclipse.cdt.make.core.useDefaultBuildCmd 58 | true 59 | 60 | 61 | 62 | 63 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 64 | 65 | 66 | 67 | 68 | 69 | org.eclipse.cdt.core.cnature 70 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 71 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 72 | 73 | 74 | 75 | 76 | Drivers 77 | 2 78 | virtual:/virtual 79 | 80 | Drivers/STM32F1xx_HAL_Driver 81 | 2 82 | virtual:/virtual 83 | 84 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_gpio_ex.c 85 | 1 86 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c 87 | 88 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_iwdg.c 89 | 1 90 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c 91 | 92 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_rtc.c 93 | 1 94 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c 95 | 96 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_rtc_ex.c 97 | 1 98 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c 99 | 100 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_spi.c 101 | 1 102 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c 103 | 104 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_spi_ex.c 105 | 1 106 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c 107 | 108 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_tim.c 109 | 1 110 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c 111 | 112 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_tim_ex.c 113 | 1 114 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c 115 | 116 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal.c 117 | 1 118 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c 119 | 120 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_rcc.c 121 | 1 122 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c 123 | 124 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_rcc_ex.c 125 | 1 126 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c 127 | 128 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_gpio.c 129 | 1 130 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c 131 | 132 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_dma.c 133 | 1 134 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c 135 | 136 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_cortex.c 137 | 1 138 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c 139 | 140 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_pwr.c 141 | 1 142 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c 143 | 144 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_flash.c 145 | 1 146 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c 147 | 148 | Drivers/STM32F1xx_HAL_Driver/stm32f1xx_hal_flash_ex.c 149 | 1 150 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c 151 | 152 | Middlewares 153 | 2 154 | virtual:/virtual 155 | 156 | Middlewares/FreeRTOS 157 | 2 158 | virtual:/virtual 159 | 160 | Middlewares/FreeRTOS/croutine.c 161 | 1 162 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/croutine.c 163 | 164 | Middlewares/FreeRTOS/event_groups.c 165 | 1 166 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c 167 | 168 | Middlewares/FreeRTOS/list.c 169 | 1 170 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/list.c 171 | 172 | Middlewares/FreeRTOS/queue.c 173 | 1 174 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/queue.c 175 | 176 | Middlewares/FreeRTOS/tasks.c 177 | 1 178 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/tasks.c 179 | 180 | Middlewares/FreeRTOS/timers.c 181 | 1 182 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/timers.c 183 | 184 | Middlewares/FreeRTOS/cmsis_os.c 185 | 1 186 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c 187 | 188 | Middlewares/FreeRTOS/heap_4.c 189 | 1 190 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c 191 | 192 | Middlewares/FreeRTOS/port.c 193 | 1 194 | /opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c 195 | 196 | 197 | -------------------------------------------------------------------------------- /startup/startup_stm32f103xb.s: -------------------------------------------------------------------------------- 1 | /** 2 | *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ 3 | * @file startup_stm32f103xb.s 4 | * @author MCD Application Team 5 | * @version V4.2.0 6 | * @date 31-March-2017 7 | * @brief STM32F103xB Devices vector table for Atollic toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * 19 | *

© COPYRIGHT(c) 2017 STMicroelectronics

20 | * 21 | * Redistribution and use in source and binary forms, with or without modification, 22 | * are permitted provided that the following conditions are met: 23 | * 1. Redistributions of source code must retain the above copyright notice, 24 | * this list of conditions and the following disclaimer. 25 | * 2. Redistributions in binary form must reproduce the above copyright notice, 26 | * this list of conditions and the following disclaimer in the documentation 27 | * and/or other materials provided with the distribution. 28 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 29 | * may be used to endorse or promote products derived from this software 30 | * without specific prior written permission. 31 | * 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 35 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 36 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 38 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 39 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 40 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | * 43 | ****************************************************************************** 44 | */ 45 | 46 | .syntax unified 47 | .cpu cortex-m3 48 | .fpu softvfp 49 | .thumb 50 | 51 | .global g_pfnVectors 52 | .global Default_Handler 53 | 54 | /* start address for the initialization values of the .data section. 55 | defined in linker script */ 56 | .word _sidata 57 | /* start address for the .data section. defined in linker script */ 58 | .word _sdata 59 | /* end address for the .data section. defined in linker script */ 60 | .word _edata 61 | /* start address for the .bss section. defined in linker script */ 62 | .word _sbss 63 | /* end address for the .bss section. defined in linker script */ 64 | .word _ebss 65 | 66 | .equ BootRAM, 0xF108F85F 67 | /** 68 | * @brief This is the code that gets called when the processor first 69 | * starts execution following a reset event. Only the absolutely 70 | * necessary set is performed, after which the application 71 | * supplied main() routine is called. 72 | * @param None 73 | * @retval : None 74 | */ 75 | 76 | .section .text.Reset_Handler 77 | .weak Reset_Handler 78 | .type Reset_Handler, %function 79 | Reset_Handler: 80 | 81 | /* Copy the data segment initializers from flash to SRAM */ 82 | movs r1, #0 83 | b LoopCopyDataInit 84 | 85 | CopyDataInit: 86 | ldr r3, =_sidata 87 | ldr r3, [r3, r1] 88 | str r3, [r0, r1] 89 | adds r1, r1, #4 90 | 91 | LoopCopyDataInit: 92 | ldr r0, =_sdata 93 | ldr r3, =_edata 94 | adds r2, r0, r1 95 | cmp r2, r3 96 | bcc CopyDataInit 97 | ldr r2, =_sbss 98 | b LoopFillZerobss 99 | /* Zero fill the bss segment. */ 100 | FillZerobss: 101 | movs r3, #0 102 | str r3, [r2], #4 103 | 104 | LoopFillZerobss: 105 | ldr r3, = _ebss 106 | cmp r2, r3 107 | bcc FillZerobss 108 | 109 | /* Call the clock system intitialization function.*/ 110 | bl SystemInit 111 | /* Call static constructors */ 112 | bl __libc_init_array 113 | /* Call the application's entry point.*/ 114 | bl main 115 | bx lr 116 | .size Reset_Handler, .-Reset_Handler 117 | 118 | /** 119 | * @brief This is the code that gets called when the processor receives an 120 | * unexpected interrupt. This simply enters an infinite loop, preserving 121 | * the system state for examination by a debugger. 122 | * 123 | * @param None 124 | * @retval : None 125 | */ 126 | .section .text.Default_Handler,"ax",%progbits 127 | Default_Handler: 128 | Infinite_Loop: 129 | b Infinite_Loop 130 | .size Default_Handler, .-Default_Handler 131 | /****************************************************************************** 132 | * 133 | * The minimal vector table for a Cortex M3. Note that the proper constructs 134 | * must be placed on this to ensure that it ends up at physical address 135 | * 0x0000.0000. 136 | * 137 | ******************************************************************************/ 138 | .section .isr_vector,"a",%progbits 139 | .type g_pfnVectors, %object 140 | .size g_pfnVectors, .-g_pfnVectors 141 | 142 | 143 | g_pfnVectors: 144 | 145 | .word _estack 146 | .word Reset_Handler 147 | .word NMI_Handler 148 | .word HardFault_Handler 149 | .word MemManage_Handler 150 | .word BusFault_Handler 151 | .word UsageFault_Handler 152 | .word 0 153 | .word 0 154 | .word 0 155 | .word 0 156 | .word SVC_Handler 157 | .word DebugMon_Handler 158 | .word 0 159 | .word PendSV_Handler 160 | .word SysTick_Handler 161 | .word WWDG_IRQHandler 162 | .word PVD_IRQHandler 163 | .word TAMPER_IRQHandler 164 | .word RTC_IRQHandler 165 | .word FLASH_IRQHandler 166 | .word RCC_IRQHandler 167 | .word EXTI0_IRQHandler 168 | .word EXTI1_IRQHandler 169 | .word EXTI2_IRQHandler 170 | .word EXTI3_IRQHandler 171 | .word EXTI4_IRQHandler 172 | .word DMA1_Channel1_IRQHandler 173 | .word DMA1_Channel2_IRQHandler 174 | .word DMA1_Channel3_IRQHandler 175 | .word DMA1_Channel4_IRQHandler 176 | .word DMA1_Channel5_IRQHandler 177 | .word DMA1_Channel6_IRQHandler 178 | .word DMA1_Channel7_IRQHandler 179 | .word ADC1_2_IRQHandler 180 | .word USB_HP_CAN1_TX_IRQHandler 181 | .word USB_LP_CAN1_RX0_IRQHandler 182 | .word CAN1_RX1_IRQHandler 183 | .word CAN1_SCE_IRQHandler 184 | .word EXTI9_5_IRQHandler 185 | .word TIM1_BRK_IRQHandler 186 | .word TIM1_UP_IRQHandler 187 | .word TIM1_TRG_COM_IRQHandler 188 | .word TIM1_CC_IRQHandler 189 | .word TIM2_IRQHandler 190 | .word TIM3_IRQHandler 191 | .word TIM4_IRQHandler 192 | .word I2C1_EV_IRQHandler 193 | .word I2C1_ER_IRQHandler 194 | .word I2C2_EV_IRQHandler 195 | .word I2C2_ER_IRQHandler 196 | .word SPI1_IRQHandler 197 | .word SPI2_IRQHandler 198 | .word USART1_IRQHandler 199 | .word USART2_IRQHandler 200 | .word USART3_IRQHandler 201 | .word EXTI15_10_IRQHandler 202 | .word RTC_Alarm_IRQHandler 203 | .word USBWakeUp_IRQHandler 204 | .word 0 205 | .word 0 206 | .word 0 207 | .word 0 208 | .word 0 209 | .word 0 210 | .word 0 211 | .word BootRAM /* @0x108. This is for boot in RAM mode for 212 | STM32F10x Medium Density devices. */ 213 | 214 | /******************************************************************************* 215 | * 216 | * Provide weak aliases for each Exception handler to the Default_Handler. 217 | * As they are weak aliases, any function with the same name will override 218 | * this definition. 219 | * 220 | *******************************************************************************/ 221 | 222 | .weak NMI_Handler 223 | .thumb_set NMI_Handler,Default_Handler 224 | 225 | .weak HardFault_Handler 226 | .thumb_set HardFault_Handler,Default_Handler 227 | 228 | .weak MemManage_Handler 229 | .thumb_set MemManage_Handler,Default_Handler 230 | 231 | .weak BusFault_Handler 232 | .thumb_set BusFault_Handler,Default_Handler 233 | 234 | .weak UsageFault_Handler 235 | .thumb_set UsageFault_Handler,Default_Handler 236 | 237 | .weak SVC_Handler 238 | .thumb_set SVC_Handler,Default_Handler 239 | 240 | .weak DebugMon_Handler 241 | .thumb_set DebugMon_Handler,Default_Handler 242 | 243 | .weak PendSV_Handler 244 | .thumb_set PendSV_Handler,Default_Handler 245 | 246 | .weak SysTick_Handler 247 | .thumb_set SysTick_Handler,Default_Handler 248 | 249 | .weak WWDG_IRQHandler 250 | .thumb_set WWDG_IRQHandler,Default_Handler 251 | 252 | .weak PVD_IRQHandler 253 | .thumb_set PVD_IRQHandler,Default_Handler 254 | 255 | .weak TAMPER_IRQHandler 256 | .thumb_set TAMPER_IRQHandler,Default_Handler 257 | 258 | .weak RTC_IRQHandler 259 | .thumb_set RTC_IRQHandler,Default_Handler 260 | 261 | .weak FLASH_IRQHandler 262 | .thumb_set FLASH_IRQHandler,Default_Handler 263 | 264 | .weak RCC_IRQHandler 265 | .thumb_set RCC_IRQHandler,Default_Handler 266 | 267 | .weak EXTI0_IRQHandler 268 | .thumb_set EXTI0_IRQHandler,Default_Handler 269 | 270 | .weak EXTI1_IRQHandler 271 | .thumb_set EXTI1_IRQHandler,Default_Handler 272 | 273 | .weak EXTI2_IRQHandler 274 | .thumb_set EXTI2_IRQHandler,Default_Handler 275 | 276 | .weak EXTI3_IRQHandler 277 | .thumb_set EXTI3_IRQHandler,Default_Handler 278 | 279 | .weak EXTI4_IRQHandler 280 | .thumb_set EXTI4_IRQHandler,Default_Handler 281 | 282 | .weak DMA1_Channel1_IRQHandler 283 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 284 | 285 | .weak DMA1_Channel2_IRQHandler 286 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 287 | 288 | .weak DMA1_Channel3_IRQHandler 289 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 290 | 291 | .weak DMA1_Channel4_IRQHandler 292 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 293 | 294 | .weak DMA1_Channel5_IRQHandler 295 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 296 | 297 | .weak DMA1_Channel6_IRQHandler 298 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 299 | 300 | .weak DMA1_Channel7_IRQHandler 301 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 302 | 303 | .weak ADC1_2_IRQHandler 304 | .thumb_set ADC1_2_IRQHandler,Default_Handler 305 | 306 | .weak USB_HP_CAN1_TX_IRQHandler 307 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 308 | 309 | .weak USB_LP_CAN1_RX0_IRQHandler 310 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 311 | 312 | .weak CAN1_RX1_IRQHandler 313 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 314 | 315 | .weak CAN1_SCE_IRQHandler 316 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 317 | 318 | .weak EXTI9_5_IRQHandler 319 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 320 | 321 | .weak TIM1_BRK_IRQHandler 322 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 323 | 324 | .weak TIM1_UP_IRQHandler 325 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 326 | 327 | .weak TIM1_TRG_COM_IRQHandler 328 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 329 | 330 | .weak TIM1_CC_IRQHandler 331 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 332 | 333 | .weak TIM2_IRQHandler 334 | .thumb_set TIM2_IRQHandler,Default_Handler 335 | 336 | .weak TIM3_IRQHandler 337 | .thumb_set TIM3_IRQHandler,Default_Handler 338 | 339 | .weak TIM4_IRQHandler 340 | .thumb_set TIM4_IRQHandler,Default_Handler 341 | 342 | .weak I2C1_EV_IRQHandler 343 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 344 | 345 | .weak I2C1_ER_IRQHandler 346 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 347 | 348 | .weak I2C2_EV_IRQHandler 349 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 350 | 351 | .weak I2C2_ER_IRQHandler 352 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 353 | 354 | .weak SPI1_IRQHandler 355 | .thumb_set SPI1_IRQHandler,Default_Handler 356 | 357 | .weak SPI2_IRQHandler 358 | .thumb_set SPI2_IRQHandler,Default_Handler 359 | 360 | .weak USART1_IRQHandler 361 | .thumb_set USART1_IRQHandler,Default_Handler 362 | 363 | .weak USART2_IRQHandler 364 | .thumb_set USART2_IRQHandler,Default_Handler 365 | 366 | .weak USART3_IRQHandler 367 | .thumb_set USART3_IRQHandler,Default_Handler 368 | 369 | .weak EXTI15_10_IRQHandler 370 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 371 | 372 | .weak RTC_Alarm_IRQHandler 373 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler 374 | 375 | .weak USBWakeUp_IRQHandler 376 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 377 | 378 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 379 | 380 | -------------------------------------------------------------------------------- /Src/STM32_EEPROM_SPI.c: -------------------------------------------------------------------------------- 1 | /** 2 | * Copyright Nikita Bulaev 2017-2019 3 | * 4 | * Some parts of this lib is taken from STM32 StdPerif libriary 5 | * stm32l152d_eval_spi_ee.c and adopted for the HAL. 6 | * 7 | * THIS SOFTWARE IS PROVIDED "AS IS" 8 | * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 9 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 10 | * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY 11 | * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 12 | * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 13 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 14 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 15 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 16 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 17 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 18 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 19 | */ 20 | 21 | #include "STM32_EEPROM_SPI.h" 22 | 23 | SPI_HandleTypeDef * EEPROM_SPI; 24 | uint8_t EEPROM_StatusByte; 25 | uint8_t RxBuffer[EEPROM_BUFFER_SIZE] = {0x00}; 26 | 27 | /** 28 | * @brief Init EEPROM SPI 29 | * 30 | * @param hspi Pointer to SPI struct handler 31 | */ 32 | void EEPROM_SPI_INIT(SPI_HandleTypeDef * hspi) { 33 | EEPROM_SPI = hspi; 34 | } 35 | 36 | /** 37 | * @brief Writes more than one byte to the EEPROM with a single WRITE cycle 38 | * (Page WRITE sequence). 39 | * 40 | * @note The number of byte can't exceed the EEPROM page size. 41 | * @param pBuffer: pointer to the buffer containing the data to be written 42 | * to the EEPROM. 43 | * @param WriteAddr: EEPROM's internal address to write to. 44 | * @param NumByteToWrite: number of bytes to write to the EEPROM, must be equal 45 | * or less than "EEPROM_PAGESIZE" value. 46 | * @retval EepromOperations value: EEPROM_STATUS_COMPLETE or EEPROM_STATUS_ERROR 47 | */ 48 | EepromOperations EEPROM_SPI_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) { 49 | while (EEPROM_SPI->State != HAL_SPI_STATE_READY) { 50 | osDelay(1); 51 | } 52 | 53 | HAL_StatusTypeDef spiTransmitStatus; 54 | 55 | sEE_WriteEnable(); 56 | 57 | /* 58 | We gonna send commands in one packet of 3 bytes 59 | */ 60 | uint8_t header[3]; 61 | 62 | header[0] = EEPROM_WRITE; // Send "Write to Memory" instruction 63 | header[1] = WriteAddr >> 8; // Send 16-bit address 64 | header[2] = WriteAddr; 65 | 66 | // Select the EEPROM: Chip Select low 67 | EEPROM_CS_LOW(); 68 | 69 | EEPROM_SPI_SendInstruction((uint8_t*)header, 3); 70 | 71 | // Make 5 attemtps to write the data 72 | for (uint8_t i = 0; i < 5; i++) { 73 | spiTransmitStatus = HAL_SPI_Transmit(EEPROM_SPI, pBuffer, NumByteToWrite, 100); 74 | 75 | if (spiTransmitStatus == HAL_BUSY) { 76 | osDelay(5); 77 | } else { 78 | break; 79 | } 80 | } 81 | 82 | // Deselect the EEPROM: Chip Select high 83 | EEPROM_CS_HIGH(); 84 | 85 | // Wait the end of EEPROM writing 86 | EEPROM_SPI_WaitStandbyState(); 87 | 88 | // Disable the write access to the EEPROM 89 | sEE_WriteDisable(); 90 | 91 | if (spiTransmitStatus == HAL_ERROR) { 92 | return EEPROM_STATUS_ERROR; 93 | } else { 94 | return EEPROM_STATUS_COMPLETE; 95 | } 96 | } 97 | 98 | /** 99 | * @brief Writes block of data to the EEPROM. In this function, the number of 100 | * WRITE cycles are reduced, using Page WRITE sequence. 101 | * 102 | * @param pBuffer: pointer to the buffer containing the data to be written 103 | * to the EEPROM. 104 | * @param WriteAddr: EEPROM's internal address to write to. 105 | * @param NumByteToWrite: number of bytes to write to the EEPROM. 106 | * @retval EepromOperations value: EEPROM_STATUS_COMPLETE or EEPROM_STATUS_ERROR 107 | */ 108 | EepromOperations EEPROM_SPI_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) { 109 | uint16_t NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0; 110 | uint16_t sEE_DataNum = 0; 111 | 112 | EepromOperations pageWriteStatus = EEPROM_STATUS_PENDING; 113 | 114 | Addr = WriteAddr % EEPROM_PAGESIZE; 115 | count = EEPROM_PAGESIZE - Addr; 116 | NumOfPage = NumByteToWrite / EEPROM_PAGESIZE; 117 | NumOfSingle = NumByteToWrite % EEPROM_PAGESIZE; 118 | 119 | if (Addr == 0) { /* WriteAddr is EEPROM_PAGESIZE aligned */ 120 | if (NumOfPage == 0) { /* NumByteToWrite < EEPROM_PAGESIZE */ 121 | sEE_DataNum = NumByteToWrite; 122 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 123 | 124 | if (pageWriteStatus != EEPROM_STATUS_COMPLETE) { 125 | return pageWriteStatus; 126 | } 127 | 128 | } else { /* NumByteToWrite > EEPROM_PAGESIZE */ 129 | while (NumOfPage--) { 130 | sEE_DataNum = EEPROM_PAGESIZE; 131 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 132 | 133 | if (pageWriteStatus != EEPROM_STATUS_COMPLETE) { 134 | return pageWriteStatus; 135 | } 136 | 137 | WriteAddr += EEPROM_PAGESIZE; 138 | pBuffer += EEPROM_PAGESIZE; 139 | } 140 | 141 | sEE_DataNum = NumOfSingle; 142 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 143 | 144 | if (pageWriteStatus != EEPROM_STATUS_COMPLETE) { 145 | return pageWriteStatus; 146 | } 147 | } 148 | } else { /* WriteAddr is not EEPROM_PAGESIZE aligned */ 149 | if (NumOfPage == 0) { /* NumByteToWrite < EEPROM_PAGESIZE */ 150 | if (NumOfSingle > count) { /* (NumByteToWrite + WriteAddr) > EEPROM_PAGESIZE */ 151 | temp = NumOfSingle - count; 152 | sEE_DataNum = count; 153 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 154 | 155 | if (pageWriteStatus != EEPROM_STATUS_COMPLETE) { 156 | return pageWriteStatus; 157 | } 158 | 159 | WriteAddr += count; 160 | pBuffer += count; 161 | 162 | sEE_DataNum = temp; 163 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 164 | } else { 165 | sEE_DataNum = NumByteToWrite; 166 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 167 | } 168 | 169 | if (pageWriteStatus != EEPROM_STATUS_COMPLETE) { 170 | return pageWriteStatus; 171 | } 172 | } else { /* NumByteToWrite > EEPROM_PAGESIZE */ 173 | NumByteToWrite -= count; 174 | NumOfPage = NumByteToWrite / EEPROM_PAGESIZE; 175 | NumOfSingle = NumByteToWrite % EEPROM_PAGESIZE; 176 | 177 | sEE_DataNum = count; 178 | 179 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 180 | 181 | if (pageWriteStatus != EEPROM_STATUS_COMPLETE) { 182 | return pageWriteStatus; 183 | } 184 | 185 | WriteAddr += count; 186 | pBuffer += count; 187 | 188 | while (NumOfPage--) { 189 | sEE_DataNum = EEPROM_PAGESIZE; 190 | 191 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 192 | 193 | if (pageWriteStatus != EEPROM_STATUS_COMPLETE) { 194 | return pageWriteStatus; 195 | } 196 | 197 | WriteAddr += EEPROM_PAGESIZE; 198 | pBuffer += EEPROM_PAGESIZE; 199 | } 200 | 201 | if (NumOfSingle != 0) { 202 | sEE_DataNum = NumOfSingle; 203 | 204 | pageWriteStatus = EEPROM_SPI_WritePage(pBuffer, WriteAddr, sEE_DataNum); 205 | 206 | if (pageWriteStatus != EEPROM_STATUS_COMPLETE) { 207 | return pageWriteStatus; 208 | } 209 | } 210 | } 211 | } 212 | 213 | return EEPROM_STATUS_COMPLETE; 214 | } 215 | 216 | /** 217 | * @brief Reads a block of data from the EEPROM. 218 | * 219 | * @param pBuffer: pointer to the buffer that receives the data read from the EEPROM. 220 | * @param ReadAddr: EEPROM's internal address to read from. 221 | * @param NumByteToRead: number of bytes to read from the EEPROM. 222 | * @retval None 223 | */ 224 | EepromOperations EEPROM_SPI_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t NumByteToRead) { 225 | while (EEPROM_SPI->State != HAL_SPI_STATE_READY) { 226 | osDelay(1); 227 | } 228 | 229 | /* 230 | We gonna send all commands in one packet of 3 bytes 231 | */ 232 | 233 | uint8_t header[3]; 234 | 235 | header[0] = EEPROM_READ; // Send "Read from Memory" instruction 236 | header[1] = ReadAddr >> 8; // Send 16-bit address 237 | header[2] = ReadAddr; 238 | 239 | // Select the EEPROM: Chip Select low 240 | EEPROM_CS_LOW(); 241 | 242 | /* Send WriteAddr address byte to read from */ 243 | EEPROM_SPI_SendInstruction(header, 3); 244 | 245 | while (HAL_SPI_Receive(EEPROM_SPI, (uint8_t*)pBuffer, NumByteToRead, 200) == HAL_BUSY) { 246 | osDelay(1); 247 | }; 248 | 249 | // Deselect the EEPROM: Chip Select high 250 | EEPROM_CS_HIGH(); 251 | 252 | return EEPROM_STATUS_COMPLETE; 253 | } 254 | 255 | /** 256 | * @brief Sends a byte through the SPI interface and return the byte received 257 | * from the SPI bus. 258 | * 259 | * @param byte: byte to send. 260 | * @retval The value of the received byte. 261 | */ 262 | uint8_t EEPROM_SendByte(uint8_t byte) { 263 | uint8_t answerByte; 264 | 265 | /* Loop while DR register in not empty */ 266 | while (EEPROM_SPI->State == HAL_SPI_STATE_RESET) { 267 | osDelay(1); 268 | } 269 | 270 | /* Send byte through the SPI peripheral */ 271 | if (HAL_SPI_Transmit(EEPROM_SPI, &byte, 1, 200) != HAL_OK) { 272 | Error_Handler(); 273 | } 274 | 275 | /* Wait to receive a byte */ 276 | while (EEPROM_SPI->State == HAL_SPI_STATE_RESET) { 277 | osDelay(1); 278 | } 279 | 280 | /* Return the byte read from the SPI bus */ 281 | if (HAL_SPI_Receive(EEPROM_SPI, &answerByte, 1, 200) != HAL_OK) { 282 | Error_Handler(); 283 | } 284 | 285 | return (uint8_t)answerByte; 286 | } 287 | /** 288 | * @brief Enables the write access to the EEPROM. 289 | * 290 | * @param None 291 | * @retval None 292 | */ 293 | void sEE_WriteEnable(void) { 294 | // Select the EEPROM: Chip Select low 295 | EEPROM_CS_LOW(); 296 | 297 | uint8_t command[1] = { EEPROM_WREN }; 298 | /* Send "Write Enable" instruction */ 299 | EEPROM_SPI_SendInstruction((uint8_t*)command, 1); 300 | 301 | // Deselect the EEPROM: Chip Select high 302 | EEPROM_CS_HIGH(); 303 | } 304 | 305 | /** 306 | * @brief Disables the write access to the EEPROM. 307 | * 308 | * @param None 309 | * @retval None 310 | */ 311 | void sEE_WriteDisable(void) { 312 | // Select the EEPROM: Chip Select low 313 | EEPROM_CS_LOW(); 314 | 315 | uint8_t command[1] = { EEPROM_WRDI }; 316 | 317 | /* Send "Write Disable" instruction */ 318 | EEPROM_SPI_SendInstruction((uint8_t*)command, 1); 319 | 320 | // Deselect the EEPROM: Chip Select high 321 | EEPROM_CS_HIGH(); 322 | } 323 | 324 | /** 325 | * @brief Write new value in EEPROM Status Register. 326 | * 327 | * @param regval : new value of register 328 | * @retval None 329 | */ 330 | void sEE_WriteStatusRegister(uint8_t regval) { 331 | uint8_t command[2]; 332 | 333 | command[0] = EEPROM_WRSR; 334 | command[1] = regval; 335 | 336 | // Enable the write access to the EEPROM 337 | sEE_WriteEnable(); 338 | 339 | // Select the EEPROM: Chip Select low 340 | EEPROM_CS_LOW(); 341 | 342 | // Send "Write Status Register" instruction 343 | // and Regval in one packet 344 | EEPROM_SPI_SendInstruction((uint8_t*)command, 2); 345 | 346 | // Deselect the EEPROM: Chip Select high 347 | EEPROM_CS_HIGH(); 348 | 349 | sEE_WriteDisable(); 350 | } 351 | 352 | 353 | /** 354 | * @brief Polls the status of the Write In Progress (WIP) flag in the EEPROM's 355 | * status register and loop until write operation has completed. 356 | * 357 | * @param None 358 | * @retval None 359 | */ 360 | uint8_t EEPROM_SPI_WaitStandbyState(void) { 361 | uint8_t sEEstatus[1] = { 0x00 }; 362 | uint8_t command[1] = { EEPROM_RDSR }; 363 | 364 | // Select the EEPROM: Chip Select low 365 | EEPROM_CS_LOW(); 366 | 367 | // Send "Read Status Register" instruction 368 | EEPROM_SPI_SendInstruction((uint8_t*)command, 1); 369 | 370 | // Loop as long as the memory is busy with a write cycle 371 | do { 372 | 373 | while (HAL_SPI_Receive(EEPROM_SPI, (uint8_t*)sEEstatus, 1, 200) == HAL_BUSY) { 374 | osDelay(1); 375 | }; 376 | 377 | osDelay(1); 378 | 379 | } while ((sEEstatus[0] & EEPROM_WIP_FLAG) == SET); // Write in progress 380 | 381 | // Deselect the EEPROM: Chip Select high 382 | EEPROM_CS_HIGH(); 383 | 384 | return 0; 385 | } 386 | 387 | /** 388 | * @brief Low level function to send header data to EEPROM 389 | * 390 | * @param instruction array of bytes to send 391 | * @param size data size in bytes 392 | */ 393 | void EEPROM_SPI_SendInstruction(uint8_t *instruction, uint8_t size) { 394 | while (EEPROM_SPI->State == HAL_SPI_STATE_RESET) { 395 | osDelay(1); 396 | } 397 | 398 | if (HAL_SPI_Transmit(EEPROM_SPI, (uint8_t*)instruction, (uint16_t)size, 200) != HAL_OK) { 399 | Error_Handler(); 400 | } 401 | } 402 | 403 | 404 | 405 | -------------------------------------------------------------------------------- /Inc/stm32f1xx_hal_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_conf.h 4 | * @brief HAL configuration file. 5 | ****************************************************************************** 6 | * @attention 7 | * 8 | *

© COPYRIGHT(c) 2019 STMicroelectronics

9 | * 10 | * Redistribution and use in source and binary forms, with or without modification, 11 | * are permitted provided that the following conditions are met: 12 | * 1. Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 2. Redistributions in binary form must reproduce the above copyright notice, 15 | * this list of conditions and the following disclaimer in the documentation 16 | * and/or other materials provided with the distribution. 17 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 18 | * may be used to endorse or promote products derived from this software 19 | * without specific prior written permission. 20 | * 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 25 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 28 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 | * 32 | ****************************************************************************** 33 | */ 34 | 35 | /* Define to prevent recursive inclusion -------------------------------------*/ 36 | #ifndef __STM32F1xx_HAL_CONF_H 37 | #define __STM32F1xx_HAL_CONF_H 38 | 39 | #ifdef __cplusplus 40 | extern "C" { 41 | #endif 42 | 43 | /* Exported types ------------------------------------------------------------*/ 44 | /* Exported constants --------------------------------------------------------*/ 45 | 46 | /* ########################## Module Selection ############################## */ 47 | /** 48 | * @brief This is the list of modules to be used in the HAL driver 49 | */ 50 | 51 | #define HAL_MODULE_ENABLED 52 | /*#define HAL_ADC_MODULE_ENABLED */ 53 | /*#define HAL_CRYP_MODULE_ENABLED */ 54 | /*#define HAL_CAN_MODULE_ENABLED */ 55 | /*#define HAL_CEC_MODULE_ENABLED */ 56 | /*#define HAL_CORTEX_MODULE_ENABLED */ 57 | /*#define HAL_CRC_MODULE_ENABLED */ 58 | /*#define HAL_DAC_MODULE_ENABLED */ 59 | /*#define HAL_DMA_MODULE_ENABLED */ 60 | /*#define HAL_ETH_MODULE_ENABLED */ 61 | /*#define HAL_FLASH_MODULE_ENABLED */ 62 | #define HAL_GPIO_MODULE_ENABLED 63 | /*#define HAL_I2C_MODULE_ENABLED */ 64 | /*#define HAL_I2S_MODULE_ENABLED */ 65 | /*#define HAL_IRDA_MODULE_ENABLED */ 66 | #define HAL_IWDG_MODULE_ENABLED 67 | /*#define HAL_NOR_MODULE_ENABLED */ 68 | /*#define HAL_NAND_MODULE_ENABLED */ 69 | /*#define HAL_PCCARD_MODULE_ENABLED */ 70 | /*#define HAL_PCD_MODULE_ENABLED */ 71 | /*#define HAL_HCD_MODULE_ENABLED */ 72 | /*#define HAL_PWR_MODULE_ENABLED */ 73 | /*#define HAL_RCC_MODULE_ENABLED */ 74 | #define HAL_RTC_MODULE_ENABLED 75 | /*#define HAL_SD_MODULE_ENABLED */ 76 | /*#define HAL_MMC_MODULE_ENABLED */ 77 | /*#define HAL_SDRAM_MODULE_ENABLED */ 78 | /*#define HAL_SMARTCARD_MODULE_ENABLED */ 79 | #define HAL_SPI_MODULE_ENABLED 80 | /*#define HAL_SRAM_MODULE_ENABLED */ 81 | #define HAL_TIM_MODULE_ENABLED 82 | /*#define HAL_UART_MODULE_ENABLED */ 83 | /*#define HAL_USART_MODULE_ENABLED */ 84 | /*#define HAL_WWDG_MODULE_ENABLED */ 85 | /*#define HAL_EXTI_MODULE_ENABLED */ 86 | 87 | #define HAL_CORTEX_MODULE_ENABLED 88 | #define HAL_DMA_MODULE_ENABLED 89 | #define HAL_FLASH_MODULE_ENABLED 90 | #define HAL_GPIO_MODULE_ENABLED 91 | #define HAL_PWR_MODULE_ENABLED 92 | #define HAL_RCC_MODULE_ENABLED 93 | 94 | /* ########################## Oscillator Values adaptation ####################*/ 95 | /** 96 | * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. 97 | * This value is used by the RCC HAL module to compute the system frequency 98 | * (when HSE is used as system clock source, directly or through the PLL). 99 | */ 100 | #if !defined (HSE_VALUE) 101 | #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ 102 | #endif /* HSE_VALUE */ 103 | 104 | #if !defined (HSE_STARTUP_TIMEOUT) 105 | #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ 106 | #endif /* HSE_STARTUP_TIMEOUT */ 107 | 108 | /** 109 | * @brief Internal High Speed oscillator (HSI) value. 110 | * This value is used by the RCC HAL module to compute the system frequency 111 | * (when HSI is used as system clock source, directly or through the PLL). 112 | */ 113 | #if !defined (HSI_VALUE) 114 | #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ 115 | #endif /* HSI_VALUE */ 116 | 117 | /** 118 | * @brief Internal Low Speed oscillator (LSI) value. 119 | */ 120 | #if !defined (LSI_VALUE) 121 | #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ 122 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 123 | The real value may vary depending on the variations 124 | in voltage and temperature. */ 125 | 126 | /** 127 | * @brief External Low Speed oscillator (LSE) value. 128 | * This value is used by the UART, RTC HAL module to compute the system frequency 129 | */ 130 | #if !defined (LSE_VALUE) 131 | #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ 132 | #endif /* LSE_VALUE */ 133 | 134 | #if !defined (LSE_STARTUP_TIMEOUT) 135 | #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ 136 | #endif /* LSE_STARTUP_TIMEOUT */ 137 | 138 | /* Tip: To avoid modifying this file each time you need to use different HSE, 139 | === you can define the HSE value in your toolchain compiler preprocessor. */ 140 | 141 | /* ########################### System Configuration ######################### */ 142 | /** 143 | * @brief This is the HAL system configuration section 144 | */ 145 | #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ 146 | #define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ 147 | #define USE_RTOS 0 148 | #define PREFETCH_ENABLE 1 149 | 150 | /* ########################## Assert Selection ############################## */ 151 | /** 152 | * @brief Uncomment the line below to expanse the "assert_param" macro in the 153 | * HAL drivers code 154 | */ 155 | /* #define USE_FULL_ASSERT 1U */ 156 | 157 | /* ################## Ethernet peripheral configuration ##################### */ 158 | 159 | /* Section 1 : Ethernet peripheral configuration */ 160 | 161 | /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ 162 | #define MAC_ADDR0 2 163 | #define MAC_ADDR1 0 164 | #define MAC_ADDR2 0 165 | #define MAC_ADDR3 0 166 | #define MAC_ADDR4 0 167 | #define MAC_ADDR5 0 168 | 169 | /* Definition of the Ethernet driver buffers size and count */ 170 | #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ 171 | #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ 172 | #define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ 173 | #define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ 174 | 175 | /* Section 2: PHY configuration section */ 176 | 177 | /* DP83848_PHY_ADDRESS Address*/ 178 | #define DP83848_PHY_ADDRESS 0x01U 179 | /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 180 | #define PHY_RESET_DELAY ((uint32_t)0x000000FF) 181 | /* PHY Configuration delay */ 182 | #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) 183 | 184 | #define PHY_READ_TO ((uint32_t)0x0000FFFF) 185 | #define PHY_WRITE_TO ((uint32_t)0x0000FFFF) 186 | 187 | /* Section 3: Common PHY Registers */ 188 | 189 | #define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ 190 | #define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ 191 | 192 | #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ 193 | #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ 194 | #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ 195 | #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ 196 | #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ 197 | #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ 198 | #define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ 199 | #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ 200 | #define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ 201 | #define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ 202 | 203 | #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ 204 | #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ 205 | #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ 206 | 207 | /* Section 4: Extended PHY Registers */ 208 | #define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ 209 | 210 | #define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ 211 | #define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ 212 | 213 | /* Includes ------------------------------------------------------------------*/ 214 | /** 215 | * @brief Include module's header file 216 | */ 217 | 218 | #ifdef HAL_RCC_MODULE_ENABLED 219 | #include "stm32f1xx_hal_rcc.h" 220 | #endif /* HAL_RCC_MODULE_ENABLED */ 221 | 222 | #ifdef HAL_EXTI_MODULE_ENABLED 223 | #include "stm32f1xx_hal_exti.h" 224 | #endif /* HAL_EXTI_MODULE_ENABLED */ 225 | 226 | #ifdef HAL_GPIO_MODULE_ENABLED 227 | #include "stm32f1xx_hal_gpio.h" 228 | #endif /* HAL_GPIO_MODULE_ENABLED */ 229 | 230 | #ifdef HAL_DMA_MODULE_ENABLED 231 | #include "stm32f1xx_hal_dma.h" 232 | #endif /* HAL_DMA_MODULE_ENABLED */ 233 | 234 | #ifdef HAL_ETH_MODULE_ENABLED 235 | #include "stm32f1xx_hal_eth.h" 236 | #endif /* HAL_ETH_MODULE_ENABLED */ 237 | 238 | #ifdef HAL_CAN_MODULE_ENABLED 239 | #include "stm32f1xx_hal_can.h" 240 | #endif /* HAL_CAN_MODULE_ENABLED */ 241 | 242 | #ifdef HAL_CEC_MODULE_ENABLED 243 | #include "stm32f1xx_hal_cec.h" 244 | #endif /* HAL_CEC_MODULE_ENABLED */ 245 | 246 | #ifdef HAL_CORTEX_MODULE_ENABLED 247 | #include "stm32f1xx_hal_cortex.h" 248 | #endif /* HAL_CORTEX_MODULE_ENABLED */ 249 | 250 | #ifdef HAL_ADC_MODULE_ENABLED 251 | #include "stm32f1xx_hal_adc.h" 252 | #endif /* HAL_ADC_MODULE_ENABLED */ 253 | 254 | #ifdef HAL_CRC_MODULE_ENABLED 255 | #include "stm32f1xx_hal_crc.h" 256 | #endif /* HAL_CRC_MODULE_ENABLED */ 257 | 258 | #ifdef HAL_DAC_MODULE_ENABLED 259 | #include "stm32f1xx_hal_dac.h" 260 | #endif /* HAL_DAC_MODULE_ENABLED */ 261 | 262 | #ifdef HAL_FLASH_MODULE_ENABLED 263 | #include "stm32f1xx_hal_flash.h" 264 | #endif /* HAL_FLASH_MODULE_ENABLED */ 265 | 266 | #ifdef HAL_SRAM_MODULE_ENABLED 267 | #include "stm32f1xx_hal_sram.h" 268 | #endif /* HAL_SRAM_MODULE_ENABLED */ 269 | 270 | #ifdef HAL_NOR_MODULE_ENABLED 271 | #include "stm32f1xx_hal_nor.h" 272 | #endif /* HAL_NOR_MODULE_ENABLED */ 273 | 274 | #ifdef HAL_I2C_MODULE_ENABLED 275 | #include "stm32f1xx_hal_i2c.h" 276 | #endif /* HAL_I2C_MODULE_ENABLED */ 277 | 278 | #ifdef HAL_I2S_MODULE_ENABLED 279 | #include "stm32f1xx_hal_i2s.h" 280 | #endif /* HAL_I2S_MODULE_ENABLED */ 281 | 282 | #ifdef HAL_IWDG_MODULE_ENABLED 283 | #include "stm32f1xx_hal_iwdg.h" 284 | #endif /* HAL_IWDG_MODULE_ENABLED */ 285 | 286 | #ifdef HAL_PWR_MODULE_ENABLED 287 | #include "stm32f1xx_hal_pwr.h" 288 | #endif /* HAL_PWR_MODULE_ENABLED */ 289 | 290 | #ifdef HAL_RTC_MODULE_ENABLED 291 | #include "stm32f1xx_hal_rtc.h" 292 | #endif /* HAL_RTC_MODULE_ENABLED */ 293 | 294 | #ifdef HAL_PCCARD_MODULE_ENABLED 295 | #include "stm32f1xx_hal_pccard.h" 296 | #endif /* HAL_PCCARD_MODULE_ENABLED */ 297 | 298 | #ifdef HAL_SD_MODULE_ENABLED 299 | #include "stm32f1xx_hal_sd.h" 300 | #endif /* HAL_SD_MODULE_ENABLED */ 301 | 302 | #ifdef HAL_MMC_MODULE_ENABLED 303 | #include "stm32f1xx_hal_mmc.h" 304 | #endif /* HAL_MMC_MODULE_ENABLED */ 305 | 306 | #ifdef HAL_NAND_MODULE_ENABLED 307 | #include "stm32f1xx_hal_nand.h" 308 | #endif /* HAL_NAND_MODULE_ENABLED */ 309 | 310 | #ifdef HAL_SPI_MODULE_ENABLED 311 | #include "stm32f1xx_hal_spi.h" 312 | #endif /* HAL_SPI_MODULE_ENABLED */ 313 | 314 | #ifdef HAL_TIM_MODULE_ENABLED 315 | #include "stm32f1xx_hal_tim.h" 316 | #endif /* HAL_TIM_MODULE_ENABLED */ 317 | 318 | #ifdef HAL_UART_MODULE_ENABLED 319 | #include "stm32f1xx_hal_uart.h" 320 | #endif /* HAL_UART_MODULE_ENABLED */ 321 | 322 | #ifdef HAL_USART_MODULE_ENABLED 323 | #include "stm32f1xx_hal_usart.h" 324 | #endif /* HAL_USART_MODULE_ENABLED */ 325 | 326 | #ifdef HAL_IRDA_MODULE_ENABLED 327 | #include "stm32f1xx_hal_irda.h" 328 | #endif /* HAL_IRDA_MODULE_ENABLED */ 329 | 330 | #ifdef HAL_SMARTCARD_MODULE_ENABLED 331 | #include "stm32f1xx_hal_smartcard.h" 332 | #endif /* HAL_SMARTCARD_MODULE_ENABLED */ 333 | 334 | #ifdef HAL_WWDG_MODULE_ENABLED 335 | #include "stm32f1xx_hal_wwdg.h" 336 | #endif /* HAL_WWDG_MODULE_ENABLED */ 337 | 338 | #ifdef HAL_PCD_MODULE_ENABLED 339 | #include "stm32f1xx_hal_pcd.h" 340 | #endif /* HAL_PCD_MODULE_ENABLED */ 341 | 342 | #ifdef HAL_HCD_MODULE_ENABLED 343 | #include "stm32f1xx_hal_hcd.h" 344 | #endif /* HAL_HCD_MODULE_ENABLED */ 345 | 346 | 347 | /* Exported macro ------------------------------------------------------------*/ 348 | #ifdef USE_FULL_ASSERT 349 | /** 350 | * @brief The assert_param macro is used for function's parameters check. 351 | * @param expr: If expr is false, it calls assert_failed function 352 | * which reports the name of the source file and the source 353 | * line number of the call that failed. 354 | * If expr is true, it returns no value. 355 | * @retval None 356 | */ 357 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) 358 | /* Exported functions ------------------------------------------------------- */ 359 | void assert_failed(uint8_t* file, uint32_t line); 360 | #else 361 | #define assert_param(expr) ((void)0U) 362 | #endif /* USE_FULL_ASSERT */ 363 | 364 | #ifdef __cplusplus 365 | } 366 | #endif 367 | 368 | #endif /* __STM32F1xx_HAL_CONF_H */ 369 | 370 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 371 | -------------------------------------------------------------------------------- /Src/main.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.c 5 | * @brief : Main program body 6 | ****************************************************************************** 7 | * This notice applies to any and all portions of this file 8 | * that are not between comment pairs USER CODE BEGIN and 9 | * USER CODE END. Other portions of this file, whether 10 | * inserted by the user or by software development tools 11 | * are owned by their respective copyright owners. 12 | * 13 | * Copyright (c) 2019 STMicroelectronics International N.V. 14 | * All rights reserved. 15 | * 16 | * Redistribution and use in source and binary forms, with or without 17 | * modification, are permitted, provided that the following conditions are met: 18 | * 19 | * 1. Redistribution of source code must retain the above copyright notice, 20 | * this list of conditions and the following disclaimer. 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, 22 | * this list of conditions and the following disclaimer in the documentation 23 | * and/or other materials provided with the distribution. 24 | * 3. Neither the name of STMicroelectronics nor the names of other 25 | * contributors to this software may be used to endorse or promote products 26 | * derived from this software without specific written permission. 27 | * 4. This software, including modifications and/or derivative works of this 28 | * software, must execute solely and exclusively on microcontroller or 29 | * microprocessor devices manufactured by or for STMicroelectronics. 30 | * 5. Redistribution and use of this software other than as permitted under 31 | * this license is void and will automatically terminate your rights under 32 | * this license. 33 | * 34 | * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 35 | * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 36 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 37 | * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY 38 | * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 39 | * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 40 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 42 | * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 43 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 44 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 45 | * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46 | * 47 | ****************************************************************************** 48 | */ 49 | /* USER CODE END Header */ 50 | 51 | /* Includes ------------------------------------------------------------------*/ 52 | #include "main.h" 53 | #include "cmsis_os.h" 54 | 55 | /* Private includes ----------------------------------------------------------*/ 56 | /* USER CODE BEGIN Includes */ 57 | #include "STM32_EEPROM_SPI.h" 58 | /* USER CODE END Includes */ 59 | 60 | /* Private typedef -----------------------------------------------------------*/ 61 | /* USER CODE BEGIN PTD */ 62 | 63 | /* USER CODE END PTD */ 64 | 65 | /* Private define ------------------------------------------------------------*/ 66 | /* USER CODE BEGIN PD */ 67 | 68 | /* USER CODE END PD */ 69 | 70 | /* Private macro -------------------------------------------------------------*/ 71 | /* USER CODE BEGIN PM */ 72 | 73 | /* USER CODE END PM */ 74 | 75 | /* Private variables ---------------------------------------------------------*/ 76 | IWDG_HandleTypeDef hiwdg; 77 | 78 | RTC_HandleTypeDef hrtc; 79 | 80 | SPI_HandleTypeDef hspi1; 81 | 82 | osThreadId defaultTaskHandle; 83 | /* USER CODE BEGIN PV */ 84 | extern uint8_t RxBuffer[32]; 85 | extern uint8_t EEPROM_StatusByte; 86 | 87 | uint8_t TxBuffer[32] = "TEST THIS COOL EEPROM STM SPI ++"; 88 | 89 | /* USER CODE END PV */ 90 | 91 | /* Private function prototypes -----------------------------------------------*/ 92 | void SystemClock_Config(void); 93 | static void MX_GPIO_Init(void); 94 | static void MX_IWDG_Init(void); 95 | static void MX_RTC_Init(void); 96 | static void MX_SPI1_Init(void); 97 | void StartDefaultTask(void const * argument); 98 | 99 | /* USER CODE BEGIN PFP */ 100 | /* Private function prototypes -----------------------------------------------*/ 101 | 102 | /* USER CODE END PFP */ 103 | 104 | /* Private user code ---------------------------------------------------------*/ 105 | /* USER CODE BEGIN 0 */ 106 | 107 | /* USER CODE END 0 */ 108 | 109 | /** 110 | * @brief The application entry point. 111 | * @retval int 112 | */ 113 | int main(void) { 114 | /* USER CODE BEGIN 1 */ 115 | 116 | /* USER CODE END 1 */ 117 | 118 | /* MCU Configuration--------------------------------------------------------*/ 119 | 120 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 121 | HAL_Init(); 122 | 123 | /* USER CODE BEGIN Init */ 124 | 125 | /* USER CODE END Init */ 126 | 127 | /* Configure the system clock */ 128 | SystemClock_Config(); 129 | 130 | /* USER CODE BEGIN SysInit */ 131 | 132 | /* USER CODE END SysInit */ 133 | 134 | /* Initialize all configured peripherals */ 135 | MX_GPIO_Init(); 136 | MX_IWDG_Init(); 137 | MX_RTC_Init(); 138 | MX_SPI1_Init(); 139 | /* USER CODE BEGIN 2 */ 140 | 141 | /* USER CODE END 2 */ 142 | 143 | /* USER CODE BEGIN RTOS_MUTEX */ 144 | /* add mutexes, ... */ 145 | /* USER CODE END RTOS_MUTEX */ 146 | 147 | /* USER CODE BEGIN RTOS_SEMAPHORES */ 148 | /* add semaphores, ... */ 149 | /* USER CODE END RTOS_SEMAPHORES */ 150 | 151 | /* USER CODE BEGIN RTOS_TIMERS */ 152 | /* start timers, add new ones, ... */ 153 | /* USER CODE END RTOS_TIMERS */ 154 | 155 | /* Create the thread(s) */ 156 | /* definition and creation of defaultTask */ 157 | osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128); 158 | defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL); 159 | 160 | /* USER CODE BEGIN RTOS_THREADS */ 161 | /* add threads, ... */ 162 | /* USER CODE END RTOS_THREADS */ 163 | 164 | /* USER CODE BEGIN RTOS_QUEUES */ 165 | /* add queues, ... */ 166 | /* USER CODE END RTOS_QUEUES */ 167 | 168 | 169 | /* Start scheduler */ 170 | osKernelStart(); 171 | 172 | /* We should never get here as control is now taken by the scheduler */ 173 | 174 | /* Infinite loop */ 175 | /* USER CODE BEGIN WHILE */ 176 | while (1) { 177 | /* USER CODE END WHILE */ 178 | 179 | /* USER CODE BEGIN 3 */ 180 | 181 | } 182 | 183 | /* USER CODE END 3 */ 184 | } 185 | 186 | /** 187 | * @brief System Clock Configuration 188 | * @retval None 189 | */ 190 | void SystemClock_Config(void) { 191 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 192 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 193 | RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 194 | 195 | /**Initializes the CPU, AHB and APB busses clocks 196 | */ 197 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSE 198 | | RCC_OSCILLATORTYPE_LSE; 199 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; 200 | RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 201 | RCC_OscInitStruct.LSEState = RCC_LSE_ON; 202 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; 203 | RCC_OscInitStruct.LSIState = RCC_LSI_ON; 204 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 205 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 206 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 207 | 208 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 209 | Error_Handler(); 210 | } 211 | 212 | /**Initializes the CPU, AHB and APB busses clocks 213 | */ 214 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 215 | | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 216 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 217 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 218 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 219 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 220 | 221 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { 222 | Error_Handler(); 223 | } 224 | 225 | PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC; 226 | PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 227 | 228 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { 229 | Error_Handler(); 230 | } 231 | } 232 | 233 | /** 234 | * @brief IWDG Initialization Function 235 | * @param None 236 | * @retval None 237 | */ 238 | static void MX_IWDG_Init(void) { 239 | 240 | /* USER CODE BEGIN IWDG_Init 0 */ 241 | 242 | /* USER CODE END IWDG_Init 0 */ 243 | 244 | /* USER CODE BEGIN IWDG_Init 1 */ 245 | 246 | /* USER CODE END IWDG_Init 1 */ 247 | hiwdg.Instance = IWDG; 248 | hiwdg.Init.Prescaler = IWDG_PRESCALER_4; 249 | hiwdg.Init.Reload = 4095; 250 | 251 | if (HAL_IWDG_Init(&hiwdg) != HAL_OK) { 252 | Error_Handler(); 253 | } 254 | 255 | /* USER CODE BEGIN IWDG_Init 2 */ 256 | 257 | /* USER CODE END IWDG_Init 2 */ 258 | 259 | } 260 | 261 | /** 262 | * @brief RTC Initialization Function 263 | * @param None 264 | * @retval None 265 | */ 266 | static void MX_RTC_Init(void) { 267 | 268 | /* USER CODE BEGIN RTC_Init 0 */ 269 | 270 | /* USER CODE END RTC_Init 0 */ 271 | 272 | RTC_TimeTypeDef sTime = {0}; 273 | RTC_DateTypeDef DateToUpdate = {0}; 274 | 275 | /* USER CODE BEGIN RTC_Init 1 */ 276 | 277 | /* USER CODE END RTC_Init 1 */ 278 | /**Initialize RTC Only 279 | */ 280 | hrtc.Instance = RTC; 281 | hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 282 | hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 283 | 284 | if (HAL_RTC_Init(&hrtc) != HAL_OK) { 285 | Error_Handler(); 286 | } 287 | 288 | /* USER CODE BEGIN Check_RTC_BKUP */ 289 | 290 | /* USER CODE END Check_RTC_BKUP */ 291 | 292 | /**Initialize RTC and set the Time and Date 293 | */ 294 | sTime.Hours = 0x0; 295 | sTime.Minutes = 0x0; 296 | sTime.Seconds = 0x0; 297 | 298 | if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK) { 299 | Error_Handler(); 300 | } 301 | 302 | DateToUpdate.WeekDay = RTC_WEEKDAY_MONDAY; 303 | DateToUpdate.Month = RTC_MONTH_JANUARY; 304 | DateToUpdate.Date = 0x1; 305 | DateToUpdate.Year = 0x0; 306 | 307 | if (HAL_RTC_SetDate(&hrtc, &DateToUpdate, RTC_FORMAT_BCD) != HAL_OK) { 308 | Error_Handler(); 309 | } 310 | 311 | /* USER CODE BEGIN RTC_Init 2 */ 312 | 313 | /* USER CODE END RTC_Init 2 */ 314 | 315 | } 316 | 317 | /** 318 | * @brief SPI1 Initialization Function 319 | * @param None 320 | * @retval None 321 | */ 322 | static void MX_SPI1_Init(void) { 323 | 324 | /* USER CODE BEGIN SPI1_Init 0 */ 325 | 326 | /* USER CODE END SPI1_Init 0 */ 327 | 328 | /* USER CODE BEGIN SPI1_Init 1 */ 329 | 330 | /* USER CODE END SPI1_Init 1 */ 331 | /* SPI1 parameter configuration*/ 332 | hspi1.Instance = SPI1; 333 | hspi1.Init.Mode = SPI_MODE_MASTER; 334 | hspi1.Init.Direction = SPI_DIRECTION_2LINES; 335 | hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 336 | hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 337 | hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 338 | hspi1.Init.NSS = SPI_NSS_SOFT; 339 | hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; 340 | hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 341 | hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 342 | hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 343 | hspi1.Init.CRCPolynomial = 10; 344 | 345 | if (HAL_SPI_Init(&hspi1) != HAL_OK) { 346 | Error_Handler(); 347 | } 348 | 349 | /* USER CODE BEGIN SPI1_Init 2 */ 350 | 351 | /* USER CODE END SPI1_Init 2 */ 352 | 353 | } 354 | 355 | /** 356 | * @brief GPIO Initialization Function 357 | * @param None 358 | * @retval None 359 | */ 360 | static void MX_GPIO_Init(void) { 361 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 362 | 363 | /* GPIO Ports Clock Enable */ 364 | __HAL_RCC_GPIOC_CLK_ENABLE(); 365 | __HAL_RCC_GPIOD_CLK_ENABLE(); 366 | __HAL_RCC_GPIOB_CLK_ENABLE(); 367 | __HAL_RCC_GPIOA_CLK_ENABLE(); 368 | 369 | /*Configure GPIO pin Output Level */ 370 | HAL_GPIO_WritePin(GPIOB, EEPROM_CS_Pin | EEPROM_WP_Pin | EEPROM_HOLD_Pin, GPIO_PIN_SET); 371 | 372 | /*Configure GPIO pin : EEPROM_CS_Pin */ 373 | GPIO_InitStruct.Pin = EEPROM_CS_Pin; 374 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 375 | GPIO_InitStruct.Pull = GPIO_NOPULL; 376 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 377 | HAL_GPIO_Init(EEPROM_CS_GPIO_Port, &GPIO_InitStruct); 378 | 379 | /*Configure GPIO pins : EEPROM_WP_Pin EEPROM_HOLD_Pin */ 380 | GPIO_InitStruct.Pin = EEPROM_WP_Pin | EEPROM_HOLD_Pin; 381 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 382 | GPIO_InitStruct.Pull = GPIO_NOPULL; 383 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 384 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 385 | 386 | } 387 | 388 | /* USER CODE BEGIN 4 */ 389 | 390 | /* USER CODE END 4 */ 391 | 392 | /* USER CODE BEGIN Header_StartDefaultTask */ 393 | /** 394 | * @brief Function implementing the defaultTask thread. 395 | * @param argument: Not used 396 | * @retval None 397 | */ 398 | /* USER CODE END Header_StartDefaultTask */ 399 | void StartDefaultTask(void const * argument) { 400 | 401 | /* USER CODE BEGIN 5 */ 402 | /* Infinite loop */ 403 | EEPROM_SPI_INIT(&hspi1); 404 | 405 | EEPROM_SPI_WriteBuffer(TxBuffer, (uint16_t)0x01, (uint16_t)32); 406 | 407 | for (;;) { 408 | EEPROM_SPI_ReadBuffer(RxBuffer, (uint16_t)0x01, (uint16_t)32); 409 | 410 | osDelay(5000); 411 | } 412 | 413 | /* USER CODE END 5 */ 414 | } 415 | 416 | /** 417 | * @brief Period elapsed callback in non blocking mode 418 | * @note This function is called when TIM2 interrupt took place, inside 419 | * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment 420 | * a global variable "uwTick" used as application time base. 421 | * @param htim : TIM handle 422 | * @retval None 423 | */ 424 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 425 | /* USER CODE BEGIN Callback 0 */ 426 | 427 | /* USER CODE END Callback 0 */ 428 | if (htim->Instance == TIM2) { 429 | HAL_IncTick(); 430 | } 431 | 432 | /* USER CODE BEGIN Callback 1 */ 433 | 434 | /* USER CODE END Callback 1 */ 435 | } 436 | 437 | /** 438 | * @brief This function is executed in case of error occurrence. 439 | * @retval None 440 | */ 441 | void Error_Handler(void) { 442 | /* USER CODE BEGIN Error_Handler_Debug */ 443 | /* User can add his own implementation to report the HAL error return state */ 444 | 445 | /* USER CODE END Error_Handler_Debug */ 446 | } 447 | 448 | #ifdef USE_FULL_ASSERT 449 | /** 450 | * @brief Reports the name of the source file and the source line number 451 | * where the assert_param error has occurred. 452 | * @param file: pointer to the source file name 453 | * @param line: assert_param error line source number 454 | * @retval None 455 | */ 456 | void assert_failed(uint8_t *file, uint32_t line) { 457 | /* USER CODE BEGIN 6 */ 458 | /* User can add his own implementation to report the file name and line number, 459 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 460 | /* USER CODE END 6 */ 461 | } 462 | #endif /* USE_FULL_ASSERT */ 463 | 464 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 465 | -------------------------------------------------------------------------------- /Src/system_stm32f1xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f1xx.c 4 | * @author MCD Application Team 5 | * @version V4.1.0 6 | * @date 29-April-2016 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. 8 | * 9 | * 1. This file provides two functions and one global variable to be called from 10 | * user application: 11 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 12 | * factors, AHB/APBx prescalers and Flash settings). 13 | * This function is called at startup just after reset and 14 | * before branch to main program. This call is made inside 15 | * the "startup_stm32f1xx_xx.s" file. 16 | * 17 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 18 | * by the user application to setup the SysTick 19 | * timer or configure other parameters. 20 | * 21 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 22 | * be called whenever the core clock is changed 23 | * during program execution. 24 | * 25 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. 26 | * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to 27 | * configure the system clock before to branch to main program. 28 | * 29 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on 30 | * the product used), refer to "HSE_VALUE". 31 | * When HSE is used as system clock source, directly or through PLL, and you 32 | * are using different crystal you have to adapt the HSE value to your own 33 | * configuration. 34 | * 35 | ****************************************************************************** 36 | * @attention 37 | * 38 | *

© COPYRIGHT(c) 2016 STMicroelectronics

39 | * 40 | * Redistribution and use in source and binary forms, with or without modification, 41 | * are permitted provided that the following conditions are met: 42 | * 1. Redistributions of source code must retain the above copyright notice, 43 | * this list of conditions and the following disclaimer. 44 | * 2. Redistributions in binary form must reproduce the above copyright notice, 45 | * this list of conditions and the following disclaimer in the documentation 46 | * and/or other materials provided with the distribution. 47 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 48 | * may be used to endorse or promote products derived from this software 49 | * without specific prior written permission. 50 | * 51 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 52 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 55 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 58 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 59 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 | * 62 | ****************************************************************************** 63 | */ 64 | 65 | /** @addtogroup CMSIS 66 | * @{ 67 | */ 68 | 69 | /** @addtogroup stm32f1xx_system 70 | * @{ 71 | */ 72 | 73 | /** @addtogroup STM32F1xx_System_Private_Includes 74 | * @{ 75 | */ 76 | 77 | #include "stm32f1xx.h" 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @addtogroup STM32F1xx_System_Private_TypesDefinitions 84 | * @{ 85 | */ 86 | 87 | /** 88 | * @} 89 | */ 90 | 91 | /** @addtogroup STM32F1xx_System_Private_Defines 92 | * @{ 93 | */ 94 | 95 | #if !defined (HSE_VALUE) 96 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. 97 | This value can be provided and adapted by the user application. */ 98 | #endif /* HSE_VALUE */ 99 | 100 | #if !defined (HSI_VALUE) 101 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. 102 | This value can be provided and adapted by the user application. */ 103 | #endif /* HSI_VALUE */ 104 | 105 | /*!< Uncomment the following line if you need to use external SRAM */ 106 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) 107 | /* #define DATA_IN_ExtSRAM */ 108 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ 109 | 110 | /*!< Uncomment the following line if you need to relocate your vector Table in 111 | Internal SRAM. */ 112 | /* #define VECT_TAB_SRAM */ 113 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. 114 | This value must be a multiple of 0x200. */ 115 | 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** @addtogroup STM32F1xx_System_Private_Macros 122 | * @{ 123 | */ 124 | 125 | /** 126 | * @} 127 | */ 128 | 129 | /** @addtogroup STM32F1xx_System_Private_Variables 130 | * @{ 131 | */ 132 | 133 | /******************************************************************************* 134 | * Clock Definitions 135 | *******************************************************************************/ 136 | #if defined(STM32F100xB) ||defined(STM32F100xE) 137 | uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */ 138 | #else /*!< HSI Selected as System Clock source */ 139 | uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ 140 | #endif 141 | 142 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 143 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 144 | 145 | /** 146 | * @} 147 | */ 148 | 149 | /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes 150 | * @{ 151 | */ 152 | 153 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) 154 | #ifdef DATA_IN_ExtSRAM 155 | static void SystemInit_ExtMemCtl(void); 156 | #endif /* DATA_IN_ExtSRAM */ 157 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ 158 | 159 | /** 160 | * @} 161 | */ 162 | 163 | /** @addtogroup STM32F1xx_System_Private_Functions 164 | * @{ 165 | */ 166 | 167 | /** 168 | * @brief Setup the microcontroller system 169 | * Initialize the Embedded Flash Interface, the PLL and update the 170 | * SystemCoreClock variable. 171 | * @note This function should be used only after reset. 172 | * @param None 173 | * @retval None 174 | */ 175 | void SystemInit (void) 176 | { 177 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ 178 | /* Set HSION bit */ 179 | RCC->CR |= (uint32_t)0x00000001; 180 | 181 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ 182 | #if !defined(STM32F105xC) && !defined(STM32F107xC) 183 | RCC->CFGR &= (uint32_t)0xF8FF0000; 184 | #else 185 | RCC->CFGR &= (uint32_t)0xF0FF0000; 186 | #endif /* STM32F105xC */ 187 | 188 | /* Reset HSEON, CSSON and PLLON bits */ 189 | RCC->CR &= (uint32_t)0xFEF6FFFF; 190 | 191 | /* Reset HSEBYP bit */ 192 | RCC->CR &= (uint32_t)0xFFFBFFFF; 193 | 194 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ 195 | RCC->CFGR &= (uint32_t)0xFF80FFFF; 196 | 197 | #if defined(STM32F105xC) || defined(STM32F107xC) 198 | /* Reset PLL2ON and PLL3ON bits */ 199 | RCC->CR &= (uint32_t)0xEBFFFFFF; 200 | 201 | /* Disable all interrupts and clear pending bits */ 202 | RCC->CIR = 0x00FF0000; 203 | 204 | /* Reset CFGR2 register */ 205 | RCC->CFGR2 = 0x00000000; 206 | #elif defined(STM32F100xB) || defined(STM32F100xE) 207 | /* Disable all interrupts and clear pending bits */ 208 | RCC->CIR = 0x009F0000; 209 | 210 | /* Reset CFGR2 register */ 211 | RCC->CFGR2 = 0x00000000; 212 | #else 213 | /* Disable all interrupts and clear pending bits */ 214 | RCC->CIR = 0x009F0000; 215 | #endif /* STM32F105xC */ 216 | 217 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) 218 | #ifdef DATA_IN_ExtSRAM 219 | SystemInit_ExtMemCtl(); 220 | #endif /* DATA_IN_ExtSRAM */ 221 | #endif 222 | 223 | #ifdef VECT_TAB_SRAM 224 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ 225 | #else 226 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 227 | #endif 228 | } 229 | 230 | /** 231 | * @brief Update SystemCoreClock variable according to Clock Register Values. 232 | * The SystemCoreClock variable contains the core clock (HCLK), it can 233 | * be used by the user application to setup the SysTick timer or configure 234 | * other parameters. 235 | * 236 | * @note Each time the core clock (HCLK) changes, this function must be called 237 | * to update SystemCoreClock variable value. Otherwise, any configuration 238 | * based on this variable will be incorrect. 239 | * 240 | * @note - The system frequency computed by this function is not the real 241 | * frequency in the chip. It is calculated based on the predefined 242 | * constant and the selected clock source: 243 | * 244 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 245 | * 246 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 247 | * 248 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 249 | * or HSI_VALUE(*) multiplied by the PLL factors. 250 | * 251 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value 252 | * 8 MHz) but the real value may vary depending on the variations 253 | * in voltage and temperature. 254 | * 255 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value 256 | * 8 MHz or 25 MHz, depending on the product used), user has to ensure 257 | * that HSE_VALUE is same as the real frequency of the crystal used. 258 | * Otherwise, this function may have wrong result. 259 | * 260 | * - The result of this function could be not correct when using fractional 261 | * value for HSE crystal. 262 | * @param None 263 | * @retval None 264 | */ 265 | void SystemCoreClockUpdate (void) 266 | { 267 | uint32_t tmp = 0, pllmull = 0, pllsource = 0; 268 | 269 | #if defined(STM32F105xC) || defined(STM32F107xC) 270 | uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; 271 | #endif /* STM32F105xC */ 272 | 273 | #if defined(STM32F100xB) || defined(STM32F100xE) 274 | uint32_t prediv1factor = 0; 275 | #endif /* STM32F100xB or STM32F100xE */ 276 | 277 | /* Get SYSCLK source -------------------------------------------------------*/ 278 | tmp = RCC->CFGR & RCC_CFGR_SWS; 279 | 280 | switch (tmp) 281 | { 282 | case 0x00: /* HSI used as system clock */ 283 | SystemCoreClock = HSI_VALUE; 284 | break; 285 | case 0x04: /* HSE used as system clock */ 286 | SystemCoreClock = HSE_VALUE; 287 | break; 288 | case 0x08: /* PLL used as system clock */ 289 | 290 | /* Get PLL clock source and multiplication factor ----------------------*/ 291 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 292 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 293 | 294 | #if !defined(STM32F105xC) && !defined(STM32F107xC) 295 | pllmull = ( pllmull >> 18) + 2; 296 | 297 | if (pllsource == 0x00) 298 | { 299 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 300 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 301 | } 302 | else 303 | { 304 | #if defined(STM32F100xB) || defined(STM32F100xE) 305 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 306 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 307 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 308 | #else 309 | /* HSE selected as PLL clock entry */ 310 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) 311 | {/* HSE oscillator clock divided by 2 */ 312 | SystemCoreClock = (HSE_VALUE >> 1) * pllmull; 313 | } 314 | else 315 | { 316 | SystemCoreClock = HSE_VALUE * pllmull; 317 | } 318 | #endif 319 | } 320 | #else 321 | pllmull = pllmull >> 18; 322 | 323 | if (pllmull != 0x0D) 324 | { 325 | pllmull += 2; 326 | } 327 | else 328 | { /* PLL multiplication factor = PLL input clock * 6.5 */ 329 | pllmull = 13 / 2; 330 | } 331 | 332 | if (pllsource == 0x00) 333 | { 334 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 335 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 336 | } 337 | else 338 | {/* PREDIV1 selected as PLL clock entry */ 339 | 340 | /* Get PREDIV1 clock source and division factor */ 341 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; 342 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 343 | 344 | if (prediv1source == 0) 345 | { 346 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 347 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 348 | } 349 | else 350 | {/* PLL2 clock selected as PREDIV1 clock entry */ 351 | 352 | /* Get PREDIV2 division factor and PLL2 multiplication factor */ 353 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; 354 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 355 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; 356 | } 357 | } 358 | #endif /* STM32F105xC */ 359 | break; 360 | 361 | default: 362 | SystemCoreClock = HSI_VALUE; 363 | break; 364 | } 365 | 366 | /* Compute HCLK clock frequency ----------------*/ 367 | /* Get HCLK prescaler */ 368 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 369 | /* HCLK clock frequency */ 370 | SystemCoreClock >>= tmp; 371 | } 372 | 373 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) 374 | /** 375 | * @brief Setup the external memory controller. Called in startup_stm32f1xx.s 376 | * before jump to __main 377 | * @param None 378 | * @retval None 379 | */ 380 | #ifdef DATA_IN_ExtSRAM 381 | /** 382 | * @brief Setup the external memory controller. 383 | * Called in startup_stm32f1xx_xx.s/.c before jump to main. 384 | * This function configures the external SRAM mounted on STM3210E-EVAL 385 | * board (STM32 High density devices). This SRAM will be used as program 386 | * data memory (including heap and stack). 387 | * @param None 388 | * @retval None 389 | */ 390 | void SystemInit_ExtMemCtl(void) 391 | { 392 | __IO uint32_t tmpreg; 393 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 394 | required, then adjust the Register Addresses */ 395 | 396 | /* Enable FSMC clock */ 397 | RCC->AHBENR = 0x00000114; 398 | 399 | /* Delay after an RCC peripheral clock enabling */ 400 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); 401 | 402 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ 403 | RCC->APB2ENR = 0x000001E0; 404 | 405 | /* Delay after an RCC peripheral clock enabling */ 406 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); 407 | 408 | (void)(tmpreg); 409 | 410 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ 411 | /*---------------- SRAM Address lines configuration -------------------------*/ 412 | /*---------------- NOE and NWE configuration --------------------------------*/ 413 | /*---------------- NE3 configuration ----------------------------------------*/ 414 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/ 415 | 416 | GPIOD->CRL = 0x44BB44BB; 417 | GPIOD->CRH = 0xBBBBBBBB; 418 | 419 | GPIOE->CRL = 0xB44444BB; 420 | GPIOE->CRH = 0xBBBBBBBB; 421 | 422 | GPIOF->CRL = 0x44BBBBBB; 423 | GPIOF->CRH = 0xBBBB4444; 424 | 425 | GPIOG->CRL = 0x44BBBBBB; 426 | GPIOG->CRH = 0x444B4B44; 427 | 428 | /*---------------- FSMC Configuration ---------------------------------------*/ 429 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ 430 | 431 | FSMC_Bank1->BTCR[4] = 0x00001091; 432 | FSMC_Bank1->BTCR[5] = 0x00110212; 433 | } 434 | #endif /* DATA_IN_ExtSRAM */ 435 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ 436 | 437 | /** 438 | * @} 439 | */ 440 | 441 | /** 442 | * @} 443 | */ 444 | 445 | /** 446 | * @} 447 | */ 448 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 449 | -------------------------------------------------------------------------------- /.mxproject: -------------------------------------------------------------------------------- 1 | [PreviousGenFiles] 2 | HeaderPath=/home/bulaev/workspace/STM32-EEPROM-SPI/Inc 3 | HeaderFiles=FreeRTOSConfig.h;stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h; 4 | SourcePath=/home/bulaev/workspace/STM32-EEPROM-SPI/Src 5 | SourceFiles=FreeRTOSConfig.h;stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h;freertos.c;stm32f1xx_it.c;stm32f1xx_hal_msp.c;stm32f1xx_hal_timebase_TIM.c;main.c;stm32f1xx_hal_timebase_tim.c; 6 | 7 | [PreviousLibFiles] 8 | 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9 | 10 | [PreviousUsedKeilFiles] 11 | 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12 | HeaderPath=C:\Users\bulaev\STM32Cube\Repository\STM32Cube_FW_F1_V1.4.0\Drivers\STM32F1xx_HAL_Driver\Inc;C:\Users\bulaev\STM32Cube\Repository\STM32Cube_FW_F1_V1.4.0\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;C:\Users\bulaev\STM32Cube\Repository\STM32Cube_FW_F1_V1.4.0\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM3;C:\Users\bulaev\STM32Cube\Repository\STM32Cube_FW_F1_V1.4.0\Drivers\CMSIS\Device\ST\STM32F1xx\Include;C:\Users\bulaev\STM32Cube\Repository\STM32Cube_FW_F1_V1.4.0\Middlewares\Third_Party\FreeRTOS\Source\include;C:\Users\bulaev\STM32Cube\Repository\STM32Cube_FW_F1_V1.4.0\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;C:\Users\bulaev\STM32Cube\Repository\STM32Cube_FW_F1_V1.4.0\Drivers\CMSIS\Include; 13 | 14 | [PreviousUsedTStudioFiles] 15 | SourceFiles=../Src/main.c;../Src/freertos.c;../Src/stm32f1xx_it.c;../Src/stm32f1xx_hal_msp.c;../Src/stm32f1xx_hal_timebase_tim.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/croutine.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/list.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/queue.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/tasks.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/timers.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;..//Src/system_stm32f1xx.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/T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16 | HeaderPath=/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Inc;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/include;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/CMSIS/Device/ST/STM32F1xx/Include;/opt/libs/STM32Cube/Repository/STM32Cube_FW_F1_V1.7.0/Drivers/CMSIS/Include;../Inc; 17 | CDefines=__weak:"__attribute__((weak))";__packed:"__attribute__((__packed__))"; 18 | 19 | -------------------------------------------------------------------------------- /.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 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