├── .github ├── FUNDING.yml └── workflows │ ├── build_docs.yml │ └── run_tests.yml ├── .gitignore ├── .pre-commit-config.yaml ├── LICENSE.txt ├── Makefile ├── README.md ├── doc ├── architecture.md ├── assets │ ├── bus_architecture.drawio.svg │ ├── io_core_architecture.drawio.svg │ ├── logic_analyzer_architecture.drawio.svg │ ├── logo.png │ ├── logo_minimal_border.png │ ├── logo_ray_only.png │ ├── logo_ray_only_transparent.png │ ├── logo_ray_only_with_shadow.png │ ├── memory_architecture.drawio.svg │ ├── read_transaction.json5 │ ├── system_architecture.drawio.svg │ ├── trigger_positions.png │ ├── uart_packets.drawio.svg │ └── write_transaction.json5 ├── ethernet_interface.md ├── getting_started.md ├── index.md ├── installation.md ├── io_core.md ├── javascripts │ └── mathjax.js ├── logic_analyzer_core.md ├── memory_core.md ├── overrides │ ├── main.html │ └── outdated.html ├── similar_tools.md ├── stylesheets │ └── extra.css ├── thesis.pdf ├── uart_interface.md └── use_cases.md ├── environment.sh ├── examples ├── amaranth │ ├── ethernet_io_core.py │ ├── uart_io_core.py │ ├── uart_logic_analyzer.py │ └── uart_memory_core.py ├── common │ ├── .gitignore │ └── divider.sv └── verilog │ ├── icestick │ ├── uart_io_core │ │ ├── .gitignore │ │ ├── blinky.py │ │ ├── build.sh │ │ ├── manta.yaml │ │ ├── top_level.pcf │ │ └── top_level.sv │ └── uart_logic_analyzer │ │ ├── .gitignore │ │ ├── build.sh │ │ ├── manta.yaml │ │ ├── top_level.pcf │ │ └── top_level.sv │ └── nexys4_ddr │ ├── ether_logic_analyzer_io_core │ ├── .gitignore │ ├── build.sh │ ├── build.tcl │ ├── divider.sv │ ├── manta.yaml │ ├── test.py │ ├── top_level.sv │ └── top_level.xdc │ ├── uart_host_to_fpga_mem │ ├── .gitignore │ ├── build.sh │ ├── build.tcl │ ├── manta.yaml │ ├── top_level.sv │ ├── top_level.xdc │ └── write.py │ ├── uart_io_core │ ├── .gitignore │ ├── blinky.py │ ├── build.sh │ ├── build.tcl │ ├── manta.yaml │ ├── top_level.sv │ └── top_level.xdc │ └── uart_logic_analyzer │ ├── .gitignore │ ├── build.sh │ ├── build.tcl │ ├── manta.yaml │ ├── top_level.sv │ └── top_level.xdc ├── mkdocs.yml ├── pyproject.toml ├── src └── manta │ ├── __init__.py │ ├── __main__.py │ ├── cli.py │ ├── ethernet │ ├── __init__.py │ ├── liteeth_gen.py │ ├── sink_bridge.py │ └── source_bridge.py │ ├── io_core.py │ ├── logic_analyzer │ ├── __init__.py │ ├── capture.py │ ├── fsm.py │ ├── playback.py │ └── trigger_block.py │ ├── manta.py │ ├── memory_core.py │ ├── uart │ ├── __init__.py │ ├── receive_bridge.py │ ├── receiver.py │ ├── transmit_bridge.py │ └── transmitter.py │ └── utils.py └── test ├── test_bridge_rx_sim.py ├── test_bridge_tx_sim.py ├── test_config_export.py ├── test_ethernet_interface.py ├── test_examples_build.py ├── test_io_core_hw.py ├── test_io_core_sim.py ├── test_logic_analyzer_fsm_sim.py ├── test_logic_analyzer_hw.py ├── test_logic_analyzer_sim.py ├── test_mem_core_hw.py ├── test_mem_core_sim.py ├── test_source_bridge_sim.py ├── test_uart_baud_mismatch.py ├── test_uart_rx_sim.py ├── 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