├── .gitattributes ├── .gitignore ├── ip └── demosaic │ ├── misc │ └── logo.png │ ├── xilinx_com_hls_demosaic_root_1_0_rgb1280x720.zip │ ├── xilinx_com_hls_demosaic_root_1_0_rgb640x480.zip │ ├── xilinx_com_hls_demosaic_root_1_0_yuyv640x480.zip │ ├── xilinx_com_hls_demosaic_root_1_0_rgb1920x1080.zip │ ├── xilinx_com_hls_demosaic_root_1_0_yuyv1280x720.zip │ ├── xilinx_com_hls_demosaic_root_1_0_yuyv1920x1080.zip │ ├── constraints │ └── demosaic_root_ooc.xdc │ ├── doc │ └── ReleaseNotes.txt │ ├── drivers │ └── demosaic_root_v1_0 │ │ ├── data │ │ ├── demosaic_root.mdd │ │ └── demosaic_root.tcl │ │ └── src │ │ ├── Makefile │ │ ├── xdemosaic_root_sinit.c │ │ ├── xdemosaic_root_hw.h │ │ ├── xdemosaic_root.h │ │ ├── xdemosaic_root_linux.c │ │ └── xdemosaic_root.c │ ├── hdl │ ├── verilog │ │ ├── demosaic_root_muldEe.v │ │ ├── demosaic_root_muleOg.v │ │ ├── demosaic_root_mulocq.v │ │ ├── demosaic_root_mulhbi.v │ │ ├── demosaic_root_macfYi.v │ │ ├── odata_p_idata_bufbkb.v │ │ ├── fifo_w1_d16_A.v │ │ ├── fifo_w24_d16_A.v │ │ ├── fifo_w40_d16_A.v │ │ ├── fifo_w1_d320_A.v │ │ ├── fifo_w1_d640_A.v │ │ ├── fifo_w1_d960_A.v │ │ ├── start_for_odata_U0.v │ │ ├── start_for_olast_U0.v │ │ ├── start_for_ouser_U0.v │ │ ├── start_for_Loop_2_dEe.v │ │ ├── start_for_Loop_2_kbM.v │ │ ├── start_for_Loop_2_qcK.v │ │ ├── start_for_demosaijbC.v │ │ ├── start_for_demosaipcA.v │ │ └── demosaic_root_ureibs.v │ └── vhdl │ │ ├── demosaic_root_muldEe.vhd │ │ ├── demosaic_root_muleOg.vhd │ │ ├── demosaic_root_mulhbi.vhd │ │ ├── demosaic_root_mulocq.vhd │ │ ├── demosaic_root_macfYi.vhd │ │ ├── odata_p_idata_bufbkb.vhd │ │ ├── fifo_w1_d16_A.vhd │ │ ├── fifo_w24_d16_A.vhd │ │ ├── fifo_w40_d16_A.vhd │ │ ├── fifo_w1_d320_A.vhd │ │ ├── fifo_w1_d640_A.vhd │ │ ├── fifo_w1_d960_A.vhd │ │ ├── start_for_odata_U0.vhd │ │ ├── start_for_olast_U0.vhd │ │ ├── start_for_ouser_U0.vhd │ │ ├── start_for_Loop_2_dEe.vhd │ │ ├── start_for_Loop_2_kbM.vhd │ │ ├── start_for_Loop_2_qcK.vhd │ │ ├── start_for_demosaijbC.vhd │ │ └── start_for_demosaipcA.vhd │ ├── xgui │ └── demosaic_root_v1_0.tcl │ └── bd │ └── bd.tcl ├── overlay ├── rm_camera.sh ├── fpga-load.dts ├── udmabuf0.dts ├── fclk0-zynqmp.dts ├── v4l2.dts └── init_camera.sh ├── src ├── linux │ └── caminit │ │ ├── src │ │ ├── main.cc │ │ ├── camcfg.cc │ │ ├── camcfg.h │ │ ├── caminit.h │ │ ├── caminit.cc │ │ └── imx219.cc │ │ └── build │ │ ├── objects.mk │ │ ├── sources.mk │ │ ├── src │ │ └── subdir.mk │ │ └── makefile └── verilog │ └── design_1_wrapper.v ├── .gitmodules ├── script ├── bit2bin.sh └── create_project.tcl ├── test ├── cam.h ├── makefile ├── uvc_camera_test.cc ├── rgbtest.cc ├── rgbvideo.cc ├── yuvtest.cc ├── cam.cc └── camera_umd │ └── uvc_camera │ └── include │ └── uvc_cam │ └── uvc_cam.h ├── etc └── xorg.conf ├── README.md └── LICENSE /.gitattributes: -------------------------------------------------------------------------------- 1 | *.zip filter=lfs diff=lfs merge=lfs -text 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ultra96_design 2 | *.jou 3 | *.log 4 | *.str 5 | *.bin 6 | .cproject 7 | .project 8 | -------------------------------------------------------------------------------- /ip/demosaic/misc/logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fixstars/ultra96_design/HEAD/ip/demosaic/misc/logo.png -------------------------------------------------------------------------------- /overlay/rm_camera.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | rmdir /config/device-tree/overlays/fpga 4 | rmdir /config/device-tree/overlays/fclk0 5 | rmdir /config/device-tree/overlays/v4l2 6 | -------------------------------------------------------------------------------- /ip/demosaic/xilinx_com_hls_demosaic_root_1_0_rgb1280x720.zip: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:28041b1bf7cbbb1334c91963e5b099ae51b6c7988c04186a428c151e07ebe46a 3 | size 104453 4 | -------------------------------------------------------------------------------- /ip/demosaic/xilinx_com_hls_demosaic_root_1_0_rgb640x480.zip: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:7bed1197a4045d86f6e59b0b0cc8c11245b71d98c135f448285d74db8b9f3962 3 | size 104658 4 | -------------------------------------------------------------------------------- /ip/demosaic/xilinx_com_hls_demosaic_root_1_0_yuyv640x480.zip: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:98e11021f34717b63750af04beada08123e3b87ea2c715b2dc60184665a7d89f 3 | size 127652 4 | -------------------------------------------------------------------------------- /overlay/fpga-load.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | / { 3 | fragment@0 { 4 | target-path = "/fpga-full"; 5 | __overlay__ { 6 | firmware-name = "fpga.bin"; 7 | }; 8 | }; 9 | }; -------------------------------------------------------------------------------- /ip/demosaic/xilinx_com_hls_demosaic_root_1_0_rgb1920x1080.zip: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:0a421d953d3bcc558561835634ff31533d24d2a42724e14c8bce2ea151f739b5 3 | size 104224 4 | -------------------------------------------------------------------------------- /ip/demosaic/xilinx_com_hls_demosaic_root_1_0_yuyv1280x720.zip: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:651efdde22a24b4c155b3fa71ccdd667f784bb0f61a051f54043729417307f1c 3 | size 127402 4 | -------------------------------------------------------------------------------- /ip/demosaic/xilinx_com_hls_demosaic_root_1_0_yuyv1920x1080.zip: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:4de7cb8ef18a8e468af45604e52a6c1013c622f289ec9aaa0a853190b0b730df 3 | size 127184 4 | -------------------------------------------------------------------------------- /src/linux/caminit/src/main.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include "caminit.h" 3 | 4 | int main(int argc, char *argv[]) 5 | { 6 | int ret; 7 | 8 | ret = caminit(SENSOR_OV5640, RESOLUTION_640_480); 9 | 10 | return ret; 11 | } 12 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "src/linux/driver"] 2 | path = src/linux/driver 3 | url = https://github.com/fixstars/linux_v4l2_driver.git 4 | [submodule "src/linux/headers"] 5 | path = src/linux/headers 6 | url = https://github.com/fixstars/linux_headers.git 7 | -------------------------------------------------------------------------------- /script/bit2bin.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cat << EOS > /tmp/design.bif 4 | all: 5 | { 6 | [destination_device = pl] ultra96_design/ultra96_design.runs/impl_1/design_1_wrapper.bit 7 | } 8 | EOS 9 | bootgen -image /tmp/design.bif -arch zynqmp -w -o fpga.bin 10 | -------------------------------------------------------------------------------- /test/cam.h: -------------------------------------------------------------------------------- 1 | #ifndef CAM_H 2 | #define CAM_H 3 | 4 | #include 5 | 6 | int v4l2init(int w, int h, __u32 pixelformat); 7 | int v4l2end(void); 8 | int v4l2grab(unsigned char **frame); 9 | int v4l2release(int buf_idx); 10 | 11 | #endif /* CAM_H */ 12 | -------------------------------------------------------------------------------- /src/linux/caminit/build/objects.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | ################################################################################ 4 | 5 | USER_OBJS := 6 | 7 | LIBS := -Wl,-lc,-lstdc++ 8 | -------------------------------------------------------------------------------- /src/linux/caminit/src/camcfg.cc: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int write_reg(int fd, unsigned short addr, unsigned char write_data) 4 | { 5 | unsigned char data[3]; 6 | 7 | data[0] = (addr >> 8) & 0xff; 8 | data[1] = addr & 0xff; 9 | data[2] = write_data; 10 | write(fd, data, 3); 11 | 12 | return 0; 13 | } 14 | -------------------------------------------------------------------------------- /src/linux/caminit/src/camcfg.h: -------------------------------------------------------------------------------- 1 | #ifndef CAMCFG_H 2 | #define CAMCFG_H 3 | 4 | typedef struct _config_t { 5 | unsigned short addr; 6 | unsigned char val; 7 | } config_t; 8 | 9 | int init_ov5640(e_resolution resolution); 10 | int init_imx219(e_resolution resolution); 11 | int write_reg(int fd, unsigned short addr, unsigned char write_data); 12 | 13 | #endif /* CAMCFG_H */ 14 | -------------------------------------------------------------------------------- /overlay/udmabuf0.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/;/plugin/; 2 | / { 3 | fragment@0 { 4 | target-path = "/amba_pl@0"; 5 | #address-celss = <2>; 6 | #size-cells = <2>; 7 | __overlay__ { 8 | udmabuf0 { 9 | compatible = "ikwzm,udmabuf-0.10.a"; 10 | device-name="udmabuf0"; 11 | size = <0x03c00000>; 12 | }; 13 | }; 14 | }; 15 | }; 16 | -------------------------------------------------------------------------------- /ip/demosaic/constraints/demosaic_root_ooc.xdc: -------------------------------------------------------------------------------- 1 | # This constraints file contains default clock frequencies to be used during out-of-context flows such as 2 | # OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified 3 | # to match the target frequencies. 4 | # This constraints file is not used in normal top-down synthesis (the default flow of Vivado) 5 | create_clock -name ap_clk -period 6.660 [get_ports ap_clk] 6 | 7 | -------------------------------------------------------------------------------- /src/linux/caminit/src/caminit.h: -------------------------------------------------------------------------------- 1 | #ifndef CAMINIT_H 2 | #define CAMINIT_H 3 | 4 | typedef enum { 5 | SENSOR_OV5640, 6 | SENSOR_IMX219, 7 | } e_sensor; 8 | 9 | typedef enum { 10 | RESOLUTION_1920_1080, 11 | RESOLUTION_1280_720, 12 | RESOLUTION_960_540, 13 | RESOLUTION_640_480, 14 | RESOLUTION_640_360, 15 | RESOLUTION_320_240, 16 | RESOLUTION_320_200 17 | } e_resolution; 18 | 19 | int caminit(e_sensor sensor, e_resolution resolution); 20 | 21 | #endif /* CAMINIT_H */ 22 | -------------------------------------------------------------------------------- /ip/demosaic/doc/ReleaseNotes.txt: -------------------------------------------------------------------------------- 1 | # ============================================================== 2 | # File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | # Version: 2018.2.2 4 | # Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | # 6 | # ============================================================== 7 | 8 | 9 | Family : zynquplus 10 | Device : xczu3eg 11 | Package : -sbva484 12 | Speed Grade : -1-e 13 | Clock Period : 6.660 ns 14 | -------------------------------------------------------------------------------- /overlay/fclk0-zynqmp.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/;/plugin/; 2 | / { 3 | fragment@0 { 4 | target-path = "/amba"; 5 | __overlay__ { 6 | fclk0 { 7 | compatible = "ikwzm,fclkcfg-0.10.a"; 8 | clocks = <&clk 0x47>; 9 | insert-rate = "100000000"; 10 | insert-enable = <1>; 11 | remove-rate = "1000000"; 12 | remove-enable = <0>; 13 | }; 14 | }; 15 | }; 16 | }; 17 | -------------------------------------------------------------------------------- /overlay/v4l2.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/;/plugin/; 2 | / { 3 | fragment@0 { 4 | target-path = "/amba_pl@0"; 5 | #address-celss = <2>; 6 | #size-cells = <2>; 7 | __overlay__ { 8 | v4l2 { 9 | compatible = "fixstars,zynq-v4l2-1.0"; 10 | #interrupt-cells = <0x3>; 11 | device-name="v4l2"; 12 | interrupt-parent = <&gic>; 13 | interrupts = <0x0 0x59 0x4>; 14 | }; 15 | }; 16 | }; 17 | }; 18 | -------------------------------------------------------------------------------- /src/linux/caminit/build/sources.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | ################################################################################ 4 | 5 | LD_SRCS := 6 | OBJ_SRCS := 7 | S_SRCS := 8 | C_SRCS := 9 | S_UPPER_SRCS := 10 | O_SRCS := 11 | EXECUTABLES := 12 | OBJS := 13 | S_UPPER_DEPS := 14 | C_DEPS := 15 | 16 | # Every subdirectory with source files must be described here 17 | SUBDIRS := \ 18 | src 19 | 20 | -------------------------------------------------------------------------------- /overlay/init_camera.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | mkdir /config/device-tree/overlays/fpga 4 | dtc -I dts -O dtb -o fpga-load.dtb fpga-load.dts 5 | cp fpga-load.dtb /config/device-tree/overlays/fpga/dtbo 6 | 7 | mkdir /config/device-tree/overlays/fclk0 8 | dtc -I dts -O dtb -o fclk0-zynqmp.dtb fclk0-zynqmp.dts 9 | cp fclk0-zynqmp.dtb /config/device-tree/overlays/fclk0/dtbo 10 | 11 | mkdir /config/device-tree/overlays/v4l2 12 | dtc -I dts -O dtb -o v4l2.dtb v4l2.dts 13 | cp v4l2.dtb /config/device-tree/overlays/v4l2/dtbo 14 | 15 | ./caminit 16 | -------------------------------------------------------------------------------- /ip/demosaic/drivers/demosaic_root_v1_0/data/demosaic_root.mdd: -------------------------------------------------------------------------------- 1 | # ============================================================== 2 | # File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | # Version: 2018.2.2 4 | # Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | # 6 | # ============================================================== 7 | 8 | OPTION psf_version = 2.1; 9 | 10 | BEGIN driver demosaic_root 11 | 12 | OPTION supported_peripherals = (demosaic_root_v1_0 ); 13 | OPTION driver_state = ACTIVE; 14 | OPTION copyfiles = all; 15 | OPTION name = demosaic_root; 16 | OPTION version = 1.0; 17 | 18 | END driver 19 | 20 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/verilog/demosaic_root_muldEe.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ps 3 | 4 | module demosaic_root_muldEe_DSP48_0(a, b, p); 5 | input [20 - 1 : 0] a; 6 | input [8 - 1 : 0] b; 7 | output [27 - 1 : 0] p; 8 | 9 | assign p = $unsigned (a) * $unsigned (b); 10 | 11 | endmodule 12 | 13 | `timescale 1 ns / 1 ps 14 | module demosaic_root_muldEe( 15 | din0, 16 | din1, 17 | dout); 18 | 19 | parameter ID = 32'd1; 20 | parameter NUM_STAGE = 32'd1; 21 | parameter din0_WIDTH = 32'd1; 22 | parameter din1_WIDTH = 32'd1; 23 | parameter dout_WIDTH = 32'd1; 24 | input[din0_WIDTH - 1:0] din0; 25 | input[din1_WIDTH - 1:0] din1; 26 | output[dout_WIDTH - 1:0] dout; 27 | 28 | 29 | 30 | demosaic_root_muldEe_DSP48_0 demosaic_root_muldEe_DSP48_0_U( 31 | .a( din0 ), 32 | .b( din1 ), 33 | .p( dout )); 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/verilog/demosaic_root_muleOg.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ps 3 | 4 | module demosaic_root_muleOg_DSP48_1(a, b, p); 5 | input [21 - 1 : 0] a; 6 | input [8 - 1 : 0] b; 7 | output [28 - 1 : 0] p; 8 | 9 | assign p = $unsigned (a) * $unsigned (b); 10 | 11 | endmodule 12 | 13 | `timescale 1 ns / 1 ps 14 | module demosaic_root_muleOg( 15 | din0, 16 | din1, 17 | dout); 18 | 19 | parameter ID = 32'd1; 20 | parameter NUM_STAGE = 32'd1; 21 | parameter din0_WIDTH = 32'd1; 22 | parameter din1_WIDTH = 32'd1; 23 | parameter dout_WIDTH = 32'd1; 24 | input[din0_WIDTH - 1:0] din0; 25 | input[din1_WIDTH - 1:0] din1; 26 | output[dout_WIDTH - 1:0] dout; 27 | 28 | 29 | 30 | demosaic_root_muleOg_DSP48_1 demosaic_root_muleOg_DSP48_1_U( 31 | .a( din0 ), 32 | .b( din1 ), 33 | .p( dout )); 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/verilog/demosaic_root_mulocq.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ps 3 | 4 | module demosaic_root_mulocq_DSP48_8(a, b, p); 5 | input [18 - 1 : 0] a; 6 | input [8 - 1 : 0] b; 7 | output [25 - 1 : 0] p; 8 | 9 | assign p = $unsigned (a) * $unsigned (b); 10 | 11 | endmodule 12 | 13 | `timescale 1 ns / 1 ps 14 | module demosaic_root_mulocq( 15 | din0, 16 | din1, 17 | dout); 18 | 19 | parameter ID = 32'd1; 20 | parameter NUM_STAGE = 32'd1; 21 | parameter din0_WIDTH = 32'd1; 22 | parameter din1_WIDTH = 32'd1; 23 | parameter dout_WIDTH = 32'd1; 24 | input[din0_WIDTH - 1:0] din0; 25 | input[din1_WIDTH - 1:0] din1; 26 | output[dout_WIDTH - 1:0] dout; 27 | 28 | 29 | 30 | demosaic_root_mulocq_DSP48_8 demosaic_root_mulocq_DSP48_8_U( 31 | .a( din0 ), 32 | .b( din1 ), 33 | .p( dout )); 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /etc/xorg.conf: -------------------------------------------------------------------------------- 1 | Section "InputDevice" 2 | Identifier "System Mouse" 3 | Driver "mouse" 4 | Option "Device" "/dev/input/mouse0" 5 | EndSection 6 | 7 | Section "InputDevice" 8 | Identifier "System Keyboard" 9 | Driver "kbd" 10 | Option "Device" "/dev/input/event0" 11 | EndSection 12 | 13 | Section "Device" 14 | Identifier "ZynqMP" 15 | Driver "fbdev" 16 | Option "DRI2" "true" 17 | Option "DRI2_PAGE_FLIP" "false" 18 | Option "DRI2_WAIT_VSYNC" "true" 19 | Option "SWcursorLCD" "false" 20 | Option "DEBUG" "false" 21 | EndSection 22 | 23 | Section "Screen" 24 | Identifier "DefaultScreen" 25 | Device "ZynqMP" 26 | DefaultDepth 16 27 | EndSection 28 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/verilog/demosaic_root_mulhbi.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ps 3 | 4 | module demosaic_root_mulhbi_DSP48_4(a, b, p); 5 | input signed [10 - 1 : 0] a; 6 | input [18 - 1 : 0] b; 7 | output signed [28 - 1 : 0] p; 8 | 9 | assign p = $signed (a) * $signed ({1'b0, b}); 10 | 11 | endmodule 12 | 13 | `timescale 1 ns / 1 ps 14 | module demosaic_root_mulhbi( 15 | din0, 16 | din1, 17 | dout); 18 | 19 | parameter ID = 32'd1; 20 | parameter NUM_STAGE = 32'd1; 21 | parameter din0_WIDTH = 32'd1; 22 | parameter din1_WIDTH = 32'd1; 23 | parameter dout_WIDTH = 32'd1; 24 | input[din0_WIDTH - 1:0] din0; 25 | input[din1_WIDTH - 1:0] din1; 26 | output[dout_WIDTH - 1:0] dout; 27 | 28 | 29 | 30 | demosaic_root_mulhbi_DSP48_4 demosaic_root_mulhbi_DSP48_4_U( 31 | .a( din0 ), 32 | .b( din1 ), 33 | .p( dout )); 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /ip/demosaic/xgui/demosaic_root_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | #Adding Group 7 | ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)} 8 | 9 | 10 | 11 | } 12 | 13 | 14 | proc update_MODELPARAM_VALUE.C_S_AXI_BUS_AXI4LS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_BUS_AXI4LS_ADDR_WIDTH } { 15 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 16 | # WARNING: There is no corresponding user parameter named "C_S_AXI_BUS_AXI4LS_ADDR_WIDTH". Setting updated value from the model parameter. 17 | set_property value 5 ${MODELPARAM_VALUE.C_S_AXI_BUS_AXI4LS_ADDR_WIDTH} 18 | } 19 | 20 | -------------------------------------------------------------------------------- /test/makefile: -------------------------------------------------------------------------------- 1 | OPENCV_DIR=./opencv-3.4.1 2 | INCLUDE=-I${OPENCV_DIR}/build -I${OPENCV_DIR}/modules/core/include -I${OPENCV_DIR}/modules/highgui/include -I${OPENCV_DIR}/modules/imgproc/include -I${OPENCV_DIR}/modules/imgcodecs/include -I${OPENCV_DIR}/modules/videoio/include 3 | LIB=-L${OPENCV_DIR}/build/lib -lstdc++ -lopencv_core -lopencv_imgcodecs -lopencv_highgui 4 | 5 | all: rgbtest yuvtest rgbvideo uvc_camera_test 6 | 7 | rgbtest: rgbtest.cc cam.cc 8 | g++ -g -o $@ $^ ${INCLUDE} ${LIB} 9 | 10 | yuvtest: yuvtest.cc cam.cc 11 | g++ -g -o $@ $^ ${INCLUDE} ${LIB} 12 | 13 | rgbvideo: rgbvideo.cc cam.cc 14 | g++ -g -o $@ $^ ${INCLUDE} ${LIB} 15 | 16 | uvc_camera_test: uvc_camera_test.cc 17 | g++ -g -o $@ $< camera_umd/uvc_camera/src/uvc_cam.cpp ${INCLUDE} -I./camera_umd/uvc_camera/include/ ${LIB} 18 | 19 | clean: 20 | rm rgbtest yuvtest rgbvideo uvc_camera_test 21 | 22 | -------------------------------------------------------------------------------- /ip/demosaic/drivers/demosaic_root_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | # ============================================================== 2 | # File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | # Version: 2018.2.2 4 | # Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | # 6 | # ============================================================== 7 | 8 | COMPILER= 9 | ARCHIVER= 10 | CP=cp 11 | COMPILER_FLAGS= 12 | EXTRA_COMPILER_FLAGS= 13 | LIB=libxil.a 14 | 15 | RELEASEDIR=../../../lib 16 | INCLUDEDIR=../../../include 17 | INCLUDES=-I./. -I${INCLUDEDIR} 18 | 19 | INCLUDEFILES=*.h 20 | LIBSOURCES=*.c 21 | OUTS = *.o 22 | 23 | 24 | libs: 25 | echo "Compiling demosaic_root" 26 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 27 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS) 28 | make clean 29 | 30 | include: 31 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 32 | 33 | clean: 34 | rm -rf ${OUTS} 35 | 36 | -------------------------------------------------------------------------------- /ip/demosaic/drivers/demosaic_root_v1_0/data/demosaic_root.tcl: -------------------------------------------------------------------------------- 1 | # ============================================================== 2 | # File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | # Version: 2018.2.2 4 | # Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | # 6 | # ============================================================== 7 | 8 | proc generate {drv_handle} { 9 | xdefine_include_file $drv_handle "xparameters.h" "XDemosaic_root" \ 10 | "NUM_INSTANCES" \ 11 | "DEVICE_ID" \ 12 | "C_S_AXI_BUS_AXI4LS_BASEADDR" \ 13 | "C_S_AXI_BUS_AXI4LS_HIGHADDR" 14 | 15 | xdefine_config_file $drv_handle "xdemosaic_root_g.c" "XDemosaic_root" \ 16 | "DEVICE_ID" \ 17 | "C_S_AXI_BUS_AXI4LS_BASEADDR" 18 | 19 | xdefine_canonical_xpars $drv_handle "xparameters.h" "XDemosaic_root" \ 20 | "DEVICE_ID" \ 21 | "C_S_AXI_BUS_AXI4LS_BASEADDR" \ 22 | "C_S_AXI_BUS_AXI4LS_HIGHADDR" 23 | } 24 | 25 | -------------------------------------------------------------------------------- /test/uvc_camera_test.cc: -------------------------------------------------------------------------------- 1 | #include "uvc_cam/uvc_cam.h" 2 | #include 3 | #include 4 | #include 5 | 6 | #define WIDTH 640 7 | #define HEIGHT 480 8 | 9 | int main(int argc, char *argv[]) 10 | { 11 | unsigned char *mem; 12 | uint32_t bytes; 13 | int idx; 14 | int w = WIDTH, h = HEIGHT; 15 | uvc_cam::Cam cam("/dev/video0", uvc_cam::Cam::MODE_RGB, w, h); 16 | 17 | cam.enumerate(); 18 | cam.v4l2_query(0, "testquery"); 19 | cam.set_v4l2_control(0, 0, "testset"); 20 | //cam.set_control(0, 0); 21 | cam.set_motion_thresholds(0, 0); 22 | 23 | cv::Mat frame(h, w, CV_8UC3); 24 | for (int i = 0; i < 20; i++) { 25 | idx = cam.grab(&mem, bytes); 26 | printf("i = %d, idx = %d\n", i, idx); 27 | frame.data = mem; 28 | std::stringstream ss; 29 | ss << "./" << i << ".png"; 30 | cv::imwrite(ss.str(), frame); 31 | cam.release(idx); 32 | } 33 | 34 | return 0; 35 | } 36 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Ultra96 Design 2 | 3 | ## Requirement 4 | 5 | These are **MANDATORY** items to be installed. 6 | 7 | 1. Vivado 2018.2 8 | 2. License of Xilinx MIPI CSI-2 Controller SubSystem 9 | 10 | You can use Evaluation license for Xilinx MIPI IP. Please go to the [product page](https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html). 11 | 12 | ## Getting started 13 | 14 | You need to create project by tcl script when right after cloning the repos. 15 | Launch vivado and create project by tcl file. 16 | 17 | ```.tcl 18 | source script/create_project.tcl 19 | ``` 20 | 21 | Then you can do synthesize, implementation and create bitstream whatever. 22 | 23 | 24 | ## Work with git 25 | 26 | If you updated block design, please export design to script/create\_bd.tcl and commit it. 27 | 28 | ```.tcl 29 | write_bd_tcl script/create_bd.tcl 30 | ``` 31 | 32 | If you want to add new IP, please extract IP archive(.zip) into ip/ directory and commit them. 33 | 34 | If you want to add new files or directories, handle them in script/create\_project.tcl and commit them. 35 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Fixstars 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /src/linux/caminit/build/src/subdir.mk: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | ################################################################################ 4 | 5 | # Add inputs and outputs from these tool invocations to the build variables 6 | CC_SRCS += \ 7 | ../src/caminit.cc ../src/camcfg.cc ../src/ov5640.cc ../src/imx219.cc 8 | 9 | CC_DEPS += \ 10 | ./src/caminit.d ./src/camcfg.d ./src/ov5640.d ./src/imx219.d 11 | 12 | OBJS += \ 13 | ./src/caminit.o ./src/camcfg.o ./src/ov5640.o ./src/imx219.o 14 | 15 | MAIN_DEPS += \ 16 | ./src/main.d 17 | 18 | MAIN_OBJS += \ 19 | ./src/main.o 20 | 21 | BSP_DIR = ../../../../ultra96_design/ultra96_design.sdk/standalone_bsp_0/psu_cortexa53_0/ 22 | 23 | # Each subdirectory must supply rules for building sources it contributes 24 | src/%.o: ../src/%.cc 25 | @echo 'Building file: $<' 26 | @echo 'Invoking: ARM v7 g++ compiler' 27 | aarch64-linux-gnu-g++ -Wall -O0 -g3 -std=c++11 -c -fmessage-length=0 -fpermissive -MT"$@" -I${BSP_DIR}/include -I ../src/ -g -fPIC -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" 28 | @echo 'Finished building: $<' 29 | @echo ' ' 30 | -------------------------------------------------------------------------------- /src/verilog/design_1_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2018.2.2 (lin64) Build 2348494 Mon Oct 1 18:25:39 MDT 2018 4 | //Date : Tue Nov 6 22:18:18 2018 5 | //Host : uroboros running 64-bit Ubuntu 16.04.5 LTS 6 | //Command : generate_target design_1_wrapper.bd 7 | //Design : design_1_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module design_1_wrapper 13 | (mipi_phy_csi_clk_n, 14 | mipi_phy_csi_clk_p, 15 | mipi_phy_csi_data_n, 16 | mipi_phy_csi_data_p); 17 | input mipi_phy_csi_clk_n; 18 | input mipi_phy_csi_clk_p; 19 | input [1:0]mipi_phy_csi_data_n; 20 | input [1:0]mipi_phy_csi_data_p; 21 | 22 | wire mipi_phy_csi_clk_n; 23 | wire mipi_phy_csi_clk_p; 24 | wire [1:0]mipi_phy_csi_data_n; 25 | wire [1:0]mipi_phy_csi_data_p; 26 | 27 | design_1 design_1_i 28 | (.mipi_phy_csi_clk_n(mipi_phy_csi_clk_n), 29 | .mipi_phy_csi_clk_p(mipi_phy_csi_clk_p), 30 | .mipi_phy_csi_data_n(mipi_phy_csi_data_n), 31 | .mipi_phy_csi_data_p(mipi_phy_csi_data_p)); 32 | endmodule 33 | -------------------------------------------------------------------------------- /test/rgbtest.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include "cam.h" 8 | 9 | #define WIDTH 640 10 | #define HEIGHT 480 11 | 12 | int main() 13 | { 14 | int rc; 15 | int w = WIDTH, h = HEIGHT; 16 | unsigned char *buf; 17 | 18 | rc = v4l2init(w, h, V4L2_PIX_FMT_RGB24); 19 | if (rc < 0) { 20 | fprintf(stderr, "v4l2init = %d\n", rc); 21 | return -1; 22 | } 23 | 24 | cv::Mat frame(h, w, CV_8UC3); 25 | for (int i = 0; i < 20; i++) { 26 | printf("frame %d\n", i); 27 | rc = v4l2grab(&buf); 28 | if (rc < 0) { 29 | fprintf(stderr, "v4l2grab = %d\n", rc); 30 | return -1; 31 | } 32 | frame.data = buf; 33 | std::stringstream ss; 34 | ss << "./" << i << ".png"; 35 | cv::imwrite(ss.str(), frame); 36 | rc = v4l2release(rc); 37 | if (rc < 0) { 38 | fprintf(stderr, "v4l2release = %d\n", rc); 39 | return -1; 40 | } 41 | } 42 | 43 | rc = v4l2end(); 44 | if (rc < 0) { 45 | fprintf(stderr, "v4l2release = %d\n", rc); 46 | return -1; 47 | } 48 | 49 | return 0; 50 | } 51 | -------------------------------------------------------------------------------- /src/linux/caminit/build/makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Automatically-generated file. Do not edit! 3 | ################################################################################ 4 | 5 | -include ../makefile.init 6 | 7 | RM := rm -rf 8 | 9 | # All of the sources participating in the build are defined here 10 | -include sources.mk 11 | -include src/subdir.mk 12 | -include subdir.mk 13 | -include objects.mk 14 | 15 | ifneq ($(MAKECMDGOALS),clean) 16 | ifneq ($(strip $(S_UPPER_DEPS)),) 17 | -include $(S_UPPER_DEPS) 18 | endif 19 | ifneq ($(strip $(C_DEPS)),) 20 | -include $(C_DEPS) 21 | endif 22 | endif 23 | 24 | -include ../makefile.defs 25 | 26 | # Add inputs and outputs from these tool invocations to the build variables 27 | 28 | # All Target 29 | all: caminit 30 | 31 | # Tool invocations 32 | caminit: $(MAIN_OBJS) $(USER_OBJS) $(OBJS) 33 | @echo 'Building target: $@' 34 | @echo 'Invoking: ARM v7 gcc linker' 35 | aarch64-linux-gnu-gcc -o $@ $(MAIN_OBJS) $(USER_OBJS) $(OBJS) $(LIBS) -L . -Wl,-no-enum-size-warning 36 | @echo 'Finished building target: $@' 37 | @echo ' ' 38 | 39 | # Other Targets 40 | clean: 41 | -$(RM) $(EXECUTABLES)$(OBJS)$(S_UPPER_DEPS)$(CC_DEPS)$(MAIN_OBJS)$(MAIN_DEPS) caminit 42 | -@echo ' ' 43 | 44 | .PHONY: all clean dependents 45 | .SECONDARY: 46 | 47 | -include ../makefile.targets 48 | -------------------------------------------------------------------------------- /ip/demosaic/drivers/demosaic_root_v1_0/src/xdemosaic_root_sinit.c: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2018.2.2 4 | // Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | #ifndef __linux__ 9 | 10 | #include "xstatus.h" 11 | #include "xparameters.h" 12 | #include "xdemosaic_root.h" 13 | 14 | extern XDemosaic_root_Config XDemosaic_root_ConfigTable[]; 15 | 16 | XDemosaic_root_Config *XDemosaic_root_LookupConfig(u16 DeviceId) { 17 | XDemosaic_root_Config *ConfigPtr = NULL; 18 | 19 | int Index; 20 | 21 | for (Index = 0; Index < XPAR_XDEMOSAIC_ROOT_NUM_INSTANCES; Index++) { 22 | if (XDemosaic_root_ConfigTable[Index].DeviceId == DeviceId) { 23 | ConfigPtr = &XDemosaic_root_ConfigTable[Index]; 24 | break; 25 | } 26 | } 27 | 28 | return ConfigPtr; 29 | } 30 | 31 | int XDemosaic_root_Initialize(XDemosaic_root *InstancePtr, u16 DeviceId) { 32 | XDemosaic_root_Config *ConfigPtr; 33 | 34 | Xil_AssertNonvoid(InstancePtr != NULL); 35 | 36 | ConfigPtr = XDemosaic_root_LookupConfig(DeviceId); 37 | if (ConfigPtr == NULL) { 38 | InstancePtr->IsReady = 0; 39 | return (XST_DEVICE_NOT_FOUND); 40 | } 41 | 42 | return XDemosaic_root_CfgInitialize(InstancePtr, ConfigPtr); 43 | } 44 | 45 | #endif 46 | 47 | -------------------------------------------------------------------------------- /test/rgbvideo.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include "cam.h" 8 | 9 | #define WIDTH 640 10 | #define HEIGHT 480 11 | 12 | int main() 13 | { 14 | int rc, key; 15 | unsigned char *buf; 16 | unsigned char rgb_buf[WIDTH * HEIGHT * 3]; 17 | int w = WIDTH, h = HEIGHT; 18 | 19 | rc = v4l2init(w, h, V4L2_PIX_FMT_RGB24); 20 | if (rc < 0) { 21 | fprintf(stderr, "v4l2init = %d\n", rc); 22 | return -1; 23 | } 24 | 25 | cv::Mat img(cv::Size(w, h), CV_8UC3); 26 | const char window[16] = "camera"; 27 | cv::namedWindow(window); 28 | 29 | while (1) { 30 | rc = v4l2grab(&buf); 31 | if (rc < 0) { 32 | fprintf(stderr, "v4l2grab = %d\n", rc); 33 | return -1; 34 | } 35 | memcpy(rgb_buf, buf, WIDTH * HEIGHT * 3); 36 | rc = v4l2release(rc); 37 | if (rc < 0) { 38 | fprintf(stderr, "v4l2release = %d\n", rc); 39 | return -1; 40 | } 41 | img.data = rgb_buf; 42 | cv::imshow(window, img); 43 | key = cv::waitKey(1); 44 | if (key == 'q') { 45 | break; 46 | } 47 | } 48 | rc = v4l2end(); 49 | if (rc < 0) { 50 | fprintf(stderr, "v4l2end = %d\n", rc); 51 | return -1; 52 | } 53 | 54 | return 0; 55 | } 56 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/verilog/demosaic_root_macfYi.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2018.2.2 4 | // Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | 10 | module demosaic_root_macfYi_DSP48_0( 11 | input [14 - 1:0] in0, 12 | input [11 - 1:0] in1, 13 | input [23 - 1:0] in2, 14 | output [24 - 1:0] dout); 15 | 16 | wire signed [27 - 1:0] a; 17 | wire signed [18 - 1:0] b; 18 | wire signed [48 - 1:0] c; 19 | wire signed [45 - 1:0] m; 20 | wire signed [48 - 1:0] p; 21 | 22 | assign a = $signed(in0); 23 | assign b = $unsigned(in1); 24 | assign c = $unsigned(in2); 25 | 26 | assign m = a * b; 27 | assign p = m + c; 28 | 29 | assign dout = p; 30 | 31 | endmodule 32 | 33 | `timescale 1 ns / 1 ps 34 | module demosaic_root_macfYi( 35 | din0, 36 | din1, 37 | din2, 38 | dout); 39 | 40 | parameter ID = 32'd1; 41 | parameter NUM_STAGE = 32'd1; 42 | parameter din0_WIDTH = 32'd1; 43 | parameter din1_WIDTH = 32'd1; 44 | parameter din2_WIDTH = 32'd1; 45 | parameter dout_WIDTH = 32'd1; 46 | input[din0_WIDTH - 1:0] din0; 47 | input[din1_WIDTH - 1:0] din1; 48 | input[din2_WIDTH - 1:0] din2; 49 | output[dout_WIDTH - 1:0] dout; 50 | 51 | 52 | 53 | demosaic_root_macfYi_DSP48_0 demosaic_root_macfYi_DSP48_0_U( 54 | .in0( din0 ), 55 | .in1( din1 ), 56 | .in2( din2 ), 57 | .dout( dout )); 58 | 59 | endmodule 60 | 61 | -------------------------------------------------------------------------------- /ip/demosaic/drivers/demosaic_root_v1_0/src/xdemosaic_root_hw.h: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2018.2.2 4 | // Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | // BUS_AXI4LS 9 | // 0x00 : Control signals 10 | // bit 0 - ap_start (Read/Write/COH) 11 | // bit 1 - ap_done (Read/COR) 12 | // bit 2 - ap_idle (Read) 13 | // bit 3 - ap_ready (Read) 14 | // bit 7 - auto_restart (Read/Write) 15 | // others - reserved 16 | // 0x04 : Global Interrupt Enable Register 17 | // bit 0 - Global Interrupt Enable (Read/Write) 18 | // others - reserved 19 | // 0x08 : IP Interrupt Enable Register (Read/Write) 20 | // bit 0 - Channel 0 (ap_done) 21 | // bit 1 - Channel 1 (ap_ready) 22 | // others - reserved 23 | // 0x0c : IP Interrupt Status Register (Read/TOW) 24 | // bit 0 - Channel 0 (ap_done) 25 | // bit 1 - Channel 1 (ap_ready) 26 | // others - reserved 27 | // 0x10 : Data signal of ap_return 28 | // bit 31~0 - ap_return[31:0] (Read) 29 | // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) 30 | 31 | #define XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_CTRL 0x00 32 | #define XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_GIE 0x04 33 | #define XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_IER 0x08 34 | #define XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_ISR 0x0c 35 | #define XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_RETURN 0x10 36 | #define XDEMOSAIC_ROOT_BUS_AXI4LS_BITS_AP_RETURN 32 37 | 38 | -------------------------------------------------------------------------------- /src/linux/caminit/src/caminit.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include "caminit.h" 12 | #include "camcfg.h" 13 | 14 | static int (*init_camera[])(e_resolution resolution) = { 15 | init_ov5640, 16 | init_imx219 17 | }; 18 | 19 | static int set_cam_gpio(int val) 20 | { 21 | int fd; 22 | char attr[32]; 23 | 24 | DIR *dir = opendir("/sys/class/gpio/gpio375"); 25 | if (!dir) { 26 | fd = open("/sys/class/gpio/export", O_WRONLY); 27 | if (fd < 0) { 28 | perror("open(/sys/class/gpio/export)"); 29 | return -1; 30 | } 31 | strcpy(attr, "375"); 32 | write(fd, attr, strlen(attr)); 33 | close(fd); 34 | dir = opendir("/sys/class/gpio/gpio375"); 35 | if (!dir) { 36 | perror("opendir(/sys/class/gpio/gpio375)"); 37 | return -1; 38 | } 39 | } 40 | closedir(dir); 41 | 42 | fd = open("/sys/class/gpio/gpio375/direction", O_WRONLY); 43 | if (fd < 0) { 44 | perror("open(/sys/class/gpio/gpio375/direction)"); 45 | return -1; 46 | } 47 | strcpy(attr, "out"); 48 | write(fd, attr, strlen(attr)); 49 | close(fd); 50 | 51 | fd = open("/sys/class/gpio/gpio375/value", O_WRONLY); 52 | if (fd < 0) { 53 | perror("open(/sys/class/gpio/gpio375/value)"); 54 | return -1; 55 | } 56 | sprintf(attr, "%d", val); 57 | write(fd, attr, strlen(attr)); 58 | close(fd); 59 | 60 | return 0; 61 | } 62 | 63 | int caminit(e_sensor sensor, e_resolution resolution) 64 | { 65 | set_cam_gpio(0); 66 | usleep(300*1000); 67 | set_cam_gpio(1); 68 | usleep(300*1000); 69 | 70 | init_camera[sensor](resolution); 71 | 72 | return 0; 73 | } 74 | -------------------------------------------------------------------------------- /ip/demosaic/bd/bd.tcl: -------------------------------------------------------------------------------- 1 | # ============================================================== 2 | # File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | # Version: 2018.2.2 4 | # Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | # 6 | # ============================================================== 7 | 8 | source -notrace [file join [file dirname [get_property XML_FILE_NAME [get_ipdefs -all -quiet xilinx.com:ip:xbip_utils:3.0]]] "common_tcl/common.tcl"] 9 | common_tcl::gen_procs xilinx.com:hls:demosaic_root:1.0 10 | 11 | source_subcore_ipfile xilinx.com:ip:xbip_utils:3.0 "common_tcl/vip.tcl" 12 | 13 | proc init {cellpath otherInfo } { 14 | set cellobj [get_bd_cells $cellpath] 15 | 16 | vip_set_datatype_file "none" 17 | vip $cellobj puts_debug "INIT ..............." ;# This will create the Virtual IP object 18 | } 19 | 20 | proc post_config_ip {cellpath otherInfo } { 21 | # Any updates to interface properties based on user configuration 22 | set cellobj [get_bd_cells $cellpath] 23 | 24 | vip $cellobj puts_debug "POST_CONFIG_IP Starting..............." 25 | 26 | vip $cellobj update_busparams true 27 | vip $cellobj update_datatypes 28 | 29 | vip $cellobj puts_debug "...........POST_CONFIG_IP Complete" 30 | } 31 | 32 | proc propagate { cellpath otherInfo } { 33 | set cellobj [get_bd_cells $cellpath] 34 | 35 | # Refresh again. 36 | vip $cellobj update_busparams 37 | vip $cellobj update_datatypes 38 | } 39 | 40 | proc post_propagate { cellpath otherInfo } { 41 | set cellobj [get_bd_cells $cellpath] 42 | 43 | vip $cellobj puts_debug "POST_PROPAGATE Starting..............." 44 | vip $cellobj validate_datatypes 45 | vip $cellobj puts_debug "...........POST_PROPAGATE Complete" 46 | } 47 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/demosaic_root_muldEe.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | 6 | entity demosaic_root_muldEe_DSP48_0 is 7 | port ( 8 | a: in std_logic_vector(20 - 1 downto 0); 9 | b: in std_logic_vector(8 - 1 downto 0); 10 | p: out std_logic_vector(27 - 1 downto 0)); 11 | 12 | end entity; 13 | 14 | architecture behav of demosaic_root_muldEe_DSP48_0 is 15 | signal a_cvt: unsigned(20 - 1 downto 0); 16 | signal b_cvt: unsigned(8 - 1 downto 0); 17 | signal p_cvt: unsigned(27 - 1 downto 0); 18 | 19 | 20 | begin 21 | 22 | a_cvt <= unsigned(a); 23 | b_cvt <= unsigned(b); 24 | p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 27)); 25 | p <= std_logic_vector(p_cvt); 26 | 27 | end architecture; 28 | 29 | Library IEEE; 30 | use IEEE.std_logic_1164.all; 31 | 32 | entity demosaic_root_muldEe is 33 | generic ( 34 | ID : INTEGER; 35 | NUM_STAGE : INTEGER; 36 | din0_WIDTH : INTEGER; 37 | din1_WIDTH : INTEGER; 38 | dout_WIDTH : INTEGER); 39 | port ( 40 | din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); 41 | din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); 42 | dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); 43 | end entity; 44 | 45 | architecture arch of demosaic_root_muldEe is 46 | component demosaic_root_muldEe_DSP48_0 is 47 | port ( 48 | a : IN STD_LOGIC_VECTOR; 49 | b : IN STD_LOGIC_VECTOR; 50 | p : OUT STD_LOGIC_VECTOR); 51 | end component; 52 | 53 | 54 | 55 | begin 56 | demosaic_root_muldEe_DSP48_0_U : component demosaic_root_muldEe_DSP48_0 57 | port map ( 58 | a => din0, 59 | b => din1, 60 | p => dout); 61 | 62 | end architecture; 63 | 64 | 65 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/demosaic_root_muleOg.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | 6 | entity demosaic_root_muleOg_DSP48_1 is 7 | port ( 8 | a: in std_logic_vector(21 - 1 downto 0); 9 | b: in std_logic_vector(8 - 1 downto 0); 10 | p: out std_logic_vector(28 - 1 downto 0)); 11 | 12 | end entity; 13 | 14 | architecture behav of demosaic_root_muleOg_DSP48_1 is 15 | signal a_cvt: unsigned(21 - 1 downto 0); 16 | signal b_cvt: unsigned(8 - 1 downto 0); 17 | signal p_cvt: unsigned(28 - 1 downto 0); 18 | 19 | 20 | begin 21 | 22 | a_cvt <= unsigned(a); 23 | b_cvt <= unsigned(b); 24 | p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 28)); 25 | p <= std_logic_vector(p_cvt); 26 | 27 | end architecture; 28 | 29 | Library IEEE; 30 | use IEEE.std_logic_1164.all; 31 | 32 | entity demosaic_root_muleOg is 33 | generic ( 34 | ID : INTEGER; 35 | NUM_STAGE : INTEGER; 36 | din0_WIDTH : INTEGER; 37 | din1_WIDTH : INTEGER; 38 | dout_WIDTH : INTEGER); 39 | port ( 40 | din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); 41 | din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); 42 | dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); 43 | end entity; 44 | 45 | architecture arch of demosaic_root_muleOg is 46 | component demosaic_root_muleOg_DSP48_1 is 47 | port ( 48 | a : IN STD_LOGIC_VECTOR; 49 | b : IN STD_LOGIC_VECTOR; 50 | p : OUT STD_LOGIC_VECTOR); 51 | end component; 52 | 53 | 54 | 55 | begin 56 | demosaic_root_muleOg_DSP48_1_U : component demosaic_root_muleOg_DSP48_1 57 | port map ( 58 | a => din0, 59 | b => din1, 60 | p => dout); 61 | 62 | end architecture; 63 | 64 | 65 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/demosaic_root_mulhbi.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | 6 | entity demosaic_root_mulhbi_DSP48_4 is 7 | port ( 8 | a: in std_logic_vector(10 - 1 downto 0); 9 | b: in std_logic_vector(18 - 1 downto 0); 10 | p: out std_logic_vector(28 - 1 downto 0)); 11 | 12 | end entity; 13 | 14 | architecture behav of demosaic_root_mulhbi_DSP48_4 is 15 | signal a_cvt: signed(10 - 1 downto 0); 16 | signal b_cvt: unsigned(18 - 1 downto 0); 17 | signal p_cvt: signed(28 - 1 downto 0); 18 | 19 | 20 | begin 21 | 22 | a_cvt <= signed(a); 23 | b_cvt <= unsigned(b); 24 | p_cvt <= signed (resize(unsigned (signed (a_cvt) * signed ('0' & b_cvt)), 28)); 25 | p <= std_logic_vector(p_cvt); 26 | 27 | end architecture; 28 | 29 | Library IEEE; 30 | use IEEE.std_logic_1164.all; 31 | 32 | entity demosaic_root_mulhbi is 33 | generic ( 34 | ID : INTEGER; 35 | NUM_STAGE : INTEGER; 36 | din0_WIDTH : INTEGER; 37 | din1_WIDTH : INTEGER; 38 | dout_WIDTH : INTEGER); 39 | port ( 40 | din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); 41 | din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); 42 | dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); 43 | end entity; 44 | 45 | architecture arch of demosaic_root_mulhbi is 46 | component demosaic_root_mulhbi_DSP48_4 is 47 | port ( 48 | a : IN STD_LOGIC_VECTOR; 49 | b : IN STD_LOGIC_VECTOR; 50 | p : OUT STD_LOGIC_VECTOR); 51 | end component; 52 | 53 | 54 | 55 | begin 56 | demosaic_root_mulhbi_DSP48_4_U : component demosaic_root_mulhbi_DSP48_4 57 | port map ( 58 | a => din0, 59 | b => din1, 60 | p => dout); 61 | 62 | end architecture; 63 | 64 | 65 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/demosaic_root_mulocq.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | 6 | entity demosaic_root_mulocq_DSP48_8 is 7 | port ( 8 | a: in std_logic_vector(18 - 1 downto 0); 9 | b: in std_logic_vector(8 - 1 downto 0); 10 | p: out std_logic_vector(25 - 1 downto 0)); 11 | 12 | end entity; 13 | 14 | architecture behav of demosaic_root_mulocq_DSP48_8 is 15 | signal a_cvt: unsigned(18 - 1 downto 0); 16 | signal b_cvt: unsigned(8 - 1 downto 0); 17 | signal p_cvt: unsigned(25 - 1 downto 0); 18 | 19 | 20 | begin 21 | 22 | a_cvt <= unsigned(a); 23 | b_cvt <= unsigned(b); 24 | p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 25)); 25 | p <= std_logic_vector(p_cvt); 26 | 27 | end architecture; 28 | 29 | Library IEEE; 30 | use IEEE.std_logic_1164.all; 31 | 32 | entity demosaic_root_mulocq is 33 | generic ( 34 | ID : INTEGER; 35 | NUM_STAGE : INTEGER; 36 | din0_WIDTH : INTEGER; 37 | din1_WIDTH : INTEGER; 38 | dout_WIDTH : INTEGER); 39 | port ( 40 | din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); 41 | din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); 42 | dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); 43 | end entity; 44 | 45 | architecture arch of demosaic_root_mulocq is 46 | component demosaic_root_mulocq_DSP48_8 is 47 | port ( 48 | a : IN STD_LOGIC_VECTOR; 49 | b : IN STD_LOGIC_VECTOR; 50 | p : OUT STD_LOGIC_VECTOR); 51 | end component; 52 | 53 | 54 | 55 | begin 56 | demosaic_root_mulocq_DSP48_8_U : component demosaic_root_mulocq_DSP48_8 57 | port map ( 58 | a => din0, 59 | b => din1, 60 | p => dout); 61 | 62 | end architecture; 63 | 64 | 65 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/verilog/odata_p_idata_bufbkb.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2018.2.2 4 | // Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | module odata_p_idata_bufbkb_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk); 10 | 11 | parameter DWIDTH = 40; 12 | parameter AWIDTH = 8; 13 | parameter MEM_SIZE = 256; 14 | 15 | input[AWIDTH-1:0] addr0; 16 | input ce0; 17 | output reg[DWIDTH-1:0] q0; 18 | input[AWIDTH-1:0] addr1; 19 | input ce1; 20 | input[DWIDTH-1:0] d1; 21 | input we1; 22 | input clk; 23 | 24 | (* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1]; 25 | 26 | 27 | 28 | 29 | always @(posedge clk) 30 | begin 31 | if (ce0) 32 | begin 33 | q0 <= ram[addr0]; 34 | end 35 | end 36 | 37 | 38 | always @(posedge clk) 39 | begin 40 | if (ce1) 41 | begin 42 | if (we1) 43 | begin 44 | ram[addr1] <= d1; 45 | end 46 | end 47 | end 48 | 49 | 50 | endmodule 51 | 52 | 53 | `timescale 1 ns / 1 ps 54 | module odata_p_idata_bufbkb( 55 | reset, 56 | clk, 57 | address0, 58 | ce0, 59 | q0, 60 | address1, 61 | ce1, 62 | we1, 63 | d1); 64 | 65 | parameter DataWidth = 32'd40; 66 | parameter AddressRange = 32'd256; 67 | parameter AddressWidth = 32'd8; 68 | input reset; 69 | input clk; 70 | input[AddressWidth - 1:0] address0; 71 | input ce0; 72 | output[DataWidth - 1:0] q0; 73 | input[AddressWidth - 1:0] address1; 74 | input ce1; 75 | input we1; 76 | input[DataWidth - 1:0] d1; 77 | 78 | 79 | 80 | odata_p_idata_bufbkb_ram odata_p_idata_bufbkb_ram_U( 81 | .clk( clk ), 82 | .addr0( address0 ), 83 | .ce0( ce0 ), 84 | .q0( q0 ), 85 | .addr1( address1 ), 86 | .ce1( ce1 ), 87 | .we1( we1 ), 88 | .d1( d1 )); 89 | 90 | endmodule 91 | 92 | -------------------------------------------------------------------------------- /test/yuvtest.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include "cam.h" 8 | 9 | #define WIDTH 640 10 | #define HEIGHT 480 11 | 12 | // saturate input into [0, 255] 13 | inline unsigned char sat(float f) 14 | { 15 | return (unsigned char)( f >= 255 ? 255 : (f < 0 ? 0 : f)); 16 | } 17 | 18 | static void yuyv_to_rgb(unsigned char *yuyv, unsigned char *rgb) 19 | { 20 | for (int i = 0; i < WIDTH * HEIGHT * 2; i += 4) { 21 | *rgb++ = sat(yuyv[i]+1.402f *(yuyv[i+3]-128)); 22 | *rgb++ = sat(yuyv[i]-0.34414f*(yuyv[i+1]-128)-0.71414f*(yuyv[i+3]-128)); 23 | *rgb++ = sat(yuyv[i]+1.772f *(yuyv[i+1]-128)); 24 | *rgb++ = sat(yuyv[i+2]+1.402f*(yuyv[i+3]-128)); 25 | *rgb++ = sat(yuyv[i+2]-0.34414f*(yuyv[i+1]-128)-0.71414f*(yuyv[i+3]-128)); 26 | *rgb++ = sat(yuyv[i+2]+1.772f*(yuyv[i+1]-128)); 27 | } 28 | } 29 | 30 | int main() 31 | { 32 | int rc; 33 | int w = WIDTH, h = HEIGHT; 34 | unsigned char *buf; 35 | unsigned char rgb_buf[WIDTH*HEIGHT*3]; 36 | 37 | rc = v4l2init(w, h, V4L2_PIX_FMT_YUYV); 38 | if (rc < 0) { 39 | fprintf(stderr, "v4l2init = %d\n", rc); 40 | return -1; 41 | } 42 | 43 | cv::Mat frame(h, w, CV_8UC3); 44 | for (int i = 0; i < 20; i++) { 45 | printf("frame %d\n", i); 46 | rc = v4l2grab(&buf); 47 | if (rc < 0) { 48 | fprintf(stderr, "v4l2grab = %d\n", rc); 49 | return -1; 50 | } 51 | yuyv_to_rgb(buf, rgb_buf); 52 | frame.data = (unsigned char *)rgb_buf; 53 | std::stringstream ss; 54 | ss << "./" << i << ".png"; 55 | cv::imwrite(ss.str(), frame); 56 | rc = v4l2release(rc); 57 | if (rc < 0) { 58 | fprintf(stderr, "v4l2release = %d\n", rc); 59 | return -1; 60 | } 61 | } 62 | 63 | rc = v4l2end(); 64 | if (rc < 0) { 65 | fprintf(stderr, "v4l2release = %d\n", rc); 66 | return -1; 67 | } 68 | 69 | return 0; 70 | } 71 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/demosaic_root_macfYi.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | library IEEE; 9 | use IEEE.std_logic_1164.all; 10 | use IEEE.numeric_std.all; 11 | 12 | entity demosaic_root_macfYi_DSP48_0 is 13 | port ( 14 | in0: in std_logic_vector(14 - 1 downto 0); 15 | in1: in std_logic_vector(11 - 1 downto 0); 16 | in2: in std_logic_vector(23 - 1 downto 0); 17 | dout: out std_logic_vector(24 - 1 downto 0)); 18 | 19 | end entity; 20 | 21 | architecture behav of demosaic_root_macfYi_DSP48_0 is 22 | signal a : signed(27-1 downto 0); 23 | signal b : signed(18-1 downto 0); 24 | signal c : signed(48-1 downto 0); 25 | signal m : signed(45-1 downto 0); 26 | signal p : signed(48-1 downto 0); 27 | begin 28 | a <= signed(resize(signed(in0), 27)); 29 | b <= signed(resize(unsigned(in1), 18)); 30 | c <= signed(resize(unsigned(in2), 48)); 31 | 32 | m <= a * b; 33 | p <= m + c; 34 | 35 | dout <= std_logic_vector(resize(unsigned(p), 24)); 36 | 37 | end architecture; 38 | 39 | Library IEEE; 40 | use IEEE.std_logic_1164.all; 41 | 42 | entity demosaic_root_macfYi is 43 | generic ( 44 | ID : INTEGER; 45 | NUM_STAGE : INTEGER; 46 | din0_WIDTH : INTEGER; 47 | din1_WIDTH : INTEGER; 48 | din2_WIDTH : INTEGER; 49 | dout_WIDTH : INTEGER); 50 | port ( 51 | din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0); 52 | din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0); 53 | din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0); 54 | dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0)); 55 | end entity; 56 | 57 | architecture arch of demosaic_root_macfYi is 58 | component demosaic_root_macfYi_DSP48_0 is 59 | port ( 60 | in0 : IN STD_LOGIC_VECTOR; 61 | in1 : IN STD_LOGIC_VECTOR; 62 | in2 : IN STD_LOGIC_VECTOR; 63 | dout : OUT STD_LOGIC_VECTOR); 64 | end component; 65 | 66 | 67 | 68 | begin 69 | demosaic_root_macfYi_DSP48_0_U : component demosaic_root_macfYi_DSP48_0 70 | port map ( 71 | in0 => din0, 72 | in1 => din1, 73 | in2 => din2, 74 | dout => dout); 75 | 76 | end architecture; 77 | 78 | 79 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/verilog/fifo_w1_d16_A.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2018.2.2 4 | // Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module fifo_w1_d16_A_shiftReg ( 12 | clk, 13 | data, 14 | ce, 15 | a, 16 | q); 17 | 18 | parameter DATA_WIDTH = 32'd1; 19 | parameter ADDR_WIDTH = 32'd4; 20 | parameter DEPTH = 5'd16; 21 | 22 | input clk; 23 | input [DATA_WIDTH-1:0] data; 24 | input ce; 25 | input [ADDR_WIDTH-1:0] a; 26 | output [DATA_WIDTH-1:0] q; 27 | 28 | reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1]; 29 | integer i; 30 | 31 | always @ (posedge clk) 32 | begin 33 | if (ce) 34 | begin 35 | for (i=0;i 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | #endif 33 | #include "xdemosaic_root_hw.h" 34 | 35 | /**************************** Type Definitions ******************************/ 36 | #ifdef __linux__ 37 | typedef uint8_t u8; 38 | typedef uint16_t u16; 39 | typedef uint32_t u32; 40 | #else 41 | typedef struct { 42 | u16 DeviceId; 43 | u32 Bus_axi4ls_BaseAddress; 44 | } XDemosaic_root_Config; 45 | #endif 46 | 47 | typedef struct { 48 | u32 Bus_axi4ls_BaseAddress; 49 | u32 IsReady; 50 | } XDemosaic_root; 51 | 52 | /***************** Macros (Inline Functions) Definitions *********************/ 53 | #ifndef __linux__ 54 | #define XDemosaic_root_WriteReg(BaseAddress, RegOffset, Data) \ 55 | Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) 56 | #define XDemosaic_root_ReadReg(BaseAddress, RegOffset) \ 57 | Xil_In32((BaseAddress) + (RegOffset)) 58 | #else 59 | #define XDemosaic_root_WriteReg(BaseAddress, RegOffset, Data) \ 60 | *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data) 61 | #define XDemosaic_root_ReadReg(BaseAddress, RegOffset) \ 62 | *(volatile u32*)((BaseAddress) + (RegOffset)) 63 | 64 | #define Xil_AssertVoid(expr) assert(expr) 65 | #define Xil_AssertNonvoid(expr) assert(expr) 66 | 67 | #define XST_SUCCESS 0 68 | #define XST_DEVICE_NOT_FOUND 2 69 | #define XST_OPEN_DEVICE_FAILED 3 70 | #define XIL_COMPONENT_IS_READY 1 71 | #endif 72 | 73 | /************************** Function Prototypes *****************************/ 74 | #ifndef __linux__ 75 | int XDemosaic_root_Initialize(XDemosaic_root *InstancePtr, u16 DeviceId); 76 | XDemosaic_root_Config* XDemosaic_root_LookupConfig(u16 DeviceId); 77 | int XDemosaic_root_CfgInitialize(XDemosaic_root *InstancePtr, XDemosaic_root_Config *ConfigPtr); 78 | #else 79 | int XDemosaic_root_Initialize(XDemosaic_root *InstancePtr, const char* InstanceName); 80 | int XDemosaic_root_Release(XDemosaic_root *InstancePtr); 81 | #endif 82 | 83 | void XDemosaic_root_Start(XDemosaic_root *InstancePtr); 84 | u32 XDemosaic_root_IsDone(XDemosaic_root *InstancePtr); 85 | u32 XDemosaic_root_IsIdle(XDemosaic_root *InstancePtr); 86 | u32 XDemosaic_root_IsReady(XDemosaic_root *InstancePtr); 87 | void XDemosaic_root_EnableAutoRestart(XDemosaic_root *InstancePtr); 88 | void XDemosaic_root_DisableAutoRestart(XDemosaic_root *InstancePtr); 89 | u32 XDemosaic_root_Get_return(XDemosaic_root *InstancePtr); 90 | 91 | 92 | void XDemosaic_root_InterruptGlobalEnable(XDemosaic_root *InstancePtr); 93 | void XDemosaic_root_InterruptGlobalDisable(XDemosaic_root *InstancePtr); 94 | void XDemosaic_root_InterruptEnable(XDemosaic_root *InstancePtr, u32 Mask); 95 | void XDemosaic_root_InterruptDisable(XDemosaic_root *InstancePtr, u32 Mask); 96 | void XDemosaic_root_InterruptClear(XDemosaic_root *InstancePtr, u32 Mask); 97 | u32 XDemosaic_root_InterruptGetEnabled(XDemosaic_root *InstancePtr); 98 | u32 XDemosaic_root_InterruptGetStatus(XDemosaic_root *InstancePtr); 99 | 100 | #ifdef __cplusplus 101 | } 102 | #endif 103 | 104 | #endif 105 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/odata_p_idata_bufbkb.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | -- 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.std_logic_unsigned.all; 12 | 13 | entity odata_p_idata_bufbkb_ram is 14 | generic( 15 | MEM_TYPE : string := "block"; 16 | DWIDTH : integer := 40; 17 | AWIDTH : integer := 8; 18 | MEM_SIZE : integer := 256 19 | ); 20 | port ( 21 | addr0 : in std_logic_vector(AWIDTH-1 downto 0); 22 | ce0 : in std_logic; 23 | q0 : out std_logic_vector(DWIDTH-1 downto 0); 24 | addr1 : in std_logic_vector(AWIDTH-1 downto 0); 25 | ce1 : in std_logic; 26 | d1 : in std_logic_vector(DWIDTH-1 downto 0); 27 | we1 : in std_logic; 28 | clk : in std_logic 29 | ); 30 | end entity; 31 | 32 | 33 | architecture rtl of odata_p_idata_bufbkb_ram is 34 | 35 | signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 36 | type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 37 | shared variable ram : mem_array; 38 | 39 | attribute syn_ramstyle : string; 40 | attribute syn_ramstyle of ram : variable is "block_ram"; 41 | attribute ram_style : string; 42 | attribute ram_style of ram : variable is MEM_TYPE; 43 | 44 | begin 45 | 46 | 47 | memory_access_guard_0: process (addr0) 48 | begin 49 | addr0_tmp <= addr0; 50 | --synthesis translate_off 51 | if (CONV_INTEGER(addr0) > mem_size-1) then 52 | addr0_tmp <= (others => '0'); 53 | else 54 | addr0_tmp <= addr0; 55 | end if; 56 | --synthesis translate_on 57 | end process; 58 | 59 | p_memory_access_0: process (clk) 60 | begin 61 | if (clk'event and clk = '1') then 62 | if (ce0 = '1') then 63 | q0 <= ram(CONV_INTEGER(addr0_tmp)); 64 | end if; 65 | end if; 66 | end process; 67 | 68 | 69 | p_memory_access_1: process (clk) 70 | begin 71 | if (clk'event and clk = '1') then 72 | if (ce1 = '1') then 73 | if (we1 = '1') then 74 | ram(CONV_INTEGER(addr1)) := d1; 75 | end if; 76 | end if; 77 | end if; 78 | end process; 79 | 80 | 81 | end rtl; 82 | 83 | 84 | Library IEEE; 85 | use IEEE.std_logic_1164.all; 86 | 87 | entity odata_p_idata_bufbkb is 88 | generic ( 89 | DataWidth : INTEGER := 40; 90 | AddressRange : INTEGER := 256; 91 | AddressWidth : INTEGER := 8); 92 | port ( 93 | reset : IN STD_LOGIC; 94 | clk : IN STD_LOGIC; 95 | address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); 96 | ce0 : IN STD_LOGIC; 97 | q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); 98 | address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); 99 | ce1 : IN STD_LOGIC; 100 | we1 : IN STD_LOGIC; 101 | d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); 102 | end entity; 103 | 104 | architecture arch of odata_p_idata_bufbkb is 105 | component odata_p_idata_bufbkb_ram is 106 | port ( 107 | clk : IN STD_LOGIC; 108 | addr0 : IN STD_LOGIC_VECTOR; 109 | ce0 : IN STD_LOGIC; 110 | q0 : OUT STD_LOGIC_VECTOR; 111 | addr1 : IN STD_LOGIC_VECTOR; 112 | ce1 : IN STD_LOGIC; 113 | we1 : IN STD_LOGIC; 114 | d1 : IN STD_LOGIC_VECTOR); 115 | end component; 116 | 117 | 118 | 119 | begin 120 | odata_p_idata_bufbkb_ram_U : component odata_p_idata_bufbkb_ram 121 | port map ( 122 | clk => clk, 123 | addr0 => address0, 124 | ce0 => ce0, 125 | q0 => q0, 126 | addr1 => address1, 127 | ce1 => ce1, 128 | we1 => we1, 129 | d1 => d1); 130 | 131 | end architecture; 132 | 133 | 134 | -------------------------------------------------------------------------------- /script/create_project.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # create_project.tcl Tcl script for creating project 3 | # 4 | set project_name "ultra96_design" 5 | set root_directory [file join [file dirname [info script]] ".."] 6 | set project_directory [file join $root_directory $project_name] 7 | set board_part [get_board_parts -quiet -latest_file_version "*ultra96v1*"] 8 | set device_part "xczu3eg-sbva484-1-e" 9 | set design_bd_tcl_file [file normalize [file join $root_directory "script/create_bd.tcl" ]] 10 | set design_pin_xdc_file [file normalize [file join $root_directory "src/constrs/Ultra96_constraints_180318.xdc" ]] 11 | lappend ip_repo_path_list [file join $root_directory "ip"] 12 | 13 | # 14 | # Create project 15 | # 16 | create_project -force $project_name $project_directory 17 | # 18 | # Set project properties 19 | # 20 | if {[info exists board_part ] && [string equal $board_part "" ] == 0} { 21 | set_property "board_part" $board_part [current_project] 22 | } elseif {[info exists device_part] && [string equal $device_part "" ] == 0} { 23 | set_property "part" $device_part [current_project] 24 | } else { 25 | puts "ERROR: Please set board_part or device_part." 26 | return 1 27 | } 28 | set_property "default_lib" "xil_defaultlib" [current_project] 29 | set_property "simulator_language" "Mixed" [current_project] 30 | set_property "target_language" "Verilog" [current_project] 31 | # 32 | # Create fileset "sources_1" 33 | # 34 | if {[string equal [get_filesets -quiet sources_1] ""]} { 35 | create_fileset -srcset sources_1 36 | } 37 | # 38 | # Create fileset "constrs_1" 39 | # 40 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 41 | create_fileset -constrset constrs_1 42 | } 43 | # 44 | # Create fileset "sim_1" 45 | # 46 | if {[string equal [get_filesets -quiet sim_1] ""]} { 47 | create_fileset -simset sim_1 48 | } 49 | # 50 | # Create run "synth_1" and set property 51 | # 52 | set synth_1_flow "Vivado Synthesis 2018" 53 | set synth_1_strategy "Vivado Synthesis Defaults" 54 | if {[string equal [get_runs -quiet synth_1] ""]} { 55 | create_run -name synth_1 -flow $synth_1_flow -strategy $synth_1_strategy -constrset constrs_1 56 | } else { 57 | set_property flow $synth_1_flow [get_runs synth_1] 58 | set_property strategy $synth_1_strategy [get_runs synth_1] 59 | } 60 | current_run -synthesis [get_runs synth_1] 61 | # 62 | # Create run "impl_1" and set property 63 | # 64 | set impl_1_flow "Vivado Implementation 2018" 65 | set impl_1_strategy "Vivado Implementation Defaults" 66 | if {[string equal [get_runs -quiet impl_1] ""]} { 67 | create_run -name impl_1 -flow $impl_1_flow -strategy $impl_1_strategy -constrset constrs_1 -parent_run synth_1 68 | } else { 69 | set_property flow $impl_1_flow [get_runs impl_1] 70 | set_property strategy $impl_1_strategy [get_runs impl_1] 71 | } 72 | current_run -implementation [get_runs impl_1] 73 | # 74 | # Set IP Repository 75 | # 76 | if {[info exists ip_repo_path_list] && [llength $ip_repo_path_list] > 0 } { 77 | set_property ip_repo_paths $ip_repo_path_list [current_fileset] 78 | update_ip_catalog 79 | } 80 | # 81 | # Create block design 82 | # 83 | if {[info exists design_bd_tcl_file]} { 84 | 85 | # 86 | # Set -dir argument value of create_bd_design 87 | # 88 | set ::origin_dir_loc [file join $project_directory $project_name.srcs] 89 | # 90 | # Read block design file 91 | # 92 | source $design_bd_tcl_file 93 | # 94 | # Save block design 95 | # 96 | regenerate_bd_layout 97 | save_bd_design 98 | # 99 | # Generate wrapper files 100 | # 101 | set design_bd_name [get_bd_designs] 102 | make_wrapper -files [get_files $design_bd_name.bd] -top -import 103 | } 104 | # 105 | # Import timing files 106 | # 107 | if {[info exists design_timing_xdc_file]} { 108 | add_files -fileset constrs_1 -norecurse $design_timing_xdc_file 109 | } 110 | # 111 | # Import pin files 112 | # 113 | if {[info exists design_pin_xdc_file]} { 114 | add_files -fileset constrs_1 -norecurse $design_pin_xdc_file 115 | } 116 | -------------------------------------------------------------------------------- /test/cam.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | 12 | #define NUM_BUFFER 2 13 | 14 | static int v4l2_fd; 15 | static void *v4l2_user_frame[NUM_BUFFER]; 16 | 17 | static int xioctl(int fd, int request, void *arg){ 18 | int rc; 19 | 20 | do rc = ioctl(fd, request, arg); 21 | while (-1 == rc && EINTR == errno); 22 | return rc; 23 | } 24 | 25 | int v4l2init(int w, int h, __u32 pixelformat) 26 | { 27 | int rc; 28 | struct v4l2_format fmt; 29 | struct v4l2_requestbuffers req; 30 | struct v4l2_buffer buf; 31 | enum v4l2_buf_type type; 32 | 33 | v4l2_fd = open("/dev/video0", O_RDWR); 34 | if (v4l2_fd < 0) { 35 | fprintf(stderr, "open = %d, errno = %d\n", v4l2_fd, errno); 36 | return -1; 37 | } 38 | 39 | memset(&fmt, 0, sizeof(fmt)); 40 | fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 41 | fmt.fmt.pix.width = w; 42 | fmt.fmt.pix.height = h; 43 | fmt.fmt.pix.pixelformat = pixelformat; 44 | fmt.fmt.pix.field = V4L2_FIELD_ANY; 45 | rc = xioctl(v4l2_fd, VIDIOC_S_FMT, &fmt); 46 | if (rc < 0) { 47 | fprintf(stderr, "VIDIOC_S_FMT: errno = %d\n", errno); 48 | return -1; 49 | } 50 | 51 | memset(&req, 0, sizeof(req)); 52 | req.count = NUM_BUFFER; 53 | req.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 54 | req.memory = V4L2_MEMORY_MMAP; 55 | rc = xioctl(v4l2_fd, VIDIOC_REQBUFS, &req); 56 | if (rc < 0) { 57 | fprintf(stderr, "VIDIOC_REQBUFS: errno = %d\n", errno); 58 | return -1; 59 | } 60 | 61 | memset(&buf, 0, sizeof(buf)); 62 | buf.memory = V4L2_MEMORY_MMAP; 63 | buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 64 | for (int i = 0; i < NUM_BUFFER; i++) { 65 | buf.index = i; 66 | rc = xioctl(v4l2_fd, VIDIOC_QUERYBUF, &buf); 67 | if (rc < 0) { 68 | fprintf(stderr, "VIDIOC_QUERYBUF: errno = %d\n", errno); 69 | return -1; 70 | } 71 | v4l2_user_frame[i] = mmap(NULL, buf.length, PROT_READ | PROT_WRITE, MAP_SHARED, v4l2_fd, buf.m.offset); 72 | if (!v4l2_user_frame[i] || v4l2_user_frame[i] == (void *)-1) { 73 | fprintf(stderr, "mmap: errno = %d\n", errno); 74 | return -1; 75 | } 76 | rc = xioctl(v4l2_fd, VIDIOC_QBUF, &buf); 77 | if (rc < 0) { 78 | fprintf(stderr, "VIDIOC_QBUF: errno = %d\n", errno); 79 | return -1; 80 | } 81 | } 82 | 83 | type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 84 | rc = xioctl(v4l2_fd, VIDIOC_STREAMON, &type); 85 | if (rc < 0) { 86 | fprintf(stderr, "VIDIOC_STREAMON: errno = %d\n", errno); 87 | return -1; 88 | } 89 | 90 | return 0; 91 | } 92 | 93 | int v4l2end(void) 94 | { 95 | int rc; 96 | enum v4l2_buf_type type; 97 | 98 | type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 99 | rc = xioctl(v4l2_fd, VIDIOC_STREAMOFF, &type); 100 | if (rc < 0) { 101 | fprintf(stderr, "VIDIOC_STREAMOFF: errno = %d\n", errno); 102 | return -1; 103 | } 104 | 105 | close(v4l2_fd); 106 | 107 | return 0; 108 | } 109 | 110 | int v4l2grab(unsigned char **frame) 111 | { 112 | int rc; 113 | struct v4l2_buffer buf; 114 | fd_set fds; 115 | struct timeval tv; 116 | 117 | memset(&buf, 0, sizeof(buf)); 118 | buf.memory = V4L2_MEMORY_MMAP; 119 | buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 120 | 121 | FD_ZERO(&fds); 122 | FD_SET(v4l2_fd, &fds); 123 | tv.tv_sec = 2; 124 | tv.tv_usec = 0; 125 | select(v4l2_fd + 1, &fds, NULL, NULL, &tv); 126 | if (FD_ISSET(v4l2_fd, &fds)) { 127 | rc = xioctl(v4l2_fd, VIDIOC_DQBUF, &buf); 128 | if (rc < 0) { 129 | fprintf(stderr, "VIDIOC_DQBUF: errno = %d\n", errno); 130 | return -1; 131 | } 132 | if (buf.index < NUM_BUFFER) { 133 | *frame = (unsigned char *)v4l2_user_frame[buf.index]; 134 | return buf.index; 135 | } else { 136 | fprintf(stderr, "VIDIOC_DQBUF: buf.index = %d\n", errno); 137 | return -1; 138 | } 139 | } else { 140 | fprintf(stderr, "select: errno = %d\n", errno); 141 | return -1; 142 | } 143 | } 144 | 145 | int v4l2release(int buf_idx) 146 | { 147 | int rc; 148 | struct v4l2_buffer buf; 149 | 150 | memset(&buf, 0, sizeof(buf)); 151 | buf.memory = V4L2_MEMORY_MMAP; 152 | buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 153 | 154 | if (buf_idx < NUM_BUFFER) { 155 | buf.index = buf_idx; 156 | rc = xioctl(v4l2_fd, VIDIOC_QBUF, &buf); 157 | if (rc < 0) { 158 | fprintf(stderr, "VIDIOC_QBUF: errno = %d\n", errno); 159 | return -1; 160 | } 161 | } 162 | 163 | return 0; 164 | } 165 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/fifo_w1_d16_A.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity fifo_w1_d16_A_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 4; 17 | DEPTH : integer := 16); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end fifo_w1_d16_A_shiftReg; 25 | 26 | architecture rtl of fifo_w1_d16_A_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity fifo_w1_d16_A is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 4; 55 | DEPTH : integer := 16); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of fifo_w1_d16_A is 70 | 71 | component fifo_w1_d16_A_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 4; 75 | DEPTH : integer := 16); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 5); 108 | if (mOutPtr = conv_std_logic_vector(0, 5)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 5); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 5) - conv_std_logic_vector(2, 5)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_fifo_w1_d16_A_shiftReg : fifo_w1_d16_A_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/verilog/demosaic_root_ureibs.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2018.2.2 4 | // Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | 10 | module demosaic_root_ureibs_div_u 11 | #(parameter 12 | in0_WIDTH = 32, 13 | in1_WIDTH = 32, 14 | out_WIDTH = 32 15 | ) 16 | ( 17 | input clk, 18 | input reset, 19 | input ce, 20 | input [in0_WIDTH-1:0] dividend, 21 | input [in1_WIDTH-1:0] divisor, 22 | output wire [out_WIDTH-1:0] quot, 23 | output wire [out_WIDTH-1:0] remd 24 | ); 25 | 26 | localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH; 27 | 28 | //------------------------Local signal------------------- 29 | reg [in0_WIDTH-1:0] dividend_tmp[0:in0_WIDTH]; 30 | reg [in1_WIDTH-1:0] divisor_tmp[0:in0_WIDTH]; 31 | reg [in0_WIDTH-1:0] remd_tmp[0:in0_WIDTH]; 32 | wire [in0_WIDTH-1:0] comb_tmp[0:in0_WIDTH-1]; 33 | wire [cal_WIDTH:0] cal_tmp[0:in0_WIDTH-1]; 34 | //------------------------Body--------------------------- 35 | assign quot = dividend_tmp[in0_WIDTH]; 36 | assign remd = remd_tmp[in0_WIDTH]; 37 | 38 | // dividend_tmp[0], divisor_tmp[0], remd_tmp[0] 39 | always @(posedge clk) 40 | begin 41 | if (ce) begin 42 | dividend_tmp[0] <= dividend; 43 | divisor_tmp[0] <= divisor; 44 | remd_tmp[0] <= 1'b0; 45 | end 46 | end 47 | 48 | genvar i; 49 | generate 50 | for (i = 0; i < in0_WIDTH; i = i + 1) 51 | begin : loop 52 | if (in0_WIDTH == 1) assign comb_tmp[i] = dividend_tmp[i][0]; 53 | else assign comb_tmp[i] = {remd_tmp[i][in0_WIDTH-2:0], dividend_tmp[i][in0_WIDTH-1]}; 54 | assign cal_tmp[i] = {1'b0, comb_tmp[i]} - {1'b0, divisor_tmp[i]}; 55 | 56 | always @(posedge clk) 57 | begin 58 | if (ce) begin 59 | if (in0_WIDTH == 1) dividend_tmp[i+1] <= ~cal_tmp[i][cal_WIDTH]; 60 | else dividend_tmp[i+1] <= {dividend_tmp[i][in0_WIDTH-2:0], ~cal_tmp[i][cal_WIDTH]}; 61 | divisor_tmp[i+1] <= divisor_tmp[i]; 62 | remd_tmp[i+1] <= cal_tmp[i][cal_WIDTH]? comb_tmp[i] : cal_tmp[i][in0_WIDTH-1:0]; 63 | end 64 | end 65 | end 66 | endgenerate 67 | 68 | endmodule 69 | 70 | module demosaic_root_ureibs_div 71 | #(parameter 72 | in0_WIDTH = 32, 73 | in1_WIDTH = 32, 74 | out_WIDTH = 32 75 | ) 76 | ( 77 | input clk, 78 | input reset, 79 | input ce, 80 | input [in0_WIDTH-1:0] dividend, 81 | input [in1_WIDTH-1:0] divisor, 82 | output reg [out_WIDTH-1:0] quot, 83 | output reg [out_WIDTH-1:0] remd 84 | ); 85 | //------------------------Local signal------------------- 86 | reg [in0_WIDTH-1:0] dividend0; 87 | reg [in1_WIDTH-1:0] divisor0; 88 | wire [in0_WIDTH-1:0] dividend_u; 89 | wire [in1_WIDTH-1:0] divisor_u; 90 | wire [out_WIDTH-1:0] quot_u; 91 | wire [out_WIDTH-1:0] remd_u; 92 | //------------------------Instantiation------------------ 93 | demosaic_root_ureibs_div_u #( 94 | .in0_WIDTH ( in0_WIDTH ), 95 | .in1_WIDTH ( in1_WIDTH ), 96 | .out_WIDTH ( out_WIDTH ) 97 | ) demosaic_root_ureibs_div_u_0 ( 98 | .clk ( clk ), 99 | .reset ( reset ), 100 | .ce ( ce ), 101 | .dividend ( dividend_u ), 102 | .divisor ( divisor_u ), 103 | .quot ( quot_u ), 104 | .remd ( remd_u ) 105 | ); 106 | //------------------------Body--------------------------- 107 | assign dividend_u = dividend0; 108 | assign divisor_u = divisor0; 109 | 110 | always @(posedge clk) 111 | begin 112 | if (ce) begin 113 | dividend0 <= dividend; 114 | divisor0 <= divisor; 115 | end 116 | end 117 | 118 | always @(posedge clk) 119 | begin 120 | if (ce) begin 121 | quot <= quot_u; 122 | remd <= remd_u; 123 | end 124 | end 125 | 126 | endmodule 127 | 128 | 129 | 130 | `timescale 1 ns / 1 ps 131 | module demosaic_root_ureibs( 132 | clk, 133 | reset, 134 | ce, 135 | din0, 136 | din1, 137 | dout); 138 | 139 | parameter ID = 32'd1; 140 | parameter NUM_STAGE = 32'd1; 141 | parameter din0_WIDTH = 32'd1; 142 | parameter din1_WIDTH = 32'd1; 143 | parameter dout_WIDTH = 32'd1; 144 | input clk; 145 | input reset; 146 | input ce; 147 | input[din0_WIDTH - 1:0] din0; 148 | input[din1_WIDTH - 1:0] din1; 149 | output[dout_WIDTH - 1:0] dout; 150 | 151 | wire[dout_WIDTH - 1:0] sig_quot; 152 | 153 | 154 | demosaic_root_ureibs_div #( 155 | .in0_WIDTH( din0_WIDTH ), 156 | .in1_WIDTH( din1_WIDTH ), 157 | .out_WIDTH( dout_WIDTH )) 158 | demosaic_root_ureibs_div_U( 159 | .dividend( din0 ), 160 | .divisor( din1 ), 161 | .remd( dout ), 162 | .quot( sig_quot ), 163 | .clk( clk ), 164 | .ce( ce ), 165 | .reset( reset )); 166 | 167 | endmodule 168 | 169 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/fifo_w24_d16_A.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity fifo_w24_d16_A_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 24; 16 | ADDR_WIDTH : integer := 4; 17 | DEPTH : integer := 16); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end fifo_w24_d16_A_shiftReg; 25 | 26 | architecture rtl of fifo_w24_d16_A_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity fifo_w24_d16_A is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 24; 54 | ADDR_WIDTH : integer := 4; 55 | DEPTH : integer := 16); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of fifo_w24_d16_A is 70 | 71 | component fifo_w24_d16_A_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 24; 74 | ADDR_WIDTH : integer := 4; 75 | DEPTH : integer := 16); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 5); 108 | if (mOutPtr = conv_std_logic_vector(0, 5)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 5); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 5) - conv_std_logic_vector(2, 5)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_fifo_w24_d16_A_shiftReg : fifo_w24_d16_A_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/fifo_w40_d16_A.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity fifo_w40_d16_A_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 40; 16 | ADDR_WIDTH : integer := 4; 17 | DEPTH : integer := 16); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end fifo_w40_d16_A_shiftReg; 25 | 26 | architecture rtl of fifo_w40_d16_A_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity fifo_w40_d16_A is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 40; 54 | ADDR_WIDTH : integer := 4; 55 | DEPTH : integer := 16); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of fifo_w40_d16_A is 70 | 71 | component fifo_w40_d16_A_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 40; 74 | ADDR_WIDTH : integer := 4; 75 | DEPTH : integer := 16); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 5); 108 | if (mOutPtr = conv_std_logic_vector(0, 5)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 5); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 5) - conv_std_logic_vector(2, 5)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_fifo_w40_d16_A_shiftReg : fifo_w40_d16_A_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/fifo_w1_d320_A.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity fifo_w1_d320_A_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 9; 17 | DEPTH : integer := 320); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end fifo_w1_d320_A_shiftReg; 25 | 26 | architecture rtl of fifo_w1_d320_A_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity fifo_w1_d320_A is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 9; 55 | DEPTH : integer := 320); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of fifo_w1_d320_A is 70 | 71 | component fifo_w1_d320_A_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 9; 75 | DEPTH : integer := 320); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 10); 108 | if (mOutPtr = conv_std_logic_vector(0, 10)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 10); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 10) - conv_std_logic_vector(2, 10)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_fifo_w1_d320_A_shiftReg : fifo_w1_d320_A_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/fifo_w1_d640_A.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity fifo_w1_d640_A_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 10; 17 | DEPTH : integer := 640); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end fifo_w1_d640_A_shiftReg; 25 | 26 | architecture rtl of fifo_w1_d640_A_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity fifo_w1_d640_A is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 10; 55 | DEPTH : integer := 640); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of fifo_w1_d640_A is 70 | 71 | component fifo_w1_d640_A_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 10; 75 | DEPTH : integer := 640); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 11); 108 | if (mOutPtr = conv_std_logic_vector(0, 11)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 11); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 11) - conv_std_logic_vector(2, 11)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_fifo_w1_d640_A_shiftReg : fifo_w1_d640_A_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/fifo_w1_d960_A.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity fifo_w1_d960_A_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 10; 17 | DEPTH : integer := 960); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end fifo_w1_d960_A_shiftReg; 25 | 26 | architecture rtl of fifo_w1_d960_A_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity fifo_w1_d960_A is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 10; 55 | DEPTH : integer := 960); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of fifo_w1_d960_A is 70 | 71 | component fifo_w1_d960_A_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 10; 75 | DEPTH : integer := 960); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 11); 108 | if (mOutPtr = conv_std_logic_vector(0, 11)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 11); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 11) - conv_std_logic_vector(2, 11)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_fifo_w1_d960_A_shiftReg : fifo_w1_d960_A_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/start_for_odata_U0.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity start_for_odata_U0_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 1; 17 | DEPTH : integer := 2); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end start_for_odata_U0_shiftReg; 25 | 26 | architecture rtl of start_for_odata_U0_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity start_for_odata_U0 is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 1; 55 | DEPTH : integer := 2); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of start_for_odata_U0 is 70 | 71 | component start_for_odata_U0_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 1; 75 | DEPTH : integer := 2); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2); 108 | if (mOutPtr = conv_std_logic_vector(0, 2)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_start_for_odata_U0_shiftReg : start_for_odata_U0_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/start_for_olast_U0.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity start_for_olast_U0_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 1; 17 | DEPTH : integer := 2); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end start_for_olast_U0_shiftReg; 25 | 26 | architecture rtl of start_for_olast_U0_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity start_for_olast_U0 is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 1; 55 | DEPTH : integer := 2); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of start_for_olast_U0 is 70 | 71 | component start_for_olast_U0_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 1; 75 | DEPTH : integer := 2); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2); 108 | if (mOutPtr = conv_std_logic_vector(0, 2)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_start_for_olast_U0_shiftReg : start_for_olast_U0_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/start_for_ouser_U0.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity start_for_ouser_U0_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 1; 17 | DEPTH : integer := 2); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end start_for_ouser_U0_shiftReg; 25 | 26 | architecture rtl of start_for_ouser_U0_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity start_for_ouser_U0 is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 1; 55 | DEPTH : integer := 2); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of start_for_ouser_U0 is 70 | 71 | component start_for_ouser_U0_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 1; 75 | DEPTH : integer := 2); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2); 108 | if (mOutPtr = conv_std_logic_vector(0, 2)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_start_for_ouser_U0_shiftReg : start_for_ouser_U0_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/start_for_Loop_2_dEe.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity start_for_Loop_2_dEe_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 1; 17 | DEPTH : integer := 2); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end start_for_Loop_2_dEe_shiftReg; 25 | 26 | architecture rtl of start_for_Loop_2_dEe_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity start_for_Loop_2_dEe is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 1; 55 | DEPTH : integer := 2); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of start_for_Loop_2_dEe is 70 | 71 | component start_for_Loop_2_dEe_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 1; 75 | DEPTH : integer := 2); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2); 108 | if (mOutPtr = conv_std_logic_vector(0, 2)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_start_for_Loop_2_dEe_shiftReg : start_for_Loop_2_dEe_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/start_for_Loop_2_kbM.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity start_for_Loop_2_kbM_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 2; 17 | DEPTH : integer := 3); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end start_for_Loop_2_kbM_shiftReg; 25 | 26 | architecture rtl of start_for_Loop_2_kbM_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity start_for_Loop_2_kbM is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 2; 55 | DEPTH : integer := 3); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of start_for_Loop_2_kbM is 70 | 71 | component start_for_Loop_2_kbM_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 2; 75 | DEPTH : integer := 3); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3); 108 | if (mOutPtr = conv_std_logic_vector(0, 3)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_start_for_Loop_2_kbM_shiftReg : start_for_Loop_2_kbM_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/start_for_Loop_2_qcK.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity start_for_Loop_2_qcK_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 2; 17 | DEPTH : integer := 3); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end start_for_Loop_2_qcK_shiftReg; 25 | 26 | architecture rtl of start_for_Loop_2_qcK_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity start_for_Loop_2_qcK is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 2; 55 | DEPTH : integer := 3); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of start_for_Loop_2_qcK is 70 | 71 | component start_for_Loop_2_qcK_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 2; 75 | DEPTH : integer := 3); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3); 108 | if (mOutPtr = conv_std_logic_vector(0, 3)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_start_for_Loop_2_qcK_shiftReg : start_for_Loop_2_qcK_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/start_for_demosaijbC.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity start_for_demosaijbC_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 1; 17 | DEPTH : integer := 2); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end start_for_demosaijbC_shiftReg; 25 | 26 | architecture rtl of start_for_demosaijbC_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity start_for_demosaijbC is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 1; 55 | DEPTH : integer := 2); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of start_for_demosaijbC is 70 | 71 | component start_for_demosaijbC_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 1; 75 | DEPTH : integer := 2); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2); 108 | if (mOutPtr = conv_std_logic_vector(0, 2)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_start_for_demosaijbC_shiftReg : start_for_demosaijbC_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/hdl/vhdl/start_for_demosaipcA.vhd: -------------------------------------------------------------------------------- 1 | -- ============================================================== 2 | -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | -- Version: 2018.2.2 4 | -- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | -- 6 | -- ============================================================== 7 | 8 | 9 | library IEEE; 10 | use IEEE.std_logic_1164.all; 11 | use IEEE.std_logic_unsigned.all; 12 | 13 | entity start_for_demosaipcA_shiftReg is 14 | generic ( 15 | DATA_WIDTH : integer := 1; 16 | ADDR_WIDTH : integer := 1; 17 | DEPTH : integer := 2); 18 | port ( 19 | clk : in std_logic; 20 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 21 | ce : in std_logic; 22 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 23 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 24 | end start_for_demosaipcA_shiftReg; 25 | 26 | architecture rtl of start_for_demosaipcA_shiftReg is 27 | --constant DEPTH_WIDTH: integer := 16; 28 | type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); 29 | signal SRL_SIG : SRL_ARRAY; 30 | 31 | begin 32 | p_shift: process (clk) 33 | begin 34 | if (clk'event and clk = '1') then 35 | if (ce = '1') then 36 | SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); 37 | end if; 38 | end if; 39 | end process; 40 | 41 | q <= SRL_SIG(conv_integer(a)); 42 | 43 | end rtl; 44 | 45 | library ieee; 46 | use ieee.std_logic_1164.all; 47 | use ieee.std_logic_unsigned.all; 48 | use ieee.std_logic_arith.all; 49 | 50 | entity start_for_demosaipcA is 51 | generic ( 52 | MEM_STYLE : string := "shiftreg"; 53 | DATA_WIDTH : integer := 1; 54 | ADDR_WIDTH : integer := 1; 55 | DEPTH : integer := 2); 56 | port ( 57 | clk : IN STD_LOGIC; 58 | reset : IN STD_LOGIC; 59 | if_empty_n : OUT STD_LOGIC; 60 | if_read_ce : IN STD_LOGIC; 61 | if_read : IN STD_LOGIC; 62 | if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 63 | if_full_n : OUT STD_LOGIC; 64 | if_write_ce : IN STD_LOGIC; 65 | if_write : IN STD_LOGIC; 66 | if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); 67 | end entity; 68 | 69 | architecture rtl of start_for_demosaipcA is 70 | 71 | component start_for_demosaipcA_shiftReg is 72 | generic ( 73 | DATA_WIDTH : integer := 1; 74 | ADDR_WIDTH : integer := 1; 75 | DEPTH : integer := 2); 76 | port ( 77 | clk : in std_logic; 78 | data : in std_logic_vector(DATA_WIDTH-1 downto 0); 79 | ce : in std_logic; 80 | a : in std_logic_vector(ADDR_WIDTH-1 downto 0); 81 | q : out std_logic_vector(DATA_WIDTH-1 downto 0)); 82 | end component; 83 | 84 | signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); 85 | signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 86 | signal shiftReg_ce : STD_LOGIC; 87 | signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); 88 | signal internal_empty_n : STD_LOGIC := '0'; 89 | signal internal_full_n : STD_LOGIC := '1'; 90 | 91 | begin 92 | if_empty_n <= internal_empty_n; 93 | if_full_n <= internal_full_n; 94 | shiftReg_data <= if_din; 95 | if_dout <= shiftReg_q; 96 | 97 | process (clk) 98 | begin 99 | if clk'event and clk = '1' then 100 | if reset = '1' then 101 | mOutPtr <= (others => '1'); 102 | internal_empty_n <= '0'; 103 | internal_full_n <= '1'; 104 | else 105 | if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and 106 | ((if_write and if_write_ce) = '0' or internal_full_n = '0') then 107 | mOutPtr <= mOutPtr - conv_std_logic_vector(1, 2); 108 | if (mOutPtr = conv_std_logic_vector(0, 2)) then 109 | internal_empty_n <= '0'; 110 | end if; 111 | internal_full_n <= '1'; 112 | elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and 113 | ((if_write and if_write_ce) = '1' and internal_full_n = '1') then 114 | mOutPtr <= mOutPtr + conv_std_logic_vector(1, 2); 115 | internal_empty_n <= '1'; 116 | if (mOutPtr = conv_std_logic_vector(DEPTH, 2) - conv_std_logic_vector(2, 2)) then 117 | internal_full_n <= '0'; 118 | end if; 119 | end if; 120 | end if; 121 | end if; 122 | end process; 123 | 124 | shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); 125 | shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; 126 | 127 | U_start_for_demosaipcA_shiftReg : start_for_demosaipcA_shiftReg 128 | generic map ( 129 | DATA_WIDTH => DATA_WIDTH, 130 | ADDR_WIDTH => ADDR_WIDTH, 131 | DEPTH => DEPTH) 132 | port map ( 133 | clk => clk, 134 | data => shiftReg_data, 135 | ce => shiftReg_ce, 136 | a => shiftReg_addr, 137 | q => shiftReg_q); 138 | 139 | end rtl; 140 | 141 | -------------------------------------------------------------------------------- /ip/demosaic/drivers/demosaic_root_v1_0/src/xdemosaic_root_linux.c: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2018.2.2 4 | // Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | #ifdef __linux__ 9 | 10 | /***************************** Include Files *********************************/ 11 | #include "xdemosaic_root.h" 12 | 13 | /***************** Macros (Inline Functions) Definitions *********************/ 14 | #define MAX_UIO_PATH_SIZE 256 15 | #define MAX_UIO_NAME_SIZE 64 16 | #define MAX_UIO_MAPS 5 17 | #define UIO_INVALID_ADDR 0 18 | 19 | /**************************** Type Definitions ******************************/ 20 | typedef struct { 21 | u32 addr; 22 | u32 size; 23 | } XDemosaic_root_uio_map; 24 | 25 | typedef struct { 26 | int uio_fd; 27 | int uio_num; 28 | char name[ MAX_UIO_NAME_SIZE ]; 29 | char version[ MAX_UIO_NAME_SIZE ]; 30 | XDemosaic_root_uio_map maps[ MAX_UIO_MAPS ]; 31 | } XDemosaic_root_uio_info; 32 | 33 | /***************** Variable Definitions **************************************/ 34 | static XDemosaic_root_uio_info uio_info; 35 | 36 | /************************** Function Implementation *************************/ 37 | static int line_from_file(char* filename, char* linebuf) { 38 | char* s; 39 | int i; 40 | FILE* fp = fopen(filename, "r"); 41 | if (!fp) return -1; 42 | s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp); 43 | fclose(fp); 44 | if (!s) return -2; 45 | for (i=0; (*s)&&(iuio_num); 55 | return line_from_file(file, info->name); 56 | } 57 | 58 | static int uio_info_read_version(XDemosaic_root_uio_info* info) { 59 | char file[ MAX_UIO_PATH_SIZE ]; 60 | sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num); 61 | return line_from_file(file, info->version); 62 | } 63 | 64 | static int uio_info_read_map_addr(XDemosaic_root_uio_info* info, int n) { 65 | int ret; 66 | char file[ MAX_UIO_PATH_SIZE ]; 67 | info->maps[n].addr = UIO_INVALID_ADDR; 68 | sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n); 69 | FILE* fp = fopen(file, "r"); 70 | if (!fp) return -1; 71 | ret = fscanf(fp, "0x%x", &info->maps[n].addr); 72 | fclose(fp); 73 | if (ret < 0) return -2; 74 | return 0; 75 | } 76 | 77 | static int uio_info_read_map_size(XDemosaic_root_uio_info* info, int n) { 78 | int ret; 79 | char file[ MAX_UIO_PATH_SIZE ]; 80 | sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n); 81 | FILE* fp = fopen(file, "r"); 82 | if (!fp) return -1; 83 | ret = fscanf(fp, "0x%x", &info->maps[n].size); 84 | fclose(fp); 85 | if (ret < 0) return -2; 86 | return 0; 87 | } 88 | 89 | int XDemosaic_root_Initialize(XDemosaic_root *InstancePtr, const char* InstanceName) { 90 | XDemosaic_root_uio_info *InfoPtr = &uio_info; 91 | struct dirent **namelist; 92 | int i, n; 93 | char* s; 94 | char file[ MAX_UIO_PATH_SIZE ]; 95 | char name[ MAX_UIO_NAME_SIZE ]; 96 | int flag = 0; 97 | 98 | assert(InstancePtr != NULL); 99 | 100 | n = scandir("/sys/class/uio", &namelist, 0, alphasort); 101 | if (n < 0) return XST_DEVICE_NOT_FOUND; 102 | for (i = 0; i < n; i++) { 103 | strcpy(file, "/sys/class/uio/"); 104 | strcat(file, namelist[i]->d_name); 105 | strcat(file, "/name"); 106 | if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) { 107 | flag = 1; 108 | s = namelist[i]->d_name; 109 | s += 3; // "uio" 110 | InfoPtr->uio_num = atoi(s); 111 | break; 112 | } 113 | } 114 | if (flag == 0) return XST_DEVICE_NOT_FOUND; 115 | 116 | uio_info_read_name(InfoPtr); 117 | uio_info_read_version(InfoPtr); 118 | for (n = 0; n < MAX_UIO_MAPS; ++n) { 119 | uio_info_read_map_addr(InfoPtr, n); 120 | uio_info_read_map_size(InfoPtr, n); 121 | } 122 | 123 | sprintf(file, "/dev/uio%d", InfoPtr->uio_num); 124 | if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) { 125 | return XST_OPEN_DEVICE_FAILED; 126 | } 127 | 128 | // NOTE: slave interface 'Bus_axi4ls' should be mapped to uioX/map0 129 | InstancePtr->Bus_axi4ls_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize()); 130 | assert(InstancePtr->Bus_axi4ls_BaseAddress); 131 | 132 | InstancePtr->IsReady = XIL_COMPONENT_IS_READY; 133 | 134 | return XST_SUCCESS; 135 | } 136 | 137 | int XDemosaic_root_Release(XDemosaic_root *InstancePtr) { 138 | XDemosaic_root_uio_info *InfoPtr = &uio_info; 139 | 140 | assert(InstancePtr != NULL); 141 | assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 142 | 143 | munmap((void*)InstancePtr->Bus_axi4ls_BaseAddress, InfoPtr->maps[0].size); 144 | 145 | close(InfoPtr->uio_fd); 146 | 147 | return XST_SUCCESS; 148 | } 149 | 150 | #endif 151 | -------------------------------------------------------------------------------- /ip/demosaic/drivers/demosaic_root_v1_0/src/xdemosaic_root.c: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2018.2.2 4 | // Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | /***************************** Include Files *********************************/ 9 | #include "xdemosaic_root.h" 10 | 11 | /************************** Function Implementation *************************/ 12 | #ifndef __linux__ 13 | int XDemosaic_root_CfgInitialize(XDemosaic_root *InstancePtr, XDemosaic_root_Config *ConfigPtr) { 14 | Xil_AssertNonvoid(InstancePtr != NULL); 15 | Xil_AssertNonvoid(ConfigPtr != NULL); 16 | 17 | InstancePtr->Bus_axi4ls_BaseAddress = ConfigPtr->Bus_axi4ls_BaseAddress; 18 | InstancePtr->IsReady = XIL_COMPONENT_IS_READY; 19 | 20 | return XST_SUCCESS; 21 | } 22 | #endif 23 | 24 | void XDemosaic_root_Start(XDemosaic_root *InstancePtr) { 25 | u32 Data; 26 | 27 | Xil_AssertVoid(InstancePtr != NULL); 28 | Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 29 | 30 | Data = XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_CTRL) & 0x80; 31 | XDemosaic_root_WriteReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_CTRL, Data | 0x01); 32 | } 33 | 34 | u32 XDemosaic_root_IsDone(XDemosaic_root *InstancePtr) { 35 | u32 Data; 36 | 37 | Xil_AssertNonvoid(InstancePtr != NULL); 38 | Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 39 | 40 | Data = XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_CTRL); 41 | return (Data >> 1) & 0x1; 42 | } 43 | 44 | u32 XDemosaic_root_IsIdle(XDemosaic_root *InstancePtr) { 45 | u32 Data; 46 | 47 | Xil_AssertNonvoid(InstancePtr != NULL); 48 | Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 49 | 50 | Data = XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_CTRL); 51 | return (Data >> 2) & 0x1; 52 | } 53 | 54 | u32 XDemosaic_root_IsReady(XDemosaic_root *InstancePtr) { 55 | u32 Data; 56 | 57 | Xil_AssertNonvoid(InstancePtr != NULL); 58 | Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 59 | 60 | Data = XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_CTRL); 61 | // check ap_start to see if the pcore is ready for next input 62 | return !(Data & 0x1); 63 | } 64 | 65 | void XDemosaic_root_EnableAutoRestart(XDemosaic_root *InstancePtr) { 66 | Xil_AssertVoid(InstancePtr != NULL); 67 | Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 68 | 69 | XDemosaic_root_WriteReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_CTRL, 0x80); 70 | } 71 | 72 | void XDemosaic_root_DisableAutoRestart(XDemosaic_root *InstancePtr) { 73 | Xil_AssertVoid(InstancePtr != NULL); 74 | Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 75 | 76 | XDemosaic_root_WriteReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_CTRL, 0); 77 | } 78 | 79 | u32 XDemosaic_root_Get_return(XDemosaic_root *InstancePtr) { 80 | u32 Data; 81 | 82 | Xil_AssertNonvoid(InstancePtr != NULL); 83 | Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 84 | 85 | Data = XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_AP_RETURN); 86 | return Data; 87 | } 88 | void XDemosaic_root_InterruptGlobalEnable(XDemosaic_root *InstancePtr) { 89 | Xil_AssertVoid(InstancePtr != NULL); 90 | Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 91 | 92 | XDemosaic_root_WriteReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_GIE, 1); 93 | } 94 | 95 | void XDemosaic_root_InterruptGlobalDisable(XDemosaic_root *InstancePtr) { 96 | Xil_AssertVoid(InstancePtr != NULL); 97 | Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 98 | 99 | XDemosaic_root_WriteReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_GIE, 0); 100 | } 101 | 102 | void XDemosaic_root_InterruptEnable(XDemosaic_root *InstancePtr, u32 Mask) { 103 | u32 Register; 104 | 105 | Xil_AssertVoid(InstancePtr != NULL); 106 | Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 107 | 108 | Register = XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_IER); 109 | XDemosaic_root_WriteReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_IER, Register | Mask); 110 | } 111 | 112 | void XDemosaic_root_InterruptDisable(XDemosaic_root *InstancePtr, u32 Mask) { 113 | u32 Register; 114 | 115 | Xil_AssertVoid(InstancePtr != NULL); 116 | Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 117 | 118 | Register = XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_IER); 119 | XDemosaic_root_WriteReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_IER, Register & (~Mask)); 120 | } 121 | 122 | void XDemosaic_root_InterruptClear(XDemosaic_root *InstancePtr, u32 Mask) { 123 | Xil_AssertVoid(InstancePtr != NULL); 124 | Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 125 | 126 | XDemosaic_root_WriteReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_ISR, Mask); 127 | } 128 | 129 | u32 XDemosaic_root_InterruptGetEnabled(XDemosaic_root *InstancePtr) { 130 | Xil_AssertNonvoid(InstancePtr != NULL); 131 | Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 132 | 133 | return XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_IER); 134 | } 135 | 136 | u32 XDemosaic_root_InterruptGetStatus(XDemosaic_root *InstancePtr) { 137 | Xil_AssertNonvoid(InstancePtr != NULL); 138 | Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); 139 | 140 | return XDemosaic_root_ReadReg(InstancePtr->Bus_axi4ls_BaseAddress, XDEMOSAIC_ROOT_BUS_AXI4LS_ADDR_ISR); 141 | } 142 | 143 | -------------------------------------------------------------------------------- /src/linux/caminit/src/imx219.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include "caminit.h" 9 | #include "camcfg.h" 10 | 11 | static config_t cfg_imx219_init_1920_1080_30[] = 12 | { 13 | {0x0100, 0x00}, 14 | {0x0103, 0x01}, 15 | {0x30EB, 0x05}, 16 | {0x30EB, 0x0C}, 17 | {0x300A, 0xFF}, 18 | {0x300B, 0xFF}, 19 | {0x30EB, 0x05}, 20 | {0x30EB, 0x09}, 21 | //{0x0114, 0x03}, 22 | {0x0114, 0x01}, // CSI_LANE_MODE changed from 3 to 1 23 | {0x0128, 0x00}, 24 | {0x012A, 0x18}, 25 | {0x012B, 0x00}, 26 | {0x0160, ((0x48e >> 8) & 0xFF)}, 27 | {0x0161, (0x48e & 0xFF)}, 28 | {0x0162, ((0xD78 >> 8) & 0xFF)}, 29 | {0x0163, (0xD78 & 0xFF)}, 30 | {0x0164, 0x02}, 31 | {0x0165, 0xA8}, 32 | {0x0166, 0x0A}, 33 | {0x0167, 0x27}, 34 | {0x0168, 0x02}, 35 | {0x0169, 0xB4}, 36 | {0x016A, 0x06}, 37 | {0x016B, 0xEB}, 38 | {0x016C, 0x07}, 39 | {0x016D, 0x80}, 40 | {0x016E, 0x04}, 41 | {0x016F, 0x38}, 42 | {0x0170, 0x01}, 43 | {0x0171, 0x01}, 44 | 45 | {0x0172, 0x03}, // added to correct color 46 | 47 | {0x0174, 0x00}, 48 | {0x0175, 0x00}, 49 | {0x018C, 0x0A}, 50 | {0x018D, 0x0A}, 51 | //{0x0301, 0x05}, 52 | {0x0301, 0x0A}, // VTPXCK_DIV changed from 0x05 to 0x0A 53 | {0x0303, 0x01}, 54 | {0x0304, 0x03}, 55 | {0x0305, 0x03}, 56 | {0x0306, 0x00}, 57 | {0x0307, 0x57}, //0x51 58 | {0x0309, 0x0A}, 59 | {0x030B, 0x01}, 60 | {0x030C, 0x00}, 61 | {0x030D, 0x5A}, //0x54 62 | {0x455E, 0x00}, 63 | {0x471E, 0x4B}, 64 | {0x4767, 0x0F}, 65 | {0x4750, 0x14}, 66 | {0x4540, 0x00}, 67 | {0x47B4, 0x14}, 68 | {0x4713, 0x30}, 69 | {0x478B, 0x10}, 70 | {0x478F, 0x10}, 71 | {0x4793, 0x10}, 72 | {0x4797, 0x0E}, 73 | {0x479B, 0x0E}, 74 | {0x0100, 0x01} 75 | }; 76 | 77 | static config_t cfg_imx219_init_1280_720_30[] = 78 | { 79 | {0x0100, 0x00}, 80 | /* software reset */ 81 | {0x0103, 0x01}, 82 | /* global settings */ 83 | {0x30EB, 0x05}, 84 | {0x30EB, 0x0C}, 85 | {0x300A, 0xFF}, 86 | {0x300B, 0xFF}, 87 | {0x30EB, 0x05}, 88 | {0x30EB, 0x09}, 89 | //{0x0114, 0x03}, 90 | {0x0114, 0x01}, // CSI_LANE_MODE changed from 3 to 1 91 | {0x0128, 0x00}, 92 | {0x012A, 0x18}, 93 | {0x012B, 0x00}, 94 | /* Bank A Settings */ 95 | {0x0160, 0x02}, 96 | {0x0161, 0x8C}, 97 | {0x0162, 0x0D}, 98 | {0x0163, 0xE8}, 99 | {0x0164, 0x01}, 100 | {0x0165, 0x68}, 101 | {0x0166, 0x0B}, 102 | {0x0167, 0x67}, 103 | {0x0168, 0x02}, 104 | {0x0169, 0x00}, 105 | {0x016A, 0x07}, 106 | {0x016B, 0x9F}, 107 | {0x016C, 0x05}, 108 | {0x016D, 0x00}, 109 | {0x016E, 0x02}, 110 | {0x016F, 0xD0}, 111 | {0x0170, 0x01}, 112 | {0x0171, 0x01}, 113 | 114 | {0x0172, 0x03}, // added to correct color 115 | 116 | {0x0174, 0x03}, 117 | {0x0175, 0x03}, 118 | {0x018C, 0x0A}, 119 | {0x018D, 0x0A}, 120 | /* clock setting */ 121 | //{0x0301, 0x05}, 122 | {0x0301, 0x0A}, // VTPXCK_DIV changed from 0x05 to 0x0A 123 | {0x0303, 0x01}, 124 | {0x0304, 0x03}, 125 | {0x0305, 0x03}, 126 | {0x0306, 0x00}, 127 | {0x0307, 0x57}, 128 | {0x0309, 0x0A}, 129 | {0x030B, 0x01}, 130 | {0x030C, 0x00}, 131 | {0x030D, 0x5A}, 132 | {0x455E, 0x00}, 133 | {0x471E, 0x4B}, 134 | {0x4767, 0x0F}, 135 | {0x4750, 0x14}, 136 | {0x4540, 0x00}, 137 | {0x47B4, 0x14}, 138 | {0x4713, 0x30}, 139 | {0x478B, 0x10}, 140 | {0x478F, 0x10}, 141 | {0x4793, 0x10}, 142 | {0x4797, 0x0E}, 143 | {0x479B, 0x0E}, 144 | /* stream on */ 145 | {0x0100, 0x01} 146 | }; 147 | 148 | static config_t cfg_imx219_init_640_480_30[] = 149 | { 150 | {0x0100, 0x00}, 151 | {0x0103, 0x01}, 152 | {0x30EB, 0x05}, 153 | {0x30EB, 0x0C}, 154 | {0x300A, 0xFF}, 155 | {0x300B, 0xFF}, 156 | {0x30EB, 0x05}, 157 | {0x30EB, 0x09}, 158 | //{0x0114, 0x03}, 159 | {0x0114, 0x01}, // CSI_LANE_MODE changed from 3 to 1 160 | {0x0128, 0x00}, 161 | {0x012A, 0x18}, 162 | {0x012B, 0x00}, 163 | {0x0160, 0x0A}, 164 | {0x0161, 0x2F}, 165 | {0x0162, 0x0D}, 166 | {0x0163, 0xE8}, 167 | {0x0164, 0x03}, 168 | {0x0165, 0xE8}, 169 | /* X_ADD_END_A */ 170 | {0x0166, 0x0D}, 171 | {0x0167, 0xE7}, 172 | /* Y_ADD_STA_A and Y_ADD_END_A */ 173 | {0x0168, 0x01}, 174 | {0x0169, 0xF0}, 175 | {0x016A, 0x09}, 176 | {0x016B, 0x6F}, 177 | /* x_output_size and y_output_size */ 178 | {0x016C, 0x02}, 179 | {0x016D, 0x80}, 180 | {0x016E, 0x01}, 181 | {0x016F, 0xE0}, 182 | {0x0170, 0x01}, 183 | {0x0171, 0x01}, 184 | 185 | {0x0172, 0x03}, // added to correct color 186 | 187 | {0x0174, 0x02}, /* binning mode x4 */ 188 | {0x0175, 0x02}, 189 | {0x018C, 0x0A}, 190 | {0x018D, 0x0A}, 191 | 192 | {0x0301, 0x05}, 193 | //{0x0301, 0x0A}, // VTPXCK_DIV changed from 0x05 to 0x0A 194 | {0x0303, 0x01}, 195 | {0x0304, 0x02}, 196 | {0x0305, 0x02}, 197 | {0x0306, 0x00}, 198 | {0x0307, 0x57}, //0x51 199 | {0x0309, 0x0A}, 200 | {0x030B, 0x01}, 201 | {0x030C, 0x00}, 202 | {0x030D, 0x5A}, //0x54 203 | {0x455E, 0x00}, 204 | {0x471E, 0x4B}, 205 | {0x4767, 0x0F}, 206 | {0x4750, 0x14}, 207 | {0x4540, 0x00}, 208 | {0x47B4, 0x14}, 209 | {0x4713, 0x30}, 210 | {0x478B, 0x10}, 211 | {0x478F, 0x10}, 212 | {0x4793, 0x10}, 213 | {0x4797, 0x0E}, 214 | {0x479B, 0x0E}, 215 | {0x0100, 0x01} 216 | }; 217 | 218 | int init_imx219(e_resolution resolution) 219 | { 220 | int fd = open("/dev/i2c-4", O_RDWR); 221 | unsigned short addr = 0x00; 222 | unsigned char dat0 = 0x5a, dat1 = 0xa5; 223 | 224 | if (fd < 0) { 225 | perror("open(/dev/i2c-4)"); 226 | return -1; 227 | } 228 | ioctl(fd, I2C_SLAVE, (0x21 >> 1)); 229 | 230 | write(fd, &addr, 2); 231 | read(fd, &dat0, 1); 232 | addr = 0x0100; 233 | write(fd, &addr, 2); 234 | read(fd, &dat1, 1); 235 | 236 | printf("ID = 0x%x, 0x%x\n", dat0, dat1); 237 | 238 | /* go to SW standby and wait EOF to pass through */ 239 | write_reg(fd, 0x0100, 0x00); 240 | usleep(500*1000); 241 | 242 | config_t *cfg; 243 | int num_cmds; 244 | switch (resolution) { 245 | case RESOLUTION_640_480: 246 | case RESOLUTION_320_240: 247 | case RESOLUTION_320_200: 248 | cfg = cfg_imx219_init_640_480_30; 249 | num_cmds = sizeof(cfg_imx219_init_640_480_30) / sizeof(cfg_imx219_init_640_480_30[0]); 250 | break; 251 | case RESOLUTION_1280_720: 252 | case RESOLUTION_640_360: 253 | cfg = cfg_imx219_init_1280_720_30; 254 | num_cmds = sizeof(cfg_imx219_init_1280_720_30) / sizeof(cfg_imx219_init_1280_720_30[0]); 255 | break; 256 | case RESOLUTION_1920_1080: 257 | case RESOLUTION_960_540: 258 | cfg = cfg_imx219_init_1920_1080_30; 259 | num_cmds = sizeof(cfg_imx219_init_1920_1080_30) / sizeof(cfg_imx219_init_1920_1080_30[0]); 260 | break; 261 | default: 262 | break; 263 | } 264 | 265 | for (int i = 0; i < num_cmds; i++) { 266 | write_reg(fd, cfg[i].addr, cfg[i].val); 267 | } 268 | 269 | int gain = 4; 270 | addr = 0x157; 271 | dat0 = 256 - 256 / gain; 272 | write_reg(fd, addr, dat0); 273 | 274 | close(fd); 275 | 276 | return 0; 277 | } 278 | -------------------------------------------------------------------------------- /test/camera_umd/uvc_camera/include/uvc_cam/uvc_cam.h: -------------------------------------------------------------------------------- 1 | // The uvc_cam package provides a simple interface to webcams visible through 2 | // the uvcvideo driver. It includes code adapted from 'guvcview', which in 3 | // turn adapted some code from 'luvcview'. 4 | // Copyright (C) 2009 Morgan Quigley 5 | // 6 | // This program is free software; you can redistribute it and/or 7 | // modify it under the terms of the GNU General Public License 8 | // as published by the Free Software Foundation; either version 2 9 | // of the License, or (at your option) any later version. 10 | 11 | // This program is distributed in the hope that it will be useful, 12 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | // GNU General Public License for more details. 15 | 16 | // You should have received a copy of the GNU General Public License 17 | // along with this program; if not, write to the Free Software 18 | // Foundation, Inc., 19 | // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20 | //////////////////////////////////////////////////////////////////////////// 21 | 22 | #ifndef UVC_CAM_H 23 | #define UVC_CAM_H 24 | 25 | #include 26 | //#include 27 | #include 28 | 29 | #include 30 | 31 | namespace uvc_cam 32 | { 33 | 34 | enum v4l2_uvc_exposure_auto_type 35 | { 36 | V4L2_UVC_EXPOSURE_MANUAL = 1, 37 | V4L2_UVC_EXPOSURE_AUTO = 2, 38 | V4L2_UVC_EXPOSURE_SHUTTER_PRIORITY = 4, 39 | V4L2_UVC_EXPOSURE_APERTURE_PRIORITY = 8 40 | }; 41 | 42 | 43 | static const int exp_vals[]= 44 | { 45 | V4L2_UVC_EXPOSURE_MANUAL, 46 | V4L2_UVC_EXPOSURE_AUTO, 47 | V4L2_UVC_EXPOSURE_SHUTTER_PRIORITY, 48 | V4L2_UVC_EXPOSURE_APERTURE_PRIORITY 49 | }; 50 | 51 | 52 | 53 | #define CSU32 const static uint32_t 54 | 55 | class Cam 56 | { 57 | public: 58 | enum mode_t { MODE_RGB, MODE_MJPG, MODE_YUYV } mode; 59 | Cam(const char *device, mode_t _mode = MODE_RGB, 60 | int _width = 640, int _height = 480, int _fps = 30); 61 | ~Cam(); 62 | static void enumerate(); 63 | int grab(unsigned char **frame, uint32_t &bytes_used); 64 | void release(unsigned buf_idx); 65 | bool set_auto_white_balance(bool on); 66 | void set_motion_thresholds(int lum, int count); 67 | void set_control(uint32_t id, int val); 68 | bool v4l2_query(int id, const std::string& name); 69 | bool set_v4l2_control(int id, int value, const std::string& name); 70 | private: 71 | std::string device; 72 | int fd, motion_threshold_luminance, motion_threshold_count; 73 | unsigned width, height, fps; 74 | v4l2_format fmt; 75 | v4l2_capability cap; 76 | v4l2_streamparm streamparm; 77 | v4l2_requestbuffers rb; 78 | v4l2_buffer buf; 79 | v4l2_timecode timecode; 80 | static const unsigned NUM_BUFFER = 2; 81 | void *mem[NUM_BUFFER]; 82 | unsigned buf_length; 83 | unsigned char *rgb_frame, *last_yuv_frame; 84 | 85 | /*------------------------- new camera class controls ---------------------*/ 86 | CSU32 V4L2_CTRL_CLASS_USER_NEW = 0x00980000; 87 | CSU32 V4L2_CID_BASE_NEW = V4L2_CTRL_CLASS_USER_NEW | 0x900; 88 | CSU32 V4L2_CID_POWER_LINE_FREQUENCY_NEW = V4L2_CID_BASE_NEW + 24; 89 | CSU32 V4L2_CID_HUE_AUTO_NEW = V4L2_CID_BASE_NEW + 25; 90 | CSU32 V4L2_CID_WHITE_BALANCE_TEMPERATURE_NEW = V4L2_CID_BASE_NEW + 26; 91 | CSU32 V4L2_CID_SHARPNESS_NEW = V4L2_CID_BASE_NEW + 27; 92 | CSU32 V4L2_CID_BACKLIGHT_COMPENSATION_NEW = V4L2_CID_BASE_NEW + 28; 93 | CSU32 V4L2_CID_LAST_NEW = V4L2_CID_BASE_NEW + 29; 94 | 95 | CSU32 V4L2_CTRL_CLASS_CAMERA_NEW = 0x009A0000; /* Camera class controls */ 96 | CSU32 V4L2_CID_CAMERA_CLASS_BASE_NEW = V4L2_CTRL_CLASS_CAMERA_NEW | 0x900; 97 | CSU32 V4L2_CID_EXPOSURE_AUTO_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 1; 98 | CSU32 V4L2_CID_EXPOSURE_ABSOLUTE_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 2; 99 | CSU32 V4L2_CID_EXPOSURE_AUTO_PRIORITY_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW+3; 100 | CSU32 V4L2_CID_PAN_RELATIVE_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 4; 101 | CSU32 V4L2_CID_TILT_RELATIVE_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 5; 102 | CSU32 V4L2_CID_PAN_RESET_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 6; 103 | CSU32 V4L2_CID_TILT_RESET_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 7; 104 | CSU32 V4L2_CID_PAN_ABSOLUTE_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 8; 105 | CSU32 V4L2_CID_TILT_ABSOLUTE_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 9; 106 | CSU32 V4L2_CID_FOCUS_ABSOLUTE_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 10; 107 | CSU32 V4L2_CID_FOCUS_RELATIVE_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 11; 108 | CSU32 V4L2_CID_FOCUS_AUTO_NEW = V4L2_CID_CAMERA_CLASS_BASE_NEW + 12; 109 | CSU32 V4L2_CID_CAMERA_CLASS_LAST = V4L2_CID_CAMERA_CLASS_BASE_NEW + 13; 110 | 111 | /*--------------- old private class controls ------------------------------*/ 112 | CSU32 V4L2_CID_PRIVATE_BASE_OLD = 0x08000000; 113 | CSU32 V4L2_CID_BACKLIGHT_COMPENSATION_OLD = V4L2_CID_PRIVATE_BASE_OLD + 0; 114 | CSU32 V4L2_CID_POWER_LINE_FREQUENCY_OLD = V4L2_CID_PRIVATE_BASE_OLD + 1; 115 | CSU32 V4L2_CID_SHARPNESS_OLD = V4L2_CID_PRIVATE_BASE_OLD + 2; 116 | CSU32 V4L2_CID_HUE_AUTO_OLD = V4L2_CID_PRIVATE_BASE_OLD + 3; 117 | CSU32 V4L2_CID_FOCUS_AUTO_OLD = V4L2_CID_PRIVATE_BASE_OLD + 4; 118 | CSU32 V4L2_CID_FOCUS_ABSOLUTE_OLD = V4L2_CID_PRIVATE_BASE_OLD + 5; 119 | CSU32 V4L2_CID_FOCUS_RELATIVE_OLD = V4L2_CID_PRIVATE_BASE_OLD + 6; 120 | CSU32 V4L2_CID_PAN_RELATIVE_OLD = V4L2_CID_PRIVATE_BASE_OLD + 7; 121 | CSU32 V4L2_CID_TILT_RELATIVE_OLD = V4L2_CID_PRIVATE_BASE_OLD + 8; 122 | CSU32 V4L2_CID_PANTILT_RESET_OLD = V4L2_CID_PRIVATE_BASE_OLD + 9; 123 | CSU32 V4L2_CID_EXPOSURE_AUTO_OLD = V4L2_CID_PRIVATE_BASE_OLD + 10; 124 | CSU32 V4L2_CID_EXPOSURE_ABSOLUTE_OLD = V4L2_CID_PRIVATE_BASE_OLD + 11; 125 | CSU32 V4L2_CID_WHITE_BALANCE_TEMP_AUTO_OLD = V4L2_CID_PRIVATE_BASE_OLD+12; 126 | CSU32 V4L2_CID_WHITE_BALANCE_TEMP_OLD = V4L2_CID_PRIVATE_BASE_OLD + 13; 127 | CSU32 V4L2_CID_PRIVATE_LAST = V4L2_CID_WHITE_BALANCE_TEMP_OLD + 1; 128 | // dynamic controls 129 | CSU32 UVC_CTRL_DATA_TYPE_RAW = 0; 130 | CSU32 UVC_CTRL_DATA_TYPE_SIGNED = 1; 131 | CSU32 UVC_CTRL_DATA_TYPE_UNSIGNED = 2; 132 | CSU32 UVC_CTRL_DATA_TYPE_BOOLEAN = 3; 133 | CSU32 UVC_CTRL_DATA_TYPE_ENUM = 4; 134 | CSU32 UVC_CTRL_DATA_TYPE_BITMASK = 5; 135 | CSU32 V4L2_CID_BASE_EXTCTR = 0x0A046D01; 136 | CSU32 V4L2_CID_BASE_LOGITECH = V4L2_CID_BASE_EXTCTR; 137 | //CSU32 V4L2_CID_PAN_RELATIVE_LOGITECH = V4L2_CID_BASE_LOGITECH; 138 | //CSU32 V4L2_CID_TILT_RELATIVE_LOGITECH = V4L2_CID_BASE_LOGITECH + 1; 139 | CSU32 V4L2_CID_PANTILT_RESET_LOGITECH = V4L2_CID_BASE_LOGITECH + 2; 140 | CSU32 V4L2_CID_FOCUS_LOGITECH = V4L2_CID_BASE_LOGITECH + 3; 141 | CSU32 V4L2_CID_LED1_MODE_LOGITECH = V4L2_CID_BASE_LOGITECH + 4; 142 | CSU32 V4L2_CID_LED1_FREQUENCY_LOGITECH = V4L2_CID_BASE_LOGITECH + 5; 143 | CSU32 V4L2_CID_DISABLE_PROCESSING_LOGITECH = V4L2_CID_BASE_LOGITECH + 0x70; 144 | CSU32 V4L2_CID_RAW_BITS_PER_PIXEL_LOGITECH = V4L2_CID_BASE_LOGITECH + 0x71; 145 | CSU32 V4L2_CID_LAST_EXTCTR = V4L2_CID_RAW_BITS_PER_PIXEL_LOGITECH; 146 | 147 | }; 148 | 149 | } 150 | 151 | #endif 152 | 153 | --------------------------------------------------------------------------------