├── .ci-scripts ├── bits.tcl └── run-linter.py ├── .gitignore ├── .gitlab-ci.yml ├── .gitmodules ├── README.md ├── asm ├── Makefile └── user-sample.s ├── golden_trace.txt ├── tb_behav.wcfg ├── thinpad_top.srcs ├── constrs_1 │ └── new │ │ └── thinpad_top.xdc ├── sim_1 │ ├── imports │ │ ├── CFImemory64Mb_bottom.mem │ │ └── CFImemory64Mb_top.mem │ └── new │ │ ├── 28F640P30.v │ │ ├── clock.v │ │ ├── cpld_model.v │ │ ├── flag_sync_cpld.v │ │ ├── include │ │ ├── BankLib.h │ │ ├── CUIcommandData.h │ │ ├── TimingData.h │ │ ├── UserData.h │ │ ├── data.h │ │ └── def.h │ │ ├── sram_model.v │ │ └── tb.sv └── sources_1 │ ├── ip │ └── pll_example │ │ ├── doc │ │ └── clk_wiz_v6_0_changelog.txt │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_plus_pll.vh │ │ ├── pll_example.v │ │ ├── pll_example.xci │ │ ├── pll_example.xdc │ │ ├── pll_example.xml │ │ ├── pll_example_board.xdc │ │ ├── pll_example_clk_wiz.v │ │ └── pll_example_ooc.xdc │ └── new │ ├── Nova132A │ ├── CTRL.v │ ├── DC.v │ ├── DF.v │ ├── EX.v │ ├── IC.v │ ├── ID.v │ ├── IF.v │ ├── MEM.v │ ├── WB.v │ ├── bridge_1x3.v │ ├── cache.v │ ├── confreg.v │ ├── hilo_reg.v │ ├── lib │ │ ├── alu.v │ │ ├── cache │ │ │ ├── bank.v │ │ │ ├── double_line.v │ │ │ ├── i_bank.v │ │ │ ├── icache_line.v │ │ │ └── line.v │ │ ├── cache_bank │ │ │ ├── cache_bank.xci │ │ │ ├── cache_bank.xml │ │ │ ├── cache_bank_ooc.xdc │ │ │ ├── doc │ │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ │ ├── hdl │ │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ ├── misc │ │ │ │ └── blk_mem_gen_v8_4.vhd │ │ │ ├── sim │ │ │ │ └── cache_bank.v │ │ │ ├── simulation │ │ │ │ └── blk_mem_gen_v8_4.v │ │ │ └── synth │ │ │ │ └── cache_bank.vhd │ │ ├── dcache_tag │ │ │ ├── dcache_tag.xci │ │ │ ├── dcache_tag.xml │ │ │ ├── dcache_tag_ooc.xdc │ │ │ ├── doc │ │ │ │ └── dist_mem_gen_v8_0_changelog.txt │ │ │ ├── hdl │ │ │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ │ │ ├── sim │ │ │ │ └── dcache_tag.v │ │ │ ├── simulation │ │ │ │ └── dist_mem_gen_v8_0.v │ │ │ └── synth │ │ │ │ └── dcache_tag.vhd │ │ ├── decoder_2_4.v │ │ ├── decoder_3_8.v │ │ ├── decoder_5_32.v │ │ ├── decoder_6_64.v │ │ ├── defines.vh │ │ ├── div.v │ │ ├── mmu.v │ │ ├── mul │ │ │ ├── add.v │ │ │ ├── fa.v │ │ │ └── mul.v │ │ └── regfile.v │ ├── mycpu_core.v │ ├── mycpu_top.v │ ├── readme.md │ └── uncache.v │ ├── SEG7_LUT.v │ ├── async.v │ ├── clock_converter.v │ ├── sram_ctrl.v │ ├── thinpad_top.v │ └── vga.v ├── thinpad_top.xpr ├── vivado_pid10360.str └── vivado_pid23304.str /.ci-scripts/bits.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fluctlight001/cpu_for_nscscc2022_single/HEAD/.ci-scripts/bits.tcl -------------------------------------------------------------------------------- /.ci-scripts/run-linter.py: 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