├── README.md ├── 代码 ├── ahb_arbiter.sv ├── ahb_decoder.sv ├── ahb_if.sv ├── ahb_master1.sv ├── ahb_master2.sv ├── ahb_pkg.sv ├── ahb_slave1.sv ├── ahb_slave2.sv ├── ahb_top.sv └── arbiter.sv └── 基于SystemVerilog的AHB总线接口设计.docx /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/README.md -------------------------------------------------------------------------------- /代码/ahb_arbiter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_arbiter.sv -------------------------------------------------------------------------------- /代码/ahb_decoder.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_decoder.sv -------------------------------------------------------------------------------- /代码/ahb_if.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_if.sv -------------------------------------------------------------------------------- /代码/ahb_master1.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_master1.sv -------------------------------------------------------------------------------- /代码/ahb_master2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_master2.sv -------------------------------------------------------------------------------- /代码/ahb_pkg.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_pkg.sv -------------------------------------------------------------------------------- /代码/ahb_slave1.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_slave1.sv -------------------------------------------------------------------------------- /代码/ahb_slave2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_slave2.sv -------------------------------------------------------------------------------- /代码/ahb_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/ahb_top.sv -------------------------------------------------------------------------------- /代码/arbiter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/代码/arbiter.sv -------------------------------------------------------------------------------- /基于SystemVerilog的AHB总线接口设计.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forever-gk/AHB-SystemVerilog/HEAD/基于SystemVerilog的AHB总线接口设计.docx --------------------------------------------------------------------------------