├── .gitignore ├── LICENSE ├── README.md ├── board ├── A-E115FB │ ├── Readme.odt │ ├── Readme.pdf │ ├── ae115fb.v │ ├── config.v │ ├── ip-components │ │ ├── baseram.v │ │ ├── bootrom.v │ │ ├── fontrom.v │ │ ├── kgdvram.qip │ │ ├── kgdvram.v │ │ ├── pll.v │ │ ├── rom000.v │ │ ├── rom055.v │ │ ├── sectorbuf.v │ │ ├── userrom.v │ │ └── vtmem.v │ ├── top.qpf │ ├── top.qsf │ └── top.sdc ├── A-ESTFv2 │ ├── Readme.odt │ ├── Readme.pdf │ ├── aestf.v │ ├── config.v │ ├── ip-components │ │ ├── bootrom.v │ │ ├── fontrom.v │ │ ├── kgdvram.qip │ │ ├── kgdvram.v │ │ ├── pll.v │ │ ├── rom000.v │ │ ├── rom055.v │ │ ├── rom134.v │ │ ├── sectorbuf.v │ │ ├── userrom.v │ │ └── vtmem.v │ ├── top.qpf │ └── top.qsf ├── AX4010 │ ├── Readme.odt │ ├── Readme.pdf │ ├── ax4010.v │ ├── config.v │ ├── ip-components │ │ ├── bootrom.v │ │ ├── fontrom.v │ │ ├── kgdvram.qip │ │ ├── kgdvram.v │ │ ├── pll.v │ │ ├── rom000.v │ │ ├── rom055.v │ │ ├── rom134.v │ │ ├── sectorbuf.v │ │ ├── userrom.v │ │ └── vtmem.v │ ├── sectorbuf.v │ ├── top.qpf │ └── top.qsf ├── OMDAZZ-RZ301 │ ├── Readme.odt │ ├── Readme.pdf │ ├── config.v │ ├── ip-components │ │ ├── bootrom.v │ │ ├── fontrom.v │ │ ├── kgdvram.qip │ │ ├── kgdvram.v │ │ ├── pll.v │ │ ├── rom000.v │ │ ├── rom055.v │ │ ├── rom134.v │ │ ├── sectorbuf.v │ │ ├── userrom.v │ │ └── vtmem.v │ ├── omdazz.v │ ├── pinout.ods │ ├── readme.md │ ├── sectorbuf.v │ ├── top.qpf │ └── top.qsf ├── QMTECH-E55 │ ├── Readme.odt │ ├── Readme.pdf │ ├── config.v │ ├── ip-components │ │ ├── bootrom.v │ │ ├── fontrom.v │ │ ├── kgdvram.qip │ │ ├── kgdvram.v │ │ ├── pll.v │ │ ├── rom000.v │ │ ├── rom055.v │ │ ├── rom134.v │ │ ├── sectorbuf.v │ │ ├── userrom.v │ │ └── vtmem.v │ ├── pinout.ods │ ├── qmtech.v │ ├── top.qpf │ └── top.qsf └── tang │ ├── Readme.odt │ ├── Readme.pdf │ ├── config.v │ ├── ip-components │ ├── pll.ipc │ ├── pll.v │ ├── tang_bootrom.v │ ├── tang_fontrom.ipc │ ├── tang_fontrom.v │ ├── tang_kgdvram.ipc │ ├── tang_kgdvram.v │ ├── tang_rom000.v │ ├── tang_rom055.v │ ├── tang_rom134.v │ ├── tang_sectorbuf.v │ ├── tang_user_rom.v │ ├── tang_vm1_vcram.v │ ├── tang_vtmem.ipc │ └── tang_vtmem.v │ ├── memory_adapter.v │ ├── pict │ ├── ioboard-rs232.png │ ├── ioboardb.png │ ├── ioboards.png │ └── tang.jpg │ ├── pinout.ods │ ├── ram │ └── vm1_vcram.mif │ ├── sipeed-tang-primer-pins.pdf │ ├── tang.v │ ├── top.adc │ ├── top.al │ └── top.sdc ├── disk ├── Makefile ├── devtable.h ├── initdisk.7z ├── sd-extract ├── sd-extract.c ├── sd-store └── sd-store.c ├── doc ├── 377.pdf ├── build-own-modules.odt ├── build-own-modules.pdf ├── card-layout.ods ├── dio.v ├── main-manual.odt ├── main-manual.pdf ├── pdp2011.odt ├── pdp2011.pdf ├── vm3.odt └── vm3.pdf ├── hdl ├── altera.sdc ├── common-config.v ├── dw.v ├── f11 │ ├── dc_302.v │ ├── dc_303.v │ ├── dc_304.v │ ├── dc_fpp.v │ ├── dc_mmu.v │ ├── dc_pla.v │ ├── dc_pla_0.v │ ├── dc_pla_1.v │ ├── dc_pla_2.v │ ├── dc_rom.v │ ├── f11_wb.v │ └── kdf11b_rom.v ├── fdd-my.v ├── irpr-centronix.v ├── kdf11-b.v ├── kgd-graphics.v ├── ksm │ ├── ksm.v │ ├── ksm_vic.v │ ├── ps2.v │ ├── vga.v │ ├── vregs.v │ ├── vtram.v │ └── vtreset.v ├── m2 │ ├── lsi_wb.v │ ├── mcp1611.v │ ├── mcp1621.v │ ├── mcp1631.v │ └── mcp_plm.v ├── m4 │ ├── am4_alu.v │ ├── am4_mcrom.v │ ├── am4_plm.v │ ├── am4_seq.v │ └── am4_wb.v ├── mc1201-01.v ├── mc1201-02.v ├── mc1201-04.v ├── mc1260.v ├── mc1280.v ├── pdp2011.v ├── pdp2011 │ ├── cpu_control_regs.v │ ├── cpuregs.v │ ├── fpuregs.v │ ├── mmu.v │ └── wb_cpu2011.v ├── rh70.v ├── rk11.v ├── rk611.v ├── rx01.v ├── sdram_ip │ ├── sdram_cmd.v │ ├── sdram_ctrl.v │ ├── sdram_para.v │ ├── sdram_top.v │ └── sdram_wr_data.v ├── sdspi.v ├── topboard16.v ├── topboard22.v ├── vm1 │ ├── vm1_plm.v │ ├── vm1_reg.v │ ├── vm1_tve.v │ └── vm1_wb.v ├── vm2 │ ├── vm2_plm.v │ └── vm2_wb.v ├── vm3 │ ├── vm3_mmu.v │ ├── vm3_plm.v │ └── vm3_wb.v ├── wbc_rst.v ├── wbc_uart.v └── wbc_vic.v ├── ksm-firmware ├── compile.sh ├── font │ ├── Makefile │ ├── font-ksm.bin │ ├── font-ksm.mif │ ├── font-main.bin │ ├── font-main.mif │ ├── font2mif │ ├── font2mif.c │ ├── fontextract │ ├── fontextract.c │ ├── fontlist │ ├── fontlist.c │ ├── fontreplace │ └── fontreplace.c ├── ksm-firmware.mac ├── ksm-firmware.mif ├── macro11 ├── rt11obj2bin └── rt11obj2bin.c ├── notab.sh ├── rom ├── 000.bin ├── 000.mif ├── 013-basic.bin ├── 013-basic.mif ├── 055.bin ├── 055.mif ├── 058-focal.bin ├── 058-focal.mif ├── 134.bin ├── 134.mif ├── 134e.bin ├── 134e.mif ├── 279.bin ├── 279.mif ├── 377.bin ├── 377.mif ├── all_22b.rom ├── checksum-134 ├── checksum-134.c ├── conv.sh ├── f11 │ ├── 000.rom │ ├── 001.rom │ ├── 002.rom │ ├── boot_diag_rom.bin │ ├── boot_diag_rom.mif │ ├── bootrom-mod │ │ ├── compile.sh │ │ ├── mboot.mac │ │ └── rom.orig │ ├── conv.sh │ └── mc3401.mif ├── m9312 │ ├── bootrom.mif │ ├── m9312-bootloaders.mac │ ├── m9312-console.mac │ ├── macro11 │ ├── rcompile.sh │ └── rt11obj2bin-t └── mc.rom └── screenshot ├── basic.png ├── clock.png ├── diger.png ├── fmg.png ├── ksmfont-rt11.png ├── land.png ├── ramtest.png ├── rombasic.png ├── rsts-boot.png ├── rsts10-mon1.png ├── rsts10-mon2.png ├── rsx11m-boot.png ├── rsx11m-plus-boot.png ├── rsx11m-plus-rmd.png ├── rsxvm4.png ├── rt11.png ├── statusline.png ├── ted.png ├── tmos.png └── tmos1-ksmfont.png /.gitignore: -------------------------------------------------------------------------------- 1 | db/ 2 | greybox_tmp/ 3 | incremental_db/ 4 | *.rpt 5 | *.qws 6 | output_files/ 7 | simulation/ 8 | ksm-firmware/*.map 9 | ksm-firmware/*.obj 10 | ksm-firmware/*.bin 11 | ksm-firmware/*.lst 12 | *.bak 13 | *.log 14 | *.db 15 | *.area 16 | *.bid 17 | *.bit 18 | *.timing 19 | *.tsm 20 | disk/ 21 | rsx/ 22 | 23 | 24 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # dvk-fpga 2 | FPGA-версия старых советских ЭВМ ДВК-1, ДВК-2, ДВК-3, Электроника-60, Электроника-79 3 | 4 | Этот проект является моей попыткой создать FPGA-версию советских ЭВМ, основанных на процессорных ядрах от уважаемого VLSAV, полученных им путем реверса схемы кристаллов. 5 | Проект основан на wishbone-версии процессоров. Вся внутренняя шина получившейся схемы - это тоже wishbone, а не асинхронная МПИ. В данный момент реализованы следующие процессорные платы: 6 | 7 | | Плата | Процессор | ЭВМ | Шина адреса | EIS | FIS | FPP | MMU | 8 | |:----------------|:---------|:----------------|:---------------|:---|:---|:---|:---| 9 | | МС1201.01 | К1801ВМ1 | ДВК-1,ДВК-2 | 16 бит|MUL| | | | 10 | | МС1201.02 | К1801ВМ2 | ДВК-3 | 16 бит| + | + | | | 11 | | МС1201.03 | К1801ВМ3 | ДВК-3M | 22 бит| + | | | + | 12 | | МС1201.04 | К1801ВМ3 | ДВК-4 | 22 бит| + | | | + | 13 | | МС1260 | М2 (LSI-11) | Электроника-60 | 16 бит| + | + | | | 14 | | МС1280 | М4 (LSI-11M) | | 16 бит| + | + | | | 15 | | MC1212 | M6 (F-11) | Электроника-60-1 | 22 бит| + | | + | + | 16 | | PDP2011 | PDP11/70 | Электроника-79 | 22 бит| + | | + | + | 17 | 18 | Как и в оригинальных ЭВМ, на верхнем уровне схемы находится соединительная корзина, в которую вставляется одна процессорная плата и несколько плат периферийных устройств. На данный момент реализованы следующие устройства: 19 | 20 | - ИРПС, контроллер последовательной передачи данных, используется в том числе для подключения консольного терминала 21 | - ИРПР, контроллер параллельной передачи, для поключения принтера 22 | - КСМ, терминальный моудль, работает с VGA-мониторами и PS/2 клавиатурой. 23 | - КГД, графический контроллер, работает в паре с КСМ 24 | - Контроллер RK11 (RK:) с подключенными у нему 8 дисками RK05 25 | - Контроллер RK611 (DM:) с подключенными у нему 8 дисками RK07 26 | - Контроллер Mussbus RH-70/RP-11 (DB:) с подключенными у нему 8 дисками RP06 27 | - Контроллер HDD RD50C (DW:) в варианте ДВК с подключенным к нему виртуальным HDD объемом 64 Мб. 28 | - Контроллер RX11 (DX:) с подключенными к нему двумя дисководами RX01 (наш аналог - ГМД70) 29 | - Контроллер КГД (MY:) с подключенными к нему двумя сдвоенными дисководами НГМД-6121 30 | - Контроллер синхронной динамической памяти SDRAM 31 | - Сетевой таймер (LTC) 32 | - ПЗУ пультового монитора/загрузчика, аналогичное DEC М9312 33 | - ПЗУ пользователя размером 8К (в ДВК-1 там размещался резидентный Бейсик или Фокал). 34 | 35 | Все дисковые контроллеры хранят свои данные на единой SD-карте, но можно разнести их и по отдельным картам. Карту распределения блоков под дисковые массивы также можно менять как угодно. 36 | 37 | Кроме вышеуказанных модулей, в схему можно добавлять и свои самодельные модули с wishbone-интерфейсом. 38 | 39 | Проект реализован на FPGA серии Altera Cyclone-4. В полной конфигурации вмещается в EP4CE10, но при отключении части устройств может уместиться даже в младшую EP4CE6. Из аппаратных особенностей этих FPGA используется только PLL и внутренняя память Altsyncram, поэтому проект должен легко портироваться на другие семейства FPGA Altera, и чуть сложнее - на FPGA других производителей. В данную разработку уже заложена возможность создания портов для различных плат, каждый порт в виде самостоятельного проекта хранится в отдельных подкаталогах boards/. 40 | Также выполнен порт проекта на плату Sipeed TANG PRIMER, основанной на китайской FPGA EG4S20BG256 фирмы Anlogic. 41 | 42 | Эта разработка с середины лета 2020 года успешно трудится в лаборатории в качестве контроллера испытательного стенда и показала полную работоспособность. Все, кому надо заменить устаревшее оборудование, основанное на плате МС1201, МС1260, МС1280,могут доработать схему под свои конкретные нужды. 43 | -------------------------------------------------------------------------------- /board/A-E115FB/Readme.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/A-E115FB/Readme.odt -------------------------------------------------------------------------------- /board/A-E115FB/Readme.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/A-E115FB/Readme.pdf -------------------------------------------------------------------------------- /board/A-E115FB/ip-components/bootrom.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // synopsys translate_off 7 | `timescale 1 ps / 1 ps 8 | // synopsys translate_on 9 | module boot_rom ( 10 | address, 11 | clock, 12 | q); 13 | 14 | input [8:0] address; 15 | input clock; 16 | output [15:0] q; 17 | `ifndef ALTERA_RESERVED_QIS 18 | // synopsys translate_off 19 | `endif 20 | tri1 clock; 21 | `ifndef ALTERA_RESERVED_QIS 22 | // synopsys translate_on 23 | `endif 24 | 25 | wire [15:0] sub_wire0; 26 | wire [15:0] q = sub_wire0[15:0]; 27 | 28 | altsyncram altsyncram_component ( 29 | .address_a (address), 30 | .clock0 (clock), 31 | .q_a (sub_wire0), 32 | .aclr0 (1'b0), 33 | .aclr1 (1'b0), 34 | .address_b (1'b1), 35 | .addressstall_a (1'b0), 36 | .addressstall_b (1'b0), 37 | .byteena_a (1'b1), 38 | .byteena_b (1'b1), 39 | .clock1 (1'b1), 40 | .clocken0 (1'b1), 41 | .clocken1 (1'b1), 42 | .clocken2 (1'b1), 43 | .clocken3 (1'b1), 44 | .data_a ({16{1'b1}}), 45 | .data_b (1'b1), 46 | .eccstatus (), 47 | .q_b (), 48 | .rden_a (1'b1), 49 | .rden_b (1'b1), 50 | .wren_a (1'b0), 51 | .wren_b (1'b0)); 52 | defparam 53 | altsyncram_component.address_aclr_a = "NONE", 54 | altsyncram_component.clock_enable_input_a = "BYPASS", 55 | altsyncram_component.clock_enable_output_a = "BYPASS", 56 | altsyncram_component.init_file = "../../rom/m9312/bootrom.mif", 57 | altsyncram_component.intended_device_family = "Cyclone IV E", 58 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=boot_rom", 59 | altsyncram_component.lpm_type = "altsyncram", 60 | altsyncram_component.numwords_a = 512, 61 | altsyncram_component.operation_mode = "ROM", 62 | altsyncram_component.outdata_aclr_a = "NONE", 63 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 64 | altsyncram_component.widthad_a = 9, 65 | altsyncram_component.width_a = 16, 66 | altsyncram_component.width_byteena_a = 1; 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /board/A-E115FB/ip-components/kgdvram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "kgdvram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "kgdvram_bb.v"] 6 | -------------------------------------------------------------------------------- /board/A-E115FB/top.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition 21 | # Date created = 17:45:33 июня 20, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "17:45:33 июня 20, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "top" 31 | -------------------------------------------------------------------------------- /board/A-E115FB/top.sdc: -------------------------------------------------------------------------------- 1 | ## Generated SDC file "top.sdc" 2 | 3 | ## Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | ## Your use of Intel Corporation's design tools, logic functions 5 | ## and other software and tools, and its AMPP partner logic 6 | ## functions, and any output files from any of the foregoing 7 | ## (including device programming or simulation files), and any 8 | ## associated documentation or information are expressly subject 9 | ## to the terms and conditions of the Intel Program License 10 | ## Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | ## the Intel FPGA IP License Agreement, or other applicable license 12 | ## agreement, including, without limitation, that your use is for 13 | ## the sole purpose of programming logic devices manufactured by 14 | ## Intel and sold by Intel or its authorized distributors. Please 15 | ## refer to the applicable agreement for further details. 16 | 17 | 18 | ## VENDOR "Altera" 19 | ## PROGRAM "Quartus Prime" 20 | ## VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" 21 | 22 | ## DATE "Fri Feb 19 07:45:51 2021" 23 | 24 | ## 25 | ## DEVICE "EP4CE22F17C7" 26 | ## 27 | 28 | 29 | #************************************************************** 30 | # Time Information 31 | #************************************************************** 32 | 33 | set_time_format -unit ns -decimal_places 3 34 | 35 | 36 | 37 | #************************************************************** 38 | # Create Clock 39 | #************************************************************** 40 | 41 | create_clock -name {clk} -period 40.000 -waveform { 0.000 20.000 } [get_ports {clk25}] 42 | 43 | #************************************************************** 44 | # Create Generated Clock 45 | #************************************************************** 46 | derive_pll_clocks 47 | 48 | #************************************************************** 49 | # Set Clock Latency 50 | #************************************************************** 51 | 52 | 53 | 54 | #************************************************************** 55 | # Set Clock Uncertainty 56 | #************************************************************** 57 | derive_clock_uncertainty 58 | 59 | 60 | 61 | #************************************************************** 62 | # Set Input Delay 63 | #************************************************************** 64 | 65 | 66 | 67 | #************************************************************** 68 | # Set Output Delay 69 | #************************************************************** 70 | 71 | 72 | 73 | #************************************************************** 74 | # Set Clock Groups 75 | #************************************************************** 76 | 77 | 78 | 79 | #************************************************************** 80 | # Set False Path 81 | #************************************************************** 82 | 83 | 84 | 85 | #************************************************************** 86 | # Set Multicycle Path 87 | #************************************************************** 88 | 89 | 90 | 91 | #************************************************************** 92 | # Set Maximum Delay 93 | #************************************************************** 94 | 95 | 96 | 97 | #************************************************************** 98 | # Set Minimum Delay 99 | #************************************************************** 100 | 101 | 102 | 103 | #************************************************************** 104 | # Set Input Transition 105 | #************************************************************** 106 | 107 | -------------------------------------------------------------------------------- /board/A-ESTFv2/Readme.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/A-ESTFv2/Readme.odt -------------------------------------------------------------------------------- /board/A-ESTFv2/Readme.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/A-ESTFv2/Readme.pdf -------------------------------------------------------------------------------- /board/A-ESTFv2/ip-components/bootrom.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // synopsys translate_off 7 | `timescale 1 ps / 1 ps 8 | // synopsys translate_on 9 | module boot_rom ( 10 | address, 11 | clock, 12 | q); 13 | 14 | input [8:0] address; 15 | input clock; 16 | output [15:0] q; 17 | `ifndef ALTERA_RESERVED_QIS 18 | // synopsys translate_off 19 | `endif 20 | tri1 clock; 21 | `ifndef ALTERA_RESERVED_QIS 22 | // synopsys translate_on 23 | `endif 24 | 25 | wire [15:0] sub_wire0; 26 | wire [15:0] q = sub_wire0[15:0]; 27 | 28 | altsyncram altsyncram_component ( 29 | .address_a (address), 30 | .clock0 (clock), 31 | .q_a (sub_wire0), 32 | .aclr0 (1'b0), 33 | .aclr1 (1'b0), 34 | .address_b (1'b1), 35 | .addressstall_a (1'b0), 36 | .addressstall_b (1'b0), 37 | .byteena_a (1'b1), 38 | .byteena_b (1'b1), 39 | .clock1 (1'b1), 40 | .clocken0 (1'b1), 41 | .clocken1 (1'b1), 42 | .clocken2 (1'b1), 43 | .clocken3 (1'b1), 44 | .data_a ({16{1'b1}}), 45 | .data_b (1'b1), 46 | .eccstatus (), 47 | .q_b (), 48 | .rden_a (1'b1), 49 | .rden_b (1'b1), 50 | .wren_a (1'b0), 51 | .wren_b (1'b0)); 52 | defparam 53 | altsyncram_component.address_aclr_a = "NONE", 54 | altsyncram_component.clock_enable_input_a = "BYPASS", 55 | altsyncram_component.clock_enable_output_a = "BYPASS", 56 | altsyncram_component.init_file = "../../rom/m9312/bootrom.mif", 57 | altsyncram_component.intended_device_family = "Cyclone IV E", 58 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=boot_rom", 59 | altsyncram_component.lpm_type = "altsyncram", 60 | altsyncram_component.numwords_a = 512, 61 | altsyncram_component.operation_mode = "ROM", 62 | altsyncram_component.outdata_aclr_a = "NONE", 63 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 64 | altsyncram_component.widthad_a = 9, 65 | altsyncram_component.width_a = 16, 66 | altsyncram_component.width_byteena_a = 1; 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /board/A-ESTFv2/ip-components/kgdvram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "kgdvram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "kgdvram_bb.v"] 6 | -------------------------------------------------------------------------------- /board/A-ESTFv2/ip-components/rom134.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: rom134.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // synopsys translate_off 15 | `timescale 1 ps / 1 ps 16 | // synopsys translate_on 17 | module rom134 ( 18 | address, 19 | clock, 20 | q); 21 | 22 | input [11:0] address; 23 | input clock; 24 | output [15:0] q; 25 | `ifndef ALTERA_RESERVED_QIS 26 | // synopsys translate_off 27 | `endif 28 | tri1 clock; 29 | `ifndef ALTERA_RESERVED_QIS 30 | // synopsys translate_on 31 | `endif 32 | 33 | wire [15:0] sub_wire0; 34 | wire [15:0] q = sub_wire0[15:0]; 35 | 36 | altsyncram altsyncram_component ( 37 | .address_a (address), 38 | .clock0 (clock), 39 | .q_a (sub_wire0), 40 | .aclr0 (1'b0), 41 | .aclr1 (1'b0), 42 | .address_b (1'b1), 43 | .addressstall_a (1'b0), 44 | .addressstall_b (1'b0), 45 | .byteena_a (1'b1), 46 | .byteena_b (1'b1), 47 | .clock1 (1'b1), 48 | .clocken0 (1'b1), 49 | .clocken1 (1'b1), 50 | .clocken2 (1'b1), 51 | .clocken3 (1'b1), 52 | .data_a ({16{1'b1}}), 53 | .data_b (1'b1), 54 | .eccstatus (), 55 | .q_b (), 56 | .rden_a (1'b1), 57 | .rden_b (1'b1), 58 | .wren_a (1'b0), 59 | .wren_b (1'b0)); 60 | defparam 61 | altsyncram_component.address_aclr_a = "NONE", 62 | altsyncram_component.clock_enable_input_a = "BYPASS", 63 | altsyncram_component.clock_enable_output_a = "BYPASS", 64 | `ifdef vm3_rom 65 | altsyncram_component.init_file = `vm3_rom, 66 | `endif 67 | altsyncram_component.intended_device_family = "Cyclone IV E", 68 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 69 | altsyncram_component.lpm_type = "altsyncram", 70 | altsyncram_component.numwords_a = 4096, 71 | altsyncram_component.operation_mode = "ROM", 72 | altsyncram_component.outdata_aclr_a = "NONE", 73 | altsyncram_component.outdata_reg_a = "CLOCK0", 74 | altsyncram_component.widthad_a = 12, 75 | altsyncram_component.width_a = 16, 76 | altsyncram_component.width_byteena_a = 1; 77 | 78 | endmodule 79 | 80 | // ============================================================ 81 | // CNX file retrieval info 82 | // ============================================================ 83 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 84 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 85 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 86 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 87 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 88 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 89 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 90 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 91 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 92 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 93 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 94 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 95 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 96 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 97 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 98 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 99 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 100 | // Retrieval info: PRIVATE: MIFfilename STRING "../../rom/134e.mif" 101 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 102 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 103 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 104 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 105 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 106 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 107 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 108 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 109 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 110 | // Retrieval info: PRIVATE: rden NUMERIC "0" 111 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 112 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 113 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 114 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 115 | // Retrieval info: CONSTANT: INIT_FILE STRING "./rom/279.mif" 116 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 117 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 118 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 119 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 120 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 121 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 122 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 123 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 124 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 125 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 126 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 127 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 128 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 129 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 130 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 131 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.v TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.inc FALSE 134 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.cmp FALSE 135 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.bsf FALSE 136 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134_inst.v FALSE 137 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134_bb.v TRUE 138 | // Retrieval info: LIB_FILE: altera_mf 139 | -------------------------------------------------------------------------------- /board/A-ESTFv2/top.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition 21 | # Date created = 17:45:33 июня 20, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "17:45:33 июня 20, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "top" 31 | -------------------------------------------------------------------------------- /board/AX4010/Readme.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/AX4010/Readme.odt -------------------------------------------------------------------------------- /board/AX4010/Readme.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/AX4010/Readme.pdf -------------------------------------------------------------------------------- /board/AX4010/ip-components/bootrom.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // synopsys translate_off 7 | `timescale 1 ps / 1 ps 8 | // synopsys translate_on 9 | module boot_rom ( 10 | address, 11 | clock, 12 | q); 13 | 14 | input [8:0] address; 15 | input clock; 16 | output [15:0] q; 17 | `ifndef ALTERA_RESERVED_QIS 18 | // synopsys translate_off 19 | `endif 20 | tri1 clock; 21 | `ifndef ALTERA_RESERVED_QIS 22 | // synopsys translate_on 23 | `endif 24 | 25 | wire [15:0] sub_wire0; 26 | wire [15:0] q = sub_wire0[15:0]; 27 | 28 | altsyncram altsyncram_component ( 29 | .address_a (address), 30 | .clock0 (clock), 31 | .q_a (sub_wire0), 32 | .aclr0 (1'b0), 33 | .aclr1 (1'b0), 34 | .address_b (1'b1), 35 | .addressstall_a (1'b0), 36 | .addressstall_b (1'b0), 37 | .byteena_a (1'b1), 38 | .byteena_b (1'b1), 39 | .clock1 (1'b1), 40 | .clocken0 (1'b1), 41 | .clocken1 (1'b1), 42 | .clocken2 (1'b1), 43 | .clocken3 (1'b1), 44 | .data_a ({16{1'b1}}), 45 | .data_b (1'b1), 46 | .eccstatus (), 47 | .q_b (), 48 | .rden_a (1'b1), 49 | .rden_b (1'b1), 50 | .wren_a (1'b0), 51 | .wren_b (1'b0)); 52 | defparam 53 | altsyncram_component.address_aclr_a = "NONE", 54 | altsyncram_component.clock_enable_input_a = "BYPASS", 55 | altsyncram_component.clock_enable_output_a = "BYPASS", 56 | altsyncram_component.init_file = "../../rom/m9312/bootrom.mif", 57 | altsyncram_component.intended_device_family = "Cyclone IV E", 58 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=boot_rom", 59 | altsyncram_component.lpm_type = "altsyncram", 60 | altsyncram_component.numwords_a = 512, 61 | altsyncram_component.operation_mode = "ROM", 62 | altsyncram_component.outdata_aclr_a = "NONE", 63 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 64 | altsyncram_component.widthad_a = 9, 65 | altsyncram_component.width_a = 16, 66 | altsyncram_component.width_byteena_a = 1; 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /board/AX4010/ip-components/kgdvram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "kgdvram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "kgdvram_bb.v"] 6 | -------------------------------------------------------------------------------- /board/AX4010/ip-components/rom134.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: rom134.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // synopsys translate_off 15 | `timescale 1 ps / 1 ps 16 | // synopsys translate_on 17 | module rom134 ( 18 | address, 19 | clock, 20 | q); 21 | 22 | input [11:0] address; 23 | input clock; 24 | output [15:0] q; 25 | `ifndef ALTERA_RESERVED_QIS 26 | // synopsys translate_off 27 | `endif 28 | tri1 clock; 29 | `ifndef ALTERA_RESERVED_QIS 30 | // synopsys translate_on 31 | `endif 32 | 33 | wire [15:0] sub_wire0; 34 | wire [15:0] q = sub_wire0[15:0]; 35 | 36 | altsyncram altsyncram_component ( 37 | .address_a (address), 38 | .clock0 (clock), 39 | .q_a (sub_wire0), 40 | .aclr0 (1'b0), 41 | .aclr1 (1'b0), 42 | .address_b (1'b1), 43 | .addressstall_a (1'b0), 44 | .addressstall_b (1'b0), 45 | .byteena_a (1'b1), 46 | .byteena_b (1'b1), 47 | .clock1 (1'b1), 48 | .clocken0 (1'b1), 49 | .clocken1 (1'b1), 50 | .clocken2 (1'b1), 51 | .clocken3 (1'b1), 52 | .data_a ({16{1'b1}}), 53 | .data_b (1'b1), 54 | .eccstatus (), 55 | .q_b (), 56 | .rden_a (1'b1), 57 | .rden_b (1'b1), 58 | .wren_a (1'b0), 59 | .wren_b (1'b0)); 60 | defparam 61 | altsyncram_component.address_aclr_a = "NONE", 62 | altsyncram_component.clock_enable_input_a = "BYPASS", 63 | altsyncram_component.clock_enable_output_a = "BYPASS", 64 | `ifdef vm3_rom 65 | altsyncram_component.init_file = `vm3_rom, 66 | `endif 67 | altsyncram_component.intended_device_family = "Cyclone IV E", 68 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 69 | altsyncram_component.lpm_type = "altsyncram", 70 | altsyncram_component.numwords_a = 4096, 71 | altsyncram_component.operation_mode = "ROM", 72 | altsyncram_component.outdata_aclr_a = "NONE", 73 | altsyncram_component.outdata_reg_a = "CLOCK0", 74 | altsyncram_component.widthad_a = 12, 75 | altsyncram_component.width_a = 16, 76 | altsyncram_component.width_byteena_a = 1; 77 | 78 | endmodule 79 | 80 | // ============================================================ 81 | // CNX file retrieval info 82 | // ============================================================ 83 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 84 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 85 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 86 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 87 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 88 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 89 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 90 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 91 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 92 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 93 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 94 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 95 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 96 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 97 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 98 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 99 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 100 | // Retrieval info: PRIVATE: MIFfilename STRING "../../rom/134e.mif" 101 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 102 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 103 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 104 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 105 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 106 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 107 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 108 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 109 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 110 | // Retrieval info: PRIVATE: rden NUMERIC "0" 111 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 112 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 113 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 114 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 115 | // Retrieval info: CONSTANT: INIT_FILE STRING "./rom/279.mif" 116 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 117 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 118 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 119 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 120 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 121 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 122 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 123 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 124 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 125 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 126 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 127 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 128 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 129 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 130 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 131 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.v TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.inc FALSE 134 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.cmp FALSE 135 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.bsf FALSE 136 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134_inst.v FALSE 137 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134_bb.v TRUE 138 | // Retrieval info: LIB_FILE: altera_mf 139 | -------------------------------------------------------------------------------- /board/AX4010/top.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition 21 | # Date created = 17:45:33 июня 20, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "17:45:33 июня 20, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "top" 31 | -------------------------------------------------------------------------------- /board/OMDAZZ-RZ301/Readme.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/OMDAZZ-RZ301/Readme.odt -------------------------------------------------------------------------------- /board/OMDAZZ-RZ301/Readme.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/OMDAZZ-RZ301/Readme.pdf -------------------------------------------------------------------------------- /board/OMDAZZ-RZ301/ip-components/bootrom.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // synopsys translate_off 7 | `timescale 1 ps / 1 ps 8 | // synopsys translate_on 9 | module boot_rom ( 10 | address, 11 | clock, 12 | q); 13 | 14 | input [8:0] address; 15 | input clock; 16 | output [15:0] q; 17 | `ifndef ALTERA_RESERVED_QIS 18 | // synopsys translate_off 19 | `endif 20 | tri1 clock; 21 | `ifndef ALTERA_RESERVED_QIS 22 | // synopsys translate_on 23 | `endif 24 | 25 | wire [15:0] sub_wire0; 26 | wire [15:0] q = sub_wire0[15:0]; 27 | 28 | altsyncram altsyncram_component ( 29 | .address_a (address), 30 | .clock0 (clock), 31 | .q_a (sub_wire0), 32 | .aclr0 (1'b0), 33 | .aclr1 (1'b0), 34 | .address_b (1'b1), 35 | .addressstall_a (1'b0), 36 | .addressstall_b (1'b0), 37 | .byteena_a (1'b1), 38 | .byteena_b (1'b1), 39 | .clock1 (1'b1), 40 | .clocken0 (1'b1), 41 | .clocken1 (1'b1), 42 | .clocken2 (1'b1), 43 | .clocken3 (1'b1), 44 | .data_a ({16{1'b1}}), 45 | .data_b (1'b1), 46 | .eccstatus (), 47 | .q_b (), 48 | .rden_a (1'b1), 49 | .rden_b (1'b1), 50 | .wren_a (1'b0), 51 | .wren_b (1'b0)); 52 | defparam 53 | altsyncram_component.address_aclr_a = "NONE", 54 | altsyncram_component.clock_enable_input_a = "BYPASS", 55 | altsyncram_component.clock_enable_output_a = "BYPASS", 56 | altsyncram_component.init_file = "../../rom/m9312/bootrom.mif", 57 | altsyncram_component.intended_device_family = "Cyclone IV E", 58 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=boot_rom", 59 | altsyncram_component.lpm_type = "altsyncram", 60 | altsyncram_component.numwords_a = 512, 61 | altsyncram_component.operation_mode = "ROM", 62 | altsyncram_component.outdata_aclr_a = "NONE", 63 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 64 | altsyncram_component.widthad_a = 9, 65 | altsyncram_component.width_a = 16, 66 | altsyncram_component.width_byteena_a = 1; 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /board/OMDAZZ-RZ301/ip-components/kgdvram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "kgdvram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "kgdvram_bb.v"] 6 | -------------------------------------------------------------------------------- /board/OMDAZZ-RZ301/ip-components/rom134.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: rom134.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // synopsys translate_off 15 | `timescale 1 ps / 1 ps 16 | // synopsys translate_on 17 | module rom134 ( 18 | address, 19 | clock, 20 | q); 21 | 22 | input [11:0] address; 23 | input clock; 24 | output [15:0] q; 25 | `ifndef ALTERA_RESERVED_QIS 26 | // synopsys translate_off 27 | `endif 28 | tri1 clock; 29 | `ifndef ALTERA_RESERVED_QIS 30 | // synopsys translate_on 31 | `endif 32 | 33 | wire [15:0] sub_wire0; 34 | wire [15:0] q = sub_wire0[15:0]; 35 | 36 | altsyncram altsyncram_component ( 37 | .address_a (address), 38 | .clock0 (clock), 39 | .q_a (sub_wire0), 40 | .aclr0 (1'b0), 41 | .aclr1 (1'b0), 42 | .address_b (1'b1), 43 | .addressstall_a (1'b0), 44 | .addressstall_b (1'b0), 45 | .byteena_a (1'b1), 46 | .byteena_b (1'b1), 47 | .clock1 (1'b1), 48 | .clocken0 (1'b1), 49 | .clocken1 (1'b1), 50 | .clocken2 (1'b1), 51 | .clocken3 (1'b1), 52 | .data_a ({16{1'b1}}), 53 | .data_b (1'b1), 54 | .eccstatus (), 55 | .q_b (), 56 | .rden_a (1'b1), 57 | .rden_b (1'b1), 58 | .wren_a (1'b0), 59 | .wren_b (1'b0)); 60 | defparam 61 | altsyncram_component.address_aclr_a = "NONE", 62 | altsyncram_component.clock_enable_input_a = "BYPASS", 63 | altsyncram_component.clock_enable_output_a = "BYPASS", 64 | `ifdef vm3_rom 65 | altsyncram_component.init_file = `vm3_rom, 66 | `endif 67 | altsyncram_component.intended_device_family = "Cyclone IV E", 68 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 69 | altsyncram_component.lpm_type = "altsyncram", 70 | altsyncram_component.numwords_a = 4096, 71 | altsyncram_component.operation_mode = "ROM", 72 | altsyncram_component.outdata_aclr_a = "NONE", 73 | altsyncram_component.outdata_reg_a = "CLOCK0", 74 | altsyncram_component.widthad_a = 12, 75 | altsyncram_component.width_a = 16, 76 | altsyncram_component.width_byteena_a = 1; 77 | 78 | endmodule 79 | 80 | // ============================================================ 81 | // CNX file retrieval info 82 | // ============================================================ 83 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 84 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 85 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 86 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 87 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 88 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 89 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 90 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 91 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 92 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 93 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 94 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 95 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 96 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 97 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 98 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 99 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 100 | // Retrieval info: PRIVATE: MIFfilename STRING "../../rom/134e.mif" 101 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 102 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 103 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 104 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 105 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 106 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 107 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 108 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 109 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 110 | // Retrieval info: PRIVATE: rden NUMERIC "0" 111 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 112 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 113 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 114 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 115 | // Retrieval info: CONSTANT: INIT_FILE STRING "./rom/279.mif" 116 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 117 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 118 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 119 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 120 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 121 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 122 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 123 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 124 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 125 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 126 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 127 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 128 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 129 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 130 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 131 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.v TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.inc FALSE 134 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.cmp FALSE 135 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.bsf FALSE 136 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134_inst.v FALSE 137 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134_bb.v TRUE 138 | // Retrieval info: LIB_FILE: altera_mf 139 | -------------------------------------------------------------------------------- /board/OMDAZZ-RZ301/pinout.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/OMDAZZ-RZ301/pinout.ods -------------------------------------------------------------------------------- /board/OMDAZZ-RZ301/readme.md: -------------------------------------------------------------------------------- 1 | Вариант проекта для платы OMDAZZ rz301. 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /board/OMDAZZ-RZ301/top.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition 21 | # Date created = 17:45:33 июня 20, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "17:45:33 июня 20, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "top" 31 | -------------------------------------------------------------------------------- /board/QMTECH-E55/Readme.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/QMTECH-E55/Readme.odt -------------------------------------------------------------------------------- /board/QMTECH-E55/Readme.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/QMTECH-E55/Readme.pdf -------------------------------------------------------------------------------- /board/QMTECH-E55/ip-components/bootrom.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // synopsys translate_off 7 | `timescale 1 ps / 1 ps 8 | // synopsys translate_on 9 | module boot_rom ( 10 | address, 11 | clock, 12 | q); 13 | 14 | input [8:0] address; 15 | input clock; 16 | output [15:0] q; 17 | `ifndef ALTERA_RESERVED_QIS 18 | // synopsys translate_off 19 | `endif 20 | tri1 clock; 21 | `ifndef ALTERA_RESERVED_QIS 22 | // synopsys translate_on 23 | `endif 24 | 25 | wire [15:0] sub_wire0; 26 | wire [15:0] q = sub_wire0[15:0]; 27 | 28 | altsyncram altsyncram_component ( 29 | .address_a (address), 30 | .clock0 (clock), 31 | .q_a (sub_wire0), 32 | .aclr0 (1'b0), 33 | .aclr1 (1'b0), 34 | .address_b (1'b1), 35 | .addressstall_a (1'b0), 36 | .addressstall_b (1'b0), 37 | .byteena_a (1'b1), 38 | .byteena_b (1'b1), 39 | .clock1 (1'b1), 40 | .clocken0 (1'b1), 41 | .clocken1 (1'b1), 42 | .clocken2 (1'b1), 43 | .clocken3 (1'b1), 44 | .data_a ({16{1'b1}}), 45 | .data_b (1'b1), 46 | .eccstatus (), 47 | .q_b (), 48 | .rden_a (1'b1), 49 | .rden_b (1'b1), 50 | .wren_a (1'b0), 51 | .wren_b (1'b0)); 52 | defparam 53 | altsyncram_component.address_aclr_a = "NONE", 54 | altsyncram_component.clock_enable_input_a = "BYPASS", 55 | altsyncram_component.clock_enable_output_a = "BYPASS", 56 | altsyncram_component.init_file = "../../rom/m9312/bootrom.mif", 57 | altsyncram_component.intended_device_family = "Cyclone IV E", 58 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=boot_rom", 59 | altsyncram_component.lpm_type = "altsyncram", 60 | altsyncram_component.numwords_a = 512, 61 | altsyncram_component.operation_mode = "ROM", 62 | altsyncram_component.outdata_aclr_a = "NONE", 63 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 64 | altsyncram_component.widthad_a = 9, 65 | altsyncram_component.width_a = 16, 66 | altsyncram_component.width_byteena_a = 1; 67 | 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /board/QMTECH-E55/ip-components/kgdvram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "kgdvram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "kgdvram_bb.v"] 6 | -------------------------------------------------------------------------------- /board/QMTECH-E55/ip-components/rom134.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: rom134.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // synopsys translate_off 15 | `timescale 1 ps / 1 ps 16 | // synopsys translate_on 17 | module rom134 ( 18 | address, 19 | clock, 20 | q); 21 | 22 | input [11:0] address; 23 | input clock; 24 | output [15:0] q; 25 | `ifndef ALTERA_RESERVED_QIS 26 | // synopsys translate_off 27 | `endif 28 | tri1 clock; 29 | `ifndef ALTERA_RESERVED_QIS 30 | // synopsys translate_on 31 | `endif 32 | 33 | wire [15:0] sub_wire0; 34 | wire [15:0] q = sub_wire0[15:0]; 35 | 36 | altsyncram altsyncram_component ( 37 | .address_a (address), 38 | .clock0 (clock), 39 | .q_a (sub_wire0), 40 | .aclr0 (1'b0), 41 | .aclr1 (1'b0), 42 | .address_b (1'b1), 43 | .addressstall_a (1'b0), 44 | .addressstall_b (1'b0), 45 | .byteena_a (1'b1), 46 | .byteena_b (1'b1), 47 | .clock1 (1'b1), 48 | .clocken0 (1'b1), 49 | .clocken1 (1'b1), 50 | .clocken2 (1'b1), 51 | .clocken3 (1'b1), 52 | .data_a ({16{1'b1}}), 53 | .data_b (1'b1), 54 | .eccstatus (), 55 | .q_b (), 56 | .rden_a (1'b1), 57 | .rden_b (1'b1), 58 | .wren_a (1'b0), 59 | .wren_b (1'b0)); 60 | defparam 61 | altsyncram_component.address_aclr_a = "NONE", 62 | altsyncram_component.clock_enable_input_a = "BYPASS", 63 | altsyncram_component.clock_enable_output_a = "BYPASS", 64 | `ifdef vm3_rom 65 | altsyncram_component.init_file = `vm3_rom, 66 | `endif 67 | altsyncram_component.intended_device_family = "Cyclone IV E", 68 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 69 | altsyncram_component.lpm_type = "altsyncram", 70 | altsyncram_component.numwords_a = 4096, 71 | altsyncram_component.operation_mode = "ROM", 72 | altsyncram_component.outdata_aclr_a = "NONE", 73 | altsyncram_component.outdata_reg_a = "CLOCK0", 74 | altsyncram_component.widthad_a = 12, 75 | altsyncram_component.width_a = 16, 76 | altsyncram_component.width_byteena_a = 1; 77 | 78 | endmodule 79 | 80 | // ============================================================ 81 | // CNX file retrieval info 82 | // ============================================================ 83 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 84 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 85 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 86 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 87 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 88 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 89 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" 90 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 91 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 92 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 93 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 94 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 95 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 96 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 97 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 98 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 99 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 100 | // Retrieval info: PRIVATE: MIFfilename STRING "../../rom/134e.mif" 101 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 102 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 103 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 104 | // Retrieval info: PRIVATE: RegOutput NUMERIC "1" 105 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 106 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 107 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" 108 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 109 | // Retrieval info: PRIVATE: WidthData NUMERIC "16" 110 | // Retrieval info: PRIVATE: rden NUMERIC "0" 111 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 112 | // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" 113 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 114 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 115 | // Retrieval info: CONSTANT: INIT_FILE STRING "./rom/279.mif" 116 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 117 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" 118 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 119 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 120 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" 121 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 122 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" 123 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 124 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 125 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 126 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 127 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 128 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 129 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 130 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 131 | // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.v TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.inc FALSE 134 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.cmp FALSE 135 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134.bsf FALSE 136 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134_inst.v FALSE 137 | // Retrieval info: GEN_FILE: TYPE_NORMAL rom134_bb.v TRUE 138 | // Retrieval info: LIB_FILE: altera_mf 139 | -------------------------------------------------------------------------------- /board/QMTECH-E55/pinout.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/QMTECH-E55/pinout.ods -------------------------------------------------------------------------------- /board/QMTECH-E55/top.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition 21 | # Date created = 17:45:33 июня 20, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "17:45:33 июня 20, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "top" 31 | -------------------------------------------------------------------------------- /board/tang/Readme.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/tang/Readme.odt -------------------------------------------------------------------------------- /board/tang/Readme.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/tang/Readme.pdf -------------------------------------------------------------------------------- /board/tang/ip-components/pll.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PLL 5 | EG4S20BG256 6 | false 7 | 8 | 9 | Any 10 | 24.0000000000000000Mhz 11 | Normal 12 | CLKC4 13 | ENABLE 14 | ENABLE 15 | ENABLE 16 | ENABLE 17 | 18 | 19 | Medium 20 | 21 | 22 | parameters_setting 23 | 4 24 | 1 25 | 26 | 27 | 0 28 | 16 29 | 60.0000000000000000Mhz 30 | 0.0000000000000000deg 31 | 32 | 33 | 1 34 | 16 35 | 60.0000000000000000Mhz 36 | 180.0000000000000000deg 37 | 38 | 39 | 2 40 | 96 41 | 10.0000000000000000Mhz 42 | 0.0000000000000000deg 43 | 44 | 45 | 3 46 | 20 47 | 48.0000000000000000Mhz 48 | 0.0000000000000000deg 49 | 50 | 51 | 4 52 | 10 53 | 96.0000000000000000Mhz 54 | 0.0000000000000000deg 55 | 56 | 57 | 58 | 59 | -------------------------------------------------------------------------------- /board/tang/ip-components/pll.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/pll.v 8 | ** Date : 2021 03 19 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | /////////////////////////////////////////////////////////////////////////////// 13 | // Input frequency: 24.000Mhz 14 | // Clock multiplication factor: 4 15 | // Clock division factor: 1 16 | // Clock information: 17 | // Clock name | Frequency | Phase shift 18 | // C0 | 60.000000 MHZ | 0 DEG 19 | // C1 | 60.000000 MHZ | 180DEG 20 | // C2 | 10.000000 MHZ | 0 DEG 21 | // C3 | 48.000000 MHZ | 0 DEG 22 | // C4 | 96.000000 MHZ | 0 DEG 23 | /////////////////////////////////////////////////////////////////////////////// 24 | `timescale 1 ns / 100 fs 25 | 26 | module pll(refclk, 27 | reset, 28 | extlock, 29 | clk0_out, 30 | clk1_out, 31 | clk2_out, 32 | clk3_out, 33 | clk4_out); 34 | 35 | input refclk; 36 | input reset; 37 | output extlock; 38 | output clk0_out; 39 | output clk1_out; 40 | output clk2_out; 41 | output clk3_out; 42 | output clk4_out; 43 | 44 | wire clk4_buf; 45 | 46 | EG_LOGIC_BUFG bufg_feedback( .i(clk4_buf), .o(clk4_out) ); 47 | 48 | EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"), 49 | .DYNCFG("DISABLE"), 50 | .FIN("24.000"), 51 | .FEEDBK_MODE("NORMAL"), 52 | .FEEDBK_PATH("CLKC4_EXT"), 53 | .STDBY_ENABLE("DISABLE"), 54 | .PLLRST_ENA("ENABLE"), 55 | .SYNC_ENABLE("DISABLE"), 56 | .DERIVE_PLL_CLOCKS("ENABLE"), 57 | .GEN_BASIC_CLOCK("ENABLE"), 58 | .GMC_GAIN(2), 59 | .ICP_CURRENT(9), 60 | .KVCO(2), 61 | .LPF_CAPACITOR(1), 62 | .LPF_RESISTOR(8), 63 | .REFCLK_DIV(1), 64 | .FBCLK_DIV(4), 65 | 66 | // clk_p 67 | .CLKC0_ENABLE("ENABLE"), 68 | .CLKC0_DIV(`PLL_DIV), 69 | .CLKC0_CPHASE(15), 70 | .CLKC0_FPHASE(0), 71 | 72 | // sdram_clk 73 | .CLKC1_ENABLE("ENABLE"), 74 | .CLKC1_DIV(`PLL_DIV /2), 75 | .CLKC1_CPHASE(15), 76 | .CLKC1_FPHASE(0), 77 | 78 | // sdclock 79 | .CLKC2_ENABLE("ENABLE"), 80 | .CLKC2_DIV(`SD_DIV), 81 | .CLKC2_CPHASE(95), 82 | .CLKC2_FPHASE(0), 83 | 84 | // clk50 85 | .CLKC3_ENABLE("ENABLE"), 86 | .CLKC3_DIV(20), 87 | .CLKC3_CPHASE(19), 88 | .CLKC3_FPHASE(0), 89 | .CLKC4_ENABLE("ENABLE"), 90 | .CLKC4_DIV(10), 91 | .CLKC4_CPHASE(9), 92 | .CLKC4_FPHASE(0) ) 93 | pll_inst (.refclk(refclk), 94 | .reset(reset), 95 | .stdby(1'b0), 96 | .extlock(extlock), 97 | .psclk(1'b0), 98 | .psdown(1'b0), 99 | .psstep(1'b0), 100 | .psclksel(3'b000), 101 | .psdone(open), 102 | .dclk(1'b0), 103 | .dcs(1'b0), 104 | .dwe(1'b0), 105 | .di(8'b00000000), 106 | .daddr(6'b000000), 107 | .do({open, open, open, open, open, open, open, open}), 108 | .fbclk(clk4_out), 109 | .clkc({clk4_buf, clk3_out, clk2_out, clk1_out, clk0_out})); 110 | 111 | endmodule 112 | -------------------------------------------------------------------------------- /board/tang/ip-components/tang_bootrom.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module tang_bootrom ( doa, addra, clka, rsta ); 4 | 5 | output [15:0] doa; 6 | 7 | input [8:0] addra; 8 | input clka; 9 | input rsta; 10 | 11 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(16), 12 | .ADDR_WIDTH_A(9), 13 | .DATA_DEPTH_A(512), 14 | .DATA_WIDTH_B(16), 15 | .ADDR_WIDTH_B(9), 16 | .DATA_DEPTH_B(512), 17 | .MODE("SP"), 18 | .REGMODE_A("NOREG"), 19 | .RESETMODE("SYNC"), 20 | .IMPLEMENT("9K"), 21 | .DEBUGGABLE("NO"), 22 | .PACKABLE("NO"), 23 | .INIT_FILE("../../../rom/m9312/bootrom.mif"), 24 | .FILL_ALL("NONE")) 25 | inst( 26 | .dia({16{1'b0}}), 27 | .dib({16{1'b0}}), 28 | .addra(addra), 29 | .addrb({9{1'b0}}), 30 | .cea(1'b1), 31 | .ceb(1'b0), 32 | .ocea(1'b0), 33 | .oceb(1'b0), 34 | .clka(clka), 35 | .clkb(1'b0), 36 | .wea(1'b0), 37 | .web(1'b0), 38 | .bea(1'b0), 39 | .beb(1'b0), 40 | .rsta(rsta), 41 | .rstb(1'b0), 42 | .doa(doa), 43 | .dob()); 44 | 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /board/tang/ip-components/tang_fontrom.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | ROM 5 | EG4S20BG256 6 | false 7 | tang_fontrom 8 | false 9 | false 10 | 11 | 12 | 9k 13 | 14 | 15 | SP 16 | 17 | 18 | 32768 19 | 1 20 | None 21 | 22 | 23 | true 24 | ../../../ksm-firmware/font/font-main.mif 25 | 26 | 27 | NONE 28 | 29 | 30 | -------------------------------------------------------------------------------- /board/tang/ip-components/tang_fontrom.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_fontrom.v 8 | ** Date : 2021 03 17 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_fontrom ( doa, addra, clka, rsta ); 15 | 16 | output [0:0] doa; 17 | 18 | input [14:0] addra; 19 | input clka; 20 | input rsta; 21 | 22 | 23 | 24 | 25 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(1), 26 | .ADDR_WIDTH_A(15), 27 | .DATA_DEPTH_A(32768), 28 | .DATA_WIDTH_B(1), 29 | .ADDR_WIDTH_B(15), 30 | .DATA_DEPTH_B(32768), 31 | .MODE("SP"), 32 | .REGMODE_A("NOREG"), 33 | .RESETMODE("SYNC"), 34 | .IMPLEMENT("9K"), 35 | .DEBUGGABLE("NO"), 36 | .PACKABLE("NO"), 37 | .INIT_FILE(`fontrom_file), 38 | .FILL_ALL("NONE")) 39 | inst( 40 | .dia({1{1'b0}}), 41 | .dib({1{1'b0}}), 42 | .addra(addra), 43 | .addrb({15{1'b0}}), 44 | .cea(1'b1), 45 | .ceb(1'b0), 46 | .ocea(1'b0), 47 | .oceb(1'b0), 48 | .clka(clka), 49 | .clkb(1'b0), 50 | .wea(1'b0), 51 | .web(1'b0), 52 | .bea(1'b0), 53 | .beb(1'b0), 54 | .rsta(rsta), 55 | .rstb(1'b0), 56 | .doa(doa), 57 | .dob()); 58 | 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /board/tang/ip-components/tang_kgdvram.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | EG_LOGIC_BRAM 5 | EG4S20BG256 6 | false 7 | tang_kgdvram 8 | NO 9 | NO 10 | none 11 | 12 | 13 | 9k 14 | 15 | 16 | DP 17 | 18 | 19 | NORMAL 20 | 16384 21 | 8 22 | None 23 | disable 24 | 25 | 26 | NORMAL 27 | 131072 28 | 1 29 | None 30 | disable 31 | 32 | 33 | NONE 34 | 35 | 36 | -------------------------------------------------------------------------------- /board/tang/ip-components/tang_kgdvram.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_kgdvram.v 8 | ** Date : 2021 03 18 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_kgdvram ( 15 | doa, dia, addra, clka, wea, 16 | dob, dib, addrb, clkb, web 17 | ); 18 | 19 | output [7:0] doa; 20 | output [0:0] dob; 21 | 22 | 23 | input [7:0] dia; 24 | input [0:0] dib; 25 | input [13:0] addra; 26 | input [16:0] addrb; 27 | input wea; 28 | input web; 29 | input clka; 30 | input clkb; 31 | 32 | 33 | 34 | 35 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(8), 36 | .DATA_WIDTH_B(1), 37 | .ADDR_WIDTH_A(14), 38 | .ADDR_WIDTH_B(17), 39 | .DATA_DEPTH_A(16384), 40 | .DATA_DEPTH_B(131072), 41 | .MODE("DP"), 42 | .REGMODE_A("NOREG"), 43 | .REGMODE_B("NOREG"), 44 | .WRITEMODE_A("NORMAL"), 45 | .WRITEMODE_B("NORMAL"), 46 | .RESETMODE("SYNC"), 47 | .IMPLEMENT("9K"), 48 | .INIT_FILE("NONE"), 49 | .FILL_ALL("NONE")) 50 | inst( 51 | .dia(dia), 52 | .dib(dib), 53 | .addra(addra), 54 | .addrb(addrb), 55 | .cea(1'b1), 56 | .ceb(1'b1), 57 | .ocea(1'b0), 58 | .oceb(1'b0), 59 | .clka(clka), 60 | .clkb(clkb), 61 | .wea(wea), 62 | .web(web), 63 | .bea(1'b0), 64 | .beb(1'b0), 65 | .rsta(1'b0), 66 | .rstb(1'b0), 67 | .doa(doa), 68 | .dob(dob)); 69 | 70 | 71 | endmodule -------------------------------------------------------------------------------- /board/tang/ip-components/tang_rom000.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_rom000.v 8 | ** Date : 2021 03 18 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_rom000 ( doa, addra, clka, rsta ); 15 | 16 | output [15:0] doa; 17 | 18 | input [11:0] addra; 19 | input clka; 20 | input rsta; 21 | 22 | 23 | 24 | 25 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(16), 26 | .ADDR_WIDTH_A(12), 27 | .DATA_DEPTH_A(4096), 28 | .DATA_WIDTH_B(16), 29 | .ADDR_WIDTH_B(12), 30 | .DATA_DEPTH_B(4096), 31 | .MODE("SP"), 32 | .REGMODE_A("NOREG"), 33 | .RESETMODE("SYNC"), 34 | .IMPLEMENT("9K"), 35 | .DEBUGGABLE("NO"), 36 | .PACKABLE("NO"), 37 | .INIT_FILE("../../../rom/000.mif"), 38 | .FILL_ALL("NONE")) 39 | inst( 40 | .dia({16{1'b0}}), 41 | .dib({16{1'b0}}), 42 | .addra(addra), 43 | .addrb({12{1'b0}}), 44 | .cea(1'b1), 45 | .ceb(1'b0), 46 | .ocea(1'b0), 47 | .oceb(1'b0), 48 | .clka(clka), 49 | .clkb(1'b0), 50 | .wea(1'b0), 51 | .web(1'b0), 52 | .bea(1'b0), 53 | .beb(1'b0), 54 | .rsta(rsta), 55 | .rstb(1'b0), 56 | .doa(doa), 57 | .dob()); 58 | 59 | 60 | endmodule -------------------------------------------------------------------------------- /board/tang/ip-components/tang_rom055.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_rom055.v 8 | ** Date : 2021 03 13 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_rom055 ( doa, addra, clka, rsta ); 15 | 16 | output [15:0] doa; 17 | 18 | input [11:0] addra; 19 | input clka; 20 | input rsta; 21 | 22 | 23 | 24 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(16), 25 | .ADDR_WIDTH_A(12), 26 | .DATA_DEPTH_A(4096), 27 | .DATA_WIDTH_B(16), 28 | .ADDR_WIDTH_B(12), 29 | .DATA_DEPTH_B(4096), 30 | .MODE("SP"), 31 | .REGMODE_A("NOREG"), 32 | .RESETMODE("SYNC"), 33 | .IMPLEMENT("9K"), 34 | .DEBUGGABLE("NO"), 35 | .PACKABLE("NO"), 36 | .INIT_FILE(`mc1201_02_rom), 37 | .FILL_ALL("NONE")) 38 | inst( 39 | .dia({16{1'b0}}), 40 | .dib({16{1'b0}}), 41 | .addra(addra), 42 | .addrb({12{1'b0}}), 43 | .cea(1'b1), 44 | .ceb(1'b0), 45 | .ocea(1'b0), 46 | .oceb(1'b0), 47 | .clka(clka), 48 | .clkb(1'b0), 49 | .wea(1'b0), 50 | .web(1'b0), 51 | .bea(1'b0), 52 | .beb(1'b0), 53 | .rsta(rsta), 54 | .rstb(1'b0), 55 | .doa(doa), 56 | .dob()); 57 | 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /board/tang/ip-components/tang_rom134.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_rom000.v 8 | ** Date : 2021 03 18 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_rom134 ( doa, addra, clka, rsta ); 15 | 16 | output [15:0] doa; 17 | 18 | input [11:0] addra; 19 | input clka; 20 | input rsta; 21 | 22 | 23 | 24 | 25 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(16), 26 | .ADDR_WIDTH_A(12), 27 | .DATA_DEPTH_A(4096), 28 | .DATA_WIDTH_B(16), 29 | .ADDR_WIDTH_B(12), 30 | .DATA_DEPTH_B(4096), 31 | .MODE("SP"), 32 | .REGMODE_A("NOREG"), 33 | .RESETMODE("SYNC"), 34 | .IMPLEMENT("9K"), 35 | .DEBUGGABLE("NO"), 36 | .PACKABLE("NO"), 37 | `ifdef vm3_rom 38 | .INIT_FILE(`vm3_rom), 39 | `endif 40 | .FILL_ALL("NONE")) 41 | inst( 42 | .dia({16{1'b0}}), 43 | .dib({16{1'b0}}), 44 | .addra(addra), 45 | .addrb({12{1'b0}}), 46 | .cea(1'b1), 47 | .ceb(1'b0), 48 | .ocea(1'b0), 49 | .oceb(1'b0), 50 | .clka(clka), 51 | .clkb(1'b0), 52 | .wea(1'b0), 53 | .web(1'b0), 54 | .bea(1'b0), 55 | .beb(1'b0), 56 | .rsta(rsta), 57 | .rstb(1'b0), 58 | .doa(doa), 59 | .dob()); 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /board/tang/ip-components/tang_sectorbuf.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_sectorbuf.v 8 | ** Date : 2021 03 27 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_sectorbuf ( 15 | doa, dia, addra, clka, wea, 16 | dob, dib, addrb, clkb, web 17 | ); 18 | 19 | output [15:0] doa; 20 | output [15:0] dob; 21 | 22 | 23 | input [15:0] dia; 24 | input [15:0] dib; 25 | input [7:0] addra; 26 | input [7:0] addrb; 27 | input wea; 28 | input web; 29 | input clka; 30 | input clkb; 31 | 32 | 33 | 34 | 35 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(16), 36 | .DATA_WIDTH_B(16), 37 | .ADDR_WIDTH_A(8), 38 | .ADDR_WIDTH_B(8), 39 | .DATA_DEPTH_A(256), 40 | .DATA_DEPTH_B(256), 41 | .MODE("DP"), 42 | .REGMODE_A("NOREG"), 43 | .REGMODE_B("NOREG"), 44 | .WRITEMODE_A("NORMAL"), 45 | .WRITEMODE_B("NORMAL"), 46 | .RESETMODE("SYNC"), 47 | .IMPLEMENT("9K"), 48 | .INIT_FILE("NONE"), 49 | .FILL_ALL("NONE")) 50 | inst( 51 | .dia(dia), 52 | .dib(dib), 53 | .addra(addra), 54 | .addrb(addrb), 55 | .cea(1'b1), 56 | .ceb(1'b1), 57 | .ocea(1'b0), 58 | .oceb(1'b0), 59 | .clka(clka), 60 | .clkb(clkb), 61 | .wea(wea), 62 | .web(web), 63 | .bea(1'b0), 64 | .beb(1'b0), 65 | .rsta(1'b0), 66 | .rstb(1'b0), 67 | .doa(doa), 68 | .dob(dob)); 69 | 70 | 71 | endmodule -------------------------------------------------------------------------------- /board/tang/ip-components/tang_user_rom.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_user_rom.v 8 | ** Date : 2021 03 19 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_user_rom ( doa, addra, clka, rsta ); 15 | 16 | output [15:0] doa; 17 | 18 | input [11:0] addra; 19 | input clka; 20 | input rsta; 21 | 22 | 23 | 24 | 25 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(16), 26 | .ADDR_WIDTH_A(12), 27 | .DATA_DEPTH_A(4096), 28 | .DATA_WIDTH_B(16), 29 | .ADDR_WIDTH_B(12), 30 | .DATA_DEPTH_B(4096), 31 | .MODE("SP"), 32 | .REGMODE_A("NOREG"), 33 | .RESETMODE("SYNC"), 34 | .IMPLEMENT("9K"), 35 | .DEBUGGABLE("NO"), 36 | .PACKABLE("NO"), 37 | .INIT_FILE(`userrom), 38 | .FILL_ALL("NONE")) 39 | inst( 40 | .dia({16{1'b0}}), 41 | .dib({16{1'b0}}), 42 | .addra(addra), 43 | .addrb({12{1'b0}}), 44 | .cea(1'b1), 45 | .ceb(1'b0), 46 | .ocea(1'b0), 47 | .oceb(1'b0), 48 | .clka(clka), 49 | .clkb(1'b0), 50 | .wea(1'b0), 51 | .web(1'b0), 52 | .bea(1'b0), 53 | .beb(1'b0), 54 | .rsta(rsta), 55 | .rstb(1'b0), 56 | .doa(doa), 57 | .dob()); 58 | 59 | 60 | endmodule -------------------------------------------------------------------------------- /board/tang/ip-components/tang_vm1_vcram.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_vm1_vcram.v 8 | ** Date : 2021 03 18 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_vm1_vcram ( 15 | doa, dia, addra, clka, wea, 16 | dob, dib, addrb, clkb, web 17 | ); 18 | 19 | output [15:0] doa; 20 | output [15:0] dob; 21 | 22 | 23 | input [15:0] dia; 24 | input [15:0] dib; 25 | input [5:0] addra; 26 | input [5:0] addrb; 27 | input [1:0] wea; 28 | input [1:0] web; 29 | input clka; 30 | input clkb; 31 | 32 | 33 | 34 | 35 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(16), 36 | .DATA_WIDTH_B(16), 37 | .ADDR_WIDTH_A(6), 38 | .ADDR_WIDTH_B(6), 39 | .DATA_DEPTH_A(64), 40 | .DATA_DEPTH_B(64), 41 | .BYTE_ENABLE(8), 42 | .BYTE_A(2), 43 | .BYTE_B(2), 44 | .MODE("DP"), 45 | .REGMODE_A("NOREG"), 46 | .REGMODE_B("NOREG"), 47 | .WRITEMODE_A("NORMAL"), 48 | .WRITEMODE_B("NORMAL"), 49 | .RESETMODE("SYNC"), 50 | .IMPLEMENT("9K"), 51 | .INIT_FILE("../ram/vm1_vcram.mif"), 52 | .FILL_ALL("NONE")) 53 | inst( 54 | .dia(dia), 55 | .dib(dib), 56 | .addra(addra), 57 | .addrb(addrb), 58 | .cea(1'b1), 59 | .ceb(1'b1), 60 | .ocea(1'b0), 61 | .oceb(1'b0), 62 | .clka(clka), 63 | .clkb(clkb), 64 | .wea(1'b0), 65 | .bea(wea), 66 | .web(1'b0), 67 | .beb(web), 68 | .rsta(1'b0), 69 | .rstb(1'b0), 70 | .doa(doa), 71 | .dob(dob)); 72 | 73 | 74 | endmodule -------------------------------------------------------------------------------- /board/tang/ip-components/tang_vtmem.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | EG_LOGIC_BRAM 5 | EG4S20BG256 6 | false 7 | tang_vtmem 8 | NO 9 | NO 10 | 8 11 | 12 | 13 | 9k 14 | 15 | 16 | SP 17 | 18 | 19 | NORMAL 20 | 2048 21 | 16 22 | None 23 | disable 24 | 25 | 26 | ../../../ksm-firmware/ksm-firmware.mif 27 | 28 | 29 | NONE 30 | 31 | 32 | -------------------------------------------------------------------------------- /board/tang/ip-components/tang_vtmem.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2011-2021 Anlogic, Inc. 3 | ** All Right Reserved. 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : /home/forth32/dvk-fpga/board/tang/ip-components/tang_vtmem.v 8 | ** Date : 2021 03 17 9 | ** TD version : 4.6.18154 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module tang_vtmem ( doa, dia, addra, clka, wea ); 15 | 16 | output [15:0] doa; 17 | 18 | input [15:0] dia; 19 | input [10:0] addra; 20 | input [1:0] wea; 21 | input clka; 22 | 23 | 24 | 25 | EG_LOGIC_BRAM #( .DATA_WIDTH_A(16), 26 | .ADDR_WIDTH_A(11), 27 | .DATA_DEPTH_A(2048), 28 | .DATA_WIDTH_B(16), 29 | .ADDR_WIDTH_B(11), 30 | .DATA_DEPTH_B(2048), 31 | .BYTE_ENABLE(8), 32 | .BYTE_A(2), 33 | .BYTE_B(2), 34 | .MODE("SP"), 35 | .REGMODE_A("NOREG"), 36 | .WRITEMODE_A("NORMAL"), 37 | .RESETMODE("SYNC"), 38 | .IMPLEMENT("9K"), 39 | .DEBUGGABLE("NO"), 40 | .PACKABLE("NO"), 41 | .INIT_FILE("../../../ksm-firmware/ksm-firmware.mif"), 42 | .FILL_ALL("NONE")) 43 | inst( 44 | .dia(dia), 45 | .dib({16{1'b0}}), 46 | .addra(addra), 47 | .addrb({11{1'b0}}), 48 | .cea(1'b1), 49 | .ceb(1'b0), 50 | .ocea(1'b0), 51 | .oceb(1'b0), 52 | .clka(clka), 53 | .clkb(1'b0), 54 | .wea(1'b0), 55 | .bea(wea), 56 | .web(1'b0), 57 | .rsta(1'b0), 58 | .rstb(1'b0), 59 | .doa(doa), 60 | .dob()); 61 | 62 | 63 | endmodule -------------------------------------------------------------------------------- /board/tang/memory_adapter.v: -------------------------------------------------------------------------------- 1 | // 2 | // Этот файл - набор интерфейсных модулей для адаптации TANG IP-компонентов к стандарту Altera. 3 | // Модули являются переходниками к мегафункциям tang-среды. 4 | // 5 | 6 | //********************************************************* 7 | //* Теневое ПЗУ платы МС1201.03/04 8 | //********************************************************* 9 | module rom134( 10 | input [11:0] address, 11 | input clock, 12 | output [15:0] q 13 | ); 14 | 15 | tang_rom134 rom( 16 | .addra(address), 17 | .doa(q), 18 | .clka(clock), 19 | .rsta(1'b0) 20 | ); 21 | 22 | endmodule 23 | 24 | //********************************************************* 25 | //* Теневое ПЗУ платы МС1201.02 26 | //********************************************************* 27 | module rom055( 28 | input [11:0] address, 29 | input clock, 30 | output [15:0] q 31 | ); 32 | 33 | tang_rom055 rom( 34 | .addra(address), 35 | .doa(q), 36 | .clka(clock), 37 | .rsta(1'b0) 38 | ); 39 | 40 | endmodule 41 | 42 | //********************************************************* 43 | //* Теневое ПЗУ платы МС1201.01 44 | //********************************************************* 45 | module rom000( 46 | input [11:0] address, 47 | input clock, 48 | output [15:0] q 49 | ); 50 | 51 | tang_rom000 rom( 52 | .addra(address), 53 | .doa(q), 54 | .clka(clock), 55 | .rsta(1'b0) 56 | ); 57 | 58 | endmodule 59 | 60 | 61 | //********************************************************* 62 | //* ОЗУ контроллера КСМ с управляющей микропрограммой 63 | //********************************************************* 64 | module vtmem ( 65 | input [10:0] address, 66 | input [1:0] byteena, 67 | input clock, 68 | input [15:0] data, 69 | input rden, 70 | input wren, 71 | output [15:0] q 72 | ); 73 | 74 | wire [1:0] writeenable; 75 | assign writeenable[0]=wren & byteena[0]; 76 | assign writeenable[1]=wren & byteena[1]; 77 | 78 | tang_vtmem vram( 79 | .doa(q), 80 | .dia(data), 81 | .addra(address), 82 | .wea(writeenable), 83 | .clka(clock) 84 | ); 85 | 86 | endmodule 87 | 88 | //********************************************************* 89 | //* ПЗУ знакогенератора со шрифтами 90 | //********************************************************* 91 | module fontrom( 92 | input [14:0] address, 93 | input clock, 94 | output q 95 | ); 96 | 97 | tang_fontrom rom( 98 | .addra(address), 99 | .doa(q), 100 | .clka(clock), 101 | .rsta(1'b0) 102 | ); 103 | 104 | endmodule 105 | 106 | 107 | 108 | //********************************************************* 109 | //* Двухпортовое ОЗУ графической подсистемы КГД 110 | //********************************************************* 111 | module kgdvram ( 112 | input [13:0] address_a, 113 | input [16:0] address_b, 114 | input clock_a, 115 | input clock_b, 116 | input [7:0] data_a, 117 | input [0:0] data_b, 118 | input wren_a, 119 | input wren_b, 120 | output [7:0] q_a, 121 | output [0:0] q_b 122 | ); 123 | 124 | 125 | tang_kgdvram vram( 126 | .doa(q_a), 127 | .dob(q_b), 128 | .dia(data_a), 129 | .dib(data_b), 130 | .addra(address_a), 131 | .addrb(address_b), 132 | .wea(wren_a), 133 | .web(wren_b), 134 | .clka(clock_a), 135 | .clkb(clock_b) 136 | ); 137 | 138 | endmodule 139 | 140 | //********************************************************* 141 | //* Регистровый файл процессора 1801ВМ1 142 | //********************************************************* 143 | module vm1_vcram ( 144 | input [5:0] address_a, 145 | input [5:0] address_b, 146 | input [1:0] byteena_a, 147 | input clock, 148 | input [15:0] data_a, 149 | input [15:0] data_b, 150 | input wren_a, 151 | input wren_b, 152 | output [15:0] q_a, 153 | output [15:0] q_b 154 | ); 155 | wire [1:0] wea; 156 | wire [1:0] web; 157 | 158 | assign wea[0] = wren_a & byteena_a[0]; 159 | assign wea[1] = wren_a & byteena_a[1]; 160 | 161 | assign web[0] = wren_b; 162 | assign web[1] = wren_b; 163 | 164 | 165 | tang_vm1_vcram vcram( 166 | .clka(clock), 167 | .clkb(clock), 168 | .wea(wea), 169 | .addra(address_a), 170 | .dia(data_a), 171 | .web(web), 172 | .addrb(address_b), 173 | .dib(data_b), 174 | .doa(q_a), 175 | .dob(q_b) 176 | ); 177 | 178 | endmodule 179 | 180 | //********************************************************* 181 | //* ПЗУ пользователя 140000-157777 для всех плат 182 | //********************************************************* 183 | module user_rom( 184 | input [11:0] address, 185 | input clock, 186 | output [15:0] q 187 | ); 188 | 189 | tang_user_rom rom( 190 | .addra(address), 191 | .doa(q), 192 | .clka(clock), 193 | .rsta(1'b0) 194 | ); 195 | 196 | endmodule 197 | 198 | //********************************************************* 199 | //* ПЗУ эмулятора пульта-загрузчика М9312 200 | //********************************************************* 201 | module boot_rom( 202 | input [8:0] address, 203 | input clock, 204 | output [15:0] q 205 | ); 206 | 207 | tang_bootrom brom( 208 | .addra(address), 209 | .doa(q), 210 | .clka(clock), 211 | .rsta(1'b0) 212 | ); 213 | 214 | endmodule 215 | 216 | 217 | //********************************************************* 218 | //* Буфер сектора для модуля sdspi 219 | //********************************************************* 220 | module sectorbuf ( 221 | input [7:0] address_a, 222 | input [7:0] address_b, 223 | input clock_a, 224 | input clock_b, 225 | input [15:0] data_a, 226 | input [15:0] data_b, 227 | input wren_a, 228 | input wren_b, 229 | output [15:0] q_a, 230 | output [15:0] q_b 231 | ); 232 | 233 | tang_sectorbuf sbuf( 234 | .doa(q_a), 235 | .dob(q_b), 236 | .dia(data_a), 237 | .dib(data_b), 238 | .addra(address_a), 239 | .addrb(address_b), 240 | .wea(wren_a), 241 | .web(wren_b), 242 | .clka(clock_a), 243 | .clkb(clock_b) 244 | ); 245 | 246 | endmodule 247 | -------------------------------------------------------------------------------- /board/tang/pict/ioboard-rs232.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/tang/pict/ioboard-rs232.png -------------------------------------------------------------------------------- /board/tang/pict/ioboardb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/tang/pict/ioboardb.png -------------------------------------------------------------------------------- /board/tang/pict/ioboards.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/tang/pict/ioboards.png -------------------------------------------------------------------------------- /board/tang/pict/tang.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/tang/pict/tang.jpg -------------------------------------------------------------------------------- /board/tang/pinout.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/tang/pinout.ods -------------------------------------------------------------------------------- /board/tang/ram/vm1_vcram.mif: -------------------------------------------------------------------------------- 1 | -- 2 | -- Initialization data for Register File and Constant/Vector Generator RAM block 3 | -- 4 | 5 | WIDTH=16; 6 | DEPTH=64; 7 | 8 | ADDRESS_RADIX=OCT; 9 | DATA_RADIX=OCT; 10 | 11 | CONTENT BEGIN 12 | 000 : 000000; 13 | 001 : 000000; 14 | 002 : 000000; 15 | 003 : 000000; 16 | 004 : 000000; 17 | 005 : 000000; 18 | 006 : 000000; 19 | 007 : 000000; 20 | 010 : 000000; 21 | 011 : 000000; 22 | 012 : 000000; 23 | 013 : 000000; 24 | 014 : 000000; 25 | 015 : 000000; 26 | 016 : 000000; 27 | 017 : 000000; 28 | 020 : 160006; 29 | 021 : 000020; 30 | 022 : 000010; 31 | 023 : 000014; 32 | 024 : 000004; 33 | 025 : 177716; 34 | 026 : 000030; 35 | 027 : 160012; 36 | 030 : 000270; 37 | 031 : 000024; 38 | 032 : 000100; 39 | 033 : 160002; 40 | 034 : 000034; 41 | 035 : 000000; 42 | 036 : 000000; 43 | 037 : 000000; 44 | 040 : 000000; 45 | 041 : 000340; 46 | 042 : 000000; 47 | 043 : 000002; 48 | 044 : 000000; 49 | 045 : 177716; 50 | 046 : 177777; 51 | 047 : 000001; 52 | 050 : 000000; 53 | 051 : 100000; 54 | 052 : 177676; 55 | 053 : 000020; 56 | 054 : 000000; 57 | 055 : 177400; 58 | 056 : 000010; 59 | 057 : 000000; 60 | 060 : 000000; 61 | 061 : 000000; 62 | 062 : 000000; 63 | 063 : 000000; 64 | 064 : 000000; 65 | 065 : 000000; 66 | 066 : 000000; 67 | 067 : 000000; 68 | 070 : 000000; 69 | 071 : 000000; 70 | 072 : 000000; 71 | 073 : 000000; 72 | 074 : 000000; 73 | 075 : 000000; 74 | 076 : 000000; 75 | 077 : 000000; 76 | END; 77 | -------------------------------------------------------------------------------- /board/tang/sipeed-tang-primer-pins.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/board/tang/sipeed-tang-primer-pins.pdf -------------------------------------------------------------------------------- /board/tang/top.adc: -------------------------------------------------------------------------------- 1 | set_pin_assignment { button[0] } { LOCATION = B10; IOSTANDARD = LVTTL33; } 2 | set_pin_assignment { button[1] } { LOCATION = B15; IOSTANDARD = LVTTL33; } 3 | set_pin_assignment { button[2] } { LOCATION = E16; IOSTANDARD = LVTTL33; } 4 | set_pin_assignment { button[3] } { LOCATION = J11; IOSTANDARD = LVTTL33; } 5 | set_pin_assignment { clk24 } { LOCATION = K14; IOSTANDARD = LVTTL33; } 6 | set_pin_assignment { irps_rxd } { LOCATION = H13; IOSTANDARD = LVTTL33; } 7 | set_pin_assignment { irps_txd } { LOCATION = J13; IOSTANDARD = LVTTL33; } 8 | set_pin_assignment { led[0] } { LOCATION = R2; IOSTANDARD = LVTTL33; } 9 | set_pin_assignment { led[1] } { LOCATION = P2; IOSTANDARD = LVTTL33; } 10 | set_pin_assignment { led[2] } { LOCATION = N5; IOSTANDARD = LVTTL33; } 11 | set_pin_assignment { led[3] } { LOCATION = C9; IOSTANDARD = LVTTL33; } 12 | set_pin_assignment { led[4] } { LOCATION = L12; IOSTANDARD = LVTTL33; } 13 | set_pin_assignment { ps2_clk } { LOCATION = T7; IOSTANDARD = LVTTL33; } 14 | set_pin_assignment { ps2_data } { LOCATION = R7; IOSTANDARD = LVTTL33; } 15 | set_pin_assignment { sdcard_cs } { LOCATION = N14; IOSTANDARD = LVTTL33; } 16 | set_pin_assignment { sdcard_miso } { LOCATION = F13; IOSTANDARD = LVTTL33; } 17 | set_pin_assignment { sdcard_mosi } { LOCATION = H14; IOSTANDARD = LVTTL33; } 18 | set_pin_assignment { sdcard_sclk } { LOCATION = M9; IOSTANDARD = LVTTL33; } 19 | set_pin_assignment { sw[0] } { LOCATION = A4; IOSTANDARD = LVTTL33; } 20 | set_pin_assignment { sw[1] } { LOCATION = A3; IOSTANDARD = LVTTL33; } 21 | set_pin_assignment { sw[2] } { LOCATION = C5; IOSTANDARD = LVTTL33; } 22 | set_pin_assignment { sw[3] } { LOCATION = B6; IOSTANDARD = LVTTL33; } 23 | set_pin_assignment { vgab } { LOCATION = N12; IOSTANDARD = LVTTL33; } 24 | set_pin_assignment { vgag } { LOCATION = R16; IOSTANDARD = LVTTL33; } 25 | set_pin_assignment { vgah } { LOCATION = P12; IOSTANDARD = LVTTL33; } 26 | set_pin_assignment { vgar } { LOCATION = M12; IOSTANDARD = LVTTL33; } 27 | set_pin_assignment { vgav } { LOCATION = N11; IOSTANDARD = LVTTL33; } 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /board/tang/top.al: -------------------------------------------------------------------------------- 1 | 2 | 3 | 2021-03-10 07:42:39 4 | 4.6.18154 5 | 11000010 6 | top 7 | 8 | EG4 9 | EG4S20BG256 10 | 11 | 12 | 13 | tang.v 14 | config.v 15 | ../../hdl/dw.v 16 | ../../hdl/fdd-my.v 17 | ../../hdl/irpr-centronix.v 18 | ../../hdl/kgd-graphics.v 19 | ../../hdl/mc1201-01.v 20 | ../../hdl/mc1201-02.v 21 | ../../hdl/mc1260.v 22 | ../../hdl/mc1280.v 23 | ../../hdl/rk11.v 24 | ../../hdl/rx01.v 25 | ../../hdl/sdspi.v 26 | ../../hdl/wbc_rst.v 27 | ../../hdl/wbc_uart.v 28 | ../../hdl/wbc_vic.v 29 | ../../hdl/vm2/vm2_plm.v 30 | ../../hdl/vm2/vm2_wb.v 31 | ../../hdl/ksm/ksm.v 32 | ../../hdl/ksm/ksm_vic.v 33 | ../../hdl/ksm/ps2.v 34 | ../../hdl/ksm/vga.v 35 | ../../hdl/ksm/vregs.v 36 | ../../hdl/ksm/vtram.v 37 | ../../hdl/ksm/vtreset.v 38 | ip-components/pll.v 39 | ip-components/tang_rom055.v 40 | memory_adapter.v 41 | ../../hdl/sdram_ip/sdram_cmd.v 42 | ../../hdl/sdram_ip/sdram_ctrl.v 43 | ../../hdl/sdram_ip/sdram_para.v 44 | ../../hdl/sdram_ip/sdram_top.v 45 | ../../hdl/sdram_ip/sdram_wr_data.v 46 | ip-components/tang_vtmem.v 47 | ip-components/tang_fontrom.v 48 | ip-components/tang_kgdvram.v 49 | ../../hdl/vm1/vm1_wb.v 50 | ../../hdl/vm1/vm1_tve.v 51 | ../../hdl/vm1/vm1_plm.v 52 | ip-components/tang_rom000.v 53 | ip-components/tang_vm1_vcram.v 54 | ../../hdl/m2/lsi_wb.v 55 | ../../hdl/m2/mcp_plm.v 56 | ../../hdl/m2/mcp1611.v 57 | ../../hdl/m2/mcp1621.v 58 | ../../hdl/m2/mcp1631.v 59 | ../../hdl/m4/am4_alu.v 60 | ../../hdl/m4/am4_mcrom.v 61 | ../../hdl/m4/am4_plm.v 62 | ../../hdl/m4/am4_seq.v 63 | ../../hdl/m4/am4_wb.v 64 | ip-components/tang_user_rom.v 65 | ip-components/tang_sectorbuf.v 66 | ip-components/tang_bootrom.v 67 | ../../hdl/rk611.v 68 | ../../hdl/topboard16.v 69 | ../../hdl/topboard22.v 70 | ../../hdl/pdp2011.v 71 | ../../hdl/pdp2011/cpu_control_regs.v 72 | ../../hdl/pdp2011/cpuregs.v 73 | ../../hdl/pdp2011/fpuregs.v 74 | ../../hdl/pdp2011/mmu.v 75 | ../../hdl/pdp2011/wb_cpu2011.v 76 | ../../hdl/rh70.v 77 | ip-components/tang_rom134.v 78 | ../../hdl/vm3/vm3_mmu.v 79 | ../../hdl/vm3/vm3_plm.v 80 | ../../hdl/vm3/vm3_wb.v 81 | ../../hdl/mc1201-04.v 82 | ../../hdl/common-config.v 83 | 84 | top.adc 85 | top.sdc 86 | 87 | 88 | 89 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 2025-01-27 21:37:38 100 | 60 101 | true 102 | 103 | 104 | -------------------------------------------------------------------------------- /board/tang/top.sdc: -------------------------------------------------------------------------------- 1 | # This file is generated by Anlogic Timing Wizard. 22 03 2021 2 | 3 | #Created Clock 4 | create_clock -name clk24 -period 41.667 -waveform { 0.000 20.834 } [get_ports {clk24}] 5 | 6 | #Derive PLL Clocks 7 | derive_pll_clocks -gen_basic_clock 8 | 9 | #Set False Path 10 | set_false_path -through [get_nets {kernel/reset/key_down}] 11 | set_false_path -through [get_nets {kernel/reset/pwr_event}] 12 | 13 | -------------------------------------------------------------------------------- /disk/Makefile: -------------------------------------------------------------------------------- 1 | all: sd-extract sd-store 2 | sd-extract: sd-extract.c 3 | sd-store: sd-store.c 4 | -------------------------------------------------------------------------------- /disk/devtable.h: -------------------------------------------------------------------------------- 1 | // Размер одного полного банка в блоках 2 | #define banksize 0x400000 3 | 4 | struct devtable_t{ 5 | char* name; // имя устройства 6 | uint32_t doffset; // смещение от начала банка 7 | uint32_t usize; // размер одного диска на карте (с учетом округления) 8 | uint32_t realsize;// реальный размер дискового контейнера 9 | uint32_t maxdev; // максимальный номер устройства данного типа 10 | }; 11 | 12 | // Описатель структуры дискового банка 13 | struct devtable_t devtable[] = { 14 | // name offset usize realsize ndev 15 | //----------------------------------------- 16 | {"RK", 0, 6144, 6144, 7}, 17 | {"DK", 0, 6144, 6144, 7}, 18 | {"DW", 0xc000, 131072, 131072, 0}, 19 | {"DX", 0x2c000, 4096, 502, 1}, 20 | {"MY", 0x2e000, 2048, 1600, 3}, 21 | {"DB", 0x30000, 393216, 393216, 7}, 22 | {"DM", 0x330000, 65536, 53790, 7}, 23 | {0} 24 | }; 25 | -------------------------------------------------------------------------------- /disk/initdisk.7z: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/disk/initdisk.7z -------------------------------------------------------------------------------- /disk/sd-extract: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/disk/sd-extract -------------------------------------------------------------------------------- /disk/sd-extract.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include "devtable.h" 7 | 8 | void main(int argc, char* argv[]) { 9 | 10 | 11 | FILE* card; 12 | FILE* out; 13 | 14 | char devname[100]; 15 | char* buf; 16 | char* outbuf; 17 | int bank=0,unit=0; 18 | char filename[100]; 19 | int id; 20 | int i; 21 | uint32_t boffset, doffset, usize, cardoffset, realsize; 22 | char DD[4]; 23 | int cyl; 24 | int sec; 25 | int adr; 26 | int outpos=0; 27 | 28 | if (argc < 3) { 29 | printf("Извлечение образа диска с SD-карты\n\ 30 | Формат командной строки:\n\ 31 | %s DEV TYPE [unit [bank [file]]]\n\n\ 32 | DEV - имя устройства Sd-карты, например /dev/sdd\n\ 33 | TYPE - тип диска, RK, DW, DX, MY\n\ 34 | unit - номер устройства для многодисковых устройств, по умолчанию 0\n\ 35 | bank - номер банка дисков, по умолчанию 0\n\ 36 | file - имя файла для записи извлекаемого образа, по умолчанию B#-DD#.DSK\n\n\ 37 | Пример: %s /dev/sdc RK 2 1 - извлечение образа RK2: из банка 1\n\n",argv[0],argv[0]); 38 | return; 39 | } 40 | 41 | DD[0]=toupper((argv[2][0])); 42 | DD[1]=toupper((argv[2][1])); 43 | DD[3]=0; 44 | 45 | // поиск устройства 46 | for(id=0;;id++) { 47 | if (devtable[id].name == 0) { 48 | printf("Неверный тип устройства - %s\n",DD); 49 | return; 50 | } 51 | if (strncmp(DD,devtable[id].name,2) == 0) { 52 | doffset=devtable[id].doffset; 53 | usize=devtable[id].usize; 54 | realsize=devtable[id].realsize; 55 | break; 56 | } 57 | } 58 | if (argc>3) unit=atoi(argv[3]); 59 | if (argc>4) bank=atoi(argv[4]); 60 | if (argc>5) strcpy(filename,argv[5]); 61 | else sprintf(filename,"B%i-%s%i.dsk",bank,devtable[id].name,unit); 62 | 63 | if (unit > devtable[id].maxdev) { 64 | printf("Недопустимый номер устройства - %i, максимально допустимый = %i",unit, devtable[id].maxdev); 65 | return; 66 | } 67 | 68 | out=fopen(filename,"w"); 69 | if (out == 0) { 70 | printf("- ошибка открытия выходного файла %s\n",filename); 71 | return; 72 | } 73 | card=fopen(argv[1],"r"); 74 | if (card == 0) { 75 | printf("- ошибка открытия SD-карты %s\n",argv[1]); 76 | return; 77 | } 78 | 79 | buf=malloc(usize*512); 80 | if (buf == 0) { 81 | printf("- недостаточно памяти под буфер\n"); 82 | return; 83 | } 84 | 85 | cardoffset=bank*banksize+doffset+unit*usize; 86 | printf("* Стартовый блок: %xh\n",cardoffset); 87 | printf("* Размер образа : %xh\n",usize); 88 | // вычитываем образ диска с карты 89 | fseek(card,(cardoffset)*512,SEEK_SET); 90 | fread(buf,512,usize,card); 91 | fclose(card); 92 | 93 | // Для дисков DX - делаем преобразование буфера 94 | if (strncmp(DD,"DX",2) == 0) { 95 | outbuf=malloc(502*512); 96 | if (outbuf == 0) { 97 | printf("- недостаточно памяти под буфер\n"); 98 | return; 99 | } 100 | for (cyl=0;cyl<77;cyl++) { 101 | for(sec=1;sec<27;sec++) { 102 | adr=((cyl<<5) + sec)*512; 103 | for(i=0;i<256;i+=2) outbuf[outpos++]=*(buf+adr+i); 104 | } 105 | } 106 | 107 | free(buf); 108 | buf=outbuf; // заменяем исходный буфер на преобразованный 109 | } 110 | 111 | // записываем образ диска в выходной файл 112 | fwrite(buf,512,realsize,out); 113 | fclose(out); 114 | free(buf); 115 | } 116 | 117 | -------------------------------------------------------------------------------- /disk/sd-store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/disk/sd-store -------------------------------------------------------------------------------- /disk/sd-store.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include "devtable.h" 7 | 8 | void main(int argc, char* argv[]) { 9 | 10 | 11 | FILE* card; 12 | FILE* in; 13 | 14 | char devname[100]; 15 | char* buf; 16 | int bank=0,unit=0; 17 | char filename[100]; 18 | int id; 19 | int i; 20 | uint32_t boffset, doffset, usize, cardoffset, realsize; 21 | char DD[4]; 22 | char* outbuf; 23 | int cyl; 24 | int sec; 25 | int adr; 26 | int pblock=0; 27 | 28 | if (argc < 5) { 29 | printf("Запись образа диска на SD-карту\n\ 30 | Формат командной строки:\n\ 31 | %s DEV TYPE unit bank [file]\n\n\ 32 | DEV - имя устройства SD-карты, например /dev/sdd\n\ 33 | TYPE - тип диска, RK, DW, DX, MY\n\ 34 | unit - номер устройства для многодисковых устройств (для однодисковых - 0)\n\ 35 | bank - номер банка дисков\n\ 36 | file - имя файла для записи извлекаемого образа, по умолчанию B#-DD#.DSK\n\n\ 37 | Пример: %s /dev/sdc RK 2 1 rt11.dsk - запись образа RK2: в банк 1\n\n",argv[0],argv[0]); 38 | return; 39 | } 40 | 41 | DD[0]=toupper((argv[2][0])); 42 | DD[1]=toupper((argv[2][1])); 43 | DD[3]=0; 44 | 45 | // поиск устройства 46 | for(id=0;;id++) { 47 | if (devtable[id].name == 0) { 48 | printf("Неверный тип устройства - %s",DD); 49 | return; 50 | } 51 | if (strncmp(DD,devtable[id].name,2) == 0) { 52 | doffset=devtable[id].doffset; 53 | usize=devtable[id].usize; 54 | realsize=devtable[id].realsize; 55 | break; 56 | } 57 | } 58 | unit=atoi(argv[3]); 59 | bank=atoi(argv[4]); 60 | if (argc>5) strcpy(filename,argv[5]); 61 | else sprintf(filename,"B%i-%s%i.dsk",bank,devtable[id].name,unit); 62 | 63 | if (unit > devtable[id].maxdev) { 64 | printf("Недопустимый номер устройства - %i, максимально допустимый = %i",unit, devtable[id].maxdev); 65 | return; 66 | } 67 | 68 | in=fopen(filename,"r"); 69 | if (in == 0) { 70 | printf("- ошибка открытия входного файла %s\n",filename); 71 | return; 72 | } 73 | card=fopen(argv[1],"r+"); 74 | if (card == 0) { 75 | printf("- ошибка открытия SD-карты %s\n",argv[1]); 76 | return; 77 | } 78 | 79 | buf=malloc(usize*512); 80 | if (buf == 0) { 81 | printf("- недостаточно памяти под буфер\n"); 82 | return; 83 | } 84 | memset(buf,0,usize*512); 85 | fread(buf,512,realsize,in); 86 | if (strncmp(DD,"DX",2) == 0) { 87 | // преобразование буфера для DX-дисков 88 | outbuf=malloc(usize*512); 89 | memset(outbuf,0,usize*512); 90 | if (outbuf == 0) { 91 | printf("- недостаточно памяти под буфер\n"); 92 | return; 93 | } 94 | memset(outbuf,0,usize*512); 95 | for (cyl=0;cyl<77;cyl++) { 96 | for(sec=1;sec<27;sec++) { 97 | adr=((cyl<<5) + sec)*512; 98 | for(i=0;i<128;i++) *(outbuf+adr+i*2)=buf[pblock+i]; 99 | pblock+=128; 100 | } 101 | } 102 | free(buf); 103 | buf=outbuf; // подставляем преобразованный буфер на место исходного 104 | } 105 | fclose(in); 106 | 107 | // Запись образа на карту 108 | cardoffset=bank*banksize+doffset+unit*usize; 109 | printf("* Стартовый блок: %xh Размер: %xh\n",cardoffset,usize); 110 | fseek(card,(cardoffset)*512,SEEK_SET); 111 | fwrite(buf,512,usize,card); 112 | fclose(card); 113 | free(buf); 114 | } 115 | -------------------------------------------------------------------------------- /doc/377.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/doc/377.pdf -------------------------------------------------------------------------------- /doc/build-own-modules.odt: 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-------------------------------------------------------------------------------- /doc/vm3.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/doc/vm3.odt -------------------------------------------------------------------------------- /doc/vm3.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/doc/vm3.pdf -------------------------------------------------------------------------------- /hdl/common-config.v: -------------------------------------------------------------------------------- 1 | // 2 | // Вспомогательные определения, общие для всех отладочных плат 3 | // Этот файл подключается в конце файла config.v, уникального для каждой платы 4 | //------------------------------------------------------------------------------------------------------------------------ 5 | 6 | // тактовая частота процессора в герцах 7 | `define clkref 50000000/`PLL_DIV*`PLL_MUL 8 | 9 | // Определение типа модуля соединительной платы-корзины 10 | `ifdef adr22 11 | `define TOPBOARD topboard22 // 22-битный 12 | `else 13 | `define TOPBOARD topboard16 // 16-битный 14 | `endif 15 | 16 | // Для платы KDF11B выкидываем монитор-загрузчик, поскольку там есть свой родной 17 | `ifdef kdf11_board 18 | `undef bootrom_module 19 | `endif 20 | 21 | // Для платы 1201.04 то же самое 22 | `ifdef mc1201_04_board 23 | `undef bootrom_module 24 | `endif 25 | 26 | // фиктивный CPUSLOW для неподдерживаемых процессорных плат 27 | `ifndef CPUSLOW 28 | `define CPUSLOW 1 29 | `endif 30 | 31 | // удаление графического модуля при отсутствии текcтового терминала 32 | `ifndef KSM_module 33 | `undef KGD_module 34 | `endif 35 | 36 | // Выбор ведущего и ведомых SDSPI 37 | `ifdef RK_module 38 | `define RK_sdmode 1'b1 39 | `define DM_sdmode 1'b0 40 | `define MY_sdmode 1'b0 41 | `define DX_sdmode 1'b0 42 | `define DW_sdmode 1'b0 43 | `define DB_sdmode 1'b0 44 | `define def_mosi rk_mosi 45 | `define def_cs rk_cs 46 | `define def_sclk rk_sclk 47 | 48 | `elsif DM_module 49 | `define DM_sdmode 1'b1 50 | `define RK_sdmode 1'b0 51 | `define MY_sdmode 1'b0 52 | `define DX_sdmode 1'b0 53 | `define DW_sdmode 1'b0 54 | `define DB_sdmode 1'b0 55 | `define def_mosi dm_mosi 56 | `define def_cs dm_cs 57 | `define def_sclk dm_sclk 58 | 59 | `elsif MY_module 60 | `define MY_sdmode 1'b1 61 | `define RK_sdmode 1'b0 62 | `define DM_sdmode 1'b0 63 | `define DX_sdmode 1'b0 64 | `define DW_sdmode 1'b0 65 | `define DB_sdmode 1'b0 66 | `define def_mosi my_mosi 67 | `define def_cs my_cs 68 | `define def_sclk my_sclk 69 | 70 | `elsif DX_module 71 | `define DX_sdmode 1'b1 72 | `define MY_sdmode 1'b0 73 | `define DM_sdmode 1'b0 74 | `define RK_sdmode 1'b0 75 | `define DW_sdmode 1'b0 76 | `define DB_sdmode 1'b0 77 | `define def_mosi dx_mosi 78 | `define def_cs dx_cs 79 | `define def_sclk dx_sclk 80 | 81 | `elsif DB_module 82 | `define DB_sdmode 1'b1 83 | `define DX_sdmode 1'b0 84 | `define MY_sdmode 1'b0 85 | `define DM_sdmode 1'b0 86 | `define RK_sdmode 1'b0 87 | `define DW_sdmode 1'b0 88 | `define def_mosi db_mosi 89 | `define def_cs db_cs 90 | `define def_sclk db_sclk 91 | 92 | `else 93 | `define DW_sdmode 1'b1 94 | `define DX_sdmode 1'b0 95 | `define DM_sdmode 1'b0 96 | `define MY_sdmode 1'b0 97 | `define RK_sdmode 1'b0 98 | `define def_mosi dw_mosi 99 | `define def_cs dw_cs 100 | `define def_sclk dw_sclk 101 | 102 | `endif 103 | 104 | // Перенос вектора ИРПС2 на нестандартный адрес при наличии DW 105 | `ifdef DW_module 106 | `define irps2_ri 16'o000330 107 | `define irps2_ti 16'o000334 108 | `else 109 | `define irps2_ri 16'o000300 110 | `define irps2_ti 16'o000304 111 | `endif 112 | 113 | -------------------------------------------------------------------------------- /hdl/f11/dc_fpp.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2014-2022 by 1801BM1@gmail.com 3 | // 4 | // DC304 MMU Chip Floating Point Register File 5 | //______________________________________________________________________________ 6 | // 7 | // Generic implementation of Register File, memory blocks are supposed to be 8 | // inferred. Some verions of synthesys tools (Quartus, etc.) do not infer memory 9 | // blocks correctly, so explicit RAM megafunction should be used, depending on 10 | // device type. It provides much better Fmax and resource usage. If vendor 11 | // specific memory function is used this file should not be included in project. 12 | // 13 | // Interface is compatible with Altera Single-Port Single Clock RAM. 14 | // 15 | module dc_fpp( 16 | input clock, 17 | input [5:0] address, 18 | input [15:0] data, 19 | input wren, 20 | input rden, 21 | output [15:0] q 22 | ); 23 | 24 | reg [15:0] ram[63:0]; 25 | reg [5:0] addr; 26 | 27 | integer i; 28 | initial 29 | begin 30 | for (i=0; i<64; i = i + 1) 31 | ram[i] = 16'h0000; 32 | end 33 | 34 | always @ (posedge clock) 35 | begin 36 | if (wren) 37 | ram[address][15:0] <= data[15:0]; 38 | if (rden) 39 | addr <= address; 40 | end 41 | assign q = ram[addr]; 42 | 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /hdl/f11/dc_mmu.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2014-2022 by 1801BM1@gmail.com 3 | // 4 | // DC304 MMU Chip Memory Managment Register File 5 | //______________________________________________________________________________ 6 | // 7 | // Generic implementation of Register File, memory blocks are supposed to be 8 | // inferred. Some verions of synthesys tools (Quartus, etc.) do not infer memory 9 | // blocks correctly, so explicit RAM megafunction should be used, depending on 10 | // device type. It provides much better Fmax and resource usage. If vendor 11 | // specific memory function is used this file should not be included in 12 | // the project. 13 | // 14 | // Interface is compatible with Altera Dual-Port Single Clock RAM with 15 | // byte lane enable strobes.. 16 | // 17 | // Port A is used to access MMU registers from CPU bus and to present page 18 | // address register (PAR) content on address translation cycle. Port B is used 19 | // to present // page descriptor register (PDR) content for address translation 20 | // and write Dirty Page flag back to PDR after memory write access. 21 | // 22 | module dc_mmu ( 23 | input clock, 24 | input [4:0] address_a, 25 | input [4:0] address_b, 26 | input [1:0] byteena_a, 27 | input [1:0] byteena_b, 28 | input [15:0] data_a, 29 | input [15:0] data_b, 30 | output [15:0] q_a, 31 | output [15:0] q_b, 32 | input wren_a, 33 | input wren_b 34 | ); 35 | 36 | reg [15:0] ram[31:0]; 37 | reg [5:0] addr_a; 38 | reg [5:0] addr_b; 39 | 40 | //______________________________________________________________________________ 41 | // 42 | // Minimal required registers initalization, otherwise, 43 | // undefined content would prevent simulation. 44 | // 45 | integer i; 46 | initial 47 | begin 48 | for (i=0; i<32; i = i+1) 49 | ram[i] = 16'h0000; 50 | end 51 | 52 | //______________________________________________________________________________ 53 | // 54 | always @ (posedge clock) 55 | begin 56 | addr_a = address_a; 57 | if (wren_a) 58 | begin 59 | if (byteena_a[0]) ram[addr_a][7:0] = data_a[7:0]; 60 | if (byteena_a[1]) ram[addr_a][15:8] = data_a[15:8]; 61 | end 62 | 63 | addr_b = address_b; 64 | if (wren_b) 65 | begin 66 | if (byteena_b[0]) ram[addr_b][7:0] = data_b[7:0]; 67 | if (byteena_b[1]) ram[addr_b][15:8] = data_b[15:8]; 68 | end 69 | end 70 | 71 | assign q_a = ram[addr_a]; 72 | assign q_b = ram[addr_b]; 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /hdl/f11/dc_pla.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2014-2022 by 1801BM1@gmail.com 3 | // 4 | //______________________________________________________________________________ 5 | // 6 | // PLA matrix: 7 | // - 23 inputs - 7 lower bits of next address, 16 bits of data 8 | // - selected if upper next address bits na[8:7] are both zeroes 9 | // - 25 outputs - 9 bits of next address and 16 bits of microcode 10 | // - 138 minterms (products) 11 | // 12 | module dc_pla 13 | #(parameter 14 | //______________________________________________________________________________ 15 | // 16 | // DC303_PLA defines PLA content of the DC303 module 17 | // - DC303_PLA = 0, 23-001C7-AA - 1811VU1 18 | // - DC303_PLA = 1, 23-002C7-AA - 1811VU3 19 | // - DC303_PLA = 2, 23-203C7-AA - 1811VU2 20 | // 21 | DC303_PLA = 0 22 | ) 23 | ( 24 | input [6:0] a_in, 25 | input [15:0] d_in, 26 | output [8:0] ma, 27 | output [15:0] mc 28 | ); 29 | 30 | generate 31 | case(DC303_PLA) 32 | 0: dc_pla_0 pla(.a_in(a_in), .d_in(d_in), .ma(ma), .mc(mc)); 33 | 1: dc_pla_1 pla(.a_in(a_in), .d_in(d_in), .ma(ma), .mc(mc)); 34 | 2: dc_pla_2 pla(.a_in(a_in), .d_in(d_in), .ma(ma), .mc(mc)); 35 | endcase 36 | endgenerate 37 | endmodule 38 | -------------------------------------------------------------------------------- /hdl/f11/dc_rom.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2014-2022 by 1801BM1@gmail.com 3 | // 4 | //______________________________________________________________________________ 5 | // 6 | // MicROM module, (128 + 10) lines x 4 pages x 25-bit words 7 | // 25-bit word provides 9-bit next address in the upper bits, 8 | // the rest is 16-bit microcode opcode 9 | // 10 | module dc_rom 11 | #(parameter 12 | //______________________________________________________________________________ 13 | // 14 | // DC303_CS defines ROM content of the DC303 ROM module 15 | // - DC303_CS = 0, 23-001C7-AA, 000.rom 16 | // - DC303_CS = 1, 23-002C7-AA, 001.rom 17 | // - DC303_CS = 2, 23-203C7-AA, 002.rom 18 | // 19 | DC303_ROM = 0 20 | ) 21 | ( 22 | input clk, 23 | input cen, 24 | input [9:0] a_in, 25 | output [8:0] ma, 26 | output [15:0] mc 27 | ); 28 | 29 | wire [8:0] addr; 30 | reg [8:0] qa; 31 | reg [15:0] qc; 32 | reg [31:0] mem [0:511]; 33 | 34 | integer i; 35 | 36 | 37 | initial 38 | begin 39 | for (i=0; i<512; i=i+1) 40 | begin 41 | mem[i] = 32'h00000000; 42 | end 43 | // 44 | // The filename for MicROM content might be explicitly 45 | // specified in synthesys/simulating tool settings 46 | // 47 | if (DC303_ROM == 0) 48 | `ifdef F11_FILE_MICROM_000 49 | $readmemh(`F11_FILE_MICROM_000, mem); 50 | `else 51 | $readmemh("..//..//rom//f11/000.rom", mem); 52 | `endif 53 | else 54 | if (DC303_ROM == 1) 55 | `ifdef F11_FILE_MICROM_001 56 | $readmemh(`F11_FILE_MICROM_001, mem); 57 | `else 58 | $readmemh("..//..//rom//f11/001.rom", mem); 59 | `endif 60 | else 61 | if (DC303_ROM == 2) 62 | `ifdef F11_FILE_MICROM_002 63 | $readmemh(`F11_FILE_MICROM_002, mem); 64 | `else 65 | $readmemh("..//..//rom//f11/002.rom", mem); 66 | `endif 67 | end 68 | 69 | // 70 | // Save memory block for the AX extension, only 10 upper MicROM locations depend on AX 71 | // The lower quarter of memory is not used (addresses are reserved for the PLA mapping) 72 | // and this can be engaged to store unique data for the locations with set AX line 73 | // 74 | assign addr[3:0] = a_in[3:0]; 75 | assign addr[8:4] = (a_in[9] & (a_in[6:4] == 3'b111)) ? {3'b000, a_in[8:7]} : a_in[8:4]; 76 | 77 | always @(posedge clk) 78 | begin 79 | if (cen) 80 | begin 81 | qa <= mem[addr][24:16]; 82 | qc <= mem[addr][15:0]; 83 | end 84 | end 85 | 86 | assign mc = qc; 87 | assign ma = qa; 88 | 89 | endmodule 90 | 91 | -------------------------------------------------------------------------------- /hdl/f11/kdf11b_rom.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ROM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: kdf11b_rom.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module kdf11b_rom ( 40 | address, 41 | clock, 42 | q); 43 | 44 | input [10:0] address; 45 | input clock; 46 | output [15:0] q; 47 | `ifndef ALTERA_RESERVED_QIS 48 | // synopsys translate_off 49 | `endif 50 | tri1 clock; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_on 53 | `endif 54 | 55 | wire [15:0] sub_wire0; 56 | wire [15:0] q = sub_wire0[15:0]; 57 | 58 | altsyncram altsyncram_component ( 59 | .address_a (address), 60 | .clock0 (clock), 61 | .q_a (sub_wire0), 62 | .aclr0 (1'b0), 63 | .aclr1 (1'b0), 64 | .address_b (1'b1), 65 | .addressstall_a (1'b0), 66 | .addressstall_b (1'b0), 67 | .byteena_a (1'b1), 68 | .byteena_b (1'b1), 69 | .clock1 (1'b1), 70 | .clocken0 (1'b1), 71 | .clocken1 (1'b1), 72 | .clocken2 (1'b1), 73 | .clocken3 (1'b1), 74 | .data_a ({16{1'b1}}), 75 | .data_b (1'b1), 76 | .eccstatus (), 77 | .q_b (), 78 | .rden_a (1'b1), 79 | .rden_b (1'b1), 80 | .wren_a (1'b0), 81 | .wren_b (1'b0)); 82 | defparam 83 | altsyncram_component.address_aclr_a = "NONE", 84 | altsyncram_component.clock_enable_input_a = "BYPASS", 85 | altsyncram_component.clock_enable_output_a = "BYPASS", 86 | altsyncram_component.init_file = "../../rom/f11/boot_diag_rom.mif", 87 | // altsyncram_component.init_file = "../../rom/f11/mc3401.mif", 88 | altsyncram_component.intended_device_family = "Cyclone IV E", 89 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 90 | altsyncram_component.lpm_type = "altsyncram", 91 | altsyncram_component.numwords_a = 2048, 92 | altsyncram_component.operation_mode = "ROM", 93 | altsyncram_component.outdata_aclr_a = "NONE", 94 | altsyncram_component.outdata_reg_a = "CLOCK0", 95 | altsyncram_component.widthad_a = 11, 96 | altsyncram_component.width_a = 16, 97 | altsyncram_component.width_byteena_a = 1; 98 | 99 | 100 | endmodule 101 | -------------------------------------------------------------------------------- /hdl/ksm/ksm_vic.v: -------------------------------------------------------------------------------- 1 | //****************************************************** 2 | //* Контроллер прерываний 3 | //****************************************************** 4 | 5 | module ksm_vic 6 | #(parameter N=1) // количество векторов 7 | ( 8 | input wb_clk_i, // system clock 9 | input wb_rst_i, // peripheral reset 10 | output reg wb_irq_o, // запрос прерывания к процессору 11 | output reg [15:0] wb_dat_o, // шина для передачи вектора прерывания к процессору 12 | input wb_stb_i, // строб от прецессора для приема вектора 13 | output reg wb_ack_o, // подтверждение передачи вектора процессору 14 | input wb_una_i, // строб безадресного запроса 15 | // 16 | input [15:0] rsel, // содержимое регистра режима запуска 17 | input [N*16-1:0] ivec, // массив значений векторов прерывания 18 | input [N-1:0] ireq, // линии запроса прерывания 19 | output reg [N-1:0] iack // линии подтверждения прерывания 20 | ); 21 | localparam W = log2(N); // число бит для записи номера вектора 22 | 23 | reg [W-1:0] nvec; // номер прерывания с наивысшим приоритетом, или 0 если активных прерываний нет. 24 | integer i; 25 | 26 | always @(posedge wb_clk_i or posedge wb_rst_i) 27 | begin 28 | if (wb_rst_i) 29 | begin 30 | // сброс контроллера 31 | wb_ack_o <= 1'b0; 32 | wb_dat_o <= 16'O000000; 33 | iack <= 0; 34 | nvec <= {(W){1'b1}}; // nvec заполнен единицами при отсутствии прерывания 35 | end 36 | else 37 | // обработка запросов на прерывания 38 | begin 39 | // сигнал подтверждения запроса вектора 40 | wb_ack_o <= wb_stb_i & // в ответ на строб от процессора 41 | (wb_irq_o | wb_una_i) // если мы выставляем вектор или процессор запросил безадресное чтение 42 | & ~wb_ack_o; // если строб уже был выставлен в предыдущем такте - то снимаем его 43 | 44 | // сигнал запроса векторного прерывания 45 | wb_irq_o <= ~(&nvec) & // если есть активный ветор 46 | (~wb_ack_o | wb_una_i); // и если вектор еще не передан или идет безадресное чтение 47 | 48 | // сигнал подтверждения прерывания к периферийному устройству 49 | for (i=N-1; i>=0; i=i-1) 50 | iack[i] <= 51 | (nvec == i) // это текущая линия обработки прерывания 52 | & ireq[i] // был запрос на прерывание 53 | & wb_stb_i // был строб от процессора - он готов принять вектор 54 | & ~wb_una_i // не идет безадресное чтение 55 | & wb_irq_o // уже выставлен запрос векторного прерывания к процессору 56 | & ~iack[i]; // если сигнал в предыдущем такте выставлен - снимаем 57 | 58 | // выставляем вектор на шину 59 | if (wb_stb_i & ~wb_ack_o & (wb_irq_o | wb_una_i)) // пришел строб от прецессора и еще не выставлено подтверждение 60 | if (wb_una_i) 61 | // безадресное чтение 62 | wb_dat_o <= rsel; 63 | else 64 | // передача ыектора прерывания 65 | wb_dat_o <= trunc_w16(ivec >> (nvec*16)); 66 | 67 | if (~wb_stb_i) 68 | begin 69 | nvec <= {(W){1'b1}}; 70 | for (i=N-1; i>=0; i=i-1) 71 | if (ireq[i]) nvec <= trunc_int(i); 72 | end 73 | else 74 | if (wb_ack_o & ~wb_una_i) 75 | nvec <= {(W){1'b1}}; 76 | end 77 | end 78 | 79 | function integer log2(input integer value); 80 | for (log2=0; value>0; log2=log2+1) 81 | value = value >> 1; 82 | endfunction 83 | 84 | function [15:0] trunc_w16(input [N*16-1:0] value); 85 | trunc_w16 = value[15:0]; 86 | endfunction 87 | 88 | function [W-1:0] trunc_int(input integer value); 89 | trunc_int = value[W-1:0]; 90 | endfunction 91 | endmodule 92 | -------------------------------------------------------------------------------- /hdl/ksm/vregs.v: -------------------------------------------------------------------------------- 1 | //*************************************************** 2 | //* Регистры видеоконтроллера 3 | //************************************************* 4 | module vregs 5 | #(parameter SPEED=19200) // начальная скорость интерфейса по умолчанию 6 | ( 7 | // шина wishbone 8 | input wb_clk_i, // тактовая частота шины 9 | input wb_rst_i, // сброс 10 | input [15:0] wb_adr_i, // адрес 11 | input [15:0] wb_dat_i, // входные данные 12 | output reg [15:0] wb_dat_o, // выходные данные 13 | input wb_cyc_i, // начало цикла шины 14 | input wb_we_i, // разрешение записи (0 - чтение) 15 | input wb_stb_i, // строб цикла шины 16 | input [1:0] wb_sel_i, // выбор конкретных байтов для записи - старший, младший или оба 17 | output reg wb_ack_o, // подтверждение выбора устройства 18 | 19 | input [2:0] initspeed, // начальная скорость последовательного порта - запишется в регистр конфигурации 20 | // регистры 21 | output reg [10:0] cursor, // регистр адреса курсора, base+0 22 | output reg [15:0] vtcsr // управляющий регистр, base+2 23 | ); 24 | //----------------------------------------------------------------------------------------------------- 25 | // base+0 регистр адреса курсора, содержит абсолютный адрес байта с курсором в области видеопамяти 26 | //----------------------------------------------------------------------------------------------------- 27 | // base+2 Регистр управления терминалом VTCSR: 28 | // 29 | // D0: 0 - локальная петля, 1 - связь с ЭВМ 30 | // D1: 31 | // D2: 0 - курсор невидим, 1 - отображается 32 | // D3: форма курсора: 0 - подчеркивание, 1 - блок 33 | // D4: 1 - звуковой сигнал 34 | // D5: импульсы управления мерцанием знаков (0 - знак погашен, 1 - отображается) 35 | // 36 | // D8..D10: скорость интерфейса: 37 | // 000 - 1200 38 | // 001 - 2400 39 | // 010 - 4800 40 | // 011 - 9600 41 | // 100 - 19200 42 | // 101 - 38400 43 | // 110 - 57600 44 | // 111 - 115200 45 | 46 | wire bus_strobe; // строб шинной транзакции 47 | wire re; // строб чтения 48 | wire we; // строб записи четных байтов 49 | wire wo; // строб записи нечетных байтов 50 | 51 | //**************************************** 52 | // Сигналы запроса доступа от шины 53 | //**************************************** 54 | // строб цикла шины 55 | assign bus_strobe = wb_cyc_i & wb_stb_i; 56 | // чтение 57 | assign re = bus_strobe & ~wb_we_i; 58 | // запись четных байтов 59 | assign we = bus_strobe & wb_we_i & wb_sel_i[0]; 60 | // запись нечетных байтов 61 | assign wo = bus_strobe & wb_we_i & wb_sel_i[1]; 62 | // формирователь ответа на цикл шины 63 | wire reply=wb_cyc_i & wb_stb_i & ~wb_ack_o; 64 | // Сигнал ответа 65 | always @(posedge wb_clk_i or posedge wb_rst_i) 66 | if (wb_rst_i == 1'b1) wb_ack_o <= 1'b0; 67 | else wb_ack_o <= reply; 68 | 69 | //**************************************** 70 | //* Обработка транзакций общей шины 71 | //**************************************** 72 | always @(posedge wb_clk_i or posedge wb_rst_i) 73 | // сброс 74 | if (wb_rst_i == 1'b1) begin 75 | cursor <= {13{1'b0}} ; // курсор в позиции 0 76 | vtcsr <= {5'b0000, initspeed,8'b00001}; // сразу включается режим online, устанавливаем скорость по умолчанию 77 | end 78 | 79 | else begin 80 | if (re == 1'b1) begin 81 | // чтение регистров 82 | if (wb_adr_i[1]) wb_dat_o <= vtcsr; // регистр управления 83 | // else wb_dat_o <= {3'b000, cursor} ; // регистр курсора - чтение не требуется 84 | end 85 | else begin 86 | // запись регистров 87 | if (wo == 1'b1) 88 | // запись нечетных байтов 89 | if (wb_adr_i[1] == 0) cursor[10:8] <= wb_dat_i[10:8] ; // регистр курсора 90 | else vtcsr[15:8] <= wb_dat_i[15:8]; // регистр управления 91 | 92 | if (we == 1'b1) 93 | // запись четных байтов 94 | if (wb_adr_i[1] == 0) cursor[7:0] <= wb_dat_i[7:0] ; // регистр курсора 95 | else vtcsr[7:0] <= wb_dat_i[7:0]; // регистр управления 96 | end 97 | end 98 | endmodule 99 | -------------------------------------------------------------------------------- /hdl/ksm/vtram.v: -------------------------------------------------------------------------------- 1 | //******************************************************************** 2 | //* Модуль статической памяти с управляющей программой терминала 3 | //******************************************************************** 4 | module vtram ( 5 | input wb_clk_i, 6 | input [15:0] wb_adr_i, 7 | input [15:0] wb_dat_i, 8 | output [15:0] wb_dat_o, 9 | input wb_cyc_i, 10 | input wb_we_i, 11 | input [1:0] wb_sel_i, 12 | input wb_stb_i, 13 | output wb_ack_o 14 | ); 15 | wire [1:0] ena; 16 | reg [1:0] ack; 17 | 18 | vtmem ram( 19 | .address(wb_adr_i[11:1]), 20 | .byteena(ena), 21 | .clock(wb_clk_i), 22 | .data(wb_dat_i), 23 | .rden(~wb_we_i & wb_cyc_i & wb_stb_i), 24 | .wren( wb_we_i & wb_cyc_i & wb_stb_i), 25 | .q(wb_dat_o)); 26 | 27 | assign ena = wb_we_i ? wb_sel_i : 2'b11; 28 | assign wb_ack_o = wb_cyc_i & wb_stb_i & (ack[1] | wb_we_i); 29 | always @ (posedge wb_clk_i) 30 | begin 31 | ack[0] <= wb_cyc_i & wb_stb_i; 32 | ack[1] <= wb_cyc_i & ack[0]; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /hdl/ksm/vtreset.v: -------------------------------------------------------------------------------- 1 | `define DCLO_WIDTH_CLK 5 2 | `define ACLO_DELAY_CLK 3 3 | 4 | //***************************************************** 5 | //* Модуль генерации сбросов 6 | //***************************************************** 7 | module vtreset ( 8 | input clk, // тактовая частота 50 МГц 9 | input rstin, // кнопка сброса, 0 - сброс, 1 - работа 10 | output dclo, // авария DC 11 | output aclo, // авария AC 12 | output reg irq50 // прерывания с частотой 50 Гц 13 | ); 14 | localparam DCLO_COUNTER_WIDTH = log2(`DCLO_WIDTH_CLK); 15 | localparam ACLO_COUNTER_WIDTH = log2(`ACLO_DELAY_CLK); 16 | 17 | reg [DCLO_COUNTER_WIDTH-1:0] dclo_cnt; 18 | reg [ACLO_COUNTER_WIDTH-1:0] aclo_cnt; 19 | reg [1:0] reset; 20 | reg [18:0] intcount; // счетчик для генерации прерываний 21 | reg aclo_out, dclo_out; 22 | 23 | assign dclo = dclo_out; 24 | assign aclo = aclo_out; 25 | 26 | always @(posedge clk) begin 27 | // 28 | // Синхронизация сигнала сброса для предотвращения метастабильности 29 | // 30 | reset[0] <= rstin; 31 | reset[1] <= reset[0]; 32 | 33 | if (reset[1]) begin 34 | dclo_cnt <= 0; 35 | aclo_cnt <= 0; 36 | aclo_out <= 1'b1; 37 | dclo_out <= 1'b1; 38 | intcount <= 19'd000000; 39 | irq50 <= 1'b0; 40 | end 41 | else begin 42 | // 43 | // Счетчик задержки DCLO 44 | // 45 | if (dclo_cnt != `DCLO_WIDTH_CLK) dclo_cnt <= dclo_cnt + 1'b1; 46 | else dclo_out <= 1'b0; // снимаем DCLO 47 | 48 | // 49 | // Счетчик задержки ACLO 50 | // 51 | if (~dclo_out) 52 | if (aclo_cnt != `ACLO_DELAY_CLK) aclo_cnt <= aclo_cnt + 1'b1; 53 | else aclo_out <= 1'b0; 54 | 55 | // генерация импульсов прерывания 56 | if (|intcount == 1'b0) begin 57 | intcount <= 19'd500000; 58 | irq50 <= ~irq50; 59 | end 60 | else intcount <= intcount-1'b1; 61 | 62 | end 63 | end 64 | 65 | // получение количества двоичных разрядов в числе 66 | function integer log2(input integer value); 67 | begin 68 | for (log2=0; value>0; log2=log2+1) 69 | value = value >> 1; 70 | end 71 | endfunction 72 | endmodule 73 | 74 | -------------------------------------------------------------------------------- /hdl/m2/mcp1631.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2014-2019 by 1801BM1@gmail.com 3 | // 4 | // MCP-1631 MicROM model, for debug and simulating only 5 | //______________________________________________________________________________ 6 | // 7 | // 8 | module mcp1631 9 | #(parameter 10 | //______________________________________________________________________________ 11 | // 12 | // LSI11_ORIGINAL_MICROM nonzero value means the original DEC Microm 13 | // 1631-10/07/15 conten is used, we can optimize 4 MSBs with ordinal logic 14 | // and save memory blocks 15 | // 16 | LSI11_ORIGINAL_MICROM = 1 17 | ) 18 | ( 19 | input pin_clk, // main clock 20 | input [10:0] pin_lc, // location counter 21 | output [21:0] pin_mo // microinstruction bus 22 | ); 23 | 24 | //______________________________________________________________________________ 25 | // 26 | // Memory array and its inititialization with 1631-10/07/15 content 27 | // Special embedded memory depth control attribute: 28 | // 29 | `ifdef LSI11_DEPTH_MICROM 30 | // 31 | // Special embedded memory depth control attribute: 32 | // 33 | // `define LSI11_DEPTH_MICROM (* max_depth = 1024 *) 34 | // 35 | // It should be globally defined as Verilog macro in synthesis 36 | // tool settings (Quartus/ISE) if supported by FPGA family/tool 37 | // 38 | `LSI11_DEPTH_MICROM 39 | `endif 40 | reg [21:0] rom [0:2047]; 41 | reg [21:0] q; 42 | reg [10:0] lcr; 43 | reg [3:0] ttl; 44 | 45 | initial 46 | begin 47 | // 48 | // The filename for MicROM content might be explicitly 49 | // specified in synthesys/simulating tool settings 50 | // 51 | `ifdef LSI11_FILE_MICROM 52 | $readmemb(`LSI11_FILE_MICROM, rom); 53 | `else 54 | $readmemb("../../rom/all_22b.rom", rom); 55 | `endif 56 | end 57 | 58 | assign pin_mo[17:0] = q[17:0]; 59 | assign pin_mo[21:18] = LSI11_ORIGINAL_MICROM ? ttl[3:0] : q[21:18]; 60 | 61 | always @ (posedge pin_clk) q <= rom[pin_lc]; 62 | always @ (posedge pin_clk) lcr <= pin_lc; 63 | 64 | always @(*) 65 | case(lcr) 66 | 11'h022: ttl <= 4'hC; 67 | 11'h025: ttl <= 4'h9; 68 | 11'h10C: ttl <= 4'h9; 69 | 11'h116: ttl <= 4'hE; 70 | 11'h156: ttl <= 4'hD; 71 | 11'h157: ttl <= 4'hD; 72 | 11'h1C2: ttl <= 4'hF; 73 | 11'h322: ttl <= 4'hB; 74 | 11'h327: ttl <= 4'hA; 75 | 11'h32C: ttl <= 4'hA; 76 | 11'h33B: ttl <= 4'h9; 77 | 11'h346: ttl <= 4'hE; 78 | 11'h347: ttl <= 4'hF; 79 | default: ttl <= 4'h0; 80 | endcase 81 | endmodule 82 | -------------------------------------------------------------------------------- /hdl/m4/am4_mcrom.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2020 by 1801BM1@gmail.com 3 | // 4 | //______________________________________________________________________________ 5 | // 6 | // M4 microcode ROM, for debug and simulating only 7 | // 8 | module mcrom 9 | ( 10 | input clk, // input clock 11 | input ena, // clock enable 12 | input [9:0] addr, // instruction address 13 | output [55:0] data // output read opcode 14 | ); 15 | 16 | //______________________________________________________________________________ 17 | // 18 | // Memory array and its inititialization with K1656RE1-001/007 content 19 | // 20 | reg [55:0] rom [0:1023]; 21 | reg [55:0] q; 22 | integer i; 23 | 24 | 25 | initial 26 | begin 27 | for (i=0; i<1023; i = i + 1) 28 | begin 29 | rom[i] = 56'h00000000000000; 30 | end 31 | // 32 | // The filename for MicROM content might be explicitly 33 | // specified in synthesys/simulating tool settings 34 | // 35 | `ifdef M4_FILE_MICROM 36 | $readmemh(`M4_FILE_MICROM, rom); 37 | `else 38 | $readmemh("../../rom/mc.rom", rom); 39 | `endif 40 | end 41 | 42 | //______________________________________________________________________________ 43 | // 44 | assign data = q; 45 | always @ (posedge clk) if (ena) q <= rom[addr]; 46 | 47 | endmodule 48 | 49 | 50 | -------------------------------------------------------------------------------- /hdl/m4/am4_plm.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2020 by 1801BM1@gmail.com 3 | //______________________________________________________________________________ 4 | // 5 | // M4 processor PDP-11 instruction decoding PLM (D123, D136) 6 | // 7 | module plm_dec 8 | ( 9 | input [15:0] ins, // PDP-11 instruction opcode 10 | output reg bf, // byte operation flag 11 | output reg [6:0] ad // address of microcode 12 | ); 13 | 14 | wire rs = ins[11:9] == 3'b000; 15 | wire rd = ins[5:3] == 3'b000; 16 | 17 | always @(*) 18 | casex(ins) // clrb/comb/incb/decb 19 | 16'o105xxx: bf = 1'b1; // negb/adcb/sbcb/tstb 20 | 16'o1060xx: bf = 1'b1; // rorb 21 | 16'o1061xx: bf = 1'b1; // rolb 22 | 16'o1062xx: bf = 1'b1; // asrb 23 | 16'o1063xx: bf = 1'b1; // aslb 24 | 16'o1064xx: bf = 1'b1; // mtps 25 | 16'o1067xx: bf = 1'b1; // mfps 26 | 16'o11xxxx: bf = 1'b1; // movb 27 | 16'o12xxxx: bf = 1'b1; // cmpb 28 | 16'o13xxxx: bf = 1'b1; // bitb 29 | 16'o14xxxx: bf = 1'b1; // bicb 30 | 16'o15xxxx: bf = 1'b1; // bisb 31 | default: bf = 1'b0; 32 | endcase 33 | 34 | always @(*) 35 | casex(ins) 36 | 16'o000000: ad = 7'h00; // halt 37 | 16'o000001: ad = 7'h03; // wait 38 | 16'o000002: ad = 7'h02; // rti 39 | 16'o000003: ad = 7'h04; // bpt 40 | 16'o000004: ad = 7'h07; // iot 41 | 16'o000005: ad = 7'h06; // reset 42 | 16'o000006: ad = 7'h02; // rtt 43 | 16'o0001xx: ad = 7'h0E; // jmp 44 | 16'o00020x: ad = 7'h36; // rts 45 | 16'o00024x: ad = 7'h40; // clx 46 | 16'o00025x: ad = 7'h40; // clx 47 | 16'o00026x: ad = 7'h43; // sex 48 | 16'o00027x: ad = 7'h43; // sex 49 | 16'o0003xx: ad = ~rd ? 7'h41 // swab 50 | /* 16'o00030x: */ : 7'h44; // swab Rd 51 | 16'o0004xx: ad = 7'h1F; // br 52 | 16'o0005xx: ad = 7'h1F; // 53 | 16'o0006xx: ad = 7'h1F; // 54 | 16'o0007xx: ad = 7'h1F; // 55 | 16'o001xxx: ad = 7'h1F; // bne/beq 56 | 16'o002xxx: ad = 7'h1F; // bge/blt 57 | 16'o003xxx: ad = 7'h1F; // bgt/ble 58 | 16'o004xxx: ad = 7'h37; // jsr 59 | // 60 | 16'o0050xx: ad = ~rd ? 7'h12 // clr 61 | /* 16'o00500x: */ : 7'h22; // clr Rd 62 | 16'o0051xx: ad = ~rd ? 7'h14 // com 63 | /* 16'o00510x: */ : 7'h24; // com Rd 64 | 16'o0052xx: ad = ~rd ? 7'h16 // inc 65 | /* 16'o00520x: */ : 7'h26; // inc Rd 66 | 16'o0053xx: ad = ~rd ? 7'h18 // dec 67 | /* 16'o00530x: */ : 7'h28; // dec Rd 68 | 16'o0054xx: ad = ~rd ? 7'h1A // neg 69 | /* 16'o00540x: */ : 7'h2A; // neg Rd 70 | 16'o0055xx: ad = ~rd ? 7'h0D // adc 71 | /* 16'o00550x: */ : 7'h4D; // adc Rd 72 | 16'o0056xx: ad = ~rd ? 7'h53 // sbc 73 | /* 16'o00560x: */ : 7'h4A; // sbc Rd 74 | 16'o0057xx: ad = ~rd ? 7'h2C // tst 75 | /* 16'o00570x: */ : 7'h6C; // tst Rd 76 | 16'o0060xx: ad = ~rd ? 7'h15 // ror 77 | /* 16'o00600x: */ : 7'h55; // ror Rd 78 | 16'o0061xx: ad = ~rd ? 7'h17 // rol 79 | /* 16'o00610x: */ : 7'h56; // rol Rd 80 | 16'o0062xx: ad = ~rd ? 7'h1B // asr 81 | /* 16'o00620x: */ : 7'h5B; // asr Rd 82 | 16'o0063xx: ad = ~rd ? 7'h1D // asl 83 | /* 16'o00630x: */ : 7'h5C; // asl Rd 84 | 16'o0064xx: ad = 7'h09; // mark 85 | 16'o0067xx: ad = 7'h08; // sxt 86 | // 87 | 16'o01xxxx: ad = (~rs | ~rd) ? 7'h31 // mov 88 | /* 16'o010x0x: */ : 7'h30; // mov Rs, Rd 89 | 16'o02xxxx: ad = (~rs | ~rd) ? 7'h13 // cmp 90 | /* 16'o020x0x: */ : 7'h3A; // cmp Rs, Rd 91 | 16'o03xxxx: ad = (~rs | ~rd) ? 7'h1C // bit 92 | /* 16'o030x0x: */ : 7'h3C; // bit Rs, Rd 93 | 16'o04xxxx: ad = (~rs | ~rd) ? 7'h1E // bic 94 | /* 16'o040x0x: */ : 7'h3E; // bic Rs, Rd 95 | 16'o05xxxx: ad = (~rs | ~rd) ? 7'h10 // bis 96 | /* 16'o050x0x: */ : 7'h20; // bis Rs, Rd 97 | 16'o06xxxx: ad = ~rs ? 7'h35 // add 98 | /* 16'o060xxx: */ : ~rd ? 7'h34 // add Rs, xx 99 | /* 16'o060x0x: */ : 7'h74; // add Rs, Rd 100 | 16'o070xxx: ad = 7'h47; // mul 101 | 16'o071xxx: ad = 7'h48; // div 102 | 16'o072xxx: ad = 7'h42; // ash 103 | 16'o073xxx: ad = 7'h45; // ashc 104 | 16'o074xxx: ad = 7'h0B; // xor 105 | 16'o07500x: ad = 7'h0F; // fadd 106 | 16'o07501x: ad = 7'h0F; // fsub 107 | 16'o07502x: ad = 7'h0F; // fmul 108 | 16'o07503x: ad = 7'h0F; // fdiv 109 | 16'o077xxx: ad = 7'h0A; // sob 110 | // 111 | 16'o100xxx: ad = 7'h1F; // bpl/bmi 112 | 16'o101xxx: ad = 7'h1F; // bhi/blos 113 | 16'o102xxx: ad = 7'h1F; // bvc/bvs 114 | 16'o103xxx: ad = 7'h1F; // bcc/bcs 115 | 16'o1040xx: ad = 7'h39; // emt 116 | 16'o1041xx: ad = 7'h39; // emt 117 | 16'o1042xx: ad = 7'h39; // emt 118 | 16'o1043xx: ad = 7'h39; // emt 119 | 16'o1044xx: ad = 7'h38; // trap 120 | 16'o1045xx: ad = 7'h38; // trap 121 | 16'o1046xx: ad = 7'h38; // trap 122 | 16'o1047xx: ad = 7'h38; // trap 123 | 16'o1050xx: ad = 7'h25; // clrb 124 | 16'o1051xx: ad = 7'h27; // comb 125 | 16'o1052xx: ad = 7'h29; // incb 126 | 16'o1053xx: ad = 7'h2B; // decb 127 | 16'o1054xx: ad = 7'h2D; // negb 128 | 16'o1055xx: ad = 7'h51; // adcb 129 | 16'o1056xx: ad = 7'h52; // sbcb 130 | 16'o1057xx: ad = 7'h2F; // tstb 131 | 16'o1060xx: ad = 7'h54; // rorb 132 | 16'o1061xx: ad = 7'h59; // rolb 133 | 16'o1062xx: ad = 7'h5A; // asrb 134 | 16'o1063xx: ad = 7'h5F; // aslb 135 | 16'o1064xx: ad = 7'h2E; // mtps 136 | 16'o1067xx: ad = 7'h0C; // mfps 137 | 16'o11xxxx: ad = (~rs | ~rd) ? 7'h33 // movb 138 | /* 16'o110x0x: */ : 7'h32; // movb Rd, Rs 139 | 16'o12xxxx: ad = 7'h3D; // cmpb 140 | 16'o13xxxx: ad = 7'h3F; // bitb 141 | 16'o14xxxx: ad = 7'h21; // bicb 142 | 16'o15xxxx: ad = 7'h23; // bisb 143 | 16'o16xxxx: ad = (~rs | ~rd) ? 7'h19 // sub 144 | /* 16'o160x0x: */ : 7'h3B; // sub Rd, Rs 145 | default: ad = 7'h01; // undefined 146 | endcase 147 | 148 | endmodule 149 | -------------------------------------------------------------------------------- /hdl/m4/am4_seq.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2020 by 1801BM1@gmail.com 3 | //______________________________________________________________________________ 4 | // 5 | // Microprogram Sequencer - combination of Am2909 and 29811, 6 | // adopted for M4 project, with configurable micro-address width 7 | // 8 | module am4_seq 9 | #(parameter 10 | AM4_ADDR_WIDTH = 10 11 | ) 12 | ( 13 | input clk, // input clock 14 | input ena, // clock enable 15 | // 16 | input [3:0] ora, // address or conditions 17 | input [AM4_ADDR_WIDTH-1:0] d, // direct data input 18 | output [AM4_ADDR_WIDTH-1:0] y, // data output 19 | // 20 | input re_n, // register input enable 21 | input za_n, // zero address set 22 | // 23 | input tst, // entry for conditional instructions 24 | input [3:0] i, // microcode instruction 25 | output ctl_n, // counter load 26 | output cte_n, // counter enable 27 | output me_n // map enable 28 | ); 29 | 30 | //______________________________________________________________________________ 31 | // 32 | reg [1:0] sp; // stack pointer 33 | reg [AM4_ADDR_WIDTH-1:0] pc; // program counter 34 | reg [AM4_ADDR_WIDTH-1:0] ar; // address register 35 | reg [AM4_ADDR_WIDTH-1:0] stk[3:0]; // stack file 36 | wire [AM4_ADDR_WIDTH-1:0] mux; // multiplexer 37 | // 38 | reg [6:0] mx; // 39 | wire [1:0] s; // address mux control 40 | wire fe_n; // file enable 41 | wire pup; // push/pop_n 42 | 43 | //______________________________________________________________________________ 44 | // 45 | always @(posedge clk) if (ena) 46 | begin 47 | // 48 | // Address register latch 49 | // 50 | if (~re_n) 51 | ar <= d; 52 | 53 | if (~za_n) 54 | sp <= 2'b11; 55 | // 56 | // Stack file operations 57 | // 58 | if (~fe_n) 59 | if (pup) 60 | begin 61 | sp <= sp + 2'b01; 62 | case(sp) 63 | 2'b00: stk[1] <= pc; 64 | 2'b01: stk[2] <= pc; 65 | 2'b10: stk[3] <= pc; 66 | 2'b11: stk[0] <= pc; 67 | endcase 68 | end 69 | else 70 | sp <= sp - 2'b01; 71 | // 72 | // Program counter 73 | // 74 | pc <= y + {{(AM4_ADDR_WIDTH-1){1'b0}}, 1'b1}; 75 | end 76 | 77 | assign mux = ((s == 2'b00) ? pc : {(AM4_ADDR_WIDTH){1'b0}}) 78 | | ((s == 2'b01) ? ar : {(AM4_ADDR_WIDTH){1'b0}}) 79 | | ((s == 2'b10) ? stk[sp] : {(AM4_ADDR_WIDTH){1'b0}}) 80 | | ((s == 2'b11) ? d : {(AM4_ADDR_WIDTH){1'b0}}) 81 | | {{(AM4_ADDR_WIDTH-4){1'b0}}, ora}; 82 | assign y = za_n ? mux : {(AM4_ADDR_WIDTH){1'b0}}; 83 | 84 | // 85 | // Microinstruction decoder 86 | // 87 | assign s[1] = mx[6]; // 00 - pc, 01 - ra 88 | assign s[0] = mx[5]; // 10 - sp, 11 - di 89 | assign fe_n = mx[4]; // 90 | assign pup = mx[3]; // 1/0 - push/pop 91 | assign ctl_n = mx[2]; 92 | assign cte_n = mx[1]; 93 | assign me_n = mx[0]; 94 | 95 | // 96 | // Unconditional commands 97 | // 98 | // 0000: jz di, ctl, cte 99 | // 0010: jmap di, me 100 | // 1100: ldct pc, ctl 101 | // 1110: cont pc 102 | // 1111: jp di 103 | // 104 | // Conditional commands 105 | // miss taken 106 | // 0001: cjs pc di, push 107 | // 0011: cjp pc di 108 | // 0100: push pc, push pc, push, ctl 109 | // 0101: jsrp ra, push di, push 110 | // 0110: cjv pc di 111 | // 0111: jrp ra di 112 | // 1000: rfct sp, cte pc, pop 113 | // 1001: rpct di, cte pc 114 | // 1010: crtn pc sp, pop 115 | // 1011: cjpp pc di, pop 116 | // 1101: loop sp pc, pop 117 | // 118 | always @(*) 119 | case(i[3:0]) 120 | 4'b0000: mx = 7'b1111001; // jz - jump zero 121 | 4'b0001: mx = ~tst ? 7'b0011111 : 7'b1101111; // cjs - cond jsb pl 122 | 4'b0010: mx = 7'b1111110; // jmap - jump map 123 | 4'b0011: mx = ~tst ? 7'b0011111 : 7'b1111111; // cjp - cond jump pl 124 | 4'b0100: mx = ~tst ? 7'b0001111 : 7'b0001011; // push - push/cond ld cntr 125 | 4'b0101: mx = ~tst ? 7'b0101111 : 7'b1101111; // jsrp - cond jsb r/pl 126 | 4'b0110: mx = ~tst ? 7'b0011111 : 7'b1111111; // cjv - cond jump vector 127 | 4'b0111: mx = ~tst ? 7'b0111111 : 7'b1111111; // jrp - cond jump r/pl 128 | 4'b1000: mx = ~tst ? 7'b1010101 : 7'b0000111; // rfct - repeat loop, ctr != 0 129 | 4'b1001: mx = ~tst ? 7'b1111101 : 7'b0011111; // rpct - repeat pl, ctr != 0 130 | 4'b1010: mx = ~tst ? 7'b0010111 : 7'b1000111; // crtn - cond return 131 | 4'b1011: mx = ~tst ? 7'b0010111 : 7'b1100111; // cjpp - cond jump pl & pop 132 | 4'b1100: mx = 7'b0011011; // ldct - ld cntr & continue 133 | 4'b1101: mx = ~tst ? 7'b1010111 : 7'b0000111; // loop - test end loop 134 | 4'b1110: mx = 7'b0011111; // cont - continue 135 | 4'b1111: mx = 7'b1111111; // jp - jump pl 136 | endcase 137 | endmodule 138 | 139 | 140 | -------------------------------------------------------------------------------- /hdl/pdp2011/cpuregs.v: -------------------------------------------------------------------------------- 1 | //====================================================================================================== 2 | // Регистровый файл процессора PDP2011 3 | //====================================================================================================== 4 | module cpuregs ( 5 | 6 | input[5:0] raddr, 7 | input[5:0] waddr, 8 | input[15:0] d, 9 | output [15:0] o, 10 | input we, 11 | input clk 12 | ); 13 | 14 | 15 | // выделение памяти под регистровый файл 16 | reg[15:0] regs[15:0]; 17 | // локальные адреса в массиве регистров 18 | wire[3:0] loc_raddr; 19 | wire[3:0] loc_waddr; 20 | 21 | // Формат входящего адреса 22 | // 0-2 - номер регистра 23 | // 3 - psw[11] - используемый набор регистров, 0 или 1 24 | // 4-5 - режим процессора: 25 | // 00 - kernel 26 | // 01 - supervisor 27 | // 11 - user 28 | 29 | // Распределение адресного пространства регистрового файла 30 | // 31 | // 0 R0, набор 0 32 | // 1 R1, набор 0 33 | // 2 R2, набор 0 34 | // 3 R3, набор 0 35 | // 4 R4, набор 0 36 | // 5 R5, набор 0 37 | // 6 SP режима KERNEL 38 | // 7 * PC - не используется 39 | // 8 R0, набор 1 40 | // 9 R1, набор 1 41 | // 10 R2, набор 1 42 | // 11 R3, набор 1 43 | // 12 R4, набор 1 44 | // 13 R5, набор 1 45 | // 14 SP режима Supervisor 46 | // 15 SP режима USER 47 | // 48 | assign loc_raddr = (raddr[2:1] != 2'b11) ? raddr[3:0] : // Регистры R0-R5 - одинаковы во всех вариантах 49 | (raddr[2:0] == 3'b110 & raddr[5:4] == 2'b00) ? 4'b0110 : // SP режима KERNEL 50 | (raddr[2:0] == 3'b110 & raddr[5:4] == 2'b01) ? 4'b1110 : // SP режима Supervisor 51 | (raddr[2:0] == 3'b110 & raddr[5:4] == 2'b11) ? 4'b1111 : // SP режима USER 52 | 4'b0111 ; 53 | 54 | assign loc_waddr = (waddr[2:1] != 2'b11) ? waddr[3:0] : 55 | (waddr[2:0] == 3'b110 & waddr[5:4] == 2'b00) ? 4'b0110 : 56 | (waddr[2:0] == 3'b110 & waddr[5:4] == 2'b01) ? 4'b1110 : 57 | (waddr[2:0] == 3'b110 & waddr[5:4] == 2'b11) ? 4'b1111 : 58 | 4'b0111 ; 59 | 60 | // выходные данные - чтение 61 | assign o = regs[loc_raddr] ; 62 | 63 | // запись данных 64 | always @(posedge clk) begin 65 | if (we == 1'b1) regs[loc_waddr] <= d ; 66 | end 67 | 68 | 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /hdl/pdp2011/fpuregs.v: -------------------------------------------------------------------------------- 1 | //==================================================== 2 | // Блок регистров FPU процессора PDP2011 3 | //==================================================== 4 | module fpuregs ( 5 | input[2:0] raddr, // адрес чтения 6 | input[2:0] waddr, // адрес записи 7 | input[63:0] d, // входные данные 8 | output [63:0] o, // выходные данные 9 | input fpmode, // 0 - 32-битный режим, 1 - 64-битный 10 | input we, // строб записи 11 | input clk // синхросигнал 12 | ); 13 | 14 | // Массив регистров, отдельно старшие и младшие слова 15 | reg[31:0] fpregh[5:0]; // биты 63-32 16 | reg[31:0] fpregl[5:0]; // биты 31-00 17 | 18 | //************************************************* 19 | //* Запись регистров 20 | //************************************************* 21 | always @(posedge clk) begin 22 | if (we == 1'b1 & waddr[2:1] != 2'b11) begin 23 | // старшие 32 бита 24 | fpregh[waddr] <= d[63:32] ; 25 | // младшие 32 бита 26 | if (fpmode == 1'b1) fpregl[waddr] <= d[31:0] ; 27 | end 28 | end 29 | 30 | //************************************************* 31 | //* Чтение регистров 32 | //************************************************* 33 | assign o = (fpmode == 1'b1)? {fpregh[raddr], fpregl[raddr]} : // 64-битные данные 34 | {fpregh[raddr], {32{1'b0}} } ; // 32-битные данные 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /hdl/sdram_ip/sdram_para.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////////////////////////////// 3 | // Module Name : sdram_para 4 | //------------------------------------------------------------------------------ 5 | 6 | // Варианты состояний инициализации 7 | `define I_NOP 4'd0 //Waiting for power-on 200us end of stable period 8 | `define I_PRE 4'd1 //Precharge state 9 | `define I_TRP 4'd2 //Waiting for precharge to complete tRP 10 | `define I_AR1 4'd3 //The first self-refresh 11 | `define I_TRF1 4'd4 //Waiting for the end of the first self-refresh tRFC 12 | `define I_AR2 4'd5 //2nd self-refresh 13 | `define I_TRF2 4'd6 //Waiting for the second self-refresh to end tRFC 14 | `define I_MRS 4'd7 //Mode register setting 15 | `define I_TMRD 4'd8 //Waiting mode register setting is complete tMRD 16 | `define I_DONE 4'd9 //loading finished 17 | 18 | 19 | //Delay parameter 20 | `define end_trp cnt_clk_r == TRP_CLK 21 | `define end_trfc cnt_clk_r == TRFC_CLK 22 | `define end_tmrd cnt_clk_r == TMRD_CLK 23 | `define end_trcd cnt_clk_r == TRCD_CLK-1 24 | `define end_tcl cnt_clk_r == `cas_latency-1 25 | `define end_rdburst cnt_clk == sdrd_byte-4//TREAD_CLK-4 //Issue a burst read interrupt command 26 | `define end_tread cnt_clk_r == sdrd_byte+2//TREAD_CLK+2 //TREAD_CLK+2 27 | `define end_wrburst cnt_clk == sdwr_byte-1//TWRITE_CLK-1 //Issue a burst write interrupt command 28 | `define end_twrite cnt_clk_r == sdwr_byte-1//TWRITE_CLK-1 29 | `define end_tdal cnt_clk_r == TDAL_CLK 30 | `define end_trwait cnt_clk_r == TRP_CLK 31 | 32 | //команды смены состояния 33 | // CKE CS RAS CAS WE 34 | `define CMD_INIT 5'b01111 // инициализация - CKE=0 CS=1 35 | `define CMD_NOP 5'b10111 // ожидание команды - CKE=1 CS=0 36 | `define CMD_ACTIVE 5'b10011 // начало команды(RAS) - RAS=0 CAS=1 WE=1 37 | `define CMD_READ 5'b10101 // чтение RAS=1 CAS=0 WE=1 38 | `define CMD_WRITE 5'b10100 // запись RAS=1 CAS=0 WE=0 39 | `define CMD_B_STOP 5'b10110 // конец цепочки обмена RAS=1 CAS=1 WE=0 40 | `define CMD_PRGE 5'b10010 // закрытие строки - RAS=0 CAS=1 WE=0 41 | `define CMD_A_REF 5'b10001 // саморегенераци - RAS=0 CAS=0 WE=1 42 | `define CMD_LMR 5'b10000 // загрузка регистра управления - RAS=0 CAS=0 WE=0 43 | 44 | 45 | //endmodule 46 | -------------------------------------------------------------------------------- /hdl/sdram_ip/sdram_wr_data.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////////////////////////////// 3 | // Description : SDRAM data read and write module 4 | //////////////////////////////////////////////////////////////////////////////// 5 | module sdram_wr_data( 6 | clk,rst_n, 7 | /*sdram_clk,*/sdram_data, 8 | sys_data_in,sys_data_out, 9 | work_state,cnt_clk 10 | ); 11 | //System signal 12 | input clk; //System clock, 100MHz 13 | input rst_n; //Reset signal, active low 14 | // SDRAM hardware interface 15 | //output sdram_clk; // SDRAM clock signal 16 | inout[15:0] sdram_data; // SDRAM data bus 17 | // SDRAM package interface 18 | input[15:0] sys_data_in; //Data register when writing SDRAM 19 | output[15:0] sys_data_out; //Data register when reading SDRAM 20 | 21 | // SDRAM internal interface 22 | input[3:0] work_state; //Data status register when reading and writing SDRAM 23 | input[8:0] cnt_clk; //Clock count 24 | 25 | `include "sdram_para.v" // Contains SDRAM parameter definition module 26 | 27 | // Варианты рабочих состояний 28 | parameter[3:0] W_ACTIVE= 4'd1 ; //Valid, read and write 29 | parameter[3:0] W_TRCD = 4'd2 ; //Waiting effectively 30 | parameter[3:0] W_IDLE = 4'd0 ; //Idle state 31 | //*********************************************************** 32 | parameter[3:0] W_READ= 4'd3 ; //Read data status 33 | parameter[3:0] W_CL = 4'd4; //Waiting for latency 34 | parameter[3:0] W_RD = 4'd5 ; //Reading data 35 | parameter[3:0] W_RWAIT= 4'd6 ; //Precharge wait state after reading is completed 36 | //************************************************************ 37 | parameter[3:0] W_WRITE = 4'd7 ; //Write data status 38 | parameter[3:0] W_WD = 4'd8 ; //Write data 39 | parameter[3:0] W_TDAL = 4'd9 ; //Waiting to write data and end self-refresh 40 | //************************************************************* 41 | parameter[3:0] W_AR = 4'd10 ; //Self refresh 42 | parameter[3:0] W_TRFC = 4'd11; //Self-refresh waiting 43 | 44 | //------------------------------------------------------------------------------ 45 | //Data write control 46 | //------------------------------------------------------------------------------ 47 | reg[15:0] sdr_din; //Burst data write register 48 | reg sdr_dlink; // SDRAM data bus input and output control 49 | 50 | //Send the data to be written to the SDRAM data bus 51 | always @ (posedge clk or negedge rst_n) 52 | if(!rst_n) sdr_din <= 16'd0; //Burst data write register reset 53 | else if((work_state == W_WRITE) | (work_state == W_WD)) sdr_din <= sys_data_in; //Continuously write 256 16-bit data stored in wrFIFO 54 | 55 | //Generate bidirectional data line direction control logic 56 | always @ (posedge clk or negedge rst_n) 57 | if(!rst_n) sdr_dlink <= 1'b0; 58 | else if((work_state == W_WRITE) | (work_state == W_WD)) sdr_dlink <= 1'b1; 59 | else sdr_dlink <= 1'b0; 60 | 61 | assign sdram_data = sdr_dlink ? sdr_din:16'hzzzz; 62 | 63 | //------------------------------------------------------------------------------ 64 | //Data readout control 65 | //------------------------------------------------------------------------------ 66 | reg[15:0] sdr_dout; //Burst data read register 67 | 68 | //Read data from SDRAM 69 | always @ (posedge clk or negedge rst_n) 70 | if(!rst_n) sdr_dout <= 16'd0; //Burst data read register reset 71 | else if((work_state == W_RD)/* & (cnt_clk > 9'd0) & (cnt_clk < 9'd10)*/) sdr_dout <= sdram_data; //Continuously read 8B 16bit data storage to rdFIFO 72 | 73 | assign sys_data_out = sdr_dout; 74 | 75 | //------------------------------------------------------------------------------ 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /hdl/vm1/vm1_reg.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2014-2019 by 1801BM1@gmail.com 3 | // 4 | // 1801VM1 Register File and Constant Generator (64x16 Dual-Port RAM/ROM) 5 | //______________________________________________________________________________ 6 | // 7 | // Generic implementation of Register File and Constant Generator, memory blocks 8 | // are assumed to be inferred. Some verions of synthesys tools (Quartus, etc.) 9 | // do not infer memory blocks correctly, so explicit RAM megafunction should be 10 | // used, depending on device type. It provides much better Fmax and resource 11 | // usage. If vendor specific memory function is used this file should not be 12 | // included in project. 13 | // 14 | // Interface is compatible with Altera Dual-Port Single Clock RAM. 15 | // Writing on Port B is not used, because Port B is for ROM only. 16 | // 17 | module vm1_vcram( 18 | input [5:0] address_a, 19 | input [5:0] address_b, 20 | input [1:0] byteena_a, 21 | input clock, 22 | input [15:0] data_a, 23 | input [15:0] data_b, 24 | input wren_a, 25 | input wren_b, 26 | output reg [15:0] q_a, 27 | output reg [15:0] q_b); 28 | 29 | reg [15:0] ram[63:0]; 30 | // 31 | // Set initial content for Constant and Vector Generator 32 | // 33 | initial 34 | begin 35 | ram[ 0] = 16'O000000; 36 | ram[ 1] = 16'O000000; 37 | ram[ 2] = 16'O000000; 38 | ram[ 3] = 16'O000000; 39 | ram[ 4] = 16'O000000; 40 | ram[ 5] = 16'O000000; 41 | ram[ 6] = 16'O000000; 42 | ram[ 7] = 16'O000000; 43 | 44 | ram[ 8] = 16'O000000; 45 | ram[ 9] = 16'O000000; 46 | ram[10] = 16'O000000; 47 | ram[11] = 16'O000000; 48 | ram[12] = 16'O000000; 49 | ram[13] = 16'O000000; 50 | ram[14] = 16'O000000; 51 | ram[15] = 16'O000000; 52 | 53 | ram[16] = 16'O160006; 54 | ram[17] = 16'O000020; 55 | ram[18] = 16'O000010; 56 | ram[19] = 16'O000014; 57 | ram[20] = 16'O000004; 58 | ram[21] = 16'O177716; 59 | ram[22] = 16'O000030; 60 | ram[23] = 16'O160012; 61 | 62 | ram[24] = 16'O000270; 63 | ram[25] = 16'O000024; 64 | ram[26] = 16'O000100; 65 | ram[27] = 16'O160002; 66 | ram[28] = 16'O000034; 67 | ram[29] = 16'O000000; 68 | ram[30] = 16'O000000; 69 | ram[31] = 16'O000000; 70 | 71 | ram[32] = 16'O000000; 72 | ram[33] = 16'O000340; 73 | ram[34] = 16'O000000; 74 | ram[35] = 16'O000002; 75 | ram[36] = 16'O000000; 76 | ram[37] = 16'O177716; 77 | ram[38] = 16'O177777; 78 | ram[39] = 16'O000001; 79 | 80 | ram[40] = 16'O000000; 81 | ram[41] = 16'O100000; 82 | ram[42] = 16'O177676; 83 | ram[43] = 16'O000020; 84 | ram[44] = 16'O000000; 85 | ram[45] = 16'O177400; 86 | ram[46] = 16'O000010; 87 | ram[47] = 16'O000000; 88 | 89 | ram[48] = 16'O000000; 90 | ram[49] = 16'O000000; 91 | ram[50] = 16'O000000; 92 | ram[51] = 16'O000000; 93 | ram[52] = 16'O000000; 94 | ram[53] = 16'O000000; 95 | ram[54] = 16'O000000; 96 | ram[55] = 16'O000000; 97 | 98 | ram[56] = 16'O000000; 99 | ram[57] = 16'O000000; 100 | ram[58] = 16'O000000; 101 | ram[59] = 16'O000000; 102 | ram[60] = 16'O000000; 103 | ram[61] = 16'O000000; 104 | ram[62] = 16'O000000; 105 | ram[63] = 16'O000000; 106 | end 107 | 108 | always @ (posedge clock) 109 | begin 110 | if (wren_a) 111 | begin 112 | if (byteena_a[0]) ram[address_a][7:0] <= data_a[7:0]; 113 | if (byteena_a[1]) ram[address_a][15:8] <= data_a[15:8]; 114 | end 115 | q_a <= ram[address_a]; 116 | if (wren_b) 117 | ram[address_b]<= data_b; 118 | q_b <= ram[address_b]; 119 | end 120 | endmodule 121 | -------------------------------------------------------------------------------- /hdl/vm3/vm3_mmu.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2014-2024 by 1801BM1@gmail.com 3 | // 4 | // Memory Managment Unit Register File 5 | //______________________________________________________________________________ 6 | // 7 | // Generic implementation of Register File, memory blocks are supposed to be 8 | // inferred. Some verions of synthesys tools (Quartus, etc.) do not infer memory 9 | // blocks correctly, so explicit RAM megafunction should be used, depending on 10 | // device type. It provides much better Fmax and resource usage. If vendor 11 | // specific memory function is used this file should not be included in 12 | // the project. 13 | // 14 | // Interface is compatible with Altera Dual-Port Single Clock RAM with 15 | // byte lane enable strobes. 16 | // 17 | // Port A is used to access MMU registers from CPU bus and to present page 18 | // address register (PAR) content on address translation cycle. Port B is used 19 | // to present page descriptor register (PDR) content for address translation only. 20 | // Actually, write enable for port B is not used. 21 | // 22 | module vm3_mmu ( 23 | input clock, 24 | input [4:0] address_a, 25 | input [4:0] address_b, 26 | input [1:0] byteena_a, 27 | input [1:0] byteena_b, 28 | input [15:0] data_a, 29 | input [15:0] data_b, 30 | output [15:0] q_a, 31 | output [15:0] q_b, 32 | input wren_a, 33 | input wren_b 34 | ); 35 | 36 | reg [15:0] ram[31:0]; 37 | reg [5:0] addr_a; 38 | reg [5:0] addr_b; 39 | 40 | //______________________________________________________________________________ 41 | // 42 | // Minimal required registers initalization, otherwise, 43 | // undefined content would prevent simulation. 44 | // 45 | integer i; 46 | initial 47 | begin 48 | for (i=0; i<32; i = i+1) 49 | ram[i] = 16'h0000; 50 | end 51 | 52 | //______________________________________________________________________________ 53 | // 54 | always @ (posedge clock) 55 | begin 56 | addr_a = address_a; 57 | if (wren_a) 58 | begin 59 | if (byteena_a[0]) ram[addr_a][7:0] = data_a[7:0]; 60 | if (byteena_a[1]) ram[addr_a][15:8] = data_a[15:8]; 61 | end 62 | 63 | addr_b = address_b; 64 | if (wren_b) 65 | begin 66 | if (byteena_b[0]) ram[addr_b][7:0] = data_b[7:0]; 67 | if (byteena_b[1]) ram[addr_b][15:8] = data_b[15:8]; 68 | end 69 | end 70 | 71 | assign q_a = ram[addr_a]; 72 | assign q_b = ram[addr_b]; 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /hdl/wbc_rst.v: -------------------------------------------------------------------------------- 1 | //************************************************************** 2 | //* Моудль генерации сбросов 3 | //************************************************************** 4 | module wbc_rst #(parameter 5 | 6 | OSCCLK=50000000, // входяшая тактовая частота платы 7 | PWR_WIDTH=10, // minimal Power Reset width in system ticks 8 | DCLO_WIDTH=15, // длительность импльса DCLO 9 | ACLO_DELAY=7, // задержка снятия ACLO после DCLO 10 | DEBOUNCE=5 // задержка для подавления дребезга кнопки сброса в миллисекундах 11 | ) 12 | ( 13 | input osc_clk, // входяшая тактовая частота платы 14 | input sys_clk, // тактовая частота процессора 15 | input pll_lock, // готовность PLL 16 | input button, // сигнал аппаратного сброса (кнопка) 17 | input sys_ready, // вход готовности внешних системных компонентов 18 | // 19 | output reg sys_dclo, // DCLO output 20 | output reg sys_aclo, // ACLO output 21 | output global_reset // Выход сигнала сброса без учета sys_read, 1 - сброс, 0 - работа 22 | ); 23 | localparam DB_COUNTER_WIDTH = log2(DEBOUNCE); 24 | localparam OS_COUNTER_WIDTH = log2(OSCCLK/1000); 25 | 26 | localparam PW_COUNTER_WIDTH = log2(PWR_WIDTH); 27 | localparam DC_COUNTER_WIDTH = log2(DCLO_WIDTH); 28 | localparam AC_COUNTER_WIDTH = log2(ACLO_DELAY); 29 | 30 | reg [DB_COUNTER_WIDTH-1:0] count_db; 31 | reg [OS_COUNTER_WIDTH-1:0] count_os; 32 | 33 | reg [PW_COUNTER_WIDTH-1:0] count_pw; 34 | reg [DC_COUNTER_WIDTH-1:0] count_dc; 35 | reg [AC_COUNTER_WIDTH-1:0] count_ac; 36 | 37 | reg osc_ms; 38 | reg pll_reg; 39 | reg but_reg; 40 | reg key_down; 41 | 42 | reg pwr_rst; // power reset - сброс с задержкой PWR_WIDTH 43 | reg sys_rst; // system reset - сброс с ожиданием готовности 44 | 45 | 46 | reg [1:0] key_syn; 47 | reg pwr_event; 48 | wire key_event; 49 | 50 | assign global_reset=key_event; 51 | //______________________________________________________________________________ 52 | // 53 | // Oscillator clock domain - button and PLL failure detectors 54 | // 55 | always @(posedge osc_clk) 56 | begin 57 | if (count_os < ((OSCCLK/1000)-1)) 58 | begin 59 | count_os <= count_os + 1'b1; 60 | osc_ms <= 1'b0; 61 | end 62 | else 63 | begin 64 | count_os <= 0; 65 | osc_ms <= 1'b1; 66 | end 67 | end 68 | // 69 | // External button debouncer 70 | // 71 | always @(posedge osc_clk) 72 | begin 73 | if (~but_reg | ~pll_reg) 74 | begin 75 | count_db <= 0; 76 | key_down <= 1'b1; 77 | end 78 | else 79 | if (osc_ms) 80 | begin 81 | if (count_db < (DEBOUNCE-1)) 82 | count_db <= count_db + 1'b1; 83 | else 84 | key_down <= 1'b0; 85 | end 86 | pll_reg <= pll_lock; 87 | but_reg <= button; 88 | pwr_event <= ~pll_reg; 89 | end 90 | //______________________________________________________________________________ 91 | // 92 | // System clock domain metastability synchronizers 93 | // 94 | always @(posedge sys_clk) 95 | begin 96 | key_syn[0] <= key_down; 97 | key_syn[1] <= key_syn[0]; 98 | end 99 | assign key_event = key_syn[1]; 100 | 101 | always @(posedge sys_clk or posedge pwr_event) 102 | begin 103 | if (pwr_event) 104 | begin 105 | count_pw <= 0; 106 | count_dc <= 0; 107 | count_ac <= 0; 108 | 109 | pwr_rst <= 1'b1; 110 | sys_rst <= 1'b1; 111 | sys_dclo <= 1'b1; 112 | sys_aclo <= 1'b1; 113 | end 114 | else 115 | begin 116 | // 117 | // Power Reset deassertion delay after Power Event 118 | // 119 | if (count_pw < (PWR_WIDTH-1)) 120 | count_pw <= count_pw + 1'b1; 121 | else 122 | pwr_rst <= 1'b0; 123 | // 124 | // Assert System Reset if button is pressed 125 | // 126 | if (key_event) 127 | begin 128 | count_dc <= 0; 129 | count_ac <= 0; 130 | sys_rst <= 1'b1; 131 | sys_dclo <= 1'b1; 132 | sys_aclo <= 1'b1; 133 | end 134 | // 135 | // System Reset waits for System Ready 136 | // Some system components may require time to complete 137 | // its internal initialization, for example, memory 138 | // controller may initialize the SDRAM chips. 139 | // 140 | if (~pwr_rst & sys_ready & ~key_event) 141 | sys_rst <= 1'b0; 142 | // 143 | // DCLO and ACLO synchronous deassertions 144 | // 145 | if (~pwr_rst & ~sys_rst & ~key_event) 146 | begin 147 | // 148 | // Count the DCLO pulse 149 | // 150 | if (count_dc < (DCLO_WIDTH-1)) 151 | count_dc <= count_dc + 1'b1; 152 | else 153 | sys_dclo <= 1'b0; 154 | // 155 | // After DCLO deassertion start ACLO counter 156 | // 157 | if (~sys_dclo) 158 | if (count_ac < (ACLO_DELAY-1)) 159 | count_ac <= count_ac + 1'b1; 160 | else 161 | sys_aclo <= 1'b0; 162 | end 163 | end 164 | end 165 | 166 | function integer log2(input integer value); 167 | begin 168 | for (log2=0; value>0; log2=log2+1) 169 | value = value >> 1; 170 | end 171 | endfunction 172 | 173 | endmodule 174 | -------------------------------------------------------------------------------- /hdl/wbc_vic.v: -------------------------------------------------------------------------------- 1 | //****************************************************** 2 | //* Контроллер прерываний 3 | //****************************************************** 4 | 5 | module wbc_vic 6 | #(parameter N=1) // количество векторов 7 | ( 8 | input wb_clk_i, // system clock 9 | input wb_rst_i, // peripheral reset 10 | output reg wb_irq_o, // запрос прерывания к процессору 11 | output reg [15:0] wb_dat_o, // шина для передачи вектора прерывания к процессору 12 | input wb_stb_i, // строб от прецессора для приема вектора 13 | output reg wb_ack_o, // подтверждение передачи вектора процессору 14 | // 15 | input [N*16-1:0] ivec, // массив значений векторов прерывания 16 | input [N-1:0] ireq, // линии запроса прерывания 17 | output reg [N-1:0] iack // линии подтверждения прерывания 18 | ); 19 | localparam W = log2(N); // число бит для записи номера вектора 20 | 21 | reg [W-1:0] nvec; // номер прерывания с наивысшим приоритетом, или 0 если активных прерываний нет. 22 | integer i; 23 | 24 | always @(posedge wb_clk_i or posedge wb_rst_i) 25 | begin 26 | if (wb_rst_i) 27 | begin 28 | // сброс контроллера 29 | wb_ack_o <= 1'b0; 30 | wb_dat_o <= 16'O000000; 31 | iack <= 0; 32 | nvec <= {(W){1'b1}}; // nvec заполнен единицами при отсутствии прерывания 33 | end 34 | else 35 | // обработка запросов на прерывания 36 | begin 37 | // сигнал подтверждения запроса вектора 38 | wb_ack_o <= wb_stb_i & // в ответ на строб от процессора 39 | wb_irq_o & // если мы выставляем вектор 40 | ~wb_ack_o; // если строб уже был выставлен в предыдущем такте - то снимаем его 41 | 42 | // сигнал запроса векторного прерывания 43 | wb_irq_o <= ~(&nvec) & // если есть активный ветор 44 | ~wb_ack_o; // и если вектор еще не передан 45 | 46 | // сигнал подтверждения прерывания к периферийному устройству 47 | for (i=N-1; i>=0; i=i-1) 48 | iack[i] <= 49 | (nvec == i) // это текущая линия обработки прерывания 50 | & ireq[i] // был запрос на прерывание 51 | & wb_stb_i // был строб от процессора - он готов принять вектор 52 | & wb_irq_o // уже выставлен запрос векторного прерывания к процессору 53 | & ~iack[i]; // если сигнал в предыдущем такте выставлен - снимаем 54 | 55 | // выставляем вектор на шину 56 | if (wb_stb_i & ~wb_ack_o & wb_irq_o) // пришел строб от прецессора и еще не выставлено подтверждение 57 | // передача вектора прерывания 58 | wb_dat_o <= trunc_w16(ivec >> (nvec*16)); 59 | 60 | if (~wb_stb_i) 61 | begin 62 | nvec <= {(W){1'b1}}; 63 | for (i=N-1; i>=0; i=i-1) 64 | if (ireq[i]) nvec <= trunc_int(i); 65 | end 66 | else 67 | if (wb_ack_o) nvec <= {(W){1'b1}}; 68 | end 69 | end 70 | 71 | function integer log2(input integer value); 72 | for (log2=0; value>0; log2=log2+1) 73 | value = value >> 1; 74 | endfunction 75 | 76 | function [15:0] trunc_w16(input [N*16-1:0] value); 77 | trunc_w16 = value[15:0]; 78 | endfunction 79 | 80 | function [W-1:0] trunc_int(input integer value); 81 | trunc_int = value[W-1:0]; 82 | endfunction 83 | endmodule 84 | -------------------------------------------------------------------------------- /ksm-firmware/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | ./macro11 -o ksm-firmware.obj -l ksm-firmware.lst ksm-firmware.mac 3 | ./rt11obj2bin ksm-firmware.obj > ksm-firmware.map 4 | srec_cat ksm-firmware.obj.bin -binary --byte-swap 2 -fill 0x00 0x0000 0x1000 -o ksm-firmware.mif -Memory_Initialization_File 16 -obs=2 5 | #srec_cat ksm-firmware.obj.bin -binary --byte-swap 2 -o ksm-firmware.mem -Vmem 16 -obs=2 6 | -------------------------------------------------------------------------------- /ksm-firmware/font/Makefile: -------------------------------------------------------------------------------- 1 | all: font2mif fontextract fontlist fontreplace font.mif font-ksm.mif 2 | font2mif: font2mif.c 3 | fontextract: fontextract.c 4 | fontlist: fontlist.c 5 | fontreplace: fontreplace.c 6 | font.mif: font-main.bin 7 | ./font2mif font-main.bin font-main.mif 8 | ./font2mif font-ksm.bin font-ksm.mif 9 | font-main.mif: font-main.bin 10 | ./font2mif font-main.bin font-main.mif 11 | font-ksm.mif: font-ksm.bin 12 | ./font2mif font-ksm.bin font-ksm.mif 13 | 14 | -------------------------------------------------------------------------------- /ksm-firmware/font/font-ksm.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/ksm-firmware/font/font-ksm.bin -------------------------------------------------------------------------------- /ksm-firmware/font/font-main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/ksm-firmware/font/font-main.bin -------------------------------------------------------------------------------- /ksm-firmware/font/font2mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/ksm-firmware/font/font2mif -------------------------------------------------------------------------------- /ksm-firmware/font/font2mif.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | void main(int argc, char* argv[]) { 4 | 5 | uint8_t buf[8]; 6 | uint8_t ch; 7 | int bit,bitpos; 8 | 9 | uint32_t adr; 10 | uint8_t prev=2; 11 | 12 | if (argc<3) { 13 | printf("\n Преобразователь двоичного файла шрифтов в формат Altera MIF для загрузки в память FPGA\n\ 14 | Формат команды:\n %s infile.bin outfile.mif\n\n",argv[0]); 15 | return; 16 | } 17 | 18 | FILE* in=fopen(argv[1],"r"); 19 | if (in == 0) { 20 | printf("Ошибка открытия входного файла %s\n",argv[1]); 21 | return; 22 | } 23 | FILE* out=fopen(argv[2],"w"); 24 | if (out == 0) { 25 | printf("Ошибка открытия выходного файла %s\n",argv[1]); 26 | return; 27 | } 28 | 29 | // MIF-заголовок 30 | fprintf(out,"WIDTH=1;\nDEPTH=32768;\nADDRESS_RADIX=HEX;\nDATA_RADIX=BIN;\n\nCONTENT BEGIN"); 31 | 32 | for(adr=0;adr<32768;adr++) { 33 | if (adr<24576) { 34 | bitpos=adr&7; 35 | if (bitpos == 0) ch=fgetc(in); // через каждые обработанные 8 бит загружаем очередной байт 36 | bit=(ch>>bitpos)&1; // выделяем очередной бит 37 | fprintf(out,"\n%04x: %1i;",adr,bit); // и выводим в mif его значение 38 | } 39 | else fprintf(out,"\n%04x: 0;",adr); // заполняем неиспользуемый хвост нулями 40 | } 41 | // MIF-терминатор 42 | fprintf(out,"\nEND;\n"); 43 | } 44 | -------------------------------------------------------------------------------- /ksm-firmware/font/fontextract: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/ksm-firmware/font/fontextract -------------------------------------------------------------------------------- /ksm-firmware/font/fontextract.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | void main(int argc,char* argv[]) { 7 | 8 | FILE* in; 9 | FILE* out; 10 | uint32_t pos; 11 | uint32_t y,x,bit,byte,off,r,i; 12 | uint8_t ch; 13 | char filename[20]; 14 | int32_t code=-1; 15 | 16 | uint8_t font[3072]; 17 | 18 | if (argc<2) { 19 | printf(" Программа предназначена для преобразования двоичного файла шрифтов в набор текстовых образов\n\ 20 | Все образы складываются в каталог out/ под именем xx.fnt, xx - позиция шрифта в исходном файле\n\ 21 | Запуск: %s [code]\n\ 22 | code - позиция исзвлекаемого символа, если не указано - извлекаются все символы\n",argv[0]); 23 | return; 24 | } 25 | in=fopen(argv[1],"r"); 26 | if (in == 0) { 27 | printf("Ошибка открытия фходного файла %s\n",argv[1]); 28 | return; 29 | } 30 | fread(font,1,3072,in); 31 | fclose(in); 32 | // 33 | // bit byte 34 | // R R R R C C C d d d d d d d d 35 | // 36 | // R - row 0 - 11 37 | // C - col 0 - 7 38 | // d - char 0 - 256 39 | 40 | mkdir ("out",0777); 41 | if (argc > 2) sscanf(argv[2],"%x",&code); 42 | 43 | for(pos=0;pos<256;pos++) { 44 | if ((pos != code) && (code != -1)) continue; 45 | sprintf(filename,"out/%02x.fnt",pos); 46 | out=fopen(filename,"w"); 47 | for(y=0;y<12;y++) { 48 | for(x=0;x<8;x++) { 49 | bit=(y<<11)|(x<<8)|pos; 50 | byte=bit>>3; 51 | ch=font[byte]; 52 | off=bit&7; 53 | r=(ch>>off)&1; 54 | if (r != 0) fprintf(out,"O"); 55 | else fprintf(out,"."); 56 | } 57 | fprintf(out,"\n"); 58 | } 59 | fclose(out); 60 | } 61 | } 62 | -------------------------------------------------------------------------------- /ksm-firmware/font/fontlist: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/ksm-firmware/font/fontlist -------------------------------------------------------------------------------- /ksm-firmware/font/fontlist.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | void main(int argc,char* argv[]) { 5 | 6 | uint32_t pos; 7 | uint32_t y,x,bit,byte,off,r,i; 8 | uint8_t ch; 9 | int code=-1; 10 | 11 | uint8_t font[3072]; 12 | 13 | if (argc<2) { 14 | printf(" Программа для просмотра образов шрифтов, содержащихся в двоичном шрифтовом файле\n\ 15 | Запуск: %s [code]\n\ 16 | code - позиция просматриваемого символа, если не указан - выводятся образы всех символов\n",argv[0]); 17 | return; 18 | } 19 | FILE* in=fopen(argv[1],"r"); // font.dat 20 | if (in == 0) { 21 | printf("Ошибка открытия входного файла %s\n",argv[1]); 22 | return; 23 | } 24 | fread(font,1,3072,in); 25 | fclose(in); 26 | 27 | if (argc>2) sscanf(argv[2],"%x",&code); 28 | // 29 | // bit byte 30 | // R R R R C C C d d d d d d d d 31 | // 32 | // R - row 0 - 11 33 | // C - col 0 - 7 34 | // d - char 0 - 256 35 | 36 | //sscanf(argv[1],"%x",&pos); 37 | //if(pos>255) return; 38 | 39 | 40 | for(pos=0;pos<256;pos++) { 41 | 42 | if (pos == code || code == -1) { 43 | printf("\n\n --- Позиция %02x ---",pos); 44 | printf("\n 01234567"); 45 | for(y=0;y<12;y++) { 46 | printf("\n %02i: ",y); 47 | for(x=0;x<8;x++) { 48 | bit=(y<<11)|(x<<8)|pos; 49 | byte=bit>>3; 50 | ch=font[byte]; 51 | off=bit&7; 52 | r=(ch>>off)&1; 53 | if (r != 0) printf("@"); 54 | else printf("."); 55 | } 56 | } 57 | printf("\n"); 58 | } 59 | } 60 | } 61 | -------------------------------------------------------------------------------- /ksm-firmware/font/fontreplace: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/ksm-firmware/font/fontreplace -------------------------------------------------------------------------------- /ksm-firmware/font/fontreplace.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | void main(int argc,char* argv[]) { 5 | 6 | FILE* in; 7 | FILE* fch; 8 | uint32_t pos; 9 | uint32_t y,x,bit,byte,off,r,i; 10 | uint8_t ch; 11 | char filename[20]; 12 | 13 | uint8_t font[3072]; 14 | int code=-1; 15 | char str[20]; 16 | 17 | if (argc<2) { 18 | printf(" Программа для замены отдельных символов в двоичном шрифтовом файле.\n\ 19 | Запуск: %s [code]\n\n\ 20 | code - позиция заменяемого символа, если не указан - заменяются символы всех найденных файлов-образов\n\n\ 21 | Файлы-образы должны лежать в текущем каталоге. Они имеют имя xx.fnt, где xx - hex-номер позиции символа\n\n",argv[0]); 22 | return; 23 | } 24 | 25 | 26 | in=fopen(argv[1],"r+"); 27 | if (in == 0) { 28 | printf("Ошибка открытия входного файла %s\n",argv[1]); 29 | return; 30 | } 31 | 32 | if (argc>2) sscanf(argv[2],"%x",&code); 33 | 34 | fread(font,1,3072,in); 35 | // 36 | // bit byte 37 | // R R R R C C C d d d d d d d d 38 | // 39 | // R - row 0 - 11 40 | // C - col 0 - 7 41 | // d - char 0 - 256 42 | 43 | for(pos=0;pos<256;pos++) { 44 | if (code != pos && code != -1) continue; 45 | sprintf(filename,"%02x.fnt",pos); 46 | fch=fopen(filename,"r"); 47 | if (fch == 0) { 48 | if (code != -1) { 49 | printf("Файл %s не найден\n",filename); 50 | return; 51 | } 52 | continue; 53 | } 54 | printf("Замена шрифта %02x\n",pos); 55 | for(y=0;y<12;y++) { 56 | fgets(str,20,fch); 57 | if (feof(in)) { 58 | printf("\n Неожиданный конец файла %s\n",filename); 59 | return; 60 | } 61 | for(x=0;x<8;x++) { 62 | bit=(y<<11)|(x<<8)|pos; 63 | byte=bit>>3; 64 | ch=font[byte]; 65 | off=bit&7; 66 | if ((str[x] != '.')&&(str[x] != ' ')) font[byte] |= (1< 2 | #include 3 | void main (int argc, char* argv[]) { 4 | 5 | uint16_t rbuf[4096]; 6 | uint32_t sum=0; 7 | int i; 8 | 9 | if (argc<2) return; 10 | FILE* rom=fopen(argv[1],"r+"); 11 | if (rom == 0) return; 12 | 13 | fread(rbuf,1,8192,rom); 14 | for(i=0;i<013776/2;i++) { 15 | sum+=rbuf[i]; 16 | if ((sum&0x10000) != 0) { 17 | sum&=0xffff; 18 | sum++; 19 | } 20 | } 21 | printf("sum = %06o\n",sum); 22 | rbuf[013776/2]=sum; 23 | fseek(rom,0,SEEK_SET); 24 | fwrite(rbuf,1,8192,rom); 25 | fclose(rom); 26 | } 27 | -------------------------------------------------------------------------------- /rom/conv.sh: -------------------------------------------------------------------------------- 1 | srec_cat 000.bin -binary --byte-swap 2 -o 000.mif -Memory_Initialization_File 16 -obs=2 2 | srec_cat 055.bin -binary --byte-swap 2 -o 055.mif -Memory_Initialization_File 16 -obs=2 3 | srec_cat 279.bin -binary --byte-swap 2 -o 279.mif -Memory_Initialization_File 16 -obs=2 4 | srec_cat 377.bin -binary --byte-swap 2 -o 377.mif -Memory_Initialization_File 16 -obs=2 5 | ./checksum-134 134.bin 6 | srec_cat 134.bin -binary --byte-swap 2 -o 134.mif -Memory_Initialization_File 16 -obs=2 7 | srec_cat 013-basic.bin -binary --byte-swap 2 -o 013-basic.mif -Memory_Initialization_File 16 -obs=2 8 | srec_cat 058-focal.bin -binary --byte-swap 2 -o 058-focal.mif -Memory_Initialization_File 16 -obs=2 9 | 10 | -------------------------------------------------------------------------------- /rom/f11/000.rom: -------------------------------------------------------------------------------- 1 | /* http://srecord.sourceforge.net/ */ 2 | @00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3 | @00000008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4 | @00000010 00F1CBFF 00F2BBAA 00E709F3 00F4EEAE 00F50983 00F6701E 00F78CEE 00F80AF9 5 | @00000018 00FAB2FE 00FAA2FE 00FB8CCC 00FCBBAA 00F609FD 00FE88EA 00FF8ECA 017A9EAA 6 | @00000020 0000E298 0000E698 0173141A 0174D28E 0175C28F 0176171A 017792FF 01789AEF 7 | @00000028 01AE0A79 00FA211A 017C0E7B 017CA2FE 017D88BB 017F0A7E 017F92EE 01F6C2EC 8 | @00000030 01270FFF 012B1228 012C1446 01722C0A 0172201A 01300F2B 01F740C9 01F81109 9 | @00000038 01FA0CF9 01FA92AA 01FBF0AA 01FCEAAB 01FE08FD 01AE0DFE 012BC0AC 0126130F 10 | @00000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11 | @00000048 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 12 | @00000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 13 | @00000058 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 14 | @00000060 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 15 | @00000068 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16 | @00000070 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 17 | @00000078 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 18 | @00000080 00AB0989 0082C27E 00E2CAFF 01DD248A 00F7258A 00A9278A 0087EEFF 01D7288A 19 | @00000088 0080757F 008AC3FA 008BEEFF 008C110F 001C670A 008E8AEE 008F8AEE 00908AEE 20 | @00000090 0091A3AE 0086502F 01E3248A 00941208 01231467 01E3269A 00ABC2E7 0106CA99 21 | @00000098 00AAEFF9 009AC3F9 009B2A0E 009C117B 009D1589 009ED38F 01E32F9A 00A0BBEE 22 | @000000A0 009B0984 00A28A99 00A38A99 00A4EE99 00A56309 00A6E69F 00C1C2E9 00A82AAA 23 | @000000A8 00A9EFFA 01E3204F 01D7410A 01E3410A 00AD6F7F 00AE3F2F 008909AF 00B0EEAF 24 | @000000B0 00B1502F 00C16B2F 00B8780F 00B4C39F 00EF25BA 00B62F2F 01E327BA 00B0C2EF 25 | @000000B8 00B909BF 00BA3F39 00BB09A7 00BCAA99 00BD6709 00BEC2FE 00AB225F 00C04209 26 | @000000C0 00E0C29E 00C2780F 00C309C8 00C43F39 00C509C7 00C61109 00E2C2DE 00E2C28E 27 | @000000C8 00C9117F 00CA1789 00E2D28E 00CC502F 01E32DCA 00CEC2EF 00CF503F 00D040EF 28 | @000000D0 0086CAEE 00D2702F 00D309F7 00D4780F 00D509DC 00D63F39 00D709D9 00D81109 29 | @000000D8 00F7C2ED 00DAEAE8 00DB6018 00F7EAE8 00DD117F 00DE1B89 00F7100E 01FD133A 30 | @000000E0 00E1EEFA 00E4630F 00E3EEFA 00E4CBFF 00E5C28B 00E6CBAA 00EC560A 00E8C28B 31 | @000000E8 00E988EE 00EA8FFF 00EB88EE 00EC8FFF 00ED88EE 00EE8FFF 00EFC2B8 01E3503F 32 | @000000F0 00F1CBFF 00F2BBAA 00E709F3 00F4EEAE 00F50983 00F6701E 00B509CB 00F8C3AE 33 | @000000F8 00F9EFFE 00FA2D0F 01E32BFA 00AB2A0F 00FDEEEF 00FEC3EA 00DFCAEE 00922F3F 34 | @00000100 0101D789 01000802 01036309 012548F9 01052109 0106EE99 0107CA88 01081218 35 | @00000108 01091218 013110A8 010B7089 010D090C 010FCB77 010E26F7 010FEE77 015420E8 36 | @00000110 011108FD 01128ABB 01140813 01162406 01158ABB 0116082B 0117240A 0118204B 37 | @00000118 0172EEBB 011A08FD 01722C4A 011C091D 01722C0A 012B1218 0172241A 0172204A 38 | @00000120 0121EEBB 012217CB 0118DE0A 0124D619 000FF69A 01261339 01FFCABB 0128D789 39 | @00000128 01040829 012A7409 01FF09F9 0000CABB 012DD287 012E1446 012FDA88 012BD60F 40 | @00000130 0131CA99 01321288 0133241A 0134BBAA 01330935 0136100F 013727BA 0138BBAA 41 | @00000138 01370925 013A9EAA 013B70EA 013C093D 01FF013F 01FF07FF 013FD28A 0006174A 42 | @00000140 0006174C 013E174C 0143D28A 013FA2CA 0145D28A 0146A2CA 013E174A 0004D28F 43 | @00000148 0147174D 014AD28F 0004A2DF 014CD28F 014DA2DF 0147174F 012B100F 0016FFFF 44 | @00000150 01510F52 01536FEF 01536F0F 0154EAF8 012B1208 01561B46 014EC0FF 000CD28E 45 | @00000158 0002420D 0002D28A 0002C2DA 0159174D 015DD28A 0002A2DA 015FD28A 0160A2DA 46 | @00000160 0159174A 01621B46 0163100C 0164C27C 0000C2A7 01661446 012BD28D 0168092B 47 | @00000168 01696E7A 0000B2A7 016B1109 016C6E7A 016DA2A7 000FC276 016F702A 01710970 48 | @00000170 0000E298 0000E698 0173141A 0174D28E 0175C28F 0176171A 0177DA18 01784EF6 49 | @00000178 01791B46 017A100F 017B4EF6 017C1B46 017D1007 017EC2E7 017F8ABF 012B081D 50 | @00000180 0181250A 018284FF 0183F4CE 018484EE 018584FF 0186F4CE 018784EE 018884FF 51 | @00000188 0189F4CE 018A84EE 018B84FF 018CBBAA 0182098D 01920E8E 018FF4CE 019084EE 52 | @00000190 019184FF 0195B4CE 019380EE 019484FF 0195A4AE 01965108 0197F2FF 01980899 53 | @00000198 019AF2EE 019A9EEA 019C099B 019C4FF8 019DC2EC 019E5049 019F1109 0000C2FC 54 | @000001A0 01A15049 01A21109 01A388EA 01A4C2EA 01A5EAFA 01A686AB 01A90EA7 01A890CC 55 | @000001A8 01A994EE 01AAF0FF 01AB09AD 01AC130F 01770C76 01AE5108 01AF208A 012BB9AA 56 | @000001B0 01B1702F 01B209B6 01B380CC 01B4ABFF 01B209B5 0000C0CC 01B76F3F 01B8F0CC 57 | @000001B8 01B9BBFF 01BA082B 01B888CC 01C109BC 01BD5049 01BE1109 01BFC2CE 01C040C9 58 | @000001C0 01C21109 01C2C2CE 01C36F3F 01C4702F 01C509CB 01C640CF 01C780CC 01C884EE 59 | @000001C8 01C9ABFF 01C609CA 01D0C0CC 01CCF0CC 01CDBBFF 01CE08D0 01CF88EE 01CC8CCC 60 | @000001D0 01D15049 01D21109 01D3C2EC 012B0DD4 01D5C2EE 01D6092B 00004CF8 01D82F8B 61 | @000001D8 01D9117B 01DA9EBB 01DB178B 01DCD38F 01D708DD 01DE2F8B 01DF117B 01E09EBB 62 | @000001E0 01E1520B 01E2178B 00DFD38F 01E42B8B 01E5117B 01E69EBB 01E7178B 01E8D30B 63 | @000001E8 01E308E9 01EA298B 01EB9EBB 01EC1B8B 01ED100F 01EED71B 01EF78FA 00DF09F0 64 | @000001F0 01270FFF 012B1228 012C1446 01722C0A 0172201A 01300F2B 012C1446 00002300 65 | @000001F8 01F22416 00F7218A 01FCD687 01FF07FE 010A8279 00FFEEAB 01FFFFFF 0172280A 66 | -------------------------------------------------------------------------------- /rom/f11/001.rom: -------------------------------------------------------------------------------- 1 | /* http://srecord.sourceforge.net/ */ 2 | @00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3 | @00000008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4 | @00000010 00F11052 00F21053 00F31064 00F41065 00F51076 00F61077 01FFFFFF 01FFFFFF 5 | @00000018 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 6 | @00000020 01710B72 017E0E72 017386FE 0174D2B8 0175D2A9 01765209 0177D26A 017E4EFA 7 | @00000028 0179701F 017C097A 017B202A 017CEAAF 017D110F 001FC27A 017FD2A9 01F6EE99 8 | @00000030 0178D2BF 01F2130F 0176D26A 01F609F4 01F524AA 01FF0012 01F75089 01F8EE9E 9 | @00000038 01F910AE 01FA103A 01FB102B 01FC130F 01F37049 01FFFFFF 0176D26A 01FE220B 10 | @00000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11 | @00000048 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 12 | @00000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 13 | @00000058 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 14 | @00000060 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 15 | @00000068 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16 | @00000070 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 17 | @00000078 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 18 | @00000080 0006D28E 0037100E 0016D28A 00164EFD 00164CFD 0082174D 0087D28A 0016A2DA 19 | @00000088 0089D28A 008AA2DA 0082174A 008C144A 0006D28F 008E184A 0037100F 0090D2C9 20 | @00000090 0091D2CA 00921049 0093104A 00A5D2A9 0095144A 0096D28E 002A144A 0098144A 21 | @00000098 0099D289 009A174A 009BD28A 009C1049 009D104A 009ED2A9 009F8AEA 00A50AA0 22 | @000000A0 00A1EEAA 00A509A2 00A3EE9A 00A4780A 003909A5 00A6C29A 00A75F09 00A84DF9 23 | @000000A8 003D10A9 00AAD28E 00ABCAFF 00AC104F 009D104F 0094D28A 00944CFD 009448FD 24 | @000000B0 00AD174D 00B2D28A 0094A2DA 00B4D28A 00B5A2DA 00AD174A 00B710DF 00B8D3A9 25 | @000000B8 003708B9 00BAD24E 00BBD24F 00BC10CE 003710CF 00BE184A 00BF100E 00C0184A 26 | @000000C0 00C1100F 00C2D3A9 003708C3 00C4D24E 00C5D24F 00C6184A 00C7100E 00C81B4A 27 | @000000C8 0037100F 0037100E 00CBD3A9 00CC08CD 00BD440D 00BD480D 00BDD28A 00D0D3A9 28 | @000000D0 00D108D3 00D24CFA 00BD4CFD 00D448FA 00BD48FD 00CE174D 00D7D28A 00BDA2DA 29 | @000000D8 00D9D28A 00DAA2DA 00CE174A 00DC208F 00DDEAF9 00DE10A9 00DFF2BB 01F109F6 30 | @000000E0 00E16F0F 00E2EEFF 00E3E78F 00E4102F 00E5D2AF 00E660EF 00E7EEFF 00E8E2F9 31 | @000000E8 00E91109 002810B9 00EB4DF9 00EC10A9 01F12C0B 00EED24A 00EF1040 00F01041 32 | @000000F0 00F11052 00F21053 00F31064 00F41065 00F51076 00F61077 01FF0090 00031067 33 | @000000F8 00F9EA8F 00FA6F0F 01F6EAF8 00FCD2AF 00FD7809 00FE09FF 0100E6EF 0100E2EF 34 | @00000100 01F610AF 0102EEFF 0103501F 0104E2FE 01F610AE 0106EEFF 0107E2F9 01081109 35 | @00000108 0109D22E 0014D23F 010BD2FF 010CC29A 00A6D2A9 010E8AEE 010FCBEE 0110EEEE 36 | @00000110 0111408E 0112CAFF 0113D2A9 0114C2EA 01150816 011648F9 013EE6FA 0118EA89 37 | @00000118 01196F09 0014EA98 011B5F09 011C4DF9 011DEE9A 011ECAFF 011F408F 01203F7E 38 | @00000120 0121082D 01229AFE 01310823 0124A3FE 0125C2EA 0126D2FE 0127D2FF 012810B8 39 | @00000128 012988EE 012AEFAE 012B86EE 012CD2B8 014C10FE 012E5209 012F10A9 0130280B 40 | @00000130 0133720A 01322A0B 0133740A 01230934 0135CABB 0136CAEE 0137CAFF 01387089 41 | @00000138 0139092C 013A10EE 012C10EF 013C0A3D 013D48F9 013EEEAA 013F0940 01404CF9 42 | @00000140 001E10A9 01426F1A 0143330A 0023092C 0145EEAA 014A0946 0147CAEE 0148CAFF 43 | @00000148 0149104E 0181104F 014B208A 0035EEAA 018110FF 014E10FF 014FD24A 0150D24F 44 | @00000150 015110EA 018110EF 0153D3A9 01580854 0155D2EA 0156D2E9 0157104A 01581049 45 | @00000158 002CD2FF 015A9EFF 00E6608F 015CCAAA 015D10E9 015E10EA 015F8AEA 0160EEAA 46 | @00000160 0161097A 017F10FE 0163EEAA 0164097A 0165D249 0166D24A 0167D2AA 016810B8 47 | @00000168 01698AAA 016A8AAA 016B9EAA 016C608A 016DEEAA 016EA0A9 016FACFF 0170ACEE 48 | @00000170 01710B72 017E0E72 017386FE 0174D2B8 0175D2A9 01765209 017710A9 0178EE9A 49 | @00000178 0179720A 017D097A 017BCABB 017CCAEE 0027CAFF 0027280B 0027D2B8 018010FF 50 | @00000180 0181D2A9 013B8AEA 0183104A 0184104A 0185D2AF 01865F0F 01874DFF 018810AF 51 | @00000188 0189D2FE 018AD2FF 018B8AEA 018CEEAA 018D097A 018ED3A9 0180088F 0190D2E9 52 | @00000190 0166D2EA 0192EAA9 002C10A9 019460CF 0195EEFF 0196E2F9 01971109 0198D2AF 53 | @00000198 01995F0F 019A4DFF 019B10AF 0010CAFF 019D10B8 019E88E9 019FCA99 01A08AAA 54 | @000001A0 01A186AA 01A40EA2 01A390FF 01A494EE 01A5F2EE 01AC09A6 01A7F2FF 01A909A8 55 | @000001A8 0020CAAA 01AAC2FE 01ABCAFF 01AC40FA 01B0F2EE 01AEBAAA 01AF88FF 01B08CEE 56 | @000001B0 01AD08B1 01B2EFF9 01B3EEFF 01B4EFEF 01B5EEEE 01B68AEE 01B7EFAE 01B888AA 57 | @000001B8 002086EE 015CCAAA 01BBEE99 01BCE29A 01BD110A 01BE88EA 01BF87BB 01C0EEAA 58 | @000001C0 01C16FFA 01C2308A 01C30AC5 01C4CABB 0111CAEE 01C66F7E 0022508E 01C8D2FF 59 | @000001C8 01D1401A 01D1D2FF 01CBD2A9 01CC5109 01CD10A9 01CEEE99 01CF7109 01D009C3 60 | @000001D0 01C4260B 01D23F8A 01D30AD6 01D4C2F9 01D5C2EF 01DFCAEE 01DF40FA 01D88C99 61 | @000001D8 01D98CFF 01DA8CEE 01DB0ACA 01DFBAAA 01DD80EE 01DE84FF 01DFAAAA 01E0388A 62 | @000001E0 01E10AD7 01E2388A 01DC09E3 01E4F1BB 01EB08E5 01E6D2A9 01E77049 01E809E9 63 | @000001E8 01E990FF 01EA94EE 01CA08ED 01ECF2EE 01ED08CA 0112CABB 01FFFFFF 01FFFFFF 64 | @000001F0 0178D2BF 01F2130F 0176D26A 01F609F4 01F524AA 01FF0012 01F7CA99 01FF0010 65 | @000001F8 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 01FFFFFF 01F1220B 66 | -------------------------------------------------------------------------------- /rom/f11/002.rom: -------------------------------------------------------------------------------- 1 | /* http://srecord.sourceforge.net/ */ 2 | @00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 3 | @00000008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4 | @00000010 00F145F3 002010A3 00F3C3AF 00F46F0F 00059E3E 000586EE 00F7E3F7 00F8CA00 5 | @00000018 00F9CA11 001DCA22 0177E2E0 0176E2E1 00FFE2E2 00FEE2E3 00FFC262 0176C251 6 | @00000020 0171A492 0172A4F1 0173A4E0 000C8833 01758C11 01768C00 0177C240 0178E204 7 | @00000028 0179E215 017AE226 017BE237 017CEE33 017DEF23 017EEE22 017FEF12 01F6EE11 8 | @00000030 0027102F 01F309F2 01FF0010 01FF007B 01F5208F 01F6EEFF 01F7EF01 01F8EE00 9 | @00000038 01F98A00 01FAEFA0 01FB88A9 01FC8600 01FDD2B9 01FE8AAF 01FF1309 003582FF 10 | @00000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11 | @00000048 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 12 | @00000050 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 13 | @00000058 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 14 | @00000060 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 15 | @00000068 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 16 | @00000070 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 17 | @00000078 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 18 | @00000080 0081EE00 0082EA0E 0014D2F4 0084D2E6 0085D2E7 00868841 00878633 0088CB11 19 | @00000088 00896F74 008A5084 008B88E0 008C8633 008DCB00 008E6F7E 008F508E 0090EE00 20 | @00000090 00990991 0092EE11 0093093F 00948A33 00954801 00968833 00978A11 0098861A 21 | @00000098 0009F044 009AEE11 009F099B 0015C2E4 009DC296 009EC2A7 0094C201 00A0B010 22 | @000000A0 00A109AE 00A20EAC 00A3A201 00A4C2E4 00A5C2F5 00A6D2FE 00A76F7E 0016508E 23 | @000000A8 00A9C296 00AAC2A7 00ABD2E9 00B5D2EA 00AD9200 00B68A33 00AF98E4 00A10917 24 | @000000B0 00A109B1 00B29896 00A109B3 00B498A7 00A109B5 00B68A32 003A0B2E 00B89499 25 | @000000B8 00B994FF 003A94EE 002F2702 00BC0A94 00BD9A20 00BE0AC2 00BF4701 00C0C202 26 | @000000C0 00C109CE 00C2B221 0034B220 00C48C66 00C58C55 00C68C44 00C7BB22 003409C8 27 | @000000C8 00CDF200 000A80EE 00CB8499 00CC84AA 00CDBB00 00C909CE 00CFAA11 00D08833 28 | @000000D0 00D18A11 00388611 00D3A496 00D4A4F5 00D5A4E4 0009C21A 00D71109 001F0D3F 29 | @000000D8 00D95F03 00DAD2F4 00DBD2F5 00DC88E0 00DD8A42 00DEE602 00DFEE22 00E0093F 30 | @000000E0 00E18A42 00E20AE3 00240EEF 00EE0E24 00E5B420 00E609F0 00E7F2EE 00E808E9 31 | @000000E8 00EE0EEF 00EF0EEE 00EBD2E7 00ECB07A 00EDB469 00E4B45F 00F141F3 00F149F3 32 | @000000F0 00F145F3 002010A3 00F3C3AF 00F46F0F 00059E3E 000586EE 00F508F7 00F8130A 33 | @000000F8 00F62F1F 00FA0836 010D2B79 00FCCA66 00FDCA77 01003FFF 01FFFFFF 01FFFFFF 34 | @00000100 010C0801 0102D2A9 0103EE9E 01045F09 010547F9 0106720E 01070908 01D1280B 35 | @00000108 0109CA00 010ACA11 010BCA22 01D1CA33 010D2B79 010EEE99 018C1109 0110D2E2 36 | @00000110 0111D2E3 01128AE6 0113CB66 0019EE66 01158807 0116CB77 0117EE77 011809C7 37 | @00000118 01198655 011AEAE5 011B8855 011C8A77 001B867B 0120408B 011F404B 0120414B 38 | @00000120 01216F70 01225080 01236F7E 0124508E 0125CA44 0030C855 0127EEAA 0128CA66 39 | @00000128 0129CA77 0130EE00 012BEE22 012C1102 012DCA99 012ECAAA 012FCA22 0127CA33 40 | @00000130 0131EEEE 0132EEFF 0133C3FE 0134C39F 0135C3A9 0029CBAA 0137093F 0138201A 41 | @00000138 00008011 013AA0F5 013BA4E4 013C8444 013D8455 013EBBAA 0138093F 0140C301 42 | @00000140 01410943 0142CA00 0138280A 0144C2BA 0145D2B9 01461109 019CCABB 00048022 43 | @00000148 014D0A49 014AA0A7 014BA496 014CA4F5 014DA4E4 014E8444 014F8455 01508466 44 | @00000150 01518477 0152BB00 01470953 0154EE02 01550943 0156C213 01472810 01580E5A 45 | @00000158 0159B0F1 015CB4E0 015BA0F1 015CA4E0 00028811 015E8E55 01570A5F 01609E55 46 | @00000160 0161F244 01640962 0163C254 01572045 01658A55 01668A55 01678A55 01688A55 47 | @00000168 01698A55 01438A55 016B0E6F 016CB0A3 016DB492 016EB4F1 0173B4E0 0170A0A3 48 | @00000170 0171A492 0172A4F1 0173A4E0 000C8833 01758C11 01768C00 01778E77 016A0A78 49 | @00000178 01799E77 017AF244 017D097B 017CC276 01854104 017E3104 0180097F 017CC275 50 | @00000180 01813204 01860982 0183C264 0184C276 016A2047 016A2107 01878A77 01888A77 51 | @00000188 01898A77 018A8A77 018B8A77 01438A77 018DC04F 018EE65F 018FE66F 0190E67F 52 | @00000190 019109CB 01950C9B 0193BAAA 00038855 0192089A 0196BAAA 01978877 01988C66 53 | @00000198 00078C55 0195089A 019B1109 0028FFFF 001FF244 01A18855 019F8877 01A08C66 54 | @000001A0 01A18C55 01A28C44 0028BAAA 01A45049 01A51109 002A10F0 01A710E2 01A810E3 55 | @000001A8 01A9D2B9 003B1109 01ABAC66 01ACAC55 01ADAC44 01AEAEAA 001C88AE 01B0EF67 56 | @000001B0 01B1EE66 01B2EF56 01B3EE55 01B4EF45 01B5EE44 01B68A44 01B7EFA4 01B88644 57 | @000001B8 01B9D2A9 01BAEE9E 01BB5F09 01BC0DF7 01BDEEAF 01BE6F7F 01BF09D9 01C0704F 58 | @000001C0 01F409F9 01C2EE9E 01C340FE 01C4EFE9 01C51109 0020CABB 01F21218 01C8CA00 59 | @000001C8 01C9CA11 01CACA22 01CBCA33 01CCD2A9 01CD5F09 01CE45F9 01CFCA44 01D0CA55 60 | @000001D0 002BCA66 01D2D2BA 01D3504A 01D4110A 003210F0 01D610E2 01D710E3 01D8D2BA 61 | @000001D8 01E1110A 01DA4DF9 01DB8A4A 01DCEEAA 01DD09DE 01DE4CF9 01DFF244 01E008E1 62 | @000001E0 01E148F9 01E210A9 001210F4 01E410E6 002010E7 01E6D241 01E7D252 01E8D253 63 | @000001E8 01E9D264 01EAD265 01EBD276 01ECD277 01EDD22F 01EEC3F8 01EFEEFF 01F06F0F 64 | @000001F0 0027102F 01F309F2 01FF0010 01FF007B 01F5208F 01F6EEFF 01F7EAF4 0033740E 65 | @000001F8 01D92A0B 01FA720E 01FB09FD 01FC4FF9 01DA280B 01CE47F9 01FF1106 0020240B 66 | -------------------------------------------------------------------------------- /rom/f11/boot_diag_rom.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/rom/f11/boot_diag_rom.bin -------------------------------------------------------------------------------- /rom/f11/bootrom-mod/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | progname=mboot 3 | base=$((0173252)) 4 | ov=4 5 | chunk=256 6 | ./macro11 -o $progname.obj -l $progname.lst $progname.mac 7 | ./rt11obj2bin $progname.obj > $progname.map 8 | cp $out.orig rom.bin 9 | start=$(($ov*$chunk+$base-0173000)) 10 | dd conv=notrunc if=$progname.obj.bin of=rom.bin bs=1 seek=$start 11 | # Коррекция DD на DM 12 | echo -n "M" | dd conv=notrunc of=rom.bin bs=1 seek=$((0x1e3)) 13 | # Коррекция DL на DB 14 | echo -n "B" | dd conv=notrunc of=rom.bin bs=1 seek=$((0x1cb)) 15 | # коррекция адреса перехода и номеров оверлеев - off=1CE adr=173372 ov l=4 h=5 16 | echo -e -n "\0372\0366\0004\0005" | dd conv=notrunc of=rom.bin bs=1 seek=$((0x1ce)) 17 | # Вписываем MY 173472 = 367 072 18 | echo -e -n "MY\0300\0000\0072\0367\0004\0005" | dd conv=notrunc of=rom.bin bs=1 seek=$((0x1ea)) 19 | cp $out.bin ../../boot_diag_rom.bin 20 | -------------------------------------------------------------------------------- /rom/f11/bootrom-mod/mboot.mac: -------------------------------------------------------------------------------- 1 | .TITLE MBOOT - MODIFIED BOOTOADERS 2 | ; 3 | ;======================================================================================================= 4 | ; Загрузчик RK611/RK07 (DM) 5 | ; На входе в R0 передается # устройства 6 | ;======================================================================================================= 7 | ; 8 | DMCSR=177440 9 | DMCS1 =+0 10 | DMWC =+2 11 | DMCSR2 =+10 12 | DMER =+14 13 | 14 | .ASECT 15 | .=173252 16 | DMSTART: 17 | MOV #DMCSR,R1 18 | MOV R0,DMCSR2(R1) ; вписываем unit# 19 | MOV #0003,(R1) ; команда подтверждения установки тома для устройства типа RK06 20 | 21 | 2$: TSTB (R1) ; ждем ответа от контроллера 22 | BPL 2$ ; 23 | TST (R1) ; была ошибка? 24 | BPL 4$ ; нет 25 | 26 | BIT #40,DMER(R1) ; ошибка неправильного типа диска? 27 | BEQ 6$ ; нет 28 | 29 | ; Неправильный тип диска - значит у нас RK07 30 | RESET ; сброс контроллера 31 | MOV R0,DMCSR2(R1) ; вписываем unit# 32 | MOV #2003,(R1) ; команда подтверждения установки тома для устройства типа RK07 33 | 34 | 3$: TSTB (R1) ; ждем ответа от контроллера 35 | BPL 3$ 36 | TST (R1) ; была ошибка? 37 | BMI 6$ ; да 38 | 39 | 4$: MOV #-512.,DMWC(R1) ; счетчик слов - 1 сектор 40 | MOV (R1),R3 ; получаем используемый тип диска 41 | BIC #377,R3 ; очищаем поле команды 42 | BIS #21,R3 ; вписываем команду чтения 43 | MOV R3,(R1) ; посылаем команду в контроллер 44 | 45 | 5$: TSTB (R1) ; ждем ответа от контроллера 46 | BPL 5$ 47 | TST (R1) ; была ошибка? 48 | BPL 7$ ; нет 49 | 50 | ; обработка ошибочных ситуаций 51 | 6$: RESET ; сбрасваем контроллер 52 | HALT ; уходим в пульт 53 | BR DMSTART ; перезапуск загрузчика 54 | ; запуск загруженного бутсектора 55 | 7$: CLR PC 56 | 57 | ;======================================================================================================= 58 | ; Загрузчик RH70/RP06 (DB) 59 | ; На входе в R0 передается # устройства 60 | ;======================================================================================================= 61 | 62 | RHCS =176700 ; CSR 63 | RHWC =+2 ; WORD COUNT 64 | RHBA =+4 ; BUS ADDR 65 | RHCS2 =+10 ; CSR2 66 | RHAS =+16 ; ATTEN 67 | RHOF =+32 ; OFFSET 68 | 69 | DBSTART: MOV #RHCS,R1 70 | MOV R0,RHCS2(R1) ; вписываем unit# 71 | MOV #071,R2 ; 34 - команда чтения 72 | MOV #021,(R1) ; команда подготовки к начальной загузке 73 | MOV #014000,RHOF(R1) ; отключение ЕСС, формат диска 22 сектора 74 | MOV RHAS(R1),RHAS(R1) ; очистка всех сигналов внимание 75 | 76 | BOOTRP: MOV #-512.,RHWC(R1) ; счетчик слов - 1 сектор 77 | MOV (R1),R3 ; CSR 78 | BIC #377,R3 ; очищаем поле команды 79 | BIS R2,R3 ; вписваем команду чтения 80 | MOV R3,(R1) ; отправляем команду в контроллер 81 | 2$: TSTB (R1) ; ждем ответа от контроллера 82 | BPL 2$ 83 | 84 | TST (R1) ; была ошибка? 85 | BPL 3$ ; нет 86 | ; контроллер вернул ошибку 87 | RESET ; сброс контроллера 88 | HALT ; вываливаемся в ODT 89 | BR DMSTART ; перезапускаем процесс загрузки 90 | 91 | 3$: BIC #377,(R1) ; очищаем поле команд в CSR 92 | CLR PC ; запускаем считанный загрузчик 93 | 94 | ;======================================================================================================= 95 | ; Загрузчик с дискет MY 96 | ; На входе в R0 передается # устройства 97 | ;======================================================================================================= 98 | MYCSR = 172140 99 | 100 | MYSTART: MOV #MYCSR,R1 101 | MOV #37,(R1) ; Команда LOAD 102 | 10$: TSTB (R1) ; ждем DRQ 103 | BPL 10$ 104 | MOV R0,2(R1) ; отправляем # устройства 105 | 20$: BIT #40,(R1) ; ждем DONE 106 | BEQ 20$ 107 | TST (R1) ; были ошибки? 108 | BPL 30$ ; нет 109 | HALT ; при ошибке вываливаемся в ODT 110 | BR MYSTART 111 | 30$: CLR PC ; запускаем считанный загрузчик 112 | 113 | .END 114 | 115 | -------------------------------------------------------------------------------- /rom/f11/bootrom-mod/rom.orig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/forth32/dvk-fpga/fe00926d72ced0b1121c9d8bf686d56ff3c67200/rom/f11/bootrom-mod/rom.orig -------------------------------------------------------------------------------- /rom/f11/conv.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | srec_cat boot_diag_rom.bin -binary --byte-swap 2 -o boot_diag_rom.mif -Memory_Initialization_File 16 -obs=2 3 | 4 | -------------------------------------------------------------------------------- /rom/m9312/macro11: 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