├── CH32V-EVT ├── Core │ ├── core_riscv.c │ └── core_riscv.h ├── Ld │ └── Link.ld ├── Peripheral │ ├── inc │ │ ├── ch32v00x.h │ │ ├── ch32v00x_adc.h │ │ ├── ch32v00x_dbgmcu.h │ │ ├── ch32v00x_dma.h │ │ ├── ch32v00x_exti.h │ │ ├── ch32v00x_flash.h │ │ ├── ch32v00x_gpio.h │ │ ├── ch32v00x_i2c.h │ │ ├── ch32v00x_iwdg.h │ │ ├── ch32v00x_misc.h │ │ ├── ch32v00x_opa.h │ │ ├── ch32v00x_pwr.h │ │ ├── ch32v00x_rcc.h │ │ ├── ch32v00x_spi.h │ │ ├── ch32v00x_tim.h │ │ ├── ch32v00x_usart.h │ │ └── ch32v00x_wwdg.h │ └── src │ │ ├── ch32v00x_adc.c │ │ ├── ch32v00x_dbgmcu.c │ │ ├── ch32v00x_dma.c │ │ ├── ch32v00x_exti.c │ │ ├── ch32v00x_flash.c │ │ ├── ch32v00x_gpio.c │ │ ├── ch32v00x_i2c.c │ │ ├── ch32v00x_iwdg.c │ │ ├── ch32v00x_misc.c │ │ ├── ch32v00x_opa.c │ │ ├── ch32v00x_pwr.c │ │ ├── ch32v00x_rcc.c │ │ ├── ch32v00x_spi.c │ │ ├── ch32v00x_tim.c │ │ ├── ch32v00x_usart.c │ │ └── ch32v00x_wwdg.c └── Startup │ └── startup_ch32v00x.S ├── LICENSE.md ├── Makefile ├── Readme.md ├── assets └── iso15693-write-message.png └── src ├── epd ├── README.md ├── ch32v00x-drv.c ├── drv.h ├── uc8253.c └── uc8253.h ├── main.c ├── mcu ├── README.md ├── ch32v00x-debug.c ├── ch32v00x-hal.c ├── ch32v00x-it.c ├── ch32v00x-sys.c ├── ch32v00x-sys.h ├── debug.h └── hal.h └── nfc-tag ├── README.md ├── ch32v00x-drv.c ├── drv.h ├── st25dv.c └── st25dv.h /CH32V-EVT/Core/core_riscv.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : core_riscv.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : RISC-V Core Peripheral Access Layer Source File 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | /* define compiler specific symbols */ 15 | #if defined(__CC_ARM) 16 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ 17 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 18 | 19 | #elif defined(__ICCARM__) 20 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ 21 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ 22 | 23 | #elif defined(__GNUC__) 24 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ 25 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ 26 | 27 | #elif defined(__TASKING__) 28 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 29 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 30 | 31 | #endif 32 | 33 | /********************************************************************* 34 | * @fn __get_MSTATUS 35 | * 36 | * @brief Return the Machine Status Register 37 | * 38 | * @return mstatus value 39 | */ 40 | uint32_t __get_MSTATUS(void) 41 | { 42 | uint32_t result; 43 | 44 | __ASM volatile("csrr %0," "mstatus": "=r"(result)); 45 | return (result); 46 | } 47 | 48 | /********************************************************************* 49 | * @fn __set_MSTATUS 50 | * 51 | * @brief Set the Machine Status Register 52 | * 53 | * @param value - set mstatus value 54 | * 55 | * @return none 56 | */ 57 | void __set_MSTATUS(uint32_t value) 58 | { 59 | __ASM volatile("csrw mstatus, %0" : : "r"(value)); 60 | } 61 | 62 | /********************************************************************* 63 | * @fn __get_MISA 64 | * 65 | * @brief Return the Machine ISA Register 66 | * 67 | * @return misa value 68 | */ 69 | uint32_t __get_MISA(void) 70 | { 71 | uint32_t result; 72 | 73 | __ASM volatile("csrr %0,""misa" : "=r"(result)); 74 | return (result); 75 | } 76 | 77 | /********************************************************************* 78 | * @fn __set_MISA 79 | * 80 | * @brief Set the Machine ISA Register 81 | * 82 | * @param value - set misa value 83 | * 84 | * @return none 85 | */ 86 | void __set_MISA(uint32_t value) 87 | { 88 | __ASM volatile("csrw misa, %0" : : "r"(value)); 89 | } 90 | 91 | /********************************************************************* 92 | * @fn __get_MTVEC 93 | * 94 | * @brief Return the Machine Trap-Vector Base-Address Register 95 | * 96 | * @return mtvec value 97 | */ 98 | uint32_t __get_MTVEC(void) 99 | { 100 | uint32_t result; 101 | 102 | __ASM volatile("csrr %0," "mtvec": "=r"(result)); 103 | return (result); 104 | } 105 | 106 | /********************************************************************* 107 | * @fn __set_MTVEC 108 | * 109 | * @brief Set the Machine Trap-Vector Base-Address Register 110 | * 111 | * @param value - set mtvec value 112 | * 113 | * @return none 114 | */ 115 | void __set_MTVEC(uint32_t value) 116 | { 117 | __ASM volatile("csrw mtvec, %0":: "r"(value)); 118 | } 119 | 120 | /********************************************************************* 121 | * @fn __get_MSCRATCH 122 | * 123 | * @brief Return the Machine Seratch Register 124 | * 125 | * @return mscratch value 126 | */ 127 | uint32_t __get_MSCRATCH(void) 128 | { 129 | uint32_t result; 130 | 131 | __ASM volatile("csrr %0," "mscratch" : "=r"(result)); 132 | return (result); 133 | } 134 | 135 | /********************************************************************* 136 | * @fn __set_MSCRATCH 137 | * 138 | * @brief Set the Machine Seratch Register 139 | * 140 | * @param value - set mscratch value 141 | * 142 | * @return none 143 | */ 144 | void __set_MSCRATCH(uint32_t value) 145 | { 146 | __ASM volatile("csrw mscratch, %0" : : "r"(value)); 147 | } 148 | 149 | /********************************************************************* 150 | * @fn __get_MEPC 151 | * 152 | * @brief Return the Machine Exception Program Register 153 | * 154 | * @return mepc value 155 | */ 156 | uint32_t __get_MEPC(void) 157 | { 158 | uint32_t result; 159 | 160 | __ASM volatile("csrr %0," "mepc" : "=r"(result)); 161 | return (result); 162 | } 163 | 164 | /********************************************************************* 165 | * @fn __set_MEPC 166 | * 167 | * @brief Set the Machine Exception Program Register 168 | * 169 | * @return mepc value 170 | */ 171 | void __set_MEPC(uint32_t value) 172 | { 173 | __ASM volatile("csrw mepc, %0" : : "r"(value)); 174 | } 175 | 176 | /********************************************************************* 177 | * @fn __get_MCAUSE 178 | * 179 | * @brief Return the Machine Cause Register 180 | * 181 | * @return mcause value 182 | */ 183 | uint32_t __get_MCAUSE(void) 184 | { 185 | uint32_t result; 186 | 187 | __ASM volatile("csrr %0," "mcause": "=r"(result)); 188 | return (result); 189 | } 190 | 191 | /********************************************************************* 192 | * @fn __set_MEPC 193 | * 194 | * @brief Set the Machine Cause Register 195 | * 196 | * @return mcause value 197 | */ 198 | void __set_MCAUSE(uint32_t value) 199 | { 200 | __ASM volatile("csrw mcause, %0":: "r"(value)); 201 | } 202 | 203 | /********************************************************************* 204 | * @fn __get_MVENDORID 205 | * 206 | * @brief Return Vendor ID Register 207 | * 208 | * @return mvendorid value 209 | */ 210 | uint32_t __get_MVENDORID(void) 211 | { 212 | uint32_t result; 213 | 214 | __ASM volatile("csrr %0,""mvendorid": "=r"(result)); 215 | return (result); 216 | } 217 | 218 | /********************************************************************* 219 | * @fn __get_MARCHID 220 | * 221 | * @brief Return Machine Architecture ID Register 222 | * 223 | * @return marchid value 224 | */ 225 | uint32_t __get_MARCHID(void) 226 | { 227 | uint32_t result; 228 | 229 | __ASM volatile("csrr %0,""marchid": "=r"(result)); 230 | return (result); 231 | } 232 | 233 | /********************************************************************* 234 | * @fn __get_MIMPID 235 | * 236 | * @brief Return Machine Implementation ID Register 237 | * 238 | * @return mimpid value 239 | */ 240 | uint32_t __get_MIMPID(void) 241 | { 242 | uint32_t result; 243 | 244 | __ASM volatile("csrr %0,""mimpid": "=r"(result)); 245 | return (result); 246 | } 247 | 248 | /********************************************************************* 249 | * @fn __get_MHARTID 250 | * 251 | * @brief Return Hart ID Register 252 | * 253 | * @return mhartid value 254 | */ 255 | uint32_t __get_MHARTID(void) 256 | { 257 | uint32_t result; 258 | 259 | __ASM volatile("csrr %0,""mhartid": "=r"(result)); 260 | return (result); 261 | } 262 | 263 | /********************************************************************* 264 | * @fn __get_SP 265 | * 266 | * @brief Return SP Register 267 | * 268 | * @return SP value 269 | */ 270 | uint32_t __get_SP(void) 271 | { 272 | uint32_t result; 273 | 274 | __ASM volatile("mv %0,""sp": "=r"(result):); 275 | return (result); 276 | } 277 | -------------------------------------------------------------------------------- /CH32V-EVT/Core/core_riscv.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : core_riscv.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : RISC-V Core Peripheral Access Layer Header File 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #ifndef __CORE_RISCV_H__ 13 | #define __CORE_RISCV_H__ 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | /* IO definitions */ 20 | #ifdef __cplusplus 21 | #define __I volatile /*!< defines 'read only' permissions */ 22 | #else 23 | #define __I volatile const /*!< defines 'read only' permissions */ 24 | #endif 25 | #define __O volatile /*!< defines 'write only' permissions */ 26 | #define __IO volatile /*!< defines 'read / write' permissions */ 27 | 28 | /* Standard Peripheral Library old types (maintained for legacy purpose) */ 29 | typedef __I uint32_t vuc32; /* Read Only */ 30 | typedef __I uint16_t vuc16; /* Read Only */ 31 | typedef __I uint8_t vuc8; /* Read Only */ 32 | 33 | typedef const uint32_t uc32; /* Read Only */ 34 | typedef const uint16_t uc16; /* Read Only */ 35 | typedef const uint8_t uc8; /* Read Only */ 36 | 37 | typedef __I int32_t vsc32; /* Read Only */ 38 | typedef __I int16_t vsc16; /* Read Only */ 39 | typedef __I int8_t vsc8; /* Read Only */ 40 | 41 | typedef const int32_t sc32; /* Read Only */ 42 | typedef const int16_t sc16; /* Read Only */ 43 | typedef const int8_t sc8; /* Read Only */ 44 | 45 | typedef __IO uint32_t vu32; 46 | typedef __IO uint16_t vu16; 47 | typedef __IO uint8_t vu8; 48 | 49 | typedef uint32_t u32; 50 | typedef uint16_t u16; 51 | typedef uint8_t u8; 52 | 53 | typedef __IO int32_t vs32; 54 | typedef __IO int16_t vs16; 55 | typedef __IO int8_t vs8; 56 | 57 | typedef int32_t s32; 58 | typedef int16_t s16; 59 | typedef int8_t s8; 60 | 61 | typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; 62 | 63 | typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 64 | 65 | typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 66 | 67 | #define RV_STATIC_INLINE static inline 68 | 69 | /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ 70 | typedef struct{ 71 | __I uint32_t ISR[8]; 72 | __I uint32_t IPR[8]; 73 | __IO uint32_t ITHRESDR; 74 | __IO uint32_t RESERVED; 75 | __IO uint32_t CFGR; 76 | __I uint32_t GISR; 77 | __IO uint8_t VTFIDR[4]; 78 | uint8_t RESERVED0[12]; 79 | __IO uint32_t VTFADDR[4]; 80 | uint8_t RESERVED1[0x90]; 81 | __O uint32_t IENR[8]; 82 | uint8_t RESERVED2[0x60]; 83 | __O uint32_t IRER[8]; 84 | uint8_t RESERVED3[0x60]; 85 | __O uint32_t IPSR[8]; 86 | uint8_t RESERVED4[0x60]; 87 | __O uint32_t IPRR[8]; 88 | uint8_t RESERVED5[0x60]; 89 | __IO uint32_t IACTR[8]; 90 | uint8_t RESERVED6[0xE0]; 91 | __IO uint8_t IPRIOR[256]; 92 | uint8_t RESERVED7[0x810]; 93 | __IO uint32_t SCTLR; 94 | }PFIC_Type; 95 | 96 | /* memory mapped structure for SysTick */ 97 | typedef struct 98 | { 99 | __IO uint32_t CTLR; 100 | __IO uint32_t SR; 101 | __IO uint32_t CNT; 102 | uint32_t RESERVED0; 103 | __IO uint32_t CMP; 104 | uint32_t RESERVED1; 105 | }SysTick_Type; 106 | 107 | 108 | #define PFIC ((PFIC_Type *) 0xE000E000 ) 109 | #define NVIC PFIC 110 | #define NVIC_KEY1 ((uint32_t)0xFA050000) 111 | #define NVIC_KEY2 ((uint32_t)0xBCAF0000) 112 | #define NVIC_KEY3 ((uint32_t)0xBEEF0000) 113 | 114 | #define SysTick ((SysTick_Type *) 0xE000F000) 115 | 116 | 117 | /********************************************************************* 118 | * @fn __enable_irq 119 | * 120 | * @brief Enable Global Interrupt 121 | * 122 | * @return none 123 | */ 124 | RV_STATIC_INLINE void __enable_irq() 125 | { 126 | uint32_t result; 127 | 128 | __asm volatile("csrr %0," "mstatus": "=r"(result)); 129 | result |= 0x88; 130 | __asm volatile ("csrw mstatus, %0" : : "r" (result) ); 131 | } 132 | 133 | /********************************************************************* 134 | * @fn __disable_irq 135 | * 136 | * @brief Disable Global Interrupt 137 | * 138 | * @return none 139 | */ 140 | RV_STATIC_INLINE void __disable_irq() 141 | { 142 | uint32_t result; 143 | 144 | __asm volatile("csrr %0," "mstatus": "=r"(result)); 145 | result &= ~0x88; 146 | __asm volatile ("csrw mstatus, %0" : : "r" (result) ); 147 | } 148 | 149 | /********************************************************************* 150 | * @fn __NOP 151 | * 152 | * @brief nop 153 | * 154 | * @return none 155 | */ 156 | RV_STATIC_INLINE void __NOP() 157 | { 158 | __asm volatile ("nop"); 159 | } 160 | 161 | /********************************************************************* 162 | * @fn NVIC_EnableIRQ 163 | * 164 | * @brief Disable Interrupt 165 | * 166 | * @param IRQn - Interrupt Numbers 167 | * 168 | * @return none 169 | */ 170 | RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 171 | { 172 | NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 173 | } 174 | 175 | /********************************************************************* 176 | * @fn NVIC_DisableIRQ 177 | * 178 | * @brief Disable Interrupt 179 | * 180 | * @param IRQn - Interrupt Numbers 181 | * 182 | * @return none 183 | */ 184 | RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 185 | { 186 | NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 187 | } 188 | 189 | /********************************************************************* 190 | * @fn NVIC_GetStatusIRQ 191 | * 192 | * @brief Get Interrupt Enable State 193 | * 194 | * @param IRQn - Interrupt Numbers 195 | * 196 | * @return 1 - 1: Interrupt Pending Enable 197 | * 0 - Interrupt Pending Disable 198 | */ 199 | RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) 200 | { 201 | return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 202 | } 203 | 204 | /********************************************************************* 205 | * @fn NVIC_GetPendingIRQ 206 | * 207 | * @brief Get Interrupt Pending State 208 | * 209 | * @param IRQn - Interrupt Numbers 210 | * 211 | * @return 1 - 1: Interrupt Pending Enable 212 | * 0 - Interrupt Pending Disable 213 | */ 214 | RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 215 | { 216 | return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 217 | } 218 | 219 | /********************************************************************* 220 | * @fn NVIC_SetPendingIRQ 221 | * 222 | * @brief Set Interrupt Pending 223 | * 224 | * @param IRQn - Interrupt Numbers 225 | * 226 | * @return none 227 | */ 228 | RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 229 | { 230 | NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 231 | } 232 | 233 | /********************************************************************* 234 | * @fn NVIC_ClearPendingIRQ 235 | * 236 | * @brief Clear Interrupt Pending 237 | * 238 | * @param IRQn - Interrupt Numbers 239 | * 240 | * @return none 241 | */ 242 | RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 243 | { 244 | NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 245 | } 246 | 247 | /********************************************************************* 248 | * @fn NVIC_GetActive 249 | * 250 | * @brief Get Interrupt Active State 251 | * 252 | * @param IRQn - Interrupt Numbers 253 | * 254 | * @return 1 - Interrupt Active 255 | * 0 - Interrupt No Active 256 | */ 257 | RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 258 | { 259 | return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 260 | } 261 | 262 | /********************************************************************* 263 | * @fn NVIC_SetPriority 264 | * 265 | * @brief Set Interrupt Priority 266 | * 267 | * @param IRQn - Interrupt Numbers 268 | * priority: bit7 - pre-emption priority 269 | * bit6 - subpriority 270 | * bit[5-0] - reserved 271 | * 272 | * @return none 273 | */ 274 | RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) 275 | { 276 | NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; 277 | } 278 | 279 | /********************************************************************* 280 | * @fn __WFI 281 | * 282 | * @brief Wait for Interrupt 283 | * 284 | * @return none 285 | */ 286 | __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) 287 | { 288 | NVIC->SCTLR &= ~(1<<3); // wfi 289 | asm volatile ("wfi"); 290 | } 291 | 292 | /********************************************************************* 293 | * @fn __WFE 294 | * 295 | * @brief Wait for Events 296 | * 297 | * @return none 298 | */ 299 | __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) 300 | { 301 | uint32_t t; 302 | 303 | t = NVIC->SCTLR; 304 | NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) 305 | NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); 306 | asm volatile ("wfi"); 307 | asm volatile ("wfi"); 308 | } 309 | 310 | /********************************************************************* 311 | * @fn SetVTFIRQ 312 | * 313 | * @brief Set VTF Interrupt 314 | * 315 | * @param addr - VTF interrupt service function base address. 316 | * IRQn - Interrupt Numbers 317 | * num - VTF Interrupt Numbers 318 | * NewState - DISABLE or ENABLE 319 | * 320 | * @return none 321 | */ 322 | RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ 323 | if(num > 1) return ; 324 | 325 | if (NewState != DISABLE) 326 | { 327 | NVIC->VTFIDR[num] = IRQn; 328 | NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); 329 | } 330 | else{ 331 | NVIC->VTFIDR[num] = IRQn; 332 | NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); 333 | } 334 | } 335 | 336 | /********************************************************************* 337 | * @fn NVIC_SystemReset 338 | * 339 | * @brief Initiate a system reset request 340 | * 341 | * @return none 342 | */ 343 | RV_STATIC_INLINE void NVIC_SystemReset(void) 344 | { 345 | NVIC->CFGR = NVIC_KEY3|(1<<7); 346 | } 347 | 348 | 349 | /* Core_Exported_Functions */ 350 | extern uint32_t __get_MSTATUS(void); 351 | extern void __set_MSTATUS(uint32_t value); 352 | extern uint32_t __get_MISA(void); 353 | extern void __set_MISA(uint32_t value); 354 | extern uint32_t __get_MTVEC(void); 355 | extern void __set_MTVEC(uint32_t value); 356 | extern uint32_t __get_MSCRATCH(void); 357 | extern void __set_MSCRATCH(uint32_t value); 358 | extern uint32_t __get_MEPC(void); 359 | extern void __set_MEPC(uint32_t value); 360 | extern uint32_t __get_MCAUSE(void); 361 | extern void __set_MCAUSE(uint32_t value); 362 | extern uint32_t __get_MVENDORID(void); 363 | extern uint32_t __get_MARCHID(void); 364 | extern uint32_t __get_MIMPID(void); 365 | extern uint32_t __get_MHARTID(void); 366 | extern uint32_t __get_SP(void); 367 | 368 | #ifdef __cplusplus 369 | } 370 | #endif 371 | 372 | #endif/* __CORE_RISCV_H__ */ 373 | 374 | 375 | 376 | 377 | 378 | -------------------------------------------------------------------------------- /CH32V-EVT/Ld/Link.ld: -------------------------------------------------------------------------------- 1 | ENTRY( _start ) 2 | 3 | __stack_size = 256; 4 | 5 | PROVIDE( _stack_size = __stack_size ); 6 | 7 | MEMORY 8 | { 9 | FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K 10 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2K 11 | } 12 | 13 | SECTIONS 14 | { 15 | .init : 16 | { 17 | _sinit = .; 18 | . = ALIGN(4); 19 | KEEP(*(SORT_NONE(.init))) 20 | . = ALIGN(4); 21 | _einit = .; 22 | } >FLASH AT>FLASH 23 | 24 | .text : 25 | { 26 | . = ALIGN(4); 27 | *(.text) 28 | *(.text.*) 29 | *(.rodata) 30 | *(.rodata*) 31 | *(.gnu.linkonce.t.*) 32 | . = ALIGN(4); 33 | } >FLASH AT>FLASH 34 | 35 | .fini : 36 | { 37 | KEEP(*(SORT_NONE(.fini))) 38 | . = ALIGN(4); 39 | } >FLASH AT>FLASH 40 | 41 | PROVIDE( _etext = . ); 42 | PROVIDE( _eitcm = . ); 43 | 44 | .preinit_array : 45 | { 46 | PROVIDE_HIDDEN (__preinit_array_start = .); 47 | KEEP (*(.preinit_array)) 48 | PROVIDE_HIDDEN (__preinit_array_end = .); 49 | } >FLASH AT>FLASH 50 | 51 | .init_array : 52 | { 53 | PROVIDE_HIDDEN (__init_array_start = .); 54 | KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) 55 | KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) 56 | PROVIDE_HIDDEN (__init_array_end = .); 57 | } >FLASH AT>FLASH 58 | 59 | .fini_array : 60 | { 61 | PROVIDE_HIDDEN (__fini_array_start = .); 62 | KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) 63 | KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) 64 | PROVIDE_HIDDEN (__fini_array_end = .); 65 | } >FLASH AT>FLASH 66 | 67 | .ctors : 68 | { 69 | /* gcc uses crtbegin.o to find the start of 70 | the constructors, so we make sure it is 71 | first. Because this is a wildcard, it 72 | doesn't matter if the user does not 73 | actually link against crtbegin.o; the 74 | linker won't look for a file to match a 75 | wildcard. The wildcard also means that it 76 | doesn't matter which directory crtbegin.o 77 | is in. */ 78 | KEEP (*crtbegin.o(.ctors)) 79 | KEEP (*crtbegin?.o(.ctors)) 80 | /* We don't want to include the .ctor section from 81 | the crtend.o file until after the sorted ctors. 82 | The .ctor section from the crtend file contains the 83 | end of ctors marker and it must be last */ 84 | KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) 85 | KEEP (*(SORT(.ctors.*))) 86 | KEEP (*(.ctors)) 87 | } >FLASH AT>FLASH 88 | 89 | .dtors : 90 | { 91 | KEEP (*crtbegin.o(.dtors)) 92 | KEEP (*crtbegin?.o(.dtors)) 93 | KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) 94 | KEEP (*(SORT(.dtors.*))) 95 | KEEP (*(.dtors)) 96 | } >FLASH AT>FLASH 97 | 98 | .dalign : 99 | { 100 | . = ALIGN(4); 101 | PROVIDE(_data_vma = .); 102 | } >RAM AT>FLASH 103 | 104 | .dlalign : 105 | { 106 | . = ALIGN(4); 107 | PROVIDE(_data_lma = .); 108 | } >FLASH AT>FLASH 109 | 110 | .data : 111 | { 112 | . = ALIGN(4); 113 | *(.gnu.linkonce.r.*) 114 | *(.data .data.*) 115 | *(.gnu.linkonce.d.*) 116 | . = ALIGN(8); 117 | PROVIDE( __global_pointer$ = . + 0x800 ); 118 | *(.sdata .sdata.*) 119 | *(.sdata2*) 120 | *(.gnu.linkonce.s.*) 121 | . = ALIGN(8); 122 | *(.srodata.cst16) 123 | *(.srodata.cst8) 124 | *(.srodata.cst4) 125 | *(.srodata.cst2) 126 | *(.srodata .srodata.*) 127 | . = ALIGN(4); 128 | PROVIDE( _edata = .); 129 | } >RAM AT>FLASH 130 | 131 | .bss : 132 | { 133 | . = ALIGN(4); 134 | PROVIDE( _sbss = .); 135 | *(.sbss*) 136 | *(.gnu.linkonce.sb.*) 137 | *(.bss*) 138 | *(.gnu.linkonce.b.*) 139 | *(COMMON*) 140 | . = ALIGN(4); 141 | PROVIDE( _ebss = .); 142 | } >RAM AT>FLASH 143 | 144 | PROVIDE( _end = _ebss); 145 | PROVIDE( end = . ); 146 | 147 | .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : 148 | { 149 | PROVIDE( _heap_end = . ); 150 | . = ALIGN(4); 151 | PROVIDE(_susrstack = . ); 152 | . = . + __stack_size; 153 | PROVIDE( _eusrstack = .); 154 | } >RAM 155 | 156 | } 157 | 158 | 159 | 160 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_adc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_adc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * ADC firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_ADC_H 14 | #define __CH32V00x_ADC_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* ADC Init structure definition */ 23 | typedef struct 24 | { 25 | uint32_t ADC_Mode; /* Configures the ADC to operate in independent or 26 | dual mode. 27 | This parameter can be a value of @ref ADC_mode */ 28 | 29 | FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in 30 | Scan (multichannels) or Single (one channel) mode. 31 | This parameter can be set to ENABLE or DISABLE */ 32 | 33 | FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in 34 | Continuous or Single mode. 35 | This parameter can be set to ENABLE or DISABLE. */ 36 | 37 | uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog 38 | to digital conversion of regular channels. This parameter 39 | can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ 40 | 41 | uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. 42 | This parameter can be a value of @ref ADC_data_align */ 43 | 44 | uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted 45 | using the sequencer for regular channel group. 46 | This parameter must range from 1 to 16. */ 47 | } ADC_InitTypeDef; 48 | 49 | /* ADC_mode */ 50 | #define ADC_Mode_Independent ((uint32_t)0x00000000) 51 | 52 | /* ADC_external_trigger_sources_for_regular_channels_conversion */ 53 | #define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) 54 | #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) 55 | #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) 56 | #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) 57 | #define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) 58 | #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) 59 | #define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) 60 | #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) 61 | 62 | /* ADC_data_align */ 63 | #define ADC_DataAlign_Right ((uint32_t)0x00000000) 64 | #define ADC_DataAlign_Left ((uint32_t)0x00000800) 65 | 66 | /* ADC_channels */ 67 | #define ADC_Channel_0 ((uint8_t)0x00) 68 | #define ADC_Channel_1 ((uint8_t)0x01) 69 | #define ADC_Channel_2 ((uint8_t)0x02) 70 | #define ADC_Channel_3 ((uint8_t)0x03) 71 | #define ADC_Channel_4 ((uint8_t)0x04) 72 | #define ADC_Channel_5 ((uint8_t)0x05) 73 | #define ADC_Channel_6 ((uint8_t)0x06) 74 | #define ADC_Channel_7 ((uint8_t)0x07) 75 | #define ADC_Channel_8 ((uint8_t)0x08) 76 | #define ADC_Channel_9 ((uint8_t)0x09) 77 | 78 | #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) 79 | #define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9) 80 | 81 | /* ADC_sampling_time */ 82 | #define ADC_SampleTime_3Cycles ((uint8_t)0x00) 83 | #define ADC_SampleTime_9Cycles ((uint8_t)0x01) 84 | #define ADC_SampleTime_15Cycles ((uint8_t)0x02) 85 | #define ADC_SampleTime_30Cycles ((uint8_t)0x03) 86 | #define ADC_SampleTime_43Cycles ((uint8_t)0x04) 87 | #define ADC_SampleTime_57Cycles ((uint8_t)0x05) 88 | #define ADC_SampleTime_73Cycles ((uint8_t)0x06) 89 | #define ADC_SampleTime_241Cycles ((uint8_t)0x07) 90 | 91 | /* ADC_external_trigger_sources_for_injected_channels_conversion */ 92 | #define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) 93 | #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) 94 | #define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) 95 | #define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) 96 | #define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) 97 | #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) 98 | 99 | /* ADC_injected_channel_selection */ 100 | #define ADC_InjectedChannel_1 ((uint8_t)0x14) 101 | #define ADC_InjectedChannel_2 ((uint8_t)0x18) 102 | #define ADC_InjectedChannel_3 ((uint8_t)0x1C) 103 | #define ADC_InjectedChannel_4 ((uint8_t)0x20) 104 | 105 | /* ADC_analog_watchdog_selection */ 106 | #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) 107 | #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) 108 | #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) 109 | #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) 110 | #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) 111 | #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) 112 | #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) 113 | 114 | /* ADC_interrupts_definition */ 115 | #define ADC_IT_EOC ((uint16_t)0x0220) 116 | #define ADC_IT_AWD ((uint16_t)0x0140) 117 | #define ADC_IT_JEOC ((uint16_t)0x0480) 118 | 119 | /* ADC_flags_definition */ 120 | #define ADC_FLAG_AWD ((uint8_t)0x01) 121 | #define ADC_FLAG_EOC ((uint8_t)0x02) 122 | #define ADC_FLAG_JEOC ((uint8_t)0x04) 123 | #define ADC_FLAG_JSTRT ((uint8_t)0x08) 124 | #define ADC_FLAG_STRT ((uint8_t)0x10) 125 | 126 | /* ADC_calibration_voltage_definition */ 127 | #define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000) 128 | #define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) 129 | 130 | /* ADC_external_trigger_sources_delay_channels_definition */ 131 | #define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000) 132 | #define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00020000) 133 | 134 | 135 | void ADC_DeInit(ADC_TypeDef *ADCx); 136 | void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); 137 | void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); 138 | void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); 139 | void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); 140 | void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); 141 | void ADC_ResetCalibration(ADC_TypeDef *ADCx); 142 | FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); 143 | void ADC_StartCalibration(ADC_TypeDef *ADCx); 144 | FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); 145 | void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); 146 | FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); 147 | void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); 148 | void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); 149 | void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 150 | void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); 151 | uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); 152 | void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); 153 | void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); 154 | void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); 155 | void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); 156 | void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); 157 | FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); 158 | void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 159 | void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); 160 | void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); 161 | uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); 162 | void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); 163 | void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); 164 | void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); 165 | FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); 166 | void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); 167 | ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); 168 | void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); 169 | void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL); 170 | void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim); 171 | 172 | #ifdef __cplusplus 173 | } 174 | #endif 175 | 176 | #endif /*__CH32V00x_ADC_H */ 177 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_dbgmcu.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * DBGMCU firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_DBGMCU_H 14 | #define __CH32V00x_DBGMCU_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* CFGR0 Register */ 23 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000001) 24 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000002) 25 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000010) 26 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000020) 27 | 28 | uint32_t DBGMCU_GetREVID(void); 29 | uint32_t DBGMCU_GetDEVID(void); 30 | uint32_t __get_DEBUG_CR(void); 31 | void __set_DEBUG_CR(uint32_t value); 32 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 33 | 34 | #ifdef __cplusplus 35 | } 36 | #endif 37 | 38 | #endif /* __CH32V00x_DBGMCU_H */ 39 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_dma.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_dma.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * DMA firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_DMA_H 14 | #define __CH32V00x_DMA_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* DMA Init structure definition */ 23 | typedef struct 24 | { 25 | uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ 26 | 27 | uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ 28 | 29 | uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. 30 | This parameter can be a value of @ref DMA_data_transfer_direction */ 31 | 32 | uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. 33 | The data unit is equal to the configuration set in DMA_PeripheralDataSize 34 | or DMA_MemoryDataSize members depending in the transfer direction. */ 35 | 36 | uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. 37 | This parameter can be a value of @ref DMA_peripheral_incremented_mode */ 38 | 39 | uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. 40 | This parameter can be a value of @ref DMA_memory_incremented_mode */ 41 | 42 | uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. 43 | This parameter can be a value of @ref DMA_peripheral_data_size */ 44 | 45 | uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. 46 | This parameter can be a value of @ref DMA_memory_data_size */ 47 | 48 | uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. 49 | This parameter can be a value of @ref DMA_circular_normal_mode. 50 | @note: The circular buffer mode cannot be used if the memory-to-memory 51 | data transfer is configured on the selected Channel */ 52 | 53 | uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. 54 | This parameter can be a value of @ref DMA_priority_level */ 55 | 56 | uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. 57 | This parameter can be a value of @ref DMA_memory_to_memory */ 58 | } DMA_InitTypeDef; 59 | 60 | /* DMA_data_transfer_direction */ 61 | #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) 62 | #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) 63 | 64 | /* DMA_peripheral_incremented_mode */ 65 | #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) 66 | #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) 67 | 68 | /* DMA_memory_incremented_mode */ 69 | #define DMA_MemoryInc_Enable ((uint32_t)0x00000080) 70 | #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) 71 | 72 | /* DMA_peripheral_data_size */ 73 | #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) 74 | #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) 75 | #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) 76 | 77 | /* DMA_memory_data_size */ 78 | #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 79 | #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) 80 | #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) 81 | 82 | /* DMA_circular_normal_mode */ 83 | #define DMA_Mode_Circular ((uint32_t)0x00000020) 84 | #define DMA_Mode_Normal ((uint32_t)0x00000000) 85 | 86 | /* DMA_priority_level */ 87 | #define DMA_Priority_VeryHigh ((uint32_t)0x00003000) 88 | #define DMA_Priority_High ((uint32_t)0x00002000) 89 | #define DMA_Priority_Medium ((uint32_t)0x00001000) 90 | #define DMA_Priority_Low ((uint32_t)0x00000000) 91 | 92 | /* DMA_memory_to_memory */ 93 | #define DMA_M2M_Enable ((uint32_t)0x00004000) 94 | #define DMA_M2M_Disable ((uint32_t)0x00000000) 95 | 96 | /* DMA_interrupts_definition */ 97 | #define DMA_IT_TC ((uint32_t)0x00000002) 98 | #define DMA_IT_HT ((uint32_t)0x00000004) 99 | #define DMA_IT_TE ((uint32_t)0x00000008) 100 | 101 | #define DMA1_IT_GL1 ((uint32_t)0x00000001) 102 | #define DMA1_IT_TC1 ((uint32_t)0x00000002) 103 | #define DMA1_IT_HT1 ((uint32_t)0x00000004) 104 | #define DMA1_IT_TE1 ((uint32_t)0x00000008) 105 | #define DMA1_IT_GL2 ((uint32_t)0x00000010) 106 | #define DMA1_IT_TC2 ((uint32_t)0x00000020) 107 | #define DMA1_IT_HT2 ((uint32_t)0x00000040) 108 | #define DMA1_IT_TE2 ((uint32_t)0x00000080) 109 | #define DMA1_IT_GL3 ((uint32_t)0x00000100) 110 | #define DMA1_IT_TC3 ((uint32_t)0x00000200) 111 | #define DMA1_IT_HT3 ((uint32_t)0x00000400) 112 | #define DMA1_IT_TE3 ((uint32_t)0x00000800) 113 | #define DMA1_IT_GL4 ((uint32_t)0x00001000) 114 | #define DMA1_IT_TC4 ((uint32_t)0x00002000) 115 | #define DMA1_IT_HT4 ((uint32_t)0x00004000) 116 | #define DMA1_IT_TE4 ((uint32_t)0x00008000) 117 | #define DMA1_IT_GL5 ((uint32_t)0x00010000) 118 | #define DMA1_IT_TC5 ((uint32_t)0x00020000) 119 | #define DMA1_IT_HT5 ((uint32_t)0x00040000) 120 | #define DMA1_IT_TE5 ((uint32_t)0x00080000) 121 | #define DMA1_IT_GL6 ((uint32_t)0x00100000) 122 | #define DMA1_IT_TC6 ((uint32_t)0x00200000) 123 | #define DMA1_IT_HT6 ((uint32_t)0x00400000) 124 | #define DMA1_IT_TE6 ((uint32_t)0x00800000) 125 | #define DMA1_IT_GL7 ((uint32_t)0x01000000) 126 | #define DMA1_IT_TC7 ((uint32_t)0x02000000) 127 | #define DMA1_IT_HT7 ((uint32_t)0x04000000) 128 | #define DMA1_IT_TE7 ((uint32_t)0x08000000) 129 | 130 | /* DMA_flags_definition */ 131 | #define DMA1_FLAG_GL1 ((uint32_t)0x00000001) 132 | #define DMA1_FLAG_TC1 ((uint32_t)0x00000002) 133 | #define DMA1_FLAG_HT1 ((uint32_t)0x00000004) 134 | #define DMA1_FLAG_TE1 ((uint32_t)0x00000008) 135 | #define DMA1_FLAG_GL2 ((uint32_t)0x00000010) 136 | #define DMA1_FLAG_TC2 ((uint32_t)0x00000020) 137 | #define DMA1_FLAG_HT2 ((uint32_t)0x00000040) 138 | #define DMA1_FLAG_TE2 ((uint32_t)0x00000080) 139 | #define DMA1_FLAG_GL3 ((uint32_t)0x00000100) 140 | #define DMA1_FLAG_TC3 ((uint32_t)0x00000200) 141 | #define DMA1_FLAG_HT3 ((uint32_t)0x00000400) 142 | #define DMA1_FLAG_TE3 ((uint32_t)0x00000800) 143 | #define DMA1_FLAG_GL4 ((uint32_t)0x00001000) 144 | #define DMA1_FLAG_TC4 ((uint32_t)0x00002000) 145 | #define DMA1_FLAG_HT4 ((uint32_t)0x00004000) 146 | #define DMA1_FLAG_TE4 ((uint32_t)0x00008000) 147 | #define DMA1_FLAG_GL5 ((uint32_t)0x00010000) 148 | #define DMA1_FLAG_TC5 ((uint32_t)0x00020000) 149 | #define DMA1_FLAG_HT5 ((uint32_t)0x00040000) 150 | #define DMA1_FLAG_TE5 ((uint32_t)0x00080000) 151 | #define DMA1_FLAG_GL6 ((uint32_t)0x00100000) 152 | #define DMA1_FLAG_TC6 ((uint32_t)0x00200000) 153 | #define DMA1_FLAG_HT6 ((uint32_t)0x00400000) 154 | #define DMA1_FLAG_TE6 ((uint32_t)0x00800000) 155 | #define DMA1_FLAG_GL7 ((uint32_t)0x01000000) 156 | #define DMA1_FLAG_TC7 ((uint32_t)0x02000000) 157 | #define DMA1_FLAG_HT7 ((uint32_t)0x04000000) 158 | #define DMA1_FLAG_TE7 ((uint32_t)0x08000000) 159 | 160 | 161 | void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); 162 | void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); 163 | void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); 164 | void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); 165 | void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); 166 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); 167 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); 168 | FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); 169 | void DMA_ClearFlag(uint32_t DMAy_FLAG); 170 | ITStatus DMA_GetITStatus(uint32_t DMAy_IT); 171 | void DMA_ClearITPendingBit(uint32_t DMAy_IT); 172 | 173 | #ifdef __cplusplus 174 | } 175 | #endif 176 | 177 | #endif /*__CH32V00x_DMA_H */ 178 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_exti.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_exti.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * EXTI firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_EXTI_H 14 | #define __CH32V00x_EXTI_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* EXTI mode enumeration */ 23 | typedef enum 24 | { 25 | EXTI_Mode_Interrupt = 0x00, 26 | EXTI_Mode_Event = 0x04 27 | } EXTIMode_TypeDef; 28 | 29 | /* EXTI Trigger enumeration */ 30 | typedef enum 31 | { 32 | EXTI_Trigger_Rising = 0x08, 33 | EXTI_Trigger_Falling = 0x0C, 34 | EXTI_Trigger_Rising_Falling = 0x10 35 | } EXTITrigger_TypeDef; 36 | 37 | /* EXTI Init Structure definition */ 38 | typedef struct 39 | { 40 | uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. 41 | This parameter can be any combination of @ref EXTI_Lines */ 42 | 43 | EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. 44 | This parameter can be a value of @ref EXTIMode_TypeDef */ 45 | 46 | EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. 47 | This parameter can be a value of @ref EXTIMode_TypeDef */ 48 | 49 | FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. 50 | This parameter can be set either to ENABLE or DISABLE */ 51 | } EXTI_InitTypeDef; 52 | 53 | /* EXTI_Lines */ 54 | #define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ 55 | #define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ 56 | #define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ 57 | #define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ 58 | #define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ 59 | #define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ 60 | #define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ 61 | #define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ 62 | #define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ 63 | #define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ 64 | 65 | void EXTI_DeInit(void); 66 | void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); 67 | void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); 68 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 69 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 70 | void EXTI_ClearFlag(uint32_t EXTI_Line); 71 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 72 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 73 | 74 | #ifdef __cplusplus 75 | } 76 | #endif 77 | 78 | #endif /* __CH32V00x_EXTI_H */ 79 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_flash.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_flash.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the FLASH 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_FLASH_H 14 | #define __CH32V00x_FLASH_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* FLASH Status */ 23 | typedef enum 24 | { 25 | FLASH_BUSY = 1, 26 | FLASH_ERROR_PG, 27 | FLASH_ERROR_WRP, 28 | FLASH_COMPLETE, 29 | FLASH_TIMEOUT 30 | } FLASH_Status; 31 | 32 | /* Flash_Latency */ 33 | #define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ 34 | #define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ 35 | #define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ 36 | 37 | /* Values to be used with CH32V00x devices (1page = 64Byte) */ 38 | #define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ 39 | #define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ 40 | #define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ 41 | #define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */ 42 | #define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ 43 | #define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ 44 | #define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ 45 | #define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ 46 | #define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ 47 | #define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ 48 | #define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ 49 | #define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ 50 | #define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ 51 | #define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ 52 | #define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ 53 | #define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ 54 | 55 | #define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ 56 | 57 | /* Option_Bytes_IWatchdog */ 58 | #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ 59 | #define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ 60 | 61 | /* Option_Bytes_nRST_STOP */ 62 | #define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ 63 | #define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ 64 | 65 | /* Option_Bytes_nRST_STDBY */ 66 | #define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ 67 | #define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ 68 | 69 | /* Option_Bytes_RST_ENandDT */ 70 | #define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ 71 | #define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ 72 | #define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ 73 | #define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */ 74 | 75 | /* FLASH_Interrupts */ 76 | #define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ 77 | #define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ 78 | #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ 79 | #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ 80 | 81 | /* FLASH_Flags */ 82 | #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ 83 | #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ 84 | #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ 85 | #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ 86 | 87 | #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ 88 | #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ 89 | #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ 90 | 91 | /* System_Reset_Start_Mode */ 92 | #define Start_Mode_USER ((uint32_t)0x00000000) 93 | #define Start_Mode_BOOT ((uint32_t)0x00004000) 94 | 95 | 96 | /*Functions used for all CH32V00x devices*/ 97 | void FLASH_SetLatency(uint32_t FLASH_Latency); 98 | void FLASH_Unlock(void); 99 | void FLASH_Lock(void); 100 | FLASH_Status FLASH_ErasePage(uint32_t Page_Address); 101 | FLASH_Status FLASH_EraseAllPages(void); 102 | FLASH_Status FLASH_EraseOptionBytes(void); 103 | FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); 104 | FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); 105 | FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); 106 | FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); 107 | FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); 108 | FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY, uint16_t OB_RST); 109 | uint32_t FLASH_GetUserOptionByte(void); 110 | uint32_t FLASH_GetWriteProtectionOptionByte(void); 111 | FlagStatus FLASH_GetReadOutProtectionStatus(void); 112 | void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); 113 | FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); 114 | void FLASH_ClearFlag(uint32_t FLASH_FLAG); 115 | FLASH_Status FLASH_GetStatus(void); 116 | FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); 117 | void FLASH_Unlock_Fast(void); 118 | void FLASH_Lock_Fast(void); 119 | void FLASH_BufReset(void); 120 | void FLASH_BufLoad(uint32_t Address, uint32_t Data0); 121 | void FLASH_ErasePage_Fast(uint32_t Page_Address); 122 | void FLASH_ProgramPage_Fast(uint32_t Page_Address); 123 | void SystemReset_StartMode(uint32_t Mode); 124 | 125 | #ifdef __cplusplus 126 | } 127 | #endif 128 | 129 | #endif /* __CH32V00x_FLASH_H */ 130 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_gpio.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_gpio.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * GPIO firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_GPIO_H 14 | #define __CH32V00x_GPIO_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* Output Maximum frequency selection */ 23 | typedef enum 24 | { 25 | GPIO_Speed_10MHz = 1, 26 | GPIO_Speed_2MHz, 27 | GPIO_Speed_50MHz 28 | } GPIOSpeed_TypeDef; 29 | 30 | /* Configuration Mode enumeration */ 31 | typedef enum 32 | { 33 | GPIO_Mode_AIN = 0x0, 34 | GPIO_Mode_IN_FLOATING = 0x04, 35 | GPIO_Mode_IPD = 0x28, 36 | GPIO_Mode_IPU = 0x48, 37 | GPIO_Mode_Out_OD = 0x14, 38 | GPIO_Mode_Out_PP = 0x10, 39 | GPIO_Mode_AF_OD = 0x1C, 40 | GPIO_Mode_AF_PP = 0x18 41 | } GPIOMode_TypeDef; 42 | 43 | /* GPIO Init structure definition */ 44 | typedef struct 45 | { 46 | uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. 47 | This parameter can be any value of @ref GPIO_pins_define */ 48 | 49 | GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. 50 | This parameter can be a value of @ref GPIOSpeed_TypeDef */ 51 | 52 | GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. 53 | This parameter can be a value of @ref GPIOMode_TypeDef */ 54 | } GPIO_InitTypeDef; 55 | 56 | /* Bit_SET and Bit_RESET enumeration */ 57 | typedef enum 58 | { 59 | Bit_RESET = 0, 60 | Bit_SET 61 | } BitAction; 62 | 63 | /* GPIO_pins_define */ 64 | #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ 65 | #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ 66 | #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ 67 | #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ 68 | #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ 69 | #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ 70 | #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ 71 | #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ 72 | #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ 73 | 74 | /* GPIO_Remap_define */ 75 | #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ 76 | #define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */ 77 | #define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */ 78 | #define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */ 79 | #define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */ 80 | #define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */ 81 | #define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */ 82 | #define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */ 83 | #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ 84 | #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ 85 | #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ 86 | #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ 87 | #define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ 88 | #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ 89 | #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ 90 | #define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ 91 | #define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ 92 | 93 | /* GPIO_Port_Sources */ 94 | #define GPIO_PortSourceGPIOA ((uint8_t)0x00) 95 | #define GPIO_PortSourceGPIOC ((uint8_t)0x02) 96 | #define GPIO_PortSourceGPIOD ((uint8_t)0x03) 97 | 98 | /* GPIO_Pin_sources */ 99 | #define GPIO_PinSource0 ((uint8_t)0x00) 100 | #define GPIO_PinSource1 ((uint8_t)0x01) 101 | #define GPIO_PinSource2 ((uint8_t)0x02) 102 | #define GPIO_PinSource3 ((uint8_t)0x03) 103 | #define GPIO_PinSource4 ((uint8_t)0x04) 104 | #define GPIO_PinSource5 ((uint8_t)0x05) 105 | #define GPIO_PinSource6 ((uint8_t)0x06) 106 | #define GPIO_PinSource7 ((uint8_t)0x07) 107 | 108 | void GPIO_DeInit(GPIO_TypeDef *GPIOx); 109 | void GPIO_AFIODeInit(void); 110 | void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); 111 | void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); 112 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 113 | uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); 114 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 115 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); 116 | void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 117 | void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 118 | void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); 119 | void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); 120 | void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); 121 | void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); 122 | void GPIO_EventOutputCmd(FunctionalState NewState); 123 | void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); 124 | void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); 125 | 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | 130 | #endif /* __CH32V00x_GPIO_H */ 131 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_iwdg.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_iwdg.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * IWDG firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_IWDG_H 14 | #define __CH32V00x_IWDG_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* IWDG_WriteAccess */ 23 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 24 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 25 | 26 | /* IWDG_prescaler */ 27 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 28 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 29 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 30 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 31 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 32 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 33 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 34 | 35 | /* IWDG_Flag */ 36 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 37 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 38 | 39 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 40 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 41 | void IWDG_SetReload(uint16_t Reload); 42 | void IWDG_ReloadCounter(void); 43 | void IWDG_Enable(void); 44 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 45 | 46 | #ifdef __cplusplus 47 | } 48 | #endif 49 | 50 | #endif /* __CH32V00x_IWDG_H */ 51 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_misc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_misc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * miscellaneous firmware library functions. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00X_MISC_H 14 | #define __CH32V00X_MISC_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* NVIC Init Structure definition */ 23 | typedef struct 24 | { 25 | uint8_t NVIC_IRQChannel; 26 | uint8_t NVIC_IRQChannelPreemptionPriority; 27 | uint8_t NVIC_IRQChannelSubPriority; 28 | FunctionalState NVIC_IRQChannelCmd; 29 | } NVIC_InitTypeDef; 30 | 31 | 32 | /* Preemption_Priority_Group */ 33 | #define NVIC_PriorityGroup_0 ((uint32_t)0x00) 34 | #define NVIC_PriorityGroup_1 ((uint32_t)0x01) 35 | #define NVIC_PriorityGroup_2 ((uint32_t)0x02) 36 | #define NVIC_PriorityGroup_3 ((uint32_t)0x03) 37 | #define NVIC_PriorityGroup_4 ((uint32_t)0x04) 38 | 39 | 40 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 41 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 42 | 43 | #ifdef __cplusplus 44 | } 45 | #endif 46 | 47 | #endif /* __CH32V00x_MISC_H */ 48 | 49 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_opa.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_opa.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * OPA firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_OPA_H 14 | #define __CH32V00x_OPA_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include "ch32v00x.h" 21 | 22 | /* OPA PSEL enumeration */ 23 | typedef enum 24 | { 25 | CHP0 = 0, 26 | CHP1 27 | } OPA_PSEL_TypeDef; 28 | 29 | /* OPA NSEL enumeration */ 30 | typedef enum 31 | { 32 | CHN0 = 0, 33 | CHN1 34 | } OPA_NSEL_TypeDef; 35 | 36 | 37 | /* OPA Init Structure definition */ 38 | typedef struct 39 | { 40 | OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ 41 | OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ 42 | } OPA_InitTypeDef; 43 | 44 | void OPA_DeInit(void); 45 | void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); 46 | void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); 47 | void OPA_Cmd(FunctionalState NewState); 48 | 49 | #ifdef __cplusplus 50 | } 51 | #endif 52 | 53 | #endif 54 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_pwr.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_pwr.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the PWR 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_PWR_H 14 | #define __CH32V00x_PWR_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* PVD_detection_level */ 23 | #define PWR_PVDLevel_2V9 ((uint32_t)0x00000000) 24 | #define PWR_PVDLevel_3V1 ((uint32_t)0x00000020) 25 | #define PWR_PVDLevel_3V3 ((uint32_t)0x00000040) 26 | #define PWR_PVDLevel_3V5 ((uint32_t)0x00000060) 27 | #define PWR_PVDLevel_3V7 ((uint32_t)0x00000080) 28 | #define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0) 29 | #define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0) 30 | #define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0) 31 | 32 | /* PWR_AWU_Prescaler */ 33 | #define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000) 34 | #define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) 35 | #define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) 36 | #define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) 37 | #define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) 38 | #define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) 39 | #define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) 40 | #define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) 41 | #define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) 42 | #define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) 43 | #define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) 44 | #define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) 45 | #define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) 46 | #define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) 47 | #define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) 48 | 49 | /* STOP_mode_entry */ 50 | #define PWR_STANDBYEntry_WFI ((uint8_t)0x01) 51 | #define PWR_STANDBYEntry_WFE ((uint8_t)0x02) 52 | 53 | /* PWR_Flag */ 54 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 55 | 56 | void PWR_DeInit(void); 57 | void PWR_PVDCmd(FunctionalState NewState); 58 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 59 | void PWR_AutoWakeUpCmd(FunctionalState NewState); 60 | void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler); 61 | void PWR_AWU_SetWindowValue(uint8_t WindowValue); 62 | void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry); 63 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 64 | 65 | #ifdef __cplusplus 66 | } 67 | #endif 68 | 69 | #endif /* __CH32V00x_PWR_H */ 70 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_rcc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_rcc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the RCC firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #ifndef __CH32V00x_RCC_H 13 | #define __CH32V00x_RCC_H 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | #include 20 | 21 | /* RCC_Exported_Types */ 22 | typedef struct 23 | { 24 | uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ 25 | uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ 26 | uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ 27 | uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ 28 | uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ 29 | } RCC_ClocksTypeDef; 30 | 31 | /* HSE_configuration */ 32 | #define RCC_HSE_OFF ((uint32_t)0x00000000) 33 | #define RCC_HSE_ON ((uint32_t)0x00010000) 34 | #define RCC_HSE_Bypass ((uint32_t)0x00040000) 35 | 36 | /* PLL_entry_clock_source */ 37 | #define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000) 38 | #define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000) 39 | 40 | /* System_clock_source */ 41 | #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 42 | #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 43 | #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 44 | 45 | /* AHB_clock_source */ 46 | #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 47 | #define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) 48 | #define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) 49 | #define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) 50 | #define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) 51 | #define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) 52 | #define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) 53 | #define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) 54 | #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 55 | #define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) 56 | #define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) 57 | #define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) 58 | #define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) 59 | 60 | /* RCC_Interrupt_source */ 61 | #define RCC_IT_LSIRDY ((uint8_t)0x01) 62 | #define RCC_IT_HSIRDY ((uint8_t)0x04) 63 | #define RCC_IT_HSERDY ((uint8_t)0x08) 64 | #define RCC_IT_PLLRDY ((uint8_t)0x10) 65 | #define RCC_IT_CSS ((uint8_t)0x80) 66 | 67 | /* ADC_clock_source */ 68 | #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) 69 | #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) 70 | #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) 71 | #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) 72 | #define RCC_PCLK2_Div12 ((uint32_t)0x0000A000) 73 | #define RCC_PCLK2_Div16 ((uint32_t)0x0000E000) 74 | #define RCC_PCLK2_Div24 ((uint32_t)0x0000A800) 75 | #define RCC_PCLK2_Div32 ((uint32_t)0x0000E800) 76 | #define RCC_PCLK2_Div48 ((uint32_t)0x0000B000) 77 | #define RCC_PCLK2_Div64 ((uint32_t)0x0000F000) 78 | #define RCC_PCLK2_Div96 ((uint32_t)0x0000B800) 79 | #define RCC_PCLK2_Div128 ((uint32_t)0x0000F800) 80 | 81 | /* AHB_peripheral */ 82 | #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) 83 | #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) 84 | 85 | /* APB2_peripheral */ 86 | #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) 87 | #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) 88 | #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) 89 | #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) 90 | #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) 91 | #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) 92 | #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 93 | #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) 94 | 95 | /* APB1_peripheral */ 96 | #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 97 | #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 98 | #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 99 | #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 100 | 101 | /* Clock_source_to_output_on_MCO_pin */ 102 | #define RCC_MCO_NoClock ((uint8_t)0x00) 103 | #define RCC_MCO_SYSCLK ((uint8_t)0x04) 104 | #define RCC_MCO_HSI ((uint8_t)0x05) 105 | #define RCC_MCO_HSE ((uint8_t)0x06) 106 | #define RCC_MCO_PLLCLK ((uint8_t)0x07) 107 | 108 | /* RCC_Flag */ 109 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 110 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) 111 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 112 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 113 | #define RCC_FLAG_PINRST ((uint8_t)0x7A) 114 | #define RCC_FLAG_PORRST ((uint8_t)0x7B) 115 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 116 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 117 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 118 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 119 | 120 | /* SysTick_clock_source */ 121 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 122 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 123 | 124 | void RCC_DeInit(void); 125 | void RCC_HSEConfig(uint32_t RCC_HSE); 126 | ErrorStatus RCC_WaitForHSEStartUp(void); 127 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 128 | void RCC_HSICmd(FunctionalState NewState); 129 | void RCC_PLLConfig(uint32_t RCC_PLLSource); 130 | void RCC_PLLCmd(FunctionalState NewState); 131 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 132 | uint8_t RCC_GetSYSCLKSource(void); 133 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 134 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 135 | void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); 136 | void RCC_LSICmd(FunctionalState NewState); 137 | void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); 138 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 139 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 140 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 141 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 142 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 143 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 144 | void RCC_MCOConfig(uint8_t RCC_MCO); 145 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 146 | void RCC_ClearFlag(void); 147 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); 148 | void RCC_ClearITPendingBit(uint8_t RCC_IT); 149 | 150 | #ifdef __cplusplus 151 | } 152 | #endif 153 | 154 | #endif /* __CH32V00x_RCC_H */ 155 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_spi.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_spi.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * SPI firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_SPI_H 14 | #define __CH32V00x_SPI_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* SPI Init structure definition */ 23 | typedef struct 24 | { 25 | uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. 26 | This parameter can be a value of @ref SPI_data_direction */ 27 | 28 | uint16_t SPI_Mode; /* Specifies the SPI operating mode. 29 | This parameter can be a value of @ref SPI_mode */ 30 | 31 | uint16_t SPI_DataSize; /* Specifies the SPI data size. 32 | This parameter can be a value of @ref SPI_data_size */ 33 | 34 | uint16_t SPI_CPOL; /* Specifies the serial clock steady state. 35 | This parameter can be a value of @ref SPI_Clock_Polarity */ 36 | 37 | uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. 38 | This parameter can be a value of @ref SPI_Clock_Phase */ 39 | 40 | uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by 41 | hardware (NSS pin) or by software using the SSI bit. 42 | This parameter can be a value of @ref SPI_Slave_Select_management */ 43 | 44 | uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be 45 | used to configure the transmit and receive SCK clock. 46 | This parameter can be a value of @ref SPI_BaudRate_Prescaler. 47 | @note The communication clock is derived from the master 48 | clock. The slave clock does not need to be set. */ 49 | 50 | uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */ 51 | 52 | uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ 53 | } SPI_InitTypeDef; 54 | 55 | /* SPI_data_direction */ 56 | #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 57 | #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 58 | #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 59 | #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 60 | 61 | /* SPI_mode */ 62 | #define SPI_Mode_Master ((uint16_t)0x0104) 63 | #define SPI_Mode_Slave ((uint16_t)0x0000) 64 | 65 | /* SPI_data_size */ 66 | #define SPI_DataSize_16b ((uint16_t)0x0800) 67 | #define SPI_DataSize_8b ((uint16_t)0x0000) 68 | 69 | /* SPI_Clock_Polarity */ 70 | #define SPI_CPOL_Low ((uint16_t)0x0000) 71 | #define SPI_CPOL_High ((uint16_t)0x0002) 72 | 73 | /* SPI_Clock_Phase */ 74 | #define SPI_CPHA_1Edge ((uint16_t)0x0000) 75 | #define SPI_CPHA_2Edge ((uint16_t)0x0001) 76 | 77 | /* SPI_Slave_Select_management */ 78 | #define SPI_NSS_Soft ((uint16_t)0x0200) 79 | #define SPI_NSS_Hard ((uint16_t)0x0000) 80 | 81 | /* SPI_BaudRate_Prescaler */ 82 | #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 83 | #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 84 | #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 85 | #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 86 | #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 87 | #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 88 | #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 89 | #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 90 | 91 | /* SPI_MSB transmission */ 92 | #define SPI_FirstBit_MSB ((uint16_t)0x0000) 93 | 94 | /* SPI_I2S_DMA_transfer_requests */ 95 | #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 96 | #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 97 | 98 | /* SPI_NSS_internal_software_management */ 99 | #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 100 | #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 101 | 102 | /* SPI_CRC_Transmit_Receive */ 103 | #define SPI_CRC_Tx ((uint8_t)0x00) 104 | #define SPI_CRC_Rx ((uint8_t)0x01) 105 | 106 | /* SPI_direction_transmit_receive */ 107 | #define SPI_Direction_Rx ((uint16_t)0xBFFF) 108 | #define SPI_Direction_Tx ((uint16_t)0x4000) 109 | 110 | /* SPI_I2S_interrupts_definition */ 111 | #define SPI_I2S_IT_TXE ((uint8_t)0x71) 112 | #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 113 | #define SPI_I2S_IT_ERR ((uint8_t)0x50) 114 | #define SPI_I2S_IT_OVR ((uint8_t)0x56) 115 | #define SPI_IT_MODF ((uint8_t)0x55) 116 | #define SPI_IT_CRCERR ((uint8_t)0x54) 117 | #define I2S_IT_UDR ((uint8_t)0x53) 118 | 119 | /* SPI_I2S_flags_definition */ 120 | #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 121 | #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 122 | #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 123 | #define I2S_FLAG_UDR ((uint16_t)0x0008) 124 | #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 125 | #define SPI_FLAG_MODF ((uint16_t)0x0020) 126 | #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 127 | #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 128 | 129 | void SPI_I2S_DeInit(SPI_TypeDef *SPIx); 130 | void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); 131 | void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); 132 | void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); 133 | void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 134 | void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 135 | void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); 136 | uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); 137 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); 138 | void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); 139 | void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); 140 | void SPI_TransmitCRC(SPI_TypeDef *SPIx); 141 | void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); 142 | uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); 143 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); 144 | void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); 145 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); 146 | void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); 147 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); 148 | void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); 149 | 150 | #ifdef __cplusplus 151 | } 152 | #endif 153 | 154 | #endif /*__CH32V00x_SPI_H */ 155 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_usart.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_usart.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the 7 | * USART firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_USART_H 14 | #define __CH32V00x_USART_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* USART Init Structure definition */ 23 | typedef struct 24 | { 25 | uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. 26 | The baud rate is computed using the following formula: 27 | - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) 28 | - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ 29 | 30 | uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. 31 | This parameter can be a value of @ref USART_Word_Length */ 32 | 33 | uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. 34 | This parameter can be a value of @ref USART_Stop_Bits */ 35 | 36 | uint16_t USART_Parity; /* Specifies the parity mode. 37 | This parameter can be a value of @ref USART_Parity 38 | @note When parity is enabled, the computed parity is inserted 39 | at the MSB position of the transmitted data (9th bit when 40 | the word length is set to 9 data bits; 8th bit when the 41 | word length is set to 8 data bits). */ 42 | 43 | uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. 44 | This parameter can be a value of @ref USART_Mode */ 45 | 46 | uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled 47 | or disabled. 48 | This parameter can be a value of @ref USART_Hardware_Flow_Control */ 49 | } USART_InitTypeDef; 50 | 51 | /* USART Clock Init Structure definition */ 52 | typedef struct 53 | { 54 | uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. 55 | This parameter can be a value of @ref USART_Clock */ 56 | 57 | uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. 58 | This parameter can be a value of @ref USART_Clock_Polarity */ 59 | 60 | uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. 61 | This parameter can be a value of @ref USART_Clock_Phase */ 62 | 63 | uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted 64 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. 65 | This parameter can be a value of @ref USART_Last_Bit */ 66 | } USART_ClockInitTypeDef; 67 | 68 | /* USART_Word_Length */ 69 | #define USART_WordLength_8b ((uint16_t)0x0000) 70 | #define USART_WordLength_9b ((uint16_t)0x1000) 71 | 72 | /* USART_Stop_Bits */ 73 | #define USART_StopBits_1 ((uint16_t)0x0000) 74 | #define USART_StopBits_0_5 ((uint16_t)0x1000) 75 | #define USART_StopBits_2 ((uint16_t)0x2000) 76 | #define USART_StopBits_1_5 ((uint16_t)0x3000) 77 | 78 | /* USART_Parity */ 79 | #define USART_Parity_No ((uint16_t)0x0000) 80 | #define USART_Parity_Even ((uint16_t)0x0400) 81 | #define USART_Parity_Odd ((uint16_t)0x0600) 82 | 83 | /* USART_Mode */ 84 | #define USART_Mode_Rx ((uint16_t)0x0004) 85 | #define USART_Mode_Tx ((uint16_t)0x0008) 86 | 87 | /* USART_Hardware_Flow_Control */ 88 | #define USART_HardwareFlowControl_None ((uint16_t)0x0000) 89 | #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) 90 | #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) 91 | #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) 92 | 93 | /* USART_Clock */ 94 | #define USART_Clock_Disable ((uint16_t)0x0000) 95 | #define USART_Clock_Enable ((uint16_t)0x0800) 96 | 97 | /* USART_Clock_Polarity */ 98 | #define USART_CPOL_Low ((uint16_t)0x0000) 99 | #define USART_CPOL_High ((uint16_t)0x0400) 100 | 101 | /* USART_Clock_Phase */ 102 | #define USART_CPHA_1Edge ((uint16_t)0x0000) 103 | #define USART_CPHA_2Edge ((uint16_t)0x0200) 104 | 105 | /* USART_Last_Bit */ 106 | #define USART_LastBit_Disable ((uint16_t)0x0000) 107 | #define USART_LastBit_Enable ((uint16_t)0x0100) 108 | 109 | /* USART_Interrupt_definition */ 110 | #define USART_IT_PE ((uint16_t)0x0028) 111 | #define USART_IT_TXE ((uint16_t)0x0727) 112 | #define USART_IT_TC ((uint16_t)0x0626) 113 | #define USART_IT_RXNE ((uint16_t)0x0525) 114 | #define USART_IT_ORE_RX ((uint16_t)0x0325) 115 | #define USART_IT_IDLE ((uint16_t)0x0424) 116 | #define USART_IT_LBD ((uint16_t)0x0846) 117 | #define USART_IT_CTS ((uint16_t)0x096A) 118 | #define USART_IT_ERR ((uint16_t)0x0060) 119 | #define USART_IT_ORE_ER ((uint16_t)0x0360) 120 | #define USART_IT_NE ((uint16_t)0x0260) 121 | #define USART_IT_FE ((uint16_t)0x0160) 122 | 123 | #define USART_IT_ORE USART_IT_ORE_ER 124 | 125 | /* USART_DMA_Requests */ 126 | #define USART_DMAReq_Tx ((uint16_t)0x0080) 127 | #define USART_DMAReq_Rx ((uint16_t)0x0040) 128 | 129 | /* USART_WakeUp_methods */ 130 | #define USART_WakeUp_IdleLine ((uint16_t)0x0000) 131 | #define USART_WakeUp_AddressMark ((uint16_t)0x0800) 132 | 133 | /* USART_LIN_Break_Detection_Length */ 134 | #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) 135 | #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) 136 | 137 | /* USART_IrDA_Low_Power */ 138 | #define USART_IrDAMode_LowPower ((uint16_t)0x0004) 139 | #define USART_IrDAMode_Normal ((uint16_t)0x0000) 140 | 141 | /* USART_Flags */ 142 | #define USART_FLAG_CTS ((uint16_t)0x0200) 143 | #define USART_FLAG_LBD ((uint16_t)0x0100) 144 | #define USART_FLAG_TXE ((uint16_t)0x0080) 145 | #define USART_FLAG_TC ((uint16_t)0x0040) 146 | #define USART_FLAG_RXNE ((uint16_t)0x0020) 147 | #define USART_FLAG_IDLE ((uint16_t)0x0010) 148 | #define USART_FLAG_ORE ((uint16_t)0x0008) 149 | #define USART_FLAG_NE ((uint16_t)0x0004) 150 | #define USART_FLAG_FE ((uint16_t)0x0002) 151 | #define USART_FLAG_PE ((uint16_t)0x0001) 152 | 153 | void USART_DeInit(USART_TypeDef *USARTx); 154 | void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); 155 | void USART_StructInit(USART_InitTypeDef *USART_InitStruct); 156 | void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); 157 | void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); 158 | void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); 159 | void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); 160 | void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); 161 | void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); 162 | void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); 163 | void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); 164 | void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); 165 | void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); 166 | void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); 167 | uint16_t USART_ReceiveData(USART_TypeDef *USARTx); 168 | void USART_SendBreak(USART_TypeDef *USARTx); 169 | void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); 170 | void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); 171 | void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); 172 | void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); 173 | void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); 174 | void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); 175 | void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); 176 | void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); 177 | void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); 178 | FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); 179 | void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); 180 | ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); 181 | void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); 182 | 183 | #ifdef __cplusplus 184 | } 185 | #endif 186 | 187 | #endif /* __CH32V00x_USART_H */ 188 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/inc/ch32v00x_wwdg.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_wwdg.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file contains all the functions prototypes for the WWDG 7 | * firmware library. 8 | ********************************************************************************* 9 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 10 | * Attention: This software (modified or not) and binary are used for 11 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 12 | *******************************************************************************/ 13 | #ifndef __CH32V00x_WWDG_H 14 | #define __CH32V00x_WWDG_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | #include 21 | 22 | /* WWDG_Prescaler */ 23 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 24 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 25 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 26 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 27 | 28 | void WWDG_DeInit(void); 29 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 30 | void WWDG_SetWindowValue(uint8_t WindowValue); 31 | void WWDG_EnableIT(void); 32 | void WWDG_SetCounter(uint8_t Counter); 33 | void WWDG_Enable(uint8_t Counter); 34 | FlagStatus WWDG_GetFlagStatus(void); 35 | void WWDG_ClearFlag(void); 36 | 37 | #ifdef __cplusplus 38 | } 39 | #endif 40 | 41 | #endif /* __CH32V00x_WWDG_H */ 42 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/src/ch32v00x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_dbgmcu.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the DBGMCU firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | 15 | #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) 16 | 17 | /********************************************************************* 18 | * @fn DBGMCU_GetREVID 19 | * 20 | * @brief Returns the device revision identifier. 21 | * 22 | * @return Revision identifier. 23 | */ 24 | uint32_t DBGMCU_GetREVID(void) 25 | { 26 | return ((*(uint32_t *)0x1FFFF7C4) >> 16); 27 | } 28 | 29 | /********************************************************************* 30 | * @fn DBGMCU_GetDEVID 31 | * 32 | * @brief Returns the device identifier. 33 | * 34 | * @return Device identifier. 35 | */ 36 | uint32_t DBGMCU_GetDEVID(void) 37 | { 38 | return ((*(uint32_t *)0x1FFFF7C4) & IDCODE_DEVID_MASK); 39 | } 40 | 41 | /********************************************************************* 42 | * @fn __get_DEBUG_CR 43 | * 44 | * @brief Return the DEBUGE Control Register 45 | * 46 | * @return DEBUGE Control value 47 | */ 48 | uint32_t __get_DEBUG_CR(void) 49 | { 50 | uint32_t result; 51 | 52 | __asm volatile("csrr %0,""0x7C0" : "=r"(result)); 53 | return (result); 54 | } 55 | 56 | /********************************************************************* 57 | * @fn __set_DEBUG_CR 58 | * 59 | * @brief Set the DEBUGE Control Register 60 | * 61 | * @param value - set DEBUGE Control value 62 | * 63 | * @return none 64 | */ 65 | void __set_DEBUG_CR(uint32_t value) 66 | { 67 | __asm volatile("csrw 0x7C0, %0" : : "r"(value)); 68 | } 69 | 70 | 71 | /********************************************************************* 72 | * @fn DBGMCU_Config 73 | * 74 | * @brief Configures the specified peripheral and low power mode behavior 75 | * when the MCU under Debug mode. 76 | * 77 | * @param DBGMCU_Periph - specifies the peripheral and low power mode. 78 | * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted 79 | * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted 80 | * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted 81 | * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted 82 | * NewState - ENABLE or DISABLE. 83 | * 84 | * @return none 85 | */ 86 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 87 | { 88 | uint32_t val; 89 | 90 | if(NewState != DISABLE) 91 | { 92 | __set_DEBUG_CR(DBGMCU_Periph); 93 | } 94 | else 95 | { 96 | val = __get_DEBUG_CR(); 97 | val &= ~(uint32_t)DBGMCU_Periph; 98 | __set_DEBUG_CR(val); 99 | } 100 | 101 | } 102 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/src/ch32v00x_exti.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_exti.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the EXTI firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | /* No interrupt selected */ 15 | #define EXTI_LINENONE ((uint32_t)0x00000) 16 | 17 | /********************************************************************* 18 | * @fn EXTI_DeInit 19 | * 20 | * @brief Deinitializes the EXTI peripheral registers to their default 21 | * reset values. 22 | * 23 | * @return none. 24 | */ 25 | void EXTI_DeInit(void) 26 | { 27 | EXTI->INTENR = 0x00000000; 28 | EXTI->EVENR = 0x00000000; 29 | EXTI->RTENR = 0x00000000; 30 | EXTI->FTENR = 0x00000000; 31 | EXTI->INTFR = 0x000FFFFF; 32 | } 33 | 34 | /********************************************************************* 35 | * @fn EXTI_Init 36 | * 37 | * @brief Initializes the EXTI peripheral according to the specified 38 | * parameters in the EXTI_InitStruct. 39 | * 40 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure 41 | * 42 | * @return none. 43 | */ 44 | void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) 45 | { 46 | uint32_t tmp = 0; 47 | 48 | tmp = (uint32_t)EXTI_BASE; 49 | if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) 50 | { 51 | EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; 52 | EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; 53 | tmp += EXTI_InitStruct->EXTI_Mode; 54 | *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; 55 | EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; 56 | EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; 57 | if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 58 | { 59 | EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; 60 | EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; 61 | } 62 | else 63 | { 64 | tmp = (uint32_t)EXTI_BASE; 65 | tmp += EXTI_InitStruct->EXTI_Trigger; 66 | *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; 67 | } 68 | } 69 | else 70 | { 71 | tmp += EXTI_InitStruct->EXTI_Mode; 72 | *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; 73 | } 74 | } 75 | 76 | /********************************************************************* 77 | * @fn EXTI_StructInit 78 | * 79 | * @brief Fills each EXTI_InitStruct member with its reset value. 80 | * 81 | * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure 82 | * 83 | * @return none. 84 | */ 85 | void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) 86 | { 87 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 88 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 89 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 90 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 91 | } 92 | 93 | /********************************************************************* 94 | * @fn EXTI_GenerateSWInterrupt 95 | * 96 | * @brief Generates a Software interrupt. 97 | * 98 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 99 | * 100 | * @return none. 101 | */ 102 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 103 | { 104 | EXTI->SWIEVR |= EXTI_Line; 105 | } 106 | 107 | /********************************************************************* 108 | * @fn EXTI_GetFlagStatus 109 | * 110 | * @brief Checks whether the specified EXTI line flag is set or not. 111 | * 112 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 113 | * 114 | * @return The new state of EXTI_Line (SET or RESET). 115 | */ 116 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 117 | { 118 | FlagStatus bitstatus = RESET; 119 | if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) 120 | { 121 | bitstatus = SET; 122 | } 123 | else 124 | { 125 | bitstatus = RESET; 126 | } 127 | return bitstatus; 128 | } 129 | 130 | /********************************************************************* 131 | * @fn EXTI_ClearFlag 132 | * 133 | * @brief Clears the EXTI's line pending flags. 134 | * 135 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 136 | * 137 | * @return None 138 | */ 139 | void EXTI_ClearFlag(uint32_t EXTI_Line) 140 | { 141 | EXTI->INTFR = EXTI_Line; 142 | } 143 | 144 | /********************************************************************* 145 | * @fn EXTI_GetITStatus 146 | * 147 | * @brief Checks whether the specified EXTI line is asserted or not. 148 | * 149 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 150 | * 151 | * @return The new state of EXTI_Line (SET or RESET). 152 | */ 153 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 154 | { 155 | ITStatus bitstatus = RESET; 156 | uint32_t enablestatus = 0; 157 | 158 | enablestatus = EXTI->INTENR & EXTI_Line; 159 | if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) 160 | { 161 | bitstatus = SET; 162 | } 163 | else 164 | { 165 | bitstatus = RESET; 166 | } 167 | return bitstatus; 168 | } 169 | 170 | /********************************************************************* 171 | * @fn EXTI_ClearITPendingBit 172 | * 173 | * @brief Clears the EXTI's line pending bits. 174 | * 175 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 176 | * 177 | * @return none 178 | */ 179 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 180 | { 181 | EXTI->INTFR = EXTI_Line; 182 | } 183 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/src/ch32v00x_gpio.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_gpio.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the GPIO firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | #include 14 | 15 | /* MASK */ 16 | #define LSB_MASK ((uint16_t)0xFFFF) 17 | #define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) 18 | #define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) 19 | #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) 20 | #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) 21 | 22 | /********************************************************************* 23 | * @fn GPIO_DeInit 24 | * 25 | * @brief Deinitializes the GPIOx peripheral registers to their default 26 | * reset values. 27 | * 28 | * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. 29 | * 30 | * @return none 31 | */ 32 | void GPIO_DeInit(GPIO_TypeDef *GPIOx) 33 | { 34 | if(GPIOx == GPIOA) 35 | { 36 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); 37 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); 38 | } 39 | else if(GPIOx == GPIOC) 40 | { 41 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); 42 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); 43 | } 44 | else if(GPIOx == GPIOD) 45 | { 46 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); 47 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); 48 | } 49 | } 50 | 51 | /********************************************************************* 52 | * @fn GPIO_AFIODeInit 53 | * 54 | * @brief Deinitializes the Alternate Functions (remap, event control 55 | * and EXTI configuration) registers to their default reset values. 56 | * 57 | * @return none 58 | */ 59 | void GPIO_AFIODeInit(void) 60 | { 61 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); 62 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); 63 | } 64 | 65 | /********************************************************************* 66 | * @fn GPIO_Init 67 | * 68 | * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. 69 | * 70 | * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that 71 | * contains the configuration information for the specified GPIO peripheral. 72 | * 73 | * @return none 74 | */ 75 | void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) 76 | { 77 | uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; 78 | uint32_t tmpreg = 0x00, pinmask = 0x00; 79 | 80 | currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); 81 | 82 | if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) 83 | { 84 | currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; 85 | } 86 | 87 | if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) 88 | { 89 | tmpreg = GPIOx->CFGLR; 90 | 91 | for(pinpos = 0x00; pinpos < 0x08; pinpos++) 92 | { 93 | pos = ((uint32_t)0x01) << pinpos; 94 | currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; 95 | 96 | if(currentpin == pos) 97 | { 98 | pos = pinpos << 2; 99 | pinmask = ((uint32_t)0x0F) << pos; 100 | tmpreg &= ~pinmask; 101 | tmpreg |= (currentmode << pos); 102 | 103 | if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 104 | { 105 | GPIOx->BCR = (((uint32_t)0x01) << pinpos); 106 | } 107 | else 108 | { 109 | if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 110 | { 111 | GPIOx->BSHR = (((uint32_t)0x01) << pinpos); 112 | } 113 | } 114 | } 115 | } 116 | GPIOx->CFGLR = tmpreg; 117 | } 118 | 119 | if(GPIO_InitStruct->GPIO_Pin > 0x00FF) 120 | { 121 | tmpreg = GPIOx->CFGHR; 122 | 123 | for(pinpos = 0x00; pinpos < 0x08; pinpos++) 124 | { 125 | pos = (((uint32_t)0x01) << (pinpos + 0x08)); 126 | currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); 127 | 128 | if(currentpin == pos) 129 | { 130 | pos = pinpos << 2; 131 | pinmask = ((uint32_t)0x0F) << pos; 132 | tmpreg &= ~pinmask; 133 | tmpreg |= (currentmode << pos); 134 | 135 | if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 136 | { 137 | GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); 138 | } 139 | 140 | if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 141 | { 142 | GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); 143 | } 144 | } 145 | } 146 | GPIOx->CFGHR = tmpreg; 147 | } 148 | } 149 | 150 | /********************************************************************* 151 | * @fn GPIO_StructInit 152 | * 153 | * @brief Fills each GPIO_InitStruct member with its default 154 | * 155 | * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure 156 | * which will be initialized. 157 | * 158 | * @return none 159 | */ 160 | void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) 161 | { 162 | GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; 163 | GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; 164 | GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; 165 | } 166 | 167 | /********************************************************************* 168 | * @fn GPIO_ReadInputDataBit 169 | * 170 | * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. 171 | * 172 | * @param GPIO_Pin - specifies the port bit to read. 173 | * This parameter can be GPIO_Pin_x where x can be (0..15). 174 | * 175 | * @return The input port pin value. 176 | */ 177 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) 178 | { 179 | uint8_t bitstatus = 0x00; 180 | 181 | if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) 182 | { 183 | bitstatus = (uint8_t)Bit_SET; 184 | } 185 | else 186 | { 187 | bitstatus = (uint8_t)Bit_RESET; 188 | } 189 | 190 | return bitstatus; 191 | } 192 | 193 | /********************************************************************* 194 | * @fn GPIO_ReadInputData 195 | * 196 | * @brief Reads the specified GPIO input data port. 197 | * 198 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. 199 | * 200 | * @return The input port pin value. 201 | */ 202 | uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) 203 | { 204 | return ((uint16_t)GPIOx->INDR); 205 | } 206 | 207 | /********************************************************************* 208 | * @fn GPIO_ReadOutputDataBit 209 | * 210 | * @brief Reads the specified output data port bit. 211 | * 212 | * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. 213 | * GPIO_Pin - specifies the port bit to read. 214 | * This parameter can be GPIO_Pin_x where x can be (0..15). 215 | * 216 | * @return none 217 | */ 218 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) 219 | { 220 | uint8_t bitstatus = 0x00; 221 | 222 | if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) 223 | { 224 | bitstatus = (uint8_t)Bit_SET; 225 | } 226 | else 227 | { 228 | bitstatus = (uint8_t)Bit_RESET; 229 | } 230 | 231 | return bitstatus; 232 | } 233 | 234 | /********************************************************************* 235 | * @fn GPIO_ReadOutputData 236 | * 237 | * @brief Reads the specified GPIO output data port. 238 | * 239 | * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. 240 | * 241 | * @return GPIO output port pin value. 242 | */ 243 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) 244 | { 245 | return ((uint16_t)GPIOx->OUTDR); 246 | } 247 | 248 | /********************************************************************* 249 | * @fn GPIO_SetBits 250 | * 251 | * @brief Sets the selected data port bits. 252 | * 253 | * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. 254 | * GPIO_Pin - specifies the port bits to be written. 255 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). 256 | * 257 | * @return none 258 | */ 259 | void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) 260 | { 261 | GPIOx->BSHR = GPIO_Pin; 262 | } 263 | 264 | /********************************************************************* 265 | * @fn GPIO_ResetBits 266 | * 267 | * @brief Clears the selected data port bits. 268 | * 269 | * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. 270 | * GPIO_Pin - specifies the port bits to be written. 271 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). 272 | * 273 | * @return none 274 | */ 275 | void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) 276 | { 277 | GPIOx->BCR = GPIO_Pin; 278 | } 279 | 280 | /********************************************************************* 281 | * @fn GPIO_WriteBit 282 | * 283 | * @brief Sets or clears the selected data port bit. 284 | * 285 | * @param GPIO_Pin - specifies the port bit to be written. 286 | * This parameter can be one of GPIO_Pin_x where x can be (0..15). 287 | * BitVal - specifies the value to be written to the selected bit. 288 | * Bit_SetL - to clear the port pin. 289 | * Bit_SetH - to set the port pin. 290 | * 291 | * @return none 292 | */ 293 | void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) 294 | { 295 | if(BitVal != Bit_RESET) 296 | { 297 | GPIOx->BSHR = GPIO_Pin; 298 | } 299 | else 300 | { 301 | GPIOx->BCR = GPIO_Pin; 302 | } 303 | } 304 | 305 | /********************************************************************* 306 | * @fn GPIO_Write 307 | * 308 | * @brief Writes data to the specified GPIO data port. 309 | * 310 | * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. 311 | * PortVal - specifies the value to be written to the port output data register. 312 | * 313 | * @return none 314 | */ 315 | void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) 316 | { 317 | GPIOx->OUTDR = PortVal; 318 | } 319 | 320 | /********************************************************************* 321 | * @fn GPIO_PinLockConfig 322 | * 323 | * @brief Locks GPIO Pins configuration registers. 324 | * 325 | * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. 326 | * GPIO_Pin - specifies the port bit to be written. 327 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). 328 | * 329 | * @return none 330 | */ 331 | void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) 332 | { 333 | uint32_t tmp = 0x00010000; 334 | 335 | tmp |= GPIO_Pin; 336 | GPIOx->LCKR = tmp; 337 | GPIOx->LCKR = GPIO_Pin; 338 | GPIOx->LCKR = tmp; 339 | tmp = GPIOx->LCKR; 340 | tmp = GPIOx->LCKR; 341 | } 342 | 343 | /********************************************************************* 344 | * @fn GPIO_PinRemapConfig 345 | * 346 | * @brief Changes the mapping of the specified pin. 347 | * 348 | * @param GPIO_Remap - selects the pin to remap. 349 | * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping 350 | * GPIO_PartialRemap_I2C1 - I2C1 Partial Alternate Function mapping 351 | * GPIO_PartialRemap_I2C1 - I2C1 Full Alternate Function mapping 352 | * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping 353 | * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping 354 | * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping 355 | * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping 356 | * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping 357 | * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping 358 | * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping 359 | * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping 360 | * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping 361 | * GPIO_Remap_PA12 - PA12 Alternate Function mapping 362 | * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping 363 | * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping 364 | * GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping 365 | * GPIO_Remap_SDI_Disable - SDI Disabled 366 | * NewState - ENABLE or DISABLE. 367 | * 368 | * @return none 369 | */ 370 | void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) 371 | { 372 | uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; 373 | 374 | tmpreg = AFIO->PCFR1; 375 | 376 | tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; 377 | tmp = GPIO_Remap & LSB_MASK; 378 | 379 | if((GPIO_Remap & 0x10000000) == 0x10000000) 380 | { 381 | tmpreg &= ~((1<<1) | (1<<22)); 382 | tmpreg |= ~DBGAFR_SDI_MASK; 383 | if(NewState != DISABLE) 384 | { 385 | tmpreg |= (GPIO_Remap & 0xEFFFFFFF); 386 | } 387 | 388 | } 389 | else if((GPIO_Remap & 0x80000000) == 0x80000000) 390 | { 391 | tmpreg &= ~((1<<2) | (1<<21)); 392 | tmpreg |= ~DBGAFR_SDI_MASK; 393 | if(NewState != DISABLE) 394 | { 395 | tmpreg |= (GPIO_Remap & 0x7FFFFFFF); 396 | } 397 | 398 | } 399 | else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))/* SDI */ 400 | { 401 | tmpreg &= DBGAFR_SDI_MASK; 402 | AFIO->PCFR1 &= DBGAFR_SDI_MASK; 403 | 404 | if(NewState != DISABLE) 405 | { 406 | tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); 407 | } 408 | } 409 | else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)/* [15:0] 2bit */ 410 | { 411 | tmp1 = ((uint32_t)0x03) << tmpmask; 412 | tmpreg &= ~tmp1; 413 | tmpreg |= ~DBGAFR_SDI_MASK; 414 | 415 | if(NewState != DISABLE) 416 | { 417 | tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); 418 | } 419 | } 420 | else/* [31:0] 1bit */ 421 | { 422 | tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); 423 | tmpreg |= ~DBGAFR_SDI_MASK; 424 | 425 | if(NewState != DISABLE) 426 | { 427 | tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); 428 | } 429 | } 430 | 431 | 432 | AFIO->PCFR1 = tmpreg; 433 | } 434 | 435 | /********************************************************************* 436 | * @fn GPIO_EXTILineConfig 437 | * 438 | * @brief Selects the GPIO pin used as EXTI Line. 439 | * 440 | * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. 441 | * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). 442 | * GPIO_PinSource - specifies the EXTI line to be configured. 443 | * This parameter can be GPIO_PinSourcex where x can be (0..7). 444 | * 445 | * @return none 446 | */ 447 | void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) 448 | { 449 | uint32_t tmp = 0x00; 450 | 451 | tmp = ((uint32_t)(3<<(GPIO_PinSource<<1))); 452 | AFIO->EXTICR &= ~tmp; 453 | AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1))); 454 | } 455 | 456 | 457 | 458 | 459 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/src/ch32v00x_iwdg.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_iwdg.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the IWDG firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | /* CTLR register bit mask */ 15 | #define CTLR_KEY_Reload ((uint16_t)0xAAAA) 16 | #define CTLR_KEY_Enable ((uint16_t)0xCCCC) 17 | 18 | /********************************************************************* 19 | * @fn IWDG_WriteAccessCmd 20 | * 21 | * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. 22 | * 23 | * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and 24 | * IWDG_RLDR registers. 25 | * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and 26 | * IWDG_RLDR registers. 27 | * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR 28 | * and IWDG_RLDR registers. 29 | * 30 | * @return none 31 | */ 32 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 33 | { 34 | IWDG->CTLR = IWDG_WriteAccess; 35 | } 36 | 37 | /********************************************************************* 38 | * @fn IWDG_SetPrescaler 39 | * 40 | * @brief Sets IWDG Prescaler value. 41 | * 42 | * @param IWDG_Prescaler - specifies the IWDG Prescaler value. 43 | * IWDG_Prescaler_4 - IWDG prescaler set to 4. 44 | * IWDG_Prescaler_8 - IWDG prescaler set to 8. 45 | * IWDG_Prescaler_16 - IWDG prescaler set to 16. 46 | * IWDG_Prescaler_32 - IWDG prescaler set to 32. 47 | * IWDG_Prescaler_64 - IWDG prescaler set to 64. 48 | * IWDG_Prescaler_128 - IWDG prescaler set to 128. 49 | * IWDG_Prescaler_256 - IWDG prescaler set to 256. 50 | * 51 | * @return none 52 | */ 53 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 54 | { 55 | IWDG->PSCR = IWDG_Prescaler; 56 | } 57 | 58 | /********************************************************************* 59 | * @fn IWDG_SetReload 60 | * 61 | * @brief Sets IWDG Reload value. 62 | * 63 | * @param Reload - specifies the IWDG Reload value. 64 | * This parameter must be a number between 0 and 0x0FFF. 65 | * 66 | * @return none 67 | */ 68 | void IWDG_SetReload(uint16_t Reload) 69 | { 70 | IWDG->RLDR = Reload; 71 | } 72 | 73 | /********************************************************************* 74 | * @fn IWDG_ReloadCounter 75 | * 76 | * @brief Reloads IWDG counter with value defined in the reload register. 77 | * 78 | * @return none 79 | */ 80 | void IWDG_ReloadCounter(void) 81 | { 82 | IWDG->CTLR = CTLR_KEY_Reload; 83 | } 84 | 85 | /********************************************************************* 86 | * @fn IWDG_Enable 87 | * 88 | * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). 89 | * 90 | * @return none 91 | */ 92 | void IWDG_Enable(void) 93 | { 94 | IWDG->CTLR = CTLR_KEY_Enable; 95 | } 96 | 97 | /********************************************************************* 98 | * @fn IWDG_GetFlagStatus 99 | * 100 | * @brief Checks whether the specified IWDG flag is set or not. 101 | * 102 | * @param IWDG_FLAG - specifies the flag to check. 103 | * IWDG_FLAG_PVU - Prescaler Value Update on going. 104 | * IWDG_FLAG_RVU - Reload Value Update on going. 105 | * 106 | * @return none 107 | */ 108 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 109 | { 110 | FlagStatus bitstatus = RESET; 111 | 112 | if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) 113 | { 114 | bitstatus = SET; 115 | } 116 | else 117 | { 118 | bitstatus = RESET; 119 | } 120 | 121 | return bitstatus; 122 | } 123 | 124 | 125 | 126 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/src/ch32v00x_misc.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_misc.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the miscellaneous firmware functions . 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | __IO uint32_t NVIC_Priority_Group = 0; 15 | 16 | /********************************************************************* 17 | * @fn NVIC_PriorityGroupConfig 18 | * 19 | * @brief Configures the priority grouping - pre-emption priority and subpriority. 20 | * 21 | * @param NVIC_PriorityGroup - specifies the priority grouping bits length. 22 | * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority 23 | * 4 bits for subpriority 24 | * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority 25 | * 3 bits for subpriority 26 | * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority 27 | * 2 bits for subpriority 28 | * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority 29 | * 1 bits for subpriority 30 | * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority 31 | * 0 bits for subpriority 32 | * 33 | * @return none 34 | */ 35 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 36 | { 37 | NVIC_Priority_Group = NVIC_PriorityGroup; 38 | } 39 | 40 | /********************************************************************* 41 | * @fn NVIC_Init 42 | * 43 | * @brief Initializes the NVIC peripheral according to the specified parameters in 44 | * the NVIC_InitStruct. 45 | * 46 | * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the 47 | * configuration information for the specified NVIC peripheral. 48 | * 49 | * @return none 50 | */ 51 | void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) 52 | { 53 | uint8_t tmppre = 0; 54 | 55 | if(NVIC_Priority_Group == NVIC_PriorityGroup_0) 56 | { 57 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); 58 | } 59 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) 60 | { 61 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) 62 | { 63 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); 64 | } 65 | else 66 | { 67 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); 68 | } 69 | } 70 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) 71 | { 72 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) 73 | { 74 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); 75 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); 76 | } 77 | else 78 | { 79 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); 80 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); 81 | } 82 | } 83 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) 84 | { 85 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) 86 | { 87 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); 88 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); 89 | } 90 | else 91 | { 92 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); 93 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); 94 | } 95 | } 96 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) 97 | { 98 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); 99 | } 100 | 101 | if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 102 | { 103 | NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); 104 | } 105 | else 106 | { 107 | NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); 108 | } 109 | } 110 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/src/ch32v00x_opa.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_opa.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the OPA firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | 15 | /********************************************************************* 16 | * @fn OPA_DeInit 17 | * 18 | * @brief Deinitializes the OPA peripheral registers to their default 19 | * reset values. 20 | * 21 | * @return none 22 | */ 23 | void OPA_DeInit(void) 24 | { 25 | EXTEN->EXTEN_CTR &= ~(uint32_t)(7 << 16); 26 | } 27 | 28 | /********************************************************************* 29 | * @fn OPA_Init 30 | * 31 | * @brief Initializes the OPA peripheral according to the specified 32 | * parameters in the OPA_InitStruct. 33 | * 34 | * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure 35 | * 36 | * @return none 37 | */ 38 | void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) 39 | { 40 | uint32_t tmp = 0; 41 | tmp = EXTEN->EXTEN_CTR; 42 | tmp &= ~(uint32_t)(3<<17); 43 | tmp |= (OPA_InitStruct->PSEL << 18) | (OPA_InitStruct->NSEL << 17); 44 | EXTEN->EXTEN_CTR = tmp; 45 | } 46 | 47 | /********************************************************************* 48 | * @fn OPA_StructInit 49 | * 50 | * @brief Fills each OPA_StructInit member with its reset value. 51 | * 52 | * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure 53 | * 54 | * @return none 55 | */ 56 | void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) 57 | { 58 | OPA_InitStruct->PSEL = CHP0; 59 | OPA_InitStruct->NSEL = CHN0; 60 | } 61 | 62 | /********************************************************************* 63 | * @fn OPA_Cmd 64 | * 65 | * @brief Enables or disables the specified OPA peripheral. 66 | * 67 | * @param OPA_NUM - Select OPA 68 | * NewState - ENABLE or DISABLE. 69 | * 70 | * @return none 71 | */ 72 | void OPA_Cmd(FunctionalState NewState) 73 | { 74 | if(NewState == ENABLE) 75 | { 76 | EXTEN->EXTEN_CTR |= (uint32_t)(1 << 16); 77 | } 78 | else 79 | { 80 | EXTEN->EXTEN_CTR &= ~(uint32_t)(1 << 16); 81 | } 82 | } 83 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/src/ch32v00x_pwr.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_pwr.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the PWR firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | #include 14 | 15 | /* PWR registers bit mask */ 16 | /* CTLR register bit mask */ 17 | #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) 18 | #define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) 19 | #define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) 20 | #define AWUWR_MASK ((uint32_t)0xFFFFFFC0) 21 | 22 | /********************************************************************* 23 | * @fn PWR_DeInit 24 | * 25 | * @brief Deinitializes the PWR peripheral registers to their default 26 | * reset values. 27 | * 28 | * @return none 29 | */ 30 | void PWR_DeInit(void) 31 | { 32 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 33 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 34 | } 35 | 36 | /********************************************************************* 37 | * @fn PWR_PVDCmd 38 | * 39 | * @brief Enables or disables the Power Voltage Detector(PVD). 40 | * 41 | * @param NewState - new state of the PVD(ENABLE or DISABLE). 42 | * 43 | * @return none 44 | */ 45 | void PWR_PVDCmd(FunctionalState NewState) 46 | { 47 | if(NewState) 48 | { 49 | PWR->CTLR |= (1 << 4); 50 | } 51 | else 52 | { 53 | PWR->CTLR &= ~(1 << 4); 54 | } 55 | } 56 | 57 | /********************************************************************* 58 | * @fn PWR_PVDLevelConfig 59 | * 60 | * @brief Configures the voltage threshold detected by the Power Voltage 61 | * Detector(PVD). 62 | * 63 | * @param PWR_PVDLevel - specifies the PVD detection level 64 | * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V 65 | * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V 66 | * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V 67 | * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V 68 | * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V 69 | * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V 70 | * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V 71 | * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V 72 | * 73 | * @return none 74 | */ 75 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 76 | { 77 | uint32_t tmpreg = 0; 78 | tmpreg = PWR->CTLR; 79 | tmpreg &= CTLR_PLS_MASK; 80 | tmpreg |= PWR_PVDLevel; 81 | PWR->CTLR = tmpreg; 82 | } 83 | 84 | /********************************************************************* 85 | * @fn PWR_AutoWakeUpCmd 86 | * 87 | * @brief Enables or disables the Auto WakeUp functionality. 88 | * 89 | * @param NewState - new state of the Auto WakeUp functionality 90 | * (ENABLE or DISABLE). 91 | * 92 | * @return none 93 | */ 94 | void PWR_AutoWakeUpCmd(FunctionalState NewState) 95 | { 96 | if(NewState) 97 | { 98 | PWR->AWUCSR |= (1 << 1); 99 | } 100 | else 101 | { 102 | PWR->AWUCSR &= ~(1 << 1); 103 | } 104 | } 105 | 106 | /********************************************************************* 107 | * @fn PWR_AWU_SetPrescaler 108 | * 109 | * @brief Sets the Auto Wake up Prescaler 110 | * 111 | * @param AWU_Prescaler - specifies the Auto Wake up Prescaler 112 | * PWR_AWU_Prescaler_1 - AWU counter clock = LSI/1 113 | * PWR_AWU_Prescaler_2 - AWU counter clock = LSI/2 114 | * PWR_AWU_Prescaler_4 - AWU counter clock = LSI/4 115 | * PWR_AWU_Prescaler_8 - AWU counter clock = LSI/8 116 | * PWR_AWU_Prescaler_16 - AWU counter clock = LSI/16 117 | * PWR_AWU_Prescaler_32 - AWU counter clock = LSI/32 118 | * PWR_AWU_Prescaler_64 - AWU counter clock = LSI/64 119 | * PWR_AWU_Prescaler_128 - AWU counter clock = LSI/128 120 | * PWR_AWU_Prescaler_256 - AWU counter clock = LSI/256 121 | * PWR_AWU_Prescaler_512 - AWU counter clock = LSI/512 122 | * PWR_AWU_Prescaler_1024 - AWU counter clock = LSI/1024 123 | * PWR_AWU_Prescaler_2048 - AWU counter clock = LSI/2048 124 | * PWR_AWU_Prescaler_4096 - AWU counter clock = LSI/4096 125 | * PWR_AWU_Prescaler_10240 - AWU counter clock = LSI/10240 126 | * PWR_AWU_Prescaler_61440 - AWU counter clock = LSI/61440 127 | * 128 | * @return none 129 | */ 130 | void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler) 131 | { 132 | uint32_t tmpreg = 0; 133 | tmpreg = PWR->AWUPSC & AWUPSC_MASK; 134 | tmpreg |= AWU_Prescaler; 135 | PWR->AWUPSC = tmpreg; 136 | } 137 | 138 | /********************************************************************* 139 | * @fn PWR_AWU_SetWindowValue 140 | * 141 | * @brief Sets the WWDG window value 142 | * 143 | * @param WindowValue - specifies the window value to be compared to the 144 | * downcounter,which must be lower than 0x3F 145 | * 146 | * @return none 147 | */ 148 | void PWR_AWU_SetWindowValue(uint8_t WindowValue) 149 | { 150 | __IO uint32_t tmpreg = 0; 151 | 152 | tmpreg = PWR->AWUWR & AWUWR_MASK; 153 | 154 | tmpreg |= WindowValue; 155 | 156 | PWR->AWUWR = tmpreg; 157 | } 158 | 159 | /********************************************************************* 160 | * @fn PWR_EnterSTANDBYMode 161 | * 162 | * @brief Enters STANDBY mode. 163 | * 164 | * @param PWR_STANDBYEntry - specifies if STANDBY mode in entered with WFI or WFE instruction. 165 | * PWR_STANDBYEntry_WFI - enter STANDBY mode with WFI instruction 166 | * PWR_STANDBYEntry_WFE - enter STANDBY mode with WFE instruction 167 | * 168 | * @return none 169 | */ 170 | void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry) 171 | { 172 | PWR->CTLR &= CTLR_DS_MASK; 173 | PWR->CTLR |= PWR_CTLR_PDDS; 174 | 175 | NVIC->SCTLR |= (1 << 2); 176 | 177 | if(PWR_STANDBYEntry == PWR_STANDBYEntry_WFI) 178 | { 179 | __WFI(); 180 | } 181 | else 182 | { 183 | __WFE(); 184 | } 185 | 186 | NVIC->SCTLR &= ~(1 << 2); 187 | } 188 | 189 | /********************************************************************* 190 | * @fn PWR_GetFlagStatus 191 | * 192 | * @brief Checks whether the specified PWR flag is set or not. 193 | * 194 | * @param PWR_FLAG - specifies the flag to check. 195 | * PWR_FLAG_PVDO - PVD Output 196 | * 197 | * @return The new state of PWR_FLAG (SET or RESET). 198 | */ 199 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 200 | { 201 | FlagStatus bitstatus = RESET; 202 | 203 | if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 204 | { 205 | bitstatus = SET; 206 | } 207 | else 208 | { 209 | bitstatus = RESET; 210 | } 211 | return bitstatus; 212 | } 213 | 214 | -------------------------------------------------------------------------------- /CH32V-EVT/Peripheral/src/ch32v00x_wwdg.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v00x_wwdg.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : This file provides all the WWDG firmware functions. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | #include 14 | 15 | /* CTLR register bit mask */ 16 | #define CTLR_WDGA_Set ((uint32_t)0x00000080) 17 | 18 | /* CFGR register bit mask */ 19 | #define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 20 | #define CFGR_W_Mask ((uint32_t)0xFFFFFF80) 21 | #define BIT_Mask ((uint8_t)0x7F) 22 | 23 | /********************************************************************* 24 | * @fn WWDG_DeInit 25 | * 26 | * @brief Deinitializes the WWDG peripheral registers to their default reset values 27 | * 28 | * @return none 29 | */ 30 | void WWDG_DeInit(void) 31 | { 32 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 33 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 34 | } 35 | 36 | /********************************************************************* 37 | * @fn WWDG_SetPrescaler 38 | * 39 | * @brief Sets the WWDG Prescaler 40 | * 41 | * @param WWDG_Prescaler - specifies the WWDG Prescaler 42 | * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 43 | * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 44 | * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 45 | * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 46 | * 47 | * @return none 48 | */ 49 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 50 | { 51 | uint32_t tmpreg = 0; 52 | tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; 53 | tmpreg |= WWDG_Prescaler; 54 | WWDG->CFGR = tmpreg; 55 | } 56 | 57 | /********************************************************************* 58 | * @fn WWDG_SetWindowValue 59 | * 60 | * @brief Sets the WWDG window value 61 | * 62 | * @param WindowValue - specifies the window value to be compared to the 63 | * downcounter,which must be lower than 0x80 64 | * 65 | * @return none 66 | */ 67 | void WWDG_SetWindowValue(uint8_t WindowValue) 68 | { 69 | __IO uint32_t tmpreg = 0; 70 | 71 | tmpreg = WWDG->CFGR & CFGR_W_Mask; 72 | 73 | tmpreg |= WindowValue & (uint32_t)BIT_Mask; 74 | 75 | WWDG->CFGR = tmpreg; 76 | } 77 | 78 | /********************************************************************* 79 | * @fn WWDG_EnableIT 80 | * 81 | * @brief Enables the WWDG Early Wakeup interrupt(EWI) 82 | * 83 | * @return none 84 | */ 85 | void WWDG_EnableIT(void) 86 | { 87 | WWDG->CFGR |= (1 << 9); 88 | } 89 | 90 | /********************************************************************* 91 | * @fn WWDG_SetCounter 92 | * 93 | * @brief Sets the WWDG counter value 94 | * 95 | * @param Counter - specifies the watchdog counter value,which must be a 96 | * number between 0x40 and 0x7F 97 | * 98 | * @return none 99 | */ 100 | void WWDG_SetCounter(uint8_t Counter) 101 | { 102 | WWDG->CTLR = Counter & BIT_Mask; 103 | } 104 | 105 | /********************************************************************* 106 | * @fn WWDG_Enable 107 | * 108 | * @brief Enables WWDG and load the counter value 109 | * 110 | * @param Counter - specifies the watchdog counter value,which must be a 111 | * number between 0x40 and 0x7F 112 | * @return none 113 | */ 114 | void WWDG_Enable(uint8_t Counter) 115 | { 116 | WWDG->CTLR = CTLR_WDGA_Set | Counter; 117 | } 118 | 119 | /********************************************************************* 120 | * @fn WWDG_GetFlagStatus 121 | * 122 | * @brief Checks whether the Early Wakeup interrupt flag is set or not 123 | * 124 | * @return The new state of the Early Wakeup interrupt flag (SET or RESET) 125 | */ 126 | FlagStatus WWDG_GetFlagStatus(void) 127 | { 128 | return (FlagStatus)(WWDG->STATR); 129 | } 130 | 131 | /********************************************************************* 132 | * @fn WWDG_ClearFlag 133 | * 134 | * @brief Clears Early Wakeup interrupt flag 135 | * 136 | * @return none 137 | */ 138 | void WWDG_ClearFlag(void) 139 | { 140 | WWDG->STATR = (uint32_t)RESET; 141 | } 142 | -------------------------------------------------------------------------------- /CH32V-EVT/Startup/startup_ch32v00x.S: -------------------------------------------------------------------------------- 1 | ;/********************************** (C) COPYRIGHT ******************************* 2 | ;* File Name : startup_ch32v00x.s 3 | ;* Author : WCH 4 | ;* Version : V1.0.0 5 | ;* Date : 2022/08/08 6 | ;* Description : vector table for eclipse toolchain. 7 | ;********************************************************************************* 8 | ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | ;* Attention: This software (modified or not) and binary are used for 10 | ;* microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | ;*******************************************************************************/ 12 | 13 | .section .init, "ax", @progbits 14 | .globl _start 15 | .align 2 16 | _start: 17 | .option norvc; 18 | j handle_reset 19 | .word 0 20 | .word NMI_Handler /* NMI Handler */ 21 | .word HardFault_Handler /* Hard Fault Handler */ 22 | .word 0 23 | .word 0 24 | .word 0 25 | .word 0 26 | .word 0 27 | .word 0 28 | .word 0 29 | .word 0 30 | .word SysTick_Handler /* SysTick Handler */ 31 | .word 0 32 | .word SW_Handler /* SW Handler */ 33 | .word 0 34 | /* External Interrupts */ 35 | .word WWDG_IRQHandler /* Window Watchdog */ 36 | .word PVD_IRQHandler /* PVD through EXTI Line detect */ 37 | .word FLASH_IRQHandler /* Flash */ 38 | .word RCC_IRQHandler /* RCC */ 39 | .word EXTI7_0_IRQHandler /* EXTI Line 7..0 */ 40 | .word AWU_IRQHandler /* AWU */ 41 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 42 | .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ 43 | .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ 44 | .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ 45 | .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ 46 | .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ 47 | .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ 48 | .word ADC1_IRQHandler /* ADC1 */ 49 | .word I2C1_EV_IRQHandler /* I2C1 Event */ 50 | .word I2C1_ER_IRQHandler /* I2C1 Error */ 51 | .word USART1_IRQHandler /* USART1 */ 52 | .word SPI1_IRQHandler /* SPI1 */ 53 | .word TIM1_BRK_IRQHandler /* TIM1 Break */ 54 | .word TIM1_UP_IRQHandler /* TIM1 Update */ 55 | .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ 56 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 57 | .word TIM2_IRQHandler /* TIM2 */ 58 | 59 | .option rvc; 60 | .section .text.vector_handler, "ax", @progbits 61 | .weak NMI_Handler 62 | .weak HardFault_Handler 63 | .weak SysTick_Handler 64 | .weak SW_Handler 65 | .weak WWDG_IRQHandler 66 | .weak PVD_IRQHandler 67 | .weak FLASH_IRQHandler 68 | .weak RCC_IRQHandler 69 | .weak EXTI7_0_IRQHandler 70 | .weak AWU_IRQHandler 71 | .weak DMA1_Channel1_IRQHandler 72 | .weak DMA1_Channel2_IRQHandler 73 | .weak DMA1_Channel3_IRQHandler 74 | .weak DMA1_Channel4_IRQHandler 75 | .weak DMA1_Channel5_IRQHandler 76 | .weak DMA1_Channel6_IRQHandler 77 | .weak DMA1_Channel7_IRQHandler 78 | .weak ADC1_IRQHandler 79 | .weak I2C1_EV_IRQHandler 80 | .weak I2C1_ER_IRQHandler 81 | .weak USART1_IRQHandler 82 | .weak SPI1_IRQHandler 83 | .weak TIM1_BRK_IRQHandler 84 | .weak TIM1_UP_IRQHandler 85 | .weak TIM1_TRG_COM_IRQHandler 86 | .weak TIM1_CC_IRQHandler 87 | .weak TIM2_IRQHandler 88 | 89 | NMI_Handler: 1: j 1b 90 | HardFault_Handler: 1: j 1b 91 | SysTick_Handler: 1: j 1b 92 | SW_Handler: 1: j 1b 93 | WWDG_IRQHandler: 1: j 1b 94 | PVD_IRQHandler: 1: j 1b 95 | FLASH_IRQHandler: 1: j 1b 96 | RCC_IRQHandler: 1: j 1b 97 | EXTI7_0_IRQHandler: 1: j 1b 98 | AWU_IRQHandler: 1: j 1b 99 | DMA1_Channel1_IRQHandler: 1: j 1b 100 | DMA1_Channel2_IRQHandler: 1: j 1b 101 | DMA1_Channel3_IRQHandler: 1: j 1b 102 | DMA1_Channel4_IRQHandler: 1: j 1b 103 | DMA1_Channel5_IRQHandler: 1: j 1b 104 | DMA1_Channel6_IRQHandler: 1: j 1b 105 | DMA1_Channel7_IRQHandler: 1: j 1b 106 | ADC1_IRQHandler: 1: j 1b 107 | I2C1_EV_IRQHandler: 1: j 1b 108 | I2C1_ER_IRQHandler: 1: j 1b 109 | USART1_IRQHandler: 1: j 1b 110 | SPI1_IRQHandler: 1: j 1b 111 | TIM1_BRK_IRQHandler: 1: j 1b 112 | TIM1_UP_IRQHandler: 1: j 1b 113 | TIM1_TRG_COM_IRQHandler: 1: j 1b 114 | TIM1_CC_IRQHandler: 1: j 1b 115 | TIM2_IRQHandler: 1: j 1b 116 | 117 | 118 | .section .text.handle_reset, "ax", @progbits 119 | .weak handle_reset 120 | .align 1 121 | handle_reset: 122 | .option push 123 | .option norelax 124 | la gp, __global_pointer$ 125 | .option pop 126 | 1: 127 | la sp, _eusrstack 128 | 2: 129 | /* Load data section from flash to RAM */ 130 | la a0, _data_lma 131 | la a1, _data_vma 132 | la a2, _edata 133 | bgeu a1, a2, 2f 134 | 1: 135 | lw t0, (a0) 136 | sw t0, (a1) 137 | addi a0, a0, 4 138 | addi a1, a1, 4 139 | bltu a1, a2, 1b 140 | 2: 141 | /* clear bss section */ 142 | la a0, _sbss 143 | la a1, _ebss 144 | bgeu a0, a1, 2f 145 | 1: 146 | sw zero, (a0) 147 | addi a0, a0, 4 148 | bltu a0, a1, 1b 149 | 2: 150 | li t0, 0x80 151 | csrw mstatus, t0 152 | 153 | li t0, 0x3 154 | csrw 0x804, t0 155 | 156 | la t0, _start 157 | ori t0, t0, 3 158 | csrw mtvec, t0 159 | 160 | jal SystemInit 161 | la t0, main 162 | csrw mepc, t0 163 | mret 164 | 165 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ###################################### 2 | # target 3 | ###################################### 4 | TARGET = ch32v003f4p6 5 | TARGET_DEFS = -DSYSCLK_FREQ_24MHZ_HSI=HSI_VALUE 6 | 7 | ###################################### 8 | # building variables 9 | ###################################### 10 | # debug build? 11 | DEBUG ?= 1 12 | DEBUG_BAUD ?= 921600 13 | # optimization for size 14 | OPT = -Os 15 | 16 | 17 | ####################################### 18 | # paths 19 | ####################################### 20 | # Build path 21 | BUILD_DIR = build 22 | 23 | ###################################### 24 | # source 25 | ###################################### 26 | # C sources 27 | C_SOURCES = \ 28 | CH32V-EVT/Peripheral/src/ch32v00x_gpio.c \ 29 | CH32V-EVT/Peripheral/src/ch32v00x_pwr.c \ 30 | CH32V-EVT/Peripheral/src/ch32v00x_opa.c \ 31 | CH32V-EVT/Peripheral/src/ch32v00x_dbgmcu.c \ 32 | CH32V-EVT/Peripheral/src/ch32v00x_adc.c \ 33 | CH32V-EVT/Peripheral/src/ch32v00x_exti.c \ 34 | CH32V-EVT/Peripheral/src/ch32v00x_dma.c \ 35 | CH32V-EVT/Peripheral/src/ch32v00x_tim.c \ 36 | CH32V-EVT/Peripheral/src/ch32v00x_rcc.c \ 37 | CH32V-EVT/Peripheral/src/ch32v00x_i2c.c \ 38 | CH32V-EVT/Peripheral/src/ch32v00x_wwdg.c \ 39 | CH32V-EVT/Peripheral/src/ch32v00x_misc.c \ 40 | CH32V-EVT/Peripheral/src/ch32v00x_iwdg.c \ 41 | CH32V-EVT/Peripheral/src/ch32v00x_usart.c \ 42 | CH32V-EVT/Peripheral/src/ch32v00x_spi.c \ 43 | CH32V-EVT/Peripheral/src/ch32v00x_flash.c \ 44 | CH32V-EVT/Core/core_riscv.c \ 45 | \ 46 | src/main.c \ 47 | src/mcu/ch32v00x-hal.c \ 48 | src/mcu/ch32v00x-sys.c \ 49 | src/mcu/ch32v00x-it.c \ 50 | src/mcu/ch32v00x-debug.c \ 51 | src/epd/uc8253.c \ 52 | src/epd/ch32v00x-drv.c \ 53 | src/nfc-tag/st25dv.c \ 54 | src/nfc-tag/ch32v00x-drv.c \ 55 | 56 | # ASM sources 57 | ASM_SOURCES = \ 58 | CH32V-EVT/Startup/startup_ch32v00x.S 59 | 60 | ####################################### 61 | # binaries 62 | ####################################### 63 | PREFIX ?= riscv-none-embed- 64 | 65 | CC = $(PREFIX)gcc 66 | AS = $(PREFIX)gcc -x assembler-with-cpp 67 | CP = $(PREFIX)objcopy 68 | SZ = $(PREFIX)size 69 | 70 | HEX = $(CP) -O ihex 71 | BIN = $(CP) -O binary -S 72 | 73 | ####################################### 74 | # CFLAGS 75 | ####################################### 76 | # cpu 77 | CPU = -march=rv32ec -mabi=ilp32e -msmall-data-limit=8 78 | 79 | # For gcc v12 and above 80 | # CPU = -march=rv32imac_zicsr -mabi=ilp32 -msmall-data-limit=8 81 | 82 | # mcu 83 | MCU = $(CPU) $(FPU) $(FLOAT-ABI) 84 | 85 | # AS includes 86 | AS_INCLUDES = 87 | 88 | # C includes 89 | C_INCLUDES = \ 90 | -ICH32V-EVT/Peripheral/inc \ 91 | -ICH32V-EVT/Debug \ 92 | -ICH32V-EVT/Core \ 93 | 94 | # compile gcc flags 95 | ASFLAGS = $(MCU) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 96 | 97 | CFLAGS = $(MCU) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 98 | 99 | ifeq ($(DEBUG), 1) 100 | CFLAGS += -g -gdwarf-2 101 | TARGET_DEFS += -DDEBUG=1 102 | TARGET_DEFS += -DDEBUG_BAUD=$(DEBUG_BAUD) 103 | endif 104 | 105 | 106 | # Generate dependency information 107 | CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" 108 | 109 | CFLAGS += $(TARGET_DEFS) 110 | 111 | ####################################### 112 | # LDFLAGS 113 | ####################################### 114 | # link script 115 | LDSCRIPT = CH32V-EVT/Ld/Link.ld 116 | 117 | # libraries 118 | LIBS = -lc -lm -lnosys 119 | LIBDIR = 120 | LDFLAGS = $(MCU) -mno-save-restore -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -T $(LDSCRIPT) -nostartfiles -Xlinker --gc-sections -Wl,-Map=$(BUILD_DIR)/$(TARGET).map --specs=nano.specs $(LIBS) 121 | 122 | # default action: build all 123 | all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin 124 | 125 | 126 | ####################################### 127 | # build the application 128 | ####################################### 129 | # list of objects 130 | OBJECTS = $(addprefix $(BUILD_DIR)/, $(C_SOURCES:.c=.o)) 131 | 132 | # list of ASM program objects 133 | OBJECTS += $(addprefix $(BUILD_DIR)/, $(ASM_SOURCES:.S=.o)) 134 | 135 | $(BUILD_DIR)/%.o: %.c Makefile 136 | @mkdir -pv $(dir $@) 137 | $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(@:.o=.lst) $< -o $@ 138 | 139 | $(BUILD_DIR)/%.o: %.S Makefile 140 | @mkdir -pv $(dir $@) 141 | $(AS) -c $(CFLAGS) $< -o $@ 142 | 143 | $(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile 144 | $(CC) $(OBJECTS) $(LDFLAGS) -o $@ 145 | $(SZ) $@ 146 | 147 | $(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 148 | $(HEX) $< $@ 149 | 150 | $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 151 | $(BIN) $< $@ 152 | 153 | $(BUILD_DIR): 154 | mkdir $@ 155 | 156 | ####################################### 157 | # Program 158 | ####################################### 159 | WCH_OPENOCD = ../MRS_Toolchain_Linux_x64_V1.92/OpenOCD/bin/openocd 160 | program: $(BUILD_DIR)/$(TARGET).elf 161 | sudo $(WCH_OPENOCD) -f /home/kein-fedora/PROJECTS/jobs/fossasia/epaper-badge/ch32v003-nfc/MRS_Toolchain_Linux_x64_V1.92/OpenOCD/bin/wch-riscv.cfg -c init -c halt -c "program $^ verify 0x00000000 verify reset exit" -c exit 162 | 163 | wlink: $(BUILD_DIR)/$(TARGET).bin 164 | sudo ../../wlink-linux-x64/wlink flash --address 0x08000000 $(BUILD_DIR)/$(TARGET).bin 165 | 166 | isp: $(BUILD_DIR)/$(TARGET).bin 167 | wchisp flash $(BUILD_DIR)/$(TARGET).bin 168 | 169 | ####################################### 170 | # clean up 171 | ####################################### 172 | clean: 173 | rm -f $(OBJECTS) 174 | rm -f $(OBJECTS:%.o=%.d) 175 | rm -f $(OBJECTS:%.o=%.lst) 176 | rm -f $(BUILD_DIR)/$(TARGET).* 177 | find $(BUILD_DIR) -type d -empty -delete 178 | 179 | ####################################### 180 | # dependencies 181 | ####################################### 182 | -include $(OBJECTS:%.o=%.d) 183 | 184 | # *** EOF *** 185 | -------------------------------------------------------------------------------- /Readme.md: -------------------------------------------------------------------------------- 1 | # Magic Epaper Firmware 2 | 3 | **Magic Epaper Firmware** is a customizable and efficient firmware designed to control FOSSASIA's epaper displays. This project is ideal for applications such as smart signage, dashboards, IoT devices, and more, providing a seamless interface for rendering content on e-ink screens. 4 | 5 | ## Features 6 | 7 | - **Optimized for the FOSSSASIA epaper Display**: Smooth rendering with minimal power consumption. 8 | - **Modular Codebase**: Easy to customize for different e-paper display sizes and types. 9 | - **Low-Power Operations**: Designed for battery-powered devices. 10 | - **Flexible Connectivity**: 11 | - Supports communication over SPI, I2C, or UART. 12 | - Compatible with the following microcontroller 13 | - **Rich Content Rendering**: 14 | - Text, images, and custom graphics. 15 | - Support for grayscale and partial refresh (depending on the display). 16 | - **Open Source**: Fully open-source firmware under the Apache2 license. 17 | 18 | ## Supported Displays 19 | 20 | The firmware currently supports the following e-ink displays: 21 | - FOSSASIA e-paper display. 22 | - Generic SPI-based e-ink displays. 23 | 24 | For other displays, you can add support by modifying the display driver module. 25 | 26 | ## Usages 27 | 28 | This firmware was designed as a bridge between the NFC reader and the epaper 29 | display. All commands from the epaper display are exposed to the NFC reader via 30 | NFC-V's (iso15693) `Write Message` command (see table below from ST25DV 31 | datasheet). 32 | 33 | ![iso15693 Write Message](assets/iso15693-write-message.png) 34 | 35 | Every message sent from the reader is encapsulated. Its length might vary but is 36 | always less than 256 bytes. 37 | 38 | The first byte is the command byte for the firmware. It instructs the firmware 39 | on how the chip should act. Available commands are: 40 | 41 | - Forwarding EPD command: `0x00` 42 | - Forwarding EPD Data: `0x01` 43 | 44 | Forwarding EPD command: this command pulls down the C/D pin of the epaper 45 | display, and forwards the next byte. This next byte is the command of the 46 | display driver chip. If more bytes follow after this next byte, these following 47 | bytes will be forwarded as parameters for the corresponding command of the 48 | display driver chip, and the C/D pin will be pulled up. Please refer to the 49 | driver chip's datasheet/manual (e.g., [UC8253's 50 | datasheet](https://www.good-display.com/companyfile/794.html)) of the display 51 | for the details of EPD's Command and its param. 52 | 53 | Forwarding EPD Data: This command pulls up the C/D pin of the epaper display, 54 | and forwards all the remaining bytes to the epaper display over SPI. It is 55 | useful when sending a big fat message block (larger than the iso15693's message 56 | length). The big fat message should be split into chunks and then sent by this 57 | Forwarding EPD Data command. 58 | 59 | Before starting to transfer, the reader must turn on energy harvesting for the 60 | tag using the `Write Dynamic Configuration` command (cmd code AEh) @02h. 61 | 62 | The reader should check if the MCU has read the previous chunk before writing 63 | another chunk by checking if the `RF_PUT_MSG` bit has been cleared using the 64 | `Read Dynamic Configuration` command (cmd code ADh) @0Dh. 65 | 66 | For the details of other ISO15693 commands that are supported and extended by 67 | ST25DV, please refer to [ST25DV's 68 | datasheet](https://www.st.com/resource/en/datasheet/st25dv04kc.pdf). 69 | 70 | ## Development 71 | 72 | ### Tools 73 | 74 | - [GNU make](https://www.gnu.org/software/make/) 75 | - [MounRiver Toolchain](http://file-oss.mounriver.com/tools/MRS_Toolchain_Linux_x64_V1.91.tar.xz) 76 | - [wlink](https://github.com/ch32-rs/wlink) 77 | - WCH-linkE 78 | 79 | ### Building 80 | 81 | Set the toolchain location, e.g.: 82 | 83 | ```sh 84 | export PREFIX=../MRS_Toolchain_Linux_x64_V1.91/RISC-V_Embedded_GCC/bin/riscv-none-embed- 85 | ``` 86 | 87 | Simply run `make` to build the firmware. 88 | 89 | ### Flashing 90 | 91 | After connecting WCH-linkE to the MCU, run `make wlink` to flash the firmware. 92 | 93 | ## License 94 | 95 | This project is licensed under the Apache2 License. See the [LICENSE](LICENSE.md) file for details. 96 | -------------------------------------------------------------------------------- /assets/iso15693-write-message.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fossasia/magic-epaper-firmware/ac89fa54bd19ffb6b9eebc840a0ffdf8544d05e9/assets/iso15693-write-message.png -------------------------------------------------------------------------------- /src/epd/README.md: -------------------------------------------------------------------------------- 1 | `drv.h` contain glue code in case reused on another platform or 2 | hardware changes. 3 | 4 | `*-drv.c` contain platform-dependent implementation of functions specified in 5 | `drv.h`. To port to another platform, just modify these files. 6 | 7 | `uc8253.h` and `uc8253.c` contain minimal code to init the display. Real usages 8 | depend on commands in the display driver's datasheet/manual. -------------------------------------------------------------------------------- /src/epd/ch32v00x-drv.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #include "uc8253.h" 6 | #include "drv.h" 7 | 8 | #define EPD_BUSY_PIN GPIO_Pin_4 // pd4 9 | #define EPD_RST_PIN GPIO_Pin_3 // pd3 10 | #define EPD_DC_PIN GPIO_Pin_2 // pd2 11 | 12 | #define EPD_CS_PIN GPIO_Pin_4 // pc4 13 | #define EPD_CLK_PIN GPIO_Pin_5 // pc5 14 | #define EPD_MOSI_PIN GPIO_Pin_6 // pc6 15 | 16 | void uc8253_switch2cmd() 17 | { 18 | GPIO_WriteBit(GPIOD, EPD_DC_PIN, 0); 19 | } 20 | 21 | void uc8253_switch2data() 22 | { 23 | GPIO_WriteBit(GPIOD, EPD_DC_PIN, 1); 24 | } 25 | 26 | void uc8253_select() 27 | { 28 | GPIO_WriteBit(GPIOC, EPD_CS_PIN, 0); 29 | } 30 | 31 | void uc8253_deselect() 32 | { 33 | GPIO_WriteBit(GPIOC, EPD_CS_PIN, 1); 34 | } 35 | 36 | void uc8253_pull_reset() 37 | { 38 | GPIO_WriteBit(GPIOD, EPD_RST_PIN, 0); 39 | } 40 | 41 | void uc8253_release_reset() 42 | { 43 | GPIO_WriteBit(GPIOD, EPD_RST_PIN, 1); 44 | } 45 | 46 | int uc8253_is_busy() 47 | { 48 | //LOW: busy, HIGH: idle 49 | return GPIO_ReadInputDataBit(GPIOD, EPD_BUSY_PIN) == 0; 50 | } 51 | 52 | void uc8253_init_hal() 53 | { 54 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE); 55 | 56 | GPIO_InitTypeDef iocfg = {0}; 57 | iocfg.GPIO_Speed = GPIO_Speed_10MHz; 58 | 59 | // reset, data/command as output 60 | iocfg.GPIO_Pin = EPD_RST_PIN | EPD_DC_PIN; 61 | iocfg.GPIO_Mode = GPIO_Mode_Out_PP; 62 | GPIO_Init(GPIOD, &iocfg); 63 | 64 | // BUSY as input 65 | iocfg.GPIO_Pin = EPD_BUSY_PIN; 66 | iocfg.GPIO_Mode = GPIO_Mode_IPU; 67 | GPIO_Init(GPIOD, &iocfg); 68 | 69 | // CS as output 70 | iocfg.GPIO_Pin = EPD_CS_PIN; 71 | iocfg.GPIO_Mode = GPIO_Mode_Out_PP; 72 | GPIO_Init(GPIOC, &iocfg); 73 | GPIO_WriteBit(GPIOC, EPD_CS_PIN, 1); // Unselect 74 | 75 | // SCK | MOSI 76 | iocfg.GPIO_Pin = EPD_CLK_PIN | EPD_MOSI_PIN; 77 | iocfg.GPIO_Mode = GPIO_Mode_AF_PP; 78 | // iocfg.GPIO_Mode = GPIO_Mode_Out_PP; 79 | GPIO_Init(GPIOC, &iocfg); 80 | } 81 | 82 | #ifdef USE_SPI_BITBANG 83 | /** 84 | * handy bit banging if the mcu doesn't have a spi peripheral 85 | */ 86 | void uc8253_write(uint8_t byte) 87 | { 88 | for (int i=0; i<8; i++) { 89 | GPIO_WriteBit(GPIOC, EPD_CLK_PIN, 0); 90 | GPIO_WriteBit(GPIOC, EPD_MOSI_PIN, ((byte << i) & 0x80) == 0x80); 91 | GPIO_WriteBit(GPIOC, EPD_CLK_PIN, 1); 92 | } 93 | GPIO_WriteBit(GPIOC, EPD_CLK_PIN, 0); 94 | } 95 | 96 | #else 97 | void uc8253_write(uint8_t byte) 98 | { 99 | SPI_I2S_SendData(SPI1, byte); 100 | while (! SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE)); 101 | } 102 | #endif 103 | 104 | // polling 105 | void uc8253_write_blk(uint8_t *buf, int len) 106 | { 107 | while (len--) { 108 | uc8253_write(*buf); 109 | buf++; 110 | } 111 | } -------------------------------------------------------------------------------- /src/epd/drv.h: -------------------------------------------------------------------------------- 1 | #ifndef __UC8253_DRV_H__ 2 | #define __UC8253_DRV_H__ 3 | 4 | #include 5 | 6 | void uc8253_switch2cmd(); 7 | void uc8253_switch2data(); 8 | 9 | void uc8253_select(); 10 | void uc8253_deselect(); 11 | 12 | void uc8253_pull_reset(); 13 | void uc8253_release_reset(); 14 | 15 | int uc8253_is_busy(); 16 | 17 | void uc8253_write(uint8_t byte); 18 | void uc8253_write_blk(uint8_t *buf, int len); 19 | 20 | void uc8253_init_hal(); 21 | 22 | #endif /* __UC8253_DRV_H__ */ 23 | -------------------------------------------------------------------------------- /src/epd/uc8253.c: -------------------------------------------------------------------------------- 1 | #include "uc8253.h" 2 | #include "drv.h" 3 | #include "../mcu/debug.h" 4 | 5 | #define PANEL_SETTING 0x00 6 | #define POWER_SETTING 0x01 7 | #define POWER_OFF 0x02 8 | #define POWER_OFF_SEQUENCE_SETTING 0x03 9 | #define POWER_ON 0x04 10 | #define POWER_ON_MEASURE 0x05 11 | #define BOOSTER_SOFT_START 0x06 12 | #define DEEP_SLEEP 0x07 13 | #define DATA_START_TRANSMISSION_1 0x10 // Black-white 14 | #define DATA_STOP 0x11 15 | #define DISPLAY_REFRESH 0x12 16 | #define DATA_START_TRANSMISSION_2 0x13 // RED 17 | #define VCOM_LUT 0x20 18 | #define W2W_LUT 0x21 19 | #define B2W_LUT 0x22 20 | #define W2B_LUT 0x23 21 | #define B2B_LUT 0x24 22 | #define BORDER_LUT 0x25 23 | #define PLL_CONTROL 0x30 24 | #define TEMPERATURE_SENSOR_CALIBRATION 0x40 25 | #define TEMPERATURE_SENSOR_SELECTION 0x41 26 | #define TEMPERATURE_SENSOR_WRITE 0x42 27 | #define TEMPERATURE_SENSOR_READ 0x43 28 | #define VCOM_AND_DATA_INTERVAL_SETTING 0x50 29 | #define LOW_POWER_DETECTION 0x51 30 | #define TCON_SETTING 0x60 31 | #define RESOLUTION_SETTING 0x61 32 | #define GSST 0x65 33 | #define GET_STATUS 0x71 34 | #define AUTO_MEASURE_VCOM 0x80 35 | #define READ_VCOM_VALUE 0x81 36 | #define VCM_DC_SETTING 0x82 37 | #define PARTIAL_WINDOW 0x90 38 | #define PARTIAL_IN 0x91 39 | #define PARTIAL_OUT 0x92 40 | #define PROGRAM_MODE 0xA0 41 | #define ACTIVE_PROGRAM 0xA1 42 | #define READ_OTP_DATA 0xA2 43 | #define POWER_SAVING 0xE3 44 | 45 | #define epd_WIDTH 240 46 | #define epd_HEIGHT 416 47 | 48 | static void reset(void) 49 | { 50 | for (int i=0; i<3; i++) { 51 | uc8253_pull_reset(); 52 | delay_ms(10); 53 | uc8253_release_reset(); 54 | delay_ms(10); 55 | } 56 | } 57 | 58 | void uc8253_send(uint8_t byte) 59 | { 60 | uc8253_switch2data(); 61 | 62 | uc8253_select(); 63 | uc8253_write(byte); 64 | uc8253_deselect(); 65 | } 66 | 67 | void uc8253_send_blk(uint8_t *bytes, uint16_t len) 68 | { 69 | uc8253_switch2data(); 70 | 71 | uc8253_select(); 72 | uc8253_write_blk(bytes, len); 73 | uc8253_deselect(); 74 | } 75 | 76 | void uc8253_cmd(uint8_t cmd) 77 | { 78 | uc8253_switch2cmd(); 79 | 80 | uc8253_select(); 81 | uc8253_write(cmd); 82 | uc8253_deselect(); 83 | } 84 | 85 | void uc8253_cmd_params(uint8_t *cmd_and_params, uint16_t len) 86 | { 87 | uint8_t cmd = cmd_and_params[0]; 88 | uc8253_cmd(cmd); 89 | uc8253_send_blk(cmd_and_params + 1, len - 1); 90 | } 91 | 92 | // wating for BUSY pin to release 93 | static void wait(void) 94 | { 95 | if (uc8253_is_busy()) 96 | PRINT("epd> wating.. "); 97 | else return; 98 | 99 | // uc8253_cmd(GET_STATUS); 100 | while(uc8253_is_busy()) { 101 | // uc8253_cmd(GET_STATUS); 102 | delay_ms(100); 103 | } 104 | PRINT("released.\n"); 105 | } 106 | 107 | /** 108 | * @brief Set cursor to x, y 109 | * 110 | * @param x8 Horizontal position, unit of 8 pixels 111 | * @param y Vertical position 112 | */ 113 | void uc8253_gotoxy(uint16_t x8, uint16_t y) 114 | { 115 | if (x8 > epd_WIDTH && y > epd_HEIGHT) return; 116 | 117 | uc8253_cmd(GSST); 118 | uc8253_send(x8 << 3); 119 | uc8253_send((y >> 8) & 0x01); 120 | uc8253_send(y & 0xFF); 121 | } 122 | 123 | /** 124 | * @brief Set cursor to x, y 125 | * 126 | * @param w8 width, unit of 8 pixels 127 | * @param y height 128 | */ 129 | void uc8253_set_resolution(uint16_t w, uint16_t h) 130 | { 131 | if (w > epd_WIDTH && h > epd_HEIGHT) return; 132 | 133 | uc8253_cmd(RESOLUTION_SETTING); 134 | uc8253_send(w << 3); 135 | uc8253_send((h >> 8) & 0x03); 136 | uc8253_send(h & 0xFF); 137 | } 138 | 139 | void uc8253_clear_mem(void) 140 | { 141 | uint16_t w, h, i, j; 142 | w = (epd_WIDTH % 8 == 0)? (epd_WIDTH / 8 ): (epd_WIDTH / 8 + 1); 143 | h = epd_HEIGHT; 144 | 145 | uc8253_cmd(DATA_START_TRANSMISSION_1); 146 | for (j = 0; j < h; j++) { 147 | for (i = 0; i < w; i++) { 148 | uc8253_send(0xFF); 149 | } 150 | } 151 | 152 | uc8253_cmd(DATA_START_TRANSMISSION_2); 153 | for (j = 0; j < h; j++) { 154 | for (i = 0; i < w; i++) { 155 | uc8253_send(0xFF); 156 | } 157 | } 158 | 159 | uc8253_gotoxy(0, 0); 160 | } 161 | 162 | void uc8253_refresh_poll() 163 | { 164 | uc8253_cmd(DISPLAY_REFRESH); 165 | wait(); 166 | } 167 | 168 | void uc8253_init() { 169 | uc8253_init_hal(); 170 | 171 | reset(); 172 | 173 | // uc8253_cmd(BOOSTER_SOFT_START); // boost soft start 174 | // uc8253_send(0xc7); // smoothest 175 | // uc8253_send(0xc7); // smoothest 176 | // uc8253_send(0xc7); // smoothest 177 | 178 | uc8253_cmd(POWER_ON); 179 | wait(); 180 | 181 | uc8253_cmd(PANEL_SETTING); 182 | uc8253_send(0b11001111); // 480x240 183 | uc8253_send(0x8D); // default 184 | 185 | uc8253_cmd(VCOM_AND_DATA_INTERVAL_SETTING); 186 | uc8253_send(0b11111111); 187 | uc8253_send(0x0f); 188 | } -------------------------------------------------------------------------------- /src/epd/uc8253.h: -------------------------------------------------------------------------------- 1 | #ifndef __uc8253_H__ 2 | #define __uc8253_H__ 3 | 4 | #include 5 | 6 | void uc8253_send(uint8_t byte); 7 | void uc8253_send_blk(uint8_t *bytes, uint16_t len); 8 | 9 | void uc8253_cmd(uint8_t reg); 10 | void uc8253_cmd_params(uint8_t *cmd_and_params, uint16_t len); 11 | 12 | /** Below are built-in functions for manipulating epd in firmware, built on 13 | * top of functions above 14 | */ 15 | 16 | void uc8253_gotoxy(uint16_t x, uint16_t y); 17 | void uc8253_set_resolution(uint16_t w, uint16_t h); 18 | void uc8253_clear_mem(void); 19 | void uc8253_refresh_poll(); 20 | 21 | void uc8253_init(); 22 | 23 | #endif /* __uc8253_H__ */ 24 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "mcu/hal.h" 4 | #include "mcu/debug.h" 5 | 6 | #include "epd/uc8253.h" 7 | #include "nfc-tag/st25dv.h" 8 | 9 | #define CMD_LUT_LEN 2 10 | 11 | // Can't use malloc due to not having enough flat mem. Doing this will give us 12 | // flat mem without wasting time to init: 13 | __attribute__ ((section (".noinit"))) uint8_t msg[256]; 14 | 15 | const void (*cmd_lut[CMD_LUT_LEN])(uint8_t *ptr, uint16_t len) = { 16 | uc8253_cmd_params, uc8253_send_blk 17 | }; 18 | 19 | static void dump_mem(uint8_t *buf, int len) 20 | { 21 | for (int i=0; i= CMD_LUT_LEN) { 36 | PRINT("command is not valid!\n"); 37 | return; 38 | } 39 | 40 | if (cmd_lut[cmd]) { 41 | (*cmd_lut[cmd])(msg + 1, ntag_msg_len - 1); 42 | 43 | PRINT("[cmd %02x] ", cmd); 44 | dump_mem(msg + 1, ntag_msg_len - 1); 45 | } else { 46 | PRINT("cmd_lut is missing!\n"); 47 | } 48 | ntag_has_new_msg = 0; 49 | } 50 | 51 | int main(void) 52 | { 53 | hal_init(); 54 | delay_init(); 55 | debug_init(); 56 | 57 | st25_enable_FTM(); 58 | st25dv_dump_allregs(); 59 | 60 | uc8253_init(); 61 | uc8253_clear_mem(); 62 | // uc8253_refresh_poll(); 63 | PRINT("init done\n"); 64 | 65 | while (1) { 66 | exe_cmd(); 67 | } 68 | } -------------------------------------------------------------------------------- /src/mcu/README.md: -------------------------------------------------------------------------------- 1 | This directory contains platform specific code to init system and peripherals. 2 | To port to another platform, users must provide glue code specified in `debug.h` 3 | and `hal.h` -------------------------------------------------------------------------------- /src/mcu/ch32v00x-debug.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | #include "ch32v00x-sys.h" 8 | #include "debug.h" 9 | 10 | static uint8_t p_us = 0; 11 | static uint16_t p_ms = 0; 12 | 13 | void delay_init(void) 14 | { 15 | p_us = SystemCoreClock / 8000000; 16 | p_ms = (uint16_t)p_us * 1000; 17 | } 18 | 19 | void delay_us(uint32_t n) 20 | { 21 | uint32_t i; 22 | 23 | SysTick->SR &= ~(1 << 0); 24 | i = (uint32_t)n * p_us; 25 | 26 | SysTick->CMP = i; 27 | SysTick->CNT = 0; 28 | SysTick->CTLR |=(1 << 0); 29 | 30 | while((SysTick->SR & (1 << 0)) != (1 << 0)); 31 | SysTick->CTLR &= ~(1 << 0); 32 | } 33 | 34 | void delay_ms(uint32_t n) 35 | { 36 | uint32_t i; 37 | 38 | SysTick->SR &= ~(1 << 0); 39 | i = (uint32_t)n * p_ms; 40 | 41 | SysTick->CMP = i; 42 | SysTick->CNT = 0; 43 | SysTick->CTLR |=(1 << 0); 44 | 45 | while((SysTick->SR & (1 << 0)) != (1 << 0)); 46 | SysTick->CTLR &= ~(1 << 0); 47 | } 48 | 49 | void USART_printf_init(uint32_t baudrate) 50 | { 51 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE); 52 | 53 | GPIO_InitTypeDef iocfg = {0}; 54 | iocfg.GPIO_Pin = GPIO_Pin_5; 55 | iocfg.GPIO_Mode = GPIO_Mode_AF_PP; 56 | iocfg.GPIO_Speed = GPIO_Speed_50MHz; 57 | GPIO_Init(GPIOD, &iocfg); 58 | 59 | USART_InitTypeDef uart_cfg; 60 | uart_cfg.USART_BaudRate = baudrate; 61 | uart_cfg.USART_WordLength = USART_WordLength_8b; 62 | uart_cfg.USART_StopBits = USART_StopBits_1; 63 | uart_cfg.USART_Parity = USART_Parity_No; 64 | uart_cfg.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 65 | uart_cfg.USART_Mode = USART_Mode_Tx; 66 | 67 | USART_Init(USART1, &uart_cfg); 68 | USART_Cmd(USART1, ENABLE); 69 | } 70 | 71 | __attribute__((used)) 72 | int _write(int fd, char *buf, int size) 73 | { 74 | int i; 75 | 76 | for(i = 0; i < size; i++){ 77 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); 78 | USART_SendData(USART1, *buf++); 79 | } 80 | 81 | return size; 82 | } 83 | 84 | void *_sbrk(ptrdiff_t incr) 85 | { 86 | extern char _end[]; 87 | extern char _heap_end[]; 88 | static char *curbrk = _end; 89 | 90 | if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) 91 | return NULL - 1; 92 | 93 | curbrk += incr; 94 | return curbrk - incr; 95 | } 96 | 97 | void debug_init() 98 | { 99 | USART_printf_init(DEBUG_BAUD); 100 | PRINT("SystemClk: %d\n", SystemCoreClock); 101 | } 102 | -------------------------------------------------------------------------------- /src/mcu/ch32v00x-hal.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | static void i2c_init() 9 | { 10 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE); 11 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); 12 | 13 | GPIO_InitTypeDef pins_init={0}; 14 | pins_init.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2; 15 | pins_init.GPIO_Mode = GPIO_Mode_AF_OD; 16 | pins_init.GPIO_Speed = GPIO_Speed_2MHz; 17 | GPIO_Init(GPIOC, &pins_init); 18 | 19 | I2C_InitTypeDef i2ccfg={0}; 20 | i2ccfg.I2C_ClockSpeed = 400000; 21 | i2ccfg.I2C_Mode = I2C_Mode_I2C; 22 | i2ccfg.I2C_DutyCycle = I2C_DutyCycle_16_9; 23 | i2ccfg.I2C_Ack = I2C_Ack_Enable; 24 | i2ccfg.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; 25 | I2C_Init(I2C1, &i2ccfg); 26 | 27 | I2C_Cmd(I2C1, ENABLE); 28 | 29 | I2C_AcknowledgeConfig(I2C1, ENABLE); 30 | } 31 | 32 | static void spi_init() 33 | { 34 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); 35 | SPI_InitTypeDef spi={0}; 36 | spi.SPI_Direction = SPI_Direction_1Line_Tx; 37 | spi.SPI_Mode = SPI_Mode_Master; 38 | 39 | spi.SPI_DataSize = SPI_DataSize_8b; 40 | spi.SPI_CPOL = SPI_CPOL_Low; 41 | spi.SPI_CPHA = SPI_CPHA_1Edge; 42 | spi.SPI_NSS = SPI_NSS_Soft; 43 | spi.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; 44 | spi.SPI_FirstBit = SPI_FirstBit_MSB; 45 | SPI_Init(SPI1, &spi); 46 | 47 | SPI_Cmd(SPI1, ENABLE); 48 | } 49 | 50 | static void setup_GPO() 51 | { 52 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC, ENABLE); 53 | 54 | GPIO_InitTypeDef p = {0}; 55 | p.GPIO_Pin = GPIO_Pin_3; 56 | p.GPIO_Speed = GPIO_Speed_2MHz; 57 | p.GPIO_Mode = GPIO_Mode_IPU; 58 | GPIO_Init(GPIOC, &p); 59 | 60 | GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, 3); 61 | EXTI_InitTypeDef ei = {0}; 62 | ei.EXTI_Line = EXTI_Line3; 63 | ei.EXTI_Mode = EXTI_Mode_Interrupt; 64 | ei.EXTI_Trigger = EXTI_Trigger_Falling; 65 | ei.EXTI_LineCmd = ENABLE; 66 | EXTI_Init(&ei); 67 | 68 | NVIC_InitTypeDef nvic = {0}; 69 | nvic.NVIC_IRQChannel = EXTI7_0_IRQn; 70 | nvic.NVIC_IRQChannelPreemptionPriority = NVIC_PriorityGroup_3; 71 | nvic.NVIC_IRQChannelSubPriority = 4; 72 | nvic.NVIC_IRQChannelCmd = ENABLE; 73 | NVIC_Init(&nvic); 74 | } 75 | 76 | void hal_init() 77 | { 78 | NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); 79 | 80 | i2c_init(); 81 | 82 | spi_init(); 83 | 84 | setup_GPO(); 85 | } -------------------------------------------------------------------------------- /src/mcu/ch32v00x-it.c: -------------------------------------------------------------------------------- 1 | #include "debug.h" 2 | 3 | void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 4 | void NMI_Handler(void) 5 | { 6 | PRINT("NMI exception\n"); 7 | } 8 | 9 | void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 10 | void HardFault_Handler(void) 11 | { 12 | PRINT("hard fault\n"); 13 | while (1); 14 | } 15 | -------------------------------------------------------------------------------- /src/mcu/ch32v00x-sys.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : system_ch32v00x.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : CH32V00x Device Peripheral Access Layer System Source File. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #include 13 | 14 | /** 15 | * System clock must be set in Makefile using -D flag in CFLAGS, arcording to 16 | * the defines below. If none was set, it will raise an error. 17 | */ 18 | 19 | // #define SYSCLK_FREQ_8MHz_HSI 8000000 20 | // #define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE 21 | // #define SYSCLK_FREQ_48MHZ_HSI 48000000 22 | // #define SYSCLK_FREQ_8MHz_HSE 8000000 23 | // #define SYSCLK_FREQ_24MHz_HSE HSE_VALUE 24 | // #define SYSCLK_FREQ_48MHz_HSE 48000000 25 | 26 | /* Clock Definitions */ 27 | #ifdef SYSCLK_FREQ_8MHz_HSI 28 | uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; 29 | #elif defined SYSCLK_FREQ_24MHZ_HSI 30 | uint32_t SystemCoreClock = SYSCLK_FREQ_24MHZ_HSI; 31 | #elif defined SYSCLK_FREQ_48MHZ_HSI 32 | uint32_t SystemCoreClock = SYSCLK_FREQ_48MHZ_HSI; 33 | #elif defined SYSCLK_FREQ_8MHz_HSE 34 | uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSE; 35 | #elif defined SYSCLK_FREQ_24MHz_HSE 36 | uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSE; 37 | #elif defined SYSCLK_FREQ_48MHz_HSE 38 | uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; 39 | #else 40 | #error "System core clock was not set" 41 | #endif 42 | 43 | __I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; 44 | 45 | /* system_private_function_proto_types */ 46 | static void SetSysClock(void); 47 | 48 | #ifdef SYSCLK_FREQ_8MHz_HSI 49 | static void SetSysClockTo_8MHz_HSI(void); 50 | #elif defined SYSCLK_FREQ_24MHZ_HSI 51 | static void SetSysClockTo_24MHZ_HSI(void); 52 | #elif defined SYSCLK_FREQ_48MHZ_HSI 53 | static void SetSysClockTo_48MHZ_HSI(void); 54 | #elif defined SYSCLK_FREQ_8MHz_HSE 55 | static void SetSysClockTo_8MHz_HSE(void); 56 | #elif defined SYSCLK_FREQ_24MHz_HSE 57 | static void SetSysClockTo_24MHz_HSE(void); 58 | #elif defined SYSCLK_FREQ_48MHz_HSE 59 | static void SetSysClockTo_48MHz_HSE(void); 60 | #endif 61 | 62 | /********************************************************************* 63 | * @fn SystemInit 64 | * 65 | * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, 66 | * the PLL and update the SystemCoreClock variable. 67 | * 68 | * @return none 69 | */ 70 | void SystemInit(void) 71 | { 72 | RCC->CTLR |= (uint32_t)0x00000001; 73 | RCC->CFGR0 &= (uint32_t)0xFCFF0000; 74 | RCC->CTLR &= (uint32_t)0xFEF6FFFF; 75 | RCC->CTLR &= (uint32_t)0xFFFBFFFF; 76 | RCC->CFGR0 &= (uint32_t)0xFFFEFFFF; 77 | RCC->INTR = 0x009F0000; 78 | 79 | SetSysClock(); 80 | } 81 | 82 | /********************************************************************* 83 | * @fn SystemCoreClockUpdate 84 | * 85 | * @brief Update SystemCoreClock variable according to Clock Register Values. 86 | * 87 | * @return none 88 | */ 89 | void SystemCoreClockUpdate(void) 90 | { 91 | uint32_t tmp = 0, pllsource = 0; 92 | 93 | tmp = RCC->CFGR0 & RCC_SWS; 94 | 95 | switch (tmp) 96 | { 97 | case 0x00: 98 | SystemCoreClock = HSI_VALUE; 99 | break; 100 | case 0x04: 101 | SystemCoreClock = HSE_VALUE; 102 | break; 103 | case 0x08: 104 | pllsource = RCC->CFGR0 & RCC_PLLSRC; 105 | if (pllsource == 0x00) { 106 | SystemCoreClock = HSI_VALUE * 2; 107 | } else { 108 | SystemCoreClock = HSE_VALUE * 2; 109 | } 110 | break; 111 | default: 112 | SystemCoreClock = HSI_VALUE; 113 | break; 114 | } 115 | 116 | tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; 117 | 118 | if (((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) { 119 | SystemCoreClock /= tmp; 120 | } else { 121 | SystemCoreClock >>= tmp; 122 | } 123 | } 124 | 125 | /********************************************************************* 126 | * @fn SetSysClock 127 | * 128 | * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. 129 | * 130 | * @return none 131 | */ 132 | static void SetSysClock(void) 133 | { 134 | #ifdef SYSCLK_FREQ_8MHz_HSI 135 | SetSysClockTo_8MHz_HSI(); 136 | #elif defined SYSCLK_FREQ_24MHZ_HSI 137 | SetSysClockTo_24MHZ_HSI(); 138 | #elif defined SYSCLK_FREQ_48MHZ_HSI 139 | SetSysClockTo_48MHZ_HSI(); 140 | #elif defined SYSCLK_FREQ_8MHz_HSE 141 | SetSysClockTo_8MHz_HSE(); 142 | #elif defined SYSCLK_FREQ_24MHz_HSE 143 | SetSysClockTo_24MHz_HSE(); 144 | #elif defined SYSCLK_FREQ_48MHz_HSE 145 | SetSysClockTo_48MHz_HSE(); 146 | #endif 147 | 148 | /* If none of the define above is enabled, the HSI is used as System clock. 149 | * source (default after reset) 150 | */ 151 | } 152 | 153 | #ifdef SYSCLK_FREQ_8MHz_HSI 154 | 155 | /********************************************************************* 156 | * @fn SetSysClockTo_8MHz_HSI 157 | * 158 | * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. 159 | * 160 | * @return none 161 | */ 162 | static void SetSysClockTo_8MHz_HSI(void) 163 | { 164 | /* Flash 0 wait state */ 165 | FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); 166 | FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; 167 | 168 | /* HCLK = SYSCLK = APB1 */ 169 | RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; 170 | } 171 | 172 | #elif defined SYSCLK_FREQ_24MHZ_HSI 173 | 174 | /********************************************************************* 175 | * @fn SetSysClockTo_24MHZ_HSI 176 | * 177 | * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. 178 | * 179 | * @return none 180 | */ 181 | static void SetSysClockTo_24MHZ_HSI(void) 182 | { 183 | /* Flash 0 wait state */ 184 | FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); 185 | FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; 186 | 187 | /* HCLK = SYSCLK = APB1 */ 188 | RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 189 | } 190 | 191 | #elif defined SYSCLK_FREQ_48MHZ_HSI 192 | 193 | /********************************************************************* 194 | * @fn SetSysClockTo_48MHZ_HSI 195 | * 196 | * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. 197 | * 198 | * @return none 199 | */ 200 | static void SetSysClockTo_48MHZ_HSI(void) 201 | { 202 | /* Flash 0 wait state */ 203 | FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); 204 | FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; 205 | 206 | /* HCLK = SYSCLK = APB1 */ 207 | RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 208 | 209 | /* PLL configuration: PLLCLK = HSI * 2 = 48 MHz */ 210 | RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC)); 211 | RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Mul2); 212 | 213 | /* Enable PLL */ 214 | RCC->CTLR |= RCC_PLLON; 215 | /* Wait till PLL is ready */ 216 | while ((RCC->CTLR & RCC_PLLRDY) == 0) { 217 | 218 | } 219 | /* Select PLL as system clock source */ 220 | RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); 221 | RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; 222 | /* Wait till PLL is used as system clock source */ 223 | while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { 224 | 225 | } 226 | } 227 | 228 | #elif defined SYSCLK_FREQ_8MHz_HSE 229 | 230 | /********************************************************************* 231 | * @fn SetSysClockTo_8MHz_HSE 232 | * 233 | * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. 234 | * 235 | * @return none 236 | */ 237 | static void SetSysClockTo_8MHz_HSE(void) 238 | { 239 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 240 | 241 | /* Close PA0-PA1 GPIO function */ 242 | RCC->APB2PCENR |= RCC_AFIOEN; 243 | AFIO->PCFR1 |= (1 << 15); 244 | 245 | RCC->CTLR |= ((uint32_t)RCC_HSEON); 246 | 247 | /* Wait till HSE is ready and if Time out is reached exit */ 248 | do { 249 | HSEStatus = RCC->CTLR & RCC_HSERDY; 250 | StartUpCounter++; 251 | } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 252 | 253 | RCC->APB2PCENR |= RCC_AFIOEN; 254 | AFIO->PCFR1 |= (1 << 15); 255 | 256 | if ((RCC->CTLR & RCC_HSERDY) != RESET) { 257 | HSEStatus = (uint32_t)0x01; 258 | } else { 259 | HSEStatus = (uint32_t)0x00; 260 | } 261 | 262 | if (HSEStatus == (uint32_t)0x01) { 263 | /* Flash 0 wait state */ 264 | FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); 265 | FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; 266 | 267 | /* HCLK = SYSCLK = APB1 */ 268 | RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; 269 | 270 | /* Select HSE as system clock source */ 271 | RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); 272 | RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; 273 | /* Wait till HSE is used as system clock source */ 274 | while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) { 275 | 276 | } 277 | } else { 278 | /* 279 | * If HSE fails to start-up, the application will have wrong clock 280 | * configuration. User can add here some code to deal with this error 281 | */ 282 | } 283 | } 284 | 285 | #elif defined SYSCLK_FREQ_24MHz_HSE 286 | 287 | /********************************************************************* 288 | * @fn SetSysClockTo_24MHz_HSE 289 | * 290 | * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. 291 | * 292 | * @return none 293 | */ 294 | static void SetSysClockTo_24MHz_HSE(void) 295 | { 296 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 297 | 298 | /* Close PA0-PA1 GPIO function */ 299 | RCC->APB2PCENR |= RCC_AFIOEN; 300 | AFIO->PCFR1 |= (1 << 15); 301 | 302 | RCC->CTLR |= ((uint32_t)RCC_HSEON); 303 | 304 | /* Wait till HSE is ready and if Time out is reached exit */ 305 | do { 306 | HSEStatus = RCC->CTLR & RCC_HSERDY; 307 | StartUpCounter++; 308 | } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 309 | 310 | RCC->APB2PCENR |= RCC_AFIOEN; 311 | AFIO->PCFR1 |= (1 << 15); 312 | 313 | if ((RCC->CTLR & RCC_HSERDY) != RESET) { 314 | HSEStatus = (uint32_t)0x01; 315 | } else { 316 | HSEStatus = (uint32_t)0x00; 317 | } 318 | 319 | if (HSEStatus == (uint32_t)0x01) { 320 | /* Flash 0 wait state */ 321 | FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); 322 | FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; 323 | 324 | /* HCLK = SYSCLK = APB1 */ 325 | RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 326 | 327 | /* Select HSE as system clock source */ 328 | RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); 329 | RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; 330 | /* Wait till HSE is used as system clock source */ 331 | while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) { 332 | 333 | } 334 | } else { 335 | /* 336 | * If HSE fails to start-up, the application will have wrong clock 337 | * configuration. User can add here some code to deal with this error 338 | */ 339 | } 340 | } 341 | 342 | #elif defined SYSCLK_FREQ_48MHz_HSE 343 | 344 | /********************************************************************* 345 | * @fn SetSysClockTo_48MHz_HSE 346 | * 347 | * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. 348 | * 349 | * @return none 350 | */ 351 | static void SetSysClockTo_48MHz_HSE(void) 352 | { 353 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 354 | 355 | /* Close PA0-PA1 GPIO function */ 356 | RCC->APB2PCENR |= RCC_AFIOEN; 357 | AFIO->PCFR1 |= (1 << 15); 358 | 359 | RCC->CTLR |= ((uint32_t)RCC_HSEON); 360 | 361 | /* Wait till HSE is ready and if Time out is reached exit */ 362 | do { 363 | HSEStatus = RCC->CTLR & RCC_HSERDY; 364 | StartUpCounter++; 365 | } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 366 | 367 | if ((RCC->CTLR & RCC_HSERDY) != RESET) { 368 | HSEStatus = (uint32_t)0x01; 369 | } else { 370 | HSEStatus = (uint32_t)0x00; 371 | } 372 | 373 | if (HSEStatus == (uint32_t)0x01) { 374 | /* Flash 0 wait state */ 375 | FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); 376 | FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; 377 | 378 | /* HCLK = SYSCLK = APB1 */ 379 | RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 380 | 381 | /* PLL configuration: PLLCLK = HSE * 2 = 48 MHz */ 382 | RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC)); 383 | RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE_Mul2); 384 | 385 | /* Enable PLL */ 386 | RCC->CTLR |= RCC_PLLON; 387 | /* Wait till PLL is ready */ 388 | while ((RCC->CTLR & RCC_PLLRDY) == 0) { 389 | 390 | } 391 | /* Select PLL as system clock source */ 392 | RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); 393 | RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; 394 | /* Wait till PLL is used as system clock source */ 395 | while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { 396 | 397 | } 398 | } else { 399 | /* 400 | * If HSE fails to start-up, the application will have wrong clock 401 | * configuration. User can add here some code to deal with this error 402 | */ 403 | } 404 | } 405 | #endif 406 | -------------------------------------------------------------------------------- /src/mcu/ch32v00x-sys.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : system_ch32v00x.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2022/08/08 6 | * Description : CH32V00x Device Peripheral Access Layer System Header File. 7 | ********************************************************************************* 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * Attention: This software (modified or not) and binary are used for 10 | * microcontroller manufactured by Nanjing Qinheng Microelectronics. 11 | *******************************************************************************/ 12 | #ifndef __SYSTEM_CH32V00x_H 13 | #define __SYSTEM_CH32V00x_H 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | #include 20 | 21 | extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ 22 | 23 | /* System_Exported_Functions */ 24 | extern void SystemInit(void); 25 | extern void SystemCoreClockUpdate(void); 26 | 27 | #ifdef __cplusplus 28 | } 29 | #endif 30 | 31 | #endif /*__CH32V00x_SYSTEM_H */ 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /src/mcu/debug.h: -------------------------------------------------------------------------------- 1 | #ifndef __DEBUG_H__ 2 | #define __DEBUG_H__ 3 | 4 | #include 5 | 6 | #ifdef DEBUG 7 | #define PRINT(X...) printf(X) 8 | #else 9 | #define PRINT(X...) 10 | #endif 11 | 12 | void delay_init(void); 13 | void delay_us(uint32_t n); 14 | void delay_ms(uint32_t n); 15 | void USART_printf_init(uint32_t baudrate); 16 | 17 | void debug_init(); 18 | 19 | #endif /* __DEBUG_H__ */ 20 | -------------------------------------------------------------------------------- /src/mcu/hal.h: -------------------------------------------------------------------------------- 1 | #ifndef __HAL_H__ 2 | #define __HAL_H__ 3 | 4 | void hal_init(); 5 | 6 | #endif /* __HAL_H__ */ 7 | -------------------------------------------------------------------------------- /src/nfc-tag/README.md: -------------------------------------------------------------------------------- 1 | `drv.h` contain glue code in case reused on another platform or 2 | hardware changes. 3 | 4 | `*-drv.c` contain platform-dependent implementation of functions specified in 5 | `drv.h`. To port to another platform, just modify these files. 6 | 7 | `st25dv.h` and `st25dv.c` contain several functions to dump st25dv's registers, 8 | open/close/check security session, check/read message from rf interface. -------------------------------------------------------------------------------- /src/nfc-tag/ch32v00x-drv.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include "../mcu/debug.h" 5 | #include "st25dv.h" 6 | #include "drv.h" 7 | 8 | volatile int ntag_has_new_msg, ntag_msg_len; 9 | 10 | void st25dv_reads(uint8_t sel, uint16_t addr, uint8_t *val, int size) 11 | { 12 | __disable_irq(); 13 | // START 1 14 | while(I2C_GetFlagStatus(I2C1, I2C_FLAG_BUSY) != RESET); 15 | I2C_GenerateSTART(I2C1, ENABLE); 16 | 17 | while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)); 18 | I2C_Send7bitAddress(I2C1, sel, I2C_Direction_Transmitter); 19 | 20 | while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)); 21 | 22 | I2C_SendData(I2C1, (u8)(addr >> 8)); 23 | while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); 24 | I2C_SendData(I2C1, (u8)(addr & 0xFF)); 25 | while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); 26 | 27 | // START 2 28 | I2C_GenerateSTART(I2C1, ENABLE); 29 | 30 | while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)); 31 | I2C_Send7bitAddress(I2C1, sel, I2C_Direction_Receiver); 32 | 33 | while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)); 34 | // while(I2C_GetFlagStatus(I2C1, I2C_FLAG_RXNE) != RESET) 35 | // I2C_AcknowledgeConfig(I2C1, DISABLE); 36 | 37 | for (int i=0; i> 8)); 58 | while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); 59 | I2C_SendData(I2C1, (u8)(addr & 0xFF)); 60 | while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)); 61 | 62 | for (int i=0; i 5 | 6 | void st25dv_reads(uint8_t sel, uint16_t addr, uint8_t *val, int size); 7 | void st25dv_writes(uint8_t sel, uint16_t addr, uint8_t *val, int size); 8 | 9 | #endif /* __ST25DV_DRV_H__ */ 10 | -------------------------------------------------------------------------------- /src/nfc-tag/st25dv.c: -------------------------------------------------------------------------------- 1 | #include "../mcu/debug.h" 2 | #include "st25dv.h" 3 | #include "drv.h" 4 | 5 | /* System configuration memory map */ 6 | /* E2=1, E1=1 */ 7 | #define GPO1 0x00 // Enable/disable GPO output and GPO ITs for RF events 8 | #define GPO2 0x01 // Enable/disable GPO ITs for I²C events and set Interruption pulse duration 9 | #define EH_MODE 0x02 // Energy harvesting default strategy after Power ON 10 | #define RF_MNGT 0x03 // RF interface state after power ON 11 | #define RFA1SS 0x04 // Area1 RF access protection 12 | #define ENDA1 0x05 // Area 1 ending point 13 | #define RFA2SS 0x06 // Area2 RF access protection 14 | #define ENDA2 0x07 // Area 2 ending point 15 | #define RFA3SS 0x08 // Area3 RF access protection 16 | #define ENDA3 0x09 // Area 3 ending point 17 | #define RFA4SS 0x0A // Area4 RF access protection 18 | #define I2CSS 0x0B // Area 1 to 4 I²C access protection 19 | #define LOCK_CCFILE 0x0C // Blocks 0 and 1 RF Write protection 20 | #define FTM 0x0D // Fast transfer mode authorization and watchdog setting. 21 | #define I2C_CFG 0x0E // I2C target address cfg and enable/disable RF switch off from I2C 22 | #define LOCK_CFG 0x0F // Protect RF Write to system cfg registers 23 | #define LOCK_DSFID 0x10 // DSFID lock status 24 | #define LOCK_AFI 0x11 // AFI lock status 25 | #define DSFID 0x12 // DSFID value 26 | #define AFI 0x13 // AFI value 27 | #define MEM_SIZEl 0x14 // Memory size value in blocks, 2 bytes 28 | #define MEM_SIZEh 0x15 // Memory size value in blocks, 2 bytes 29 | #define BLK_SIZE 0x16 // Block size value in bytes 30 | #define IC_REF 0x17 // IC reference value 31 | #define UID 0x18 // Unique identifier, 8 bytes 32 | #define IC_REV 0x20 // IC revision 33 | 34 | #define I2C_PWD 0x0900 // I2C security session password, 8 bytes 35 | 36 | /* Dynamic registers memory map */ 37 | /* E2 = 0, E1 = 1 */ 38 | #define GPO_CTRL_Dyn 0x2000 // GPO control 39 | #define EH_CTRL_Dyn 0x2002 // Energy Harvesting management and usage status 40 | #define RF_MNGT_Dyn 0x2003 // RF interface usage management 41 | #define I2C_SSO_Dyn 0x2004 // I2C security session status 42 | #define IT_STS_Dyn 0x2005 // Interruptions status 43 | #define MB_CTRL_Dyn 0x2006 // Fast transfer mode control and status 44 | #define MB_LEN_Dyn 0x2007 // Length of fast transfer mode message 45 | #define MB_Dyn 0x2008 // Fast transfer mode buffer (256-Bytes) 46 | 47 | /* Device Address */ 48 | #define SEL_CODE 0b10100010 49 | #define SEL_SYSTEM 0b00001100 | SEL_CODE 50 | #define SEL_USER 0b00000100 | SEL_CODE 51 | // #define R 0b00000000 52 | // #define W 0b00000001 53 | 54 | void st25dv_write(uint8_t sel, uint16_t addr, uint8_t val) 55 | { 56 | st25dv_writes(sel, addr, &val, 1); 57 | } 58 | 59 | uint8_t st25dv_read(uint8_t sel, uint16_t addr) 60 | { 61 | uint8_t val; 62 | st25dv_reads(sel, addr, &val, 1); 63 | return val; 64 | } 65 | 66 | void st25dv_dump_sysregs() 67 | { 68 | const int n = 0x21; 69 | uint8_t regs[n]; 70 | const char *sysreg_names[] = { 71 | " GPO1", 72 | " GPO2", 73 | " EH_MODE", 74 | " RF_MNGT", 75 | " RFA1SS", 76 | " ENDA1", 77 | " RFA2SS", 78 | " ENDA2", 79 | " RFA3SS", 80 | " ENDA3", 81 | " RFA4SS", 82 | " I2CSS", 83 | "LOCK_CCFILE", 84 | " FTM", 85 | " I2C_CFG", 86 | " LOCK_CFG", 87 | " LOCK_DSFID", 88 | " LOCK_AFI", 89 | " DSFID", 90 | " AFI", 91 | " MEM_SIZEl", 92 | " MEM_SIZEh", 93 | " BLK_SIZE", 94 | " IC_REF", 95 | " UID", // 8 bytes 96 | " IC_REV" 97 | }; 98 | st25dv_reads(SEL_SYSTEM, 0x00, regs, n); 99 | 100 | PRINT("System regs:\n"); 101 | for (int i=0; i 5 | 6 | extern volatile int ntag_has_new_msg, ntag_msg_len; 7 | 8 | void st25dv_dump_sysregs(); 9 | void st25dv_dump_usrregs(); 10 | void st25dv_dump_allregs(); 11 | 12 | void st25dv_open_session(); 13 | void st25dv_close_session(); 14 | int st25dv_is_session_opened(); 15 | 16 | void st25_enable_FTM(); 17 | uint8_t st25dv_has_rf_put_msg(); 18 | uint8_t st25dv_mb_len(); 19 | int st25dv_gather_msg(uint8_t *buf); 20 | 21 | #endif /* __ST25DV_H__ */ 22 | --------------------------------------------------------------------------------