├── .gitignore ├── AVC2013 ├── PWM_SRC ├── README.md ├── avc-mjpg-streamer │ ├── CHANGELOG │ ├── LICENSE │ ├── Makefile │ ├── README │ ├── fix_dependency.sh │ ├── launch_streamer.sh │ ├── mjpg_streamer.c │ ├── mjpg_streamer.h │ ├── plugins │ │ ├── input.h │ │ ├── input_file │ │ │ └── input_file.c │ │ ├── input_memory │ │ │ ├── Makefile │ │ │ ├── input_memory.c │ │ │ ├── jpeg_func.c │ │ │ └── jpeg_func.h │ │ ├── output.h │ │ └── output_http │ │ │ ├── Makefile │ │ │ ├── httpd.c │ │ │ ├── httpd.h │ │ │ └── output_http.c │ ├── start.sh │ ├── utils.c │ ├── utils.h │ └── www │ │ ├── LICENSE.txt │ │ ├── bodybg.gif │ │ ├── cambozola.jar │ │ ├── control.htm │ │ ├── example.jpg │ │ ├── favicon.ico │ │ ├── favicon.png │ │ ├── fix.css │ │ ├── functions.js │ │ ├── sidebarbg.gif │ │ └── style.css ├── avc_platform │ ├── avc_mark1.ucf │ ├── avc_platform.vhd │ ├── avc_platform.xise │ ├── clock_divider.vhd │ ├── dc_motor_model.vhd │ ├── ipcore_dir │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ └── clock_gen.xise │ ├── logipi_ra2.ucf │ ├── pid_controller.vhd │ ├── pid_controller_tb.vhd │ ├── pid_filter.vhd │ ├── pwm_gen.vhd │ ├── quad_encoder_block.vhd │ ├── servo_controller.vhd │ ├── servo_controller_tb.vhd │ ├── steering_control.vhd │ ├── watchdog.vhd │ └── watchdog_tb.vhd ├── avcinit.sh ├── color-classifier │ └── color_lut_interface.py ├── grab_from_cam │ ├── Makefile │ ├── grab_frame.c │ ├── jpeg_func.c │ └── jpeg_func.h ├── imu-python-wrapper │ ├── README │ ├── mpu9150-python.c │ ├── setup.py │ └── test_dmp.py └── platform-python-wrapper │ ├── avc_navigation.py │ ├── avc_platform.py │ ├── controllers.py │ ├── dla_1.py │ ├── dla_2.py │ ├── ether_client.py │ ├── gps_service.py │ ├── launch_avc.sh │ └── waypoint_provider.py ├── README.md ├── book-example-code ├── Readme.txt ├── pong-chu-logi-edu-examples-verilog │ ├── ch01 │ │ ├── list_ch01_01_eq1.v │ │ ├── list_ch01_02_eq1_implicit.v │ │ ├── list_ch01_03_eq2_sop.v │ │ ├── list_ch01_04_eq2.v │ │ ├── list_ch01_05_eq1_primitive.v │ │ ├── list_ch01_06_eq1_udp.v │ │ └── list_ch01_07_eq2_tb.v │ ├── ch02 │ │ ├── list_ch02_01_eq1.v │ │ ├── list_ch02_02_eq2.v │ │ ├── list_ch02_03_eq2_tb.v │ │ └── list_eq2_s3.ucf │ ├── ch03 │ │ ├── ch03_17_sm_add_test.zip │ │ ├── ch03_17_sm_add_test │ │ │ ├── ch03_17_sm_add_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch03_20_shifter_test.zip │ │ ├── ch03_20_shifter_test │ │ │ ├── ch03_20_shifter_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch03_22_fp_adder_test.zip │ │ ├── ch03_22_fp_adder_test │ │ │ ├── ch03_22_fp_adder_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch3_13_hex_to_sseg_test.zip │ │ ├── ch3_13_hex_to_sseg_test │ │ │ ├── ch3_14_hex_to_sseg_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch03_01_eq1_always.v │ │ ├── list_ch03_02_and_block_assign.v │ │ ├── list_ch03_03_and_cont_assign.v │ │ ├── list_ch03_04_prio_encoder_if.v │ │ ├── list_ch03_05_decoder_2_4_if.v │ │ ├── list_ch03_06_decoder_2_4_case.v │ │ ├── list_ch03_07_prio_encoder_case.v │ │ ├── list_ch03_08_prio_encoder_casez.v │ │ ├── list_ch03_09_adder_carry_hard_lit.v │ │ ├── list_ch03_10_adder_carry_local_par.v │ │ ├── list_ch03_11_adder_carry_para.v │ │ ├── list_ch03_12_adder_insta.v │ │ ├── list_ch03_13_adder_carry_95.v │ │ ├── list_ch03_14_hex_to_sseg.v │ │ ├── list_ch03_15_hex_to_sseg_test.v │ │ ├── list_ch03_16_sign_mag_addt.v │ │ ├── list_ch03_17_sm_add_test.v │ │ ├── list_ch03_18_barrel_shifter_case.v │ │ ├── list_ch03_19_barrel_shifter_stage.v │ │ ├── list_ch03_20_shifter_test.v │ │ ├── list_ch03_21_fp_adder.v │ │ ├── list_ch03_22_fp_adder_test.v │ │ └── list_ch04_13_disp_mux.v │ ├── ch04 │ │ ├── ch04_16_disp_mux_test.zip │ │ ├── ch04_16_disp_mux_test │ │ │ ├── ch04_16_disp_mux_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch04_16_hex_mux_test_junk │ │ │ ├── ch04_16_hex_mux_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch04_19_stop_watch_test.zip │ │ ├── ch04_19_stop_watch_test │ │ │ ├── list_ch04_19_stop_watch_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch04_21_fifo_test.zip │ │ ├── ch04_21_fifo_test │ │ │ ├── ch04_21_fifo_test.xise │ │ │ ├── led8_sseg.vhd │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch04_01_d_ff.v │ │ ├── list_ch04_02_d_ff_reset.v │ │ ├── list_ch04_03_d_ff_en_1seg.v │ │ ├── list_ch04_04_d_ff_en_2seg.v │ │ ├── list_ch04_05_reg_reset.v │ │ ├── list_ch04_06_reg_file.v │ │ ├── list_ch04_07_free_run_shift_reg.v │ │ ├── list_ch04_08_univ_shift_reg.v │ │ ├── list_ch04_09_free_run_bin_counter.v │ │ ├── list_ch04_10_univ_bin_counter.v │ │ ├── list_ch04_11_mod_m_counter.v │ │ ├── list_ch04_12_bin_counter_tb.v │ │ ├── list_ch04_13_disp_mux.v │ │ ├── list_ch04_14_disp_mux_test.v │ │ ├── list_ch04_15_disp_hex_mux.v │ │ ├── list_ch04_16_hex_mux_test.v │ │ ├── list_ch04_17_stop_watch_cascade.v │ │ ├── list_ch04_18_stop_watch_if.v │ │ ├── list_ch04_19_stop_watch_test.v │ │ ├── list_ch04_20_fifo.v │ │ ├── list_ch04_21_fifo_test.v │ │ └── list_ch06_02_debounce.v │ ├── ch05 │ │ ├── ch05_07_debounce_test.zip │ │ ├── ch05_07_debounce_test │ │ │ ├── ch05_07_debounce_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch05_01_fsm_eg_mult_seg.v │ │ ├── list_ch05_02_fsm_eg_2_seg.v │ │ ├── list_ch05_03_edge_detect_moore.v │ │ ├── list_ch05_04_edge_detect_mealy.v │ │ ├── list_ch05_05_edge_detect_gate.v │ │ ├── list_ch05_06_db_fsm.v │ │ └── list_ch05_07_debounce_test.v │ ├── ch06 │ │ ├── ch06_03_debounce_fsmd_test.zip │ │ ├── ch06_03_debounce_fsmd_test │ │ │ ├── ch06_03_debounce_fsmd_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch06_01_debounce_explicit.v │ │ ├── list_ch06_02_debounce.v │ │ ├── list_ch06_03_debounce_fsmd_test.v │ │ ├── list_ch06_04_fib.v │ │ ├── list_ch06_05_div.v │ │ ├── list_ch06_06_bin2bcd.v │ │ ├── list_ch06_07_period_counter.v │ │ └── list_ch06_08_low_freq_counter.v │ ├── ch07 │ │ ├── list_ch07_01_and_block.v │ │ ├── list_ch07_02_and_nonblock.v │ │ ├── list_ch07_03_eq1_block.v │ │ ├── list_ch07_04_eq1_non_block.v │ │ ├── list_ch07_05_ab_ff_2seg.v │ │ ├── list_ch07_06_ab_ff_all.v │ │ ├── list_ch07_07_ bin_counter_merge.v │ │ ├── list_ch07_08_ bin_counter_terse.v │ │ ├── list_ch07_09_univ_bin_counter_merged.v │ │ ├── list_ch07_10_fsm_eg_merged.v │ │ ├── list_ch07_11_div_combined.v │ │ ├── list_ch07_12_mod_m_counter_fc.v │ │ ├── list_ch07_14_eq2_file_tb.v │ │ ├── list_ch07_15_eq2_task.v │ │ ├── list_ch07_16_eq2_function.v │ │ ├── list_ch07_17_bin_gen.v │ │ ├── list_ch07_18_bin_monitor.v │ │ ├── list_ch07_19_bin_counter_tb3.v │ │ ├── list_ch07_20_exp1.v │ │ ├── list_ch07_20_exp1.v.bak │ │ └── vector.txt │ ├── ch08 │ │ ├── ch08_05_uart_test.zip │ │ ├── ch08_05_uart_test │ │ │ ├── ch08_05_uart_test.xise │ │ │ ├── led8_sseg.vhd │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch08_01_uart_rx.v │ │ ├── list_ch08_02_flag_buf.v │ │ ├── list_ch08_03_uart_tx.v │ │ ├── list_ch08_04_uart.v │ │ └── list_ch08_05_uart_test.v │ ├── ch09 │ │ ├── ch09_02_kb_monitor.zip │ │ ├── ch09_02_kb_monitor │ │ │ ├── ch09_02_kb_monitor.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch09_05_kb_test.zip │ │ ├── ch09_05_kb_test │ │ │ ├── ch09_05_kb_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch09_01_ps2_rx.v │ │ ├── list_ch09_02_kb_monitor.v │ │ ├── list_ch09_03_kb_code.v │ │ ├── list_ch09_04_key2ascii.v │ │ └── list_ch09_05_kb_test.v │ ├── ch10 │ │ ├── ch10_03_ps2_monitor.zip │ │ ├── ch10_03_ps2_monitor │ │ │ ├── ch10_03_ps2_monitor.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch10_05_mouse_led.zip │ │ ├── ch10_05_mouse_led │ │ │ ├── ch10_05_mouse_led.xise │ │ │ ├── led8_sseg.vhd │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch10_01_ps2_tx.v │ │ ├── list_ch10_02_ps2_rxtx.v │ │ ├── list_ch10_03_ps2_monitor.v │ │ ├── list_ch10_04_mouse.v │ │ └── list_ch10_05_mouse_led.v │ ├── ch11 │ │ ├── list_ch11_01_sram_ctrl.v │ │ ├── list_ch11_02_ram_ctrl_test.v │ │ ├── list_ch11_03_sram_test.v │ │ └── readme.txt │ ├── ch12 │ │ ├── list_ch12_01_xilinx_one_port_ram_async.v │ │ ├── list_ch12_02_xilinx_one_port_ram_sync.v │ │ ├── list_ch12_03_xilinx_dual_port_ram_async.v │ │ ├── list_ch12_04_xilinx_dual_port_ram_sync.v │ │ ├── list_ch12_05_rom_template.v │ │ ├── list_ch12_06_xilinx_rom_sync_template.v │ │ └── readme.txt │ ├── ch13 │ │ ├── ch13_02_vga_test.zip │ │ ├── ch13_02_vga_test │ │ │ ├── ch13_02_vga_test.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── ch13_06_pong_top_an.zip │ │ ├── ch13_06_pong_top_an │ │ │ ├── ch13_06_pong_top_an.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch13_01_vga_sync.v │ │ ├── list_ch13_02_vga_test.v │ │ ├── list_ch13_03_pong_graph_st.v │ │ ├── list_ch13_04_pong_top_st.v │ │ ├── list_ch13_04_pong_top_st.zip │ │ ├── list_ch13_04_pong_top_st │ │ │ ├── list_ch13_04_pong_top_st.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch13_05_ pong_graph_animate.v │ │ ├── list_ch13_06_pong_top_an.v │ │ ├── list_ch13_07_bitmap_gen.v │ │ └── list_ch13_08_dot_top.v │ ├── ch14 │ │ ├── ch14_03_font_test_top.zip │ │ ├── ch14_03_font_test_top │ │ │ ├── ch14_03_font_test_top.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ ├── list_ch14_01_font_rom.v │ │ ├── list_ch14_02_font_test_gen.v │ │ ├── list_ch14_03_font_test_top.v │ │ ├── list_ch14_04_text_screen_gen.v │ │ ├── list_ch14_05_text_screen_top.v │ │ ├── list_ch14_06_pong_text.v │ │ ├── list_ch14_07_pong_graph.v │ │ ├── list_ch14_08_m100_counter.v │ │ ├── list_ch14_09_timer.v │ │ ├── list_ch14_10_pong_top.v │ │ ├── list_ch14_10_pong_top.zip │ │ ├── list_ch14_10_pong_top │ │ │ ├── list_ch14_10_pong_top.xise │ │ │ └── logipi_r1_0_edu.ucf │ │ └── logipi_r1_0_edu.ucf │ ├── ch16 │ │ ├── SIO_ROM.V │ │ ├── list_ch16_02_sio_rom.psm │ │ └── list_ch16_03_pico_sio.v │ ├── ch17 │ │ ├── BTN_ROM.V │ │ ├── UART_ROM.V │ │ ├── list_17_1_btn_rom.psm │ │ ├── list_17_3_uart_rom.psm │ │ ├── list_ch17_02_pico_btn.v │ │ └── list_ch17_04_pico_uart.v │ ├── ch18 │ │ ├── INT_ROM.V │ │ ├── list_18_1_int_rom.psm │ │ └── list_ch18_02_pico_int.v │ ├── ch_app │ │ ├── list_ch_ap_01_bin_counter.v │ │ ├── list_ch_ap_02_counter_inst.v │ │ ├── list_ch_ap_03_prio_encoder_if.v │ │ ├── list_ch_ap_04_prio_encoder_case.v │ │ ├── list_ch_ap_05_compare_no_defult.v │ │ ├── list_ch_ap_06_compare_with_default.v │ │ ├── list_ch_ap_07_reg_template.v │ │ ├── list_ch_ap_08_reg_file.v │ │ ├── list_ch_ap_09_bin_counter.v │ │ ├── list_ch_ap_10_fsm_eg_2_seg.v │ │ ├── list_ch_ap_11_fib.v │ │ └── s3.ucf │ ├── logipi_r1_0_edu.ucf │ ├── original_vlog_src.zip │ ├── vfx_source │ │ └── led8_sseg.vhd │ └── visio │ │ └── ch05 │ │ ├── ch05_SE_dual_edge_mealy.png │ │ ├── ch05_SE_dual_edge_mealy.vsd │ │ ├── ch05_SE_dual_edge_moore.png │ │ ├── ch05_SE_dual_edge_moore.vsd │ │ ├── ch05_db_fsm.png │ │ ├── ch05_db_fsm.vsd │ │ ├── ch05_db_fsm_SE_1.png │ │ └── ch05_db_fsm_SE_1.vsd └── pong-chu-logi-edu-examples-vhdl │ ├── PongChu_fpga_VHDL_src_original.zip │ ├── ch01 │ ├── list_ch01_01_eq1.vhd │ ├── list_ch01_02_03_04_eq2.vhd │ └── list_ch01_05_tb.vhd │ ├── ch02 │ ├── list_ch02_01_eq1.vhd │ ├── list_ch02_02_eq2.vhd │ └── list_ch02_03_tb.vhd │ ├── ch03 │ ├── ch3_13_hex_to_sseg_test.zip │ ├── ch3_13_hex_to_sseg_test │ │ ├── ch3_13_hex_to_sseg_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch03_01_03_05_07_prio.vhd │ ├── list_ch03_02_04_06_08_decode.vhd │ ├── list_ch03_09_10_add.vhd │ ├── list_ch03_11_gen_add.vhd │ ├── list_ch03_12_hex2led.vhd │ ├── list_ch03_13_led_test.vhd │ ├── list_ch03_14_smadd.vhd │ ├── list_ch03_15_smadd_test.vhd │ ├── list_ch03_16_17_shift.vhd │ ├── list_ch03_18_shift_test.vhd │ ├── list_ch03_18_shift_test.zip │ ├── list_ch03_18_shift_test │ │ ├── list_ch03_18_shift_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch03_19_fp.vhd │ ├── list_ch03_20_fp_test.vhd │ ├── list_ch03_20_fp_test.zip │ ├── list_ch03_20_fp_test │ │ ├── list_ch03_20_fp_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch3_15_smadd_test.zip │ └── list_ch3_15_smadd_test │ │ ├── ch3_15_smadd_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── ch04 │ ├── ch04_21_fifo_test.zip │ ├── ch04_21_fifo_test │ │ ├── ch04_21_fifo_test.xise │ │ ├── led8_sseg.vhd │ │ └── logipi_r1_0_edu.ucf │ ├── ch4_14_disp_test.zip │ ├── ch4_14_disp_test │ │ ├── ch4_14_disp_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── ch4_16_disp_hex_test.zip │ ├── ch4_16_disp_hex_test │ │ ├── ch4_16_disp_hex_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── ch4_19_watch_test.zip │ ├── ch4_19_watch_test │ │ ├── ch4_19_watch_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch04_01_dff.vhd │ ├── list_ch04_02_dffr.vhd │ ├── list_ch04_03_04_dffen.vhd │ ├── list_ch04_05_reg.vhd │ ├── list_ch04_06_reg_file.vhd │ ├── list_ch04_07_shift.vhd │ ├── list_ch04_08_shift_u.vhd │ ├── list_ch04_09_bin.vhd │ ├── list_ch04_10_bin_u.vhd │ ├── list_ch04_11_mod_m.vhd │ ├── list_ch04_12_bin_tb.vhd │ ├── list_ch04_13_disp_mux.vhd │ ├── list_ch04_14_disp_test.vhd │ ├── list_ch04_15_disp_hex.vhd │ ├── list_ch04_16_hex_test.vhd │ ├── list_ch04_17_18_watch.vhd │ ├── list_ch04_19_watch_test.vhd │ ├── list_ch04_20_fifo.vhd │ └── list_ch04_21_fifo_test.vhd │ ├── ch05 │ ├── ch5_7_debounce_test.zip │ ├── ch5_7_debounce_test │ │ ├── ch5_7_debounce_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch05_01_02_fsm_eg.vhd │ ├── list_ch05_03_04_05_edge.vhd │ ├── list_ch05_06_debounce.vhd │ └── list_ch05_07_db_test.vhd │ ├── ch06 │ ├── ch6_3_db_test.zip │ ├── ch6_3_db_test │ │ ├── ch6_3_db_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch06_01_02_debounce.vhd │ ├── list_ch06_03_db_test.vhd │ ├── list_ch06_04_fib.vhd │ ├── list_ch06_05_div.vhd │ ├── list_ch06_06_bcd.vhd │ ├── list_ch06_07_period.vhd │ └── list_ch06_08_slow_freq.vhd │ ├── ch07 │ ├── ch07_uart_test.zip │ ├── ch07_uart_test │ │ ├── ch07_uart_test.xise │ │ ├── led8_sseg.vhd │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch07_01_uart_rx.vhd │ ├── list_ch07_02_flag.vhd │ ├── list_ch07_03_uart_tx.vhd │ ├── list_ch07_04_uart.vhd │ └── list_ch07_05_uart_test.vhd │ ├── ch08 │ ├── ch08_02_kb_mon.zip │ ├── ch08_02_kb_mon │ │ ├── ch08_02_kb_mon.xise │ │ └── logipi_r1_0_edu.ucf │ ├── ch08_5_kb_test.zip │ ├── ch08_5_kb_test │ │ ├── ch08_5_kb_test.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch08_01_ps2_rx.vhd │ ├── list_ch08_02_kb_mon.vhd │ ├── list_ch08_03_kb_lcode.vhd │ ├── list_ch08_04_key2ascii.vhd │ └── list_ch08_05_kb_test.vhd │ ├── ch09 │ ├── ch09_05_mouse_led.zip │ ├── ch09_05_mouse_led │ │ ├── ch09_05_mouse_led.xise │ │ ├── led8_sseg.vhd │ │ └── logipi_r1_0_edu.ucf │ ├── ch09_3_ps2_monitor.zip │ ├── ch09_3_ps2_monitor │ │ ├── ch09_3_ps2_monitor.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch09_01_ps2_tx.vhd │ ├── list_ch09_02_ps2_rxtx.vhd │ ├── list_ch09_03_ps2_mon.vhd │ ├── list_ch09_04_mouse.vhd │ └── list_ch09_05_mouse_led.vhd │ ├── ch10 │ ├── list_ch10_01_sram.vhd │ ├── list_ch10_02_sram_test1.vhd │ ├── list_ch10_03_sram_test2.vhd │ └── readme.txt │ ├── ch11 │ ├── list_ch11_01_x_ram_1p_async.vhd │ ├── list_ch11_02_x_ram_1p_sync.vhd │ ├── list_ch11_03_x_ram_2p_async.vhd │ ├── list_ch11_04_x_ram_2p_sync.vhd │ ├── list_ch11_05_x_rom_async.vhd │ ├── list_ch11_06_x_rom_sync.vhd │ └── readme.txt │ ├── ch12 │ ├── ch12_02_vga_sync_test.zip │ ├── ch12_02_vga_sync_test │ │ ├── ch12_02_vga_sync_test.gise │ │ ├── ch12_02_vga_sync_test.xise │ │ ├── iseconfig │ │ │ ├── ch12_02_vga_sync_test.projectmgr │ │ │ └── vga_test.xreport │ │ ├── logipi_r1_0_edu.ucf │ │ ├── par_usage_statistics.html │ │ ├── vga_test_bitgen.xwbt │ │ ├── vga_test_guide.ncd │ │ └── vga_test_summary.html │ ├── ch12_04_pong_top_st.zip │ ├── ch12_04_pong_top_st │ │ ├── ch12_04_pong_top_st.xise │ │ └── logipi_r1_0_edu.ucf │ ├── ch12_06_pong_top_an.zip │ ├── ch12_06_pong_top_an │ │ ├── ch12_06_pong_top_an.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch12_01_vga_sync.vhd │ ├── list_ch12_02_vga_sync_test.vhd │ ├── list_ch12_03_pong_gra_st.vhd │ ├── list_ch12_04_pong_top_st.vhd │ ├── list_ch12_05_pong_gra_an.vhd │ ├── list_ch12_06_pong_top_an.vhd │ ├── list_ch12_07_dot_gra.vhd │ ├── list_ch12_08_dot_top.vhd │ └── readme.txt │ ├── ch13 │ ├── ch13_03_font_test_top.zip │ ├── ch13_03_font_test_top │ │ ├── ch13_03_font_test_top.xise │ │ └── logipi_r1_0_edu.ucf │ ├── list_ch13_01_font_rom.vhd │ ├── list_ch13_02_font_test_gen.vhd │ ├── list_ch13_03_font_test_top.vhd │ ├── list_ch13_04_text_scr_gen.vhd │ ├── list_ch13_05_text_scr_top.vhd │ ├── list_ch13_06_pong_text.vhd │ ├── list_ch13_07_pong_graph.vhd │ ├── list_ch13_08_pong_counter.vhd │ ├── list_ch13_09_pong_timer.vhd │ ├── list_ch13_10_pong_top.vhd │ ├── list_ch13_10_pong_top.zip │ ├── list_ch13_10_pong_top │ │ ├── list_ch13_10_pong_top.xise │ │ └── logipi_r1_0_edu.ucf │ └── readme.txt │ ├── ch15 │ ├── SIO_ROM.VHD │ ├── list_ch15_02_sio_rom.psm │ └── list_ch15_03_pico_sio.vhd │ ├── ch16 │ ├── BTN_ROM.VHD │ ├── UART_ROM.VHD │ ├── list_ch16_01_btn_rom.psm │ ├── list_ch16_02_pico_btn.vhd │ ├── list_ch16_03_uart_rom.psm │ └── list_ch16_04_pico_uart.vhd │ ├── ch17 │ ├── INT_ROM.VHD │ ├── list_ch17_01_int_rom.psm │ └── list_ch17_02_pico_int.vhd │ ├── ch_appendix │ ├── list_ch_app_a01.vhd │ ├── list_ch_app_a02.vhd │ ├── list_ch_app_a03.vhd │ ├── list_ch_app_a04.vhd │ ├── list_ch_app_a05.vhd │ ├── list_ch_app_a06.vhd │ ├── list_ch_app_a07.vhd │ ├── list_ch_app_a08.vhd │ ├── list_ch_app_a09.vhd │ ├── list_ch_app_a10.vhd │ ├── list_ch_app_a11.vhd │ ├── list_ch_app_a12.vhd │ └── s3.ucf │ ├── example-listing.txt │ ├── logipi_r1_0_edu.ucf │ ├── vfx_source │ └── led8_sseg.vhd │ └── visio │ └── ch05 │ ├── ch05_SE_dual_edge_mealy.png │ ├── ch05_SE_dual_edge_mealy.vsd │ ├── ch05_SE_dual_edge_moore.png │ ├── ch05_SE_dual_edge_moore.vsd │ ├── ch05_db_fsm.png │ ├── ch05_db_fsm.vsd │ ├── ch05_db_fsm_SE_1.png │ └── ch05_db_fsm_SE_1.vsd ├── cheapscope-hamster ├── hw │ ├── capture.vhd │ ├── cheapscope.vhd │ ├── cheapscope_count_demo.vhd │ ├── logipi_ra2.ucf │ ├── tb_top_level.vhd │ └── transmitter.vhd ├── ise │ └── ise.xise └── sw │ ├── cheapscope.c │ ├── en-dsbl-serial │ ├── rpi-serial-console │ └── serial-utility-readme.txt │ └── readme.txt ├── doc ├── 1bit_counter.png ├── 1bit_counter.svg ├── eight_bit_stage.png └── fpga_struct.png ├── logi-bitcoin-miner ├── Open-Source-FPGA-Bitcoin-Miner-master │ ├── .gitignore │ └── projects │ │ └── VHDL_Xilinx_Port │ │ ├── Logibone.py │ │ ├── README.md │ │ ├── config.py │ │ ├── logibone_miner.py │ │ ├── miner.py │ │ ├── miner.vhd │ │ ├── sha256_ch.vhd │ │ ├── sha256_e0.vhd │ │ ├── sha256_e1.vhd │ │ ├── sha256_maj.vhd │ │ ├── sha256_pipeline.vhd │ │ ├── sha256_s0.vhd │ │ ├── sha256_s1.vhd │ │ ├── sha256_transform.vhd │ │ ├── top.vhd │ │ └── uart.vhd ├── logibone-hw │ ├── Open-Source-FPGA-Bitcoin-Miner-master │ │ ├── .gitignore │ │ └── projects │ │ │ └── VHDL_Xilinx_Port │ │ │ ├── Logibone.py │ │ │ ├── README.md │ │ │ ├── config.py │ │ │ ├── logibone_miner.py │ │ │ ├── miner.py │ │ │ ├── miner.vhd │ │ │ ├── sha256_ch.vhd │ │ │ ├── sha256_e0.vhd │ │ │ ├── sha256_e1.vhd │ │ │ ├── sha256_maj.vhd │ │ │ ├── sha256_pipeline.vhd │ │ │ ├── sha256_s0.vhd │ │ │ ├── sha256_s1.vhd │ │ │ ├── sha256_transform.vhd │ │ │ ├── top.vhd │ │ │ └── uart.vhd │ ├── ipcore_dir │ │ ├── clock_gen.asy │ │ ├── clock_gen.ncf │ │ ├── clock_gen.sym │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ ├── clock_gen.xise │ │ ├── clock_gen │ │ │ ├── doc │ │ │ │ └── clk_wiz_gsg521.pdf │ │ │ ├── example_design │ │ │ │ ├── clock_gen_exdes.ucf │ │ │ │ └── clock_gen_exdes.vhd │ │ │ ├── implement │ │ │ │ ├── implement.sh │ │ │ │ └── xst.scr │ │ │ └── simulation │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ ├── functional │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── wave.do │ │ │ │ └── wave.sv │ │ │ │ └── timing │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ ├── sdf_cmd_file │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ └── wave.do │ │ ├── clock_gen_exdes.ncf │ │ ├── clock_gen_xmdf.tcl │ │ ├── coregen.cgp │ │ ├── create_clock_gen.tcl │ │ └── edit_clock_gen.tcl │ ├── logibone_mining.ucf │ ├── logibone_mining.vhd │ ├── logibone_mining.xise │ ├── logibone_mining.xpi │ ├── logibone_ra2_1.ucf │ └── logibone_ra3.ucf ├── logipi-hw │ ├── ipcore_dir │ │ ├── clock_gen.asy │ │ ├── clock_gen.sym │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ ├── clock_gen.xise │ │ ├── clock_gen │ │ │ ├── doc │ │ │ │ └── clk_wiz_gsg521.pdf │ │ │ ├── example_design │ │ │ │ ├── clock_gen_exdes.ucf │ │ │ │ └── clock_gen_exdes.vhd │ │ │ ├── implement │ │ │ │ ├── implement.sh │ │ │ │ └── xst.scr │ │ │ └── simulation │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ ├── functional │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── wave.do │ │ │ │ └── wave.sv │ │ │ │ └── timing │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ ├── sdf_cmd_file │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ └── wave.do │ │ ├── clock_gen_exdes.ncf │ │ ├── clock_gen_xmdf.tcl │ │ ├── coregen.cgp │ │ └── create_clock_gen.tcl │ ├── logipi-hw.xise │ ├── logipi.ucf │ ├── logipi_mining.vhd │ ├── logipi_mining.xpi │ ├── logipi_ra2.ucf │ └── logipi_ra3.ucf └── sw │ ├── config.py │ ├── logibone.py │ ├── logibone_miner.py │ ├── mark1_miner.py │ ├── mark1_rpi.py │ ├── mark1_rpi_miner.py │ ├── startum.py~ │ ├── stratum.py │ └── stratum.py~ ├── logi-blink-led ├── README.TXT ├── bitfiles │ └── logibone_r1_blink.bit ├── doc │ ├── arch_diagram.png │ └── arch_diagram.svg └── hw │ ├── logibone │ ├── hdl │ │ ├── logibone_blink.ucf │ │ ├── logibone_blink.vhd │ │ ├── logibone_blink_R1.ucf │ │ ├── logibone_blink_RA2.ucf │ │ ├── logibone_ra1_blink.ucf │ │ ├── logibone_ra2_1.ucf │ │ └── logibone_ra2_blink.ucf │ └── ise │ │ └── blink_led.xise │ └── logipi │ ├── hdl │ ├── logipi_blink.vhd │ └── logipi_blink_R1.ucf │ └── ise │ └── logipi-hw.xise ├── logi-camera-bin ├── hw │ └── logipi │ │ ├── hdl │ │ ├── bin_to_fifo_tb.vhd │ │ ├── logipi_bin_cam.vhd │ │ └── logipi_ra3.ucf │ │ └── ise │ │ ├── iseconfig │ │ ├── logipi_bin_cam.projectmgr │ │ ├── logipi_bin_cam.xreport │ │ └── logipi_camera.xreport │ │ └── logipi_bin_cam.xise └── sw │ ├── grab_from_cam │ ├── Makefile │ ├── config.h │ ├── grab │ ├── grab.c │ ├── grab.c~ │ ├── grab_web.sh │ ├── grabbed_frame0000.jpg │ ├── grabbed_frame0000.yuv │ ├── jpeg_func.c │ └── jpeg_func.h │ ├── sensor_configuration │ ├── Makefile │ ├── ov7670.h │ ├── ov7670.h~ │ ├── sensor_conf │ ├── sensor_conf.c │ └── sensor_conf.o │ └── set_threshold.py ├── logi-camera-demo ├── README.TXT ├── hw │ ├── logibone │ │ ├── hdl │ │ │ ├── logibone_camera.ucf │ │ │ ├── logibone_camera.vhd │ │ │ ├── logibone_ra2_1.ucf │ │ │ ├── logibone_ra3.ucf │ │ │ └── test_alex.vhd │ │ └── ise │ │ │ ├── fuseRelaunch.cmd │ │ │ ├── ipcore_dir │ │ │ ├── clock_gen.ucf │ │ │ ├── clock_gen.vhd │ │ │ ├── clock_gen.xco │ │ │ └── clock_gen.xise │ │ │ └── logibone_camera.xise │ └── logipi │ │ ├── hdl │ │ ├── logipi_camera.vhd │ │ ├── logipi_ra1.ucf │ │ ├── logipi_ra2.ucf │ │ └── logipi_ra3.ucf │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ └── clock_gen.xise │ │ └── logipi-hw.xise ├── mark1-rpi-hw │ ├── ipcore_dir │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ └── clock_gen.xise │ ├── mark1-rpi-camera.xise │ ├── mark1_rpi_camera.ucf │ └── mark1_rpi_camera.vhd └── sw │ └── logi-mjpg-streamer │ ├── CHANGELOG │ ├── LICENSE │ ├── Makefile │ ├── README │ ├── fix_dependency.sh │ ├── launch_streamer.sh │ ├── mjpg_streamer.c │ ├── mjpg_streamer.h │ ├── plugins │ ├── input.h │ ├── input_file │ │ └── input_file.c │ ├── input_memory │ │ ├── Makefile │ │ ├── config.h │ │ ├── input_memory.c │ │ ├── jpeg_func.c │ │ ├── jpeg_func.h │ │ ├── wishbone_wrapper.c │ │ └── wishbone_wrapper.h │ ├── output.h │ └── output_http │ │ ├── Makefile │ │ ├── httpd.c │ │ ├── httpd.h │ │ └── output_http.c │ ├── start.sh │ ├── utils.c │ ├── utils.h │ └── www │ ├── bodybg.gif │ ├── cambozola.jar │ ├── control.htm │ ├── example.jpg │ ├── favicon.ico │ ├── favicon.png │ ├── fix.css │ ├── functions.js │ ├── sidebarbg.gif │ └── style.css ├── logi-camera-test ├── bitfiles │ └── logi_camera_test.bit ├── hw │ └── logipi │ │ ├── hdl │ │ ├── logi_camera_test.vhd │ │ ├── logipi_ra2.ucf │ │ └── logipi_ra3.ucf │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ └── clock_gen.xise │ │ └── logi_camera_test.xise └── sw │ └── logipi │ ├── Makefile │ ├── config.h │ ├── jpeg_func.c │ ├── jpeg_func.h │ ├── make_test.sh │ ├── test.c │ ├── wishbone_wrapper.c │ └── wishbone_wrapper.h ├── logi-com-test ├── hw │ ├── logibone │ │ ├── hdl │ │ │ ├── logibone_com_test.vhd │ │ │ ├── logibone_r1.ucf │ │ │ └── logibone_r1_5.ucf │ │ └── ise │ │ │ ├── ipcore_dir │ │ │ ├── clock_gen.asy │ │ │ ├── clock_gen.gise │ │ │ ├── clock_gen.sym │ │ │ ├── clock_gen.ucf │ │ │ ├── clock_gen.vhd │ │ │ ├── clock_gen.xco │ │ │ ├── clock_gen.xdc │ │ │ ├── clock_gen.xise │ │ │ ├── clock_gen │ │ │ │ ├── clk_wiz_v3_5_readme.txt │ │ │ │ ├── doc │ │ │ │ │ ├── clk_wiz_gsg521.pdf │ │ │ │ │ ├── clk_wiz_v3_5_readme.txt │ │ │ │ │ └── clk_wiz_v3_5_vinfo.html │ │ │ │ ├── example_design │ │ │ │ │ ├── clock_gen_exdes.ucf │ │ │ │ │ ├── clock_gen_exdes.vhd │ │ │ │ │ └── clock_gen_exdes.xdc │ │ │ │ ├── implement │ │ │ │ │ ├── implement.sh │ │ │ │ │ ├── planAhead_ise.sh │ │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ │ ├── xst.prj │ │ │ │ │ └── xst.scr │ │ │ │ └── simulation │ │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ │ ├── functional │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── wave.do │ │ │ │ │ └── wave.sv │ │ │ │ │ └── timing │ │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ │ ├── sdf_cmd_file │ │ │ │ │ ├── simcmds.tcl │ │ │ │ │ ├── simulate_isim.sh │ │ │ │ │ ├── simulate_mti.do │ │ │ │ │ ├── simulate_mti.sh │ │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ │ ├── simulate_vcs.sh │ │ │ │ │ ├── ucli_commands.key │ │ │ │ │ ├── vcs_session.tcl │ │ │ │ │ └── wave.do │ │ │ ├── clock_gen_exdes.ncf │ │ │ ├── clock_gen_flist.txt │ │ │ ├── clock_gen_xmdf.tcl │ │ │ ├── coregen.cgp │ │ │ ├── create_clock_gen.tcl │ │ │ └── tmp │ │ │ │ └── customization_gui.0.756167222167.out │ │ │ ├── iseconfig │ │ │ └── logibone_wishbone.xreport │ │ │ └── logibone_com_test.xise │ └── logipi │ │ ├── hdl │ │ ├── logipi_com_test.vhd │ │ └── logipi_r1.ucf │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.asy │ │ ├── clock_gen.gise │ │ ├── clock_gen.sym │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ ├── clock_gen.xdc │ │ ├── clock_gen.xise │ │ ├── clock_gen │ │ │ ├── clk_wiz_v3_5_readme.txt │ │ │ ├── doc │ │ │ │ ├── clk_wiz_gsg521.pdf │ │ │ │ ├── clk_wiz_v3_5_readme.txt │ │ │ │ └── clk_wiz_v3_5_vinfo.html │ │ │ ├── example_design │ │ │ │ ├── clock_gen_exdes.ucf │ │ │ │ ├── clock_gen_exdes.vhd │ │ │ │ └── clock_gen_exdes.xdc │ │ │ ├── implement │ │ │ │ ├── implement.sh │ │ │ │ ├── planAhead_ise.sh │ │ │ │ ├── planAhead_ise.tcl │ │ │ │ ├── planAhead_rdn.sh │ │ │ │ ├── planAhead_rdn.tcl │ │ │ │ ├── xst.prj │ │ │ │ └── xst.scr │ │ │ └── simulation │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ ├── functional │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── wave.do │ │ │ │ └── wave.sv │ │ │ │ └── timing │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ ├── sdf_cmd_file │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ └── wave.do │ │ ├── clock_gen_exdes.ncf │ │ ├── clock_gen_flist.txt │ │ ├── clock_gen_xmdf.tcl │ │ ├── coregen.cgp │ │ ├── coregen.log │ │ ├── create_clock_gen.tcl │ │ └── tmp │ │ │ └── customization_gui.0.506763464076.out │ │ ├── iseconfig │ │ └── logipi_wishbone.xreport │ │ └── logipi-com.xise └── sw │ ├── logibone │ ├── Makefile │ ├── test_wishbone.c │ ├── wishbone_wrapper.c │ └── wishbone_wrapper.h │ ├── logibone_spi │ ├── Makefile │ ├── test_wishbone.c │ ├── wishbone_wrapper.c │ └── wishbone_wrapper.h │ └── logipi │ ├── Makefile │ ├── test_wishbone │ ├── test_wishbone.c │ ├── wishbone_wrapper.c │ └── wishbone_wrapper.h ├── logi-edu-test ├── bitfiles │ └── logi_edu_test.bit ├── hw │ └── logipi │ │ ├── hdl │ │ ├── logi_edu_test.vhd │ │ ├── logipi_r1_1_edu.ucf │ │ ├── logipi_r1_5.ucf │ │ ├── logipi_ra2.ucf │ │ ├── logipi_ra2_edu.ucf │ │ ├── logipi_ra3.ucf │ │ ├── logipi_ra3_edu.ucf │ │ ├── sound_440.vhd │ │ ├── vga_bar_top.vhd │ │ └── vga_sync.vhd │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ └── clock_gen.xise │ │ └── logi_edu_test.xise └── sw │ └── common │ ├── Makefile │ ├── config.h │ ├── make_test.sh │ ├── test.c │ ├── wishbone_wrapper.c │ └── wishbone_wrapper.h ├── logi-edu ├── README.TXT ├── logi-edu-demo │ └── hw │ │ └── logipi │ │ ├── hdl │ │ ├── audio │ │ │ └── sound_440.vhd │ │ ├── logi_edu_demo.vhd │ │ ├── nes_ctl │ │ │ └── nes_ctl.vhd │ │ ├── pong │ │ │ ├── font_rom.vhd │ │ │ ├── pong_counter.vhd │ │ │ ├── pong_graph.vhd │ │ │ ├── pong_text.vhd │ │ │ ├── pong_timer.vhd │ │ │ ├── pong_top.vhd │ │ │ └── vga_sync.vhd │ │ ├── ps2 │ │ │ ├── mouse.vhd │ │ │ ├── mouse_led_sseg.vhd │ │ │ ├── ps2_rx.vhd │ │ │ ├── ps2_rxtx.vhd │ │ │ └── ps2_tx.vhd │ │ ├── sseg │ │ │ ├── list_ch04_15_disp_hex.vhd │ │ │ └── ssegx4_basic.vhd │ │ ├── ucf │ │ │ ├── logipi_r1.ucf │ │ │ ├── logipi_ra2.ucf │ │ │ ├── logipi_ra2_edu.ucf │ │ │ ├── logipi_ra3.ucf │ │ │ └── logipi_ra3_edu.ucf │ │ └── vga │ │ │ ├── vga_bar_top.vhd │ │ │ └── vga_sync.vhd │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.xco │ │ └── clock_gen.xise │ │ └── logi_edu_demo.xise ├── logi-mark1-edu-pong │ ├── hdl │ │ ├── Mark1_EDU_RA1.ucf │ │ ├── Mark1_EDU_RA2.ucf │ │ ├── list_ch12_01_vga_sync.vhd │ │ ├── list_ch13_01_font_rom.vhd │ │ ├── list_ch13_06_pong_text.vhd │ │ ├── list_ch13_07_pong_graph.vhd │ │ ├── list_ch13_08_pong_counter.vhd │ │ ├── list_ch13_09_pong_timer.vhd │ │ ├── list_ch13_10_pong_top.vhd │ │ ├── logipi_ra2_edu.ucf │ │ └── nes_ctl │ │ │ ├── nes_ctl.vhd │ │ │ ├── nes_ctl_tb.vhd │ │ │ └── nes_test.vhd │ └── ise │ │ └── vga_pong.xise ├── logi-pi-edu-pong │ ├── hdl │ │ ├── list_ch12_01_vga_sync.vhd │ │ ├── list_ch13_01_font_rom.vhd │ │ ├── list_ch13_06_pong_text.vhd │ │ ├── list_ch13_07_pong_graph.vhd │ │ ├── list_ch13_08_pong_counter.vhd │ │ ├── list_ch13_09_pong_timer.vhd │ │ ├── list_ch13_10_pong_top.vhd │ │ ├── logipi_r1_0_edu.ucf │ │ ├── logipi_ra2_edu.ucf │ │ ├── logipi_ra3_edu.ucf │ │ └── nes_ctl │ │ │ └── nes_ctl.vhd │ └── ise │ │ └── logi_vga_pong.xise ├── logi-pi-nes-servo-pwm │ ├── hw │ │ ├── hdl │ │ │ ├── logipi_ra3.ucf │ │ │ └── skeleton_pwm_servo.vhd │ │ └── ise │ │ │ └── skeleton_nes_servo_pwm.xise │ └── sw │ │ ├── nes_servo_control.py │ │ └── wishbone_map.py └── loig-pi-edu-mouse_led_sseg │ ├── hdl │ ├── mouse.vhd │ ├── mouse_led_sseg.vhd │ ├── ps2_rx.vhd │ ├── ps2_rxtx.vhd │ ├── ps2_tx.vhd │ └── ucf │ │ ├── logipi_r1_0_edu.ucf │ │ └── logipi_ra2_edu.ucf │ └── ise │ └── mouse_led_sseg.xise ├── logi-face ├── hw │ ├── compute_adc_mean.vhd │ └── logiface_pack.vhd ├── logipi-hw │ ├── ipcore_dir │ │ ├── clock_gen.xco │ │ └── clock_gen.xise │ ├── logipi.ucf │ ├── logipi_face.vhd │ └── logipi_face.xise └── sw │ ├── lin_client.py │ ├── logiface.py │ ├── python │ ├── logipi.c │ └── setup.py │ └── test_led_mat.py ├── logi-fcc-standalone └── hw │ ├── common │ ├── Memory_tester.vhd │ ├── SDRAM_Controller.vhd │ ├── blinker.vhd │ ├── sdram_model.vhd │ └── tb_top_level.vhd │ ├── logibone │ ├── hdl │ │ ├── logibone_fcc_standalone.vhd │ │ ├── logibone_fcc_standalone_simple.vhd │ │ ├── logibone_fcc_standalone_simple_nopll.vhd │ │ └── logibone_r1.ucf │ ├── ise │ │ ├── iseconfig │ │ │ ├── cheapscope.xreport │ │ │ └── logibone_fcc_standalone.projectmgr │ │ └── logibone_fcc_standalone.xise │ └── work │ │ ├── cheapscope_summary.html │ │ ├── logibone_fcc_standalone.gise │ │ ├── logibone_fcc_standalone_bitgen.xwbt │ │ ├── logibone_fcc_standalone_guide.ncd │ │ └── par_usage_statistics.html │ └── logipi │ ├── hdl │ ├── logipi_fcc_simple.vhd │ ├── logipi_fcc_standalone.vhd │ ├── logipi_fcc_standalone.vhd~ │ └── logipi_r1.ucf │ ├── ise │ ├── iseconfig │ │ ├── logipi_fcc_standalone.projectmgr │ │ └── logipi_fcc_standalone.xreport │ └── logipi_fcc_standalone.xise │ └── work │ ├── logipi_fcc_standalone.gise │ ├── logipi_fcc_standalone_bitgen.xwbt │ ├── logipi_fcc_standalone_guide.ncd │ ├── logipi_fcc_standalone_summary.html │ └── par_usage_statistics.html ├── logi-fcc ├── README ├── hw │ ├── common │ │ ├── Memory_tester.vhd │ │ ├── Memory_tester_v2.vhd │ │ ├── Memory_tester_v3.vhd │ │ ├── SDRAM_Controller.vhd │ │ └── wishbone_freq_gen.vhd │ ├── logibone │ │ ├── hdl │ │ │ ├── logibone_ra2_1.ucf │ │ │ ├── logibone_ra3.ucf │ │ │ └── logibone_test.vhd │ │ └── ise │ │ │ ├── ipcore_dir │ │ │ ├── clock_gen.gise │ │ │ ├── clock_gen.ncf │ │ │ ├── clock_gen.ucf │ │ │ ├── clock_gen.vhd │ │ │ ├── clock_gen.xco │ │ │ └── clock_gen.xise │ │ │ ├── iseconfig │ │ │ ├── logibone_test.projectmgr │ │ │ └── logibone_test.xreport │ │ │ ├── logibone_test.gise │ │ │ ├── logibone_test.xise │ │ │ ├── logibone_test_bitgen.xwbt │ │ │ ├── logibone_test_guide.ncd │ │ │ ├── logibone_test_summary.html │ │ │ └── par_usage_statistics.html │ └── logipi │ │ ├── hdl │ │ ├── logipi.ucf │ │ ├── logipi_ra2.ucf │ │ ├── logipi_ra3.ucf │ │ └── logipi_test.vhd │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.gise │ │ ├── clock_gen.ncf │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ └── clock_gen.xise │ │ ├── iseconfig │ │ ├── logipi_test.projectmgr │ │ └── logipi_test.xreport │ │ ├── logipi_test.gise │ │ ├── logipi_test.xise │ │ ├── logipi_test_bitgen.xwbt │ │ ├── logipi_test_guide.ncd │ │ ├── logipi_test_summary.html │ │ ├── par_usage_statistics.html │ │ └── test_top.vhd └── sw │ └── common │ ├── Makefile │ ├── config.h │ ├── test.c │ ├── test.c~ │ ├── wishbone_wrapper.c │ └── wishbone_wrapper.h ├── logi-laser-bot ├── hw │ ├── common │ │ └── max_pos_col.vhd │ └── logibone │ │ ├── hdl │ │ ├── logibone_cam_test.vhd │ │ └── logibone_ra3.ucf │ │ └── ise │ │ ├── iseconfig │ │ ├── logibone_cam_test.xreport │ │ └── logibone_laser_bot.projectmgr │ │ └── logibone_laser_bot.xise └── sw │ ├── bot.py │ ├── get_max_pos.py │ ├── laser.py │ └── sensor_configuration │ ├── Makefile │ ├── ov7670.h │ └── sensor_conf.c ├── logi-machine-vision ├── README.TXT ├── hw │ ├── logibone │ │ ├── hdl │ │ │ ├── logibone_machine_vision.vhd │ │ │ ├── logibone_ra2_1.ucf │ │ │ └── logibone_ra3.ucf │ │ └── ise │ │ │ ├── ipcore_dir │ │ │ ├── clock_gen.ucf │ │ │ ├── clock_gen.vhd │ │ │ ├── clock_gen.xco │ │ │ └── clock_gen.xise │ │ │ └── logibone_machine_vision.xise │ └── logipi │ │ ├── hdl │ │ ├── logipi_machine_vision.vhd │ │ └── logipi_r1.ucf │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.asy │ │ ├── clock_gen.sym │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ ├── clock_gen.xise │ │ ├── clock_gen │ │ │ ├── doc │ │ │ │ └── clk_wiz_gsg521.pdf │ │ │ ├── example_design │ │ │ │ ├── clock_gen_exdes.ucf │ │ │ │ └── clock_gen_exdes.vhd │ │ │ ├── implement │ │ │ │ ├── implement.sh │ │ │ │ └── xst.scr │ │ │ └── simulation │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ ├── functional │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── wave.do │ │ │ │ └── wave.sv │ │ │ │ └── timing │ │ │ │ ├── clock_gen_tb.vhd │ │ │ │ ├── sdf_cmd_file │ │ │ │ ├── simcmds.tcl │ │ │ │ ├── simulate_isim.sh │ │ │ │ ├── simulate_mti.do │ │ │ │ ├── simulate_mti.sh │ │ │ │ ├── simulate_ncsim.sh │ │ │ │ ├── simulate_vcs.sh │ │ │ │ ├── ucli_commands.key │ │ │ │ ├── vcs_session.tcl │ │ │ │ └── wave.do │ │ ├── clock_gen_exdes.ncf │ │ ├── clock_gen_xmdf.tcl │ │ ├── coregen.cgp │ │ ├── create_clock_gen.tcl │ │ └── edit_clock_gen.tcl │ │ └── logipi_machine_vision.xise └── sw │ ├── Makefile │ ├── beagle_qvga.jpg │ ├── grabbed_frame.jpg │ ├── image_demo.c │ ├── jpeg_func.c │ └── jpeg_func.h ├── logi-matrix ├── hw │ ├── logibone │ │ ├── hdl │ │ │ ├── logibone_mat.vhd │ │ │ └── logibone_ra3.ucf │ │ └── ise │ │ │ ├── iseconfig │ │ │ ├── logibone_mat.projectmgr │ │ │ └── logibone_mat.xreport │ │ │ ├── logibone_mat.gise │ │ │ ├── logibone_mat.xise │ │ │ ├── logibone_mat_bitgen.xwbt │ │ │ ├── logibone_mat_guide.ncd │ │ │ ├── logibone_mat_summary.html │ │ │ └── par_usage_statistics.html │ └── logipi │ │ ├── hdl │ │ ├── logipi_matrix.vhd │ │ ├── logipi_r1.ucf │ │ ├── matrix_ctrl_tb.vhd │ │ ├── rgb_32_32_matrix_ctrl.vhd │ │ └── wishbone_led_matrix_ctrl.vhd │ │ └── ise │ │ ├── iseconfig │ │ └── wishbone_led_matrix_ctrl.xreport │ │ └── logipi_matrix.xise └── sw │ ├── logipi │ ├── Makefile │ ├── README.md │ ├── data │ │ ├── README │ │ ├── beagleboard_logo.raw │ │ ├── frame_000.ppm │ │ ├── frame_001.ppm │ │ └── frame_002.ppm │ ├── gif.c │ ├── gif_4up.c │ ├── includes │ │ ├── gammalut.h │ │ ├── libppm.h │ │ └── wishbone_wrapper.h │ ├── led_white.c │ ├── led_white_4up.c │ ├── libppm.c │ ├── one_led.c │ ├── picture.c │ ├── test_wishbone │ ├── test_wishbone.c │ └── wishbone_wrapper.c │ └── test_mat.py ├── logi-motor-control ├── hw │ └── logibone │ │ ├── bitfiles │ │ └── logibone_motor_control.bit │ │ ├── hdl │ │ ├── logibone_motor_control.vhd │ │ └── logibone_r1.ucf │ │ └── ise │ │ ├── iseconfig │ │ └── logibon_motor_control.xreport │ │ └── logibone_motor_control.xise └── sw │ └── simulink │ ├── README.txt │ ├── SFB__logi_readall__SFB.mat │ ├── SFB__logibone_motor_block__SFB.mat │ ├── beaglebone_logi.slx │ ├── logi_readall.c │ ├── logi_readall.mexw64 │ ├── logi_readall.tlc │ ├── logi_readall_wrapper.c │ ├── logibone_motor_block.c │ ├── logibone_motor_block.mexw64 │ ├── logibone_motor_block.tlc │ ├── logibone_motor_block_wrapper.c │ ├── logibone_motorcontrol1.slx │ ├── logibone_motorcontrol2.slx │ ├── logibone_motorcontrol_openloop.mp4 │ └── rtwmakecfg.m ├── logi-sdram-fifo └── hw │ └── logibone │ ├── hdl │ ├── logibone_r1.ucf │ └── sdram_fifo_test.vhd │ └── ise │ ├── iseconfig │ └── sdram_fifo_test.xreport │ └── logibon_sdram_fifo.xise ├── logi-sdram-test └── hw │ ├── common │ ├── Memory_tester.vhd │ ├── SDRAM_Controller.vhd │ └── blinker.vhd │ ├── logibone │ ├── hdl │ │ ├── logibone_r1.ucf │ │ └── top_level.vhd │ └── ise │ │ ├── iseconfig │ │ ├── logibone-sdram.projectmgr │ │ └── top_level.xreport │ │ └── logibone-sdram.xise │ └── logipi │ ├── hdl │ ├── logipi_ra1.ucf │ └── top_level.vhd │ └── ise │ ├── iseconfig │ └── top_level.xreport │ └── logipi-sdram_v0.5.xise ├── logi-test ├── README ├── hw │ ├── common │ │ ├── Memory_tester.vhd │ │ └── SDRAM_Controller.vhd │ ├── logibone │ │ ├── hdl │ │ │ ├── logibone_ra2_1.ucf │ │ │ ├── logibone_ra3.ucf │ │ │ └── logibone_test.vhd │ │ └── ise │ │ │ ├── ipcore_dir │ │ │ ├── clock_gen.ucf │ │ │ ├── clock_gen.vhd │ │ │ ├── clock_gen.xco │ │ │ └── clock_gen.xise │ │ │ └── logibone_test.xise │ └── logipi │ │ ├── hdl │ │ ├── logipi.ucf │ │ ├── logipi_r1_5.ucf │ │ ├── logipi_ra2.ucf │ │ ├── logipi_ra3.ucf │ │ └── logipi_test.vhd │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ └── clock_gen.xise │ │ ├── logipi_test.xise │ │ └── test_top.vhd └── sw │ └── common │ ├── Makefile │ ├── config.h │ ├── fcc │ ├── Makefile │ ├── config.h │ ├── loop_call.sh │ ├── test.c │ ├── wishbone_wrapper.c │ └── wishbone_wrapper.h │ ├── loop_call.sh │ ├── test.c │ ├── wishbone_wrapper.c │ └── wishbone_wrapper.h ├── logi-ugv ├── hw │ └── logipi │ │ ├── hdl │ │ ├── data_cache.vhd │ │ ├── l3gd20_tb.vhd │ │ ├── logipi_r1.ucf │ │ ├── nmea_frame_extractor.vhd │ │ ├── ping_sensor_v2.vhd │ │ ├── ping_tb.vhd │ │ ├── test_serial.vhd │ │ ├── test_ugv.vhd │ │ ├── wishbone_gps.vhd │ │ └── wishbone_ping.vhd │ │ └── ise │ │ └── test_ugv.xise └── sw │ ├── avc_navigation.py │ ├── avc_waypoints.txt │ ├── controllers.py │ ├── coordinates.py │ ├── ether_client.py │ ├── gps_service.py │ ├── gps_test.py │ ├── imu_service.py │ ├── laas_waypoints.txt │ ├── linux-mpu9150 │ ├── LICENSE │ ├── Makefile │ ├── Makefile-native │ ├── README.md │ ├── build │ │ ├── lib.linux-armv6l-2.7 │ │ │ └── mpu9150.so │ │ ├── lib.linux-x86_64-2.7 │ │ │ └── mpu9150.so │ │ ├── temp.linux-armv6l-2.7 │ │ │ ├── eMPL │ │ │ │ ├── inv_mpu.o │ │ │ │ └── inv_mpu_dmp_motion_driver.o │ │ │ ├── glue │ │ │ │ └── linux_glue.o │ │ │ ├── mpu9150-python.o │ │ │ └── mpu9150 │ │ │ │ ├── mpu9150.o │ │ │ │ ├── quaternion.o │ │ │ │ └── vector3d.o │ │ └── temp.linux-x86_64-2.7 │ │ │ ├── eMPL │ │ │ ├── inv_mpu.o │ │ │ └── inv_mpu_dmp_motion_driver.o │ │ │ ├── glue │ │ │ └── linux_glue.o │ │ │ ├── mpu9150-python.o │ │ │ └── mpu9150 │ │ │ ├── mpu9150.o │ │ │ ├── quaternion.o │ │ │ └── vector3d.o │ ├── eMPL │ │ ├── README.md │ │ ├── dmpKey.h │ │ ├── dmpmap.h │ │ ├── inv_mpu.c │ │ ├── inv_mpu.h │ │ ├── inv_mpu_dmp_motion_driver.c │ │ └── inv_mpu_dmp_motion_driver.h │ ├── glue │ │ ├── linux_glue.c │ │ └── linux_glue.h │ ├── imu.c │ ├── imucal.c │ ├── local_defaults.h │ ├── magcal.txt │ ├── mpu9150-python.c │ ├── mpu9150 │ │ ├── mpu9150.c │ │ ├── mpu9150.h │ │ ├── quaternion.c │ │ ├── quaternion.h │ │ ├── vector3d.c │ │ └── vector3d.h │ ├── setup.py │ └── test_dmp.py │ ├── path_tracking_service.py │ ├── robot_model.py │ ├── speed_service.py │ ├── state_estimate_service.py │ ├── state_estimate_test.py │ ├── test_encoder.py │ ├── test_gps.py │ ├── test_sonar.py │ ├── traj_plot.py │ ├── ugv_map.py │ ├── ugv_navigation.py │ ├── ugv_platform.py │ ├── ugv_simulator.py │ └── waypoint_provider.py ├── logi-virtual-components ├── README.TXT ├── hw │ └── logipi │ │ ├── hdl │ │ ├── design_top.vhd │ │ ├── logipi_r1_0.ucf │ │ ├── logipi_ra2.ucf │ │ └── logipi_virtual_component.vhd │ │ └── ise │ │ ├── ipcore_dir │ │ ├── clock_gen.ucf │ │ ├── clock_gen.vhd │ │ ├── clock_gen.xco │ │ └── clock_gen.xise │ │ └── logipi_virtual_component.xise └── sw │ └── logi_panel │ ├── fifo_lib │ ├── Makefile │ ├── beaglebone-fifolib.c │ ├── fifo_test.c │ ├── fifolib.h │ └── rpi-fifolib.c │ ├── img │ ├── brd │ │ └── breadboard_800x293.png │ ├── finger │ │ └── finger_point_100.png │ ├── led │ │ ├── led_blue_final.png │ │ ├── led_clear_final.png │ │ ├── led_green_final.png │ │ └── led_yellow_final.png │ ├── pb │ │ ├── pb_npushed_75.png │ │ ├── pb_pushed_75.png │ │ ├── push_button.png │ │ ├── push_button_50.png │ │ ├── push_button_75.png │ │ └── push_button_75.psd │ ├── sseg │ │ ├── sega_100.png │ │ ├── segb_100.png │ │ ├── segc_100.png │ │ ├── segd_100.png │ │ ├── sege_100.png │ │ ├── segf_100.png │ │ ├── segg_100.png │ │ ├── segp_100.png │ │ ├── sseg_back_100.png │ │ └── sseg_mod_100.psd │ └── sw │ │ ├── sw1_h.png │ │ ├── sw1_l.png │ │ ├── sw2_h.png │ │ ├── sw2_l.png │ │ ├── sw3_h.png │ │ ├── sw3_l.png │ │ ├── sw4_h.png │ │ ├── sw4_l.png │ │ ├── sw5_h.png │ │ ├── sw5_l.png │ │ ├── sw6_h.png │ │ ├── sw6_l.png │ │ ├── sw6_l.psd │ │ ├── sw7_h.png │ │ ├── sw7_l.png │ │ ├── sw8_300_complete.psd │ │ ├── sw8_background.png │ │ ├── sw8_h.png │ │ └── sw8_l.png │ ├── virtual_component.py │ └── virtual_components.png ├── logi-wishbone ├── README.TXT ├── hw │ ├── logibone │ │ ├── hdl │ │ │ ├── logibone_r1.ucf │ │ │ ├── logibone_ra2_1.ucf │ │ │ ├── logibone_ra3.ucf │ │ │ └── logibone_wishbone.vhd │ │ └── ise │ │ │ ├── fuseRelaunch.cmd │ │ │ ├── ipcore_dir │ │ │ ├── clock_gen.ucf │ │ │ ├── clock_gen.vhd │ │ │ ├── clock_gen.xco │ │ │ └── clock_gen.xise │ │ │ ├── logibone-wishbone.xise │ │ │ └── wishbone-gpmc.xds │ └── logipi │ │ ├── hdl │ │ ├── logipi.ucf │ │ ├── logipi_ra2.ucf │ │ ├── logipi_ra3.ucf │ │ └── logipi_wishbone.vhd │ │ └── ise │ │ ├── iseconfig │ │ ├── logipi_wishbone.projectmgr │ │ └── logipi_wishbone.xreport │ │ ├── logipi_wishbone.xise │ │ └── logipi_wishbone_summary.html └── sw │ ├── logibone │ ├── MEMORY_LAYOUT.TXT │ ├── README.TXT │ ├── read_wishbone │ ├── read_wishbone.c │ ├── test_wishbone.c │ ├── write_wishbone │ └── write_wishbone.c │ ├── logipi │ ├── MEMORY_LAYOUT.TXT │ ├── Makefile │ ├── README.TXT │ ├── read_wishbone.c │ ├── test_wishbone.c │ ├── wishbone_wrapper.c │ ├── wishbone_wrapper.h │ └── write_wishbone.c │ └── test_wishbone.py ├── logipi-gpio_example └── hw │ ├── hdl │ ├── logipi_gpio.v │ ├── logipi_gpio.vhd │ └── logipi_r1_5.ucf │ ├── ise │ ├── iseconfig │ │ ├── logipi_gpio.projectmgr │ │ └── logipi_gpio.xreport │ └── logipi_gpio.xise │ └── work │ ├── logipi_gpio.gise │ ├── logipi_gpio_bitgen.xwbt │ ├── logipi_gpio_guide.ncd │ ├── logipi_gpio_summary.html │ └── par_usage_statistics.html ├── picoblaze_s6_basic ├── hdl │ ├── kcpsm6.vhd │ ├── logibone_r1_0.ucf │ └── pico_s6_top.vhd ├── ise │ ├── iseconfig │ │ └── pb_s6_basic.projectmgr │ └── pb_s6_basic.xise └── psm │ ├── ROM_form.vhd │ ├── kcpsm6.exe │ ├── pico_io_rom.psm │ └── pico_io_rom.vhd └── sump-logi-analyzer ├── client ├── Makefile ├── Manifest.txt ├── doc │ ├── package-list │ ├── resources │ │ └── inherit.gif │ └── stylesheet.css ├── license.txt ├── org │ └── sump │ │ ├── analyzer │ │ ├── CapturedData.java │ │ ├── Configurable.java │ │ ├── Device.java │ │ ├── DeviceController.java │ │ ├── Diagram.java │ │ ├── DiagramLabels.java │ │ ├── DiagramSettings.java │ │ ├── Loader.java │ │ ├── MainWindow.java │ │ ├── Project.java │ │ ├── StatusChangeListener.java │ │ ├── icons │ │ │ ├── fileclose.png │ │ │ ├── fileopen.png │ │ │ ├── filesaveas.png │ │ │ ├── la.png │ │ │ ├── launch.png │ │ │ ├── reload.png │ │ │ ├── viewmag+.png │ │ │ ├── viewmag-.png │ │ │ └── viewmag1.png │ │ └── tools │ │ │ ├── Base.java │ │ │ ├── I2CProtocolAnalysis.java │ │ │ ├── SPIProtocolAnalysis.java │ │ │ ├── StateAnalysis.java │ │ │ └── Tool.java │ │ └── util │ │ └── Properties.java ├── run.bat └── run.sh ├── fpga ├── clockman.vhd ├── controller.vhd ├── core.vhd ├── decoder.vhd ├── demux.vhd ├── display.vhd ├── eia232.vhd ├── filter.vhd ├── flags.vhd ├── ise-prj │ └── sump_analyzer │ │ ├── la.bld │ │ ├── la_map.map │ │ ├── la_map.mrp │ │ ├── la_map.ngm │ │ ├── sump_analyzer.xise │ │ └── webtalk_pn.xml ├── la.ucf ├── la.vhd ├── license.txt ├── prescaler.vhd ├── receiver.vhd ├── sampler.vhd ├── sram.vhd ├── stage.vhd ├── sync.vhd ├── test_core_simple.vhd ├── transmitter.vhd └── trigger.vhd ├── la-bin-0.8.tar.bz2 ├── la-src-0.8.tar.bz2 └── tester └── test.asm /.gitignore: -------------------------------------------------------------------------------- 1 | # Compiled Bitstreams 2 | *.bit 3 | 4 | # Xilinx generated files 5 | *.prj 6 | *.xst 7 | *.xwbt 8 | *.html 9 | *.gise 10 | *.xreport 11 | *.asy 12 | *.sym 13 | *.vho 14 | *.xdc 15 | *.ncf 16 | *.ncd 17 | *.log 18 | *.tcl 19 | *.cgp 20 | *.tcl 21 | *.out 22 | *.wdb 23 | */tmp/* 24 | */clock_gen/* 25 | */_xmsgs/* 26 | */iseconfig/* 27 | */ipcore_dir/*.txt 28 | *.cmd_log 29 | *.syr 30 | *.xmsgs 31 | *.vho 32 | *.bat 33 | 34 | -------------------------------------------------------------------------------- /AVC2013/PWM_SRC: -------------------------------------------------------------------------------- 1 | PWM VHDL files 2 | -------------------------------------------------------------------------------- /AVC2013/README.md: -------------------------------------------------------------------------------- 1 | Log-projects 2 | ============ 3 | AVC 2013 Code Base 4 | --app (python applications) 5 | --logi (Fpga frmware) 6 | --docs (documentation) 7 | 8 | This is the driectory for the AVC 2013 code base. the app directory contains the python application code and test rotuines. -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/CHANGELOG: -------------------------------------------------------------------------------- 1 | 2 | A changelog is available at: 3 | http://mjpg-streamer.svn.sourceforge.net/viewvc/mjpg-streamer/?view=log 4 | -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/fix_dependency.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ln -s /usr/include/libv4l1-videodev.h /usr/include/linux/videodev.h 4 | -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/launch_streamer.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ./mjpg_streamer -i "./input_memory.so -i $1 -r 160x120" -o "./output_http.so -w ./www" 3 | -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/plugins/input_memory/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################### 2 | # 3 | # Purpose: Makefile for "M-JPEG Streamer" 4 | # Author.: Tom Stoeveken (TST) 5 | # Version: 0.3 6 | # License: GPL 7 | # 8 | ############################################################### 9 | 10 | CC = gcc 11 | 12 | FIFO_LIB_DIR = /root/fifo_lib 13 | 14 | OTHER_HEADERS = ../../mjpg_streamer.h ../../utils.h ../output.h ../input.h $(FIFO_LIB_DIR)/fifolib.h 15 | 16 | CFLAGS += -O2 -DLINUX -D_GNU_SOURCE -Wall -shared -fPIC 17 | #CFLAGS += -DDEBUG 18 | LFLAGS += -lpthread -ldl -ljpeg -lm 19 | 20 | all: input_memory.so 21 | 22 | clean: 23 | rm -f *.a *.o core *~ *.so *.lo 24 | 25 | input_memory.so: $(OTHER_HEADERS) input_memory.c jpeg_func.c $(FIFO_LIB_DIR)/rpi-fifolib.c 26 | $(CC) $(CFLAGS) -I$(FIFO_LIB_DIR) -o $@ input_memory.c jpeg_func.c $(FIFO_LIB_DIR)/rpi-fifolib.c 27 | 28 | -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/plugins/input_memory/jpeg_func.h: -------------------------------------------------------------------------------- 1 | int write_jpegfile(char * frame, unsigned short width, unsigned short height, FILE * fd, int quality); 2 | int write_jpegmem_gray(char * frame, unsigned short width, unsigned short height, unsigned char **outbuffer, long unsigned int *outlen, int quality); 3 | int write_jpegmem_rgb(char * frame, unsigned short width, unsigned short height, unsigned char **outbuffer, long unsigned int *outlen, int quality); 4 | -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/plugins/output_http/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################### 2 | # 3 | # Purpose: Makefile for "M-JPEG Streamer" 4 | # Author.: Tom Stoeveken (TST) 5 | # Version: 0.3 6 | # License: GPL 7 | # 8 | ############################################################### 9 | 10 | CC = gcc 11 | 12 | OTHER_HEADERS = ../../mjpg_streamer.h ../../utils.h ../output.h ../input.h 13 | 14 | CFLAGS += -O2 -DLINUX -D_GNU_SOURCE -Wall -shared -fPIC 15 | #CFLAGS += -DDEBUG 16 | LFLAGS += -lpthread -ldl 17 | 18 | all: output_http.so 19 | 20 | clean: 21 | rm -f *.a *.o core *~ *.so *.lo 22 | 23 | output_http.so: $(OTHER_HEADERS) output_http.c httpd.lo 24 | $(CC) $(CFLAGS) -o $@ output_http.c httpd.lo 25 | 26 | httpd.lo: $(OTHER_HEADERS) httpd.h httpd.c 27 | $(CC) -c $(CFLAGS) -o $@ httpd.c 28 | -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/www/bodybg.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/AVC2013/avc-mjpg-streamer/www/bodybg.gif -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/www/cambozola.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/AVC2013/avc-mjpg-streamer/www/cambozola.jar -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/www/example.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/AVC2013/avc-mjpg-streamer/www/example.jpg -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/www/favicon.ico: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/AVC2013/avc-mjpg-streamer/www/favicon.ico -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/www/favicon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/AVC2013/avc-mjpg-streamer/www/favicon.png -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/www/fix.css: -------------------------------------------------------------------------------- 1 | /**************** IE fixes ****************/ 2 | 3 | html 4 | {overflow:hidden;} 5 | 6 | body 7 | {height:100%; width:100%; overflow:auto;} -------------------------------------------------------------------------------- /AVC2013/avc-mjpg-streamer/www/sidebarbg.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/AVC2013/avc-mjpg-streamer/www/sidebarbg.gif -------------------------------------------------------------------------------- /AVC2013/avcinit.sh: -------------------------------------------------------------------------------- 1 | sudo gpsd /dev/ttyAMA0 -F /var/run/gpsd.sock 2 | sudo logi_loader avc_platform/avc_platform.bit 3 | -------------------------------------------------------------------------------- /AVC2013/grab_from_cam/Makefile: -------------------------------------------------------------------------------- 1 | #Compiler to use 2 | CC=gcc 3 | #Compiler Flags 4 | CFLAGS=-c -I../fifo_lib/#-Wall 5 | #Linker Flags 6 | LDFLAGS= -ljpeg -lrt 7 | 8 | all: grab_frame 9 | 10 | grab_frame: grab_frame.o jpeg_func.o fifolib.o 11 | $(CC) -o grab_frame grab_frame.o jpeg_func.o ../fifo_lib/rpi-fifolib.o $(LDFLAGS) 12 | 13 | fifolib.o: 14 | make -C ../fifo_lib 15 | 16 | grab_frame.o: grab_frame.c 17 | $(CC) $(CFLAGS) grab_frame.c 18 | 19 | jpeg_func.o: jpeg_func.c 20 | $(CC) $(CFLAGS) jpeg_func.c 21 | 22 | clean: 23 | rm -rf *o grab_frame 24 | -------------------------------------------------------------------------------- /AVC2013/grab_from_cam/jpeg_func.h: -------------------------------------------------------------------------------- 1 | int write_jpegfile(char * frame, unsigned short width, unsigned short height, int nbChan, FILE * fd, int quality); 2 | int write_jpegmem(char * frame, unsigned short width, unsigned short height, unsigned short nbChannels, unsigned char **outbuffer, long unsigned int *outlen, int quality); 3 | int read_jpeg_file( char *filename, unsigned char ** buffer); 4 | -------------------------------------------------------------------------------- /AVC2013/imu-python-wrapper/README: -------------------------------------------------------------------------------- 1 | These file builds a python wrapper for the mpu9150 library : 2 | 3 | git://github.com/Pansenti/linux-mpu9150.git 4 | 5 | just copy the two files into the cloned git folder and run : 6 | 7 | python setup.py build 8 | python setup.py install 9 | 10 | To test the installation run the test_dmp.py file (with imu connected to I2C bus 1) 11 | 12 | You will need the python-dev package installed to build the package. 13 | -------------------------------------------------------------------------------- /AVC2013/imu-python-wrapper/setup.py: -------------------------------------------------------------------------------- 1 | from distutils.core import setup, Extension 2 | 3 | module1 = Extension('mpu9150', 4 | sources = ['mpu9150-python.c', 5 | 'mpu9150/mpu9150.c', 6 | 'mpu9150/quaternion.c', 7 | 'mpu9150/vector3d.c', 8 | 'eMPL/inv_mpu.c', 9 | 'eMPL/inv_mpu_dmp_motion_driver.c', 10 | 'glue/linux_glue.c', ], 11 | include_dirs=['./mpu9150', 12 | './eMPL', 13 | './glue'], 14 | define_macros=[('EMPL_TARGET_LINUX', None), 15 | ('MPU9150', None), 16 | ('AK8975_SECONDARY', None), 17 | ('Wall', None), 18 | ('fsingle-precision-constant', None), 19 | ], 20 | libraries=['m']) 21 | 22 | setup (name = 'PackageName', 23 | version = '1.0', 24 | description = 'This is a demo package', 25 | ext_modules = [module1]) 26 | -------------------------------------------------------------------------------- /AVC2013/imu-python-wrapper/test_dmp.py: -------------------------------------------------------------------------------- 1 | import mpu9150 2 | import time 3 | 4 | mpu9150.mpuInit(1, 10, 4) 5 | mpu9150.setMagCal('magcal.txt') 6 | mpu9150.setAccCal('accelcal.txt') 7 | while True : 8 | i = mpu9150.mpuRead() 9 | if i >= 0: 10 | print mpu9150.getFusedEuler() 11 | time.sleep(0.1) 12 | 13 | -------------------------------------------------------------------------------- /AVC2013/platform-python-wrapper/ether_client.py: -------------------------------------------------------------------------------- 1 | 2 | from socket import * 3 | 4 | 5 | 6 | HOST = '10.0.7.2' 7 | PORT = 2045 #our port from before 8 | ADDR = (HOST,PORT) 9 | BUFSIZE = 4096 10 | 11 | cli = socket( AF_INET,SOCK_STREAM) 12 | cli.connect((ADDR)) 13 | 14 | cli.send('{ "steer" : 30.0, "time" : 5000.0, "speed" : 45.0 }') 15 | cli.send('{ "steer" : -30.0, "time" : 5000.0, "speed" : -45.0 }') 16 | 17 | cli.close() 18 | -------------------------------------------------------------------------------- /AVC2013/platform-python-wrapper/gps_service.py: -------------------------------------------------------------------------------- 1 | import os 2 | from gps import * 3 | from time import * 4 | import time 5 | import threading 6 | 7 | gpsd = None #seting the global variable 8 | 9 | os.system('clear') #clear the terminal (optional) 10 | 11 | class Point(object): 12 | def __init__(self, lat, lon): 13 | self.lat = lat 14 | self.lon = lon 15 | 16 | class GpsService(threading.Thread): 17 | def __init__(self): 18 | threading.Thread.__init__(self) 19 | global gpsd #bring it in scope 20 | gpsd = gps(mode=WATCH_ENABLE) #starting the stream of info 21 | self.current_value = None 22 | self.daemon = True 23 | self.running = True #setting the thread running to true 24 | 25 | def run(self): 26 | global gpsd 27 | while True: 28 | gpsd.next() 29 | sleep(0.1) 30 | 31 | def getPosition(self): 32 | current_pos = Point(gpsd.fix.latitude, gpsd.fix.longitude) 33 | return current_pos 34 | 35 | 36 | -------------------------------------------------------------------------------- /AVC2013/platform-python-wrapper/launch_avc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | modprobe spi_bcm2708 4 | modprobe i2c_dev 5 | logi_loader avc_platform.bit 6 | gpsd -n /dev/ttyUSB0 7 | python avc_navigation.py 8 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Log-projects 2 | ============ 3 | 4 | Each project has its own repository and can link to other repositories (loader, tools, HardwareCV) -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch01/list_ch01_01_eq1.v: -------------------------------------------------------------------------------- 1 | // Listing 1.1 2 | module eq1 3 | // I/O ports 4 | ( 5 | input wire i0, i1, 6 | output wire eq 7 | ); 8 | 9 | // signal declaration 10 | wire p0, p1; 11 | 12 | // body 13 | // sum of two product terms 14 | assign eq = p0 | p1; 15 | // product terms 16 | assign p0 = ~i0 & ~i1; 17 | assign p1 = i0 & i1; 18 | 19 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch01/list_ch01_02_eq1_implicit.v: -------------------------------------------------------------------------------- 1 | // Listing 1.2 2 | module eq1_implicit 3 | ( 4 | input i0, i1, // no data type declaration 5 | output eq 6 | ); 7 | 8 | // no internal signal declaration 9 | 10 | // product terms must be placed in front 11 | assign p0 = ~i0 & ~i1; //implicit declaration 12 | assign p1 = i0 & i1; //implicit declaration 13 | // sum of two product terms 14 | assign eq = p0 | p1; 15 | 16 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch01/list_ch01_03_eq2_sop.v: -------------------------------------------------------------------------------- 1 | // Listing 1.3 2 | module eq2_sop 3 | ( 4 | input wire[1:0] a, b, 5 | output wire aeqb 6 | ); 7 | 8 | // internal signal declaration 9 | wire p0, p1, p2, p3; 10 | 11 | // sum of product terms 12 | assign aeqb = p0 | p1 | p2 | p3; 13 | // product terms 14 | assign p0 = (~a[1] & ~b[1]) & (~a[0] & ~b[0]); 15 | assign p1 = (~a[1] & ~b[1]) & (a[0] & b[0]); 16 | assign p2 = (a[1] & b[1]) & (~a[0] & ~b[0]); 17 | assign p3 = (a[1] & b[1]) & (a[0] & b[0]); 18 | 19 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch01/list_ch01_04_eq2.v: -------------------------------------------------------------------------------- 1 | // Listing 1.4 2 | module eq2 3 | ( 4 | input wire[1:0] a, b, 5 | output wire aeqb 6 | ); 7 | 8 | // internal signal declaration 9 | wire e0, e1; 10 | 11 | // body 12 | // instantiate two 1-bit comparators 13 | eq1 eq_bit0_unit (.i0(a[0]), .i1(b[0]), .eq(e0)); 14 | eq1 eq_bit1_unit (.eq(e1), .i0(a[1]), .i1(b[1])); 15 | 16 | // a and b are equal if individual bits are equal 17 | assign aeqb = e0 & e1; 18 | 19 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch01/list_ch01_05_eq1_primitive.v: -------------------------------------------------------------------------------- 1 | // Listing 1.5 2 | module eq1_primitive 3 | ( 4 | input wire i0, i1, 5 | output wire eq 6 | ); 7 | 8 | // internal signal declaration 9 | wire i0_n, i1_n, p0, p1; 10 | 11 | //primitive gate instantiations 12 | not unit1 (i0_n, i0); // i0_n = ~i0; 13 | not unit2 (i1_n, i1); // i1_n = ~i1; 14 | and unit3 (p0, i0_n, i1_n); // p0 = i0_n & i1_n; 15 | and unit4 (p1, i0, i1); // p1 = i0 & i1; 16 | or unit5 (eq, p0, p1); // eq = p0 | p1; 17 | 18 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch01/list_ch01_06_eq1_udp.v: -------------------------------------------------------------------------------- 1 | // Listing 1.6 2 | primitive eq1_udp(eq, i0, i1); 3 | output eq; 4 | input i0, i1; 5 | 6 | table 7 | // i0 i1 : eq 8 | 0 0 : 1; 9 | 0 1 : 0; 10 | 1 0 : 0; 11 | 1 1 : 1; 12 | endtable 13 | 14 | endprimitive -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch02/list_ch02_01_eq1.v: -------------------------------------------------------------------------------- 1 | // Listing 2.1 2 | module eq1 3 | // I/O ports 4 | ( 5 | input wire i0, i1, 6 | output wire eq 7 | ); 8 | 9 | // signal declaration 10 | wire p0, p1; 11 | 12 | // body 13 | // sum of two product terms 14 | assign eq = p0 | p1; 15 | // product terms 16 | assign p0 = ~i0 & ~i1; 17 | assign p1 = i0 & i1; 18 | 19 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch02/list_ch02_02_eq2.v: -------------------------------------------------------------------------------- 1 | // Listing 2.2 2 | module eq2 3 | ( 4 | input wire[1:0] a, b, 5 | output wire aeqb 6 | ); 7 | 8 | // internal signal declaration 9 | wire e0, e1; 10 | 11 | // body 12 | // instantiate two 1-bit comparators 13 | eq1 eq_bit0_unit (.i0(a[0]), .i1(b[0]), .eq(e0)); 14 | eq1 eq_bit1_unit (.eq(e1), .i0(a[1]), .i1(b[1])); 15 | 16 | // a and b are equal if individual bits are equal 17 | assign aeqb = e0 & e1; 18 | 19 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/ch03_17_sm_add_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch03/ch03_17_sm_add_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/ch03_20_shifter_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch03/ch03_20_shifter_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/ch03_22_fp_adder_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch03/ch03_22_fp_adder_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/ch3_13_hex_to_sseg_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch03/ch3_13_hex_to_sseg_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_01_eq1_always.v: -------------------------------------------------------------------------------- 1 | // Listing 3.1 2 | module eq1_always 3 | ( 4 | input wire i0, i1, 5 | output reg eq // eq declared as reg 6 | ); 7 | 8 | // p0 and p1 declared as reg 9 | reg p0, p1; 10 | 11 | always @(i0, i1) // i0 an i1 must be in sensitivity list 12 | begin 13 | // the order of statements is important 14 | p0 = ~i0 & ~i1; 15 | p1 = i0 & i1; 16 | eq = p0 | p1; 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_02_and_block_assign.v: -------------------------------------------------------------------------------- 1 | // Listing 3.2 2 | module and_block_assign 3 | ( 4 | input wire a, b, c, 5 | output reg y 6 | ); 7 | 8 | always @* 9 | begin 10 | y = a; 11 | y = y & b; 12 | y = y & c; 13 | end 14 | 15 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_03_and_cont_assign.v: -------------------------------------------------------------------------------- 1 | // Listing 3.3 2 | module and_cont_assign 3 | ( 4 | input wire a, b, c, 5 | output wire y 6 | ); 7 | 8 | assign y = a; 9 | assign y = y & b; 10 | assign y = y & c; 11 | 12 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_04_prio_encoder_if.v: -------------------------------------------------------------------------------- 1 | // Listing 3.4 2 | module prio_encoder_if 3 | ( 4 | input wire [4:1] r, 5 | output reg [2:0] y 6 | ); 7 | 8 | always @* 9 | if (r[4]==1'b1) // can be written as (r[4]) 10 | y = 3'b100; 11 | else if (r[3]==1'b1) // can be written as (r[3]) 12 | y = 3'b011; 13 | else if (r[2]==1'b1) // can be written as (r[2]) 14 | y = 3'b010; 15 | else if (r[1]==1'b1) // can be written as (r[1]) 16 | y = 3'b001; 17 | else 18 | y = 3'b000; 19 | 20 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_05_decoder_2_4_if.v: -------------------------------------------------------------------------------- 1 | // Listing 3.5 2 | module decoder_2_4_if 3 | ( 4 | input wire [1:0] a, 5 | input wire en, 6 | output reg [3:0] y 7 | ); 8 | 9 | always @* 10 | if (en==1'b0) // can be written as (~en) 11 | y = 4'b0000; 12 | else if (a==2'b00) 13 | y = 4'b0001; 14 | else if (a==2'b01) 15 | y = 4'b0010; 16 | else if (a==2'b10) 17 | y = 4'b0100; 18 | else 19 | y = 4'b1000; 20 | 21 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_06_decoder_2_4_case.v: -------------------------------------------------------------------------------- 1 | // Listing 3.6 2 | module decoder_2_4_case 3 | ( 4 | input wire [1:0] a, 5 | input wire en, 6 | output reg [3:0] y 7 | ); 8 | 9 | always @* 10 | case({en,a}) 11 | 3'b000, 3'b001, 3'b010, 3'b011: y = 4'b0000; 12 | 3'b100: y = 4'b0001; 13 | 3'b101: y = 4'b0010; 14 | 3'b110: y = 4'b0100; 15 | 3'b111: y = 4'b1000; // default can also be used 16 | endcase 17 | 18 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_07_prio_encoder_case.v: -------------------------------------------------------------------------------- 1 | // Listing 3.7 2 | module prio_encoder_case 3 | ( 4 | input wire [4:1] r, 5 | output reg [2:0] y 6 | ); 7 | 8 | always @* 9 | case(r) 10 | 4'b1000, 4'b1001, 4'b1010, 4'b1011, 11 | 4'b1100, 4'b1101, 4'b1110, 4'b1111: 12 | y = 3'b100; 13 | 4'b0100, 4'b0101, 4'b0110, 4'b0111: 14 | y = 3'b011; 15 | 4'b0010, 4'b0011: 16 | y = 3'b010; 17 | 4'b0001: 18 | y = 3'b001; 19 | 4'b0000: // default can also be used 20 | y = 3'b000; 21 | endcase 22 | 23 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_08_prio_encoder_casez.v: -------------------------------------------------------------------------------- 1 | // Listing 3.8 2 | module prio_encoder_casez 3 | ( 4 | input wire [4:1] r, 5 | output reg [2:0] y 6 | ); 7 | 8 | always @* 9 | casez(r) 10 | 4'b1???: y = 3'b100; 11 | 4'b01??: y = 3'b011; 12 | 4'b001?: y = 3'b010; 13 | 4'b0001: y = 3'b001; 14 | 4'b0000: y = 3'b000; // default can also be used 15 | endcase 16 | 17 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_09_adder_carry_hard_lit.v: -------------------------------------------------------------------------------- 1 | // Listing 3.9 2 | module adder_carry_hard_lit 3 | ( 4 | input wire [3:0] a, b, 5 | output wire [3:0] sum, 6 | output wire cout // carry-out 7 | ); 8 | 9 | // signal declaration 10 | wire [4:0] sum_ext; 11 | 12 | //body 13 | assign sum_ext = {1'b0, a} + {1'b0, b}; 14 | assign sum = sum_ext[3:0]; 15 | assign cout= sum_ext[4]; 16 | 17 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_10_adder_carry_local_par.v: -------------------------------------------------------------------------------- 1 | // Listing 3.10 2 | module adder_carry_local_par 3 | ( 4 | input wire [3:0] a, b, 5 | output wire [3:0] sum, 6 | output wire cout // carry-out 7 | ); 8 | 9 | // constant declaration 10 | localparam N = 4, 11 | N1 = N-1; 12 | 13 | // signal declaration 14 | wire [N:0] sum_ext; 15 | 16 | //body 17 | assign sum_ext = {1'b0, a} + {1'b0, b}; 18 | assign sum = sum_ext[N1:0]; 19 | assign cout= sum_ext[N]; 20 | 21 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_11_adder_carry_para.v: -------------------------------------------------------------------------------- 1 | // Listing 3.11 2 | module adder_carry_para 3 | #(parameter N=4) 4 | ( 5 | input wire [N-1:0] a, b, 6 | output wire [N-1:0] sum, 7 | output wire cout // carry-out 8 | ); 9 | 10 | // constant declaration 11 | localparam N1 = N-1; 12 | 13 | // signal declaration 14 | wire [N:0] sum_ext; 15 | 16 | //body 17 | assign sum_ext = {1'b0, a} + {1'b0, b}; 18 | assign sum = sum_ext[N1:0]; 19 | assign cout= sum_ext[N]; 20 | 21 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_12_adder_insta.v: -------------------------------------------------------------------------------- 1 | // Listing 3.12 2 | module adder_insta 3 | ( 4 | input wire [3:0] a4, b4, 5 | output wire [3:0] sum4, 6 | output wire c4, 7 | input wire [7:0] a8, b8, 8 | output wire [7:0] sum8, 9 | output wire c8 10 | ); 11 | 12 | // instantiate 8-bit adder 13 | adder_carry_para #(.N(8)) unit1 14 | (.a(a8), .b(b8), .sum(sum8), .cout(c8)); 15 | 16 | // instantiate 4-bit adder 17 | adder_carry_para unit2 18 | (.a(a4), .b(b4), .sum(sum4), .cout(c4)); 19 | 20 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_13_adder_carry_95.v: -------------------------------------------------------------------------------- 1 | // Listing 3.13 2 | module adder_carry_95 (a, b, sum, cout); 3 | parameter N = 4; // parameter declared before the port 4 | parameter N1 = N-1; // no localparam in Verilog-1995 5 | input wire [N1:0] a, b; 6 | output wire [N1:0] sum; 7 | output wire cout; 8 | 9 | // signal declaration 10 | wire [N:0] sum_ext; 11 | 12 | //body 13 | assign sum_ext = {1'b0, a} + {1'b0, b}; 14 | assign sum = sum_ext[N1:0]; 15 | assign cout= sum_ext[N]; 16 | 17 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_18_barrel_shifter_case.v: -------------------------------------------------------------------------------- 1 | // Listing 3.18 2 | module barrel_shifter_case 3 | ( 4 | input wire [7:0] a, 5 | input wire [2:0] amt, 6 | output reg [7:0] y 7 | ); 8 | 9 | // body 10 | always @* 11 | case(amt) 12 | 3'o0: y = a; 13 | 3'o1: y = {a[0], a[7:1]}; 14 | 3'o2: y = {a[1:0], a[7:2]}; 15 | 3'o3: y = {a[2:0], a[7:3]}; 16 | 3'o4: y = {a[3:0], a[7:4]}; 17 | 3'o5: y = {a[4:0], a[7:5]}; 18 | 3'o6: y = {a[5:0], a[7:6]}; 19 | default: y = {a[6:0], a[7]}; 20 | endcase 21 | 22 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch03/list_ch03_19_barrel_shifter_stage.v: -------------------------------------------------------------------------------- 1 | // Listing 3.19 2 | module barrel_shifter_stage 3 | ( 4 | input wire [7:0] a, 5 | input wire [2:0] amt, 6 | output wire [7:0] y 7 | ); 8 | 9 | // signal declaration 10 | wire [7:0] s0, s1; 11 | 12 | // body 13 | // stage 0, shift 0 or 1 bit 14 | assign s0 = amt[0] ? {a[0], a[7:1]} : a; 15 | // stage 1, shift 0 or 2 bits 16 | assign s1 = amt[1] ? {s0[1:0], s0[7:2]} : s0; 17 | // stage 2, shift 0 or 4 bits 18 | assign y = amt[2] ? {s1[3:0], s1[7:4]} : s1; 19 | 20 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/ch04_16_disp_mux_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch04/ch04_16_disp_mux_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/ch04_19_stop_watch_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch04/ch04_19_stop_watch_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/ch04_21_fifo_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch04/ch04_21_fifo_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_01_d_ff.v: -------------------------------------------------------------------------------- 1 | // Listing 4.1 2 | module d_ff 3 | ( 4 | input wire clk, 5 | input wire d, 6 | output reg q 7 | ); 8 | 9 | // body 10 | always @(posedge clk) 11 | q <= d; 12 | 13 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_02_d_ff_reset.v: -------------------------------------------------------------------------------- 1 | // Listing 4.2 2 | module d_ff_reset 3 | ( 4 | input wire clk, reset, 5 | input wire d, 6 | output reg q 7 | ); 8 | 9 | // body 10 | always @(posedge clk, posedge reset) 11 | if (reset) 12 | q <= 1'b0; 13 | else 14 | q <= d; 15 | 16 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_03_d_ff_en_1seg.v: -------------------------------------------------------------------------------- 1 | // Listing 4.3 2 | module d_ff_en_1seg 3 | ( 4 | input wire clk, reset, 5 | input wire en, 6 | input wire d, 7 | output reg q 8 | ); 9 | 10 | // body 11 | always @(posedge clk, posedge reset) 12 | if (reset) 13 | q <= 1'b0; 14 | else if (en) 15 | q <= d; 16 | 17 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_04_d_ff_en_2seg.v: -------------------------------------------------------------------------------- 1 | // Listing 4.4 2 | module d_ff_en_2seg 3 | ( 4 | input wire clk, reset, 5 | input wire en, 6 | input wire d, 7 | output reg q 8 | ); 9 | 10 | // signal declaration 11 | reg r_reg, r_next; 12 | 13 | // body 14 | // D FF 15 | always @(posedge clk, posedge reset) 16 | if (reset) 17 | r_reg <= 1'b0; 18 | else 19 | r_reg <= r_next; 20 | 21 | // next-state logic 22 | always @* 23 | if (en) 24 | r_next = d; 25 | else 26 | r_next = r_reg; 27 | 28 | // output logic 29 | always @* 30 | q = r_reg; 31 | 32 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_05_reg_reset.v: -------------------------------------------------------------------------------- 1 | // Listing 4.5 2 | module reg_reset 3 | ( 4 | input wire clk, reset, 5 | input wire [7:0] d, 6 | output reg [7:0] q 7 | ); 8 | 9 | // body 10 | always @(posedge clk, posedge reset) 11 | if (reset) 12 | q <= 0; 13 | else 14 | q <= d; 15 | 16 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_06_reg_file.v: -------------------------------------------------------------------------------- 1 | // Listing 4.6 2 | module reg_file 3 | #( 4 | parameter B = 8, // number of bits 5 | W = 2 // number of address bits 6 | ) 7 | ( 8 | input wire clk, 9 | input wire wr_en, 10 | input wire [W-1:0] w_addr, r_addr, 11 | input wire [B-1:0] w_data, 12 | output wire [B-1:0] r_data 13 | ); 14 | 15 | // signal declaration 16 | reg [B-1:0] array_reg [2**W-1:0]; 17 | 18 | // body 19 | // write operation 20 | always @(posedge clk) 21 | if (wr_en) 22 | array_reg[w_addr] <= w_data; 23 | // read operation 24 | assign r_data = array_reg[r_addr]; 25 | 26 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_07_free_run_shift_reg.v: -------------------------------------------------------------------------------- 1 | // Listing 4.7 2 | module free_run_shift_reg 3 | #(parameter N=8) 4 | ( 5 | input wire clk, reset, 6 | input wire s_in, 7 | output wire s_out 8 | ); 9 | 10 | //signal declaration 11 | reg [N-1:0] r_reg; 12 | wire [N-1:0] r_next; 13 | 14 | // body 15 | // register 16 | always @(posedge clk, posedge reset) 17 | if (reset) 18 | r_reg <= 0; 19 | else 20 | r_reg <= r_next; 21 | 22 | // next-state logic 23 | assign r_next = {s_in, r_reg[N-1:1]}; 24 | // output logic 25 | assign s_out = r_reg[0]; 26 | 27 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_08_univ_shift_reg.v: -------------------------------------------------------------------------------- 1 | // Listing 4.8 2 | module univ_shift_reg 3 | #(parameter N=8) 4 | ( 5 | input wire clk, reset, 6 | input wire [1:0] ctrl, 7 | input wire [N-1:0] d, 8 | output wire [N-1:0] q 9 | ); 10 | 11 | //signal declaration 12 | reg [N-1:0] r_reg, r_next; 13 | 14 | // body 15 | // register 16 | always @(posedge clk, posedge reset) 17 | if (reset) 18 | r_reg <= 0; 19 | else 20 | r_reg <= r_next; 21 | 22 | // next-state logic 23 | always @* 24 | case(ctrl) 25 | 2'b00: r_next = r_reg; // no op 26 | 2'b01: r_next = {r_reg[N-2:0], d[0]}; // shift left 27 | 2'b10: r_next = {d[N-1], r_reg[N-1:1]}; // shift right 28 | default: r_next = d; // load 29 | endcase 30 | // output logic 31 | assign q = r_reg; 32 | 33 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_09_free_run_bin_counter.v: -------------------------------------------------------------------------------- 1 | // Listing 4.9 2 | module free_run_bin_counter 3 | #(parameter N=8) 4 | ( 5 | input wire clk, reset, 6 | output wire max_tick, 7 | output wire [N-1:0] q 8 | ); 9 | 10 | //signal declaration 11 | reg [N-1:0] r_reg; 12 | wire [N-1:0] r_next; 13 | 14 | // body 15 | // register 16 | always @(posedge clk, posedge reset) 17 | if (reset) 18 | r_reg <= 0; // {N{1b'0}} 19 | else 20 | r_reg <= r_next; 21 | 22 | // next-state logic 23 | assign r_next = r_reg + 1; 24 | // output logic 25 | assign q = r_reg; 26 | assign max_tick = (r_reg==2**N-1) ? 1'b1 : 1'b0; 27 | //can also use (r_reg=={N{1'b1}}) 28 | 29 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_10_univ_bin_counter.v: -------------------------------------------------------------------------------- 1 | // Listing 4.10 2 | module univ_bin_counter 3 | #(parameter N=8) 4 | ( 5 | input wire clk, reset, 6 | input wire syn_clr, load, en, up, 7 | input wire [N-1:0] d, 8 | output wire max_tick, min_tick, 9 | output wire [N-1:0] q 10 | ); 11 | 12 | //signal declaration 13 | reg [N-1:0] r_reg, r_next; 14 | 15 | // body 16 | // register 17 | always @(posedge clk, posedge reset) 18 | if (reset) 19 | r_reg <= 0; // 20 | else 21 | r_reg <= r_next; 22 | 23 | // next-state logic 24 | always @* 25 | if (syn_clr) 26 | r_next = 0; 27 | else if (load) 28 | r_next = d; 29 | else if (en & up) 30 | r_next = r_reg + 1; 31 | else if (en & ~up) 32 | r_next = r_reg - 1; 33 | else 34 | r_next = r_reg; 35 | 36 | // output logic 37 | assign q = r_reg; 38 | assign max_tick = (r_reg==2**N-1) ? 1'b1 : 1'b0; 39 | assign min_tick = (r_reg==0) ? 1'b1 : 1'b0; 40 | 41 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_11_mod_m_counter.v: -------------------------------------------------------------------------------- 1 | // Listing 4.11 2 | module mod_m_counter 3 | #( 4 | parameter N=4, // number of bits in counter 5 | M=10 // mod-M 6 | ) 7 | ( 8 | input wire clk, reset, 9 | output wire max_tick, 10 | output wire [N-1:0] q 11 | ); 12 | 13 | //signal declaration 14 | reg [N-1:0] r_reg; 15 | wire [N-1:0] r_next; 16 | 17 | // body 18 | // register 19 | always @(posedge clk, posedge reset) 20 | if (reset) 21 | r_reg <= 0; 22 | else 23 | r_reg <= r_next; 24 | 25 | // next-state logic 26 | assign r_next = (r_reg==(M-1)) ? 0 : r_reg + 1; 27 | // output logic 28 | assign q = r_reg; 29 | assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0; 30 | 31 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_16_hex_mux_test.v: -------------------------------------------------------------------------------- 1 | // Listing 4.16 2 | module hex_mux_test 3 | ( 4 | input wire clk, 5 | input wire [7:0] sw, 6 | output wire [3:0] an, 7 | output wire [7:0] sseg 8 | ); 9 | 10 | // signal declaration 11 | wire [3:0] a, b; 12 | wire [7:0] sum; 13 | 14 | // instantiate 7-seg LED display module 15 | disp_hex_mux disp_unit 16 | (.clk(clk), .reset(1'b0), 17 | .hex3(sum[7:4]), .hex2(sum[3:0]), .hex1(b), .hex0(a), 18 | .dp_in(4'b1011), .an(an), .sseg(sseg)); 19 | 20 | // adder 21 | assign a = sw[3:0]; 22 | assign b = sw[7:4]; 23 | assign sum = {4'b0,a} + {4'b0,b}; 24 | 25 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch04/list_ch04_19_stop_watch_test.v: -------------------------------------------------------------------------------- 1 | // Listing 4.19 2 | module stop_watch_test 3 | ( 4 | input wire clk, 5 | input wire [1:0] btn_n, 6 | output wire [3:0] an, 7 | output wire [7:0] sseg 8 | ); 9 | 10 | // signal declaration 11 | wire [3:0] d2, d1, d0; 12 | wire [1:0] btn; 13 | 14 | assign btn = ~btn_n; 15 | // instantiate 7-seg LED display module 16 | disp_hex_mux disp_unit 17 | (.clk(clk), .reset(1'b0), 18 | .hex3(4'b0), .hex2(d2), .hex1(d1), .hex0(d0), 19 | .dp_in(4'b1101), .an(an), .sseg(sseg)); 20 | 21 | // instantiate stopwatch 22 | stop_watch_if counter_unit 23 | (.clk(clk), .go(btn[1]), .clr(btn[0]), 24 | .d2(d2), .d1(d1), .d0(d0) ); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch05/ch05_07_debounce_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch05/ch05_07_debounce_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch05/list_ch05_05_edge_detect_gate.v: -------------------------------------------------------------------------------- 1 | // Listing 5.5 2 | module edge_detect_gate 3 | ( 4 | input wire clk, reset, 5 | input wire level, 6 | output wire tick 7 | ); 8 | 9 | // signal declaration 10 | reg delay_reg; 11 | 12 | // delay register 13 | always @(posedge clk, posedge reset) 14 | if (reset) 15 | delay_reg <= 1'b0; 16 | else 17 | delay_reg <= level; 18 | 19 | // decoding logic 20 | assign tick = ~delay_reg & level; 21 | 22 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch06/ch06_03_debounce_fsmd_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch06/ch06_03_debounce_fsmd_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_01_and_block.v: -------------------------------------------------------------------------------- 1 | // Listing 7.1 2 | module and_block 3 | ( 4 | input wire a, b, c, 5 | output reg y 6 | ); 7 | 8 | always @* 9 | begin 10 | y = a; 11 | y = y & b; 12 | y = y & c; 13 | end 14 | 15 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_02_and_nonblock.v: -------------------------------------------------------------------------------- 1 | // Listing 7.2 2 | module and_nonblock 3 | ( 4 | input wire a, b, c, 5 | output reg y 6 | ); 7 | 8 | always @* 9 | begin // y$_{entry}$ = y 10 | y <= a; // y$_{exit}$ = a 11 | y <= y & b; // y$_{exit}$ = y$_{entry}$ \& b 12 | y <= y & c; // y$_{exit}$ = y$_{entry}$ \& c 13 | end // y = y$_{exit}$ 14 | 15 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_03_eq1_block.v: -------------------------------------------------------------------------------- 1 | // Listing 7.3 2 | module eq1_block 3 | ( 4 | input wire i0, i1, 5 | output reg eq 6 | ); 7 | 8 | reg p0, p1; 9 | 10 | always @(i0,i1) // only i0 and i1 in sensitivity list 11 | // the order of statements is important 12 | begin 13 | p0 = ~i0 & ~i1; 14 | p1 = i0 & i1; 15 | eq = p0 | p1; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_04_eq1_non_block.v: -------------------------------------------------------------------------------- 1 | // Listing 7.4 2 | module eq1_non_block 3 | ( 4 | input wire i0, i1, 5 | output reg eq 6 | ); 7 | 8 | reg p0, p1; 9 | 10 | always @(i0,i1,p0,p1) // p0, p1 also in sensitivity list 11 | // the order of statements is not important 12 | begin // p0$_{entry}$ = p0; p1$_{entry}$ = p1; 13 | p0 <= ~i0 & ~i1; // p0$_{exit}$ = ~i0 \& ~i1; 14 | p1 <= i0 & i1; // p1$_{exit}$ = i0 \& i1 15 | eq <= p0 | p1; // eq$_{exit}$ = p0$_{entry}$ | p1$_{entry}$ 16 | end // eq = eq$_{exit}$; p0 = p0$_{exit}$; p1 = p1$_{exit}$; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_05_ab_ff_2seg.v: -------------------------------------------------------------------------------- 1 | // Listing 7.5 2 | module ab_ff_2seg 3 | ( 4 | input wire clk, 5 | input wire a, b, 6 | output reg q 7 | ); 8 | 9 | reg q_next; 10 | 11 | // D FF 12 | always @(posedge clk) 13 | q <= q_next; 14 | 15 | // combinational circuit 16 | always @* 17 | q_next = a & b; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_07_ bin_counter_merge.v: -------------------------------------------------------------------------------- 1 | // Listing 7.7 2 | module bin_counter_merge 3 | #(parameter N=8) 4 | ( 5 | input wire clk, reset, 6 | output wire max_tick, 7 | output wire [N-1:0] q 8 | ); 9 | 10 | //signal declaration 11 | reg [N-1:0] r_next, r_reg; 12 | 13 | // body 14 | // register and next-state logic 15 | always @(posedge clk, posedge reset) 16 | if (reset) 17 | r_reg <= 0; // {N{1b'0}} 18 | else 19 | begin 20 | // next-state logic 21 | r_next = r_reg + 1; 22 | // register 23 | r_reg <= r_next; 24 | end 25 | // output logic 26 | assign q = r_reg; 27 | assign max_tick = (r_reg==2**N-1) ? 1'b1 : 1'b0; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_08_ bin_counter_terse.v: -------------------------------------------------------------------------------- 1 | // Listing 7.8 2 | module bin_counter_terse 3 | #(parameter N=8) 4 | ( 5 | input wire clk, reset, 6 | output wire max_tick, 7 | output reg [N-1:0] q 8 | ); 9 | 10 | // body 11 | always @(posedge clk, posedge reset) 12 | if (reset) 13 | q <= 0; 14 | else 15 | q <= q + 1; 16 | // output logic 17 | assign max_tick = (q==2**N-1) ? 1'b1 : 1'b0; 18 | 19 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_09_univ_bin_counter_merged.v: -------------------------------------------------------------------------------- 1 | // Listing 7.9 2 | module univ_bin_counter_merged 3 | #(parameter N=8) 4 | ( 5 | input wire clk, reset, 6 | input wire syn_clr, load, en, up, 7 | input wire [N-1:0] d, 8 | output wire max_tick, min_tick, 9 | output reg [N-1:0] q 10 | ); 11 | 12 | // body 13 | // register and next-state logic 14 | always @(posedge clk, posedge reset) 15 | if (reset) 16 | q <= 0; // 17 | else if (syn_clr) 18 | q <= 0; 19 | else if (load) 20 | q <= d; 21 | else if (en & up ) 22 | q <= q + 1; 23 | else if (en & ~up ) 24 | q <= q - 1; 25 | // no else branch since q <= q is implicitly implied 26 | 27 | // output logic 28 | assign max_tick = (q==2**N-1) ? 1'b1 : 1'b0; 29 | assign min_tick = (q==0) ? 1'b1 : 1'b0; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_12_mod_m_counter_fc.v: -------------------------------------------------------------------------------- 1 | // Listing 7.12 2 | module mod_m_counter_fc 3 | #(parameter M=10) // mod-M 4 | ( 5 | input wire clk, reset, 6 | output wire max_tick, 7 | output wire [log2(M)-1:0] q 8 | ); 9 | 10 | //signal declaration 11 | localparam N = log2(M); // number of bits for M 12 | reg [N-1:0] r_reg; 13 | wire [N-1:0] r_next; 14 | 15 | // body 16 | // register 17 | always @(posedge clk, posedge reset) 18 | if (reset) 19 | r_reg <= 0; 20 | else 21 | r_reg <= r_next; 22 | 23 | // next-state logic 24 | assign r_next = (r_reg==(M-1)) ? 0 : r_reg + 1; 25 | // output logic 26 | assign q = r_reg; 27 | assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0; 28 | 29 | // log2 constant function 30 | function integer log2(input integer n); 31 | integer i; 32 | begin 33 | log2 = 1; 34 | for (i = 0; 2**i < n; i = i + 1) 35 | log2 = i + 1; 36 | end 37 | endfunction 38 | 39 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_15_eq2_task.v: -------------------------------------------------------------------------------- 1 | // Listing 7.15 2 | module eq2_task 3 | ( 4 | input wire [1:0] a, b, 5 | output reg aeqb 6 | ); 7 | 8 | reg e0, e1; 9 | 10 | always @* 11 | begin 12 | equ_tsk(2, a[0], b[0], e0); 13 | equ_tsk(2, a[1], b[1], e1); 14 | aeqb = e0 & e1; 15 | end 16 | 17 | // task definition 18 | task equ_tsk 19 | ( 20 | input integer delay, 21 | input i0, i1, 22 | output eq1 23 | ); 24 | begin 25 | #delay eq1 = (~i0 & ~i1) | (i0 & i1); 26 | end 27 | endtask 28 | 29 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_16_eq2_function.v: -------------------------------------------------------------------------------- 1 | // Listing 7.16 2 | module eq2_function 3 | ( 4 | input wire [1:0] a, b, 5 | output reg aeqb 6 | ); 7 | 8 | reg e0, e1; 9 | 10 | always @* 11 | begin 12 | #2 e0 = equ_fnc(a[0], b[0]); 13 | #2 e1 = equ_fnc(a[1], b[1]); 14 | aeqb = e0 & e1; 15 | end 16 | 17 | // function definition 18 | function equ_fnc(input i0, i1); 19 | begin 20 | equ_fnc = (~i0 & ~i1) | (i0 & i1); 21 | end 22 | endfunction 23 | 24 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_19_bin_counter_tb3.v: -------------------------------------------------------------------------------- 1 | //Listing 7.19 2 | `timescale 1 ns/10 ps 3 | 4 | module bin_counter_tb3(); 5 | 6 | // declaration 7 | localparam T=20; // clock period 8 | wire clk, reset; 9 | wire syn_clr, load, en, up; 10 | wire [2:0] d; 11 | wire max_tick, min_tick; 12 | wire [2:0] q; 13 | 14 | // uut instantiation 15 | univ_bin_counter #(.N(3)) uut 16 | (.clk(clk), .reset(reset), .syn_clr(syn_clr), 17 | .load(load), .en(en), .up(up), .d(d), 18 | .max_tick(max_tick), .min_tick(min_tick), .q(q)); 19 | 20 | // test vector generator 21 | bin_gen #(.N(3),.T(20)) gen_unit 22 | (.clk(clk), .reset(reset), .syn_clr(syn_clr), 23 | .load(load), .en(en), .up(up), .d(d)); 24 | 25 | // bin_monitor instantiation 26 | bin_monitor #(.N(3)) mon_unit 27 | (.clk(clk), .reset(reset), .syn_clr(syn_clr), 28 | .load(load), .en(en), .up(up), .d(d), 29 | .max_tick(max_tick), .min_tick(min_tick), .q(q)); 30 | 31 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_20_exp1.v: -------------------------------------------------------------------------------- 1 | // Listing 7.20 2 | module exp1 3 | ( 4 | input wire clk, 5 | input wire x0, y0, z0, 6 | output reg x3, y3, z3 7 | ); 8 | 9 | reg x1, x2, y1, y2, z1, z2; 10 | // attempt 1 11 | always @(posedge clk) 12 | begin 13 | x1 <= x0; 14 | x2 <= x1; 15 | x3 <= x2; 16 | end 17 | 18 | // attempt 2 19 | always @(posedge clk) 20 | begin 21 | y1 = y0; 22 | y2 = y1; 23 | y3 = y2; 24 | end 25 | 26 | 27 | // attempt 3 28 | always @(posedge clk) 29 | begin 30 | z1 = z0; 31 | z3 = z2; 32 | z2 = z1; 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/list_ch07_20_exp1.v.bak: -------------------------------------------------------------------------------- 1 | // Listing 7.20 2 | module exp1 3 | ( 4 | input wire clk, 5 | input wire x0, y0, z0, 6 | output reg x3, y3, z3 7 | ); 8 | 9 | reg x1, x2, y1, y2, z1, z2; 10 | // attempt 1 11 | always @(posedge clk) 12 | begin 13 | x1 <= x0; 14 | x2 <= x1; 15 | x3 <= x2; 16 | end 17 | 18 | // attempt 2 19 | always @(posedge clk) 20 | begin 21 | y1 = y0; 22 | y2 = y1; 23 | y3 = y2; 24 | end 25 | 26 | endmodule 27 | 28 | // attempt 3 29 | always @(posedge clk) 30 | begin 31 | z1 = z0; 32 | z3 = z2; 33 | z2 = z1; 34 | end -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch07/vector.txt: -------------------------------------------------------------------------------- 1 | 00_00 2 | 01_00 3 | 01_11 4 | 10_10 5 | 10_00 6 | 11_11 7 | 11_01 8 | 00_10 9 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch08/ch08_05_uart_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch08/ch08_05_uart_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch09/ch09_02_kb_monitor.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch09/ch09_02_kb_monitor.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch09/ch09_05_kb_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch09/ch09_05_kb_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch10/ch10_03_ps2_monitor.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch10/ch10_03_ps2_monitor.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch10/ch10_05_mouse_led.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch10/ch10_05_mouse_led.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch10/list_ch10_02_ps2_rxtx.v: -------------------------------------------------------------------------------- 1 | //Listing 10.2 2 | module ps2_rxtx 3 | ( 4 | input wire clk, reset, 5 | input wire wr_ps2, 6 | inout wire ps2d, ps2c, 7 | input wire [7:0] din, 8 | output wire rx_done_tick, tx_done_tick, 9 | output wire [7:0] dout 10 | ); 11 | 12 | // signal declaration 13 | wire tx_idle; 14 | 15 | // body 16 | // instantiate ps2 receiver 17 | ps2_rx ps2_rx_unit 18 | (.clk(clk), .reset(reset), .rx_en(tx_idle), 19 | .ps2d(ps2d), .ps2c(ps2c), 20 | .rx_done_tick(rx_done_tick), .dout(dout)); 21 | // instantiate ps2 transmitter 22 | ps2_tx ps2_tx_unit 23 | (.clk(clk), .reset(reset), .wr_ps2(wr_ps2), 24 | .din(din), .ps2d(ps2d), .ps2c(ps2c), 25 | .tx_idle(tx_idle), .tx_done_tick(tx_done_tick)); 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch11/readme.txt: -------------------------------------------------------------------------------- 1 | unable to run listings using SRAM: 2 | 3 | examples using the original SRAM examples cannot currently be run on the logi-edu based on the logi using a different RAM chip. Let us know if you would like us to implememnt an SRAM to SDRAM wrapper to remedy this. -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch12/list_ch12_01_xilinx_one_port_ram_async.v: -------------------------------------------------------------------------------- 1 | // Listing 12.1 2 | // Single-port RAM with asynchronous read 3 | // Modified from XST 8.1i v_rams_04 4 | 5 | module xilinx_one_port_ram_async 6 | #( 7 | parameter ADDR_WIDTH = 8, 8 | DATA_WIDTH = 1 9 | ) 10 | ( 11 | input wire clk, 12 | input wire we, 13 | input wire [ADDR_WIDTH-1:0] addr, 14 | input wire [DATA_WIDTH-1:0] din, 15 | output wire [DATA_WIDTH-1:0] dout 16 | ); 17 | 18 | // signal declaration 19 | reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; 20 | 21 | // body 22 | always @(posedge clk) 23 | if (we) // write operation 24 | ram[addr] <= din; 25 | // read operation 26 | assign dout = ram[addr]; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch12/list_ch12_02_xilinx_one_port_ram_sync.v: -------------------------------------------------------------------------------- 1 | // Listing 12.2 2 | // Single-port RAM with synchronous read 3 | // Modified from XST 8.1i v_rams_07 4 | 5 | module xilinx_one_port_ram_sync 6 | #( 7 | parameter ADDR_WIDTH = 12, 8 | DATA_WIDTH = 8 9 | ) 10 | ( 11 | input wire clk, 12 | input wire we, 13 | input wire [ADDR_WIDTH-1:0] addr, 14 | input wire [DATA_WIDTH-1:0] din, 15 | output wire [DATA_WIDTH-1:0] dout 16 | ); 17 | 18 | // signal declaration 19 | reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; 20 | reg [ADDR_WIDTH-1:0] addr_reg; 21 | 22 | // body 23 | always @(posedge clk) 24 | begin 25 | if (we) // write operation 26 | ram[addr] <= din; 27 | addr_reg <= addr; 28 | end 29 | // read operation 30 | assign dout = ram[addr_reg]; 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch12/list_ch12_03_xilinx_dual_port_ram_async.v: -------------------------------------------------------------------------------- 1 | // Listing 12.3 2 | // Dual-port RAM with asynchronous read 3 | // Modified from XST 8.1i v_rams_09 4 | 5 | module xilinx_dual_port_ram_async 6 | #( 7 | parameter ADDR_WIDTH = 6, 8 | DATA_WIDTH = 8 9 | ) 10 | ( 11 | input wire clk, 12 | input wire we, 13 | input wire [ADDR_WIDTH-1:0] addr_a, addr_b, 14 | input wire [DATA_WIDTH-1:0] din_a, 15 | output wire [DATA_WIDTH-1:0] dout_a, dout_b 16 | ); 17 | 18 | // signal declaration 19 | reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; 20 | 21 | // body 22 | always @(posedge clk) 23 | if (we) // write operation 24 | ram[addr_a] <= din_a; 25 | // two read operations 26 | assign dout_a = ram[addr_a]; 27 | assign dout_b = ram[addr_b]; 28 | 29 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch12/list_ch12_04_xilinx_dual_port_ram_sync.v: -------------------------------------------------------------------------------- 1 | // Listing 12.4 2 | // Dual-port RAM with synchronous read 3 | // Modified from XST 8.1i v_rams_11 4 | 5 | module xilinx_dual_port_ram_sync 6 | #( 7 | parameter ADDR_WIDTH = 6, 8 | DATA_WIDTH = 8 9 | ) 10 | ( 11 | input wire clk, 12 | input wire we, 13 | input wire [ADDR_WIDTH-1:0] addr_a, addr_b, 14 | input wire [DATA_WIDTH-1:0] din_a, 15 | output wire [DATA_WIDTH-1:0] dout_a, dout_b 16 | ); 17 | 18 | // signal declaration 19 | reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; 20 | reg [ADDR_WIDTH-1:0] addr_a_reg, addr_b_reg; 21 | 22 | // body 23 | always @(posedge clk) 24 | begin 25 | if (we) // write operation 26 | ram[addr_a] <= din_a; 27 | addr_a_reg <= addr_a; 28 | addr_b_reg <= addr_b; 29 | end 30 | // two read operations 31 | assign dout_a = ram[addr_a_reg]; 32 | assign dout_b = ram[addr_b_reg]; 33 | 34 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch12/list_ch12_05_rom_template.v: -------------------------------------------------------------------------------- 1 | // Listing 12.5 2 | module rom_template 3 | ( 4 | input wire [3:0] addr, 5 | output reg [7:0] data 6 | ); 7 | 8 | // body 9 | always @* 10 | case (addr) 11 | 4'h0: data = 7'b0000001; 12 | 4'h1: data = 7'b1001111; 13 | 4'h2: data = 7'b0010010; 14 | 4'h3: data = 7'b0000110; 15 | 4'h4: data = 7'b1001100; 16 | 4'h5: data = 7'b0100100; 17 | 4'h6: data = 7'b0100000; 18 | 4'h7: data = 7'b0001111; 19 | 4'h8: data = 7'b0000000; 20 | 4'h9: data = 7'b0000100; 21 | 4'ha: data = 7'b0001000; 22 | 4'hb: data = 7'b1100000; 23 | 4'hc: data = 7'b0110001; 24 | 4'hd: data = 7'b1000010; 25 | 4'he: data = 7'b0110000; 26 | 4'hf: data = 7'b0111000; 27 | endcase 28 | 29 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch12/list_ch12_06_xilinx_rom_sync_template.v: -------------------------------------------------------------------------------- 1 | // Listing 12.6 2 | module xilinx_rom_sync_template 3 | ( 4 | input wire clk, 5 | input wire [3:0] addr, 6 | output reg [7:0] data 7 | ); 8 | 9 | // signal declaration 10 | reg [3:0] addr_reg; 11 | 12 | // body 13 | always @(posedge clk) 14 | addr_reg <= addr; 15 | 16 | always @* 17 | case (addr_reg) 18 | 4'h0: data = 7'b0000001; 19 | 4'h1: data = 7'b1001111; 20 | 4'h2: data = 7'b0010010; 21 | 4'h3: data = 7'b0000110; 22 | 4'h4: data = 7'b1001100; 23 | 4'h5: data = 7'b0100100; 24 | 4'h6: data = 7'b0100000; 25 | 4'h7: data = 7'b0001111; 26 | 4'h8: data = 7'b0000000; 27 | 4'h9: data = 7'b0000100; 28 | 4'ha: data = 7'b0001000; 29 | 4'hb: data = 7'b1100000; 30 | 4'hc: data = 7'b0110001; 31 | 4'hd: data = 7'b1000010; 32 | 4'he: data = 7'b0110000; 33 | 4'hf: data = 7'b0111000; 34 | endcase 35 | 36 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch12/readme.txt: -------------------------------------------------------------------------------- 1 | unable to run listings using SRAM: 2 | 3 | examples using the original SRAM examples cannot currently be run on the logi-edu based on the logi using a different RAM chip. Let us know if you would like us to implememnt an SRAM to SDRAM wrapper to remedy this. -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch13/ch13_02_vga_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch13/ch13_02_vga_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch13/ch13_06_pong_top_an.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch13/ch13_06_pong_top_an.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch13/list_ch13_04_pong_top_st.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch13/list_ch13_04_pong_top_st.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch14/ch14_03_font_test_top.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch14/ch14_03_font_test_top.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch14/list_ch14_09_timer.v: -------------------------------------------------------------------------------- 1 | // Listing 14.9 2 | module timer 3 | ( 4 | input wire clk, reset, 5 | input wire timer_start, timer_tick, 6 | output wire timer_up 7 | ); 8 | 9 | // signal declaration 10 | reg [6:0] timer_reg, timer_next; 11 | 12 | // registers 13 | always @(posedge clk, posedge reset) 14 | if (reset) 15 | timer_reg <= 7'b1111111; 16 | else 17 | timer_reg <= timer_next; 18 | 19 | // next-state logic 20 | always @* 21 | if (timer_start) 22 | timer_next = 7'b1111111; 23 | else if ((timer_tick) && (timer_reg != 0)) 24 | timer_next = timer_reg - 1; 25 | else 26 | timer_next = timer_reg; 27 | // output 28 | assign timer_up = (timer_reg==0); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch14/list_ch14_10_pong_top.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/ch14/list_ch14_10_pong_top.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch_app/list_ch_ap_02_counter_inst.v: -------------------------------------------------------------------------------- 1 | // Listing A.2 2 | module counter_inst 3 | ( 4 | input wire clk, reset, 5 | input wire syn_clr16, load16, en16, 6 | input wire [15:0] d, 7 | output wire max_tick8, max_tick16, 8 | output wire [15:0] q 9 | ); 10 | 11 | // body 12 | // instantiation of 16-bit counter, all ports used 13 | bin_counter #(.N(16)) counter_16_unit 14 | (.clk(clk), .reset(reset), 15 | .syn_clr(syn_clr16), .load(load16), .en(en16), 16 | .d(d), .max_tick(max_tick16), .q(q)); 17 | // instantiation of free-running 8-bit counter 18 | // with only the max_tick signal 19 | bin_counter counter_8_unit 20 | (.clk(clk), .reset(reset), 21 | .syn_clr(1'b0), .load(1'b0), .en(1'b1), 22 | .d(8'h00), .max_tick(max_tick8), .q()); 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch_app/list_ch_ap_03_prio_encoder_if.v: -------------------------------------------------------------------------------- 1 | // Listing A.3 2 | module prio_encoder_if 3 | ( 4 | input wire [4:1] r, 5 | output wire [2:0] y1, 6 | output reg [2:0] y2 7 | ); 8 | 9 | // Conditional operator 10 | assign y1 = (r[4]) ? 3'b100 : // can also use (r[4]==1'b1) 11 | (r[3]) ? 3'b011 : 12 | (r[2]) ? 3'b010 : 13 | (r[1]) ? 3'b001 : 14 | 3'b000; 15 | 16 | // If statement 17 | // - each branch can contain multiple statements 18 | // with begin ... end delimiters 19 | always @* 20 | if (r[4]) 21 | y2 = 3'b100; 22 | else if (r[3]) 23 | y2 = 3'b011; 24 | else if (r[2]) 25 | y2 = 3'b010; 26 | else if (r[1]) 27 | y2 = 3'b001; 28 | else 29 | y2 = 3'b000; 30 | 31 | endmodule -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch_app/list_ch_ap_05_compare_no_defult.v: -------------------------------------------------------------------------------- 1 | // Listing A.5 2 | module compare_no_defult 3 | ( 4 | input wire a, b, 5 | output reg gt, eq 6 | ); 7 | 8 | // - use @* to include all inputs in sensitivity list 9 | // - else branch cannot be omitted 10 | // - all outputs must be assigned in all branches 11 | always @* 12 | if (a > b) 13 | begin 14 | gt = 1'b1; 15 | eq = 1'b0; 16 | end 17 | else if (a == b) 18 | begin 19 | gt = 1'b0; 20 | eq = 1'b1; 21 | end 22 | else // else branch cannot be omitted 23 | begin 24 | gt = 1'b0; 25 | eq = 1'b0; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch_app/list_ch_ap_06_compare_with_default.v: -------------------------------------------------------------------------------- 1 | // Listing A.6 2 | module compare_with_default 3 | ( 4 | input wire a, b, 5 | output reg gt, eq 6 | ); 7 | 8 | // - use @* to include all inputs in sensitivity list 9 | // - assign each output with a default value 10 | always @* 11 | begin 12 | gt = 1'b0; // default value for gt 13 | eq = 1'b0; // default value for eq 14 | if (a > b) 15 | gt = 1'b1; 16 | else if (a == b) 17 | eq = 1'b1; 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/ch_app/list_ch_ap_08_reg_file.v: -------------------------------------------------------------------------------- 1 | // Listing A.8 2 | module reg_file 3 | #( 4 | parameter B = 8, // number of bits 5 | W = 2 // number of address bits 6 | ) 7 | ( 8 | input wire clk, 9 | input wire wr_en, 10 | input wire [W-1:0] w_addr, r_addr, 11 | input wire [B-1:0] w_data, 12 | output wire [B-1:0] r_data 13 | ); 14 | 15 | // signal declaration 16 | reg [B-1:0] array_reg [2**W-1:0]; 17 | 18 | // body 19 | // write operation 20 | always @(posedge clk) 21 | if (wr_en) 22 | array_reg[w_addr] <= w_data; 23 | // read operation 24 | assign r_data = array_reg[r_addr]; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/original_vlog_src.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/original_vlog_src.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_SE_dual_edge_mealy.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_SE_dual_edge_mealy.png -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_SE_dual_edge_mealy.vsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_SE_dual_edge_mealy.vsd -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_SE_dual_edge_moore.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_SE_dual_edge_moore.png -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_SE_dual_edge_moore.vsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_SE_dual_edge_moore.vsd -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_db_fsm.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_db_fsm.png -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_db_fsm.vsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_db_fsm.vsd -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_db_fsm_SE_1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_db_fsm_SE_1.png -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_db_fsm_SE_1.vsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-verilog/visio/ch05/ch05_db_fsm_SE_1.vsd -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/PongChu_fpga_VHDL_src_original.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/PongChu_fpga_VHDL_src_original.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch01/list_ch01_01_eq1.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 1.1 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity eq1 is 5 | port( 6 | i0, i1: in std_logic; 7 | eq: out std_logic 8 | ); 9 | end eq1; 10 | 11 | architecture sop_arch of eq1 is 12 | signal p0, p1: std_logic; 13 | begin 14 | -- sum of two product terms 15 | eq <= p0 or p1; 16 | -- product terms 17 | p0 <= (not i0) and (not i1); 18 | p1 <= i0 and i1; 19 | end sop_arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch02/list_ch02_01_eq1.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 2.1 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity eq1 is 5 | port( 6 | i0, i1: in std_logic; 7 | eq: out std_logic 8 | ); 9 | end eq1; 10 | 11 | architecture sop_arch of eq1 is 12 | signal p0, p1: std_logic; 13 | begin 14 | -- sum of two product terms 15 | eq <= p0 or p1; 16 | -- product terms 17 | p0 <= (not i0) and (not i1); 18 | p1 <= i0 and i1; 19 | end sop_arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch02/list_ch02_02_eq2.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 2.2 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity eq2 is 5 | port( 6 | a, b: in std_logic_vector(1 downto 0); 7 | aeqb: out std_logic 8 | ); 9 | end eq2; 10 | 11 | architecture struc_arch of eq2 is 12 | signal e0, e1: std_logic; 13 | begin 14 | -- instantiate two 1-bit comparators 15 | eq_bit0_unit: entity work.eq1(sop_arch) 16 | port map(i0=>a(0), i1=>b(0), eq=>e0); 17 | eq_bit1_unit: entity work.eq1(sop_arch) 18 | port map(i0=>a(1), i1=>b(1), eq=>e1); 19 | -- a and b are equal if individual bits are equal 20 | aeqb <= e0 and e1; 21 | end struc_arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/ch3_13_hex_to_sseg_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/ch3_13_hex_to_sseg_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/list_ch03_09_10_add.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 3.9 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | entity add_w_carry is 6 | port( 7 | a, b: in std_logic_vector(3 downto 0); 8 | cout: out std_logic; 9 | sum: out std_logic_vector(3 downto 0) 10 | ); 11 | end add_w_carry; 12 | 13 | architecture hard_arch of add_w_carry is 14 | signal a_ext, b_ext, sum_ext: unsigned(4 downto 0); 15 | begin 16 | a_ext <= unsigned('0' & a); 17 | b_ext <= unsigned('0' & b); 18 | sum_ext <= a_ext + b_ext; 19 | sum <= std_logic_vector(sum_ext(3 downto 0)); 20 | cout <= sum_ext(4); 21 | end hard_arch; 22 | 23 | -- Listing 3.10 24 | architecture const_arch of add_w_carry is 25 | constant N: integer := 4; 26 | signal a_ext, b_ext, sum_ext: unsigned(N downto 0); 27 | begin 28 | a_ext <= unsigned('0' & a); 29 | b_ext <= unsigned('0' & b); 30 | sum_ext <= a_ext + b_ext; 31 | sum <= std_logic_vector(sum_ext(N-1 downto 0)); 32 | cout <= sum_ext(N); 33 | end const_arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/list_ch03_11_gen_add.vhd: -------------------------------------------------------------------------------- 1 | --Listing 3.11 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | entity gen_add_w_carry is 6 | generic(N: integer:=4); 7 | port( 8 | a, b: in std_logic_vector(N-1 downto 0); 9 | cout: out std_logic; 10 | sum: out std_logic_vector(N-1 downto 0) 11 | ); 12 | end gen_add_w_carry; 13 | 14 | architecture arch of gen_add_w_carry is 15 | signal a_ext, b_ext, sum_ext: unsigned(N downto 0); 16 | begin 17 | a_ext <= unsigned('0' & a); 18 | b_ext <= unsigned('0' & b); 19 | sum_ext <= a_ext + b_ext; 20 | sum <= std_logic_vector(sum_ext(N-1 downto 0)); 21 | cout <= sum_ext(N); 22 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/list_ch03_18_shift_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/list_ch03_18_shift_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/list_ch03_20_fp_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/list_ch03_20_fp_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/list_ch3_15_smadd_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch03/list_ch3_15_smadd_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/ch04_21_fifo_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/ch04_21_fifo_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/ch4_14_disp_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/ch4_14_disp_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/ch4_16_disp_hex_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/ch4_16_disp_hex_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/ch4_19_watch_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/ch4_19_watch_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/list_ch04_01_dff.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 4.1 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity d_ff is 5 | port( 6 | clk: in std_logic; 7 | d: in std_logic; 8 | q: out std_logic 9 | ); 10 | end d_ff; 11 | 12 | architecture arch of d_ff is 13 | begin 14 | process(clk) 15 | begin 16 | if (clk'event and clk='1') then 17 | q <= d; 18 | end if; 19 | end process; 20 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/list_ch04_02_dffr.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 4.2 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity d_ff_reset is 5 | port( 6 | clk, reset: in std_logic; 7 | d: in std_logic; 8 | q: out std_logic 9 | ); 10 | end d_ff_reset; 11 | 12 | architecture arch of d_ff_reset is 13 | begin 14 | process(clk,reset) 15 | begin 16 | if (reset='1') then 17 | q <='0'; 18 | elsif (clk'event and clk='1') then 19 | q <= d; 20 | end if; 21 | end process; 22 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/list_ch04_05_reg.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 4.5 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity reg_reset is 5 | port( 6 | clk, reset: in std_logic; 7 | d: in std_logic_vector(7 downto 0); 8 | q: out std_logic_vector(7 downto 0) 9 | ); 10 | end reg_reset; 11 | 12 | architecture arch of reg_reset is 13 | begin 14 | process(clk,reset) 15 | begin 16 | if (reset='1') then 17 | q <=(others=>'0'); 18 | elsif (clk'event and clk='1') then 19 | q <= d; 20 | end if; 21 | end process; 22 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/list_ch04_07_shift.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 4.7 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity free_run_shift_reg is 5 | generic(N: integer := 8); 6 | port( 7 | clk, reset: in std_logic; 8 | s_in: in std_logic; 9 | s_out: out std_logic 10 | ); 11 | end free_run_shift_reg; 12 | 13 | architecture arch of free_run_shift_reg is 14 | signal r_reg: std_logic_vector(N-1 downto 0); 15 | signal r_next: std_logic_vector(N-1 downto 0); 16 | begin 17 | -- register 18 | process(clk,reset) 19 | begin 20 | if (reset='1') then 21 | r_reg <= (others=>'0'); 22 | elsif (clk'event and clk='1') then 23 | r_reg <= r_next; 24 | end if; 25 | end process; 26 | -- next-state logic (shift right 1 bit) 27 | r_next <= s_in & r_reg(N-1 downto 1); 28 | -- output 29 | s_out <= r_reg(0); 30 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/list_ch04_09_bin.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 4.9 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | entity free_run_bin_counter is 6 | generic(N: integer := 8); 7 | port( 8 | clk, reset: in std_logic; 9 | max_tick: out std_logic; 10 | q: out std_logic_vector(N-1 downto 0) 11 | ); 12 | end free_run_bin_counter; 13 | 14 | architecture arch of free_run_bin_counter is 15 | signal r_reg: unsigned(N-1 downto 0); 16 | signal r_next: unsigned(N-1 downto 0); 17 | begin 18 | -- register 19 | process(clk,reset) 20 | begin 21 | if (reset='1') then 22 | r_reg <= (others=>'0'); 23 | elsif (clk'event and clk='1') then 24 | r_reg <= r_next; 25 | end if; 26 | end process; 27 | -- next-state logic 28 | r_next <= r_reg + 1; 29 | -- output logic 30 | q <= std_logic_vector(r_reg); 31 | max_tick <= '1' when r_reg=(2**N-1) else '0'; 32 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/list_ch04_11_mod_m.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 4.11 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | entity mod_m_counter is 6 | generic( 7 | N: integer := 4; -- number of bits 8 | M: integer := 10 -- mod-M 9 | ); 10 | port( 11 | clk, reset: in std_logic; 12 | max_tick: out std_logic; 13 | q: out std_logic_vector(N-1 downto 0) 14 | ); 15 | end mod_m_counter; 16 | 17 | architecture arch of mod_m_counter is 18 | signal r_reg: unsigned(N-1 downto 0); 19 | signal r_next: unsigned(N-1 downto 0); 20 | begin 21 | -- register 22 | process(clk,reset) 23 | begin 24 | if (reset='1') then 25 | r_reg <= (others=>'0'); 26 | elsif (clk'event and clk='1') then 27 | r_reg <= r_next; 28 | end if; 29 | end process; 30 | -- next-state logic 31 | r_next <= (others=>'0') when r_reg=(M-1) else 32 | r_reg + 1; 33 | -- output logic 34 | q <= std_logic_vector(r_reg); 35 | max_tick <= '1' when r_reg=(M-1) else '0'; 36 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch04/list_ch04_19_watch_test.vhd: -------------------------------------------------------------------------------- 1 | --Listing 4.19 2 | -- notes to run on logi: 3 | -- * btn(0) = reset the timers, btn(1) enables the timer to count. 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | entity stop_watch_test is 7 | port( 8 | clk: in std_logic; 9 | btn_n: in std_logic_vector(1 downto 0); 10 | an: out std_logic_vector(3 downto 0); 11 | sseg: out std_logic_vector(7 downto 0) 12 | ); 13 | end stop_watch_test; 14 | 15 | architecture arch of stop_watch_test is 16 | signal d2, d1, d0: std_logic_vector(3 downto 0); 17 | signal btn: std_logic_vector(1 downto 0); 18 | begin 19 | 20 | btn <= not(btn_n); 21 | 22 | disp_unit: entity work.disp_hex_mux 23 | port map( 24 | clk=>clk, reset=>'0', 25 | hex3=>"0000", hex2=>d2, 26 | hex1=>d1, hex0=>d0, 27 | dp_in=>"1101", an=>an, sseg=>sseg); 28 | 29 | watch_unit: entity work.stop_watch(cascade_arch) 30 | port map( 31 | clk=>clk, go=>btn(1), clr=>btn(0), 32 | d2 =>d2, d1=>d1, d0=>d0 ); 33 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch05/ch5_7_debounce_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch05/ch5_7_debounce_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch06/ch6_3_db_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch06/ch6_3_db_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch07/ch07_uart_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch07/ch07_uart_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch08/ch08_02_kb_mon.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch08/ch08_02_kb_mon.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch08/ch08_5_kb_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch08/ch08_5_kb_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch09/ch09_05_mouse_led.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch09/ch09_05_mouse_led.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch09/ch09_3_ps2_monitor.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch09/ch09_3_ps2_monitor.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch09/list_ch09_02_ps2_rxtx.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 9.2 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity ps2_rxtx is 5 | port ( 6 | clk, reset: in std_logic; 7 | wr_ps2: std_logic; 8 | din: in std_logic_vector(7 downto 0); 9 | dout: out std_logic_vector(7 downto 0); 10 | rx_done_tick: out std_logic; 11 | tx_done_tick: out std_logic; 12 | ps2d, ps2c: inout std_logic 13 | ); 14 | end ps2_rxtx; 15 | 16 | architecture arch of ps2_rxtx is 17 | signal tx_idle: std_logic; 18 | begin 19 | ps2_tx_unit: entity work.ps2_tx(arch) 20 | port map(clk=>clk, reset=>reset, wr_ps2=>wr_ps2, 21 | din=>din, ps2d=>ps2d, ps2c=>ps2c, 22 | tx_idle=>tx_idle, tx_done_tick=>tx_done_tick); 23 | ps2_rx_unit: entity work.ps2_rx(arch) 24 | port map(clk=>clk, reset=>reset, rx_en=>tx_idle, 25 | ps2d=>ps2d, ps2c=>ps2c, 26 | rx_done_tick=>rx_done_tick, dout=>dout); 27 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch10/readme.txt: -------------------------------------------------------------------------------- 1 | unable to run listings using SRAM: 2 | 3 | examples using the original SRAM examples cannot currently be run on the logi-edu based on the logi using a different RAM chip. Let us know if you would like us to implememnt an SRAM to SDRAM wrapper to remedy this. -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch11/readme.txt: -------------------------------------------------------------------------------- 1 | unable to run listings using SRAM: 2 | 3 | examples using the original SRAM examples cannot currently be run on the logi-edu based on the logi using a different RAM chip. Let us know if you would like us to implememnt an SRAM to SDRAM wrapper to remedy this. -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch12/ch12_02_vga_sync_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch12/ch12_02_vga_sync_test.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch12/ch12_02_vga_sync_test/vga_test_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=E:\Dropbox\Prj\Valent\LOGI-FAMILY\1logi-github\private\Logi-projects\New-book-example\logi-pi-edu\vhdl\pong-chu-mark1-examples-vhdl\ch12\ch12_02_vga_sync_test\vga_test.ncd 3 | OUTFILE=E:\Dropbox\Prj\Valent\LOGI-FAMILY\1logi-github\private\Logi-projects\New-book-example\logi-pi-edu\vhdl\pong-chu-mark1-examples-vhdl\ch12\ch12_02_vga_sync_test\vga_test.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx9-2tqg144 6 | WORKINGDIR=E:\Dropbox\Prj\Valent\LOGI-FAMILY\1logi-github\private\Logi-projects\New-book-example\logi-pi-edu\vhdl\pong-chu-mark1-examples-vhdl\ch12\ch12_02_vga_sync_test 7 | LICENSE=WebPack 8 | USER_INFO=202672454_0_0_477 9 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch12/ch12_04_pong_top_st.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch12/ch12_04_pong_top_st.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch12/ch12_06_pong_top_an.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch12/ch12_06_pong_top_an.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch12/readme.txt: -------------------------------------------------------------------------------- 1 | unable to run listings using SRAM: 2 | 3 | examples using the original SRAM examples cannot currently be run on the logi-edu based on the logi using a different RAM chip. Let us know if you would like us to implememnt an SRAM to SDRAM wrapper to remedy this. -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch13/ch13_03_font_test_top.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch13/ch13_03_font_test_top.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch13/list_ch13_10_pong_top.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/book-example-code/pong-chu-logi-edu-examples-vhdl/ch13/list_ch13_10_pong_top.zip -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch13/readme.txt: -------------------------------------------------------------------------------- 1 | unable to run listings: 2 | list_ch13_05_text_scr_top cannot currently be run on the logi-edu based on the logi using a different RAM interface. -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch_appendix/list_ch_app_a03.vhd: -------------------------------------------------------------------------------- 1 | --********************************************* 2 | -- Listing A.3 3 | --********************************************* 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | use ieee.numeric_std.all; 7 | entity arith_demo is 8 | port( 9 | a, b: in std_logic_vector(7 downto 0); 10 | diff, inc: out std_logic_vector(7 downto 0) 11 | ); 12 | end arith_demo; 13 | 14 | architecture arch of arith_demo is 15 | signal au, bu, diffu: unsigned(7 downto 0); 16 | begin 17 | -- convert inputs to unigned/sgined internally and 18 | -- then convert the result back 19 | au <= unsigned(a); 20 | bu <= unsigned(b); 21 | diffu <= au - bu when (au > bu) else 22 | bu - au; 23 | diff <= std_logic_vector(diffu); 24 | -- convert multiple times in a statement 25 | inc <= std_logic_vector(unsigned(a) + 1); 26 | end arch; 27 | 28 | -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch_appendix/list_ch_app_a04.vhd: -------------------------------------------------------------------------------- 1 | --********************************************* 2 | -- Listing A.4 3 | --********************************************* 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | entity fixed_shift_demo is 7 | port( 8 | a: in std_logic_vector(7 downto 0); 9 | sh1, sh2, sh3, rot, swap: out 10 | std_logic_vector(7 downto 0) 11 | ); 12 | end fixed_shift_demo; 13 | 14 | architecture arch of fixed_shift_demo is 15 | begin 16 | -- shift left 3 positions 17 | sh1 <= a(4 downto 0) & "000" ; 18 | -- shift right 3 positions (logical shift) 19 | sh2 <= "000" & a(7 downto 3); 20 | -- shift right 3 positions and shifting in sign bit 21 | -- (arithematic shift) 22 | sh3 <= a(7) & a(7) & a(7)& a(7 downto 3); 23 | -- rotate right 3 positions 24 | rot <= a(2 downto 0) & a(7 downto 3); 25 | -- swap two nibbles 26 | swap <= a(3 downto 0) & a(7 downto 4); 27 | end arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/ch_appendix/list_ch_app_a05.vhd: -------------------------------------------------------------------------------- 1 | --********************************************* 2 | -- Listing A.5 3 | --********************************************* 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | entity decoder1 is 7 | port( 8 | a: in std_logic_vector(1 downto 0); 9 | en: in std_logic; 10 | y1, y2: out std_logic_vector(3 downto 0) 11 | ); 12 | end decoder1; 13 | 14 | architecture concurrent_arch of decoder1 is 15 | signal s: std_logic_vector(2 downto 0); 16 | begin 17 | -- conditional signal assignment statement 18 | y1 <= "0000" when (en='0') else 19 | "0001" when (a="00") else 20 | "0010" when (a="01") else 21 | "0100" when (a="10") else 22 | "1000"; -- a="11" 23 | 24 | -- selected signal assignment statement 25 | s <= en & a; 26 | with s select 27 | y2 <= "0000" when "000"|"001"|"010"|"011", 28 | "0001" when "100", 29 | "0010" when "101", 30 | "0100" when "110", 31 | "1000" when others; -- s="111" 32 | end concurrent_arch; -------------------------------------------------------------------------------- /book-example-code/pong-chu-logi-edu-examples-vhdl/visio/ch05/ch05_SE_dual_edge_mealy.png: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /cheapscope-hamster/sw/readme.txt: -------------------------------------------------------------------------------- 1 | Cheapscope Setup: 2 | 3 | - install libncurses: sudo apt-get install libncurses5-dev 4 | - build cheapscope: gcc -o cheapscope cheapscope.c -lncurses 5 | - ensure that rpi ttyAMA0 is not being used by system (used by default): 6 | 7 | - Easy utility to all user access to serial port 8 | - install using: 9 | sudo wget https://raw.github.com/lurch/rpi-serial-console/master/rpi-serial-console -O /usr/bin/rpi-serial-console && sudo chmod +x /usr/bin/rpi-serial-console 10 | - if already installed: 11 | cp rpi-serial-console /usr/bin/rpi-serial-console && sudo chmod +x /usr/bin/rpi-serial-console 12 | 13 | - Check the status: rpi-serial-console status 14 | - if enabled user must disable the ttyama0 port(make available for user access): sudo rpi-serial-console disable 15 | - reboot 16 | - run the cheapscope: ./cheapscope /dev/ttyAMA0 17 | 18 | -------------------------------------------------------------------------------- /doc/1bit_counter.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/doc/1bit_counter.png -------------------------------------------------------------------------------- /doc/eight_bit_stage.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/doc/eight_bit_stage.png -------------------------------------------------------------------------------- /doc/fpga_struct.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/doc/fpga_struct.png -------------------------------------------------------------------------------- /logi-bitcoin-miner/Open-Source-FPGA-Bitcoin-Miner-master/.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.swp 3 | db 4 | incremental_db 5 | work 6 | quartus_output 7 | PLLJ_PLLSPE_INFO.txt 8 | *.cr.mti 9 | vsim.wlf 10 | transcript 11 | webtalk.log 12 | webtalk_impact.xml 13 | usage_statistics_webtalk.html 14 | impact.xsl 15 | impact_impact.xwbt -------------------------------------------------------------------------------- /logi-bitcoin-miner/Open-Source-FPGA-Bitcoin-Miner-master/projects/VHDL_Xilinx_Port/README.md: -------------------------------------------------------------------------------- 1 | This is a re-implementation done by TheSeven (http://forum.bitcoin.org/index.php?action=profile;u=15929). 2 | 3 | Features: 4 | * Re-implemented as VHDL. 5 | * Uses RS232 for communication with PC. 6 | * Compatible with ISE and Xilinx devices. 7 | * Python scripts act as the controller on the PC. 8 | 9 | Currently no project file or device specific configuration is included. (TODO) 10 | 11 | 12 | If you found this code useful, please feel free to donate to TheSeven: 13 | 14Jc8vWq1mPv7vWnP5VquZZgpLEtzW2vja 14 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/Open-Source-FPGA-Bitcoin-Miner-master/projects/VHDL_Xilinx_Port/config.py: -------------------------------------------------------------------------------- 1 | fpgaport = "/dev/ttyUSB0" 2 | pools = [ \ 3 | { 4 | "name": "bitlc", \ 5 | "servers": [ \ 6 | {"host": "pool.bitlc.net", "port": 80}, \ 7 | ], \ 8 | "username": "hwNBwG", \ 9 | "password": "prYxXy", \ 10 | }, \ 11 | ] 12 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/Open-Source-FPGA-Bitcoin-Miner-master/.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.swp 3 | db 4 | incremental_db 5 | work 6 | quartus_output 7 | PLLJ_PLLSPE_INFO.txt 8 | *.cr.mti 9 | vsim.wlf 10 | transcript 11 | webtalk.log 12 | webtalk_impact.xml 13 | usage_statistics_webtalk.html 14 | impact.xsl 15 | impact_impact.xwbt -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/Open-Source-FPGA-Bitcoin-Miner-master/projects/VHDL_Xilinx_Port/README.md: -------------------------------------------------------------------------------- 1 | This is a re-implementation done by TheSeven (http://forum.bitcoin.org/index.php?action=profile;u=15929). 2 | 3 | Features: 4 | * Re-implemented as VHDL. 5 | * Uses RS232 for communication with PC. 6 | * Compatible with ISE and Xilinx devices. 7 | * Python scripts act as the controller on the PC. 8 | 9 | Currently no project file or device specific configuration is included. (TODO) 10 | 11 | 12 | If you found this code useful, please feel free to donate to TheSeven: 13 | 14Jc8vWq1mPv7vWnP5VquZZgpLEtzW2vja 14 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/Open-Source-FPGA-Bitcoin-Miner-master/projects/VHDL_Xilinx_Port/config.py: -------------------------------------------------------------------------------- 1 | fpgaport = "/dev/ttyUSB0" 2 | pools = [ \ 3 | { 4 | "name": "bitlc", \ 5 | "servers": [ \ 6 | {"host": "pool.bitlc.net", "port": 80}, \ 7 | ], \ 8 | "username": "hwNBwG", \ 9 | "password": "prYxXy", \ 10 | }, \ 11 | ] 12 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clock_gen 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | LINE Normal 608 976 576 976 18 | PIN 608 976 RIGHT 36 19 | PINATTR PinName locked 20 | PINATTR Polarity OUT 21 | 22 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen.ncf -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt MIXED 3 | -top clock_gen_exdes 4 | -p xc6slx9-tqg144-2 5 | -ifn xst.prj 6 | -ofn clock_gen_exdes 7 | -keep_hierarchy soft 8 | -equivalent_register_removal no 9 | -max_fanout 65535 10 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- 1 | COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", 2 | SCOPE = :dut; 3 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | 10 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | 2 | run 50000ns 3 | quit 4 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/clock_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logibone-hw/logibone_mining.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=NO 4 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clock_gen 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | LINE Normal 608 272 576 272 18 | PIN 608 272 RIGHT 36 19 | PINATTR PinName clk_out3 20 | PINATTR Polarity OUT 21 | LINE Normal 608 976 576 976 22 | PIN 608 976 RIGHT 36 23 | PINATTR PinName locked 24 | PINATTR Polarity OUT 25 | 26 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt MIXED 3 | -top clock_gen_exdes 4 | -p xc6slx9-tqg144-2 5 | -ifn xst.prj 6 | -ofn clock_gen_exdes 7 | -keep_hierarchy soft 8 | -equivalent_register_removal no 9 | -max_fanout 65535 10 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- 1 | COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", 2 | SCOPE = :dut; 3 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | 10 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | 2 | run 50000ns 3 | quit 4 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/clock_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/logipi-hw/logipi_mining.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=NO 4 | -------------------------------------------------------------------------------- /logi-bitcoin-miner/sw/config.py: -------------------------------------------------------------------------------- 1 | pools = [ \ 2 | { 3 | "name": "btcguild", \ 4 | "servers": [ \ 5 | {"host": "btcguild.com", "port": 8332}, \ 6 | ], \ 7 | "username": "USERNAME", \ 8 | "password": "PASSWORD", \ 9 | }, \ 10 | ] 11 | -------------------------------------------------------------------------------- /logi-blink-led/README.TXT: -------------------------------------------------------------------------------- 1 | Blink LED Project ************************************************************************* 2 | * DOCUMENTATION: http://valentfx.com/wiki/index.php?title=LOGI_-_LED_Blink_-_Project 3 | * DESCRIPTION ************** 4 | This is a "hello world" demo for the LOGI FPGA. This shows the functioning nuts and bolts of the Pi/Bone and LOGI FPGA. A bitstream is loaded using the logi_loader and the FPGA begins to run: 2xLED should turn on and off. 5 | * INSTRUCTIONS ************* 6 | Generate Programming File using Xilinx ISE open: File | New Project | logi-blink-led/hw/logipi/ise/logipi-hw.xise 7 | * TROUBLESHOOTING ********** 8 | 9 | * SUGGESTIONS ************** 10 | 11 | ************************************************************************************* 12 | -------------------------------------------------------------------------------- /logi-blink-led/bitfiles/logibone_r1_blink.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-blink-led/bitfiles/logibone_r1_blink.bit -------------------------------------------------------------------------------- /logi-blink-led/doc/arch_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-blink-led/doc/arch_diagram.png -------------------------------------------------------------------------------- /logi-blink-led/hw/logibone/hdl/logibone_blink_R1.ucf: -------------------------------------------------------------------------------- 1 | ###################################################### 2 | ###################################################### 3 | ## UCF Constraints file ## 4 | ###################################################### 5 | ###################################################### 6 | 7 | ###################### 8 | # Timing Constraints # 9 | ###################### 10 | 11 | ##### Grouping Constraints ##### 12 | NET OSC_FPGA TNM_NET = clk50_grp; 13 | 14 | ##### Clock Period Constraints ##### 15 | TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns; 16 | 17 | ####################### 18 | # Pin LOC Constraints # 19 | ###################### 20 | 21 | NET LED<0> LOC = "P140" ; 22 | NET LED<1> LOC = "P74" ; 23 | NET OSC_FPGA LOC = "P85" ; 24 | 25 | -------------------------------------------------------------------------------- /logi-blink-led/hw/logibone/hdl/logibone_blink_RA2.ucf: -------------------------------------------------------------------------------- 1 | ###################################################### 2 | ###################################################### 3 | ## These constraints are for Mark-1 RPI/FPGA shield ## 4 | ###################################################### 5 | ###################################################### 6 | 7 | ###################### 8 | # Timing Constraints # 9 | ###################### 10 | 11 | ##### Grouping Constraints ##### 12 | NET OSC_FPGA TNM_NET = clk50_grp; 13 | 14 | ##### Clock Period Constraints ##### 15 | TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns; 16 | 17 | ####################### 18 | # Pin LOC Constraints # 19 | ###################### 20 | 21 | NET "ARD_SCL" LOC = "P87" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; 22 | NET "ARD_SDA" LOC = "P88" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; 23 | ##### Bank 2 ##### 24 | #NET SHIELD_RST LOC = "P40" ;# IO_L64N_D9_2 25 | NET LED<0> LOC = "P62" ;# IO_L64P_D8_2 26 | NET LED<1> LOC = "P74" ;# IO_L62N_D6_2 27 | NET OSC_FPGA LOC = "P92" ;# IO_L30N_GCLK0_USERCCLK_2 28 | 29 | -------------------------------------------------------------------------------- /logi-blink-led/hw/logibone/hdl/logibone_ra1_blink.ucf: -------------------------------------------------------------------------------- 1 | ###################################################### 2 | ###################################################### 3 | ## These constraints are for Mark-1 RPI/FPGA shield ## 4 | ###################################################### 5 | ###################################################### 6 | 7 | ###################### 8 | # Timing Constraints # 9 | ###################### 10 | 11 | ##### Grouping Constraints ##### 12 | NET OSC_FPGA TNM_NET = clk50_grp; 13 | 14 | ##### Clock Period Constraints ##### 15 | TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns; 16 | 17 | ####################### 18 | # Pin LOC Constraints # 19 | ###################### 20 | 21 | ##### Bank 2 ##### 22 | NET "LED[0]" IOSTANDARD = LVTTL; 23 | NET "LED[0]" DRIVE = 2; 24 | NET "LED[0]" SLEW = SLOW; 25 | NET "LED[0]" LOC = P55; 26 | # 27 | NET "LED[1]" IOSTANDARD = LVTTL; 28 | NET "LED[1]" DRIVE = 2; 29 | NET "LED[1]" SLEW = SLOW; 30 | NET "LED[1]" LOC = P93; 31 | NET "OSC_FPGA" LOC = P92; 32 | 33 | -------------------------------------------------------------------------------- /logi-blink-led/hw/logibone/hdl/logibone_ra2_blink.ucf: -------------------------------------------------------------------------------- 1 | ###################################################### 2 | ###################################################### 3 | ## These constraints are for Mark-1 RPI/FPGA shield ## 4 | ###################################################### 5 | ###################################################### 6 | 7 | ###################### 8 | # Timing Constraints # 9 | ###################### 10 | 11 | ##### Grouping Constraints ##### 12 | NET OSC_FPGA TNM_NET = clk50_grp; 13 | 14 | ##### Clock Period Constraints ##### 15 | TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns; 16 | 17 | ####################### 18 | # Pin LOC Constraints # 19 | ###################### 20 | 21 | ##### Bank 2 ##### 22 | #NET SHIELD_RST LOC = "P40" ;# IO_L64N_D9_2 23 | NET LED<0> LOC = "P62" ;# IO_L64P_D8_2 24 | NET LED<1> LOC = "P74" ;# IO_L62N_D6_2 25 | NET OSC_FPGA LOC = "P92" ;# IO_L30N_GCLK0_USERCCLK_2 26 | 27 | -------------------------------------------------------------------------------- /logi-blink-led/hw/logipi/hdl/logipi_blink_R1.ucf: -------------------------------------------------------------------------------- 1 | ###################################################### 2 | ###################################################### 3 | ## These constraints are for Mark-1 RPI/FPGA shield ## 4 | ###################################################### 5 | ###################################################### 6 | 7 | ###################### 8 | # Timing Constraints # 9 | ###################### 10 | 11 | ##### Grouping Constraints ##### 12 | NET OSC_FPGA TNM_NET = clk50_grp; 13 | 14 | ##### Clock Period Constraints ##### 15 | TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns; 16 | 17 | ####################### 18 | # Pin LOC Constraints # 19 | ###################### 20 | 21 | ##### Bank 2 ##### 22 | NET "LED<0>" LOC = "P105" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D6 23 | NET "LED<1>" LOC = "P104" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D7 24 | NET "OSC_FPGA" LOC = "P85" | IOSTANDARD = LVTTL; 25 | 26 | -------------------------------------------------------------------------------- /logi-camera-bin/sw/grab_from_cam/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | C_FLAGS = -I/home/debian/logi-tools/c 3 | LD_FLAGS = -lc -ljpeg -L/home/debian/logi-tools/c -llogi 4 | 5 | all: grab 6 | 7 | clean: 8 | rm -f *.a *.o grab 9 | 10 | grab : grab.c jpeg_func.c 11 | $(CC) $(C_FLAGS) -o $@ grab.c jpeg_func.c $(LD_FLAGS) 12 | 13 | -------------------------------------------------------------------------------- /logi-camera-bin/sw/grab_from_cam/config.h: -------------------------------------------------------------------------------- 1 | 2 | #define FIFO_ADDR 0x0000 3 | #define FIFO_CMD_OFFSET 0x0200 4 | #define FIFO_SIZE_OFFSET 0x0200 5 | #define FIFO_AVAILABLE_OFFSET 0x0202 6 | 7 | 8 | -------------------------------------------------------------------------------- /logi-camera-bin/sw/grab_from_cam/grab: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-camera-bin/sw/grab_from_cam/grab -------------------------------------------------------------------------------- /logi-camera-bin/sw/grab_from_cam/grab_web.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | sudo ./grab 4 | sudo cp grabbed_frame0000.jpg /var/www/html/ 5 | -------------------------------------------------------------------------------- /logi-camera-bin/sw/grab_from_cam/grabbed_frame0000.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-camera-bin/sw/grab_from_cam/grabbed_frame0000.jpg -------------------------------------------------------------------------------- /logi-camera-bin/sw/grab_from_cam/grabbed_frame0000.yuv: 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-------------------------------------------------------------------------------- 1 | 2 | CC = gcc 3 | CFLAGS = -I/home/debian/logi-tools/c 4 | LFLAGS = -llogi 5 | 6 | 7 | all : sensor_conf 8 | 9 | clean : 10 | rm *.o sensor_conf 11 | 12 | sensor_conf : sensor_conf.o 13 | $(CC) -o sensor_conf sensor_conf.o $(LFLAGS) 14 | 15 | sensor_conf.o : sensor_conf.c 16 | $(CC) $(CFLAGS) -c sensor_conf.c 17 | 18 | -------------------------------------------------------------------------------- /logi-camera-bin/sw/sensor_configuration/sensor_conf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-camera-bin/sw/sensor_configuration/sensor_conf -------------------------------------------------------------------------------- /logi-camera-bin/sw/sensor_configuration/sensor_conf.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-camera-bin/sw/sensor_configuration/sensor_conf.o -------------------------------------------------------------------------------- /logi-camera-bin/sw/set_threshold.py: -------------------------------------------------------------------------------- 1 | import logi 2 | 3 | THRESHOLD = 0x7F 4 | logi.logiWrite(0x1004, (THRESHOLD, THRESHOLD)) 5 | -------------------------------------------------------------------------------- /logi-camera-demo/hw/logibone/ise/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "secureip" -o "/home/jpiat/development/FPGA/logi-family/logi-projects/logi-camera-demo/hw/logibone/ise/i2c_conf_new_tb_isim_beh.exe" -prj "/home/jpiat/development/FPGA/logi-family/logi-projects/logi-camera-demo/hw/logibone/ise/i2c_conf_new_tb_beh.prj" "work.i2c_conf_new_tb" 2 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/CHANGELOG: -------------------------------------------------------------------------------- 1 | 2 | A changelog is available at: 3 | http://mjpg-streamer.svn.sourceforge.net/viewvc/mjpg-streamer/?view=log 4 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/fix_dependency.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ln -s /usr/include/linux/videodev2.h /usr/include/linux/videodev.h 4 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/launch_streamer.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | LD_LIBRARY_PATH=/usr/lib/arm-linux-gnueabihf/ 3 | ./mjpg_streamer -i "./input_memory.so -i 0 -r 320x240" -o "./output_http.so -w ./www" 4 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/plugins/input_memory/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################### 2 | # 3 | # Purpose: Makefile for "M-JPEG Streamer" 4 | # Author.: Tom Stoeveken (TST) 5 | # Version: 0.3 6 | # License: GPL 7 | # 8 | ############################################################### 9 | 10 | CC = gcc 11 | 12 | OTHER_HEADERS = ../../mjpg_streamer.h ../../utils.h ../output.h ../input.h wishbone_wrapper.h 13 | 14 | CFLAGS += -O2 -DLINUX -D_GNU_SOURCE -DLOGIBONE -Wall -shared -fPIC 15 | #CFLAGS += -DDEBUG 16 | LFLAGS += -lpthread -ldl -ljpeg -lm 17 | 18 | all: input_memory.so 19 | 20 | clean: 21 | rm -f *.a *.o core *~ *.so *.lo 22 | 23 | input_memory.so: $(OTHER_HEADERS) input_memory.c jpeg_func.c wishbone_wrapper.c 24 | $(CC) $(CFLAGS) -o $@ input_memory.c jpeg_func.c wishbone_wrapper.c $(LFLAGS) 25 | 26 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/plugins/input_memory/config.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | #ifdef LOGIBONE 4 | 5 | #define FIFO_ADDR 0x0000 6 | #define FIFO_CMD_OFFSET 0x0200 7 | #define FIFO_SIZE_OFFSET 0x0200 8 | #define FIFO_AVAILABLE_OFFSET 0x0201 9 | 10 | #define SINGLE_ACCESS_SIZE 1024 11 | 12 | #define LOG_PATH "/home/ubuntu/tests_log/%ld_test.log" 13 | 14 | #endif 15 | 16 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/plugins/input_memory/jpeg_func.h: -------------------------------------------------------------------------------- 1 | int write_jpegfile(char * frame, unsigned short width, unsigned short height, FILE * fd, int quality); 2 | int write_jpegmem_gray(char * frame, unsigned short width, unsigned short height, unsigned char **outbuffer, long unsigned int *outlen, int quality); 3 | int write_jpegmem_rgb(char * frame, unsigned short width, unsigned short height, unsigned char **outbuffer, long unsigned int *outlen, int quality); 4 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/plugins/input_memory/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 6 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 7 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/plugins/output_http/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################### 2 | # 3 | # Purpose: Makefile for "M-JPEG Streamer" 4 | # Author.: Tom Stoeveken (TST) 5 | # Version: 0.3 6 | # License: GPL 7 | # 8 | ############################################################### 9 | 10 | CC = gcc 11 | 12 | OTHER_HEADERS = ../../mjpg_streamer.h ../../utils.h ../output.h ../input.h 13 | 14 | CFLAGS += -O2 -DLINUX -D_GNU_SOURCE -Wall -shared -fPIC 15 | #CFLAGS += -DDEBUG 16 | LFLAGS += -lpthread -ldl 17 | 18 | all: output_http.so 19 | 20 | clean: 21 | rm -f *.a *.o core *~ *.so *.lo 22 | 23 | output_http.so: $(OTHER_HEADERS) output_http.c httpd.lo 24 | $(CC) $(CFLAGS) -o $@ output_http.c httpd.lo 25 | 26 | httpd.lo: $(OTHER_HEADERS) httpd.h httpd.c 27 | $(CC) -c $(CFLAGS) -o $@ httpd.c 28 | -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/www/bodybg.gif: -------------------------------------------------------------------------------- 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width:100%; overflow:auto;} -------------------------------------------------------------------------------- /logi-camera-demo/sw/logi-mjpg-streamer/www/sidebarbg.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-camera-demo/sw/logi-mjpg-streamer/www/sidebarbg.gif -------------------------------------------------------------------------------- /logi-camera-test/bitfiles/logi_camera_test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-camera-test/bitfiles/logi_camera_test.bit -------------------------------------------------------------------------------- /logi-camera-test/sw/logipi/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | LD_FLAGS = -lc -ljpeg 3 | 4 | all: test_logi_cam 5 | 6 | clean: 7 | rm -f *.a *.o test_logi_cam 8 | 9 | test_logi_cam : test.c wishbone_wrapper.c jpeg_func.c 10 | $(CC) -D LOGIPI -o $@ test.c wishbone_wrapper.c jpeg_func.c $(LD_FLAGS) 11 | 12 | -------------------------------------------------------------------------------- /logi-camera-test/sw/logipi/config.h: -------------------------------------------------------------------------------- 1 | //DEFINE WHICH TESTS TO RUN 2 | //COMMENT OUT TESTS YOU DO NOT WANT TO RUN 3 | 4 | #ifdef LOGIPI 5 | 6 | #define LOAD_CMD "/usr/bin/logi_loader logi_camera_test.bit" 7 | 8 | #define FIFO_ADDR 0x0000 9 | #define FIFO_CMD_OFFSET 0x0004 10 | #define FIFO_SIZE_OFFSET 0x0004 11 | #define FIFO_AVAILABLE_OFFSET 0x00041 12 | 13 | #define LOG_PATH "/home/pi/tests_log/%ld_test.log" 14 | 15 | #endif 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /logi-camera-test/sw/logipi/jpeg_func.h: -------------------------------------------------------------------------------- 1 | int write_jpegfile(char * frame, unsigned short width, unsigned short height, int nbChan, FILE * fd, int quality); 2 | int write_jpegmem(char * frame, unsigned short width, unsigned short height, unsigned short nbChannels, unsigned char **outbuffer, long unsigned int *outlen, int quality); 3 | int read_jpeg_file( char *filename, unsigned char ** buffer); 4 | -------------------------------------------------------------------------------- /logi-camera-test/sw/logipi/make_test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | mkdir /home/pi/tests_log 3 | sudo apt-get install libjpeg8-dev fbi 4 | make clean 5 | make 6 | sudo ./test_logi_cam 7 | -------------------------------------------------------------------------------- /logi-camera-test/sw/logipi/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 6 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 7 | unsigned int wishbone_write_noinc(unsigned char * buffer, unsigned int length, unsigned int address); 8 | unsigned int wishbone_read_noinc(unsigned char * buffer, unsigned int length, unsigned int address); 9 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clock_gen 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 976 576 976 14 | PIN 608 976 RIGHT 36 15 | PINATTR PinName locked 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/implement/xst.prj: -------------------------------------------------------------------------------- 1 | vhdl work ../../clock_gen.vhd 2 | vhdl work ../example_design/clock_gen_exdes.vhd 3 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt MIXED 3 | -top clock_gen_exdes 4 | -p xc6slx9-tqg144-3 5 | -ifn xst.prj 6 | -ofn clock_gen_exdes 7 | -keep_hierarchy soft 8 | -equivalent_register_removal no 9 | -max_fanout 65535 10 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- 1 | COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", 2 | SCOPE = :dut; 3 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | 10 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | 2 | run 50000ns 3 | quit 4 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/clock_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /logi-com-test/hw/logibone/ise/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -3 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clock_gen 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 976 576 976 14 | PIN 608 976 RIGHT 36 15 | PINATTR PinName locked 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/implement/xst.prj: -------------------------------------------------------------------------------- 1 | vhdl work ../../clock_gen.vhd 2 | vhdl work ../example_design/clock_gen_exdes.vhd 3 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt MIXED 3 | -top clock_gen_exdes 4 | -p xc6slx9-tqg144-3 5 | -ifn xst.prj 6 | -ofn clock_gen_exdes 7 | -keep_hierarchy soft 8 | -equivalent_register_removal no 9 | -max_fanout 65535 10 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- 1 | COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", 2 | SCOPE = :dut; 3 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | 10 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | 2 | run 50000ns 3 | quit 4 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/clock_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /logi-com-test/hw/logipi/ise/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -3 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /logi-com-test/sw/logibone/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | 3 | 4 | all: test_wishbone 5 | 6 | clean: 7 | rm -f *.a *.o test_wishbone 8 | 9 | wishbone_wrapper.o: wishbone_wrapper.c 10 | $(CC) -c wishbone_wrapper.c 11 | 12 | test_wishbone : test_wishbone.c wishbone_wrapper.o 13 | $(CC) -o $@ test_wishbone.c wishbone_wrapper.o 14 | -------------------------------------------------------------------------------- /logi-com-test/sw/logibone/wishbone_wrapper.c: -------------------------------------------------------------------------------- 1 | #include "wishbone_wrapper.h" 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | int fd ; 15 | 16 | int logi_open(){ 17 | fd = open("/dev/logibone_mem", O_RDWR | O_SYNC); 18 | return 1 ; 19 | } 20 | 21 | void logi_close(){ 22 | close(fd); 23 | } 24 | 25 | int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address){ 26 | int count = 0 ; 27 | if(fd == 0){ 28 | logi_open(); 29 | } 30 | count = pwrite(fd, buffer, length, address); 31 | return count ; 32 | } 33 | int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address){ 34 | int count = 0 ; 35 | if(fd == 0){ 36 | logi_open(); 37 | } 38 | count = pread(fd, buffer, length, address); 39 | return count ; 40 | } 41 | 42 | -------------------------------------------------------------------------------- /logi-com-test/sw/logibone/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | #ifndef WISHBONE_WRAPPER_H 2 | #define WISHBONE_WRAPPER_H 3 | 4 | int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 5 | int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 6 | 7 | #endif 8 | 9 | -------------------------------------------------------------------------------- /logi-com-test/sw/logibone_spi/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | 3 | 4 | all: test_wishbone 5 | 6 | clean: 7 | rm -f *.a *.o test_wishbone 8 | 9 | wishbone_wrapper.o: wishbone_wrapper.c 10 | $(CC) -c wishbone_wrapper.c 11 | 12 | test_wishbone : test_wishbone.c wishbone_wrapper.o 13 | $(CC) -o $@ test_wishbone.c wishbone_wrapper.o 14 | -------------------------------------------------------------------------------- /logi-com-test/sw/logibone_spi/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | int wishbone_init(void); 5 | int set_speed(unsigned long speed_arg); 6 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 7 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 8 | -------------------------------------------------------------------------------- /logi-com-test/sw/logipi/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | 3 | 4 | all: test_wishbone 5 | 6 | clean: 7 | rm -f *.a *.o test_wishbone 8 | 9 | wishbone_wrapper.o: wishbone_wrapper.c 10 | $(CC) -c wishbone_wrapper.c 11 | 12 | test_wishbone : test_wishbone.c wishbone_wrapper.o 13 | $(CC) -o $@ test_wishbone.c wishbone_wrapper.o 14 | -------------------------------------------------------------------------------- /logi-com-test/sw/logipi/test_wishbone: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-com-test/sw/logipi/test_wishbone -------------------------------------------------------------------------------- /logi-com-test/sw/logipi/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | int wishbone_init(void); 5 | int set_speed(unsigned long speed_arg); 6 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 7 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 8 | -------------------------------------------------------------------------------- /logi-edu-test/bitfiles/logi_edu_test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-edu-test/bitfiles/logi_edu_test.bit -------------------------------------------------------------------------------- /logi-edu-test/sw/common/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | LD_FLAGS = -lc 3 | 4 | all: test_logi_edu 5 | 6 | clean: 7 | rm -f *.a *.o test_logi_edu 8 | 9 | test_logi_edu : test.c wishbone_wrapper.c 10 | $(CC) -D LOGIPI -o $@ test.c wishbone_wrapper.c $(LD_FLAGS) 11 | 12 | -------------------------------------------------------------------------------- /logi-edu-test/sw/common/make_test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | mkdir /home/pi/tests_log 4 | make clean 5 | make 6 | sudo ./test_logi_edu 7 | -------------------------------------------------------------------------------- /logi-edu-test/sw/common/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 6 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 7 | -------------------------------------------------------------------------------- /logi-edu/logi-edu-demo/hw/logipi/hdl/pong/pong_timer.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 13.9 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | entity timer is 6 | port( 7 | clk, reset: in std_logic; 8 | timer_start, timer_tick: in std_logic; 9 | timer_up: out std_logic 10 | ); 11 | end timer; 12 | 13 | architecture arch of timer is 14 | signal timer_reg, timer_next: unsigned(6 downto 0); 15 | begin 16 | -- registers 17 | process (clk, reset) 18 | begin 19 | if reset='1' then 20 | timer_reg <= (others=>'1'); 21 | elsif (clk'event and clk='1') then 22 | timer_reg <= timer_next; 23 | end if; 24 | end process; 25 | -- next-state logic 26 | process(timer_start,timer_reg,timer_tick) 27 | begin 28 | if (timer_start='1') then 29 | timer_next <= (others=>'1'); 30 | elsif timer_tick='1' and timer_reg/=0 then 31 | timer_next <= timer_reg - 1; 32 | else 33 | timer_next <= timer_reg; 34 | end if; 35 | end process; 36 | timer_up <='1' when timer_reg=0 else '0'; 37 | end arch; -------------------------------------------------------------------------------- /logi-edu/logi-edu-demo/hw/logipi/hdl/ps2/ps2_rxtx.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 9.2 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity ps2_rxtx is 5 | port ( 6 | clk, reset: in std_logic; 7 | wr_ps2: std_logic; 8 | din: in std_logic_vector(7 downto 0); 9 | dout: out std_logic_vector(7 downto 0); 10 | rx_done_tick: out std_logic; 11 | tx_done_tick: out std_logic; 12 | ps2d, ps2c: inout std_logic 13 | ); 14 | end ps2_rxtx; 15 | 16 | architecture arch of ps2_rxtx is 17 | signal tx_idle: std_logic; 18 | begin 19 | ps2_tx_unit: entity work.ps2_tx(arch) 20 | port map(clk=>clk, reset=>reset, wr_ps2=>wr_ps2, 21 | din=>din, ps2d=>ps2d, ps2c=>ps2c, 22 | tx_idle=>tx_idle, tx_done_tick=>tx_done_tick); 23 | ps2_rx_unit: entity work.ps2_rx(arch) 24 | port map(clk=>clk, reset=>reset, rx_en=>tx_idle, 25 | ps2d=>ps2d, ps2c=>ps2c, 26 | rx_done_tick=>rx_done_tick, dout=>dout); 27 | end arch; -------------------------------------------------------------------------------- /logi-edu/logi-mark1-edu-pong/hdl/list_ch13_09_pong_timer.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 13.9 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | use ieee.numeric_std.all; 5 | entity timer is 6 | port( 7 | clk, reset: in std_logic; 8 | timer_start, timer_tick: in std_logic; 9 | timer_up: out std_logic 10 | ); 11 | end timer; 12 | 13 | architecture arch of timer is 14 | signal timer_reg, timer_next: unsigned(6 downto 0); 15 | begin 16 | -- registers 17 | process (clk, reset) 18 | begin 19 | if reset='1' then 20 | timer_reg <= (others=>'1'); 21 | elsif (clk'event and clk='1') then 22 | timer_reg <= timer_next; 23 | end if; 24 | end process; 25 | -- next-state logic 26 | process(timer_start,timer_reg,timer_tick) 27 | begin 28 | if (timer_start='1') then 29 | timer_next <= (others=>'1'); 30 | elsif timer_tick='1' and timer_reg/=0 then 31 | timer_next <= timer_reg - 1; 32 | else 33 | timer_next <= timer_reg; 34 | end if; 35 | end process; 36 | timer_up <='1' when timer_reg=0 else '0'; 37 | end arch; -------------------------------------------------------------------------------- /logi-edu/logi-pi-nes-servo-pwm/sw/wishbone_map.py: -------------------------------------------------------------------------------- 1 | #Watch_0 = 0x0002 2 | #Servo_0 = 0x0020 3 | #Pwm_0 = 0x0010 4 | pwm = 0x0000 5 | servo = 0x0020 -------------------------------------------------------------------------------- /logi-edu/loig-pi-edu-mouse_led_sseg/hdl/ps2_rxtx.vhd: -------------------------------------------------------------------------------- 1 | -- Listing 9.2 2 | library ieee; 3 | use ieee.std_logic_1164.all; 4 | entity ps2_rxtx is 5 | port ( 6 | clk, reset: in std_logic; 7 | wr_ps2: std_logic; 8 | din: in std_logic_vector(7 downto 0); 9 | dout: out std_logic_vector(7 downto 0); 10 | rx_done_tick: out std_logic; 11 | tx_done_tick: out std_logic; 12 | ps2d, ps2c: inout std_logic 13 | ); 14 | end ps2_rxtx; 15 | 16 | architecture arch of ps2_rxtx is 17 | signal tx_idle: std_logic; 18 | begin 19 | ps2_tx_unit: entity work.ps2_tx(arch) 20 | port map(clk=>clk, reset=>reset, wr_ps2=>wr_ps2, 21 | din=>din, ps2d=>ps2d, ps2c=>ps2c, 22 | tx_idle=>tx_idle, tx_done_tick=>tx_done_tick); 23 | ps2_rx_unit: entity work.ps2_rx(arch) 24 | port map(clk=>clk, reset=>reset, rx_en=>tx_idle, 25 | ps2d=>ps2d, ps2c=>ps2c, 26 | rx_done_tick=>rx_done_tick, dout=>dout); 27 | end arch; -------------------------------------------------------------------------------- /logi-face/hw/logiface_pack.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Package File Template 3 | -- 4 | -- Purpose: This package defines supplemental types, subtypes, 5 | -- constants, and functions 6 | -- 7 | -- To use any of the example code shown below, uncomment the lines and modify as necessary 8 | -- 9 | 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.all; 12 | 13 | package logiface_pack is 14 | 15 | component compute_adc_mean is 16 | generic(NB_SAMPLES : positive := 512); 17 | port( 18 | clk, resetn : in std_logic ; 19 | 20 | sample_in : in std_logic_vector(9 downto 0); 21 | dv_in : in std_logic ; 22 | 23 | mean_val : out std_logic_vector(9 downto 0) 24 | ); 25 | end component; 26 | end logiface_pack; 27 | -------------------------------------------------------------------------------- /logi-face/sw/lin_client.py: -------------------------------------------------------------------------------- 1 | import time 2 | 3 | 4 | lin_file = open('/root/linphone_out') 5 | while True: 6 | line = lin_file.readline() 7 | if line: 8 | if line.find("Message") != -1: 9 | print line.split(":")[-1] 10 | -------------------------------------------------------------------------------- /logi-face/sw/python/setup.py: -------------------------------------------------------------------------------- 1 | from distutils.core import setup, Extension 2 | 3 | module1 = Extension('logipi', sources = ['logipi.c', '../fifo_lib/rpi-fifolib.c'], include_dirs=['../fifo_lib']) 4 | 5 | setup (name = 'PackageName', 6 | version = '1.0', 7 | description = 'This is a demo package', 8 | ext_modules = [module1]) 9 | -------------------------------------------------------------------------------- /logi-fcc-standalone/hw/logibone/work/logibone_fcc_standalone_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc-standalone/hw/logibone/work/logibone_fcc_standalone.ncd 3 | OUTFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc-standalone/hw/logibone/work/logibone_fcc_standalone.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx9-2tqg144 6 | WORKINGDIR=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc-standalone/hw/logibone/work 7 | LICENSE=WebPack 8 | USER_INFO=208450455_1777487672_0_558 9 | -------------------------------------------------------------------------------- /logi-fcc-standalone/hw/logipi/work/logipi_fcc_standalone_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=H:\Dropbox\1LOGI\1LOGI_SRC\1logi-github\1LOGI-REPO\Logi-projects\logi-fcc-standalone\hw\logipi\work\logipi_fcc_standalone.ncd 3 | OUTFILE=H:\Dropbox\1LOGI\1LOGI_SRC\1logi-github\1LOGI-REPO\Logi-projects\logi-fcc-standalone\hw\logipi\work\logipi_fcc_standalone.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx9-2tqg144 6 | WORKINGDIR=H:\Dropbox\1LOGI\1LOGI_SRC\1logi-github\1LOGI-REPO\Logi-projects\logi-fcc-standalone\hw\logipi\work 7 | LICENSE=WebPack 8 | USER_INFO=202672454_0_0_477 9 | -------------------------------------------------------------------------------- /logi-fcc/README: -------------------------------------------------------------------------------- 1 | To run the test, take the bitfile corresponding to your platform from test_bit_files 2 | and rename it to logipi_test.bit. 3 | Copy the logipi-sw directory to the platform, and then copy the renamed logipi_test.bit file 4 | and copy it in the logipi-sw directory on the platform. In the end you should have the folder 5 | logipi-sw on the platform, with the bitfile inside. Log on the platform and go to the logipi-sw 6 | folder. Type "make" then enter. To run the test do a "sudo ./test_logipi" and follow the 7 | instructions on screen. Test will indicate which part fail or indicate a success. 8 | -------------------------------------------------------------------------------- /logi-fcc/hw/logibone/ise/ipcore_dir/clock_gen.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-fcc/hw/logibone/ise/ipcore_dir/clock_gen.ncf -------------------------------------------------------------------------------- /logi-fcc/hw/logibone/ise/logibone_test_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc/hw/logibone/ise/logibone_test.ncd 3 | OUTFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc/hw/logibone/ise/logibone_test.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx9-2tqg144 6 | WORKINGDIR=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc/hw/logibone/ise 7 | LICENSE=WebPack 8 | USER_INFO=__174162038_174162039_174422429 9 | -------------------------------------------------------------------------------- /logi-fcc/hw/logipi/ise/ipcore_dir/clock_gen.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-fcc/hw/logipi/ise/ipcore_dir/clock_gen.ncf -------------------------------------------------------------------------------- /logi-fcc/hw/logipi/ise/logipi_test_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc/hw/logipi/ise/logipi_test.ncd 3 | OUTFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc/hw/logipi/ise/logipi_test.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx9-2tqg144 6 | WORKINGDIR=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-fcc/hw/logipi/ise 7 | LICENSE=WebPack 8 | USER_INFO=208450455_1777487672_0_558 9 | -------------------------------------------------------------------------------- /logi-fcc/sw/common/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | LD_FLAGS = -lc 3 | 4 | all: test_logipi test_logibone 5 | 6 | clean: 7 | rm -f *.a *.o test_logipi test_logibone 8 | 9 | test_logipi : test.c wishbone_wrapper.c 10 | $(CC) -D LOGIPI -o $@ test.c wishbone_wrapper.c $(LD_FLAGS) 11 | 12 | test_logibone : test.c wishbone_wrapper.c 13 | $(CC) -D LOGIBONE -o $@ test.c wishbone_wrapper.c $(LD_FLAGS) 14 | -------------------------------------------------------------------------------- /logi-fcc/sw/common/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 6 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 7 | -------------------------------------------------------------------------------- /logi-laser-bot/sw/sensor_configuration/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CC = gcc 3 | CFLAGS = -I/home/debian/logi-tools/c 4 | LFLAGS = -llogi 5 | 6 | 7 | all : sensor_conf 8 | 9 | clean : 10 | rm *.o sensor_conf 11 | 12 | sensor_conf : sensor_conf.o 13 | $(CC) -o sensor_conf sensor_conf.o $(LFLAGS) 14 | 15 | sensor_conf.o : sensor_conf.c 16 | $(CC) $(CFLAGS) -c sensor_conf.c 17 | 18 | -------------------------------------------------------------------------------- /logi-machine-vision/README.TXT: -------------------------------------------------------------------------------- 1 | Machine Vision Project ************************************************************************* 2 | * DOCUMENTATION: http://valentfx.com/wiki/index.php?title=LOGI_-_Machine_Vision_-_Project 3 | * DESCRIPTION ************** 4 | This proect does not require a camera. It loads an image and processes it 5 | * INSTRUCTIONS ************* 6 | Generate Programming File using Xilinx ISE open: File | New Project | logi-machine-vision/hw/logipi/ise/logipi_machine_vision.xise 7 | * TROUBLESHOOTING ********** 8 | Please add HowTo! 9 | * SUGGESTIONS ************** 10 | Open up the individual project folder to build each project. 11 | ************************************************************************************* 12 | -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 clock_gen 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | LINE Normal 608 976 576 976 18 | PIN 608 976 RIGHT 36 19 | PINATTR PinName locked 20 | PINATTR Polarity OUT 21 | 22 | -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen/doc/clk_wiz_gsg521.pdf -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt MIXED 3 | -top clock_gen_exdes 4 | -p xc6slx9-tqg144-2 5 | -ifn xst.prj 6 | -ofn clock_gen_exdes 7 | -keep_hierarchy soft 8 | -equivalent_register_removal no 9 | -max_fanout 65535 10 | -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- 1 | COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", 2 | SCOPE = :dut; 3 | -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /clock_gen_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | 10 | -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | 2 | run 50000ns 3 | quit 4 | -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/clock_gen/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /logi-machine-vision/hw/logipi/ise/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = VHDL 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = false 9 | SET vhdlsim = true 10 | -------------------------------------------------------------------------------- /logi-machine-vision/sw/Makefile: -------------------------------------------------------------------------------- 1 | #Compiler to use 2 | CC=gcc 3 | #Compiler Flags 4 | #Linker Flags 5 | CFLAGS = -c 6 | LDFLAGS= -ljpeg -lrt -llogi 7 | 8 | 9 | all: image_demo 10 | 11 | image_demo: image_demo.o jpeg_func.o 12 | $(CC) -o image_demo image_demo.o jpeg_func.o $(LDFLAGS) 13 | 14 | image_demo.o: image_demo.c 15 | $(CC) $(CFLAGS) image_demo.c 16 | 17 | jpeg_func.o: jpeg_func.c 18 | $(CC) $(CFLAGS) jpeg_func.c 19 | 20 | clean: 21 | rm -rf *.o image_demo 22 | -------------------------------------------------------------------------------- /logi-machine-vision/sw/beagle_qvga.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-machine-vision/sw/beagle_qvga.jpg -------------------------------------------------------------------------------- /logi-machine-vision/sw/grabbed_frame.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-machine-vision/sw/grabbed_frame.jpg -------------------------------------------------------------------------------- /logi-machine-vision/sw/jpeg_func.h: -------------------------------------------------------------------------------- 1 | int write_jpegfile(char * frame, unsigned short width, unsigned short height, FILE * fd, int quality); 2 | int write_jpegmem(char * frame, unsigned short width, unsigned short height, unsigned short nbChannels, unsigned char **outbuffer, long unsigned int *outlen, int quality); 3 | int read_jpeg_file( char *filename, unsigned char ** buffer); 4 | -------------------------------------------------------------------------------- /logi-matrix/hw/logibone/ise/logibone_mat_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-matrix/hw/logibone/ise/logibone_mat.ncd 3 | OUTFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-matrix/hw/logibone/ise/logibone_mat.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx9-2tqg144 6 | WORKINGDIR=/home/jpiat/development/FPGA/logi-family/logi-projects/logi-matrix/hw/logibone/ise 7 | LICENSE=WebPack 8 | USER_INFO=208450455_1777487672_0_558 9 | -------------------------------------------------------------------------------- /logi-matrix/sw/logipi/README.md: -------------------------------------------------------------------------------- 1 | Software to work with a 32*32 LED matrix controlled by logipi 2 | 3 | 4 | 0. requirement 5 | ----------------------------------------------------------- 6 | liblogipi.so exists in /home/pi/logi-tools/c 7 | change LD_LIBRARY_PATH to /home/pi/logi-tools/c 8 | preload the bit stream to the FPGA 9 | 10 | 11 | 1. use of test_wishbone 12 | ------------------------------------------------------------ 13 | tests the communication and speed 14 | make and run 15 | 16 | 17 | 2. use of test_gif 18 | ------------------------------------------------------------ 19 | please put frames of ppm file into data/ 20 | edit the filename in gif.c and make 21 | 22 | 23 | 3. use of one_led and led_white 24 | ------------------------------------------------------------ 25 | led_white turns the panel to white 26 | one_led lets you control single/continuous leds 27 | 28 | 4. LED games 29 | ------------------------------------------------------------- 30 | Not finished! Will probably open source after finish and consent of the 31 | author. 32 | -------------------------------------------------------------------------------- /logi-matrix/sw/logipi/data/README: -------------------------------------------------------------------------------- 1 | I'm here to make sure git doesn't remove this directory when it's empty 2 | 3 | But, put your frames here please 4 | -------------------------------------------------------------------------------- /logi-matrix/sw/logipi/data/beagleboard_logo.raw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-matrix/sw/logipi/data/beagleboard_logo.raw -------------------------------------------------------------------------------- /logi-matrix/sw/logipi/data/frame_000.ppm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-matrix/sw/logipi/data/frame_000.ppm -------------------------------------------------------------------------------- /logi-matrix/sw/logipi/data/frame_001.ppm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-matrix/sw/logipi/data/frame_001.ppm -------------------------------------------------------------------------------- /logi-matrix/sw/logipi/data/frame_002.ppm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-matrix/sw/logipi/data/frame_002.ppm -------------------------------------------------------------------------------- /logi-matrix/sw/logipi/test_wishbone: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-matrix/sw/logipi/test_wishbone -------------------------------------------------------------------------------- /logi-motor-control/hw/logibone/bitfiles/logibone_motor_control.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/hw/logibone/bitfiles/logibone_motor_control.bit -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/README.txt: -------------------------------------------------------------------------------- 1 | MATLAB r2014b Simulink Models using BeagleBoneBlack support package for Embedded Coder 2 | 3 | Uses motor control bitstream in hw directory. 4 | 5 | Tested with PmodHB5 modules plugged into top row of PMOD1 and PMOD2 ports, and 6 | two Digilent geared DC motors (1:53 reduction) 7 | 8 | Included S-Functions built for MS Windows 64-bits 9 | 10 | Runs on standard logibone image referenced in logibone quick start guide, but 11 | you must first disable password authentication for ubuntu user in 12 | sudoers file. Run sudo visudo and add the following on last line: 13 | 14 | ubuntu ALL = NOPASSWD: ALL 15 | 16 | TODO: 17 | -Models currently limited to 10Hz max 18 | -Combine multiple logibone reads and write into a single one for performance? 19 | -Use logibone library? 20 | -Load bitstream in block initialization? 21 | -Bitstream load conditional on checksum register perhaps? 22 | -Pass certain data as block parameters instead of input signals? 23 | -Build for win32? -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/SFB__logi_readall__SFB.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/sw/simulink/SFB__logi_readall__SFB.mat -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/SFB__logibone_motor_block__SFB.mat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/sw/simulink/SFB__logibone_motor_block__SFB.mat -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/beaglebone_logi.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/sw/simulink/beaglebone_logi.slx -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/logi_readall.mexw64: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/sw/simulink/logi_readall.mexw64 -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/logibone_motor_block.mexw64: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/sw/simulink/logibone_motor_block.mexw64 -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/logibone_motorcontrol1.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/sw/simulink/logibone_motorcontrol1.slx -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/logibone_motorcontrol2.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/sw/simulink/logibone_motorcontrol2.slx -------------------------------------------------------------------------------- /logi-motor-control/sw/simulink/logibone_motorcontrol_openloop.mp4: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-motor-control/sw/simulink/logibone_motorcontrol_openloop.mp4 -------------------------------------------------------------------------------- /logi-test/README: -------------------------------------------------------------------------------- 1 | To run the test, take the bitfile corresponding to your platform from test_bit_files 2 | and rename it to logipi_test.bit. 3 | Copy the logipi-sw directory to the platform, and then copy the renamed logipi_test.bit file 4 | and copy it in the logipi-sw directory on the platform. In the end you should have the folder 5 | logipi-sw on the platform, with the bitfile inside. Log on the platform and go to the logipi-sw 6 | folder. Type "make" then enter. To run the test do a "sudo ./test_logipi" and follow the 7 | instructions on screen. Test will indicate which part fail or indicate a success. 8 | -------------------------------------------------------------------------------- /logi-test/sw/common/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | LD_FLAGS = -lc 3 | 4 | all: test_logipi test_logibone 5 | 6 | clean: 7 | rm -f *.a *.o test_logipi test_logibone 8 | 9 | test_logipi : test.c wishbone_wrapper.c 10 | $(CC) -D LOGIPI -o $@ test.c wishbone_wrapper.c $(LD_FLAGS) 11 | 12 | test_logibone : test.c wishbone_wrapper.c 13 | $(CC) -D LOGIBONE -o $@ test.c wishbone_wrapper.c $(LD_FLAGS) 14 | -------------------------------------------------------------------------------- /logi-test/sw/common/fcc/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | LD_FLAGS = -lc 3 | 4 | all: test_logipi test_logibone 5 | 6 | clean: 7 | rm -f *.a *.o test_logipi test_logibone 8 | 9 | test_logipi : test.c wishbone_wrapper.c 10 | $(CC) -D LOGIPI -o $@ test.c wishbone_wrapper.c $(LD_FLAGS) 11 | 12 | test_logibone : test.c wishbone_wrapper.c 13 | $(CC) -D LOGIBONE -o $@ test.c wishbone_wrapper.c $(LD_FLAGS) 14 | -------------------------------------------------------------------------------- /logi-test/sw/common/fcc/loop_call.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | while : 4 | do 5 | sudo ./$1 6 | sleep 0.1 7 | done 8 | -------------------------------------------------------------------------------- /logi-test/sw/common/fcc/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 6 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 7 | -------------------------------------------------------------------------------- /logi-test/sw/common/loop_call.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Recommend syntax for setting an infinite while loop 3 | while : 4 | do 5 | ./$1 6 | sleep 0.1 7 | done 8 | -------------------------------------------------------------------------------- /logi-test/sw/common/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 6 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 7 | -------------------------------------------------------------------------------- /logi-ugv/sw/avc_waypoints.txt: -------------------------------------------------------------------------------- 1 | QGC WPL 120 2 | 0 1 0 16 0 5 0 0 40.071353786811521 -105.229775905609131 0 1 3 | 1 0 3 16 0 5 0 0 40.0712757901478014 -105.230092406272888 25 1 4 | 2 0 3 16 0 5 0 0 40.070688759760138 -105.229719579219818 25 1 5 | 3 0 3 16 0 5 0 0 40.070904278497224 -105.229134857654572 25 1 6 | 4 0 3 16 0 5 0 0 40.0711834255620687 -105.229386985301971 25 1 7 | 5 0 3 16 0 5 0 0 40.0713886800269208 -105.229456722736359 25 1 8 | 6 0 3 16 0 5 0 0 40.0713312088391049 -105.229899287223816 25 1 9 | -------------------------------------------------------------------------------- /logi-ugv/sw/ether_client.py: -------------------------------------------------------------------------------- 1 | 2 | from socket import * 3 | 4 | 5 | 6 | HOST = '127.0.1.1' 7 | PORT = 2045 #our port from before 8 | ADDR = (HOST,PORT) 9 | BUFSIZE = 4096 10 | 11 | cli = socket( AF_INET,SOCK_STREAM) 12 | cli.connect((ADDR)) 13 | 14 | cli.send('{ "steer" : -10.0, "time" : 3000.0, "speed" : 75 }') 15 | cli.send('{ "steer" : -45.0, "time" : 800.0, "speed" : 75 }') 16 | cli.send('{ "steer" : -10.0, "time" : 2000.0, "speed" : 75 }') 17 | cli.send('{ "steer" : -45.0, "time" : 800.0, "speed" : 75 }') 18 | cli.send('{ "steer" : -10.0, "time" : 3000.0, "speed" : 75 }') 19 | cli.send('{ "steer" : -45.0, "time" : 800.0, "speed" : 75 }') 20 | cli.send('{ "steer" : -10.0, "time" : 3000.0, "speed" : 0 }') 21 | 22 | cli.close() 23 | -------------------------------------------------------------------------------- /logi-ugv/sw/laas_waypoints.txt: -------------------------------------------------------------------------------- 1 | QGC WPL 120 2 | 0 1 0 16 0 5 0 0 43.5616184221655587 1.4776235818862915 0 1 3 | 1 0 3 16 0 5 0 0 43.5616456328246784 1.47741973400115967 25 1 4 | 2 0 3 16 0 5 0 0 43.5617894603901803 1.47773087024688721 25 1 5 | 3 0 3 16 0 5 0 0 43.5614279472075765 1.47770941257476807 25 1 6 | 4 0 3 16 0 5 0 0 43.5613735256804091 1.47759139537811279 25 1 7 | 5 0 3 16 0 5 0 0 43.5616145349275499 1.47734463214874268 25 1 8 | -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | -25 2 | 124 3 | 15 4 | 154 5 | -154 6 | 21 7 | -------------------------------------------------------------------------------- /logi-ugv/sw/linux-mpu9150/setup.py: -------------------------------------------------------------------------------- 1 | from distutils.core import setup, Extension 2 | 3 | module1 = Extension('mpu9150', 4 | sources = ['mpu9150-python.c', 5 | 'mpu9150/mpu9150.c', 6 | 'mpu9150/quaternion.c', 7 | 'mpu9150/vector3d.c', 8 | 'eMPL/inv_mpu.c', 9 | 'eMPL/inv_mpu_dmp_motion_driver.c', 10 | 'glue/linux_glue.c', ], 11 | include_dirs=['./mpu9150', 12 | './eMPL', 13 | './glue'], 14 | define_macros=[('EMPL_TARGET_LINUX', None), 15 | ('MPU9150', None), 16 | ('AK8975_SECONDARY', None), 17 | ('Wall', None), 18 | ('fsingle-precision-constant', None), 19 | ], 20 | libraries=['m']) 21 | 22 | setup (name = 'PackageName', 23 | version = '1.0', 24 | description = 'This is a demo package', 25 | ext_modules = [module1]) 26 | -------------------------------------------------------------------------------- /logi-ugv/sw/linux-mpu9150/test_dmp.py: -------------------------------------------------------------------------------- 1 | import mpu9150 2 | import time 3 | from math import * 4 | 5 | mpu9150.mpuInit(1, 10, 4) 6 | mpu9150.setMagCal('magcal.txt') 7 | mpu9150.setAccCal('accelcal.txt') 8 | while True : 9 | i = mpu9150.mpuRead() 10 | if i >= 0: 11 | #print mpu9150.getFusedEuler() 12 | 13 | mag = mpu9150.getCalMag() 14 | bearing = atan2(mag[0], mag[1])*(180.0/pi) 15 | if bearing < 0 : 16 | bearing = bearing +360 17 | print bearing 18 | time.sleep(0.1) 19 | 20 | -------------------------------------------------------------------------------- /logi-ugv/sw/test_encoder.py: -------------------------------------------------------------------------------- 1 | import logi 2 | import time 3 | import math 4 | from binascii import * 5 | from string import * 6 | 7 | logi.logiWrite(0x000D, (0x01, 0x01)) 8 | logi.logiWrite(0x000D, (0x00, 0x00)) 9 | 10 | 11 | #calibration procedure: 12 | #1) put the car on the floor and lay a meter or ruler on the side 13 | #2) start the script and push the on a given distance (20cm to 1m) 14 | #3) write-down the tick value at the end of the distance 15 | #4) report the distance in the CALIBRATE_DISTANCE variable, and report the tick count in the CALIBRATE_TICK in the script 16 | #5) run the script again, and verify that the reported distance is fine, you can adjust the CALIBRATE_TICK and CALIBRATE_DISTANCE to give 17 | 18 | CALIBRATE_TICK = 1.0 19 | CALIBRATE_DISTANCE = 1.0 20 | CONV_FACTOR = CALIBRATE_DISTANCE/CALIBRATE_TICK 21 | 22 | while True: 23 | enc_reg = logi.logiRead(0x000D, 2) 24 | enc_val = (enc_reg[1] << 8) | enc_reg[0] 25 | dist = float(enc_val)*CONV_FACTOR 26 | print "tick : "+str(enc_val)+"tick" 27 | print "dist : "+str(dist)+"m" 28 | time.sleep(0.1) 29 | -------------------------------------------------------------------------------- /logi-ugv/sw/test_sonar.py: -------------------------------------------------------------------------------- 1 | import logi 2 | import time 3 | from binascii import * 4 | from string import * 5 | 6 | 7 | 8 | while True: 9 | time.sleep(0.1) 10 | logi.logiWrite(0x0004, (0xFF, 0xFF)) 11 | for i in range(3): 12 | sonar = logi.logiRead(0x0010+i, 2) 13 | sonar_tp = (sonar[1] << 8) | sonar[0] 14 | sonar_cm = float(sonar_tp)/59.0 15 | print "sonar "+str(i)+" :"+str(sonar_cm)+" cm" 16 | -------------------------------------------------------------------------------- /logi-ugv/sw/traj_plot.py: -------------------------------------------------------------------------------- 1 | import math 2 | import matplotlib.pyplot as plt 3 | import csv 4 | 5 | def importXYLog(file_path): 6 | waypoints_xy = [] 7 | with open(file_path) as xy_csv: 8 | for line in csv.reader(xy_csv): 9 | if len(line) == 2: 10 | waypoints_xy.append((float(line[0]), float(line[1]))) 11 | return waypoints_xy 12 | 13 | if __name__ == "__main__": 14 | 15 | 16 | corner_x_pos = [] 17 | corner_y_pos =[] 18 | 19 | xy_wp = importXYLog("./xy.log") 20 | for xy in xy_wp: 21 | print xy 22 | corner_x_pos.append(xy[0]) 23 | corner_y_pos.append(xy[1]) 24 | 25 | plt.plot(corner_x_pos, corner_y_pos, 'k') 26 | #plt.axis([-15.0, 15.0, 0.0, 30.0]) 27 | plt.show() 28 | exit() 29 | 30 | 31 | -------------------------------------------------------------------------------- /logi-ugv/sw/ugv_map.py: -------------------------------------------------------------------------------- 1 | GPS_0 = 0x40 2 | PING_0 = 0x4 3 | SERVO_0 = 0x10 4 | WATCH_0 = 0x0 5 | REG_0 = 0x0C 6 | -------------------------------------------------------------------------------- /logi-virtual-components/sw/logi_panel/fifo_lib/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | 3 | 4 | all: beaglebone_fifo_test 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-------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | The Default strategy provides a balanced optimization of performance results vs. runtime. The default property values correspond to the default values of each of the underlying implementation tools. This strategy keeps all properties in an unlocked state so that you can modify the values as you wish. 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logibone/MEMORY_LAYOUT.TXT: -------------------------------------------------------------------------------- 1 | address | name | note | 2 | 0x0000 register_0 read :0xDEAD 3 | 0x0002 register_1 read : 0xBEEF 4 | 0x0004 register_3 read/write register 5 | 0x0006 register_4 write pmod2/read pmod1 and switches 6 | 0x0010 pwm_divider system_clock divider for pwm 7 | 0x0012 pwm_period pwm signa period 8 | 0x0014 pwm0_high high time for pwm0 (unconnected) 9 | 0x0016 pwm1_high high time for pwm1 connected to LED0 10 | 0x0018 pwm2_hight high time for pwm2 connected to LED1 11 | 12 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logibone/read_wishbone: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-wishbone/sw/logibone/read_wishbone -------------------------------------------------------------------------------- /logi-wishbone/sw/logibone/read_wishbone.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | //#include 11 | #include 12 | 13 | 14 | int main(int argc, char ** argv){ 15 | int fd, address ; 16 | unsigned short i ; 17 | unsigned short readVal ; 18 | if(argc < 1){ 19 | printf("not enough arguments \n"); 20 | return 0 ; 21 | } 22 | address = (int) strtol(argv[1], NULL, 0); 23 | fd = open("/dev/logibone_mem", O_RDWR | O_SYNC); 24 | pread(fd, &readVal, 2, address); 25 | printf("0x%x \n", readVal); 26 | close(fd); 27 | return 0 ; 28 | } 29 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logibone/write_wishbone: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/logi-wishbone/sw/logibone/write_wishbone -------------------------------------------------------------------------------- /logi-wishbone/sw/logibone/write_wishbone.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | //#include 11 | #include 12 | 13 | 14 | int main(int argc, char ** argv){ 15 | int fd, address ; 16 | unsigned short i ; 17 | unsigned short writeVal ; 18 | if(argc < 2){ 19 | printf("not enough arguments \n"); 20 | return 0 ; 21 | } 22 | address = (int) strtol(argv[1], NULL, 0); 23 | writeVal = (unsigned short) strtol(argv[2], NULL, 0); 24 | printf("Writing 0x%x @ 0x%x \n", writeVal, address); 25 | fd = open("/dev/logibone_mem", O_RDWR | O_SYNC); 26 | 27 | if(pwrite(fd, &writeVal, 2, address) < 2){ 28 | printf("Write error !"); 29 | } 30 | close(fd); 31 | return 0 ; 32 | } 33 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logipi/MEMORY_LAYOUT.TXT: -------------------------------------------------------------------------------- 1 | address | name | note | 2 | 0x0000 register_0 read :0xDEAD 3 | 0x0002 register_1 read : 0xBEEF 4 | 0x0004 register_3 read/write register 5 | 0x0006 register_4 write pmod2/read pmod1 and switches 6 | 0x0010 pwm_divider system_clock divider for pwm 7 | 0x0012 pwm_period pwm signa period 8 | 0x0014 pwm0_high high time for pwm0 (unconnected) 9 | 0x0016 pwm1_high high time for pwm1 connected to LED0 10 | 0x0018 pwm2_hight high time for pwm2 connected to LED1 11 | 12 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logipi/Makefile: -------------------------------------------------------------------------------- 1 | CC = gcc 2 | 3 | 4 | all: read_wishbone write_wishbone test_wishbone 5 | 6 | clean: 7 | rm -f *.a *.o write_wishbone read_wishbone test_wishbone 8 | 9 | wishbone_wrapper.o: wishbone_wrapper.c 10 | $(CC) -c wishbone_wrapper.c 11 | 12 | read_wishbone : read_wishbone.c wishbone_wrapper.o 13 | $(CC) -o $@ read_wishbone.c wishbone_wrapper.o 14 | 15 | write_wishbone : write_wishbone.c wishbone_wrapper.o 16 | $(CC) -o $@ write_wishbone.c wishbone_wrapper.o 17 | 18 | test_wishbone : test_wishbone.c wishbone_wrapper.o 19 | $(CC) -o $@ test_wishbone.c wishbone_wrapper.o 20 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logipi/read_wishbone.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include "wishbone_wrapper.h" 12 | 13 | 14 | int main(int argc, char ** argv){ 15 | int fd, address ; 16 | unsigned short i ; 17 | unsigned short readVal ; 18 | if(argc < 1){ 19 | printf("not enough arguments \n"); 20 | return 0 ; 21 | } 22 | address = (int) strtol(argv[1], NULL, 0); 23 | wishbone_read(&readVal, 2, address); 24 | printf("0x%x \n", readVal); 25 | return 0 ; 26 | } 27 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logipi/test_wishbone.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include "wishbone_wrapper.h" 12 | 13 | int main(int argc, char ** argv){ 14 | int address ; 15 | unsigned short i ; 16 | unsigned short writeVals [2048] ; 17 | struct timeval temp1,temp2; 18 | long elapsed_u_sec,elapsed_s_sec,elapsed_m_time,elapsed_u_time; 19 | gettimeofday(&temp1,NULL); 20 | if((i = wishbone_write(writeVals, 2048, 0)) < 2048){ 21 | printf("Write error !, returned %d \n", i); 22 | } 23 | gettimeofday(&temp2,NULL); 24 | elapsed_s_sec=temp2.tv_sec-temp1.tv_sec; 25 | elapsed_u_sec=temp2.tv_usec-temp1.tv_usec; 26 | elapsed_u_time=(elapsed_s_sec)*100000+elapsed_u_sec; 27 | printf("Time in Microsecond=%ld \n",elapsed_u_time); 28 | printf("W Speed=====%d KB/Sec \n",(2048*1000)/elapsed_u_time ); 29 | return 0 ; 30 | } 31 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logipi/wishbone_wrapper.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | unsigned int wishbone_write(unsigned char * buffer, unsigned int length, unsigned int address); 6 | unsigned int wishbone_read(unsigned char * buffer, unsigned int length, unsigned int address); 7 | -------------------------------------------------------------------------------- /logi-wishbone/sw/logipi/write_wishbone.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include "wishbone_wrapper.h" 12 | 13 | 14 | int main(int argc, char ** argv){ 15 | int fd, address ; 16 | unsigned short i ; 17 | unsigned short writeVal ; 18 | if(argc < 2){ 19 | printf("not enough arguments \n"); 20 | return 0 ; 21 | } 22 | address = (int) strtol(argv[1], NULL, 0); 23 | writeVal = (unsigned short) strtol(argv[2], NULL, 0); 24 | printf("Writing 0x%x @ 0x%x \n", writeVal, address); 25 | if(wishbone_write(&writeVal, 2, address) < 2){ 26 | printf("Write error !"); 27 | } 28 | close(fd); 29 | return 0 ; 30 | } 31 | -------------------------------------------------------------------------------- /logi-wishbone/sw/test_wishbone.py: -------------------------------------------------------------------------------- 1 | 2 | import time, math 3 | from logi import * 4 | 5 | print "Demo Details:******************************************************************" 6 | print "* The user can modify the .py file to experiment with accessing the FPGA by reading and writing data on the FPGA. See the Register set defined in the README.TXT file" 7 | print "* This demo writes values to the FPGA PWM peripherals and increment the duty cycle sinusoidally. You can see the value output being displayed on LED0" 8 | print "* key CTL C to exit the program" 9 | print "*****************************************************************************" 10 | 11 | 12 | 13 | logiWrite(0x0008, (0x04, 0x00)) 14 | logiWrite(0x0009, (0x00, 0x08)) 15 | t = 0 16 | while True: 17 | val = abs(int(0x0800 * math.sin(t))) 18 | logiWrite(0x000B, ((val & 0x00FF), (val >> 7))) 19 | time.sleep(0.01) 20 | t = t + 0.01 21 | -------------------------------------------------------------------------------- /logipi-gpio_example/hw/hdl/logipi_gpio.v: -------------------------------------------------------------------------------- 1 | // Blink two LEDs 2 | // (c) KNJN LLC - fpga4fun.com 3 | 4 | module logipi_gpio(OSC_FPGA, LED, rpi_gpio); 5 | input OSC_FPGA; 6 | input rpi_gpio; 7 | output [1:0] LED; 8 | 9 | reg [31:0] cnt; 10 | always @(posedge OSC_FPGA) cnt <= cnt + 32'h1; 11 | assign LED[0] = ~cnt[22] & ~cnt[20]; 12 | // LED1 depends on RPi GPIO 13 | assign LED[1] = cnt[25-(rpi_gpio << 2)]; 14 | endmodule -------------------------------------------------------------------------------- /logipi-gpio_example/hw/hdl/logipi_r1_5.ucf: -------------------------------------------------------------------------------- 1 | ##### Grouping Constraints ##### 2 | NET OSC_FPGA TNM_NET = clk50_grp; 3 | 4 | ##### Clock Period Constraints ##### 5 | TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns; 6 | 7 | ####################### 8 | # Pin LOC Constraints # 9 | ###################### 10 | 11 | ##### Bank 2 ##### 12 | NET "LED<0>" LOC = "P105" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D6 13 | NET "LED<1>" LOC = "P104" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D7 14 | NET "RPI_GPIO" LOC = "P81" | IOSTANDARD = LVTTL; #SHARED WITH ARD_D7 15 | NET "OSC_FPGA" LOC = "P85" | IOSTANDARD = LVTTL; 16 | -------------------------------------------------------------------------------- /logipi-gpio_example/hw/work/logipi_gpio_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logipi-gpio_example/hw/work/logipi_gpio.ncd 3 | OUTFILE=/home/jpiat/development/FPGA/logi-family/logi-projects/logipi-gpio_example/hw/work/logipi_gpio.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx9-3tqg144 6 | WORKINGDIR=/home/jpiat/development/FPGA/logi-family/logi-projects/logipi-gpio_example/hw/work 7 | LICENSE=WebPack 8 | USER_INFO=__174162038_174162039_174422429 9 | -------------------------------------------------------------------------------- /picoblaze_s6_basic/hdl/kcpsm6.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-logi/logi-projects/481f61b5f1e967c9a95ba5c28e62cb6bfac97462/picoblaze_s6_basic/hdl/kcpsm6.vhd -------------------------------------------------------------------------------- /picoblaze_s6_basic/psm/ROM_form.vhd: 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/sump-logi-analyzer/client/Makefile: -------------------------------------------------------------------------------- 1 | all: 2 | jar cfm analyzer.jar \ 3 | Manifest.txt \ 4 | org/sump/analyzer/*.class \ 5 | org/sump/analyzer/tools/*.class \ 6 | org/sump/analyzer/icons/*.png \ 7 | org/sump/util/*.class \ 8 | -------------------------------------------------------------------------------- /sump-logi-analyzer/client/Manifest.txt: -------------------------------------------------------------------------------- 1 | Main-Class: org.sump.analyzer.Loader 2 | -------------------------------------------------------------------------------- /sump-logi-analyzer/client/doc/package-list: -------------------------------------------------------------------------------- 1 | org.sump.analyzer 2 | org.sump.analyzer.tools 3 | org.sump.util 4 | -------------------------------------------------------------------------------- /sump-logi-analyzer/client/doc/resources/inherit.gif: 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