├── .gitignore ├── README.md ├── mil1553-spi ├── .editorconfig ├── .gitattributes ├── .gitignore ├── LICENSE ├── README.md ├── doc │ ├── mil1553-ServiceProtocol.pdf │ └── mil1553-spi_diagram.pdf ├── readme │ ├── mil1553-spi_diagram.png │ └── mil1553-spi_test.png └── src │ ├── board │ ├── DE0 │ │ ├── AlteraMemory.qip │ │ ├── AlteraMemory.v │ │ ├── AlteraMemoryWrapper.sv │ │ ├── DE0_TOP.qpf │ │ ├── DE0_TOP.qsf │ │ ├── DE0_TOP.sdc │ │ ├── DE0_TOP.v │ │ ├── pll_100.ppf │ │ ├── pll_100.qip │ │ └── pll_100.v │ └── DE0_tests │ │ ├── MilLight │ │ ├── MilLight.sln │ │ ├── MilLight │ │ │ ├── FTD2XX_NET.XML │ │ │ ├── MilLight.csproj │ │ │ ├── MilLight │ │ │ │ ├── MilSpiBridge │ │ │ │ │ ├── IMilSpiBridge.cs │ │ │ │ │ ├── MilSpiBridge.cs │ │ │ │ │ └── SeviceProtocolBrige.cs │ │ │ │ ├── ServiceProtocol.cd │ │ │ │ └── ServiceProtocol │ │ │ │ │ ├── ExpirableObject.cs │ │ │ │ │ ├── MilFrame.cs │ │ │ │ │ ├── SPFrame.cs │ │ │ │ │ ├── SPReceiveReply.cs │ │ │ │ │ ├── SPReceiveRequest.cs │ │ │ │ │ ├── SPReply.cs │ │ │ │ │ ├── SPRequest.cs │ │ │ │ │ ├── SPResetRequest.cs │ │ │ │ │ ├── SPStatusReply.cs │ │ │ │ │ ├── SPStatusRequest.cs │ │ │ │ │ ├── SPTransmitRequest.cs │ │ │ │ │ ├── StreamExtensions.cs │ │ │ │ │ └── interfaces.cs │ │ │ ├── Properties │ │ │ │ └── AssemblyInfo.cs │ │ │ └── packages.config │ │ ├── MilTest │ │ │ ├── HardwareErrorTest.cs │ │ │ ├── HardwareTest.cs │ │ │ ├── MilTest.csproj │ │ │ ├── PacketGenerator.cs │ │ │ ├── Properties │ │ │ │ └── AssemblyInfo.cs │ │ │ └── ProtocolTest.cs │ │ └── lib │ │ │ ├── FTD2XX_NET.dll │ │ │ ├── MPSSELight.dll │ │ │ └── MPSSELight.dll.config │ │ └── batch_tests │ │ ├── SpiLight │ │ ├── FTD2XX_NET.dll │ │ ├── FluentCommandLineParser.dll │ │ ├── FluentCommandLineParser.xml │ │ ├── MPSSELight.dll │ │ ├── SpiLight.exe │ │ └── SpiLight.exe.config │ │ ├── cmdstart.bat │ │ ├── milTest.bat │ │ ├── sequence_1_send.spi_txt │ │ ├── sequence_2_statusT.spi_txt │ │ ├── sequence_3_statusR.spi_txt │ │ └── sequence_4_receive.spi_txt │ ├── docs │ ├── mil1553-ServiceProtocol.odt │ └── mil1553-spi_diagram.odg │ └── mil1553-spi │ ├── MemoryArbiter.sv │ ├── MemoryBlock.sv │ ├── MemoryReader.sv │ ├── MemoryRingBuffer.sv │ ├── MemoryWriter.sv │ ├── ServiceProtocol.sv │ ├── ServiceProtocolDecoder.sv │ ├── ServiceProtocolEncoder.sv │ ├── controlBus.sv │ ├── controlReset.sv │ ├── controlStatus.sv │ ├── interfaces.sv │ ├── ipMilSpiDoubleA.sv │ ├── ipMilSpiDoubleB.sv │ ├── ipMilSpiSingle.sv │ ├── linkMil.sv │ ├── linkSpi.sv │ ├── milConnectionPoint.sv │ ├── milData.sv │ ├── milEncoderDecoder.sv │ ├── milReceiver.sv │ ├── milSpiBlock.sv │ ├── milSpiBlock2.sv │ ├── milTransceiver.sv │ ├── milTransmitter.sv │ ├── settings.sv │ ├── signal.sv │ ├── spiCore.sv │ └── spiReceiver.sv ├── mymil ├── mil.v ├── mil_control.v ├── mil_receiver.v ├── mil_transmitter.v ├── mymil.qpf └── mymil.qsf └── sumilink └── pervichNsignal.mdl /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | *.do 3 | *.wlf 4 | *.o 5 | *.afx 6 | *.crf 7 | *.htm 8 | *.tra 9 | *.dep 10 | *.lst 11 | *.o 12 | *.crf 13 | *.autosave 14 | 15 | **/*.o 16 | **/*.afx 17 | **/*.crf 18 | **/*.htm 19 | **/*.tra 20 | **/*.dep 21 | **/*.lst 22 | 23 | **/**/*.o 24 | **/**/*.afx 25 | **/**/*.crf 26 | **/**/*.htm 27 | **/**/*.tra 28 | **/**/*.dep 29 | **/**/*.lst 30 | *.mif 31 | **/*.mif 32 | **/**/*.mif 33 | **/**/**/*.mif 34 | 35 | default.txt 36 | **/default.txt 37 | **/**/default.txt 38 | **/**/**/default.txt 39 | <<<<<<< Updated upstream 40 | input300000.txt 41 | **/input300000.txt 42 | **/**/input300000.txt 43 | **/**/**/input300000.txt 44 | 45 | 46 | ======= 47 | **/**/**/**/default.txt 48 | **/**/**/**/**/default.txt 49 | **/**/**/**/**/**/default.txt 50 | **/**/**/**/**/**/**/default.txt 51 | **/**/**/**/**/**/**/**/default.txt 52 | **/**/**/**/**/**/**/**/**/default.txt 53 | >>>>>>> Stashed changes 54 | 55 | !binary/Fibonacci.HEX 56 | !binary/Fibonacci2.HEX 57 | !binary/ProgFLASH.exe 58 | 59 | *.ddb 60 | **/*.ddb 61 | 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**/*.r20* 123 | **/**/*.r20* 124 | **/**/**/*.r20* 125 | 126 | 127 | 128 | *.mdl.original 129 | **/*.mdl.original 130 | **/**/*.mdl.original 131 | **/**/**/*.mdl.original 132 | 133 | *.mdlxml 134 | **/*.mdlxml 135 | **/**/*.mdlxml 136 | **/**/**/*.mdlxml 137 | 138 | 139 | *.jic 140 | *.map 141 | 142 | *sopc_* 143 | *.jdi 144 | *.ptf.* 145 | *.sof 146 | *.pof 147 | *.qws 148 | *.smsg 149 | *_inst.vhd 150 | *_generation_script* 151 | *.done 152 | *.qarlog 153 | *.rpt 154 | *.summary 155 | *.qws 156 | *.cmp 157 | *.eqn 158 | *.html 159 | *.jpg 160 | *.bak 161 | *.qar 162 | *.sopc_builder 163 | 164 | *~ 165 | *.tcl 166 | *.pin 167 | *.stp 168 | # ignore Quartus II generated folders 169 | 170 | 171 | db/ 172 | incremental_db/ 173 | simulation/ 174 | timing/ 175 | testbench/ 176 | *_sim/ 177 | #modelsim 178 | 179 | 180 | **/wlft* 181 | **/_lib1* 182 | 183 | verilog.psm 184 | verilog.prw 185 | _primary* 186 | 187 | 188 | 189 | **/*.jic 190 | **/*.map 191 | 192 | **/*sopc_* 193 | **/*.jdi 194 | **/*.ptf.* 195 | **/*.sof 196 | **/*.pof 197 | **/*.qws 198 | **/*.smsg 199 | **/*_inst.vhd 200 | **/*_generation_script* 201 | **/*.done 202 | **/*.qarlog 203 | **/*.rpt 204 | **/*.summary 205 | **/*.qws 206 | **/*.cmp 207 | **/*.eqn 208 | **/*.html 209 | **/*.jpg 210 | **/*.bak 211 | **/*.qar 212 | **/*.sopc_builder 213 | 214 | **/*~ 215 | **/*.tcl 216 | **/*.pin 217 | 218 | # ignore Quartus II generated folders 219 | **/db/ 220 | **/incremental_db/ 221 | **/simulation/ 222 | **/timing/ 223 | **/testbench/ 224 | **/*_sim/ 225 | 226 | **/**/*.jic 227 | **/**/*.map 228 | **/**/*sopc_* 229 | **/**/*.jdi 230 | **/**/*.ptf.* 231 | **/**/*.sof 232 | **/**/*.pof 233 | **/**/*.qws 234 | **/**/*.smsg 235 | **/**/*_inst.vhd 236 | **/**/*_generation_script* 237 | **/**/*.done 238 | **/**/*.qarlog 239 | **/**/*.rpt 240 | **/**/*.summary 241 | **/**/*.qws 242 | **/**/*.cmp 243 | **/**/*.eqn 244 | **/**/*.html 245 | **/**/*.jpg 246 | **/**/*.bak 247 | **/**/*.qar 248 | **/**/*.sopc_builder 249 | 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-------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # mil-std-1553b-soc 2 | development interface mil-std-1553b for system on chip 3 | -------------------------------------------------------------------------------- /mil1553-spi/.editorconfig: -------------------------------------------------------------------------------- 1 | # Matches multiple files with brace expansion notation 2 | # Set default charset 3 | [*.{v,sv}] 4 | charset = utf-8 5 | indent_style = tab 6 | indent_size = 4 7 | trim_trailing_whitespace = true -------------------------------------------------------------------------------- /mil1553-spi/.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | 7 | # Standard to msysgit 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Backup files are not needed, 243 | # because we have git ;-) 244 | _UpgradeReport_Files/ 245 | Backup*/ 246 | UpgradeLog*.XML 247 | UpgradeLog*.htm 248 | 249 | # SQL Server files 250 | *.mdf 251 | *.ldf 252 | 253 | # Business Intelligence projects 254 | *.rdl.data 255 | *.bim.layout 256 | *.bim_*.settings 257 | 258 | # Microsoft Fakes 259 | FakesAssemblies/ 260 | 261 | # GhostDoc plugin setting file 262 | *.GhostDoc.xml 263 | 264 | # Node.js Tools for Visual Studio 265 | .ntvs_analysis.dat 266 | 267 | # Visual Studio 6 build log 268 | *.plg 269 | 270 | # Visual Studio 6 workspace options file 271 | *.opt 272 | 273 | # Visual Studio LightSwitch build output 274 | **/*.HTMLClient/GeneratedArtifacts 275 | **/*.DesktopClient/GeneratedArtifacts 276 | **/*.DesktopClient/ModelManifest.xml 277 | **/*.Server/GeneratedArtifacts 278 | **/*.Server/ModelManifest.xml 279 | _Pvt_Extensions 280 | 281 | # Paket dependency manager 282 | .paket/paket.exe 283 | paket-files/ 284 | 285 | # FAKE - F# Make 286 | .fake/ 287 | 288 | # JetBrains Rider 289 | .idea/ 290 | *.sln.iml 291 | 292 | -------------------------------------------------------------------------------- /mil1553-spi/LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2016 Stanislav Zhelnio 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /mil1553-spi/README.md: -------------------------------------------------------------------------------- 1 | # mil1553-spi 2 | MIL-STD-1553 <-> SPI bridge with internal memory buffer support. 3 | 4 | Available commands (see detailes in [/doc](/doc)): 5 | - transmit data to mil interface 6 | - get data, received from mil interface 7 | - status request 8 | - device reset 9 | 10 | **Attention**: it was not tested with real MIL-STD-1553 devices 11 | 12 | ## IP core block diagram 13 | ![Alt text](/readme/mil1553-spi_diagram.png?raw=true "diagram") 14 | ## Directory structure 15 | | Folder | Description | 16 | | --- | --- | 17 | | [/doc](/doc) | project documentation | 18 | | [/src/board/DE0](/src/board/DE0) | Altera and Terasic board specific code for hardware tests | 19 | | [/src/board/DE0_tests/batch_tests](/src/board/DE0_tests/batch_tests) | simple batch data transfer tests (SpiLight is used) | 20 | | [/src/board/DE0_tests/MilLight](/src/board/DE0_tests/MilLight) | bridge communication .NET library, Unit Test Project for automatic hardware testing | 21 | | [/src/mil1553-spi](/src/mil1553-spi) | mil1553-spi bridge IP cores SystemVerilog source code | 22 | | [/src/testbench](/src/testbench) | mil1553-spi bridge IP cores SystemVerilog testbenches | 23 | 24 | ## Hardware test configuration 25 | ![Alt text](/readme/mil1553-spi_test.png?raw=true "test diagram") 26 | 27 | ## Hardware test configuration build report 28 | ``` 29 | +---------------------------------------------------------------------------------+ 30 | ; Flow Summary ; 31 | +------------------------------------+--------------------------------------------+ 32 | ; Flow Status ; Successful - Sun Dec 04 17:52:03 2016 ; 33 | ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; 34 | ; Revision Name ; DE0_TOP ; 35 | ; Top-level Entity Name ; DE0_TOP ; 36 | ; Family ; Cyclone III ; 37 | ; Device ; EP3C16F484C6 ; 38 | ; Timing Models ; Final ; 39 | ; Total logic elements ; 2,077 / 15,408 ( 13 % ) ; 40 | ; Total combinational functions ; 1,960 / 15,408 ( 13 % ) ; 41 | ; Dedicated logic registers ; 837 / 15,408 ( 5 % ) ; 42 | ; Total registers ; 837 ; 43 | ; Total pins ; 252 / 347 ( 73 % ) ; 44 | ; Total virtual pins ; 0 ; 45 | ; Total memory bits ; 4,096 / 516,096 ( < 1 % ) ; 46 | ; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; 47 | ; Total PLLs ; 1 / 4 ( 25 % ) ; 48 | +------------------------------------+--------------------------------------------+ 49 | ``` 50 | -------------------------------------------------------------------------------- /mil1553-spi/doc/mil1553-ServiceProtocol.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/doc/mil1553-ServiceProtocol.pdf -------------------------------------------------------------------------------- /mil1553-spi/doc/mil1553-spi_diagram.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/doc/mil1553-spi_diagram.pdf -------------------------------------------------------------------------------- /mil1553-spi/readme/mil1553-spi_diagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/readme/mil1553-spi_diagram.png -------------------------------------------------------------------------------- /mil1553-spi/readme/mil1553-spi_test.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/readme/mil1553-spi_test.png -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0/AlteraMemory.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "AlteraMemory.v"] 4 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0/AlteraMemory.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: AlteraMemory.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.1.0 Build 162 10/23/2013 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module AlteraMemory ( 40 | clock, 41 | data, 42 | rdaddress, 43 | rden, 44 | wraddress, 45 | wren, 46 | q); 47 | 48 | input clock; 49 | input [15:0] data; 50 | input [7:0] rdaddress; 51 | input rden; 52 | input [7:0] wraddress; 53 | input wren; 54 | output [15:0] q; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_off 57 | `endif 58 | tri1 clock; 59 | tri1 rden; 60 | tri0 wren; 61 | `ifndef ALTERA_RESERVED_QIS 62 | // synopsys translate_on 63 | `endif 64 | 65 | wire [15:0] sub_wire0; 66 | wire [15:0] q = sub_wire0[15:0]; 67 | 68 | altsyncram altsyncram_component ( 69 | .address_a (wraddress), 70 | .clock0 (clock), 71 | .data_a (data), 72 | .rden_b (rden), 73 | .wren_a (wren), 74 | .address_b (rdaddress), 75 | .q_b (sub_wire0), 76 | .aclr0 (1'b0), 77 | .aclr1 (1'b0), 78 | .addressstall_a (1'b0), 79 | .addressstall_b (1'b0), 80 | .byteena_a (1'b1), 81 | .byteena_b (1'b1), 82 | .clock1 (1'b1), 83 | .clocken0 (1'b1), 84 | .clocken1 (1'b1), 85 | .clocken2 (1'b1), 86 | .clocken3 (1'b1), 87 | .data_b ({16{1'b1}}), 88 | .eccstatus (), 89 | .q_a (), 90 | .rden_a (1'b1), 91 | .wren_b (1'b0)); 92 | defparam 93 | altsyncram_component.address_aclr_b = "NONE", 94 | altsyncram_component.address_reg_b = "CLOCK0", 95 | altsyncram_component.clock_enable_input_a = "BYPASS", 96 | altsyncram_component.clock_enable_input_b = "BYPASS", 97 | altsyncram_component.clock_enable_output_b = "BYPASS", 98 | altsyncram_component.intended_device_family = "Cyclone III", 99 | altsyncram_component.lpm_type = "altsyncram", 100 | altsyncram_component.numwords_a = 256, 101 | altsyncram_component.numwords_b = 256, 102 | altsyncram_component.operation_mode = "DUAL_PORT", 103 | altsyncram_component.outdata_aclr_b = "NONE", 104 | altsyncram_component.outdata_reg_b = "CLOCK0", 105 | altsyncram_component.power_up_uninitialized = "FALSE", 106 | altsyncram_component.rdcontrol_reg_b = "CLOCK0", 107 | altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", 108 | altsyncram_component.widthad_a = 8, 109 | altsyncram_component.widthad_b = 8, 110 | altsyncram_component.width_a = 16, 111 | altsyncram_component.width_b = 16, 112 | altsyncram_component.width_byteena_a = 1; 113 | 114 | 115 | endmodule 116 | 117 | // ============================================================ 118 | // CNX file retrieval info 119 | // ============================================================ 120 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 121 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 122 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 123 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 124 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 125 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 126 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 127 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 128 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 129 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 130 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 131 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 132 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 133 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 134 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 135 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 136 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 137 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 138 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 139 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 140 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 141 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 142 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 143 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" 144 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" 145 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 146 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 147 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 148 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 149 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 150 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096" 151 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 152 | // Retrieval info: PRIVATE: MIFfilename STRING "" 153 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" 154 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 155 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" 156 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 157 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 158 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 159 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 160 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 161 | // Retrieval info: PRIVATE: REGq NUMERIC "1" 162 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" 163 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 164 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 165 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 166 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 167 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 168 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 169 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 170 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" 171 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" 172 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" 173 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" 174 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 175 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" 176 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 177 | // Retrieval info: PRIVATE: enable NUMERIC "0" 178 | // Retrieval info: PRIVATE: rden NUMERIC "1" 179 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 180 | // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" 181 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 182 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 183 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 184 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 185 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 186 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 187 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 188 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" 189 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" 190 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 191 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" 192 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 193 | // Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0" 194 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 195 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 196 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" 197 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" 198 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" 199 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 200 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 201 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" 202 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" 203 | // Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]" 204 | // Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" 205 | // Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]" 206 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" 207 | // Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0 208 | // Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0 209 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 210 | // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 211 | // Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0 212 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 213 | // Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 214 | // Retrieval info: GEN_FILE: TYPE_NORMAL AlteraMemory.v TRUE 215 | // Retrieval info: GEN_FILE: TYPE_NORMAL AlteraMemory.inc FALSE 216 | // Retrieval info: GEN_FILE: TYPE_NORMAL AlteraMemory.cmp FALSE 217 | // Retrieval info: GEN_FILE: TYPE_NORMAL AlteraMemory.bsf FALSE 218 | // Retrieval info: GEN_FILE: TYPE_NORMAL AlteraMemory_inst.v FALSE 219 | // Retrieval info: GEN_FILE: TYPE_NORMAL AlteraMemory_bb.v FALSE 220 | // Retrieval info: LIB_FILE: altera_mf 221 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0/AlteraMemoryWrapper.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef AMW_INCLUDE 8 | `define AMW_INCLUDE 9 | 10 | //memory helper 11 | module AlteraMemoryWrapper( input bit nRst, clk, 12 | IMemory.memory mem); 13 | 14 | AlteraMemory memory( clk, mem.wr_data, 15 | mem.rd_addr[7:0], mem.rd_enable, 16 | mem.wr_addr[7:0], mem.wr_enable, 17 | mem.rd_data); 18 | 19 | logic we; 20 | logic re [1:0]; 21 | assign mem.busy = we | mem.wr_enable | re[1] | re[0] | mem.rd_enable; 22 | 23 | always_ff @ (posedge clk) begin 24 | if(!nRst) 25 | {we, re[1], re[0]} <= '0; 26 | else 27 | {we, mem.rd_ready, re[1], re[0]} 28 | <= {mem.wr_enable, re[1], re[0], mem.rd_enable}; 29 | end 30 | 31 | endmodule 32 | 33 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0/DE0_TOP.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2008 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "8.0" 18 | DATE = "19:06:14 March 06, 2009" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "DE0_TOP" 24 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0/DE0_TOP.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************ 2 | # THIS IS A WIZARD-GENERATED FILE. 3 | # 4 | # Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 5 | # 6 | #************************************************************ 7 | 8 | # Copyright (C) 1991-2013 Altera Corporation 9 | # Your use of Altera Corporation's design tools, logic functions 10 | # and other software and tools, and its AMPP partner logic 11 | # functions, and any output files from any of the foregoing 12 | # (including device programming or simulation files), and any 13 | # associated documentation or information are expressly subject 14 | # to the terms and conditions of the Altera Program License 15 | # Subscription Agreement, Altera MegaCore Function License 16 | # Agreement, or other applicable license agreement, including, 17 | # without limitation, that your use is for the sole purpose of 18 | # programming logic devices manufactured by Altera and sold by 19 | # Altera or its authorized distributors. Please refer to the 20 | # applicable agreement for further details. 21 | 22 | 23 | 24 | # Clock constraints 25 | 26 | create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}] 27 | 28 | 29 | # Automatically constrain PLL and other generated clocks 30 | derive_pll_clocks -create_base_clocks 31 | 32 | # Automatically calculate clock uncertainty to jitter and other effects. 33 | derive_clock_uncertainty 34 | 35 | # tsu/th constraints 36 | 37 | # tco constraints 38 | 39 | # tpd constraints 40 | 41 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0/DE0_TOP.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // Copyright (c) 2009 by Terasic Technologies Inc. 3 | // -------------------------------------------------------------------- 4 | // 5 | // Permission: 6 | // 7 | // Terasic grants permission to use and modify this code for use 8 | // in synthesis for all Terasic Development Boards and Altera Development 9 | // Kits made by Terasic. Other use of this code, including the selling 10 | // ,duplication, or modification of any portion is strictly prohibited. 11 | // 12 | // Disclaimer: 13 | // 14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference 15 | // which illustrates how these types of functions can be implemented. 16 | // It is the user's responsibility to verify their design for 17 | // consistency and functionality through the use of formal 18 | // verification methods. Terasic provides no warranty regarding the use 19 | // or functionality of this code. 20 | // 21 | // -------------------------------------------------------------------- 22 | // 23 | // Terasic Technologies Inc 24 | // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, 25 | // HsinChu County, Taiwan 26 | // 302 27 | // 28 | // web: http://www.terasic.com/ 29 | // email: support@terasic.com 30 | // 31 | // -------------------------------------------------------------------- 32 | // 33 | // Major Functions: DE0 TOP 34 | // 35 | // -------------------------------------------------------------------- 36 | // 37 | // Revision History : 38 | // -------------------------------------------------------------------- 39 | // Ver :| Author :| Mod. Date :| Changes Made: 40 | 41 | // -------------------------------------------------------------------- 42 | 43 | 44 | module DE0_TOP 45 | ( 46 | //////////////////// Clock Input //////////////////// 47 | CLOCK_50, // 50 MHz 48 | CLOCK_50_2, // 50 MHz 49 | //////////////////// Push Button //////////////////// 50 | BUTTON, // Pushbutton[2:0] 51 | //////////////////// DPDT Switch //////////////////// 52 | SW, // Toggle Switch[9:0] 53 | //////////////////// 7-SEG Dispaly //////////////////// 54 | HEX0_D, // Seven Segment Digit 0 55 | HEX0_DP, // Seven Segment Digit DP 0 56 | HEX1_D, // Seven Segment Digit 1 57 | HEX1_DP, // Seven Segment Digit DP 1 58 | HEX2_D, // Seven Segment Digit 2 59 | HEX2_DP, // Seven Segment Digit DP 2 60 | HEX3_D, // Seven Segment Digit 3 61 | HEX3_DP, // Seven Segment Digit DP 3 62 | //////////////////////// LED //////////////////////// 63 | LEDG, // LED Green[9:0] 64 | //////////////////////// UART //////////////////////// 65 | UART_TXD, // UART Transmitter 66 | UART_RXD, // UART Receiver 67 | UART_CTS, // UART Clear To Send 68 | UART_RTS, // UART Request To Send 69 | ///////////////////// SDRAM Interface //////////////// 70 | DRAM_DQ, // SDRAM Data bus 16 Bits 71 | DRAM_ADDR, // SDRAM Address bus 13 Bits 72 | DRAM_LDQM, // SDRAM Low-byte Data Mask 73 | DRAM_UDQM, // SDRAM High-byte Data Mask 74 | DRAM_WE_N, // SDRAM Write Enable 75 | DRAM_CAS_N, // SDRAM Column Address Strobe 76 | DRAM_RAS_N, // SDRAM Row Address Strobe 77 | DRAM_CS_N, // SDRAM Chip Select 78 | DRAM_BA_0, // SDRAM Bank Address 0 79 | DRAM_BA_1, // SDRAM Bank Address 1 80 | DRAM_CLK, // SDRAM Clock 81 | DRAM_CKE, // SDRAM Clock Enable 82 | //////////////////// Flash Interface //////////////// 83 | FL_DQ, // FLASH Data bus 15 Bits 84 | FL_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1 85 | FL_ADDR, // FLASH Address bus 22 Bits 86 | FL_WE_N, // FLASH Write Enable 87 | FL_RST_N, // FLASH Reset 88 | FL_OE_N, // FLASH Output Enable 89 | FL_CE_N, // FLASH Chip Enable 90 | FL_WP_N, // FLASH Hardware Write Protect 91 | FL_BYTE_N, // FLASH Selects 8/16-bit mode 92 | FL_RY, // FLASH Ready/Busy 93 | //////////////////// LCD Module 16X2 //////////////// 94 | LCD_BLON, // LCD Back Light ON/OFF 95 | LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read 96 | LCD_EN, // LCD Enable 97 | LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data 98 | LCD_DATA, // LCD Data bus 8 bits 99 | //////////////////// SD_Card Interface //////////////// 100 | SD_DAT0, // SD Card Data 0 101 | SD_DAT3, // SD Card Data 3 102 | SD_CMD, // SD Card Command Signal 103 | SD_CLK, // SD Card Clock 104 | SD_WP_N, // SD Card Write Protect 105 | //////////////////// PS2 //////////////////////////// 106 | PS2_KBDAT, // PS2 Keyboard Data 107 | PS2_KBCLK, // PS2 Keyboard Clock 108 | PS2_MSDAT, // PS2 Mouse Data 109 | PS2_MSCLK, // PS2 Mouse Clock 110 | //////////////////// VGA //////////////////////////// 111 | VGA_HS, // VGA H_SYNC 112 | VGA_VS, // VGA V_SYNC 113 | VGA_R, // VGA Red[3:0] 114 | VGA_G, // VGA Green[3:0] 115 | VGA_B, // VGA Blue[3:0] 116 | //////////////////// GPIO //////////////////////////// 117 | GPIO0_CLKIN, // GPIO Connection 0 Clock In Bus 118 | GPIO0_CLKOUT, // GPIO Connection 0 Clock Out Bus 119 | GPIO0_D, // GPIO Connection 0 Data Bus 120 | GPIO1_CLKIN, // GPIO Connection 1 Clock In Bus 121 | GPIO1_CLKOUT, // GPIO Connection 1 Clock Out Bus 122 | GPIO1_D // GPIO Connection 1 Data Bus 123 | ); 124 | 125 | //////////////////////// Clock Input //////////////////////// 126 | input CLOCK_50; // 50 MHz 127 | input CLOCK_50_2; // 50 MHz 128 | //////////////////////// Push Button //////////////////////// 129 | input [2:0] BUTTON; // Pushbutton[2:0] 130 | //////////////////////// DPDT Switch //////////////////////// 131 | input [9:0] SW; // Toggle Switch[9:0] 132 | //////////////////////// 7-SEG Dispaly //////////////////////// 133 | output [6:0] HEX0_D; // Seven Segment Digit 0 134 | output HEX0_DP; // Seven Segment Digit DP 0 135 | output [6:0] HEX1_D; // Seven Segment Digit 1 136 | output HEX1_DP; // Seven Segment Digit DP 1 137 | output [6:0] HEX2_D; // Seven Segment Digit 2 138 | output HEX2_DP; // Seven Segment Digit DP 2 139 | output [6:0] HEX3_D; // Seven Segment Digit 3 140 | output HEX3_DP; // Seven Segment Digit DP 3 141 | //////////////////////////// LED //////////////////////////// 142 | output [9:0] LEDG; // LED Green[9:0] 143 | //////////////////////////// UART //////////////////////////// 144 | output UART_TXD; // UART Transmitter 145 | input UART_RXD; // UART Receiver 146 | output UART_CTS; // UART Clear To Send 147 | input UART_RTS; // UART Request To Send 148 | /////////////////////// SDRAM Interface //////////////////////// 149 | inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits 150 | output [12:0] DRAM_ADDR; // SDRAM Address bus 13 Bits 151 | output DRAM_LDQM; // SDRAM Low-byte Data Mask 152 | output DRAM_UDQM; // SDRAM High-byte Data Mask 153 | output DRAM_WE_N; // SDRAM Write Enable 154 | output DRAM_CAS_N; // SDRAM Column Address Strobe 155 | output DRAM_RAS_N; // SDRAM Row Address Strobe 156 | output DRAM_CS_N; // SDRAM Chip Select 157 | output DRAM_BA_0; // SDRAM Bank Address 0 158 | output DRAM_BA_1; // SDRAM Bank Address 1 159 | output DRAM_CLK; // SDRAM Clock 160 | output DRAM_CKE; // SDRAM Clock Enable 161 | //////////////////////// Flash Interface //////////////////////// 162 | inout [14:0] FL_DQ; // FLASH Data bus 15 Bits 163 | inout FL_DQ15_AM1; // FLASH Data bus Bit 15 or Address A-1 164 | output [21:0] FL_ADDR; // FLASH Address bus 22 Bits 165 | output FL_WE_N; // FLASH Write Enable 166 | output FL_RST_N; // FLASH Reset 167 | output FL_OE_N; // FLASH Output Enable 168 | output FL_CE_N; // FLASH Chip Enable 169 | output FL_WP_N; // FLASH Hardware Write Protect 170 | output FL_BYTE_N; // FLASH Selects 8/16-bit mode 171 | input FL_RY; // FLASH Ready/Busy 172 | //////////////////// LCD Module 16X2 //////////////////////////// 173 | inout [7:0] LCD_DATA; // LCD Data bus 8 bits 174 | output LCD_BLON; // LCD Back Light ON/OFF 175 | output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read 176 | output LCD_EN; // LCD Enable 177 | output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data 178 | //////////////////// SD Card Interface //////////////////////// 179 | inout SD_DAT0; // SD Card Data 0 180 | inout SD_DAT3; // SD Card Data 3 181 | inout SD_CMD; // SD Card Command Signal 182 | output SD_CLK; // SD Card Clock 183 | input SD_WP_N; // SD Card Write Protect 184 | //////////////////////// PS2 //////////////////////////////// 185 | inout PS2_KBDAT; // PS2 Keyboard Data 186 | inout PS2_KBCLK; // PS2 Keyboard Clock 187 | inout PS2_MSDAT; // PS2 Mouse Data 188 | inout PS2_MSCLK; // PS2 Mouse Clock 189 | //////////////////////// VGA //////////////////////////// 190 | output VGA_HS; // VGA H_SYNC 191 | output VGA_VS; // VGA V_SYNC 192 | output [3:0] VGA_R; // VGA Red[3:0] 193 | output [3:0] VGA_G; // VGA Green[3:0] 194 | output [3:0] VGA_B; // VGA Blue[3:0] 195 | //////////////////////// GPIO //////////////////////////////// 196 | input [1:0] GPIO0_CLKIN; // GPIO Connection 0 Clock In Bus 197 | output [1:0] GPIO0_CLKOUT; // GPIO Connection 0 Clock Out Bus 198 | inout [31:0] GPIO0_D; // GPIO Connection 0 Data Bus 199 | input [1:0] GPIO1_CLKIN; // GPIO Connection 1 Clock In Bus 200 | output [1:0] GPIO1_CLKOUT; // GPIO Connection 1 Clock Out Bus 201 | inout [31:0] GPIO1_D; // GPIO Connection 1 Data Bus 202 | 203 | //======================================================= 204 | // REG/WIRE declarations 205 | //======================================================= 206 | 207 | reg clk100; 208 | 209 | //IO interfaces 210 | ISpi spi(); 211 | IMilStd mil0(); 212 | IMilStd mil1(); 213 | IMemory mem(); 214 | 215 | //connection mil's to each other 216 | MilConnectionPoint mcp(mil0,mil1); 217 | 218 | //debug output 219 | assign GPIO0_D[5] = mil0.RXin; 220 | assign GPIO0_D[6] = mil0.nRXin; 221 | 222 | assign spi.master.nCS = GPIO0_D[0]; 223 | assign spi.master.mosi = GPIO0_D[2]; 224 | assign spi.master.sck = GPIO0_D[3]; 225 | assign GPIO0_D[4] = spi.master.miso; 226 | 227 | assign GPIO1_D[0] = clk100; 228 | assign LEDG[0] = clk100; 229 | assign LEDG[1] = mil0.RXin; 230 | assign LEDG[2] = !spi.master.nCS; 231 | assign LEDG[3] = spi.master.mosi; 232 | assign LEDG[4] = spi.master.sck; 233 | assign LEDG[5] = spi.master.miso; 234 | 235 | //======================================================= 236 | // Structural coding 237 | //======================================================= 238 | 239 | defparam milSpi.milSpiBlock.SPI_BLOCK_ADDR0 = 8'hAB; 240 | defparam milSpi.milSpiBlock.SPI_BLOCK_ADDR1 = 8'hAC; 241 | 242 | defparam milSpi.memoryBlock.RING2_0_MEM_START = 16'h00; 243 | defparam milSpi.memoryBlock.RING2_0_MEM_END = 16'h3E; 244 | defparam milSpi.memoryBlock.RING2_1_MEM_START = 16'h40; 245 | defparam milSpi.memoryBlock.RING2_1_MEM_END = 16'h7E; 246 | defparam milSpi.memoryBlock.RING2_2_MEM_START = 16'h80; 247 | defparam milSpi.memoryBlock.RING2_2_MEM_END = 16'hBE; 248 | defparam milSpi.memoryBlock.RING2_3_MEM_START = 16'hC0; 249 | defparam milSpi.memoryBlock.RING2_3_MEM_END = 16'hFE; 250 | 251 | pll_100 pll(CLOCK_50, clk100); 252 | 253 | IpMilSpiDoubleB milSpi( .clk(clk100), .nRst(BUTTON[0]), 254 | .spi(spi), 255 | .mil0(mil0), .mil1(mil1), 256 | .mbus(mem)); 257 | 258 | AlteraMemoryWrapper memory( .clk(clk100), .nRst(BUTTON[0]), 259 | .mem(mem)); 260 | 261 | endmodule -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0/pll_100.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0/pll_100.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_100.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_100_bb.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_100.ppf"] 6 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio 14 4 | VisualStudioVersion = 14.0.25420.1 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "MilTest", "MilTest\MilTest.csproj", "{87F310C4-C9B2-45A6-A31A-B90946563A8D}" 7 | EndProject 8 | Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "MilLight", "MilLight\MilLight.csproj", "{CF4EAF10-77A4-435D-B706-779275906BB0}" 9 | EndProject 10 | Global 11 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 12 | Debug|Any CPU = Debug|Any CPU 13 | Release|Any CPU = Release|Any CPU 14 | EndGlobalSection 15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 16 | {87F310C4-C9B2-45A6-A31A-B90946563A8D}.Debug|Any CPU.ActiveCfg = Debug|Any CPU 17 | {87F310C4-C9B2-45A6-A31A-B90946563A8D}.Debug|Any CPU.Build.0 = Debug|Any CPU 18 | {87F310C4-C9B2-45A6-A31A-B90946563A8D}.Release|Any CPU.ActiveCfg = Release|Any CPU 19 | {87F310C4-C9B2-45A6-A31A-B90946563A8D}.Release|Any CPU.Build.0 = Release|Any CPU 20 | {CF4EAF10-77A4-435D-B706-779275906BB0}.Debug|Any CPU.ActiveCfg = Debug|Any CPU 21 | {CF4EAF10-77A4-435D-B706-779275906BB0}.Debug|Any CPU.Build.0 = Debug|Any CPU 22 | {CF4EAF10-77A4-435D-B706-779275906BB0}.Release|Any CPU.ActiveCfg = Release|Any CPU 23 | {CF4EAF10-77A4-435D-B706-779275906BB0}.Release|Any CPU.Build.0 = Release|Any CPU 24 | EndGlobalSection 25 | GlobalSection(SolutionProperties) = preSolution 26 | HideSolutionNode = FALSE 27 | EndGlobalSection 28 | EndGlobal 29 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight.csproj: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | Debug 6 | AnyCPU 7 | {CF4EAF10-77A4-435D-B706-779275906BB0} 8 | Library 9 | Properties 10 | MilLight 11 | MilLight 12 | v4.5.2 13 | 512 14 | 15 | 16 | true 17 | full 18 | false 19 | bin\Debug\ 20 | DEBUG;TRACE 21 | prompt 22 | 4 23 | 24 | 25 | pdbonly 26 | true 27 | bin\Release\ 28 | TRACE 29 | prompt 30 | 4 31 | 32 | 33 | 34 | ..\packages\FTD2XX.Net.1.0.14\lib\FTD2XX_NET.dll 35 | True 36 | 37 | 38 | ..\lib\MPSSELight.dll 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 83 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/MilSpiBridge/IMilSpiBridge.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using MilTest.MilLight.ServiceProtocol; 8 | using System; 9 | using System.Collections.Generic; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.MilSpiBridge 15 | { 16 | public interface IMilSpiBridge 17 | { 18 | List Receive(byte addr, UInt16 size); 19 | List WaitReceive(byte addr, UInt16 size); 20 | void Transmit(byte addr, List data); 21 | void DeviceReset(byte addr); 22 | ISPStatus getDeviceStatus(byte addr); 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/MilSpiBridge/MilSpiBridge.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using MilTest.MilLight.ServiceProtocol; 8 | using System; 9 | using System.Collections.Generic; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading; 13 | using System.Threading.Tasks; 14 | 15 | namespace MilTest.MilLight.MilSpiBridge 16 | { 17 | public class MilSpiBridge : SeviceProtocolBrige, IMilSpiBridge 18 | { 19 | public class DeviceStatus : ISPStatus 20 | { 21 | public DeviceStatus(ushort receivedQueueSize, ushort transmitQueueSize, ushort spiErrorCount) 22 | { 23 | ReceivedQueueSize = receivedQueueSize; 24 | TransmitQueueSize = transmitQueueSize; 25 | SpiErrorCount = spiErrorCount; 26 | } 27 | public ushort ReceivedQueueSize { get; set; } 28 | public ushort TransmitQueueSize { get; set; } 29 | public ushort SpiErrorCount { get; set; } 30 | } 31 | 32 | public MilSpiBridge(string mpsseSerialNumber) : base(mpsseSerialNumber) { } 33 | 34 | const byte MilFrameSizeInWords = 2; 35 | 36 | private UInt16 packNum = 0; 37 | 38 | public void DeviceReset(byte addr) 39 | { 40 | transmitPacket(new SPResetRequest() { Addr = addr, PackNum = packNum++ }); 41 | } 42 | 43 | public void Transmit(byte addr, List data) 44 | { 45 | var packet = new SPTransmitRequest() { Addr = addr, Data = data, PackNum = packNum++ }; 46 | if (!packet.IsValid) 47 | throw new ArgumentException("Not valid frame data"); 48 | 49 | transmitPacket(packet); 50 | } 51 | 52 | public ISPStatus getDeviceStatus(byte addr) 53 | { 54 | var reply = (ISPStatus)transmitPacket(new SPStatusRequest() { Addr = addr, PackNum = packNum++ }, 55 | new SPStatusReply()); 56 | 57 | return new DeviceStatus((ushort)(reply.ReceivedQueueSize / MilFrameSizeInWords), 58 | (ushort)(reply.TransmitQueueSize / MilFrameSizeInWords), 59 | reply.SpiErrorCount); 60 | } 61 | 62 | public List Receive(byte addr, UInt16 size) 63 | { 64 | var reply = (ISPData)transmitPacket(new SPReceiveRequest() 65 | { 66 | Addr = addr, 67 | RequestedSize = (UInt16)(size * MilFrameSizeInWords), 68 | PackNum = packNum++ 69 | }, 70 | new SPReceiveReply()); 71 | return reply.Data; 72 | } 73 | 74 | public List WaitReceive(byte addr, UInt16 size) 75 | { 76 | const int maxWaitTime = 3000; 77 | const int recheckPeriod = 300; 78 | 79 | var cts = new CancellationTokenSource(maxWaitTime); 80 | 81 | return Task>.Run(() => 82 | { 83 | List result = new List(); 84 | while (!cts.Token.IsCancellationRequested) 85 | { 86 | result.AddRange(Receive(addr, (UInt16)(size - result.Count))); 87 | 88 | if (result.Count == size) 89 | break; 90 | 91 | Task.Delay(recheckPeriod); 92 | } 93 | 94 | return result; 95 | 96 | }, cts.Token).Result; 97 | } 98 | } 99 | } 100 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/MilSpiBridge/SeviceProtocolBrige.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using MilTest.MilLight.ServiceProtocol; 8 | using MPSSELight; 9 | using System; 10 | using System.Collections.Generic; 11 | using System.Diagnostics; 12 | using System.IO; 13 | using System.Linq; 14 | using System.Text; 15 | using System.Threading.Tasks; 16 | using static MPSSELight.MpsseDevice; 17 | 18 | namespace MilTest.MilLight.MilSpiBridge 19 | { 20 | public abstract class SeviceProtocolBrige 21 | { 22 | string mpsseSerialNumber; 23 | public SeviceProtocolBrige(string mpsseSerialNumber) 24 | { 25 | this.mpsseSerialNumber = mpsseSerialNumber; 26 | } 27 | 28 | MpsseDevice deviceConnect() 29 | { 30 | MpsseParams mp = new MpsseParams() { clockDevisor = 1 }; 31 | return new FT2232D(mpsseSerialNumber, mp); 32 | } 33 | 34 | protected void spiWrite(byte[] data) 35 | { 36 | using (MpsseDevice mpsse = deviceConnect()) 37 | { 38 | SpiDevice spi = new SpiDevice(mpsse); 39 | DebugWrite("transmitRaw: ", data); 40 | spi.write(data); 41 | } 42 | } 43 | 44 | protected byte[] spiReadWrite(byte[] data) 45 | { 46 | using (MpsseDevice mpsse = deviceConnect()) 47 | { 48 | SpiDevice spi = new SpiDevice(mpsse); 49 | 50 | DebugWrite("transmitRaw: ", data); 51 | byte[] rcvd = spi.readWrite(data); 52 | DebugWrite("receivedRaw: ", rcvd); 53 | return rcvd; 54 | } 55 | } 56 | 57 | protected object transmitPacket(ISerializable request, IDeserializable reply = null) 58 | { 59 | MemoryStream stream = new MemoryStream(); 60 | request.Serialize(stream); 61 | byte[] rawRequest = stream.ToArray(); 62 | 63 | if (reply == null) 64 | { 65 | DebugWrite("transmit: ", request); 66 | spiWrite(rawRequest); 67 | return null; 68 | } 69 | else 70 | { 71 | byte[] rawReply = spiReadWrite(rawRequest); 72 | stream = new MemoryStream(rawReply); 73 | reply.Deserialize(stream); 74 | 75 | DebugWrite("received: ", reply); 76 | 77 | if (!((IValidate)reply).IsValid) 78 | throw new CheckSumException(); 79 | 80 | return reply; 81 | } 82 | } 83 | 84 | public class CheckSumException : IOException 85 | { 86 | public CheckSumException() : base() { } 87 | public CheckSumException(string message) : base(message) { } 88 | public CheckSumException(string message, int hresult) : base(message, hresult) { } 89 | public CheckSumException(string message, Exception innerException) : base(message, innerException) { } 90 | } 91 | 92 | static void DebugWrite(string header, byte[] data) 93 | { 94 | Debug.Write(header); 95 | string hex = BitConverter.ToString(data).Replace("-", ""); 96 | Debug.WriteLine(hex); 97 | } 98 | 99 | static void DebugWrite(string header, object data) 100 | { 101 | Debug.Write(header); 102 | Debug.WriteLine(data); 103 | } 104 | } 105 | } 106 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol.cd: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | EACAAAAAEABAABAAAAAQAAAAAAAAAAAAAAAAAAAAAAA= 7 | MilLight\ServiceProtocol\ExpirableObject.cs 8 | 9 | 10 | 11 | 12 | 13 | BAAAAAQAAABAgAAEgAgAAgAAACJAAJAAAAAQAAAAAAA= 14 | MilLight\ServiceProtocol\MilFrame.cs 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | AAAQgAAAAAhAEAAMwBAABgAAAAIAAIAAIAAAEAAAAAA= 25 | MilLight\ServiceProtocol\SPFrame.cs 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | AAAQgAAAAAAAABAEQAAABAAAAAAAABAAAAAQMAAAAAA= 36 | MilLight\ServiceProtocol\SPReceiveReply.cs 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | AAAQgAAgAAAAAAAAQAAABAQgAAAAAAAAAAAAEAAAAAA= 47 | MilLight\ServiceProtocol\SPReceiveRequest.cs 48 | 49 | 50 | 51 | 52 | 53 | AAAAAAAAACAAAAAAACgAAAAAAABAAAAAAAAAIAQAAAA= 54 | MilLight\ServiceProtocol\SPReply.cs 55 | 56 | 57 | 58 | 59 | 60 | 61 | AAAAAAAAAAAAAAAAAAAAACQAACAAAAAAAAAAAAAAAAA= 62 | MilLight\ServiceProtocol\SPRequest.cs 63 | 64 | 65 | 66 | 67 | 68 | 69 | AAAAAAAAAAAAAAAAAAAABAAAAAAAAAAAAAAAAAAAAAA= 70 | MilLight\ServiceProtocol\SPResetRequest.cs 71 | 72 | 73 | 74 | 75 | 76 | AAAQgAAAAAAAAAAAQAgoBIAACACAAAAAAAAQMAAAAAA= 77 | MilLight\ServiceProtocol\SPStatusReply.cs 78 | 79 | 80 | 81 | 82 | 83 | 84 | AAAAAAAAAAAAAAAAAAAABCAAAAAAAAAAAAAAAAAAAAA= 85 | MilLight\ServiceProtocol\SPStatusRequest.cs 86 | 87 | 88 | 89 | 90 | 91 | AAAQgAAAAAAAABAEQAgABAQAAAAAABAAAAAQEAAAAAA= 92 | MilLight\ServiceProtocol\SPTransmitRequest.cs 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | AAAAAAAAAQAAAAAAAAAAAAAAAAAAAAAAAAABAAAAAAA= 103 | MilLight\ServiceProtocol\StreamExtensions.cs 104 | 105 | 106 | 107 | 108 | 109 | BAAAAAAAAAAAgAAAAAAAAgAAAAAAABAAAAAAAAAAAAA= 110 | MilLight\ServiceProtocol\interfaces.cs 111 | 112 | 113 | 114 | 115 | 116 | AAAAAAAAAAgAEAAAAAAABgAAAAAAAAAAIAAAAAAAAAA= 117 | MilLight\ServiceProtocol\interfaces.cs 118 | 119 | 120 | 121 | 122 | 123 | AAAAAAAAAAAAAAAAAAAAAAAAAAAAABAAAAAAAAAAAAA= 124 | MilLight\ServiceProtocol\interfaces.cs 125 | 126 | 127 | 128 | 129 | 130 | AAAAAAAAAAAAAAAAAAgIAIAAAAAAAAAAAAAAAAAAAAA= 131 | MilLight\ServiceProtocol\interfaces.cs 132 | 133 | 134 | 135 | 136 | 137 | AAAAAAAAAAAAAAAAAAAAAAAAACAAAAAAAAAAAAAAAAA= 138 | MilLight\ServiceProtocol\interfaces.cs 139 | 140 | 141 | 142 | 143 | 144 | AAAAAAAAAAAAAAAAAAAAAAAAAABAAAAAAAAAAAAAAAA= 145 | MilLight\ServiceProtocol\interfaces.cs 146 | 147 | 148 | 149 | 150 | 151 | AAAAAAAEAAAABAAAAEAAAAAAAAAAAAAQAAAAAAAAABA= 152 | MilLight\ServiceProtocol\interfaces.cs 153 | 154 | 155 | 156 | 157 | 158 | AAAAAAAAAAAAAAAAAAAEAAAAEABAAAAAAQAAAAAAAAA= 159 | MilLight\ServiceProtocol\interfaces.cs 160 | 161 | 162 | 163 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/ExpirableObject.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.Linq; 10 | using System.Runtime.CompilerServices; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public abstract class ExpirableObject 17 | { 18 | private bool isActual = false; 19 | public virtual bool IsActual 20 | { 21 | get { return isActual; } 22 | } 23 | 24 | protected void Expire() 25 | { 26 | isActual = false; 27 | } 28 | 29 | private bool inProgress = false; 30 | 31 | [MethodImpl(MethodImplOptions.Synchronized)] 32 | protected void Actualize() 33 | { 34 | if(inProgress) 35 | return; 36 | 37 | try 38 | { 39 | inProgress = true; 40 | 41 | if (IsActual) 42 | return; 43 | 44 | Actualization(); 45 | isActual = true; 46 | } 47 | finally 48 | { 49 | inProgress = false; 50 | } 51 | } 52 | 53 | protected virtual void Actualization() { } 54 | } 55 | } 56 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/MilFrame.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public class MilFrame : ExpirableObject, IMilFrame, ISerializable, IDeserializable 17 | { 18 | #region IMilFrame 19 | 20 | private MilType header = MilType.WDATA; 21 | public MilType Header 22 | { 23 | get 24 | { 25 | Actualize(); 26 | return header; 27 | } 28 | set 29 | { 30 | header = value; 31 | Expire(); 32 | } 33 | } 34 | 35 | private UInt16 data; 36 | public UInt16 Data 37 | { 38 | get 39 | { 40 | Actualize(); 41 | return data; 42 | } 43 | set 44 | { 45 | data = value; 46 | Expire(); 47 | } 48 | } 49 | 50 | public UInt16 Size 51 | { 52 | get { return 2; } //header + data 53 | } 54 | 55 | private UInt16 checkSum; 56 | public UInt16 CheckSum 57 | { 58 | get 59 | { 60 | Actualize(); 61 | return checkSum; 62 | } 63 | } 64 | 65 | public bool IsValid 66 | { 67 | get 68 | { 69 | return true; 70 | } 71 | } 72 | 73 | protected override void Actualization() 74 | { 75 | checkSum = (UInt16)((UInt16)header + data); 76 | } 77 | 78 | public override bool Equals(object obj) 79 | { 80 | MilFrame o = obj as MilFrame; 81 | if (o == null) 82 | return false; 83 | 84 | return o.Header == Header 85 | && o.Data == Data; 86 | } 87 | 88 | public override int GetHashCode() 89 | { 90 | int hash = 35; 91 | hash = hash * 28 + Header.GetHashCode(); 92 | hash = hash * 28 + Data.GetHashCode(); 93 | return hash; 94 | } 95 | 96 | #endregion IMilData 97 | 98 | #region IBinaryFrame 99 | 100 | public UInt16 Serialize(Stream stream) 101 | { 102 | stream.WriteUInt16((UInt16)Header); 103 | stream.WriteUInt16(Data); 104 | return Size; 105 | } 106 | 107 | public UInt16 Deserialize(Stream stream) 108 | { 109 | Header = (MilType)stream.ReadUInt16(); 110 | Data = stream.ReadUInt16(); 111 | return Size; 112 | } 113 | 114 | #endregion 115 | 116 | public override string ToString() 117 | { 118 | return string.Format("{0} {1:X4}", Header, Data); 119 | } 120 | } 121 | } 122 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPFrame.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public abstract class SPFrame : ExpirableObject, ISPFrame 17 | { 18 | #region ISPPacket 19 | 20 | protected const UInt16 HeaderSize = 4; 21 | 22 | private byte addr; 23 | public byte Addr 24 | { 25 | get 26 | { 27 | Actualize(); 28 | return addr; 29 | } 30 | set 31 | { 32 | addr = value; 33 | Expire(); 34 | } 35 | } 36 | 37 | public abstract SPCommand Command { get; } 38 | 39 | public UInt16 PackNum { get; set; } 40 | 41 | private UInt16 dataSize; 42 | public UInt16 DataSize 43 | { 44 | get 45 | { 46 | Actualize(); 47 | return dataSize; 48 | } 49 | 50 | protected set { dataSize = value; } 51 | } 52 | 53 | private UInt16 checkSum; 54 | public UInt16 CheckSum 55 | { 56 | get 57 | { 58 | Actualize(); 59 | return checkSum; 60 | } 61 | 62 | protected set { checkSum = value; } 63 | } 64 | 65 | protected override void Actualization() 66 | { 67 | dataSize = PayloadDataSize(); 68 | checkSum = (UInt16)((addr << 8) + (dataSize >> 8)); 69 | checkSum += (UInt16)((dataSize << 8) + ((byte)Command)); 70 | checkSum += PayloadCheckSum(); 71 | } 72 | 73 | protected virtual UInt16 PayloadDataSize() 74 | { 75 | return 0; 76 | } 77 | 78 | protected virtual UInt16 PayloadCheckSum() 79 | { 80 | return 0; 81 | } 82 | 83 | #endregion ISPPacket 84 | 85 | #region Equality 86 | public override bool Equals(object obj) 87 | { 88 | SPFrame o = obj as SPFrame; 89 | if (o == null) 90 | return false; 91 | 92 | return o.Addr == Addr 93 | && o.CheckSum == CheckSum 94 | && o.Command == Command 95 | && o.DataSize == DataSize 96 | && PayloadEquals(obj); 97 | } 98 | 99 | protected virtual bool PayloadEquals(object obj) 100 | { 101 | return true; 102 | } 103 | 104 | public override int GetHashCode() 105 | { 106 | int hash = 11; 107 | hash = hash * 24 + Addr.GetHashCode(); 108 | hash = hash * 24 + CheckSum.GetHashCode(); 109 | hash = hash * 24 + Command.GetHashCode(); 110 | hash = hash * 24 + DataSize.GetHashCode(); 111 | hash = hash * 24 + PayloadHashCode(); 112 | return hash; 113 | } 114 | 115 | protected virtual int PayloadHashCode() 116 | { 117 | return 0; 118 | } 119 | 120 | #endregion Equality 121 | 122 | public override string ToString() 123 | { 124 | return string.Format("addr:{0:X2} cmd:{1} size:{2:X4} crc:{3:X4} num:{4:X4}", Addr, Command, DataSize, CheckSum, PackNum); 125 | } 126 | } 127 | } 128 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPReceiveReply.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public class SPReceiveReply : SPReply, ISPData 17 | { 18 | public override SPCommand Command 19 | { 20 | get { return SPCommand.Receive; } 21 | } 22 | 23 | public override bool IsActual 24 | { 25 | get { return base.IsActual && !Data.Exists(a => !((ExpirableObject)a).IsActual); } 26 | } 27 | 28 | private List data = new List(); 29 | public List Data 30 | { 31 | get 32 | { 33 | Actualize(); 34 | return data; 35 | } 36 | set 37 | { 38 | data = value; 39 | Expire(); 40 | } 41 | } 42 | 43 | protected override ushort PayloadDataSize() 44 | { 45 | return (UInt16)(data.Sum(a => a.Size)); 46 | } 47 | 48 | protected override ushort PayloadCheckSum() 49 | { 50 | return (UInt16)(data.Sum(a => a.CheckSum)); 51 | } 52 | 53 | protected override bool PayloadEquals(object obj) 54 | { 55 | ISPData o = obj as ISPData; 56 | if (o == null) 57 | return false; 58 | 59 | return Enumerable.SequenceEqual(o.Data, Data); 60 | } 61 | 62 | protected override int PayloadHashCode() 63 | { 64 | return Data.GetHashCode(); 65 | } 66 | 67 | protected override ushort PayloadDeserialize(Stream stream, ushort payloadSize) 68 | { 69 | Data = new List(); 70 | 71 | for (int i = 0; i < payloadSize;) 72 | { 73 | MilFrame mp = new MilFrame(); 74 | UInt16 s = mp.Deserialize(stream); 75 | i += s; 76 | Data.Add(mp); 77 | } 78 | 79 | return payloadSize; 80 | } 81 | 82 | public override string ToString() 83 | { 84 | return string.Format("{0} data:{1}", base.ToString(), string.Join(", ", Data)); 85 | } 86 | } 87 | } 88 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPReceiveRequest.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public class SPReceiveRequest : SPRequest 17 | { 18 | public override SPCommand Command 19 | { 20 | get { return SPCommand.Receive; } 21 | } 22 | 23 | private UInt16 requestedSize = 0; 24 | public UInt16 RequestedSize 25 | { 26 | get 27 | { 28 | Actualize(); 29 | return requestedSize; 30 | } 31 | set 32 | { 33 | requestedSize = value; 34 | Expire(); 35 | } 36 | } 37 | 38 | protected override ushort PayloadDataSize() 39 | { 40 | return RequestedSize; 41 | } 42 | 43 | protected override ushort PayloadCheckSum() 44 | { 45 | return RequestedSize; 46 | } 47 | 48 | protected override bool PayloadEquals(object obj) 49 | { 50 | SPReceiveRequest o = obj as SPReceiveRequest; 51 | if (o == null) 52 | return false; 53 | 54 | return RequestedSize == o.RequestedSize; 55 | } 56 | 57 | protected override int PayloadHashCode() 58 | { 59 | return RequestedSize.GetHashCode(); 60 | } 61 | 62 | protected override ushort PayloadSerialize(Stream stream) 63 | { 64 | for (int i = 0; i < RequestedSize; i++) 65 | stream.WriteUInt16(0); 66 | return RequestedSize; 67 | } 68 | } 69 | } 70 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPReply.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public abstract class SPReply : SPFrame, IDeserializable, IValidate 17 | { 18 | public UInt16 Deserialize(Stream stream) 19 | { 20 | byte firstSeqByte = 0; 21 | do 22 | { 23 | int data = stream.ReadByte(); 24 | firstSeqByte = (byte)data; 25 | } 26 | while (firstSeqByte == 0); 27 | 28 | Addr = firstSeqByte; 29 | 30 | UInt16 payloadSize = stream.ReadUInt16(); 31 | DeserializedCommand = (SPCommand)stream.ReadByte(); 32 | 33 | UInt16 osize = HeaderSize; 34 | osize += PayloadDeserialize(stream, payloadSize); 35 | 36 | DeserializedCheckSum = stream.ReadUInt16(); 37 | PackNum = stream.ReadUInt16(); 38 | 39 | return osize; 40 | } 41 | 42 | protected virtual UInt16 PayloadDeserialize(Stream stream, ushort payloadSize) 43 | { 44 | return 0; 45 | } 46 | 47 | private UInt16? DeserializedCheckSum = null; 48 | private SPCommand? DeserializedCommand = null; 49 | 50 | public bool IsValid 51 | { 52 | get 53 | { 54 | return ((DeserializedCheckSum ?? CheckSum) == CheckSum) 55 | && ((DeserializedCommand ?? Command) == Command); 56 | } 57 | } 58 | 59 | public bool WasDeserialised 60 | { 61 | get { return (DeserializedCheckSum != null); } 62 | } 63 | } 64 | } 65 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPRequest.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public abstract class SPRequest : SPFrame, ISerializable 17 | { 18 | public UInt16 Serialize(Stream stream) 19 | { 20 | stream.WriteByte(Addr); 21 | stream.WriteUInt16(DataSize); 22 | stream.WriteByte((byte)Command); 23 | 24 | UInt16 osize = HeaderSize; 25 | osize += PayloadSerialize(stream); 26 | 27 | stream.WriteUInt16(CheckSum); 28 | stream.WriteUInt16(PackNum); 29 | 30 | for (int i = 0; i < PostfixSize(); i++) 31 | stream.WriteUInt16(0); 32 | 33 | return osize; 34 | } 35 | 36 | protected virtual UInt16 PayloadSerialize(Stream stream) 37 | { 38 | return 0; 39 | } 40 | 41 | protected virtual UInt16 PostfixSize() 42 | { 43 | return 3; 44 | } 45 | } 46 | } 47 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPResetRequest.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.Linq; 10 | using System.Text; 11 | using System.Threading.Tasks; 12 | 13 | namespace MilTest.MilLight.ServiceProtocol 14 | { 15 | public class SPResetRequest : SPRequest 16 | { 17 | public override SPCommand Command 18 | { 19 | get { return SPCommand.Reset; } 20 | } 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPStatusReply.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public class SPStatusReply : SPReply, ISPStatus 17 | { 18 | public override SPCommand Command 19 | { 20 | get { return SPCommand.Status; } 21 | } 22 | 23 | protected const UInt16 statusPayloadSize = 3; 24 | 25 | private ushort transmitQueueSize; 26 | public ushort TransmitQueueSize 27 | { 28 | get 29 | { 30 | Actualize(); 31 | return transmitQueueSize; 32 | } 33 | set 34 | { 35 | transmitQueueSize = value; 36 | Expire(); 37 | } 38 | } 39 | 40 | private ushort receivedQueueSize; 41 | public ushort ReceivedQueueSize 42 | { 43 | get 44 | { 45 | Actualize(); 46 | return receivedQueueSize; 47 | } 48 | set 49 | { 50 | receivedQueueSize = value; 51 | Expire(); 52 | } 53 | } 54 | 55 | private ushort spiErrorCount; 56 | public ushort SpiErrorCount 57 | { 58 | get 59 | { 60 | Actualize(); 61 | return spiErrorCount; 62 | } 63 | set 64 | { 65 | spiErrorCount = value; 66 | Expire(); 67 | } 68 | } 69 | 70 | protected override ushort PayloadDataSize() 71 | { 72 | return statusPayloadSize; 73 | } 74 | 75 | protected override ushort PayloadCheckSum() 76 | { 77 | return (UInt16)(transmitQueueSize + receivedQueueSize + spiErrorCount); 78 | } 79 | 80 | protected override bool PayloadEquals(object obj) 81 | { 82 | SPStatusReply o = obj as SPStatusReply; 83 | if (o == null) 84 | return false; 85 | 86 | return o.receivedQueueSize == receivedQueueSize 87 | && o.transmitQueueSize == transmitQueueSize 88 | && o.spiErrorCount == spiErrorCount; 89 | } 90 | 91 | protected override int PayloadHashCode() 92 | { 93 | int hash = 56; 94 | hash = hash * 23 + receivedQueueSize.GetHashCode(); 95 | hash = hash * 23 + transmitQueueSize.GetHashCode(); 96 | hash = hash * 23 + spiErrorCount.GetHashCode(); 97 | return hash; 98 | } 99 | 100 | protected override ushort PayloadDeserialize(Stream stream, ushort payloadSize) 101 | { 102 | if (payloadSize != statusPayloadSize) 103 | throw new ArgumentException("Illegal payloadSize. It should be identical to statusPayloadSize"); 104 | 105 | receivedQueueSize = stream.ReadUInt16(); 106 | transmitQueueSize = stream.ReadUInt16(); 107 | spiErrorCount = stream.ReadUInt16(); 108 | 109 | return statusPayloadSize; 110 | } 111 | 112 | public override string ToString() 113 | { 114 | return string.Format("{0} ReceivedQueueSize:{1:X4} TransmitQueueSize:{2:X4} SpiErrorCount:{3:X4}", 115 | base.ToString(), ReceivedQueueSize, TransmitQueueSize, SpiErrorCount); 116 | } 117 | } 118 | } 119 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPStatusRequest.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.Linq; 10 | using System.Text; 11 | using System.Threading.Tasks; 12 | 13 | namespace MilTest.MilLight.ServiceProtocol 14 | { 15 | public class SPStatusRequest : SPRequest 16 | { 17 | public override SPCommand Command 18 | { 19 | get { return SPCommand.Status; } 20 | } 21 | 22 | protected override UInt16 PostfixSize() 23 | { 24 | return (UInt16)(base.PostfixSize() + 3 /*size of SPStatusReply payload in words*/); 25 | } 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/SPTransmitRequest.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public class SPTransmitRequest : SPRequest, ISPData, IValidate 17 | { 18 | public override SPCommand Command 19 | { 20 | get { return SPCommand.Send; } 21 | } 22 | 23 | public override bool IsActual 24 | { 25 | get { return base.IsActual && !Data.Exists(a => !((ExpirableObject)a).IsActual); } 26 | } 27 | 28 | private List data = new List(); 29 | public List Data 30 | { 31 | get 32 | { 33 | Actualize(); 34 | return data; 35 | } 36 | set 37 | { 38 | data = value; 39 | Expire(); 40 | } 41 | } 42 | 43 | public bool IsValid 44 | { 45 | get 46 | { 47 | return data.Count > 0 48 | && data[0].Header == MilType.WSERV 49 | && data.Count(a => a.Header == MilType.WDATA) == data.Count - 1; 50 | } 51 | } 52 | 53 | protected override ushort PayloadDataSize() 54 | { 55 | return (UInt16)(data.Sum(a => a.Size)); 56 | } 57 | 58 | protected override ushort PayloadCheckSum() 59 | { 60 | return (UInt16)(data.Sum(a => a.CheckSum)); 61 | } 62 | 63 | protected override bool PayloadEquals(object obj) 64 | { 65 | ISPData o = obj as ISPData; 66 | if (o == null) 67 | return false; 68 | 69 | return Enumerable.SequenceEqual(o.Data, Data); 70 | } 71 | 72 | protected override int PayloadHashCode() 73 | { 74 | return Data.GetHashCode(); 75 | } 76 | 77 | protected override UInt16 PayloadSerialize(Stream stream) 78 | { 79 | ushort size = 0; 80 | Data.ForEach(a => size += ((ISerializable)a).Serialize(stream)); 81 | return size; 82 | } 83 | 84 | public override string ToString() 85 | { 86 | return string.Format("{0} data:{1}", base.ToString(), string.Join(", ", Data)); 87 | } 88 | } 89 | } 90 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/StreamExtensions.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public static class StreamExtensions 17 | { 18 | public static void WriteUInt16(this Stream stream, UInt16 value) 19 | { 20 | stream.WriteByte((byte)(value >> 8)); 21 | stream.WriteByte((byte)(value & 0xFF)); 22 | } 23 | 24 | public static UInt16 ReadUInt16(this Stream stream) 25 | { 26 | UInt16 result; 27 | byte[] buffer = new byte[2]; 28 | 29 | stream.Read(buffer, 0, 2); 30 | 31 | result = (UInt16)(buffer[0] << 8); 32 | result += buffer[1]; 33 | 34 | return result; 35 | } 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/MilLight/ServiceProtocol/interfaces.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Collections.Generic; 9 | using System.IO; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest.MilLight.ServiceProtocol 15 | { 16 | public enum SPCommand : byte 17 | { 18 | Unknown = 0xFF, 19 | Reset = 0xA0, 20 | Send = 0xA2, 21 | Status = 0xB0, 22 | Receive = 0xB2 23 | } 24 | 25 | public enum MilType : UInt16 26 | { 27 | WSERVERR = 0xFFA0, 28 | WSERV = 0xFFA1, 29 | WDATAERR = 0xFFA2, 30 | WDATA = 0xFFA3 31 | } 32 | 33 | public interface IMilFrame 34 | { 35 | MilType Header { get; set; } 36 | UInt16 Data { get; set; } 37 | UInt16 CheckSum { get; } 38 | UInt16 Size { get; } 39 | } 40 | 41 | public interface ISPFrame 42 | { 43 | byte Addr { get; set; } 44 | UInt16 DataSize { get; } 45 | SPCommand Command { get; } 46 | UInt16 CheckSum { get; } 47 | UInt16 PackNum { get; set; } 48 | } 49 | 50 | public interface ISPData 51 | { 52 | List Data { get; set; } 53 | } 54 | 55 | public interface ISPStatus 56 | { 57 | UInt16 TransmitQueueSize { get; } 58 | UInt16 ReceivedQueueSize { get; } 59 | UInt16 SpiErrorCount { get; } 60 | } 61 | 62 | public interface ISerializable 63 | { 64 | UInt16 Serialize(Stream stream); 65 | } 66 | 67 | public interface IDeserializable 68 | { 69 | UInt16 Deserialize(Stream stream); 70 | 71 | } 72 | 73 | public interface IValidate 74 | { 75 | bool IsValid { get; } 76 | } 77 | } 78 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | using System.Reflection; 2 | using System.Runtime.CompilerServices; 3 | using System.Runtime.InteropServices; 4 | 5 | // General Information about an assembly is controlled through the following 6 | // set of attributes. Change these attribute values to modify the information 7 | // associated with an assembly. 8 | [assembly: AssemblyTitle("MilLight")] 9 | [assembly: AssemblyDescription("")] 10 | [assembly: AssemblyConfiguration("")] 11 | [assembly: AssemblyCompany("")] 12 | [assembly: AssemblyProduct("MilLight")] 13 | [assembly: AssemblyCopyright("Copyright © 2016")] 14 | [assembly: AssemblyTrademark("")] 15 | [assembly: AssemblyCulture("")] 16 | 17 | // Setting ComVisible to false makes the types in this assembly not visible 18 | // to COM components. If you need to access a type in this assembly from 19 | // COM, set the ComVisible attribute to true on that type. 20 | [assembly: ComVisible(false)] 21 | 22 | // The following GUID is for the ID of the typelib if this project is exposed to COM 23 | [assembly: Guid("cf4eaf10-77a4-435d-b706-779275906bb0")] 24 | 25 | // Version information for an assembly consists of the following four values: 26 | // 27 | // Major Version 28 | // Minor Version 29 | // Build Number 30 | // Revision 31 | // 32 | // You can specify all the values or you can default the Build and Revision Numbers 33 | // by using the '*' as shown below: 34 | // [assembly: AssemblyVersion("1.0.*")] 35 | [assembly: AssemblyVersion("1.0.0.0")] 36 | [assembly: AssemblyFileVersion("1.0.0.0")] 37 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilLight/packages.config: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilTest/HardwareErrorTest.cs: -------------------------------------------------------------------------------- 1 | using Microsoft.VisualStudio.TestTools.UnitTesting; 2 | using MilTest.MilLight.MilSpiBridge; 3 | using MilTest.MilLight.ServiceProtocol; 4 | using System; 5 | using System.Collections.Generic; 6 | using System.Linq; 7 | using System.Text; 8 | using System.Threading; 9 | using System.Threading.Tasks; 10 | 11 | namespace MilTest 12 | { 13 | [TestClass] 14 | public class HardwareErrorTest 15 | { 16 | const byte transmitterAddr = 0xAB; 17 | const byte receiverAddr = 0xAC; 18 | const string mpsseDeviceSerialNum = "A"; 19 | 20 | [TestInitialize()] 21 | public void HardwareErrorTestInitialize() 22 | { 23 | IMilSpiBridge bridge = new MilSpiBridge(mpsseDeviceSerialNum); 24 | bridge.DeviceReset(transmitterAddr); 25 | } 26 | 27 | [TestMethod] 28 | public void SendErrorAndCheckStatus() 29 | { 30 | ErrorBridgeTransmitter bridge = new ErrorBridgeTransmitter(mpsseDeviceSerialNum); 31 | 32 | List tdata = new List() { new MilFrame() { Header = MilType.WSERV, Data = 1 } }; 33 | 34 | bridge.Transmit(transmitterAddr, tdata); 35 | 36 | Thread.Sleep(500); 37 | 38 | ISPStatus status = bridge.getDeviceStatus(transmitterAddr); 39 | Assert.IsTrue(status.SpiErrorCount == 1); 40 | 41 | status = bridge.getDeviceStatus(receiverAddr); 42 | Assert.IsTrue(status.ReceivedQueueSize == 0); 43 | } 44 | 45 | class SPErrorCheckSumTransmitRequest : SPTransmitRequest 46 | { 47 | protected override ushort PayloadCheckSum() 48 | { 49 | //adding error to packet checksum 50 | return (ushort)(base.PayloadCheckSum() + 1); 51 | } 52 | } 53 | 54 | class ErrorBridgeTransmitter : MilSpiBridge 55 | { 56 | public ErrorBridgeTransmitter(string mpsseSerialNumber) : base(mpsseSerialNumber) { } 57 | 58 | public new void Transmit(byte addr, List data) 59 | { 60 | var packet = new SPErrorCheckSumTransmitRequest() { Addr = addr, Data = data, PackNum = 0 }; 61 | if (!packet.IsValid) 62 | throw new ArgumentException("Not valid frame data"); 63 | 64 | transmitPacket(packet); 65 | } 66 | 67 | } 68 | } 69 | } 70 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilTest/HardwareTest.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using System.Text; 9 | using System.Collections.Generic; 10 | using Microsoft.VisualStudio.TestTools.UnitTesting; 11 | using System.Threading; 12 | using System.Linq; 13 | using MilTest.MilLight.ServiceProtocol; 14 | using MilTest.MilLight.MilSpiBridge; 15 | 16 | namespace MilTest 17 | { 18 | class MainC 19 | { 20 | public static void Main() 21 | { 22 | var t = new HardwareErrorTest(); 23 | t.SendErrorAndCheckStatus(); 24 | } 25 | } 26 | 27 | [TestClass] 28 | public class HardwareTest 29 | { 30 | const byte transmitterAddr = 0xAB; 31 | const byte receiverAddr = 0xAC; 32 | const string mpsseDeviceSerialNum = "A"; 33 | const int cycleTestCount = 100; 34 | 35 | [TestInitialize()] 36 | public void HardwareTestInitialize() 37 | { 38 | IMilSpiBridge bridge = new MilSpiBridge(mpsseDeviceSerialNum); 39 | bridge.DeviceReset(transmitterAddr); 40 | } 41 | 42 | [TestMethod] 43 | public void ResetAndStatusTest() 44 | { 45 | IMilSpiBridge bridge = new MilSpiBridge(mpsseDeviceSerialNum); 46 | 47 | List tdata = PacketGenerator.randomPacket(1); 48 | 49 | bridge.Transmit(transmitterAddr, tdata); 50 | 51 | Thread.Sleep(500); 52 | 53 | ISPStatus status = bridge.getDeviceStatus(receiverAddr); 54 | Assert.IsTrue(status.ReceivedQueueSize == 1); 55 | 56 | bridge.DeviceReset(transmitterAddr); 57 | 58 | Thread.Sleep(200); 59 | 60 | status = bridge.getDeviceStatus(receiverAddr); 61 | Assert.IsTrue(status.ReceivedQueueSize == 0); 62 | } 63 | 64 | 65 | 66 | [TestMethod] 67 | public void TransmissionFixedTest() 68 | { 69 | TransmissionTest(PacketGenerator.fixedPacket()); 70 | } 71 | 72 | [TestMethod] 73 | public void TransmissionRandom1Test() 74 | { 75 | TransmissionTest(PacketGenerator.randomPacket(1)); 76 | } 77 | 78 | [TestMethod] 79 | public void TransmissionRandom2Test() 80 | { 81 | TransmissionTest(PacketGenerator.randomPacket(2)); 82 | } 83 | 84 | [TestMethod] 85 | public void TransmissionRandomNTest() 86 | { 87 | TransmissionTest(PacketGenerator.randomPacket()); 88 | } 89 | 90 | [TestMethod] 91 | public void TransmissionFixedCycleTest() 92 | { 93 | for (int i = 0; i < cycleTestCount; i++) 94 | TransmissionTest(PacketGenerator.fixedPacket()); 95 | } 96 | 97 | [TestMethod] 98 | public void TransmissionRandom1CycleTest() 99 | { 100 | for (int i = 0; i < cycleTestCount; i++) 101 | TransmissionTest(PacketGenerator.randomPacket(1)); 102 | } 103 | 104 | [TestMethod] 105 | public void TransmissionRandomNCycleTest() 106 | { 107 | for (int i = 0; i < cycleTestCount; i++) 108 | TransmissionTest(PacketGenerator.randomPacket()); 109 | } 110 | 111 | void TransmissionTest(List tdata) 112 | { 113 | IMilSpiBridge bridge = new MilSpiBridge(mpsseDeviceSerialNum); 114 | 115 | bridge.Transmit(transmitterAddr, tdata); 116 | 117 | List rdata = bridge.WaitReceive(receiverAddr, (ushort)tdata.Count); 118 | 119 | Assert.IsTrue(Enumerable.SequenceEqual(rdata, tdata)); 120 | } 121 | } 122 | } 123 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilTest/MilTest.csproj: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | Debug 5 | AnyCPU 6 | {87F310C4-C9B2-45A6-A31A-B90946563A8D} 7 | Exe 8 | Properties 9 | MilTest 10 | MilTest 11 | v4.5.2 12 | 512 13 | {3AC096D0-A1C2-E12C-1390-A8335801FDAB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} 14 | 10.0 15 | $(MSBuildExtensionsPath32)\Microsoft\VisualStudio\v$(VisualStudioVersion) 16 | $(ProgramFiles)\Common Files\microsoft shared\VSTT\$(VisualStudioVersion)\UITestExtensionPackages 17 | False 18 | UnitTest 19 | 20 | 21 | true 22 | full 23 | false 24 | bin\Debug\ 25 | DEBUG;TRACE 26 | prompt 27 | 4 28 | 29 | 30 | pdbonly 31 | true 32 | bin\Release\ 33 | TRACE 34 | prompt 35 | 4 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | False 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | {cf4eaf10-77a4-435d-b706-779275906bb0} 67 | MilLight 68 | 69 | 70 | 71 | 72 | 73 | 74 | False 75 | 76 | 77 | False 78 | 79 | 80 | False 81 | 82 | 83 | False 84 | 85 | 86 | 87 | 88 | 89 | 90 | 97 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilTest/PacketGenerator.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using MilTest.MilLight.ServiceProtocol; 8 | using System; 9 | using System.Collections.Generic; 10 | using System.Linq; 11 | using System.Text; 12 | using System.Threading.Tasks; 13 | 14 | namespace MilTest 15 | { 16 | static class PacketGenerator 17 | { 18 | private static Random rnd = new Random(); 19 | 20 | public static List randomPacket(int size) 21 | { 22 | if (size == 0) 23 | throw new ArgumentException("packet size should be greater then 0"); 24 | 25 | List result = new List(); 26 | 27 | //header 28 | result.Add(new MilFrame() { Header = MilType.WSERV, Data = (ushort)rnd.Next() }); 29 | 30 | //body 31 | for (int i = 1; i < size; i++) 32 | result.Add(new MilFrame() { Header = MilType.WDATA, Data = (ushort)rnd.Next() }); 33 | 34 | return result; 35 | } 36 | 37 | public static List randomPacket() 38 | { 39 | const int maxPacketSize = 30; 40 | return randomPacket(rnd.Next(1, maxPacketSize)); 41 | } 42 | 43 | public static List fixedPacket() 44 | { 45 | return new List() 46 | { 47 | new MilFrame() { Data = 0x0001, Header = MilType.WSERV }, 48 | new MilFrame() { Data = 0x0002 }, 49 | new MilFrame() { Data = 0xAB45 }, 50 | new MilFrame() { Data = 0xFFA1 } 51 | }; 52 | } 53 | } 54 | 55 | } 56 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilTest/Properties/AssemblyInfo.cs: -------------------------------------------------------------------------------- 1 | using System.Reflection; 2 | using System.Runtime.CompilerServices; 3 | using System.Runtime.InteropServices; 4 | 5 | // General Information about an assembly is controlled through the following 6 | // set of attributes. Change these attribute values to modify the information 7 | // associated with an assembly. 8 | [assembly: AssemblyTitle("MilTest")] 9 | [assembly: AssemblyDescription("")] 10 | [assembly: AssemblyConfiguration("")] 11 | [assembly: AssemblyCompany("")] 12 | [assembly: AssemblyProduct("MilTest")] 13 | [assembly: AssemblyCopyright("Copyright © 2016")] 14 | [assembly: AssemblyTrademark("")] 15 | [assembly: AssemblyCulture("")] 16 | 17 | // Setting ComVisible to false makes the types in this assembly not visible 18 | // to COM components. If you need to access a type in this assembly from 19 | // COM, set the ComVisible attribute to true on that type. 20 | [assembly: ComVisible(false)] 21 | 22 | // The following GUID is for the ID of the typelib if this project is exposed to COM 23 | [assembly: Guid("87f310c4-c9b2-45a6-a31a-b90946563a8d")] 24 | 25 | // Version information for an assembly consists of the following four values: 26 | // 27 | // Major Version 28 | // Minor Version 29 | // Build Number 30 | // Revision 31 | // 32 | // You can specify all the values or you can default the Build and Revision Numbers 33 | // by using the '*' as shown below: 34 | // [assembly: AssemblyVersion("1.0.*")] 35 | [assembly: AssemblyVersion("1.0.0.0")] 36 | [assembly: AssemblyFileVersion("1.0.0.0")] 37 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/MilTest/ProtocolTest.cs: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | using System; 8 | using Microsoft.VisualStudio.TestTools.UnitTesting; 9 | using System.Collections.Generic; 10 | using System.IO; 11 | using System.Linq; 12 | using MilTest.MilLight.ServiceProtocol; 13 | 14 | namespace MilTest 15 | { 16 | 17 | [TestClass] 18 | public abstract class SerializeTestCase 19 | { 20 | public abstract ISerializable getPacket(); 21 | public abstract byte[] getReferenceRawData(); 22 | 23 | [TestMethod] 24 | public void EncodeTest() 25 | { 26 | ISerializable t = getPacket(); 27 | 28 | MemoryStream stream = new MemoryStream(); 29 | t.Serialize(stream); 30 | byte[] data = stream.ToArray(); 31 | 32 | byte[] normalData = getReferenceRawData(); 33 | 34 | Assert.IsTrue(Enumerable.SequenceEqual(data, normalData)); 35 | } 36 | } 37 | 38 | [TestClass] 39 | public class ProtocolReset : SerializeTestCase 40 | { 41 | public override ISerializable getPacket() 42 | { 43 | return new SPResetRequest() { Addr = 0xab, PackNum = 1 }; 44 | } 45 | 46 | public override byte[] getReferenceRawData() 47 | { 48 | return new byte[] { 49 | 0xab, 0x00, 0x00, 0xa0, 50 | 0xab, 0xa0, 0x00, 0x01, 51 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 52 | }; 53 | } 54 | } 55 | 56 | [TestClass] 57 | public class ProtocolStatusRequest : SerializeTestCase 58 | { 59 | public override ISerializable getPacket() 60 | { 61 | return new SPStatusRequest() { Addr = 0xab, PackNum = 1 }; 62 | } 63 | 64 | public override byte[] getReferenceRawData() 65 | { 66 | return new byte[] { 67 | 0xab, 0x00, 0x00, 0xb0, 68 | 0xab, 0xb0, 0x00, 0x01, 69 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 70 | }; 71 | } 72 | } 73 | 74 | [TestClass] 75 | public class ProtocolTransmitRequest : SerializeTestCase 76 | { 77 | public override ISerializable getPacket() 78 | { 79 | return new SPTransmitRequest() 80 | { 81 | Addr = 0xab, 82 | PackNum = 1, 83 | Data = new List() 84 | { 85 | new MilFrame() { Data = 0x0001, Header = MilType.WSERV }, 86 | new MilFrame() { Data = 0x0002 }, 87 | new MilFrame() { Data = 0xAB45 }, 88 | new MilFrame() { Data = 0xFFA1 } 89 | } 90 | }; 91 | } 92 | 93 | public override byte[] getReferenceRawData() 94 | { 95 | return new byte[] { 96 | 0xab, 0x00, 0x08, 0xa2, 97 | 0xff, 0xa1, 0x00, 0x01, 0xff, 0xa3, 0x00, 0x02, 98 | 0xff, 0xa3, 0xab, 0x45, 0xff, 0xa3, 0xff, 0xa1, 99 | 0x5d, 0x15, 0x00, 0x01, 100 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 101 | }; 102 | } 103 | } 104 | 105 | [TestClass] 106 | public class ProtocolReceiveRequest : SerializeTestCase 107 | { 108 | public override ISerializable getPacket() 109 | { 110 | return new SPReceiveRequest() 111 | { 112 | Addr = 0xab, 113 | PackNum = 1, 114 | RequestedSize = 8 115 | }; 116 | } 117 | 118 | public override byte[] getReferenceRawData() 119 | { 120 | return new byte[] { 121 | 0xab, 0x00, 0x08, 0xb2, 122 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 123 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 124 | 0xb3, 0xba, 0x00, 0x01, 125 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 126 | }; 127 | } 128 | } 129 | 130 | [TestClass] 131 | public abstract class DeserializeTestCase 132 | { 133 | public abstract SPReply createPacket(); 134 | public abstract SPReply getReferencePacket(); 135 | public abstract byte[] getRawData(); 136 | 137 | [TestMethod] 138 | public void DecodeTest() 139 | { 140 | MemoryStream iStream = new MemoryStream(getRawData()); 141 | SPReply r = createPacket(); 142 | r.Deserialize(iStream); 143 | 144 | SPReply t = getReferencePacket(); 145 | 146 | Assert.IsTrue(r.Equals(t)); 147 | Assert.IsTrue(r.IsActual); 148 | Assert.IsTrue(r.IsValid); 149 | } 150 | } 151 | 152 | [TestClass] 153 | public class ProtocolStatusReplyCase : DeserializeTestCase 154 | { 155 | public override SPReply createPacket() 156 | { 157 | return new SPStatusReply(); 158 | } 159 | 160 | public override byte[] getRawData() 161 | { 162 | return new byte[] { 163 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 164 | 0xab, 0x00, 0x03, 0xb0, 165 | 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 166 | 0xae, 0xb6, 0x00, 0x02 167 | }; 168 | } 169 | 170 | public override SPReply getReferencePacket() 171 | { 172 | return new SPStatusReply() 173 | { 174 | Addr = 0xAB, 175 | ReceivedQueueSize = 1, 176 | TransmitQueueSize = 2, 177 | SpiErrorCount = 3, 178 | PackNum = 2 179 | }; 180 | } 181 | } 182 | 183 | [TestClass] 184 | public class ProtocolReceiveReplyCase : DeserializeTestCase 185 | { 186 | public override SPReply createPacket() 187 | { 188 | return new SPReceiveReply(); 189 | } 190 | 191 | public override byte[] getRawData() 192 | { 193 | return new byte[] { 194 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 195 | 0xab, 0x00, 0x08, 0xb2, 196 | 0xff, 0xa1, 0x00, 0x01, 0xff, 0xa3, 0x00, 0x02, 197 | 0xff, 0xa3, 0xab, 0x45, 0xff, 0xa3, 0xff, 0xa1, 198 | 0x5d, 0x25, 0x00, 0x01 199 | }; 200 | } 201 | 202 | public override SPReply getReferencePacket() 203 | { 204 | return new SPReceiveReply() 205 | { 206 | Addr = 0xab, 207 | PackNum = 1, 208 | Data = new List() 209 | { 210 | new MilFrame() { Data = 0x0001, Header = MilType.WSERV }, 211 | new MilFrame() { Data = 0x0002 }, 212 | new MilFrame() { Data = 0xAB45 }, 213 | new MilFrame() { Data = 0xFFA1 } 214 | } 215 | }; 216 | } 217 | } 218 | } 219 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/lib/FTD2XX_NET.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/src/board/DE0_tests/MilLight/lib/FTD2XX_NET.dll -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/lib/MPSSELight.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/src/board/DE0_tests/MilLight/lib/MPSSELight.dll -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/MilLight/lib/MPSSELight.dll.config: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/FTD2XX_NET.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/FTD2XX_NET.dll -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/FluentCommandLineParser.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/FluentCommandLineParser.dll -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/MPSSELight.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/MPSSELight.dll -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/SpiLight.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/SpiLight.exe -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/SpiLight/SpiLight.exe.config: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/cmdstart.bat: -------------------------------------------------------------------------------- 1 | start cmd -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/milTest.bat: -------------------------------------------------------------------------------- 1 | SpiLight\SpiLight.exe -d A -Ss -I sequence_1_send.spi_txt 2 | SpiLight\SpiLight.exe -d A -Ss -I sequence_2_statusT.spi_txt 3 | SpiLight\SpiLight.exe -d A -Ss -I sequence_3_statusR.spi_txt 4 | SpiLight\SpiLight.exe -d A -Ss -I sequence_4_receive.spi_txt 5 | -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/sequence_1_send.spi_txt: -------------------------------------------------------------------------------- 1 | AB0008A2FFA10001FFA10002FFA1AB45FFA3FFA15D110000 -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/sequence_2_statusT.spi_txt: -------------------------------------------------------------------------------- 1 | AB0000B0ABB0000000000000000000000000000000000000000000 -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/sequence_3_statusR.spi_txt: -------------------------------------------------------------------------------- 1 | AC0002B0000000000000AEB0000000000000000000000000000000000000000000 -------------------------------------------------------------------------------- /mil1553-spi/src/board/DE0_tests/batch_tests/sequence_4_receive.spi_txt: -------------------------------------------------------------------------------- 1 | AC0006B2000000000000000000000000B1B2000000000000000000000000 -------------------------------------------------------------------------------- /mil1553-spi/src/docs/mil1553-ServiceProtocol.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/src/docs/mil1553-ServiceProtocol.odt -------------------------------------------------------------------------------- /mil1553-spi/src/docs/mil1553-spi_diagram.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpga-soc/mil-std-1553b-soc/931780ef508bd63b01d2c0825a021f7d04520da9/mil1553-spi/src/docs/mil1553-spi_diagram.odg -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/MemoryArbiter.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef ARBITER_INCLUDE 8 | `define ARBITER_INCLUDE 9 | 10 | module Arbiter(input bit nRst, clk, 11 | IArbiter.arbiter client[3:0]); 12 | 13 | logic [3:0] requestedChannel, 14 | grantedChannel, newGrantedChannel; 15 | 16 | assign {client[3].grant, client[2].grant, 17 | client[1].grant, client[0].grant} = grantedChannel; 18 | 19 | assign requestedChannel = {client[3].request, client[2].request, 20 | client[1].request, client[0].request}; 21 | 22 | always_ff @ (posedge clk) 23 | if(!nRst) 24 | grantedChannel <= '0; 25 | else 26 | grantedChannel <= newGrantedChannel; 27 | 28 | always_comb begin 29 | newGrantedChannel = grantedChannel; 30 | 31 | if(!(requestedChannel & grantedChannel)) begin 32 | if( requestedChannel & 4'b0001) newGrantedChannel = 4'b0001; 33 | else if(requestedChannel & 4'b0010) newGrantedChannel = 4'b0010; 34 | else if(requestedChannel & 4'b0100) newGrantedChannel = 4'b0100; 35 | else if(requestedChannel & 4'b1000) newGrantedChannel = 4'b1000; 36 | else newGrantedChannel = '0; 37 | end 38 | end 39 | 40 | endmodule 41 | 42 | module Arbiter8(input bit nRst, clk, 43 | IArbiter.arbiter client[7:0]); 44 | 45 | logic [7:0] requestedChannel, 46 | grantedChannel, newGrantedChannel; 47 | 48 | assign {client[7].grant, client[6].grant, client[5].grant, client[4].grant, 49 | client[3].grant, client[2].grant, client[1].grant, client[0].grant } = grantedChannel; 50 | 51 | assign requestedChannel = 52 | {client[7].request, client[6].request, client[5].request, client[4].request, 53 | client[3].request, client[2].request, client[1].request, client[0].request}; 54 | 55 | always_ff @ (posedge clk) 56 | if(!nRst) 57 | grantedChannel <= '0; 58 | else 59 | grantedChannel <= newGrantedChannel; 60 | 61 | always_comb begin 62 | newGrantedChannel = grantedChannel; 63 | 64 | if(!(requestedChannel & grantedChannel)) begin 65 | if( requestedChannel & 8'b00000001) newGrantedChannel = 8'b00000001; 66 | else if(requestedChannel & 8'b00000010) newGrantedChannel = 8'b00000010; 67 | else if(requestedChannel & 8'b00000100) newGrantedChannel = 8'b00000100; 68 | else if(requestedChannel & 8'b00001000) newGrantedChannel = 8'b00001000; 69 | else if(requestedChannel & 8'b00010000) newGrantedChannel = 8'b00010000; 70 | else if(requestedChannel & 8'b00100000) newGrantedChannel = 8'b00100000; 71 | else if(requestedChannel & 8'b01000000) newGrantedChannel = 8'b01000000; 72 | else if(requestedChannel & 8'b10000000) newGrantedChannel = 8'b10000000; 73 | else newGrantedChannel = '0; 74 | end 75 | end 76 | 77 | endmodule 78 | 79 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/MemoryBlock.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MEMORYBLOCK_INCLUDE 8 | `define MEMORYBLOCK_INCLUDE 9 | 10 | module MemoryBlock( input bit nRst, clk, 11 | IPush.slave push0, 12 | IPush.slave push1, 13 | IPop.slave pop0, 14 | IPop.slave pop1, 15 | IRingBufferControl.slave rcontrol0, 16 | IRingBufferControl.slave rcontrol1, 17 | IMemory mbus); 18 | 19 | parameter RING1_MEM_START = 16'h00; 20 | parameter RING1_MEM_END = 16'h7F; 21 | parameter RING2_MEM_START = 16'h80; 22 | parameter RING2_MEM_END = 16'hFF; 23 | 24 | IMemoryReader rbus0(); 25 | IMemoryReader rbus1(); 26 | IMemoryWriter wbus0(); 27 | IMemoryWriter wbus1(); 28 | IArbiter abus[3:0](); 29 | 30 | Arbiter arbiter(nRst, clk, abus); 31 | MemoryWriter writerA(nRst, clk, mbus.writer, wbus0.slave, abus[0].client); 32 | MemoryWriter writerB(nRst, clk, mbus.writer, wbus1.slave, abus[1].client); 33 | MemoryReader readerA(nRst, clk, mbus.reader, rbus0.slave, abus[2].client); 34 | MemoryReader readerB(nRst, clk, mbus.reader, rbus1.slave, abus[3].client); 35 | 36 | RingBuffer #(.MEM_START_ADDR(RING1_MEM_START), .MEM_END_ADDR(RING1_MEM_END)) 37 | ringA (nRst, clk, rcontrol0, push0, pop0, wbus0.master, rbus0.master); 38 | 39 | RingBuffer #(.MEM_START_ADDR(RING2_MEM_START), .MEM_END_ADDR(RING2_MEM_END)) 40 | ringB (nRst, clk, rcontrol1, push1, pop1, wbus1.master, rbus1.master); 41 | 42 | assign mbus.wr_enable = ( abus[0].grant | abus[1].grant) ? 'z : '0; 43 | assign mbus.rd_enable = ( abus[2].grant | abus[3].grant) ? 'z : '0; 44 | 45 | endmodule 46 | 47 | 48 | 49 | 50 | module MemoryBlock2( input bit nRst, clk, 51 | IPush.slave push0, push1, push2, push3, 52 | IPop.slave pop0, pop1, pop2, pop3, 53 | IRingBufferControl.slave rc0, rc1, rc2, rc3, 54 | IMemory mbus); 55 | 56 | parameter RING2_0_MEM_START = 16'h0000; 57 | parameter RING2_0_MEM_END = 16'h007F; 58 | parameter RING2_1_MEM_START = 16'h0080; 59 | parameter RING2_1_MEM_END = 16'h00FF; 60 | parameter RING2_2_MEM_START = 16'h0100; 61 | parameter RING2_2_MEM_END = 16'h017F; 62 | parameter RING2_3_MEM_START = 16'h0180; 63 | parameter RING2_3_MEM_END = 16'h01FF; 64 | 65 | IMemoryReader rbus[3:0](); 66 | IMemoryWriter wbus[3:0](); 67 | IArbiter abus[7:0](); 68 | 69 | Arbiter8 arbiter(nRst, clk, abus); 70 | MemoryWriter writer0(nRst, clk, mbus.writer, wbus[0].slave, abus[0].client); 71 | MemoryWriter writer1(nRst, clk, mbus.writer, wbus[1].slave, abus[1].client); 72 | MemoryWriter writer2(nRst, clk, mbus.writer, wbus[2].slave, abus[2].client); 73 | MemoryWriter writer3(nRst, clk, mbus.writer, wbus[3].slave, abus[3].client); 74 | MemoryReader reader0(nRst, clk, mbus.reader, rbus[0].slave, abus[4].client); 75 | MemoryReader reader1(nRst, clk, mbus.reader, rbus[1].slave, abus[5].client); 76 | MemoryReader reader2(nRst, clk, mbus.reader, rbus[2].slave, abus[6].client); 77 | MemoryReader reader3(nRst, clk, mbus.reader, rbus[3].slave, abus[7].client); 78 | 79 | RingBuffer #(.MEM_START_ADDR(RING2_0_MEM_START), .MEM_END_ADDR(RING2_0_MEM_END)) 80 | ring0 (nRst, clk, rc0, push0, pop0, wbus[0].master, rbus[0].master); 81 | 82 | RingBuffer #(.MEM_START_ADDR(RING2_1_MEM_START), .MEM_END_ADDR(RING2_1_MEM_END)) 83 | ring1 (nRst, clk, rc1, push1, pop1, wbus[1].master, rbus[1].master); 84 | 85 | RingBuffer #(.MEM_START_ADDR(RING2_2_MEM_START), .MEM_END_ADDR(RING2_2_MEM_END)) 86 | ring2 (nRst, clk, rc2, push2, pop2, wbus[2].master, rbus[2].master); 87 | 88 | RingBuffer #(.MEM_START_ADDR(RING2_3_MEM_START), .MEM_END_ADDR(RING2_3_MEM_END)) 89 | ring3 (nRst, clk, rc3, push3, pop3, wbus[3].master, rbus[3].master); 90 | 91 | assign mbus.wr_enable = ( abus[0].grant | abus[1].grant 92 | | abus[2].grant | abus[3].grant) ? 'z : '0; 93 | assign mbus.rd_enable = ( abus[4].grant | abus[5].grant 94 | | abus[6].grant | abus[7].grant) ? 'z : '0; 95 | 96 | endmodule 97 | 98 | 99 | 100 | `endif 101 | -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/MemoryReader.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MEMORYREADER_INCLUDE 8 | `define MEMORYREADER_INCLUDE 9 | 10 | module MemoryReader(input bit nRst, clk, 11 | IMemory.reader mbus, //memory side 12 | IMemoryReader.slave cbus, //reader data side 13 | IArbiter.client abus //arbiter side 14 | ); 15 | enum {IDLE, WAIT_ACTION, PRE_ACTION, ACTION, POST_ACTION } State, Next; 16 | 17 | always_ff @ (posedge clk) 18 | if(!nRst) 19 | State <= IDLE; 20 | else begin 21 | State <= Next; 22 | if(State == ACTION && Next == POST_ACTION) 23 | cbus.data <= mbus.rd_data; 24 | end 25 | 26 | always_comb begin 27 | Next = State; 28 | unique case(State) 29 | IDLE: if(cbus.request) Next = WAIT_ACTION; 30 | WAIT_ACTION: if(abus.grant) Next = PRE_ACTION; 31 | PRE_ACTION: if(mbus.busy) Next = ACTION; 32 | ACTION: if(mbus.rd_ready) Next = POST_ACTION; 33 | POST_ACTION: Next = (cbus.request) ? WAIT_ACTION : IDLE; 34 | endcase 35 | end 36 | 37 | logic [1:0] out; 38 | assign {cbus.done, abus.request} = out; 39 | 40 | assign mbus.rd_addr = (State == PRE_ACTION || State == ACTION) ? cbus.addr : 'z; 41 | assign mbus.rd_enable = (!abus.grant) ? 'bz 42 | : ((State == PRE_ACTION) ? 'b1 : 'b0); 43 | 44 | always_comb begin 45 | unique case(State) 46 | IDLE: out=2'b00; 47 | WAIT_ACTION: out=2'b01; 48 | PRE_ACTION: out=2'b01; 49 | ACTION: out=2'b01; 50 | POST_ACTION: out=2'b10; 51 | endcase 52 | end 53 | endmodule 54 | 55 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/MemoryRingBuffer.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `include "settings.sv" 8 | 9 | `ifndef RINGBUFFER_INCLUDE 10 | `define RINGBUFFER_INCLUDE 11 | 12 | interface IRingBufferControl(); 13 | logic [`ADDRW_TOP:0] memUsed; 14 | logic open, commit, rollback; 15 | 16 | modport master(input memUsed, output open, commit, rollback); 17 | modport slave(output memUsed, input open, commit, rollback); 18 | endinterface 19 | 20 | module RingBuffer(input bit nRst, clk, 21 | IRingBufferControl.slave control, 22 | IPush.slave push, 23 | IPop.slave pop, 24 | IMemoryWriter.master wbus, 25 | IMemoryReader.master rbus 26 | ); 27 | // real max used space = MEM_END_ADDR - MEM_START_ADDR 28 | // one memory cell is always unused 29 | parameter MEM_START_ADDR = 16'd0; 30 | parameter MEM_END_ADDR = 16'd2; 31 | 32 | logic [`ADDRW_TOP:0] waddr, nextWaddr, optWaddr, 33 | raddr, nextRaddr, optRaddr, 34 | taddr, nextTaddr, optTaddr; 35 | 36 | logic [`ADDRW_TOP:0] used; 37 | 38 | assign wbus.addr = waddr; 39 | assign wbus.data = push.data; 40 | assign rbus.addr = raddr; 41 | assign pop.data = rbus.data; 42 | assign wbus.request = push.request; 43 | assign rbus.request = (used == '0) ? 0 : pop.request; 44 | assign control.memUsed = used; 45 | 46 | assign used = (taddr >= raddr) ? (taddr - raddr) 47 | : (MEM_END_ADDR - MEM_START_ADDR + taddr - raddr + 1); 48 | 49 | logic isInTransaction; 50 | logic isInTransactionFlag; 51 | assign isInTransaction = (control.open | isInTransactionFlag); 52 | 53 | always_ff @ (posedge clk) 54 | if(!nRst) begin 55 | raddr <= MEM_START_ADDR; 56 | waddr <= MEM_START_ADDR; 57 | taddr <= MEM_START_ADDR; 58 | isInTransactionFlag <= 0; 59 | push.done <= 0; 60 | pop.done <= 0; 61 | end 62 | else begin 63 | raddr <= nextRaddr; 64 | waddr <= nextWaddr; 65 | taddr <= nextTaddr; 66 | 67 | if(control.open) 68 | isInTransactionFlag <= 1; 69 | else if(control.commit | control.rollback) 70 | isInTransactionFlag <= 0; 71 | 72 | push.done <= wbus.done; 73 | pop.done <= rbus.done; 74 | end 75 | 76 | always_comb begin 77 | 78 | optWaddr = (waddr == MEM_END_ADDR) ? MEM_START_ADDR : waddr + 1; 79 | optRaddr = (raddr == MEM_END_ADDR) ? MEM_START_ADDR : raddr + 1; 80 | optTaddr = (taddr == MEM_END_ADDR) ? MEM_START_ADDR : taddr + 1; 81 | 82 | nextRaddr = (rbus.done && used > 0) || 83 | (wbus.done && optWaddr == raddr) ? optRaddr : raddr; 84 | 85 | nextWaddr = (control.rollback) ? taddr : (wbus.done ? optWaddr : waddr); 86 | 87 | nextTaddr = (!isInTransaction) || 88 | (isInTransaction && control.commit) ? nextWaddr : 89 | (isInTransaction && rbus.done && taddr == nextRaddr) || 90 | (isInTransaction && wbus.done && taddr == nextWaddr) ? optTaddr : taddr; 91 | end 92 | endmodule 93 | 94 | `endif 95 | -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/MemoryWriter.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MEMORYWRITER_INCLUDE 8 | `define MEMORYWRITER_INCLUDE 9 | 10 | module MemoryWriter(input bit nRst, clk, 11 | IMemory.writer mbus, 12 | IMemoryWriter.slave cbus, 13 | IArbiter.client abus 14 | ); 15 | enum {IDLE, WAIT_ACTION, PRE_ACTION, ACTION, POST_ACTION } State, Next; 16 | 17 | always_ff @ (posedge clk) 18 | if(!nRst) 19 | State <= IDLE; 20 | else 21 | State <= Next; 22 | 23 | always_comb begin 24 | Next = State; 25 | unique case(State) 26 | IDLE: if(cbus.request) Next = WAIT_ACTION; 27 | WAIT_ACTION: if(abus.grant) Next = PRE_ACTION; 28 | PRE_ACTION: if(mbus.busy) Next = ACTION; 29 | ACTION: if(!mbus.busy) Next = POST_ACTION; 30 | POST_ACTION: Next = (cbus.request) ? WAIT_ACTION : IDLE; 31 | endcase 32 | end 33 | 34 | logic [1:0] out; 35 | assign {cbus.done, abus.request} = out; 36 | 37 | assign mbus.wr_addr = (State == PRE_ACTION || State == ACTION) ? cbus.addr : 'z; 38 | assign mbus.wr_data = (State == PRE_ACTION || State == ACTION) ? cbus.data : 'z; 39 | assign mbus.wr_enable = (!abus.grant) ? 'bz 40 | : ((State == PRE_ACTION) ? 'b1 : 'b0); 41 | 42 | always_comb begin 43 | unique case(State) 44 | IDLE: out=2'b00; 45 | WAIT_ACTION: out=2'b01; 46 | PRE_ACTION: out=2'b01; 47 | ACTION: out=2'b01; 48 | POST_ACTION: out=2'b10; 49 | endcase 50 | end 51 | 52 | endmodule 53 | 54 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/ServiceProtocol.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef SERVICE_PROTOCOL_INCLUDE 8 | `define SERVICE_PROTOCOL_INCLUDE 9 | 10 | package ServiceProtocol; 11 | 12 | typedef enum logic[7:0] { TCC_UNKNOWN = 8'hFF, 13 | TCC_RESET = 8'hA0, // device reset 14 | TCC_SEND_DATA = 8'hA2, // send data to mil 15 | TCC_RECEIVE_STS = 8'hB0, // send status info to spi 16 | TCC_RECEIVE_DATA = 8'hB2 // send to spi all the data received from mil 17 | } TCommandCode; 18 | 19 | typedef struct packed { 20 | logic[7:0] addr; 21 | logic[15:0] size; 22 | TCommandCode cmdcode; 23 | logic[15:0] crc; 24 | logic[15:0] num; 25 | } ServiceProtocolHeader; 26 | 27 | typedef struct packed { 28 | logic[15:0] part1; 29 | logic[15:0] part2; 30 | } ServiceProtocolHeaderPart; 31 | 32 | 33 | function TCommandCode decodeTccCommand(byte cmdCode); 34 | priority case (cmdCode) 35 | default: return TCC_UNKNOWN; 36 | TCC_RESET: return TCC_RESET; 37 | TCC_SEND_DATA: return TCC_SEND_DATA; 38 | TCC_RECEIVE_STS: return TCC_RECEIVE_STS; 39 | TCC_RECEIVE_DATA: return TCC_RECEIVE_DATA; 40 | endcase 41 | endfunction 42 | 43 | endpackage 44 | 45 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/ServiceProtocolDecoder.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef SP_DECODER_INCLUDE 8 | `define SP_DECODER_INCLUDE 9 | 10 | interface IServiceProtocolDControl(); 11 | logic[7:0] addr, wordNum; 12 | logic[15:0] size; 13 | ServiceProtocol::TCommandCode cmdCode; 14 | 15 | logic packetStart, packetErr, packetEnd, enable; 16 | 17 | modport slave( output addr, cmdCode, wordNum, size, 18 | packetStart, packetErr, packetEnd, 19 | input enable); 20 | modport master( input addr, cmdCode, wordNum, size, 21 | packetStart, packetErr, packetEnd, 22 | output enable); 23 | endinterface 24 | 25 | module ServiceProtocolDecoder(input bit nRst, clk, 26 | IPush.slave receivedData, 27 | IPush.master decodedBus, 28 | IServiceProtocolDControl.slave control); 29 | import ServiceProtocol::*; 30 | 31 | assign receivedData.done = decodedBus.done; 32 | 33 | ServiceProtocolHeader receivedHeader; 34 | ServiceProtocolHeaderPart headerPart; 35 | 36 | assign {receivedHeader.addr, receivedHeader.size, receivedHeader.cmdcode} 37 | = {headerPart.part1, headerPart.part2[15:8], decodeTccCommand(headerPart.part2[7:0])}; 38 | 39 | logic[15:0] receivedWordsCntr; 40 | logic[15:0] crc; 41 | 42 | enum {WAIT, PACKET_HEAD1, PACKET_HEAD2, 43 | PACKET_DATA, PACKET_CRC, PACKET_NUM, PACKET_POST} State, Next; 44 | 45 | always_ff @ (posedge clk) begin 46 | if(!nRst | !control.enable) 47 | State <= WAIT; 48 | else if(receivedData.request) 49 | State <= Next; 50 | end 51 | 52 | logic dataParseEnable; 53 | assign dataParseEnable = (State == PACKET_DATA || State == PACKET_CRC || 54 | State == PACKET_NUM || State == PACKET_POST); 55 | 56 | assign decodedBus.data = (State == PACKET_DATA) ? receivedData.data : 'z; 57 | assign control.wordNum = (State == PACKET_DATA ) ? receivedWordsCntr : 'z; 58 | assign control.addr = (dataParseEnable) ? receivedHeader.addr : 'z; 59 | assign control.size = (dataParseEnable) ? receivedHeader.size : 'z; 60 | assign control.cmdCode = (dataParseEnable) ? receivedHeader.cmdcode : TCC_UNKNOWN; 61 | 62 | always_ff @ (posedge clk) begin 63 | if(receivedData.request) begin 64 | unique case(Next) 65 | WAIT: crc <= '0; 66 | PACKET_HEAD1: begin 67 | headerPart.part1 <= receivedData.data; 68 | crc <= receivedData.data; 69 | receivedWordsCntr <= 0; 70 | end 71 | 72 | PACKET_HEAD2: begin 73 | headerPart.part2 <= receivedData.data; 74 | crc <= crc + receivedData.data; 75 | end 76 | 77 | PACKET_DATA: begin 78 | if(State == PACKET_HEAD2) 79 | control.packetStart <= 1; 80 | else 81 | receivedWordsCntr <= receivedWordsCntr + 1; 82 | 83 | decodedBus.request <= 1; 84 | crc <= crc + receivedData.data; 85 | end 86 | 87 | PACKET_CRC: begin 88 | receivedHeader.crc = receivedData.data; 89 | if(receivedWordsCntr != 0) begin 90 | if(crc == receivedData.data) 91 | control.packetEnd <= 1; 92 | else 93 | control.packetErr <= 1; 94 | end 95 | end 96 | PACKET_NUM: receivedHeader.num <= receivedData.data; 97 | endcase 98 | end 99 | 100 | if(State == WAIT) 101 | {control.packetStart, control.packetEnd, control.packetErr, decodedBus.request} <= '0; 102 | 103 | if({control.packetStart, control.packetEnd, control.packetErr, decodedBus.request} != '0) 104 | {control.packetStart, control.packetEnd, control.packetErr, decodedBus.request} <= '0; 105 | 106 | end 107 | 108 | always_comb begin 109 | Next = State; 110 | unique case(State) 111 | WAIT: Next = PACKET_HEAD1; 112 | PACKET_HEAD1: Next = PACKET_HEAD2; 113 | PACKET_HEAD2: if(receivedHeader == TCC_UNKNOWN) Next = WAIT; 114 | else if(receivedHeader.size == 0) Next = PACKET_CRC; 115 | else Next = PACKET_DATA; 116 | 117 | PACKET_DATA: if(receivedWordsCntr == (receivedHeader.size - 1)) Next = PACKET_CRC; 118 | PACKET_CRC: Next = PACKET_NUM; 119 | PACKET_NUM: Next = PACKET_POST; 120 | PACKET_POST: if(receivedData.data != '0) Next = PACKET_HEAD1; 121 | endcase 122 | end 123 | 124 | endmodule 125 | 126 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/ServiceProtocolEncoder.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef SP_ENCODER_INCLUDE 8 | `define SP_ENCODER_INCLUDE 9 | 10 | interface IServiceProtocolEControl(); 11 | logic[7:0] addr; 12 | logic[15:0] size; 13 | ServiceProtocol::TCommandCode cmdCode; 14 | logic enable; 15 | 16 | modport slave(input addr, size, cmdCode, enable); 17 | modport master(output addr, size, cmdCode, enable); 18 | endinterface 19 | 20 | module ServiceProtocolEncoder(input bit nRst, clk, 21 | IPop.master data, 22 | IPush.master packet, 23 | IServiceProtocolEControl.slave control); 24 | 25 | enum logic [4:0] { WAIT, 26 | PACKET_HEAD1_L, PACKET_HEAD1_W, 27 | PACKET_HEAD2_L, PACKET_HEAD2_W, 28 | PACKET_DATA_LR, PACKET_DATA_LW, PACKET_DATA_SR, PACKET_DATA_SW, 29 | PACKET_CRC_L, PACKET_CRC_W, 30 | PACKET_NUM_L, PACKET_NUM_W, 31 | IDLE } State, Next; 32 | 33 | logic[15:0] cntr; 34 | logic[15:0] crc, num; 35 | 36 | import ServiceProtocol::*; 37 | ServiceProtocolHeaderPart headerPart; 38 | 39 | always_ff @ (posedge clk) 40 | if(!nRst) 41 | State <= WAIT; 42 | else 43 | State <= Next; 44 | 45 | always_ff @ (posedge clk) begin 46 | if(!nRst) 47 | num <= 0; 48 | 49 | if(Next == PACKET_HEAD1_L) begin 50 | crc <= '0; 51 | cntr <= control.size; 52 | {headerPart.part1, headerPart.part2} <= {control.addr, control.size, control.cmdCode}; 53 | end 54 | 55 | if(State == PACKET_HEAD1_L) 56 | num <= num + 1; 57 | 58 | if(Next == PACKET_DATA_LR) 59 | cntr <= cntr - 1; 60 | 61 | if(State == PACKET_HEAD1_L || State == PACKET_HEAD2_L || State == PACKET_DATA_SR) 62 | crc <= crc + packet.data; 63 | end 64 | 65 | 66 | always_comb begin 67 | case(State) 68 | WAIT: {data.request, packet.request, packet.data} = '0; 69 | PACKET_HEAD1_L: {data.request, packet.request, packet.data} = { 2'b01, headerPart.part1 }; 70 | PACKET_HEAD1_W: {data.request, packet.request, packet.data} = { 2'b00, headerPart.part1 }; 71 | PACKET_HEAD2_L: {data.request, packet.request, packet.data} = { 2'b01, headerPart.part2 }; 72 | PACKET_HEAD2_W: {data.request, packet.request, packet.data} = { 2'b00, headerPart.part2 }; 73 | PACKET_DATA_LR: begin {data.request, packet.request} = 2'b10; packet.data = 'x; end 74 | PACKET_DATA_LW: begin {data.request, packet.request} = 2'b00; packet.data = 'x; end 75 | PACKET_DATA_SR: {data.request, packet.request, packet.data} = { 2'b01, data.data }; 76 | PACKET_DATA_SW: {data.request, packet.request, packet.data} = { 2'b00, data.data }; 77 | PACKET_CRC_L: {data.request, packet.request, packet.data} = { 2'b01, crc }; 78 | PACKET_CRC_W: {data.request, packet.request, packet.data} = { 2'b00, crc }; 79 | PACKET_NUM_L: {data.request, packet.request, packet.data} = { 2'b01, num }; 80 | PACKET_NUM_W: {data.request, packet.request, packet.data} = { 2'b00, num }; 81 | IDLE: {data.request, packet.request, packet.data} = '0; 82 | endcase 83 | end 84 | 85 | always_comb begin 86 | Next = State; 87 | if(!control.enable) 88 | Next = WAIT; 89 | else 90 | unique case(State) 91 | WAIT: if(control.enable)Next = PACKET_HEAD1_L; 92 | PACKET_HEAD1_L: Next = PACKET_HEAD1_W; 93 | PACKET_HEAD1_W: if(packet.done) Next = PACKET_HEAD2_L; 94 | PACKET_HEAD2_L: Next = PACKET_HEAD2_W; 95 | PACKET_HEAD2_W: if(packet.done) Next = (cntr == '0) ? PACKET_CRC_L : PACKET_DATA_LR; 96 | PACKET_DATA_LR: Next = PACKET_DATA_LW; 97 | PACKET_DATA_LW: if(data.done) Next = PACKET_DATA_SR; 98 | PACKET_DATA_SR: Next = PACKET_DATA_SW; 99 | PACKET_DATA_SW: if(packet.done) Next = (cntr == '0) ? PACKET_CRC_L : PACKET_DATA_LR; 100 | PACKET_CRC_L: Next = PACKET_CRC_W; 101 | PACKET_CRC_W: if(packet.done) Next = PACKET_NUM_L; 102 | PACKET_NUM_L: Next = PACKET_NUM_W; 103 | PACKET_NUM_W: if(packet.done) Next = IDLE; 104 | IDLE: ; 105 | endcase 106 | end 107 | 108 | endmodule 109 | 110 | 111 | 112 | 113 | 114 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/controlBus.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef CONTROLBUS_INCLUDE 8 | `define CONTROLBUS_INCLUDE 9 | 10 | //get from IPop and push to IPush 11 | module BusPusher( input bit nRst, clk, 12 | input logic enable, 13 | IPush.master push, 14 | IPop.master pop); 15 | 16 | logic beginEnabled; 17 | upFront beginEnabledStrobe (nRst, clk, enable, beginEnabled); 18 | 19 | enum logic [2:0] {IDLE, READ_REQ, READ_WAIT, WRITE_REQ, WRITE_WAIT } State, Next; 20 | 21 | assign push.data = pop.data; 22 | assign push.request = (State == WRITE_REQ); 23 | assign pop.request = (State == READ_REQ); 24 | 25 | always_ff @ (posedge clk) 26 | if (!nRst) 27 | State <= IDLE; 28 | else 29 | State <= Next; 30 | 31 | always_comb begin 32 | Next = State; 33 | unique case(State) 34 | IDLE: if(beginEnabled) Next = READ_REQ; 35 | READ_REQ: Next = READ_WAIT; 36 | READ_WAIT: if(pop.done) Next = WRITE_REQ; 37 | WRITE_REQ: Next = WRITE_WAIT; 38 | WRITE_WAIT: if(push.done) 39 | Next = (enable) ? READ_REQ : IDLE; 40 | endcase 41 | end 42 | endmodule 43 | 44 | module BusMux( input bit nRst, clk, 45 | input logic [1:0] key, 46 | IPop.slave out, 47 | IPop.master in0, 48 | IPop.master in1); 49 | 50 | always_comb begin 51 | case(key) 52 | 2'b00: begin 53 | {out.data, out.done, in0.request} = {in0.data, in0.done, out.request}; 54 | in1.request = '0; 55 | end 56 | 2'b01: begin 57 | {out.data, out.done, in1.request} = {in1.data, in1.done, out.request}; 58 | in0.request = '0; 59 | end 60 | default: begin 61 | {out.done, in0.request, in1.request} = '0; 62 | out.data = 'x; 63 | end 64 | endcase 65 | end 66 | endmodule 67 | 68 | module BusMux2( input bit nRst, clk, 69 | input logic [2:0] key, 70 | IPop.slave out, 71 | IPop.master in0, 72 | IPop.master in1, 73 | IPop.master in2, 74 | IPop.master in3); 75 | 76 | always_comb begin 77 | case(key) 78 | 3'b000: begin 79 | {out.data, out.done, in0.request} = {in0.data, in0.done, out.request}; 80 | {in1.request, in2.request, in3.request} = '0; 81 | end 82 | 3'b001: begin 83 | {out.data, out.done, in1.request} = {in1.data, in1.done, out.request}; 84 | {in0.request, in2.request, in3.request} = '0; 85 | end 86 | 32'b010: begin 87 | {out.data, out.done, in2.request} = {in2.data, in2.done, out.request}; 88 | {in1.request, in0.request, in3.request} = '0; 89 | end 90 | 3'b011: begin 91 | {out.data, out.done, in3.request} = {in3.data, in3.done, out.request}; 92 | {in1.request, in2.request, in0.request} = '0; 93 | end 94 | default: begin 95 | {out.done, in0.request, in1.request, in2.request, in3.request} = '0; 96 | out.data = 'x; 97 | end 98 | endcase 99 | end 100 | endmodule 101 | 102 | module PushMux( input bit nRst, clk, 103 | input logic [1:0] key, 104 | IPush.slave in, 105 | IPush.master out0, 106 | IPush.master out1); 107 | 108 | always_comb begin 109 | case(key) 110 | 2'b00: begin 111 | {out0.data, out0.request, in.done } = {in.data, in.request, out0.done }; 112 | {out1.data, out1.request} = '0; 113 | end 114 | 2'b01: begin 115 | {out1.data, out1.request, in.done } = {in.data, in.request, out1.done }; 116 | {out0.data, out0.request} = '0; 117 | end 118 | default: begin 119 | {out0.request, out1.request, in.done } = '0; 120 | {out0.data, out1.data} = 'x; 121 | end 122 | endcase 123 | end 124 | endmodule 125 | 126 | module BusGate(input bit nRst, clk, 127 | input logic enable, 128 | IPush.slave in, 129 | IPush.master out); 130 | always_comb begin 131 | if(enable) 132 | {out.data, out.request, in.done} = {in.data, in.request, out.done}; 133 | else 134 | {out.data, out.request, in.done} = '0; 135 | end 136 | endmodule 137 | 138 | `endif 139 | -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/controlReset.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef CONTROLRESET_INCLUDE 8 | `define CONTROLRESET_INCLUDE 9 | 10 | module ResetGenerator( input bit nRst, clk, 11 | input logic nResetRequest, 12 | output logic nResetSignal); 13 | 14 | parameter pause = 16; 15 | logic [3:0] pauseCntr, nextCntr; 16 | logic [2:0] buffer; 17 | 18 | assign nResetSignal = (pauseCntr == '0) & nRst; 19 | 20 | always_ff @ (posedge clk) begin 21 | if(!nRst) begin 22 | buffer <= '1; 23 | pauseCntr <= '0; 24 | end 25 | else begin 26 | buffer <= {buffer[1:0], nResetRequest}; 27 | pauseCntr <= nextCntr; 28 | end 29 | end 30 | 31 | always_comb begin 32 | nextCntr = pauseCntr; 33 | if(buffer == '0) 34 | nextCntr = 1; 35 | else if(pauseCntr != '0) 36 | nextCntr = pauseCntr + 1; 37 | end 38 | 39 | endmodule 40 | 41 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/controlStatus.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef CONTROLSTATUS_INCLUDE 8 | `define CONTROLSTATUS_INCLUDE 9 | 10 | interface IStatusInfoControl(); 11 | logic enable; 12 | logic [15:0] statusWord0; 13 | logic [15:0] statusWord1; 14 | logic [15:0] statusWord2; 15 | logic [1:0] statusSize; 16 | 17 | modport slave (input enable, statusWord0, statusWord1, statusWord2, 18 | output statusSize); 19 | modport master( output enable, statusWord0, statusWord1, statusWord2, 20 | input statusSize); 21 | endinterface 22 | 23 | module StatusInfo(input bit nRst, clk, 24 | IPop.slave out, 25 | IStatusInfoControl.slave control); 26 | 27 | assign control.statusSize = 3; 28 | 29 | enum logic [2:0] {IDLE, SW0_L, SW0_S, SW1_L, SW1_S, SW2_L, SW2_S } Next, State; 30 | 31 | always_ff @ (posedge clk) 32 | if(!nRst | !control.enable) 33 | State <= IDLE; 34 | else 35 | State <= Next; 36 | 37 | assign out.done = (State == SW0_L || State == SW1_L || State == SW2_L); 38 | 39 | always_comb begin 40 | unique case(State) 41 | IDLE: out.data = 'x; 42 | SW0_L: out.data = control.statusWord0; 43 | SW0_S: out.data = control.statusWord0; 44 | SW1_L: out.data = control.statusWord1; 45 | SW1_S: out.data = control.statusWord1; 46 | SW2_L: out.data = control.statusWord2; 47 | SW2_S: out.data = control.statusWord2; 48 | endcase 49 | end 50 | 51 | always_comb begin 52 | Next = State; 53 | unique case(State) 54 | IDLE: if(out.request) Next = SW0_L; 55 | SW0_L: Next = SW0_S; 56 | SW0_S: if(out.request) Next = SW1_L; 57 | SW1_L: Next = SW1_S; 58 | SW1_S: if(out.request) Next = SW2_L; 59 | SW2_L: Next = SW2_S; 60 | SW2_S: ; 61 | endcase 62 | end 63 | 64 | endmodule 65 | 66 | `endif 67 | -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/interfaces.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `include "settings.sv" 8 | 9 | `ifndef INTERFACES_INCLUDE 10 | `define INTERFACES_INCLUDE 11 | 12 | interface IPush(); 13 | logic request, done; 14 | logic [`DATAW_TOP:0] data; 15 | 16 | modport master(output data, output request, input done); 17 | modport slave(input data, input request, output done); 18 | endinterface 19 | 20 | interface IPop(); 21 | logic request, done; 22 | logic [`DATAW_TOP:0] data; 23 | 24 | modport master(input data, output request, input done); 25 | modport slave(output data, input request, output done); 26 | endinterface 27 | 28 | interface IPushMil(); 29 | logic request, done; 30 | milStd1553::MilData data; 31 | 32 | modport master(output data, output request, input done); 33 | modport slave(input data, input request, output done); 34 | endinterface 35 | 36 | interface IPopMil(); 37 | logic request, done; 38 | milStd1553::MilData data; 39 | 40 | modport master(input data, output request, input done); 41 | modport slave(output data, input request, output done); 42 | endinterface 43 | 44 | interface ISpi(); 45 | tri1 nCS; 46 | tri0 mosi, sck, miso; 47 | 48 | modport master(output nCS, mosi, sck, input miso); 49 | modport slave(input nCS, mosi, sck, output miso); 50 | endinterface 51 | 52 | interface IMemory(); 53 | tri0 wr_enable, rd_enable; 54 | tri0 [`ADDRW_TOP:0] rd_addr; 55 | tri0 [`ADDRW_TOP:0] wr_addr; 56 | tri0 [`DATAW_TOP:0] wr_data; 57 | 58 | logic rd_ready, busy; 59 | logic [`DATAW_TOP:0] rd_data; 60 | 61 | modport writer(output wr_addr, wr_data, wr_enable, 62 | input busy); 63 | 64 | modport reader(output rd_addr, rd_enable, 65 | input rd_data, rd_ready, busy); 66 | 67 | modport memory(input wr_addr, wr_data, wr_enable, 68 | input rd_addr, rd_enable, 69 | output rd_data, rd_ready, busy); 70 | endinterface 71 | 72 | interface IArbiter(); 73 | logic request, grant; 74 | 75 | modport client(output request, input grant); 76 | modport arbiter(input request, output grant); 77 | endinterface 78 | 79 | interface IMemoryReader(); 80 | logic request, done; 81 | 82 | logic [`ADDRW_TOP:0] addr; 83 | logic [`DATAW_TOP:0] data; 84 | 85 | modport master(output addr, input data, output request, input done); 86 | modport slave(input addr, output data, input request, output done); 87 | endinterface 88 | 89 | interface IMemoryWriter(); 90 | logic request, done; 91 | 92 | logic [`ADDRW_TOP:0] addr; 93 | logic [`DATAW_TOP:0] data; 94 | 95 | modport master(output addr, output data, output request, input done); 96 | modport slave(input addr, input data, input request, output done); 97 | endinterface 98 | 99 | interface IMilStd(); 100 | logic TXout, nTXout, RXin, nRXin; 101 | 102 | //modport device(input RXin, nRXin, output TXout, nTXout); 103 | modport line(output RXin, nRXin, input TXout, nTXout); 104 | modport rx(input RXin, nRXin); 105 | modport tx(output TXout, nTXout); 106 | 107 | endinterface 108 | 109 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/ipMilSpiDoubleA.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILSPIDOUBLE_INCLUDE 8 | `define MILSPIDOUBLE_INCLUDE 9 | 10 | module IpMilSpiDoubleA(input logic clk, nRst, 11 | ISpi spi0, 12 | ISpi spi1, 13 | IMilStd mil0, 14 | IMilStd mil1, 15 | IMemory mbus); 16 | 17 | IPush spiToMem0(); 18 | IPush milToMem0(); 19 | IPop memToSpi0(); 20 | IPop memToMil0(); 21 | IRingBufferControl milToSpiRBControl0(); 22 | IRingBufferControl spiToMilRBControl0(); 23 | 24 | IPush spiToMem1(); 25 | IPush milToMem1(); 26 | IPop memToSpi1(); 27 | IPop memToMil1(); 28 | IRingBufferControl milToSpiRBControl1(); 29 | IRingBufferControl spiToMilRBControl1(); 30 | logic nResetRequest0, nResetRequest1, nResetSignal; 31 | 32 | ResetGenerator resetGenerator(.nRst(nRst), .clk(clk), 33 | .nResetRequest(nResetRequest0 & nResetRequest1), 34 | .nResetSignal(nResetSignal)); 35 | 36 | MilSpiBlock milSpiBlock0(.nRst(nResetSignal), .clk(clk), 37 | .spi(spi0), .mil(mil0), 38 | .pushFromMil(milToMem0.master), 39 | .pushFromSpi(spiToMem0.master), 40 | .popToSpi(memToSpi0.master), 41 | .popToMil(memToMil0.master), 42 | .rcontrolMS(milToSpiRBControl0.master), 43 | .rcontrolSM(spiToMilRBControl0.master), 44 | .nResetRequest(nResetRequest0)); 45 | 46 | MilSpiBlock milSpiBlock1(.nRst(nResetSignal), .clk(clk), 47 | .spi(spi1), .mil(mil1), 48 | .pushFromMil(milToMem1.master), 49 | .pushFromSpi(spiToMem1.master), 50 | .popToSpi(memToSpi1.master), 51 | .popToMil(memToMil1.master), 52 | .rcontrolMS(milToSpiRBControl1.master), 53 | .rcontrolSM(spiToMilRBControl1.master), 54 | .nResetRequest(nResetRequest1)); 55 | 56 | MemoryBlock2 memoryBlock(.nRst(nResetSignal), .clk(clk), 57 | .push0(spiToMem0.slave), 58 | .push1(spiToMem1.slave), 59 | .push2(milToMem0.slave), 60 | .push3(milToMem1.slave), 61 | .pop0(memToMil0.slave), 62 | .pop1(memToMil1.slave), 63 | .pop2(memToSpi0.slave), 64 | .pop3(memToSpi1.slave), 65 | .rc0(spiToMilRBControl0.slave), 66 | .rc1(spiToMilRBControl1.slave), 67 | .rc2(milToSpiRBControl0.slave), 68 | .rc3(milToSpiRBControl1.slave), 69 | .mbus(mbus)); 70 | 71 | endmodule 72 | 73 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/ipMilSpiDoubleB.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILSPIDOUBLE_INCLUDE 8 | `define MILSPIDOUBLE_INCLUDE 9 | 10 | module IpMilSpiDoubleB(input logic clk, nRst, 11 | ISpi spi, 12 | IMilStd mil0, 13 | IMilStd mil1, 14 | IMemory mbus); 15 | 16 | IPush spiToMem0(); 17 | IPush milToMem0(); 18 | IPop memToSpi0(); 19 | IPop memToMil0(); 20 | IRingBufferControl milToSpiRBControl0(); 21 | IRingBufferControl spiToMilRBControl0(); 22 | 23 | IPush spiToMem1(); 24 | IPush milToMem1(); 25 | IPop memToSpi1(); 26 | IPop memToMil1(); 27 | IRingBufferControl milToSpiRBControl1(); 28 | IRingBufferControl spiToMilRBControl1(); 29 | logic nResetRequest, nResetSignal; 30 | 31 | ResetGenerator resetGenerator( .nRst(nRst), .clk(clk), 32 | .nResetRequest(nResetRequest), 33 | .nResetSignal(nResetSignal)); 34 | 35 | MilSpiBlock2 milSpiBlock( .nRst(nResetSignal), .clk(clk), 36 | .spi(spi), 37 | .mil0(mil0), 38 | .mil1(mil1), 39 | .pushFromMil0(milToMem0.master), 40 | .pushFromMil1(milToMem1.master), 41 | .pushFromSpi0(spiToMem0.master), 42 | .pushFromSpi1(spiToMem1.master), 43 | .popToSpi0(memToSpi0.master), 44 | .popToSpi1(memToSpi1.master), 45 | .popToMil0(memToMil0.master), 46 | .popToMil1(memToMil1.master), 47 | .rcontrolMS0(milToSpiRBControl0.master), 48 | .rcontrolSM0(spiToMilRBControl0.master), 49 | .rcontrolMS1(milToSpiRBControl1.master), 50 | .rcontrolSM1(spiToMilRBControl1.master), 51 | .nResetRequest(nResetRequest)); 52 | 53 | MemoryBlock2 memoryBlock(.nRst(nResetSignal), .clk(clk), 54 | .push0(spiToMem0.slave), 55 | .push1(spiToMem1.slave), 56 | .push2(milToMem0.slave), 57 | .push3(milToMem1.slave), 58 | .pop0(memToMil0.slave), 59 | .pop1(memToMil1.slave), 60 | .pop2(memToSpi0.slave), 61 | .pop3(memToSpi1.slave), 62 | .rc0(spiToMilRBControl0.slave), 63 | .rc1(spiToMilRBControl1.slave), 64 | .rc2(milToSpiRBControl0.slave), 65 | .rc3(milToSpiRBControl1.slave), 66 | .mbus(mbus)); 67 | 68 | endmodule 69 | 70 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/ipMilSpiSingle.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILSPISINGLE_INCLUDE 8 | `define MILSPISINGLE_INCLUDE 9 | 10 | module IpMilSpiSingle(input logic clk, nRst, 11 | ISpi spi, 12 | IMilStd mil, 13 | IMemory mbus); 14 | 15 | IPush spiToMem(); 16 | IPush milToMem(); 17 | IPop memToSpi(); 18 | IPop memToMil(); 19 | IRingBufferControl milToSpiRBControl(); 20 | IRingBufferControl spiToMilRBControl(); 21 | logic nResetRequest, nResetSignal; 22 | 23 | ResetGenerator resetGenerator(.nRst(nRst), .clk(clk), 24 | .nResetRequest(nResetRequest), 25 | .nResetSignal(nResetSignal)); 26 | 27 | MilSpiBlock milSpiBlock(.nRst(nResetSignal), .clk(clk), 28 | .spi(spi), .mil(mil), 29 | .pushFromMil(milToMem.master), 30 | .pushFromSpi(spiToMem.master), 31 | .popToSpi(memToSpi.master), 32 | .popToMil(memToMil.master), 33 | .rcontrolMS(milToSpiRBControl.master), 34 | .rcontrolSM(spiToMilRBControl.master), 35 | .nResetRequest(nResetRequest)); 36 | 37 | MemoryBlock memoryBlock(.nRst(nResetSignal), .clk(clk), 38 | .push0(spiToMem.slave), 39 | .push1(milToMem.slave), 40 | .pop0(memToMil.slave), 41 | .pop1(memToSpi.slave), 42 | .rcontrol0(spiToMilRBControl.slave), 43 | .rcontrol1(milToSpiRBControl.slave), 44 | .mbus(mbus)); 45 | 46 | endmodule 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/linkMil.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef LINKMIL_INCLUDE 8 | `define LINKMIL_INCLUDE 9 | 10 | module LinkMil(input bit nRst, clk, 11 | IPush.master pushFromMil, 12 | IPush.slave pushToMil, 13 | IMilControl.slave milControl, 14 | IMilStd mil); 15 | 16 | IPushMil rmpush(); 17 | IPushMil tmpush(); 18 | 19 | milTransceiver milStd(.nRst(nRst), .clk(clk), 20 | .rpush(rmpush.master), .tpush(tmpush.slave), 21 | .mil(mil), .control(milControl)); 22 | 23 | milMemEncoder milToMemEncoder(.nRst(nRst), .clk(clk), 24 | .mil(rmpush.slave), 25 | .push(pushFromMil)); 26 | 27 | memMilEncoder memToMilEncoder(.nRst(nRst), .clk(clk), 28 | .mil(tmpush.master), 29 | .push(pushToMil)); 30 | 31 | endmodule 32 | 33 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/linkSpi.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef LINKSPI_INCLUDE 8 | `define LINKSPI_INCLUDE 9 | 10 | 11 | interface ILinkSpiControl(); 12 | //from ISpiReceiverControl 13 | logic outQueueOverflow, inQueueOverflow, spiIsBusy; 14 | 15 | //from IServiceProtocolDControl 16 | logic [7:0] inAddr; 17 | logic [7:0] inWordNum; 18 | logic [15:0] inSize; 19 | ServiceProtocol::TCommandCode inCmdCode; 20 | logic inPacketStart, inPacketErr, inPacketEnd; 21 | 22 | //from IServiceProtocolEControl 23 | logic [7:0] outAddr; 24 | logic outEnable; 25 | logic [15:0] outDataSize; 26 | ServiceProtocol::TCommandCode outCmdCode; 27 | 28 | modport slave( output inCmdCode, inWordNum, inAddr, inSize, 29 | inPacketStart, inPacketErr, inPacketEnd, 30 | spiIsBusy, outQueueOverflow, inQueueOverflow, 31 | input outEnable, outCmdCode, outDataSize, outAddr); 32 | 33 | modport master( input inCmdCode, inWordNum, inAddr, inSize, 34 | inPacketStart, inPacketErr, inPacketEnd, 35 | spiIsBusy, outQueueOverflow, inQueueOverflow, 36 | output outEnable, outCmdCode, outDataSize, outAddr); 37 | endinterface 38 | 39 | module LinkSpi( input bit nRst, clk, 40 | ISpi.slave spi, 41 | IPush.master pushFromSpi, 42 | IPop.master popToSpi, 43 | ILinkSpiControl.slave control); 44 | 45 | IPush rspi(); 46 | IPush tspi(); 47 | ISpiReceiverControl spiControl(); 48 | SpiReceiver spiReceiver(.nRst(nRst), .clk(clk), 49 | .transmitBus(tspi.slave), .receiveBus(rspi.master), 50 | .controlBus(spiControl.slave), .spi(spi)); 51 | 52 | IServiceProtocolDControl decoderControl(); 53 | ServiceProtocolDecoder spDecoder(.nRst(nRst), .clk(clk), 54 | .receivedData(rspi.slave), .decodedBus(pushFromSpi), 55 | .control(decoderControl.slave)); 56 | 57 | IServiceProtocolEControl encoderControl(); 58 | ServiceProtocolEncoder spEncoder(.nRst(nRst), .clk(clk), 59 | .data(popToSpi), .packet(tspi.master), 60 | .control(encoderControl.slave)); 61 | 62 | //ISpiReceiverControl 63 | assign control.spiIsBusy = spiControl.isBusy; 64 | assign control.outQueueOverflow = spiControl.overflowInTQueue; 65 | assign control.inQueueOverflow = spiControl.overflowInRQueue; 66 | 67 | //IServiceProtocolDControl 68 | assign control.inCmdCode = decoderControl.cmdCode; 69 | assign control.inWordNum = decoderControl.wordNum; 70 | assign control.inPacketStart = decoderControl.packetStart; 71 | assign control.inPacketErr = decoderControl.packetErr; 72 | assign control.inPacketEnd = decoderControl.packetEnd; 73 | assign control.inAddr = decoderControl.addr; 74 | assign control.inSize = decoderControl.size; 75 | assign decoderControl.enable = spiControl.isBusy; 76 | 77 | //IServiceProtocolEControl 78 | assign encoderControl.cmdCode = control.outCmdCode; 79 | assign encoderControl.addr = control.outAddr; 80 | assign encoderControl.enable = control.outEnable; 81 | assign encoderControl.size = control.outDataSize; 82 | 83 | endmodule 84 | 85 | `endif 86 | -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/milConnectionPoint.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILCONNPOINT_INCLUDE 8 | `define MILCONNPOINT_INCLUDE 9 | 10 | module MilConnectionPoint( IMilStd.line mil0, 11 | IMilStd.line mil1); 12 | 13 | assign mil0.RXin = mil0.TXout | mil1.TXout; 14 | assign mil0.nRXin = mil0.nTXout | mil1.nTXout; 15 | assign mil1.RXin = mil0.RXin; 16 | assign mil1.nRXin = mil0.nRXin; 17 | 18 | endmodule 19 | 20 | module MilConnectionPoint3( IMilStd.line mil0, 21 | IMilStd.line mil1, 22 | IMilStd.line mil2); 23 | 24 | assign mil0.RXin = mil0.TXout | mil1.TXout | mil2.TXout; 25 | assign mil0.nRXin = mil0.nTXout | mil1.nTXout | mil2.nTXout; 26 | assign mil1.RXin = mil0.RXin; 27 | assign mil1.nRXin = mil0.nRXin; 28 | assign mil2.RXin = mil0.RXin; 29 | assign mil2.nRXin = mil0.nRXin; 30 | 31 | endmodule 32 | 33 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/milData.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILDATA_INCLUDE 8 | `define MILDATA_INCLUDE 9 | 10 | package milStd1553; 11 | 12 | typedef enum logic[1:0] { 13 | WSERVERR = 2'b00, 14 | WSERV = 2'b01, 15 | WDATAERR = 2'b10, 16 | WDATA = 2'b11 17 | } WordType; 18 | 19 | typedef struct packed { 20 | WordType dataType; 21 | logic [15:0] dataWord; 22 | } MilData; 23 | 24 | endpackage 25 | 26 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/milEncoderDecoder.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `include "settings.sv" 8 | 9 | `ifndef MILENDECODER_INCLUDE 10 | `define MILENDECODER_INCLUDE 11 | 12 | `define ESC_WSERVERR 16'hFFA0 13 | `define ESC_WSERV 16'hFFA1 14 | `define ESC_WDATAERR 16'hFFA2 15 | `define ESC_WDATA 16'hFFA3 16 | 17 | module milMemEncoder(input bit nRst, clk, 18 | IPushMil.slave mil, 19 | IPush.master push); 20 | 21 | import milStd1553::*; 22 | 23 | logic [`DATAW_TOP:0] data, nextData, escData; 24 | assign push.data = data; 25 | 26 | enum logic[2:0] {IDLE = 3'd0, WORD1_LOAD = 3'd1, WORD1_WAIT = 3'd2, 27 | WORD2_LOAD = 3'd3, WORD2_WAIT = 3'd4, REPORT = 3'd5 } State, Next; 28 | 29 | assign push.request = (State == WORD1_LOAD || State == WORD2_LOAD); 30 | assign mil.done = (State == REPORT); 31 | 32 | always_ff @ (posedge clk) 33 | if(!nRst) 34 | State = IDLE; 35 | else 36 | State = Next; 37 | 38 | always_ff @ (posedge clk) begin 39 | data <= nextData; 40 | end 41 | 42 | always_comb begin 43 | unique case(mil.data.dataType) 44 | WSERVERR: escData = `ESC_WSERVERR; 45 | WSERV: escData = `ESC_WSERV; 46 | WDATAERR: escData = `ESC_WDATAERR; 47 | WDATA: escData = `ESC_WDATA; 48 | endcase 49 | 50 | Next = State; 51 | unique case(State) 52 | IDLE: if(mil.request) Next = WORD1_LOAD; 53 | WORD1_LOAD: Next = WORD1_WAIT; 54 | WORD1_WAIT: if(push.done) Next = WORD2_LOAD; 55 | WORD2_LOAD: Next = WORD2_WAIT; 56 | WORD2_WAIT: if(push.done) Next = REPORT; 57 | REPORT: Next = IDLE; 58 | endcase 59 | 60 | nextData = 'z; 61 | unique case(Next) 62 | IDLE: ; 63 | WORD1_LOAD: nextData = escData; 64 | WORD1_WAIT: nextData = escData; 65 | WORD2_LOAD: nextData = mil.data.dataWord; 66 | WORD2_WAIT: nextData = mil.data.dataWord; 67 | REPORT: ; 68 | endcase 69 | end 70 | 71 | endmodule 72 | 73 | 74 | module memMilEncoder(input bit nRst, clk, 75 | IPushMil.master mil, 76 | IPush.slave push); 77 | 78 | import milStd1553::*; 79 | WordType dataType, nextDataType; 80 | 81 | enum logic[2:0] {IDLE = 3'd0, WORD1_DONE = 3'd1, WORD2_LOAD = 3'd2, 82 | WORD2_SEND = 3'd3, WORD2_WAIT = 3'd4, WORD2_DONE = 3'd5} State, Next; 83 | 84 | assign mil.request = (State == WORD2_SEND); 85 | assign push.done = (State == WORD1_DONE || State == WORD2_DONE); 86 | 87 | always_ff @ (posedge clk) 88 | if(!nRst) 89 | State = IDLE; 90 | else 91 | State = Next; 92 | 93 | logic idleState; //strange bug, not working wout this 94 | assign idleState = (State == IDLE); 95 | 96 | always_ff @ (posedge clk) begin 97 | if(idleState) 98 | dataType <= nextDataType; 99 | if(Next == WORD2_SEND) begin 100 | mil.data.dataWord <= push.data; 101 | mil.data.dataType <= dataType; 102 | end 103 | end 104 | 105 | always_comb begin 106 | nextDataType = WDATA; 107 | priority case(push.data) 108 | `ESC_WSERVERR: nextDataType = WSERVERR; 109 | `ESC_WSERV: nextDataType = WSERV; 110 | `ESC_WDATAERR: nextDataType = WDATAERR; 111 | `ESC_WDATA: nextDataType = WDATA; 112 | default: nextDataType = WDATA; 113 | endcase 114 | end 115 | 116 | always_comb begin 117 | Next = State; 118 | unique case(State) 119 | IDLE: if(push.request) Next = WORD1_DONE; 120 | WORD1_DONE: Next = WORD2_LOAD; 121 | WORD2_LOAD: if(push.request) Next = WORD2_SEND; 122 | WORD2_SEND: Next = WORD2_WAIT; 123 | WORD2_WAIT: if(mil.done) Next = WORD2_DONE; 124 | WORD2_DONE: Next = IDLE; 125 | endcase 126 | end 127 | 128 | endmodule 129 | 130 | `endif 131 | -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/milReceiver.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILRECEIVER_INCLUDE 8 | `define MILRECEIVER_INCLUDE 9 | 10 | interface IMilRxControl(); 11 | logic grant, busy; 12 | 13 | modport slave( input grant, output busy); 14 | modport master( output grant, input busy); 15 | 16 | endinterface 17 | 18 | module milReceiver( input bit nRst, clk, 19 | IMilStd.rx mil, 20 | IPushMil.master push, 21 | IMilRxControl.slave control); 22 | 23 | import milStd1553::*; 24 | 25 | logic _RXin; 26 | inputFilter iFilter0(nRst, clk, mil.RXin, _RXin); 27 | inputFilter iFilter1(nRst, clk, (mil.RXin | mil.nRXin), control.busy); 28 | 29 | logic signal; 30 | assign signal = (control.grant) ? _RXin : 1'b0; 31 | 32 | logic readStrobe; 33 | readStrobeGenerator strobeGen(nRst, clk, signal, readStrobe); 34 | 35 | struct packed { 36 | logic [1:0] prev; 37 | logic [5:0] sync; 38 | logic [31:0] content; 39 | logic [1:0] parity; 40 | logic [2:0] next; 41 | } buffer; 42 | 43 | logic wordReceived, parityIsIncorrect; 44 | MilData data; 45 | logic [16:0] error; 46 | 47 | upFront wordReceivedUp(nRst, clk, wordReceived, push.request); 48 | 49 | always_ff @ (posedge clk) begin 50 | if(!nRst) 51 | buffer <= '0; 52 | else begin 53 | if(readStrobe) 54 | buffer <= {buffer[($bits(buffer) - 2):0], signal}; 55 | if(wordReceived) 56 | push.data <= data; 57 | end 58 | end 59 | 60 | always_comb begin 61 | 62 | for(int i = 0; i != 16; i++) begin 63 | data.dataWord[i] = buffer.content[i * 2 + 1]; 64 | error[i] = !(buffer.content[i * 2] ^ buffer.content[i * 2 + 1]); 65 | end 66 | error[16] = !(^buffer.parity); 67 | 68 | wordReceived = 1'b0; 69 | parityIsIncorrect = (buffer.parity[1] == (^data.dataWord)); 70 | 71 | if(error == '0) begin 72 | if( buffer.sync == 6'b111000 && (buffer.next == 3'b000 || buffer.next == 3'b111)) begin 73 | data.dataType = parityIsIncorrect ? WSERVERR : WSERV; 74 | wordReceived = 1'b1; 75 | end 76 | if( buffer.sync == 6'b000111 && (buffer.next == 3'b000 || buffer.next == 3'b111) && buffer.prev != 2'b00) begin 77 | data.dataType = parityIsIncorrect? WDATAERR : WDATA; 78 | wordReceived = 1'b1; 79 | end 80 | end 81 | end 82 | 83 | endmodule 84 | 85 | module readStrobeGenerator( input bit nRst, clk, 86 | input logic line, 87 | output logic strobe); 88 | parameter period = 49; 89 | parameter start = 25; 90 | 91 | logic changeStrobe; 92 | logic [5:0] cntr, nextCntr; 93 | 94 | assign strobe = (cntr == 0); 95 | 96 | signalChange schange(nRst, clk, line, changeStrobe); 97 | 98 | always_ff @ (posedge clk) 99 | cntr <= nextCntr; 100 | 101 | always_comb begin 102 | if(!nRst | changeStrobe) nextCntr = start; 103 | else if(cntr == period) nextCntr = 0; 104 | else nextCntr = cntr + 1; 105 | end 106 | endmodule 107 | 108 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/milSpiBlock.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILSPIBLOCK_INCLUDE 8 | `define MILSPIBLOCK_INCLUDE 9 | 10 | module MilSpiBlock ( input logic nRst, clk, 11 | ISpi spi, 12 | IMilStd mil, 13 | IPush.master pushFromMil, //from mil 14 | IPush.master pushFromSpi, //from spi 15 | IPop.master popToSpi, //to spi 16 | IPop.master popToMil, //to mil 17 | IRingBufferControl.master rcontrolMS, // mil -> spi 18 | IRingBufferControl.master rcontrolSM, // spi -> mil 19 | output logic nResetRequest); 20 | 21 | parameter SPI_BLOCK_ADDR = 8'hAB; 22 | 23 | import ServiceProtocol::*; 24 | 25 | logic enablePushToMil, enablePushFromSpi; 26 | logic [1:0] muxKeyPopToSpi; 27 | 28 | IPush tMilPush(); 29 | IPush rSpiPush(); 30 | IPop tSpiPop(); 31 | IPop tStatPop(); 32 | 33 | IMilControl milControl(); 34 | ILinkSpiControl spiControl(); 35 | IStatusInfoControl statusControl(); 36 | 37 | //mil -> mem 38 | LinkMil linkMil(.nRst(nRst), .clk(clk), 39 | .pushFromMil(pushFromMil), 40 | .pushToMil(tMilPush), 41 | .milControl(milControl.slave), 42 | .mil(mil)); 43 | 44 | //mil <- busPusher(enablePushToMil) <- mem 45 | BusPusher busPusher(.nRst(nRst), .clk(clk), 46 | .enable(enablePushToMil), 47 | .push(tMilPush.master), 48 | .pop(popToMil)); 49 | 50 | LinkSpi linkSpi(.nRst(nRst), .clk(clk), 51 | .spi(spi.slave), 52 | .pushFromSpi(rSpiPush.master), 53 | .popToSpi(tSpiPop.master), 54 | .control(spiControl.slave)); 55 | 56 | //spi -> busGate(enablePushFromSpi) -> mem 57 | BusGate busGate(.nRst(nRst), .clk(clk), 58 | .enable(enablePushFromSpi), 59 | .in(rSpiPush.slave), 60 | .out(pushFromSpi)); 61 | 62 | //spi <- busMux(muxKeyPopToSpi) <= mem, status 63 | BusMux busMus( .nRst(nRst), .clk(clk), 64 | .key(muxKeyPopToSpi), 65 | .out(tSpiPop.slave), 66 | .in0(popToSpi), 67 | .in1(tStatPop.master)); 68 | 69 | //status word generator 70 | StatusInfo statusInfo( .nRst(nRst), .clk(clk), 71 | .out(tStatPop.slave), 72 | .control(statusControl)); 73 | 74 | //error counter 75 | logic [15:0] errorCounter; 76 | always_ff @ (posedge clk) begin 77 | if(!nRst) 78 | errorCounter <= 0; 79 | else 80 | errorCounter <= errorCounter + rcontrolSM.rollback; 81 | end 82 | 83 | //control interfaces 84 | assign statusControl.statusWord0 = rcontrolMS.memUsed; 85 | assign statusControl.statusWord1 = rcontrolSM.memUsed; 86 | assign statusControl.statusWord2 = errorCounter; 87 | 88 | //module addr filter 89 | logic addrCorrect; 90 | assign addrCorrect = (spiControl.inAddr == SPI_BLOCK_ADDR); 91 | 92 | //command processing 93 | logic [4:0] conf; 94 | 95 | TCommandCode commandCode; 96 | assign commandCode = addrCorrect ? spiControl.inCmdCode : TCC_UNKNOWN; 97 | assign spiControl.outAddr = SPI_BLOCK_ADDR; 98 | assign spiControl.outCmdCode = commandCode; 99 | assign rcontrolSM.open = addrCorrect ? spiControl.inPacketStart : 0; 100 | assign rcontrolSM.commit = addrCorrect ? spiControl.inPacketEnd : 0; 101 | assign rcontrolSM.rollback = addrCorrect ? spiControl.inPacketErr : 0; 102 | 103 | assign { rcontrolMS.open, rcontrolMS.commit, rcontrolMS.rollback } = '0; 104 | 105 | assign { enablePushFromSpi, muxKeyPopToSpi, 106 | spiControl.outEnable, statusControl.enable } = conf; 107 | 108 | assign enablePushToMil = (rcontrolSM.memUsed != 0); 109 | 110 | always_ff @ (posedge clk) begin 111 | if(!nRst) 112 | nResetRequest <= 1; 113 | 114 | if(commandCode == TCC_RESET) 115 | nResetRequest <= 0; 116 | end 117 | 118 | always_comb begin 119 | case(commandCode) 120 | default: conf = 5'b01100; 121 | TCC_UNKNOWN: conf = 5'b01100; 122 | TCC_RESET: conf = 5'b01100; // device reset 123 | TCC_SEND_DATA: conf = 5'b11100; // send data to mil 124 | TCC_RECEIVE_STS: conf = 5'b00111; // send status to spi 125 | TCC_RECEIVE_DATA: conf = 5'b00010; // send all the received data to spi 126 | endcase 127 | end 128 | 129 | always_comb begin 130 | case(commandCode) 131 | default: spiControl.outDataSize = '0; 132 | TCC_RECEIVE_STS: spiControl.outDataSize = statusControl.statusSize; 133 | TCC_RECEIVE_DATA: spiControl.outDataSize = (spiControl.inSize < rcontrolMS.memUsed) ? 134 | spiControl.inSize : rcontrolMS.memUsed; 135 | endcase 136 | end 137 | 138 | endmodule 139 | 140 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/milSpiBlock2.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILSPIBLOCK2_INCLUDE 8 | `define MILSPIBLOCK2_INCLUDE 9 | 10 | module MilSpiBlock2 ( input logic nRst, clk, 11 | ISpi spi, 12 | IMilStd mil0, 13 | IMilStd mil1, 14 | IPush.master pushFromMil0, //from mil0 15 | IPush.master pushFromMil1, //from mil1 16 | IPush.master pushFromSpi0, //from spi0 17 | IPush.master pushFromSpi1, //from spi1 18 | IPop.master popToSpi0, //to spi0 19 | IPop.master popToSpi1, //to spi1 20 | IPop.master popToMil0, //to mil0 21 | IPop.master popToMil1, //to mil1 22 | IRingBufferControl.master rcontrolMS0, // mil0 -> spi 23 | IRingBufferControl.master rcontrolSM0, // spi -> mil0 24 | IRingBufferControl.master rcontrolMS1, // mil1 -> spi 25 | IRingBufferControl.master rcontrolSM1, // spi -> mil1 26 | output logic nResetRequest); 27 | 28 | parameter SPI_BLOCK_ADDR0 = 8'hAB; 29 | parameter SPI_BLOCK_ADDR1 = 8'hAC; 30 | 31 | import ServiceProtocol::*; 32 | 33 | logic [1:0] muxKeyPushFromSpi; 34 | logic [2:0] muxKeyPopToSpi; 35 | logic enablePushToMil0, enablePushToMil1; 36 | 37 | IPush tMilPush0(); 38 | IPush tMilPush1(); 39 | IPush rSpiPush(); 40 | IPop tSpiPop(); 41 | IPop tStatPop0(); 42 | IPop tStatPop1(); 43 | 44 | IMilControl milControl0(); 45 | IMilControl milControl1(); 46 | ILinkSpiControl spiControl(); 47 | IStatusInfoControl statusControl0(); 48 | IStatusInfoControl statusControl1(); 49 | 50 | //mil0 -> mem 51 | LinkMil linkMil0(.nRst(nRst), .clk(clk), 52 | .pushFromMil(pushFromMil0), 53 | .pushToMil(tMilPush0), 54 | .milControl(milControl0.slave), 55 | .mil(mil0)); 56 | 57 | //mil1 -> mem 58 | LinkMil linkMil1(.nRst(nRst), .clk(clk), 59 | .pushFromMil(pushFromMil1), 60 | .pushToMil(tMilPush1), 61 | .milControl(milControl1.slave), 62 | .mil(mil1)); 63 | 64 | //mil0 <- busPusher(enablePushToMil0) <- mem 65 | BusPusher busPusher0(.nRst(nRst), .clk(clk), 66 | .enable(enablePushToMil0), 67 | .push(tMilPush0.master), 68 | .pop(popToMil0)); 69 | 70 | //mil1 <- busPusher(enablePushToMil1) <- mem 71 | BusPusher busPusher1(.nRst(nRst), .clk(clk), 72 | .enable(enablePushToMil1), 73 | .push(tMilPush1.master), 74 | .pop(popToMil1)); 75 | 76 | LinkSpi linkSpi(.nRst(nRst), .clk(clk), 77 | .spi(spi.slave), 78 | .pushFromSpi(rSpiPush.master), 79 | .popToSpi(tSpiPop.master), 80 | .control(spiControl.slave)); 81 | 82 | //spi -> PushMux(muxKeyPushFromSpi) => mem0, mem1 83 | PushMux pushMux(.nRst(nRst), .clk(clk), 84 | .key(muxKeyPushFromSpi), 85 | .in(rSpiPush), 86 | .out0(pushFromSpi0), 87 | .out1(pushFromSpi1)); 88 | 89 | //spi <- BusMux2(muxKeyPopToSpi) <= mem0, status0, mem1, status1 90 | BusMux2 busMux( .nRst(nRst), .clk(clk), 91 | .key(muxKeyPopToSpi), 92 | .out(tSpiPop.slave), 93 | .in0(popToSpi0), 94 | .in1(tStatPop0.master), 95 | .in2(popToSpi1), 96 | .in3(tStatPop1.master)); 97 | 98 | //status word generator 99 | StatusInfo statusInfo0( .nRst(nRst), .clk(clk), 100 | .out(tStatPop0.slave), 101 | .control(statusControl0)); 102 | 103 | //status word generator 104 | StatusInfo statusInfo1( .nRst(nRst), .clk(clk), 105 | .out(tStatPop1.slave), 106 | .control(statusControl1)); 107 | 108 | //checksum error counters 109 | logic [15:0] errorCounter0; 110 | logic [15:0] errorCounter1; 111 | always_ff @ (posedge clk) begin 112 | if(!nRst) 113 | {errorCounter0, errorCounter1} <= 0; 114 | else begin 115 | errorCounter0 <= errorCounter0 + rcontrolSM0.rollback; 116 | errorCounter1 <= errorCounter1 + rcontrolSM1.rollback; 117 | end 118 | end 119 | 120 | //control interfaces 121 | assign statusControl0.statusWord0 = rcontrolMS0.memUsed; 122 | assign statusControl0.statusWord1 = rcontrolSM0.memUsed; 123 | assign statusControl0.statusWord2 = errorCounter0; 124 | assign statusControl1.statusWord0 = rcontrolMS1.memUsed; 125 | assign statusControl1.statusWord1 = rcontrolSM1.memUsed; 126 | assign statusControl1.statusWord2 = errorCounter1; 127 | 128 | //command processing 129 | logic [8:0] confOut; 130 | assign { muxKeyPushFromSpi, muxKeyPopToSpi, spiControl.outEnable, 131 | nResetRequest, statusControl0.enable, statusControl1.enable } = confOut; 132 | assign enablePushToMil0 = (rcontrolSM0.memUsed != 0); 133 | assign enablePushToMil1 = (rcontrolSM1.memUsed != 0); 134 | 135 | assign {rcontrolMS0.open, rcontrolMS0.commit, rcontrolMS0.rollback} = '0; 136 | assign {rcontrolMS1.open, rcontrolMS1.commit, rcontrolMS1.rollback} = '0; 137 | 138 | logic [5:0] confIn; 139 | assign confIn[0] = (spiControl.inAddr == SPI_BLOCK_ADDR0); 140 | assign confIn[1] = (spiControl.inAddr == SPI_BLOCK_ADDR1); 141 | assign confIn[2] = (spiControl.inCmdCode == TCC_RESET); 142 | assign confIn[3] = (spiControl.inCmdCode == TCC_SEND_DATA); 143 | assign confIn[4] = (spiControl.inCmdCode == TCC_RECEIVE_STS); 144 | assign confIn[5] = (spiControl.inCmdCode == TCC_RECEIVE_DATA); 145 | 146 | always_comb begin 147 | case(confIn) 148 | default: confOut = 9'b101000100; 149 | 6'b100001: confOut = 9'b100001100; // TCC_RECEIVE_DATA from SPI_BLOCK_ADDR0 150 | 6'b010001: confOut = 9'b100011110; // TCC_RECEIVE_STS from SPI_BLOCK_ADDR0 151 | 6'b001001: confOut = 9'b001000100; // TCC_SEND_DATA from SPI_BLOCK_ADDR0 152 | 6'b000101: confOut = 9'b101000000; // TCC_RESET from SPI_BLOCK_ADDR0 153 | 6'b100010: confOut = 9'b100101100; // TCC_RECEIVE_DATA from SPI_BLOCK_ADDR1 154 | 6'b010010: confOut = 9'b100111101; // TCC_RECEIVE_STS from SPI_BLOCK_ADDR1 155 | 6'b001010: confOut = 9'b011000100; // TCC_SEND_DATA from SPI_BLOCK_ADDR1 156 | 6'b000110: confOut = 9'b101000100; // TCC_RESET from SPI_BLOCK_ADDR1 157 | endcase 158 | end 159 | 160 | // TCC_SEND_DATA from SPI_BLOCK_ADDR0 161 | assign rcontrolSM0.open = (confIn == 6'b001001) ? spiControl.inPacketStart : '0; 162 | assign rcontrolSM0.commit = (confIn == 6'b001001) ? spiControl.inPacketEnd : '0; 163 | assign rcontrolSM0.rollback = (confIn == 6'b001001) ? spiControl.inPacketErr : '0; 164 | 165 | // TCC_SEND_DATA from SPI_BLOCK_ADDR1 166 | assign rcontrolSM1.open = (confIn == 6'b001010) ? spiControl.inPacketStart : '0; 167 | assign rcontrolSM1.commit = (confIn == 6'b001010) ? spiControl.inPacketEnd : '0; 168 | assign rcontrolSM1.rollback = (confIn == 6'b001010) ? spiControl.inPacketErr : '0; 169 | 170 | always_comb begin 171 | case(confIn) 172 | default: begin 173 | spiControl.outDataSize = '0; 174 | spiControl.outAddr = '0; 175 | spiControl.outCmdCode = TCC_UNKNOWN; 176 | end 177 | 6'b100001: begin // TCC_RECEIVE_DATA from SPI_BLOCK_ADDR0 178 | spiControl.outDataSize = (spiControl.inSize < rcontrolMS0.memUsed) ? spiControl.inSize : rcontrolMS0.memUsed; 179 | spiControl.outAddr = SPI_BLOCK_ADDR0; 180 | spiControl.outCmdCode = spiControl.inCmdCode; 181 | end 182 | 6'b010001: begin // TCC_RECEIVE_STS from SPI_BLOCK_ADDR0 183 | spiControl.outDataSize = statusControl0.statusSize; 184 | spiControl.outAddr = SPI_BLOCK_ADDR0; 185 | spiControl.outCmdCode = spiControl.inCmdCode; 186 | end 187 | 6'b100010: begin // TCC_RECEIVE_DATA from SPI_BLOCK_ADDR1 188 | spiControl.outDataSize = (spiControl.inSize < rcontrolMS1.memUsed) ? spiControl.inSize : rcontrolMS1.memUsed; 189 | spiControl.outAddr = SPI_BLOCK_ADDR1; 190 | spiControl.outCmdCode = spiControl.inCmdCode; 191 | end 192 | 6'b010010: begin // TCC_RECEIVE_STS from SPI_BLOCK_ADDR1 193 | spiControl.outDataSize = statusControl1.statusSize; 194 | spiControl.outAddr = SPI_BLOCK_ADDR1; 195 | spiControl.outCmdCode = spiControl.inCmdCode; 196 | end 197 | endcase 198 | end 199 | 200 | endmodule 201 | 202 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/milTransceiver.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILTRANSCEIVER_INCLUDE 8 | `define MILTRANSCEIVER_INCLUDE 9 | 10 | interface IMilControl(); 11 | logic receiverBusy, transmitterBusy; 12 | logic packetStart, packetEnd; 13 | 14 | modport slave(output receiverBusy, transmitterBusy, packetStart, packetEnd); 15 | modport master(input receiverBusy, transmitterBusy, packetStart, packetEnd); 16 | 17 | endinterface 18 | 19 | module milTransceiver( input bit nRst, clk, 20 | IPushMil.master rpush, 21 | IPushMil.slave tpush, 22 | IMilStd mil, 23 | IMilControl.slave control); 24 | 25 | parameter T2R_DELAY = 12; 26 | 27 | logic ioClk; 28 | logic [3:0] cntr, nextCntr; 29 | 30 | IMilTxControl tcontrol(); 31 | milTransmitter t(nRst, clk, ioClk, tpush, mil, tcontrol); 32 | 33 | IMilRxControl rcontrol(); 34 | milReceiver r(nRst, clk, mil, rpush, rcontrol); 35 | 36 | enum logic[1:0] {RECEIVE, TRANSMIT, WAIT} State, Next; 37 | 38 | ioClkGenerator ioClkGen(nRst, clk, ioClk); 39 | 40 | assign control.receiverBusy = rcontrol.busy; 41 | assign control.transmitterBusy = tcontrol.busy; 42 | 43 | upFront packetStartStrobe(nRst, clk, rcontrol.busy, control.packetStart); 44 | downFront packetEndStrobe(nRst, clk, rcontrol.busy, control.packetEnd); 45 | 46 | logic upIoClk; 47 | upFront upIoClkStrobe(nRst, clk, ioClk, upIoClk); 48 | 49 | always_ff @ (posedge clk) begin 50 | if(!nRst) begin 51 | State <= RECEIVE; 52 | cntr <= 0; 53 | end 54 | else begin 55 | State <= Next; 56 | if(upIoClk) cntr <= nextCntr; 57 | end 58 | end 59 | 60 | always_comb begin 61 | Next = State; 62 | unique case(State) 63 | RECEIVE: if(!rcontrol.busy && tcontrol.request) Next = TRANSMIT; 64 | TRANSMIT: if(!tcontrol.request) Next = WAIT; 65 | WAIT: if(cntr == T2R_DELAY || rcontrol.busy) Next = RECEIVE; 66 | endcase 67 | 68 | unique case(State) 69 | RECEIVE: {rcontrol.grant, tcontrol.grant} = 2'b10; 70 | TRANSMIT: {rcontrol.grant, tcontrol.grant} = 2'b01; 71 | WAIT: {rcontrol.grant, tcontrol.grant} = 2'b10; 72 | endcase 73 | 74 | nextCntr = (State == WAIT) ? (cntr + 1) : 0; 75 | end 76 | 77 | endmodule 78 | 79 | module ioClkGenerator( input bit nRst, clk, 80 | output logic ioClk); 81 | 82 | parameter period = 49; 83 | logic [5:0] cntr, nextCntr; 84 | 85 | assign nextCntr = (cntr == period) ? 0 : (cntr + 1); 86 | 87 | always_ff @ (posedge clk) 88 | if(!nRst) begin 89 | cntr <= '0; 90 | ioClk <= 1'b0; 91 | end 92 | else begin 93 | cntr <= nextCntr; 94 | if(nextCntr == 0) 95 | ioClk = !ioClk; 96 | end 97 | endmodule 98 | 99 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/milTransmitter.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef MILTRANSMITTER_INCLUDE 8 | `define MILTRANSMITTER_INCLUDE 9 | 10 | interface IMilTxControl(); 11 | logic grant, busy, request; 12 | 13 | modport slave(input grant, output busy, request); 14 | modport master(output grant, input busy, request); 15 | 16 | endinterface 17 | 18 | module milTransmitter(input bit nRst, clk, ioClk, 19 | IPushMil.slave push, 20 | IMilStd.tx mil, 21 | IMilTxControl.slave control); 22 | import milStd1553::*; 23 | 24 | logic upIoClk, downIoClk; 25 | upFront up(nRst, clk, ioClk, upIoClk); 26 | downFront down(nRst, clk, ioClk, downIoClk); 27 | 28 | enum logic[3:0] {IDLE, LOAD, DATA, PARITY, POSTFIX1, POSTFIX2, 29 | L01, L02, H11, H12, H01, H02, L11, L12} State, Next; 30 | 31 | logic line; 32 | assign mil.TXout = (State != IDLE) ? line : 1'b0; 33 | assign mil.nTXout = (State != IDLE) ? !line : 1'b0; 34 | assign control.busy = (State != IDLE); 35 | assign push.done = (State == LOAD); 36 | 37 | logic dataInQueue, parityBit; 38 | logic [3:0] cntr, nextCntr; 39 | MilData data; 40 | 41 | assign control.request = dataInQueue || control.busy; 42 | 43 | always_ff @ (posedge clk) begin 44 | if(!nRst) 45 | State <= IDLE; 46 | else 47 | State <= Next; 48 | end 49 | 50 | always_ff @ (posedge clk) begin 51 | if(!nRst) 52 | dataInQueue <= 0; 53 | else begin 54 | if(push.request & !dataInQueue) 55 | dataInQueue <= 1; 56 | if(!push.request && State == LOAD) 57 | dataInQueue <= 0; 58 | end 59 | end 60 | 61 | always_ff @ (posedge clk) begin 62 | unique case(Next) 63 | IDLE: line <= 1'b0; 64 | LOAD: begin data <= push.data; parityBit <= '1; end 65 | L01: line <= 1'b0; 66 | L02: line <= 1'b0; 67 | H11: line <= 1'b1; 68 | H12: line <= 1'b1; 69 | H01: line <= 1'b1; 70 | H02: line <= 1'b1; 71 | L11: line <= 1'b0; 72 | L12: line <= 1'b0; 73 | DATA: begin 74 | if(upIoClk) begin 75 | line <= data.dataWord[nextCntr]; 76 | parityBit <= parityBit ^ data.dataWord[nextCntr]; 77 | end 78 | 79 | if(downIoClk) 80 | line <= !data.dataWord[cntr]; 81 | end 82 | PARITY: begin 83 | if(upIoClk) 84 | line <= parityBit; 85 | if(downIoClk) 86 | line <= !parityBit; 87 | end 88 | POSTFIX1: line <= 1'b0; 89 | POSTFIX2: line <= 1'b0; 90 | endcase 91 | 92 | if(upIoClk) 93 | cntr <= nextCntr; 94 | end 95 | 96 | always_comb begin 97 | nextCntr = (State == DATA) ? cntr - 1 : 15; 98 | 99 | Next = State; 100 | unique case(State) 101 | IDLE: if(dataInQueue && upIoClk && control.grant) Next = LOAD; 102 | LOAD: unique case(data.dataType) 103 | WSERVERR: Next = IDLE; 104 | WDATAERR: Next = IDLE; 105 | WDATA: Next = L01; 106 | WSERV: Next = H01; 107 | endcase 108 | L01: if(downIoClk) Next = L02; 109 | L02: if(downIoClk) Next = H11; 110 | H11: if(upIoClk) Next = H12; 111 | H12: if(upIoClk) Next = DATA; 112 | H01: if(downIoClk) Next = H02; 113 | H02: if(downIoClk) Next = L11; 114 | L11: if(upIoClk) Next = L12; 115 | L12: if(upIoClk) Next = DATA; 116 | DATA: if(upIoClk && nextCntr == 15) Next = PARITY; 117 | PARITY: if(upIoClk) Next = (dataInQueue) ? LOAD : POSTFIX1; 118 | POSTFIX1: if(upIoClk) Next = POSTFIX2; 119 | POSTFIX2: if(downIoClk) Next = IDLE; 120 | endcase 121 | end 122 | 123 | endmodule 124 | 125 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/settings.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef SETTINGS_INCLUDE 8 | `define SETTINGS_INCLUDE 9 | 10 | `define DATAW_SIZE 16 11 | `define DATAC_SIZE 4 12 | `define DATAW_TOP (`DATAW_SIZE - 1) 13 | `define DATAC_TOP (`DATAC_SIZE - 1) 14 | 15 | `define ADDRW_SIZE 8 16 | `define ADDRW_TOP (`ADDRW_SIZE - 1) 17 | 18 | 19 | `endif 20 | -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/signal.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef COMMON_INCLUDE 8 | `define COMMON_INCLUDE 9 | 10 | module signalChange( input bit nRst, 11 | input bit clk, 12 | input bit signal, 13 | output bit strobe); 14 | logic [1:0] buffer; 15 | assign strobe = buffer[1] ^ buffer[0]; 16 | 17 | always_ff @ (posedge clk) 18 | if(!nRst) 19 | buffer <= 0; 20 | else 21 | buffer <= {buffer[0], signal}; 22 | endmodule 23 | 24 | module upFront(input bit nRst, 25 | input bit clk, 26 | input bit signal, 27 | output bit strobe); 28 | 29 | logic [1:0] buffer; 30 | assign strobe = !buffer[1] & buffer[0]; 31 | 32 | always_ff @ (posedge clk) 33 | if(!nRst) 34 | buffer <= 0; 35 | else 36 | buffer <= {buffer[0], signal}; 37 | endmodule 38 | 39 | module downFront( input bit nRst, 40 | input bit clk, 41 | input bit signal, 42 | output bit strobe); 43 | 44 | logic [1:0] buffer; 45 | assign strobe = buffer[1] & !buffer[0]; 46 | 47 | always_ff @ (posedge clk) 48 | if(!nRst) 49 | buffer <= 0; 50 | else 51 | buffer <= {buffer[0], signal}; 52 | endmodule 53 | 54 | module inputFilter( input bit nRst, 55 | input bit clk, 56 | input bit signal, 57 | output bit out); 58 | logic [1:0] buffer; 59 | assign out = buffer[1]; 60 | 61 | always_ff @ (posedge clk) 62 | if(!nRst) 63 | buffer <= 0; 64 | else 65 | buffer <= {buffer[0], signal}; 66 | endmodule 67 | 68 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/spiCore.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `include "settings.sv" 8 | 9 | `ifndef SPI_CORE_INCLUDE 10 | `define SPI_CORE_INCLUDE 11 | 12 | module spiCore(input bit nRst, clk, spiClk, 13 | input logic[`DATAW_TOP:0] tData, 14 | output logic[`DATAW_TOP:0] rData, 15 | input logic nCS, iPin, 16 | output logic tDone, rDone, oPin, tFinish); 17 | 18 | logic[`DATAW_TOP:0] tBuffer, rBuffer; 19 | logic[`DATAC_TOP:0] cntr; 20 | logic clkUp, clkDown; 21 | 22 | enum logic[4:0] { IDLE = 5'b00001, 23 | LOAD = 5'b00010, 24 | TRANSMIT = 5'b00100, 25 | READ = 5'b01000, 26 | SAVE = 5'b10000 } State, Next; 27 | 28 | upFront upStrobe(nRst, clk, spiClk, clkUp); 29 | downFront downStrobe(nRst, clk, spiClk, clkDown); 30 | 31 | assign oPin = (State != IDLE) ? tBuffer[`DATAW_TOP] : 1'bz; 32 | assign tFinish = (clkDown && State == SAVE); 33 | 34 | always_ff @ (posedge clk) 35 | if(!nRst | nCS) 36 | State <= IDLE; 37 | else 38 | State <= Next; 39 | 40 | always_ff @ (posedge clk) begin 41 | unique case(State) 42 | IDLE: begin rBuffer <= 0; {tDone, rDone} <= '0; end 43 | LOAD: begin tBuffer <= tData; cntr <= 0; tDone <= 1; end 44 | READ: if(clkUp) rBuffer <= {rBuffer[(`DATAW_TOP - 1):0], iPin}; 45 | TRANSMIT: if(clkDown) begin tBuffer <= tBuffer << 1; cntr <= cntr + 1'b1; end 46 | SAVE: ; 47 | endcase 48 | 49 | if(State == READ && Next == SAVE) 50 | begin rData <= {rBuffer[(`DATAW_TOP - 1):0], iPin}; rDone <= 1; end 51 | 52 | if({tDone, rDone} != '0) 53 | {tDone, rDone} <= '0; 54 | end 55 | 56 | always_comb begin 57 | Next = State; 58 | unique case(State) 59 | IDLE: if(!nCS) Next = LOAD; 60 | LOAD: Next = READ; 61 | READ: if(clkUp) Next = (cntr == '1) ? SAVE : TRANSMIT; 62 | 63 | TRANSMIT: if(clkDown) Next = READ; 64 | 65 | SAVE: if(clkDown) Next = LOAD; 66 | endcase 67 | end 68 | endmodule 69 | 70 | 71 | module spiMaster( input bit nRst, clk, spiClk, 72 | input logic[`DATAW_TOP:0] tData, input logic requestInsertToTQueue, output logic doneInsertToTQueue, 73 | output logic[`DATAW_TOP:0] rData, output logic requestReceivedToRQueue, input logic doneSavedFromRQueue, 74 | output logic overflowInTQueue, overflowInRQueue, 75 | input logic miso, 76 | output logic mosi, nCS, sck); 77 | 78 | logic _nCS, _wordInTransmitQueue, _wordInReceiveQueue, _transmissionFinished, _doneInsertToTQueue; 79 | logic clkUp; 80 | 81 | logic _miso; 82 | inputFilter iFilter0(nRst, clk, miso, _miso); 83 | 84 | assign nCS = _nCS; 85 | assign sck = (!nCS) ? spiClk : 1'b1; 86 | 87 | assign overflowInTQueue = _wordInTransmitQueue & requestInsertToTQueue; 88 | assign overflowInRQueue = _wordInReceiveQueue & requestReceivedToRQueue; 89 | assign doneInsertToTQueue = (_wordInTransmitQueue) ? _doneInsertToTQueue : 1'b0; 90 | 91 | upFront upStrobe(nRst, clk, spiClk, clkUp); 92 | 93 | always_ff @ (posedge clk) begin 94 | if(!nRst) begin 95 | {_wordInTransmitQueue, _wordInReceiveQueue} <= '0; 96 | _nCS <= 1; 97 | end 98 | else begin 99 | if(requestInsertToTQueue) 100 | _wordInTransmitQueue <= 1'b1; 101 | if(_doneInsertToTQueue & !requestInsertToTQueue) 102 | _wordInTransmitQueue <= 1'b0; 103 | 104 | if(requestReceivedToRQueue) 105 | _wordInReceiveQueue <= 1'b1; 106 | if(doneSavedFromRQueue & !requestReceivedToRQueue) 107 | _wordInReceiveQueue <= 1'b0; 108 | 109 | if((_wordInTransmitQueue | requestInsertToTQueue) & _nCS & clkUp) 110 | _nCS <= 1'b0; 111 | if(_transmissionFinished & !_wordInTransmitQueue) 112 | _nCS <= 1'b1; 113 | end 114 | end 115 | 116 | spiCore spi( .nRst(nRst), .clk(clk), .spiClk(spiClk), 117 | .tData(tData), .rData(rData), .nCS(_nCS), .iPin(_miso), 118 | .tDone(_doneInsertToTQueue), .rDone(requestReceivedToRQueue), 119 | .oPin(mosi), .tFinish(_transmissionFinished)); 120 | endmodule 121 | 122 | module spiSlave (input bit nRst, clk, 123 | input logic[`DATAW_TOP:0] tData, input logic requestInsertToTQueue, output logic doneInsertToTQueue, 124 | output logic[`DATAW_TOP:0] rData, output logic requestReceivedToRQueue, input logic doneSavedFromRQueue, 125 | output logic overflowInTQueue, overflowInRQueue, isBusy, 126 | input logic mosi, 127 | output logic miso, 128 | input logic nCS, sck); 129 | 130 | logic _wordInTransmitQueue, _wordInReceiveQueue, _transmitFinished, _doneInsertToTQueue; 131 | 132 | logic _mosi, _nCS, _sck; 133 | inputFilter iFilter0(nRst, clk, mosi, _mosi); 134 | inputFilter iFilter1(nRst, clk, nCS, _nCS); 135 | inputFilter iFilter2(nRst, clk, sck, _sck); 136 | 137 | logic[`DATAW_TOP:0] _tData; 138 | assign _tData = (_wordInTransmitQueue | requestInsertToTQueue) ? tData : '0; //'1; //'0; 139 | 140 | assign overflowInTQueue = _wordInTransmitQueue & requestInsertToTQueue; 141 | assign overflowInRQueue = _wordInReceiveQueue & requestReceivedToRQueue; 142 | assign doneInsertToTQueue = (_wordInTransmitQueue) ? _doneInsertToTQueue : 1'b0; 143 | assign isBusy = !_nCS; 144 | 145 | always_ff @ (posedge clk) begin 146 | if(!nRst) 147 | {_wordInTransmitQueue, _wordInReceiveQueue} <= '0; 148 | else begin 149 | if(requestInsertToTQueue) 150 | _wordInTransmitQueue <= 1'b1; 151 | if(_doneInsertToTQueue & !requestInsertToTQueue) 152 | _wordInTransmitQueue <= 1'b0; 153 | 154 | if(requestReceivedToRQueue) 155 | _wordInReceiveQueue <= 1'b1; 156 | if(doneSavedFromRQueue & !requestReceivedToRQueue) 157 | _wordInReceiveQueue <= 1'b0; 158 | end 159 | end 160 | 161 | spiCore spi( .nRst(nRst), .clk(clk), .spiClk(_sck), 162 | .tData(_tData), .rData(rData), .nCS(_nCS), .iPin(_mosi), 163 | .tDone(_doneInsertToTQueue), .rDone(requestReceivedToRQueue), 164 | .oPin(miso), .tFinish(_transmitFinished)); 165 | endmodule 166 | 167 | `endif -------------------------------------------------------------------------------- /mil1553-spi/src/mil1553-spi/spiReceiver.sv: -------------------------------------------------------------------------------- 1 | /* MIL-STD-1553 <-> SPI bridge 2 | * Copyright(c) 2016 Stanislav Zhelnio 3 | * Licensed under the MIT license (MIT) 4 | * https://github.com/zhelnio/mil1553-spi 5 | */ 6 | 7 | `ifndef SPI_RECEIVER_INCLUDE 8 | `define SPI_RECEIVER_INCLUDE 9 | 10 | interface ISpiReceiverControl(); 11 | logic overflowInTQueue, overflowInRQueue, isBusy; 12 | 13 | modport master (input overflowInTQueue, overflowInRQueue, isBusy); 14 | modport slave (output overflowInTQueue, overflowInRQueue, isBusy); 15 | endinterface 16 | 17 | 18 | module SpiReceiver(input bit nRst, clk, 19 | IPush.slave transmitBus, 20 | IPush.master receiveBus, 21 | ISpiReceiverControl.slave controlBus, 22 | ISpi.slave spi); 23 | 24 | spiSlave spis(.nRst(nRst), .clk(clk), 25 | .tData(transmitBus.data), .requestInsertToTQueue(transmitBus.request), .doneInsertToTQueue(transmitBus.done), 26 | .rData(receiveBus.data), .requestReceivedToRQueue(receiveBus.request), .doneSavedFromRQueue(receiveBus.done), 27 | .overflowInTQueue(controlBus.overflowInTQueue), .overflowInRQueue(controlBus.overflowInRQueue), .isBusy(controlBus.isBusy), 28 | .mosi(spi.mosi), .miso(spi.miso), .nCS(spi.nCS), .sck(spi.sck)); 29 | endmodule 30 | 31 | `endif -------------------------------------------------------------------------------- /mymil/mil.v: -------------------------------------------------------------------------------- 1 | module mil( 2 | 3 | input iCLK, 4 | input iRESET, 5 | 6 | // MKO interface - channel A 7 | input [1:0]iDA, 8 | output [1:0]oDA, 9 | output oRX_STROB_A, 10 | output oTX_INHIBIT_A, 11 | 12 | 13 | // MKO interface - channel B 14 | input [1:0]iDB, 15 | output [1:0]oDB, 16 | output oRX_STROB_B, 17 | output oTX_INHIBIT_B, 18 | 19 | // RAM device M 20 | input [4:0] iA_RD_M, 21 | input iCLK_RD_M, 22 | output [15:0] oD_RD_M, 23 | output oBUSY_M, 24 | 25 | // RAM device G 26 | input [15:0] iD_WR_G, 27 | input [4:0] iA_WR_G, 28 | input iCLK_WE_G, 29 | input iWE_G, 30 | output oBUSY_G 31 | 32 | ); 33 | 34 | 35 | reg clk25 = 1'b0; 36 | reg [4:0]ena_reg = 5'd0; 37 | 38 | wire [1:0]DO; 39 | wire [1:0]DI = {iDA[1]|iDB[1], iDA[0]|iDB[0]}; 40 | 41 | wire [15:0]RX_DATA; 42 | wire RX_CD; 43 | wire RX_DONE; 44 | wire PARITY_ERROR; 45 | wire [15:0]TX_DATA; 46 | wire TX_CD; 47 | wire TX_EN; 48 | wire TX_BUSY; 49 | 50 | always @(posedge iCLK)begin 51 | clk25 <= !clk25; 52 | end 53 | 54 | always @(posedge clk25 or posedge iRESET)begin 55 | if(iRESET)begin 56 | ena_reg = 5'd0; 57 | end 58 | else begin 59 | ena_reg <= {ena_reg[3:0], TX_BUSY}; 60 | end 61 | end 62 | 63 | mil_control CONTROL( 64 | .iCLK(clk25), 65 | .iRESET(iRESET), 66 | 67 | .iRX_DONE(RX_DONE), 68 | .iRX_DATA(RX_DATA), 69 | .iRX_CD(RX_CD), 70 | .iPARITY_ERROR(PARITY_ERROR), 71 | 72 | .oTX_EN(TX_EN), 73 | .oTX_DATA(TX_DATA), 74 | .oTX_CD(TX_CD), 75 | .iTX_BUSY(TX_BUSY), 76 | 77 | .iA_RD_M(iA_RD_M), 78 | .iCLK_RD_M(iCLK_RD_M), 79 | .oD_RD_M(oD_RD_M), 80 | .oBUSY_M(oBUSY_M), 81 | 82 | .iD_WR_G(iD_WE_G), 83 | .iA_WR_G(iA_WR_G), 84 | .iCLK_WE_G(iCLK_WE_G), 85 | .iWE_G(iWE_G), 86 | .oBUSY_G(oBUSY_G) 87 | ); 88 | 89 | 90 | 91 | mil_transmitter TRANSMITTER( 92 | .iCLK(clk25), 93 | .iRESET(iRESET), 94 | .iCD(TX_CD), 95 | .iEN(TX_EN), 96 | .iDATA(TX_DATA), 97 | .oDO(DO), 98 | .oBUSY(TX_BUSY) 99 | ); 100 | 101 | 102 | mil_receiver RECEIVER( 103 | .iCLK(clk25), 104 | .iRESET(iRESET), 105 | .iDI(DI), 106 | .oDATA(RX_DATA), 107 | .oCD(RX_CD), 108 | .oDONE(RX_DONE), 109 | .oPARITY_ERROR(PARITY_ERROR) 110 | ); 111 | 112 | 113 | assign oDA = DO; 114 | assign oDB = DO; 115 | 116 | assign oRX_STROB_A = ~{|ena_reg}; 117 | assign oTX_INHIBIT_A = ~{|ena_reg}; 118 | assign oRX_STROB_B = ~{|ena_reg}; 119 | assign oTX_INHIBIT_B = ~{|ena_reg}; 120 | 121 | endmodule 122 | -------------------------------------------------------------------------------- /mymil/mil_control.v: -------------------------------------------------------------------------------- 1 | module mil_control( 2 | input iCLK, 3 | input iRESET, 4 | 5 | input iRX_DONE, 6 | input [15:0]iRX_DATA, 7 | input iRX_CD, 8 | input iPARITY_ERROR, 9 | 10 | output oTX_EN, 11 | output [15:0]oTX_DATA, 12 | output oTX_CD, 13 | input iTX_BUSY, 14 | 15 | input [4:0]iA_RD_M, 16 | input iCLK_RD_M, 17 | output [15:0]oD_RD_M, 18 | output oBUSY_M, 19 | 20 | input [15:0] iD_WR_G, 21 | input [4:0] iA_WR_G, 22 | input iCLK_WE_G, 23 | input iWE_G, 24 | output oBUSY_G 25 | 26 | ); 27 | 28 | 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /mymil/mil_receiver.v: -------------------------------------------------------------------------------- 1 | module mil_receiver( 2 | input iCLK, 3 | input iRESET, 4 | input [1:0]iDI, 5 | 6 | output reg [15:0]oDATA, 7 | output reg oCD, 8 | output reg oDONE, 9 | output reg oPARITY_ERROR 10 | 11 | ); 12 | 13 | reg [2:0]pos_shift; 14 | reg [2:0]neg_shift; 15 | reg [2:0]sig_shift; 16 | reg [2:0]length_bit; 17 | reg det_sig; 18 | reg [39:0]manchester; 19 | reg ena_wr; 20 | 21 | wire IN_DATA; 22 | wire RESET_LENGTH_BIT; 23 | wire MIDDLE_BIT = (length_bit == 3'd3); 24 | wire TRUE_DATA_PACKET; 25 | wire [15:0]DATA_BUF; 26 | wire PARITY_BUF; 27 | wire CD_BUF; 28 | 29 | 30 | 31 | always@(posedge iCLK or posedge iRESET)begin 32 | if(iRESET)begin 33 | pos_shift <= 3'd0; 34 | neg_shift <= 3'd0; 35 | end 36 | else begin 37 | pos_shift <= {pos_shift, iDI[1]}; 38 | neg_shift <= {neg_shift, iDI[0]}; 39 | end 40 | end 41 | 42 | 43 | always@(posedge iCLK or posedge iRESET)begin 44 | if(iRESET)begin 45 | det_sig <= 1'b0; 46 | end 47 | else case({pos_shift[2], neg_shift[2]}) 48 | 2'b00:det_sig<=~det_sig; 49 | 2'b01:det_sig<=1'b0; 50 | 2'b10:det_sig<=1'b1; 51 | 2'b11:det_sig<=~det_sig; 52 | endcase 53 | end 54 | 55 | 56 | 57 | always@(posedge iCLK or posedge iRESET)begin 58 | if(iRESET)begin 59 | sig_shift <= 3'd0; 60 | end 61 | else begin 62 | sig_shift[2:0] <= {sig_shift[1:0], det_sig}; 63 | end 64 | end 65 | 66 | always@(posedge iCLK or posedge iRESET)begin 67 | if(iRESET)begin 68 | length_bit<=3'd0; 69 | end 70 | else begin 71 | if(RESET_LENGTH_BIT)begin 72 | length_bit<=3'd0; 73 | end 74 | else begin 75 | length_bit<=length_bit + 3'd1; 76 | end 77 | end 78 | end 79 | 80 | always@(posedge iCLK or posedge iRESET)begin 81 | if(iRESET)begin 82 | manchester<=40'd0; 83 | end 84 | else if(MIDDLE_BIT)begin 85 | manchester[39:0]<={manchester[38:0], IN_DATA}; 86 | end 87 | end 88 | 89 | genvar i; 90 | generate for(i=0; i<=15; i=i+1)begin: bit_a 91 | assign DATA_BUF[i]=manchester[2*i+3]; 92 | end 93 | endgenerate 94 | 95 | 96 | always@(posedge iCLK )begin 97 | oDONE <= TRUE_DATA_PACKET & ena_wr; 98 | end 99 | 100 | always@(posedge iCLK or posedge iRESET)begin 101 | if(iRESET)begin 102 | oDATA <= 16'd0; 103 | oCD <= 1'd0; 104 | ena_wr <= 1'b0; 105 | oPARITY_ERROR <= 1'b0; 106 | end 107 | else begin 108 | ena_wr <= MIDDLE_BIT; 109 | if(TRUE_DATA_PACKET &ena_wr)begin 110 | oCD <= CD_BUF; 111 | oDATA <= DATA_BUF[15:0]; 112 | oPARITY_ERROR <= ~(^({DATA_BUF,PARITY_BUF})); 113 | end 114 | end 115 | end 116 | 117 | assign IN_DATA = sig_shift[2]; 118 | 119 | assign RESET_LEGTH_BIT = sig_shift[2]^sig_shift[1]; 120 | 121 | assign TRUE_DATA_PACKET = ((manchester[39:34]==6'b000111)|(manchester[39:34]==6'b111000)) 122 | &(manchester[33]^manchester[32]&manchester[31]^manchester[30]); 123 | 124 | assign PARITY_BUF = manchester[1]; 125 | assign CD_BUF = manchester[35]; 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /mymil/mil_transmitter.v: -------------------------------------------------------------------------------- 1 | module mil_transmitter( 2 | input iCLK, 3 | input iRESET, 4 | input iCD, 5 | input iEN, 6 | input [15:0]iDATA, 7 | output reg [1:0]oDO, 8 | output reg oBUSY 9 | ); 10 | 11 | reg [15:0] data_buf; 12 | reg cd_buf; 13 | reg [2:0] length_bit; 14 | reg [5:0] count_bit; 15 | 16 | wire [31:0]DATA_MANCHESTER; 17 | wire [39:0]WORD_MANCHESTER; 18 | wire PARITY; 19 | 20 | 21 | 22 | 23 | always@(posedge iCLK or posedge iRESET)begin 24 | if(iRESET)begin 25 | length_bit <= 3'd0; 26 | end 27 | else begin 28 | if(iEN)begin 29 | length_bit <= 3'd0; 30 | end 31 | else begin 32 | length_bit <= length_bit + 3'd1; 33 | end 34 | end 35 | end 36 | 37 | 38 | always@(posedge iCLK or posedge iRESET)begin 39 | if(iRESET)begin 40 | data_buf <= 16'd0; 41 | cd_buf <= 1'b0; 42 | end 43 | else begin 44 | if(iEN)begin 45 | data_buf <= iDATA; 46 | cd_buf <= iCD; 47 | end 48 | end 49 | end 50 | 51 | always@(posedge iCLK or posedge iRESET)begin 52 | if(iRESET)begin 53 | count_bit <= 6'd0; 54 | end 55 | else begin 56 | if(iEN)begin 57 | count_bit <= 6'd39; 58 | end 59 | else if((count_bit != 6'd0)&(length_bit == 3'd7))begin 60 | count_bit <= count_bit-1'b1; 61 | end 62 | end 63 | end 64 | 65 | 66 | always@(posedge iCLK or posedge iRESET)begin 67 | if(iRESET)begin 68 | oBUSY <= 1'b0; 69 | end 70 | else begin 71 | if(iEN)begin 72 | oBUSY <= 1'b1; 73 | end 74 | else if((count_bit != 6'd0)&(length_bit == 3'd7))begin 75 | oBUSY <= 1'b0; 76 | end 77 | end 78 | end 79 | 80 | 81 | always @(posedge iCLK)begin 82 | if(oBUSY)begin 83 | oDO[1] <= DATA_MANCHESTER[count_bit]; 84 | oDO[0] <= ~DATA_MANCHESTER[count_bit]; 85 | end 86 | else begin 87 | oDO[1] <= 1'b0; 88 | oDO[0] <= 1'b0; 89 | end 90 | end 91 | 92 | genvar i; 93 | generate for(i=0; i<16; i=i+1)begin: gen_manchester 94 | assign DATA_MANCHESTER[2*i]= ~data_buf[i]; 95 | assign DATA_MANCHESTER[2*i+1]= data_buf[i]; 96 | end 97 | endgenerate 98 | 99 | 100 | assign WORD_MANCHESTER[39:34] = cd_buf ? 6'b000111:6'b111000; 101 | assign WORD_MANCHESTER[33:2] = DATA_MANCHESTER; 102 | assign WORD_MANCHESTER[1:0] = PARITY ? 2'b10:2'b01; 103 | assign PARITY = ~(^data_buf); 104 | 105 | 106 | endmodule 107 | -------------------------------------------------------------------------------- /mymil/mymil.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2010 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 10.1 Build 153 11/29/2010 SJ Full Version 21 | # Date created = 20:40:28 December 03, 2017 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "10.1" 26 | DATE = "20:40:28 December 03, 2017" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "mymil" 31 | -------------------------------------------------------------------------------- /mymil/mymil.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2010 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 10.1 Build 153 11/29/2010 SJ Full Version 21 | # Date created = 20:40:28 December 03, 2017 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # mymil_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus II software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone IV E" 40 | set_global_assignment -name DEVICE EP4CE22F17C6 41 | set_global_assignment -name TOP_LEVEL_ENTITY mil 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:40:28 DECEMBER 03, 2017" 44 | set_global_assignment -name LAST_QUARTUS_VERSION 10.1 45 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 46 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 47 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 48 | set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V 49 | set_global_assignment -name VERILOG_FILE mil.v 50 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 51 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 52 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 53 | set_global_assignment -name VERILOG_FILE mil_transmitter.v 54 | set_global_assignment -name VERILOG_FILE mil_receiver.v 55 | set_global_assignment -name VERILOG_FILE mil_control.v 56 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top --------------------------------------------------------------------------------