├── .gitignore ├── LICENSE ├── README.md ├── common └── docs │ ├── copyright.tex │ ├── defaulttext.tex │ ├── listingsstyles.tex │ └── preamble.tex ├── release_design_files.py ├── verilog ├── lab1 │ └── doc │ │ ├── figures │ │ ├── figure2.fm │ │ ├── figure2.pdf │ │ ├── figure3.fm │ │ ├── figure3.pdf │ │ ├── figure4.fm │ │ ├── figure4.pdf │ │ ├── figure5.fm │ │ ├── figure5.pdf │ │ ├── figure6.fm │ │ ├── figure6.pdf │ │ ├── figure7.fm │ │ └── figure7.pdf │ │ └── verilog_lab1.tex ├── lab10 │ ├── design_files │ │ ├── DE0-CV │ │ │ ├── part3.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part3.qpf │ │ │ │ ├── part3.qsf │ │ │ │ └── part3.sdc │ │ │ ├── part4.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part4.qpf │ │ │ │ ├── part4.qsf │ │ │ │ └── part4.sdc │ │ │ └── part5.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part5.qpf │ │ │ │ ├── part5.qsf │ │ │ │ └── part5.sdc │ │ ├── DE1-SoC │ │ │ ├── Assembler_sbasm │ │ │ │ ├── README.txt │ │ │ │ └── sbasm.py │ │ │ ├── part3.Verilog │ │ │ │ ├── Simulator │ │ │ │ │ ├── testbench.tcl │ │ │ │ │ ├── testbench.v │ │ │ │ │ └── wave.do │ │ │ │ ├── flipflop.v │ │ │ │ ├── inst_mem.mif │ │ │ │ ├── inst_mem.v │ │ │ │ ├── part3.cdf │ │ │ │ ├── part3.qpf │ │ │ │ ├── part3.qsf │ │ │ │ ├── part3.sdc │ │ │ │ ├── part3.v │ │ │ │ ├── proc.v │ │ │ │ ├── sim │ │ │ │ │ ├── run_compile.bat │ │ │ │ │ ├── run_sim.bat │ │ │ │ │ └── simfpga.vpi │ │ │ │ ├── sw_led.s │ │ │ │ ├── tb │ │ │ │ │ └── tb.v │ │ │ │ └── top.v │ │ │ ├── part4.Verilog │ │ │ │ ├── Simulator │ │ │ │ │ ├── testbench.tcl │ │ │ │ │ ├── testbench.v │ │ │ │ │ └── wave.do │ │ │ │ ├── flipflop.v │ │ │ │ ├── inst_mem.mif │ │ │ │ ├── inst_mem.v │ │ │ │ ├── part4.cdf │ │ │ │ ├── part4.qpf │ │ │ │ ├── part4.qsf │ │ │ │ ├── part4.sdc │ │ │ │ ├── part4.v │ │ │ │ ├── proc.v │ │ │ │ ├── seg7.s │ │ │ │ ├── seg7.v │ │ │ │ ├── sim │ │ │ │ │ ├── run_compile.bat │ │ │ │ │ ├── run_sim.bat │ │ │ │ │ └── simfpga.vpi │ │ │ │ ├── tb │ │ │ │ │ └── tb.v │ │ │ │ └── top.v │ │ │ └── part5.Verilog │ │ │ │ ├── Simulator │ │ │ │ ├── testbench.tcl │ │ │ │ ├── testbench.v │ │ │ │ └── wave.do │ │ │ │ ├── branches.s │ │ │ │ ├── flipflop.v │ │ │ │ ├── inst_mem.mif │ │ │ │ ├── inst_mem.v │ │ │ │ ├── part5.cdf │ │ │ │ ├── part5.qpf │ │ │ │ ├── part5.qsf │ │ │ │ ├── part5.sdc │ │ │ │ ├── part5.v │ │ │ │ ├── proc.v │ │ │ │ ├── scroll.s │ │ │ │ ├── seg7.s │ │ │ │ ├── seg7.v │ │ │ │ ├── sim │ │ │ │ ├── run_compile.bat │ │ │ │ ├── run_sim.bat │ │ │ │ └── simfpga.vpi │ │ │ │ ├── sitbooboosit.s │ │ │ │ ├── sw_led.s │ │ │ │ ├── tb │ │ │ │ └── tb.v │ │ │ │ └── top.v │ │ ├── DE10-Lite │ │ │ ├── part3.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part3.qpf │ │ │ │ └── part3.qsf │ │ │ ├── part4.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part4.qpf │ │ │ │ ├── part4.qsf │ │ │ │ └── part4.sdc │ │ │ └── part5.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part5.qpf │ │ │ │ ├── part5.qsf │ │ │ │ └── part5.sdc │ │ ├── DE10-Standard │ │ │ ├── part3.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part3.cdf │ │ │ │ ├── part3.qpf │ │ │ │ ├── part3.qsf │ │ │ │ └── part3.sdc │ │ │ ├── part4.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part4.cdf │ │ │ │ ├── part4.qpf │ │ │ │ ├── part4.qsf │ │ │ │ └── part4.sdc │ │ │ └── part5.Verilog │ │ │ │ ├── Readme.txt │ │ │ │ ├── part5.cdf │ │ │ │ ├── part5.qpf │ │ │ │ ├── part5.qsf │ │ │ │ └── part5.sdc │ │ └── DE2-115 │ │ │ ├── part3.Verilog │ │ │ ├── Readme.txt │ │ │ ├── part3.qpf │ │ │ ├── part3.qsf │ │ │ └── part3.sdc │ │ │ ├── part4.Verilog │ │ │ ├── Readme.txt │ │ │ ├── part4.qpf │ │ │ ├── part4.qsf │ │ │ └── part4.sdc │ │ │ └── part5.Verilog │ │ │ ├── Readme.txt │ │ │ ├── part5.qpf │ │ │ ├── part5.qsf │ │ │ └── part5.sdc │ └── doc │ │ ├── figures │ │ ├── figure12_F.pdf │ │ ├── figure12_F.svg │ │ ├── figure13.pdf │ │ ├── figure13.svg │ │ ├── figure14.pdf │ │ ├── part3.png │ │ └── part5.png │ │ └── verilog_lab10.tex ├── lab11 │ ├── design_files │ │ ├── barrel │ │ │ ├── Simulator │ │ │ │ ├── testbench.tcl │ │ │ │ ├── testbench.v │ │ │ │ └── wave.do │ │ │ └── barrel.v │ │ ├── figure_26.s │ │ ├── figure_28.s │ │ ├── part8 │ │ │ ├── Readme.txt │ │ │ ├── Simulator │ │ │ │ ├── testbench.tcl │ │ │ │ ├── testbench.v │ │ │ │ └── wave.do │ │ │ ├── flipflop.v │ │ │ ├── inst_mem.v │ │ │ ├── part8.qpf │ │ │ ├── part8.qsf │ │ │ ├── part8.sdc │ │ │ ├── part8.v │ │ │ ├── proc.v │ │ │ ├── seg7.v │ │ │ ├── sim │ │ │ │ ├── run_compile.bat │ │ │ │ ├── run_sim.bat │ │ │ │ └── simfpga.vpi │ │ │ ├── tb │ │ │ │ └── tb.v │ │ │ └── top.v │ │ └── shift_test.s │ └── doc │ │ ├── figures │ │ ├── bl_pop.png │ │ ├── part3.png │ │ ├── part5.png │ │ ├── push_bl.png │ │ ├── r6.pdf │ │ ├── r6.svg │ │ ├── shift_a.png │ │ └── shift_b.png │ │ └── verilog_lab11.tex ├── lab2 │ └── doc │ │ ├── figures │ │ ├── figure1.fm │ │ ├── figure1.pdf │ │ ├── figure2.fm │ │ └── figure2.pdf │ │ └── verilog_lab2.tex ├── lab3 │ ├── design_files │ │ ├── part1 │ │ │ └── testbench.v │ │ └── part4 │ │ │ └── testbench.v │ └── doc │ │ ├── figures │ │ ├── D_latch.fm │ │ ├── D_latch.pdf │ │ ├── RS_latch.fm │ │ ├── RS_latch.pdf │ │ ├── figure3.fm │ │ ├── figure3.pdf │ │ ├── figure5.fm │ │ ├── figure5.pdf │ │ ├── figure6.fm │ │ ├── figure6.pdf │ │ └── simulation.pdf │ │ └── verilog_lab3.tex ├── lab4 │ └── doc │ │ ├── figures │ │ ├── figure1.fm │ │ ├── figure1.pdf │ │ ├── figure_hint.fm │ │ └── figure_hint.pdf │ │ └── verilog_lab4.tex ├── lab5 │ └── doc │ │ ├── figures │ │ ├── fig_morse_code_circuit_schematic.fm │ │ └── fig_morse_code_circuit_schematic.pdf │ │ └── verilog_lab5.tex ├── lab6 │ └── doc │ │ ├── figures │ │ ├── accumulator.pdf │ │ ├── adder_tree.fm │ │ ├── adder_tree.pdf │ │ ├── array_mult_adders.fm │ │ ├── array_mult_adders.pdf │ │ ├── figure1.fm │ │ ├── figure3.fm │ │ ├── figure3.pdf │ │ ├── figure4.fm │ │ ├── figure4.pdf │ │ ├── registered_adder.pdf │ │ ├── registered_mult.fm │ │ ├── registered_mult.pdf │ │ └── ripple_carry.pdf │ │ └── verilog_lab6.tex ├── lab7 │ └── doc │ │ ├── figures │ │ ├── fig_morse_code_circuit_schematic.fm │ │ ├── fig_morse_code_circuit_schematic.pdf │ │ ├── figure1.fm │ │ ├── figure1.pdf │ │ ├── figure2.fm │ │ ├── figure2.pdf │ │ └── figure4.png │ │ └── verilog_lab7.tex ├── lab8 │ ├── design_files │ │ └── testbench.v │ └── doc │ │ ├── figures │ │ ├── figure1.fm │ │ ├── figure1.pdf │ │ ├── figure2.png │ │ ├── figure3.png │ │ ├── figure4.fm │ │ ├── figure4.pdf │ │ ├── figure4.png │ │ ├── figure5.png │ │ ├── figure6.png │ │ └── simulation.png │ │ └── verilog_lab8.tex └── lab9 │ ├── design_files │ ├── DE0-CV │ │ ├── part1.Verilog │ │ │ └── Readme.txt │ │ └── part2.Verilog │ │ │ ├── Readme.txt │ │ │ ├── part2.qpf │ │ │ └── part2.qsf │ ├── DE1-SoC │ │ ├── part1.Verilog │ │ │ ├── Simulator │ │ │ │ ├── testbench.tcl │ │ │ │ ├── testbench.v │ │ │ │ └── wave.do │ │ │ └── proc.v │ │ └── part2.Verilog │ │ │ ├── Simulator │ │ │ ├── testbench.tcl │ │ │ ├── testbench.v │ │ │ └── wave.do │ │ │ ├── inst_mem.mif │ │ │ ├── inst_mem.v │ │ │ ├── part2.cdf │ │ │ ├── part2.qpf │ │ │ ├── part2.qsf │ │ │ ├── part2.sdc │ │ │ ├── part2.v │ │ │ ├── proc.v │ │ │ ├── sim │ │ │ ├── run_compile.bat │ │ │ ├── run_sim.bat │ │ │ └── simfpga.vpi │ │ │ ├── tb │ │ │ └── tb.v │ │ │ └── top.v │ ├── DE10-Lite │ │ ├── part1.Verilog │ │ │ └── Readme.txt │ │ └── part2.Verilog │ │ │ ├── Readme.txt │ │ │ ├── part2.qpf │ │ │ └── part2.qsf │ ├── DE10-Standard │ │ ├── part1.Verilog │ │ │ └── Readme.txt │ │ └── part2.Verilog │ │ │ ├── Readme.txt │ │ │ ├── part2.cdf │ │ │ ├── part2.qpf │ │ │ └── part2.qsf │ └── DE2-115 │ │ ├── part1.Verilog │ │ └── Readme.txt │ │ └── part2.Verilog │ │ ├── Readme.txt │ │ ├── part2.qpf │ │ └── part2.qsf │ └── doc │ ├── figures │ ├── figure1.pdf │ ├── figure1.svg │ ├── figure3.png │ ├── figure4.pdf │ ├── figure7.png │ ├── figure8.png │ ├── figure9.png │ ├── figure_ROM.pdf │ └── figuresim2.png │ └── verilog_lab9.tex └── vhdl ├── lab1 └── doc │ ├── figures │ ├── figure2.fm │ ├── figure2.pdf │ ├── figure3.fm │ ├── figure3.pdf │ ├── figure4.fm │ ├── figure4.pdf │ ├── figure5.fm │ ├── figure5.pdf │ ├── figure6.fm │ ├── figure6.pdf │ ├── figure7.fm │ └── figure7.pdf │ └── vhdl_lab1.tex ├── lab10 ├── design_files │ ├── DE0-CV │ │ ├── part3.VHDL │ │ │ ├── Readme.txt │ │ │ ├── part3.qpf │ │ │ ├── part3.qsf │ │ │ └── part3.sdc │ │ ├── part4.VHDL │ │ │ ├── Readme.txt │ │ │ ├── part4.qpf │ │ │ ├── part4.qsf │ │ │ └── part4.sdc │ │ └── part5.VHDL │ │ │ ├── Readme.txt │ │ │ ├── part5.qpf │ │ │ ├── part5.qsf │ │ │ └── part5.sdc │ ├── DE1-SoC │ │ ├── Assembler_sbasm │ │ │ ├── README.txt │ │ │ └── sbasm.py │ │ ├── part3.VHDL │ │ │ ├── Simulator │ │ │ │ ├── testbench.tcl │ │ │ │ ├── testbench.vht │ │ │ │ └── wave.do │ │ │ ├── flipflop.vhd │ │ │ ├── inst_mem.mif │ │ │ ├── inst_mem.vhd │ │ │ ├── part3.cdf │ │ │ ├── part3.qpf │ │ │ ├── part3.qsf │ │ │ ├── part3.sdc │ │ │ ├── part3.vhd │ │ │ ├── proc.vhd │ │ │ ├── sim │ │ │ │ ├── run_compile.bat │ │ │ │ ├── run_sim.bat │ │ │ │ └── simfpga.vpi │ │ │ ├── sw_led.s │ │ │ ├── tb │ │ │ │ └── tb.v │ │ │ └── top.vhd │ │ ├── part4.VHDL │ │ │ ├── Simulator │ │ │ │ ├── testbench.tcl │ │ │ │ ├── testbench.vht │ │ │ │ └── wave.do │ │ │ ├── flipflop.vhd │ │ │ ├── inst_mem.mif │ │ │ ├── inst_mem.vhd │ │ │ ├── part4.cdf │ │ │ ├── part4.qpf │ │ │ ├── part4.qsf │ │ │ ├── part4.sdc │ │ │ ├── part4.vhd │ │ │ ├── proc.vhd │ │ │ ├── seg7.s │ │ │ ├── seg7.vhd │ │ │ ├── sim │ │ │ │ ├── run_compile.bat │ │ │ │ ├── run_sim.bat │ │ │ │ └── simfpga.vpi │ │ │ ├── tb │ │ │ │ └── tb.v │ │ │ └── top.vhd │ │ └── part5.VHDL │ │ │ ├── Simulator │ │ │ ├── testbench.tcl │ │ │ ├── testbench.vht │ │ │ └── wave.do │ │ │ ├── branches.s │ │ │ ├── flipflop.vhd │ │ │ ├── inst_mem.mif │ │ │ ├── inst_mem.vhd │ │ │ ├── part5.cdf │ │ │ ├── part5.qpf │ │ │ ├── part5.qsf │ │ │ ├── part5.sdc │ │ │ ├── part5.vhd │ │ │ ├── proc.vhd │ │ │ ├── scroll.s │ │ │ ├── seg7.s │ │ │ ├── seg7.vhd │ │ │ ├── sim │ │ │ ├── run_compile.bat │ │ │ ├── run_sim.bat │ │ │ └── simfpga.vpi │ │ │ ├── sitbooboosit.s │ │ │ ├── sw_led.s │ │ │ ├── tb │ │ │ └── tb.v │ │ │ └── top.vhd │ ├── DE10-Lite │ │ ├── part3.VHDL │ │ │ ├── part3.qpf │ │ │ ├── part3.qsf │ │ │ └── part3.sdc │ │ ├── part4.VHDL │ │ │ ├── Readme.txt │ │ │ ├── part4.qpf │ │ │ ├── part4.qsf │ │ │ └── part4.sdc │ │ └── part5.VHDL │ │ │ ├── Readme.txt │ │ │ ├── part5.qpf │ │ │ ├── part5.qsf │ │ │ └── part5.sdc │ ├── DE10-Standard │ │ ├── part3.VHDL │ │ │ ├── part3.cdf │ │ │ ├── part3.qpf │ │ │ ├── part3.qsf │ │ │ └── part3.sdc │ │ ├── part4.VHDL │ │ │ ├── Readme.txt │ │ │ ├── part4.cdf │ │ │ ├── part4.qpf │ │ │ ├── part4.qsf │ │ │ └── part4.sdc │ │ └── part5.VHDL │ │ │ ├── Readme.txt │ │ │ ├── part5.cdf │ │ │ ├── part5.qpf │ │ │ ├── part5.qsf │ │ │ └── part5.sdc │ └── DE2-115 │ │ ├── part3.VHDL │ │ ├── Readme.txt │ │ ├── part3.qpf │ │ ├── part3.qsf │ │ └── part3.sdc │ │ ├── part4.VHDL │ │ ├── Readme.txt │ │ ├── part4.qpf │ │ ├── part4.qsf │ │ └── part4.sdc │ │ └── part5.VHDL │ │ ├── Readme.txt │ │ ├── part5.qpf │ │ ├── part5.qsf │ │ └── part5.sdc └── doc │ ├── figures │ ├── figure12_F.pdf │ ├── figure12_F.svg │ ├── figure13.pdf │ ├── figure13.svg │ ├── figure14.pdf │ ├── part3.png │ └── part5.png │ └── vhdl_lab10.tex ├── lab11 ├── design_files │ ├── barrel │ │ ├── Simulator │ │ │ ├── testbench.tcl │ │ │ ├── testbench.vht │ │ │ └── wave.do │ │ ├── barrel.v │ │ └── top.vhd │ ├── figure_26.s │ ├── figure_28.s │ ├── part8 │ │ ├── Readme.txt │ │ ├── Simulator │ │ │ ├── testbench.tcl │ │ │ ├── testbench.vht │ │ │ └── wave.do │ │ ├── flipflop.vhd │ │ ├── inst_mem.vhd │ │ ├── part8.qpf │ │ ├── part8.qsf │ │ ├── part8.sdc │ │ ├── part8.vhd │ │ ├── proc.vhd │ │ ├── regn.vhd │ │ ├── seg7.vhd │ │ ├── sim │ │ │ ├── run_compile.bat │ │ │ ├── run_sim.bat │ │ │ └── simfpga.vpi │ │ ├── tb │ │ │ └── tb.v │ │ └── top.vhd │ └── shift_test.s └── doc │ ├── figures │ ├── bl_pop.png │ ├── part3.png │ ├── part5.png │ ├── push_bl.png │ ├── r6.pdf │ ├── r6.svg │ ├── shift_a.png │ └── shift_b.png │ └── vhdl_lab11.tex ├── lab2 └── doc │ ├── figures │ ├── figure1.fm │ ├── figure1.pdf │ ├── figure2.fm │ └── figure2.pdf │ └── vhdl_lab2.tex ├── lab3 ├── design_files │ ├── part1 │ │ └── testbench.vhd │ └── part4 │ │ └── testbench.vhd └── doc │ ├── figures │ ├── D_latch.fm │ ├── D_latch.pdf │ ├── RS_latch.fm │ ├── RS_latch.pdf │ ├── figure3.fm │ ├── figure3.pdf │ ├── figure5.fm │ ├── figure5.pdf │ ├── figure6.fm │ ├── figure6.pdf │ └── simulation.pdf │ └── vhdl_lab3.tex ├── lab4 └── doc │ ├── figures │ ├── figure1.fm │ ├── figure1.pdf │ ├── figure_hint.fm │ └── figure_hint.pdf │ └── vhdl_lab4.tex ├── lab5 └── doc │ ├── figures │ ├── fig_morse_code_circuit_schematic.fm │ └── fig_morse_code_circuit_schematic.pdf │ └── vhdl_lab5.tex ├── lab6 └── doc │ ├── figures │ ├── accumulator.pdf │ ├── adder_tree.fm │ ├── adder_tree.pdf │ ├── array_mult_adders.fm │ ├── array_mult_adders.pdf │ ├── figure1.fm │ ├── figure3.fm │ ├── figure3.pdf │ ├── figure4.fm │ ├── figure4.pdf │ ├── registered_adder.pdf │ ├── registered_mult.fm │ ├── registered_mult.pdf │ └── ripple_carry.pdf │ └── vhdl_lab6.tex ├── lab7 └── doc │ ├── figures │ ├── fig_morse_code_circuit_schematic.fm │ ├── fig_morse_code_circuit_schematic.pdf │ ├── figure1.fm │ ├── figure1.pdf │ ├── figure2.fm │ ├── figure2.pdf │ └── figure4.png │ └── vhdl_lab7.tex ├── lab8 ├── design_files │ └── testbench.vhd └── doc │ ├── figures │ ├── figure1.fm │ ├── figure1.pdf │ ├── figure2.png │ ├── figure3.png │ ├── figure4.fm │ ├── figure4.pdf │ ├── figure4.png │ ├── figure5.png │ ├── figure6.png │ └── simulation.png │ └── vhdl_lab8.tex └── lab9 ├── design_files ├── DE0-CV │ ├── part1.VHDL │ │ └── Readme.txt │ └── part2.VHDL │ │ ├── Readme.txt │ │ ├── part2.qpf │ │ └── part2.qsf ├── DE1-SoC │ ├── part1.VHDL │ │ ├── Simulator │ │ │ ├── testbench.tcl │ │ │ ├── testbench.vht │ │ │ └── wave.do │ │ └── proc.vhd │ └── part2.VHDL │ │ ├── Simulator │ │ ├── testbench.tcl │ │ ├── testbench.vht │ │ └── wave.do │ │ ├── inst_mem.mif │ │ ├── inst_mem.vhd │ │ ├── part2.qpf │ │ ├── part2.qsf │ │ ├── part2.sdc │ │ ├── part2.vhd │ │ ├── proc.vhd │ │ ├── sim │ │ ├── run_compile.bat │ │ ├── run_sim.bat │ │ └── simfpga.vpi │ │ ├── tb │ │ └── tb.v │ │ └── top.vhd ├── DE10-Lite │ ├── part1.VHDL │ │ └── Readme.txt │ └── part2.VHDL │ │ ├── Readme.txt │ │ ├── part2.qpf │ │ └── part2.qsf ├── DE10-Standard │ ├── part1.VHDL │ │ └── Readme.txt │ └── part2.VHDL │ │ ├── Readme.txt │ │ ├── part2.cdf │ │ ├── part2.qpf │ │ └── part2.qsf └── DE2-115 │ ├── part1.VHDL │ └── Readme.txt │ └── part2.VHDL │ ├── Readme.txt │ ├── part2.qpf │ └── part2.qsf └── doc ├── figures ├── figure1.pdf ├── figure1.svg ├── figure3.png ├── figure4.pdf ├── figure7.png ├── figure8.png ├── figure9.png ├── figure_ROM.pdf └── figuresim2.png └── vhdl_lab9.tex /.gitignore: -------------------------------------------------------------------------------- 1 | # Releases directory 2 | release/ 3 | 4 | # iv Files 5 | *.swp 6 | 7 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 FPGAcademy.org 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Digital Logic Laboratory Exercises 2 | 3 | These laboratory exercises begin with fundamental concepts and perform simple operations on the DE-series boards, like using 4 | switches and controlling LEDs and seven-segment displays. These exercises assume that students are just beginning to learn 5 | about digital logic concepts. Subsequent exercises progress to more advanced topics such as arithmetic circuits, flip-flops, 6 | counters, state machines, memories, data paths, and simple processors. Instructors of courses may choose to adopt the entire 7 | sequence of exercises, only selected exercises, or just parts of some exercises. We have tried to make the material as 8 | modular as possible so that instructors can combine these exercises with their own teaching materials. 9 | 10 | Each exercise consists of multiple parts. In most cases the solution required for the early parts can be reused in a modular 11 | fashion in later parts. Also, the solutions produced for early exercises are often reusable for parts of more advanced 12 | exercises. Our basic approach is to encourage students to develop their circuits in small increments and to build larger 13 | circuits in a modular, hierarchical fashion. 14 | -------------------------------------------------------------------------------- /common/docs/copyright.tex: -------------------------------------------------------------------------------- 1 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2 | %%% FPGAcademy Copyright Information %%% 3 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 4 | 5 | %Always put the copyright on a new page (clear page), with some vertical space from top 6 | \clearpage 7 | \vspace{1in} 8 | 9 | \noindent 10 | 11 | Copyright {\copyright} FPGAcademy.org. All rights reserved. FPGAcademy and the 12 | FPGAcademy logo are trademarks of FPGAcademy.org. This document is provided 13 | "as is", without warranty of any kind, express or implied, including but not 14 | limited to the warranties of merchantability, fitness for a particular purpose 15 | and noninfringement. In no event shall the authors or copyright holders be 16 | liable for any claim, damages or other liability, whether in an action of 17 | contract, tort or otherwise, arising from, out of or in connection with the 18 | document or the use or other dealings in the document. 19 | ~\\ 20 | ~\\ 21 | **Other names and brands may be claimed as the property of others. 22 | 23 | -------------------------------------------------------------------------------- /common/docs/defaulttext.tex: -------------------------------------------------------------------------------- 1 | \newcommand{\UPDatePublished}{Oct 2021} 2 | \newcommand{\versnum}{21.1} %version number quartus/AMP 3 | \newcommand{\quartusname}{Quartus\textsuperscript{\textregistered} Prime} 4 | \newcommand{\UPTextBar}{For \quartusname{} \versnum{}} 5 | \newcommand{\thisyear}{2021 } %for copyright 6 | \newcommand{\company}{FPGAcademy.org} 7 | \newcommand{\longteamname}{FPGAcademy.org} 8 | \newcommand{\teamname}{FPGAcademy} 9 | \newcommand{\website}{FPGAcademy.org} 10 | 11 | \newcommand{\productAcronym}{AMP} 12 | \newcommand{\productNameShort}{Monitor Program} 13 | 14 | \newcommand{\productNameMedTM}{A Monitor Program} 15 | \newcommand{\productNameMed}{A Monitor Program} 16 | 17 | %\newcommand{\headerLogoFilePath}[1]{#1/FPGAcademy.png} 18 | -------------------------------------------------------------------------------- /common/docs/preamble.tex: -------------------------------------------------------------------------------- 1 | \addtolength{\textwidth}{1.5in} 2 | \addtolength{\oddsidemargin}{-0.75in} 3 | \addtolength{\topmargin}{-0.75in} 4 | \addtolength{\textheight}{1.5in} 5 | \addtolength{\evensidemargin}{0.75in} 6 | \setlength\parindent{0pt} 7 | \raggedbottom 8 | 9 | \usepackage{ae,aecompl} 10 | \usepackage{epsfig,float,times} 11 | \usepackage[hypcap]{caption} 12 | \usepackage[pdftex, colorlinks]{hyperref} 13 | \usepackage{graphicx} 14 | \usepackage[usenames, dvipsnames]{color} 15 | \usepackage{rotating} 16 | \usepackage{tikz} 17 | \usetikzlibrary{automata,positioning} 18 | \usepackage{placeins} 19 | 20 | \widowpenalty 10000 21 | \clubpenalty 10000 22 | 23 | \newcommand{\red}[1]{{\color{red}\sf{#1}}} 24 | \newcommand{\green}[1]{{\color{green}\sf{#1}}} 25 | \newcommand{\blue}[1]{{\color{blue}\sf{#1}}} 26 | \definecolor{PineGreen}{rgb}{0.0, 0.47, 0.44} 27 | \definecolor{ForestGreen}{rgb}{0.13, 0.55, 0.13} 28 | \definecolor{Brown}{rgb}{0.59, 0.29, 0.0} 29 | 30 | \input{\CommonDocsPath/defaulttext.tex} 31 | \input{\CommonDocsPath/listingsstyles.tex} 32 | 33 | \hypersetup{ 34 | pdftitle={Digital Logic Lab Exercise \LabNum}, 35 | linkcolor=blue, 36 | hyperindex=true, 37 | pdfauthor={FPGAcademy.org}, 38 | pdfkeywords={FPGAcademy.org, FPGAcademy, Lab, Exercise, Digital Logic}, 39 | bookmarks, 40 | bookmarksopen=false, 41 | filecolor=blue, 42 | pdfstartview={FitH}, 43 | urlcolor=blue, 44 | plainpages=false, 45 | pdfpagelabels=true, 46 | linkbordercolor={1 1 1} %no color for link border 47 | } 48 | 49 | -------------------------------------------------------------------------------- /release_design_files.py: -------------------------------------------------------------------------------- 1 | # Zip the design files folder and put them in the release folder 2 | 3 | import os, shutil 4 | 5 | release_path = './release/' 6 | versions = [['./verilog/', 'verilog_'], ['./vhdl/', 'vhdl_']] 7 | 8 | for version in versions: 9 | labs = os.listdir(version[0]) 10 | for lab in labs: 11 | design_files_path = version[0] + lab + '/design_files' 12 | if (os.path.isdir(design_files_path)): 13 | output_zip_filename = release_path + version[1] + lab + '_design_files' 14 | shutil.make_archive(output_zip_filename, 'zip', design_files_path); 15 | 16 | -------------------------------------------------------------------------------- /verilog/lab1/doc/figures/figure2.fm: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab1/doc/figures/figure7.pdf -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE0-CV/part3.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE0-CV/part3.Verilog/part3.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE0-CV/part4.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE0-CV/part4.Verilog/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE0-CV/part5.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE0-CV/part5.Verilog/part5.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part5" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | # in case Quartus generated an "empty black box" file for the memory, delete it 10 | if {[file exists ../inst_mem_bb.v]} { 11 | file delete ../inst_mem_bb.v 12 | } 13 | 14 | if {[file exists work]} { 15 | file delete -force work 16 | } 17 | 18 | # create the default "work" library 19 | vlib work; 20 | 21 | # compile the Verilog source code in the parent folder 22 | vlog -nolock ../*.v 23 | # compile the Verilog code of the testbench 24 | vlog -nolock *.v 25 | # start the Simulator 26 | vsim work.testbench -Lf 220model -Lf altera_mf_ver -Lf verilog 27 | # show waveforms specified in wave.do 28 | do wave.do 29 | 30 | # advance the simulation the desired amount of time 31 | run 1500 ns 32 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/Simulator/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module testbench ( ); 4 | 5 | parameter CLOCK_PERIOD = 20; 6 | 7 | reg [9:0] SW; 8 | wire [0:0] KEY; 9 | wire [9:0] LEDR; 10 | 11 | reg CLOCK_50; 12 | initial begin 13 | CLOCK_50 <= 1'b0; 14 | end // initial 15 | always @ (*) 16 | begin : Clock_Generator 17 | #((CLOCK_PERIOD) / 2) CLOCK_50 <= ~CLOCK_50; 18 | end 19 | 20 | reg Resetn; 21 | initial begin 22 | Resetn <= 1'b0; 23 | #20 Resetn <= 1'b1; 24 | end // initial 25 | 26 | initial begin 27 | SW <= 10'h0; 28 | #20 SW <= 10'b1010101010; 29 | #560 SW <= 10'b1101010101; 30 | end // initial 31 | 32 | assign KEY[0] = Resetn; 33 | part3 U1 (KEY, SW, CLOCK_50, LEDR); 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/flipflop.v: -------------------------------------------------------------------------------- 1 | module flipflop (D, Resetn, Clock, Q); 2 | input D, Resetn, Clock; 3 | output Q; 4 | reg Q; 5 | 6 | always @(posedge Clock) 7 | if (Resetn == 0) 8 | Q <= 1'b0; 9 | else 10 | Q <= D; 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/inst_mem.mif: -------------------------------------------------------------------------------- 1 | WIDTH = 16; 2 | DEPTH = 256; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = HEX; 5 | 6 | CONTENT 7 | BEGIN 8 | 0 : 3610; % mvt r3, #0x1000 % 9 | 1 : 3830; % mvt r4, #0x3000 % 10 | 2 : 8004; % ld r0, [r4] % 11 | 3 : a003; % st r0, [r3] % 12 | 4 : 1e02; % mv r7, #0x0002 % 13 | END; 14 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/part3.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CSEMA5F31) Path("C:/Users/profb/Dropbox/UofT/Courses/ece243_19/Labs/Lab2/solutions/DE1-SoC/part3.Verilog/") File("part3.sof") MfrSpec(OpMask(1)); 8 | P ActionCode(Ign) 9 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/part3.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part3" 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/part3.v: -------------------------------------------------------------------------------- 1 | // Reset with KEY[0]. SW[9] is Run. 2 | // The processor executes the instructions in the file inst_mem.mif 3 | module part3 (KEY, SW, CLOCK_50, LEDR); 4 | input [0:0] KEY; 5 | input [9:0] SW; 6 | input CLOCK_50; 7 | output [9:0] LEDR; 8 | 9 | wire [15:0] DOUT, ADDR; 10 | reg [15:0] DIN; 11 | wire W, Sync, Run; 12 | wire inst_mem_cs, SW_cs, LED_reg_cs; 13 | wire [15:0] inst_mem_q; 14 | wire [8:0] LED_reg, SW_reg; // LED[9] and SW[9] are used for Run 15 | 16 | // synchronize the Run input 17 | flipflop U1 (SW[9], KEY[0], CLOCK_50, Sync); 18 | flipflop U2 (Sync, KEY[0], CLOCK_50, Run); 19 | 20 | // module proc(DIN, Resetn, Clock, Run, DOUT, ADDR, W); 21 | proc U3 (DIN, KEY[0], CLOCK_50, Run, DOUT, ADDR, W); 22 | 23 | assign inst_mem_cs = (ADDR[15:12] == 4'h0); 24 | assign LED_reg_cs = (ADDR[15:12] == 4'h1); 25 | assign SW_cs = (ADDR[15:12] == 4'h3); 26 | // module inst_mem (address, clock, data, wren, q); 27 | inst_mem U4 (ADDR[7:0], CLOCK_50, DOUT, inst_mem_cs & W, inst_mem_q); 28 | 29 | always @ (*) 30 | if (inst_mem_cs == 1'b1) 31 | DIN = inst_mem_q; 32 | else if (SW_cs == 1'b1) 33 | DIN = {7'b0000000, SW_reg}; 34 | else 35 | DIN = 16'bxxxxxxxxxxxxxxxx; 36 | 37 | // module regn(R, Rin, Clock, Q); 38 | regn #(.n(9)) U5 (DOUT[8:0], KEY[0], LED_reg_cs & W, CLOCK_50, LED_reg); 39 | assign LEDR[8:0] = LED_reg; 40 | assign LEDR[9] = Run; 41 | 42 | // module regn(R, Rin, Clock, Q); 43 | regn #(.n(9)) U6 (SW[8:0], KEY[0], 1'b1, CLOCK_50, SW_reg); // SW[9] is used for Run 44 | 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work rmdir /S /Q work 8 | 9 | vlib work 10 | vlog -nolock ../tb/*.v 11 | if exist ../*.v ( 12 | vlog -nolock ../*.v 13 | ) 14 | if exist ../*.sv ( 15 | vlog -nolock ../*.sv 16 | ) 17 | if exist ../*.vhd ( 18 | vcom -nolock ../*.vhd 19 | ) 20 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | ) 10 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab10/design_files/DE1-SoC/part3.Verilog/sim/simfpga.vpi -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/sw_led.s: -------------------------------------------------------------------------------- 1 | .define LED_ADDRESS 0x10 2 | .define SW_ADDRESS 0x30 3 | 4 | // Read SW switches and display on LEDs 5 | mvt r3, #LED_ADDRESS // point to LED port 6 | mvt r4, #SW_ADDRESS // point to SW port 7 | MAIN: ld r0, [r4] // read SW values 8 | st r0, [r3] // light up LEDs 9 | mv pc, #MAIN 10 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part3.Verilog/top.v: -------------------------------------------------------------------------------- 1 | module top (CLOCK_50, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); 2 | 3 | input CLOCK_50; // DE-series 50 MHz clock signal 4 | input wire [9:0] SW; // DE-series switches 5 | input wire [3:0] KEY; // DE-series pushbuttons 6 | 7 | output wire [6:0] HEX0; // DE-series HEX displays 8 | output wire [6:0] HEX1; 9 | output wire [6:0] HEX2; 10 | output wire [6:0] HEX3; 11 | output wire [6:0] HEX4; 12 | output wire [6:0] HEX5; 13 | 14 | output wire [9:0] LEDR; // DE-series LEDs 15 | 16 | part3 U1 (KEY[0], SW, CLOCK_50, LEDR); 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | # in case Quartus generated an "empty black box" file for the memory, delete it 10 | if {[file exists ../inst_mem_bb.v]} { 11 | file delete ../inst_mem_bb.v 12 | } 13 | 14 | if {[file exists work]} { 15 | file delete -force work 16 | } 17 | 18 | # create the default "work" library 19 | vlib work; 20 | 21 | # compile the Verilog source code in the parent folder 22 | vlog -nolock ../*.v 23 | # compile the Verilog code of the testbench 24 | vlog -nolock *.v 25 | # start the Simulator 26 | vsim work.testbench -Lf 220model -Lf altera_mf_ver -Lf verilog 27 | # show waveforms specified in wave.do 28 | do wave.do 29 | 30 | # advance the simulation the desired amount of time 31 | run 5500 ns 32 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/Simulator/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module testbench ( ); 4 | 5 | parameter CLOCK_PERIOD = 20; 6 | 7 | reg [9:0] SW; 8 | wire [0:0] KEY; 9 | wire [9:0] LEDR; 10 | wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5; 11 | 12 | reg CLOCK_50; 13 | initial begin 14 | CLOCK_50 <= 1'b0; 15 | end // initial 16 | always @ (*) 17 | begin : Clock_Generator 18 | #((CLOCK_PERIOD) / 2) CLOCK_50 <= ~CLOCK_50; 19 | end 20 | 21 | reg Resetn; 22 | initial begin 23 | Resetn <= 1'b0; 24 | #20 Resetn <= 1'b1; 25 | end // initial 26 | 27 | initial begin 28 | SW <= 10'h0; 29 | #20 SW <= 10'b1000000000; 30 | #3000 SW <= 10'b1000000001; 31 | #1100 SW <= 10'b1000000101; 32 | end // initial 33 | 34 | assign KEY[0] = Resetn; 35 | part4 U1 (KEY, SW, CLOCK_50, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/flipflop.v: -------------------------------------------------------------------------------- 1 | module flipflop (D, Resetn, Clock, Q); 2 | input D, Resetn, Clock; 3 | output Q; 4 | reg Q; 5 | 6 | always @(posedge Clock) 7 | if (Resetn == 0) 8 | Q <= 1'b0; 9 | else 10 | Q <= D; 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/inst_mem.mif: -------------------------------------------------------------------------------- 1 | WIDTH = 16; 2 | DEPTH = 256; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = HEX; 5 | 6 | CONTENT 7 | BEGIN 8 | 0 : 0a07; % mv r5, r7 % 9 | 1 : 1e0c; % mv r7, #0x000c % 10 | 2 : 3420; % mvt r2, #0x2000 % 11 | 3 : 161b; % mv r3, #0x001b % 12 | 4 : 3830; % mvt r4, #0x3000 % 13 | 5 : 8004; % ld r0, [r4] % 14 | 6 : d007; % and r0, #0x0007 % 15 | 7 : 4400; % add r2, r0 % 16 | 8 : 4600; % add r3, r0 % 17 | 9 : 8003; % ld r0, [r3] % 18 | a : a002; % st r0, [r2] % 19 | b : 1e02; % mv r7, #0x0002 % 20 | c : 1000; % mv r0, #0x0000 % 21 | d : 3220; % mvt r1, #0x2000 % 22 | e : a001; % st r0, [r1] % 23 | f : 5201; % add r1, #0x0001 % 24 | 10 : a001; % st r0, [r1] % 25 | 11 : 5201; % add r1, #0x0001 % 26 | 12 : a001; % st r0, [r1] % 27 | 13 : 5201; % add r1, #0x0001 % 28 | 14 : a001; % st r0, [r1] % 29 | 15 : 5201; % add r1, #0x0001 % 30 | 16 : a001; % st r0, [r1] % 31 | 17 : 5201; % add r1, #0x0001 % 32 | 18 : a001; % st r0, [r1] % 33 | 19 : 5a01; % add r5, #0x0001 % 34 | 1a : 0e05; % mv r7, r5 % 35 | 1b : 003f; % data % 36 | 1c : 0006; % data % 37 | 1d : 005b; % data % 38 | 1e : 004f; % data % 39 | 1f : 0066; % data % 40 | 20 : 006d; % data % 41 | END; 42 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/part4.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CSEMA5F31) Path("C:/Users/profb/Dropbox/UofT/Courses/ece243_19/Labs/Lab2/solutions/DE1-SoC/part4.Verilog/") File("part4.sof") MfrSpec(OpMask(1)); 8 | P ActionCode(Ign) 9 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/part4.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part4" 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/proc.v: -------------------------------------------------------------------------------- 1 | ... use your processor code from Part III 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/seg7.v: -------------------------------------------------------------------------------- 1 | // Data written to registers R0 to R5 are sent to the H digits 2 | module seg7 (Data, Addr, Sel, Resetn, Clock, H5, H4, H3, H2, H1, H0); 3 | input [6:0] Data; 4 | input [2:0] Addr; 5 | input Sel, Resetn, Clock; 6 | output [6:0] H5, H4, H3, H2, H1, H0; 7 | 8 | wire [6:0] nData; 9 | assign nData = ~Data; 10 | 11 | reg7 reg_R0 (nData, Clock, Resetn, Sel & (Addr == 3'b000), H0); 12 | // ... fill in the rest of the code for ports H1, ..., H5 13 | endmodule 14 | 15 | module reg7 (R, Clock, Resetn, E, Q); 16 | parameter n = 7; 17 | input [n-1:0] R; 18 | input Clock, Resetn, E; 19 | output [n-1:0] Q; 20 | reg [n-1:0] Q; 21 | 22 | always @(posedge Clock) 23 | if (Resetn == 0) 24 | Q <= {n{1'b1}}; // turn OFF all segments on reset 25 | else if (E) 26 | Q <= R; 27 | endmodule 28 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work rmdir /S /Q work 8 | 9 | vlib work 10 | vlog -nolock ../tb/*.v 11 | if exist ../*.v ( 12 | vlog -nolock ../*.v 13 | ) 14 | if exist ../*.sv ( 15 | vlog -nolock ../*.sv 16 | ) 17 | if exist ../*.vhd ( 18 | vcom -nolock ../*.vhd 19 | ) 20 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | ) 10 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab10/design_files/DE1-SoC/part4.Verilog/sim/simfpga.vpi -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part4.Verilog/top.v: -------------------------------------------------------------------------------- 1 | module top (CLOCK_50, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); 2 | 3 | input CLOCK_50; // DE-series 50 MHz clock signal 4 | input wire [9:0] SW; // DE-series switches 5 | input wire [3:0] KEY; // DE-series pushbuttons 6 | 7 | output wire [6:0] HEX0; // DE-series HEX displays 8 | output wire [6:0] HEX1; 9 | output wire [6:0] HEX2; 10 | output wire [6:0] HEX3; 11 | output wire [6:0] HEX4; 12 | output wire [6:0] HEX5; 13 | 14 | output wire [9:0] LEDR; // DE-series LEDs 15 | 16 | part4 U1 (KEY[0], SW, CLOCK_50, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR); 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | # in case Quartus generated an "empty black box" file for the memory, delete it 10 | if {[file exists ../inst_mem_bb.v]} { 11 | file delete ../inst_mem_bb.v 12 | } 13 | 14 | if {[file exists work]} { 15 | file delete -force work 16 | } 17 | 18 | # create the default "work" library 19 | vlib work; 20 | 21 | # compile the Verilog source code in the parent folder 22 | vlog -nolock ../*.v 23 | # compile the Verilog code of the testbench 24 | vlog -nolock *.v 25 | # start the Simulator 26 | vsim work.testbench -Lf 220model -Lf altera_mf_ver -Lf verilog 27 | # show waveforms specified in wave.do 28 | do wave.do 29 | 30 | # advance the simulation the desired amount of time 31 | run 2500 ns 32 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/Simulator/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module testbench ( ); 4 | 5 | parameter CLOCK_PERIOD = 20; 6 | 7 | reg [9:0] SW; 8 | wire [0:0] KEY; 9 | wire [9:0] LEDR; 10 | wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5; 11 | 12 | reg CLOCK_50; 13 | initial begin 14 | CLOCK_50 <= 1'b0; 15 | end // initial 16 | always @ (*) 17 | begin : Clock_Generator 18 | #((CLOCK_PERIOD) / 2) CLOCK_50 <= ~CLOCK_50; 19 | end 20 | 21 | reg Resetn; 22 | initial begin 23 | Resetn <= 1'b0; 24 | #20 Resetn <= 1'b1; 25 | end // initial 26 | 27 | initial begin 28 | SW <= 10'h0; 29 | #40 SW <= 10'b1000000000; 30 | end // initial 31 | 32 | assign KEY[0] = Resetn; 33 | part5 U1 (KEY, SW, CLOCK_50, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR); 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/Simulator/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider proc 4 | add wave -noupdate -label Clock /testbench/U1/U3/Clock 5 | add wave -noupdate -label IR -radix hexadecimal /testbench/U1/U3/IR 6 | add wave -noupdate -label W /testbench/U1/U3/W 7 | add wave -noupdate -label Done /testbench/U1/U3/Done 8 | add wave -noupdate -label pc -radix hexadecimal /testbench/U1/U3/pc 9 | add wave -noupdate -label ADDR -radix hexadecimal /testbench/U1/U3/ADDR 10 | add wave -noupdate -label DIN -radix hexadecimal /testbench/U1/U3/DIN 11 | add wave -noupdate -label FSM /testbench/U1/U3/Tstep_Q 12 | add wave -noupdate -label r0 -radix hexadecimal /testbench/U1/U3/r0 13 | add wave -noupdate -label Buswires -radix hexadecimal /testbench/U1/U3/BusWires 14 | add wave -noupdate -label Select /testbench/U1/U3/Select 15 | add wave -noupdate -label z /testbench/U1/U3/z 16 | add wave -noupdate -label c /testbench/U1/U3/c 17 | add wave -noupdate -label n /testbench/U1/U3/n 18 | TreeUpdate [SetDefaultTree] 19 | WaveRestoreCursors {{Cursor 1} {1550000 ps} 0} 20 | quietly wave cursor active 1 21 | configure wave -namecolwidth 89 22 | configure wave -valuecolwidth 64 23 | configure wave -justifyvalue left 24 | configure wave -signalnamewidth 0 25 | configure wave -snapdistance 10 26 | configure wave -datasetprefix 0 27 | configure wave -rowmargin 4 28 | configure wave -childrowmargin 2 29 | configure wave -gridoffset 0 30 | configure wave -gridperiod 1 31 | configure wave -griddelta 40 32 | configure wave -timeline 0 33 | configure wave -timelineunits ns 34 | update 35 | WaveRestoreZoom {1383426 ps} {1656296 ps} 36 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/branches.s: -------------------------------------------------------------------------------- 1 | MAIN: mv r0, #2 2 | LOOP: sub r0, #1 // subtract to test bne 3 | bne LOOP 4 | beq T1 // r0 == 0, test beq 5 | mv pc, #DEAD 6 | T1: mvt r0, #0xFF 7 | add r0, #0xFF // r0 = 0xFFFF 8 | bcc T2 // carry = 0, test bcc 9 | mv pc, #DEAD 10 | T2: add r0, #1 11 | bcs T3 // carry = 1, test bcs 12 | mv pc, #DEAD 13 | T3: bpl T4 14 | mv pc, #DEAD 15 | T4: add r0, #-1 16 | bmi T5 17 | mv pc, #DEAD 18 | T5: b MAIN 19 | DEAD: mv pc, #DEAD 20 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/flipflop.v: -------------------------------------------------------------------------------- 1 | module flipflop (D, Resetn, Clock, Q); 2 | input D, Resetn, Clock; 3 | output Q; 4 | reg Q; 5 | 6 | always @(posedge Clock) 7 | if (Resetn == 0) 8 | Q <= 1'b0; 9 | else 10 | Q <= D; 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/inst_mem.mif: -------------------------------------------------------------------------------- 1 | WIDTH = 16; 2 | DEPTH = 256; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = HEX; 5 | 6 | CONTENT 7 | BEGIN 8 | 0 : 1002; % mv r0, #0x0002 % 9 | 1 : 7001; % sub r0, #0x0001 % 10 | 2 : 25fe; % bne 1 % 11 | 3 : 2201; % beq 5 % 12 | 4 : 1e12; % mv r7, #0x0012 % 13 | 5 : 30ff; % mvt r0, #0xff00 % 14 | 6 : 50ff; % add r0, #0x00ff % 15 | 7 : 2601; % bcc 9 % 16 | 8 : 1e12; % mv r7, #0x0012 % 17 | 9 : 5001; % add r0, #0x0001 % 18 | a : 2801; % bcs c % 19 | b : 1e12; % mv r7, #0x0012 % 20 | c : 2a01; % bpl e % 21 | d : 1e12; % mv r7, #0x0012 % 22 | e : 51ff; % add r0, #0xffff % 23 | f : 2c01; % bmi 11 % 24 | 10 : 1e12; % mv r7, #0x0012 % 25 | 11 : 21ee; % b 0 % 26 | 12 : 1e12; % mv r7, #0x0012 % 27 | END; 28 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/part5.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CSEMA5F31) Path("C:/Users/profb/Dropbox/UofT/Courses/ece243_19/Labs/Lab2/solutions/DE1-SoC/part5.Verilog/") File("part5.sof") MfrSpec(OpMask(1)); 8 | P ActionCode(Ign) 9 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/part5.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part5" 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/proc.v: -------------------------------------------------------------------------------- 1 | ... use your processor code from Part III, and add support for b{cond} 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/seg7.v: -------------------------------------------------------------------------------- 1 | // Data written to registers R0 to R5 are sent to the H digits 2 | module seg7 (Data, Addr, Sel, Resetn, Clock, H5, H4, H3, H2, H1, H0); 3 | input [6:0] Data; 4 | input [2:0] Addr; 5 | input Sel, Resetn, Clock; 6 | output [6:0] H5, H4, H3, H2, H1, H0; 7 | 8 | wire [6:0] nData; 9 | assign nData = ~Data; 10 | 11 | reg7 reg_R0 (nData, Clock, Resetn, Sel & (Addr == 3'b000), H0); 12 | reg7 reg_R1 (nData, Clock, Resetn, Sel & (Addr == 3'b001), H1); 13 | reg7 reg_R2 (nData, Clock, Resetn, Sel & (Addr == 3'b010), H2); 14 | reg7 reg_R3 (nData, Clock, Resetn, Sel & (Addr == 3'b011), H3); 15 | reg7 reg_R4 (nData, Clock, Resetn, Sel & (Addr == 3'b100), H4); 16 | reg7 reg_R5 (nData, Clock, Resetn, Sel & (Addr == 3'b101), H5); 17 | endmodule 18 | 19 | module reg7 (R, Clock, Resetn, E, Q); 20 | parameter n = 7; 21 | input [n-1:0] R; 22 | input Clock, Resetn, E; 23 | output [n-1:0] Q; 24 | reg [n-1:0] Q; 25 | 26 | always @(posedge Clock) 27 | if (Resetn == 0) 28 | Q <= {n{1'b1}}; // turn OFF all segments on reset 29 | else if (E) 30 | Q <= R; 31 | endmodule 32 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work rmdir /S /Q work 8 | 9 | vlib work 10 | vlog -nolock ../tb/*.v 11 | if exist ../*.v ( 12 | vlog -nolock ../*.v 13 | ) 14 | if exist ../*.sv ( 15 | vlog -nolock ../*.sv 16 | ) 17 | if exist ../*.vhd ( 18 | vcom -nolock ../*.vhd 19 | ) 20 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | 10 | ) 11 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab10/design_files/DE1-SoC/part5.Verilog/sim/simfpga.vpi -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/sw_led.s: -------------------------------------------------------------------------------- 1 | .define LED_ADDRESS 0x10 2 | .define SW_ADDRESS 0x30 3 | 4 | // Read SW switches and display on LEDs 5 | mvt r3, #LED_ADDRESS // point to LED port 6 | mvt r4, #SW_ADDRESS // point to SW port 7 | MAIN: ld r0, [r4] // read SW values 8 | st r0, [r3] // light up LEDs 9 | mv pc, #MAIN 10 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE1-SoC/part5.Verilog/top.v: -------------------------------------------------------------------------------- 1 | module top (CLOCK_50, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); 2 | 3 | input CLOCK_50; // DE-series 50 MHz clock signal 4 | input wire [9:0] SW; // DE-series switches 5 | input wire [3:0] KEY; // DE-series pushbuttons 6 | 7 | output wire [6:0] HEX0; // DE-series HEX displays 8 | output wire [6:0] HEX1; 9 | output wire [6:0] HEX2; 10 | output wire [6:0] HEX3; 11 | output wire [6:0] HEX4; 12 | output wire [6:0] HEX5; 13 | 14 | output wire [9:0] LEDR; // DE-series LEDs 15 | 16 | part5 U1 (KEY[0], SW, CLOCK_50, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR); 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Lite/part3.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Lite/part3.Verilog/part3.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Lite/part4.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Lite/part4.Verilog/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Lite/part5.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Lite/part5.Verilog/part5.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part5" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part3.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part3.Verilog/part3.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSXFC6D6F31) Path("C:/Users/profb/Dropbox/U_Program/Laboratory_Exercises/Digital_Logic/vhdl/Exercise10/solutions/DE10-Standard/part3.VHDL/") File("part3.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part3.Verilog/part3.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part4.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part4.Verilog/part4.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSXFC6D6F31) Path("C:/Users/profb/Dropbox/U_Program/Laboratory_Exercises/Digital_Logic/vhdl/Exercise10/solutions/DE10-Standard/part4.VHDL/") File("part4.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part4.Verilog/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part5.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part5.Verilog/part5.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSXFC6D6F31) Path("C:/Users/profb/Dropbox/U_Program/Laboratory_Exercises/Digital_Logic/vhdl/Exercise10/solutions/DE10-Standard/part5.VHDL/") File("part5.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE10-Standard/part5.Verilog/part5.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part5" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE2-115/part3.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE2-115/part3.Verilog/part3.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE2-115/part4.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE2-115/part4.Verilog/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE2-115/part5.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab10/design_files/DE2-115/part5.Verilog/part5.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part5" 24 | -------------------------------------------------------------------------------- /verilog/lab10/doc/figures/figure12_F.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab10/doc/figures/figure12_F.pdf -------------------------------------------------------------------------------- /verilog/lab10/doc/figures/figure13.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab10/doc/figures/figure13.pdf -------------------------------------------------------------------------------- /verilog/lab10/doc/figures/figure14.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab10/doc/figures/figure14.pdf -------------------------------------------------------------------------------- /verilog/lab10/doc/figures/part3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab10/doc/figures/part3.png -------------------------------------------------------------------------------- /verilog/lab10/doc/figures/part5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab10/doc/figures/part5.png -------------------------------------------------------------------------------- /verilog/lab11/design_files/barrel/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # create the default "work" library 5 | vlib work; 6 | 7 | # compile the Verilog source code in the parent folder 8 | vlog -nolock ../*.v 9 | # compile the Verilog code of the testbench 10 | vlog -nolock *.v 11 | # start the Simulator, including some libraries that may be needed 12 | vsim work.testbench -Lf 220model -Lf altera_mf_ver -Lf verilog 13 | # show waveforms specified in wave.do 14 | do wave.do 15 | # advance the simulation the desired amount of time 16 | run 360 ns 17 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/barrel/Simulator/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module testbench ( ); 4 | reg [1:0] shift_type; 5 | reg [15:0] data_in; 6 | wire [15:0] data_out; 7 | reg [3:0] shift; 8 | 9 | parameter lsl = 2'b00, lsr = 2'b01, asr = 2'b10, ror = 2'b11; 10 | 11 | barrel U1 (shift_type, shift, data_in, data_out); 12 | 13 | initial begin 14 | shift_type <= lsl; data_in <= 16'hF0F0; shift <= 4'b0; 15 | #20 shift <= 4'b1; 16 | #20 shift_type <= lsr; 17 | #20 shift_type = lsl; shift <= 4'b0100; 18 | #20 shift_type <= lsr; 19 | #20 shift_type <= asr; shift <= 4'b0; 20 | #20 shift <= 4'b0100; 21 | #20 shift_type <= ror; shift <= 4'b0; 22 | #20 shift <= 4'b0100; 23 | #20 shift <= 4'b1000; 24 | #20 shift_type <= asr; data_in <= 16'h8080; shift <= 4'b0; 25 | #20 shift <= 4'b1; 26 | #20 shift <= 4'b0100; 27 | #20 shift_type = ror; shift <= 4'b1; 28 | #20 shift_type = ror; shift <= 4'b0100; 29 | #20 shift_type = ror; shift <= 4'b1111; 30 | end // initial 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/barrel/Simulator/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider Barrel 4 | add wave -noupdate -label shift_type /testbench/U1/shift_type 5 | add wave -noupdate -label data_in -radix hexadecimal /testbench/U1/data_in 6 | add wave -noupdate -label data_out -radix hexadecimal /testbench/U1/data_out 7 | add wave -noupdate -label shift -radix hexadecimal /testbench/U1/shift 8 | TreeUpdate [SetDefaultTree] 9 | WaveRestoreCursors {{Cursor 1} {20000 ps} 0} 10 | quietly wave cursor active 1 11 | configure wave -namecolwidth 85 12 | configure wave -valuecolwidth 64 13 | configure wave -justifyvalue left 14 | configure wave -signalnamewidth 0 15 | configure wave -snapdistance 10 16 | configure wave -datasetprefix 0 17 | configure wave -rowmargin 4 18 | configure wave -childrowmargin 2 19 | configure wave -gridoffset 0 20 | configure wave -gridperiod 1 21 | configure wave -griddelta 40 22 | configure wave -timeline 0 23 | configure wave -timelineunits ns 24 | update 25 | WaveRestoreZoom {0 ps} {235352 ps} 26 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/barrel/barrel.v: -------------------------------------------------------------------------------- 1 | // This module specifies a barrel shifter that can perform lsl, lsr, asr, and ror 2 | module barrel (shift_type, shift, data_in, data_out); 3 | input wire [1:0] shift_type; 4 | input wire [3:0] shift; 5 | input wire [15:0] data_in; 6 | output reg [15:0] data_out; 7 | 8 | parameter lsl = 2'b00, lsr = 2'b01, asr = 2'b10, ror = 2'b11; 9 | 10 | always @(*) 11 | if (shift_type == lsl) 12 | data_out = data_in << shift; 13 | else if (shift_type == lsr) 14 | data_out = data_in >> shift; 15 | else if (shift_type == asr) 16 | data_out = {{16{data_in[15]}},data_in} >> shift; // sign extend 17 | else // ror 18 | data_out = (data_in >> shift) | (data_in << (16 - shift)); 19 | endmodule 20 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/figure_26.s: -------------------------------------------------------------------------------- 1 | START: mvt sp, #0x10 // sp = 0x1000 = 4096 2 | mv r4, =0x0F0F 3 | push r4 4 | bl SUBR 5 | pop r4 6 | END: b END 7 | 8 | SUBR: sub r4, r4 9 | mv pc, lr 10 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/figure_28.s: -------------------------------------------------------------------------------- 1 | START: mv r0, #4 2 | mv r4, =0x0F0F 3 | lsl r4, #1 // lsl with Op2 = #D 4 | lsr r4, #1 // lsr with Op2 = #D 5 | lsl r4, r0 // lsl with Op2 = rY 6 | asr r4, #1 // asr with Op2 = #D 7 | ror r4, r0 // ror with Op2 = rY 8 | END: b END 9 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/Readme.txt: -------------------------------------------------------------------------------- 1 | The files part8.qsf and part8.cdf are suitable for the DE1-SoC board. If you 2 | are using a different board, then these files should be changed as needed. 3 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | 10 | # create the default "work" library 11 | vlib work; 12 | 13 | # compile the Verilog source code in the parent folder 14 | vlog -nolock ../*.v 15 | # compile the Verilog code of the testbench 16 | vlog -nolock *.v 17 | # start the Simulator 18 | vsim work.testbench -Lf 220model -Lf altera_mf_ver -Lf verilog 19 | # show waveforms specified in wave.do 20 | do wave.do 21 | # advance the simulation the desired amount of time 22 | run 2750 ns 23 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/Simulator/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module testbench ( ); 4 | 5 | parameter CLOCK_PERIOD = 20; 6 | 7 | reg [9:0] SW; 8 | wire [0:0] KEY; 9 | wire [9:0] LEDR; 10 | wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5; 11 | 12 | reg CLOCK_50; 13 | initial begin 14 | CLOCK_50 <= 1'b0; 15 | end // initial 16 | always @ (*) 17 | begin : Clock_Generator 18 | #((CLOCK_PERIOD) / 2) CLOCK_50 <= ~CLOCK_50; 19 | end 20 | 21 | reg Resetn; 22 | initial begin 23 | Resetn <= 1'b0; 24 | #20 Resetn <= 1'b1; 25 | end // initial 26 | 27 | initial begin 28 | SW <= 10'h0; 29 | #40 SW <= 10'b1000000011; 30 | end // initial 31 | 32 | assign KEY[0] = Resetn; 33 | part8 U1 (KEY, SW, CLOCK_50, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR); 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/flipflop.v: -------------------------------------------------------------------------------- 1 | module flipflop (D, Resetn, Clock, Q); 2 | input D, Resetn, Clock; 3 | output Q; 4 | reg Q; 5 | 6 | always @(posedge Clock) 7 | if (Resetn == 0) 8 | Q <= 1'b0; 9 | else 10 | Q <= D; 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/part8.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part8" 2 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/proc.v: -------------------------------------------------------------------------------- 1 | 2 | ... put your processor code here 3 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/seg7.v: -------------------------------------------------------------------------------- 1 | // Data written to registers R0 to R5 are sent to the H digits 2 | module seg7 (Data, Addr, Sel, Resetn, Clock, H5, H4, H3, H2, H1, H0); 3 | input wire [6:0] Data; 4 | input wire [2:0] Addr; 5 | input wire Sel, Resetn, Clock; 6 | output wire [6:0] H5, H4, H3, H2, H1, H0; 7 | 8 | wire [6:0] nData; 9 | assign nData = ~Data; 10 | 11 | reg7 reg_R0 (nData, Clock, Resetn, Sel & (Addr == 3'b000), H0); 12 | reg7 reg_R1 (nData, Clock, Resetn, Sel & (Addr == 3'b001), H1); 13 | reg7 reg_R2 (nData, Clock, Resetn, Sel & (Addr == 3'b010), H2); 14 | reg7 reg_R3 (nData, Clock, Resetn, Sel & (Addr == 3'b011), H3); 15 | reg7 reg_R4 (nData, Clock, Resetn, Sel & (Addr == 3'b100), H4); 16 | reg7 reg_R5 (nData, Clock, Resetn, Sel & (Addr == 3'b101), H5); 17 | endmodule 18 | 19 | module reg7 (R, Clock, Resetn, E, Q); 20 | parameter n = 7; 21 | input wire [n-1:0] R; 22 | input wire Clock, Resetn, E; 23 | output reg [n-1:0] Q; 24 | 25 | always @(posedge Clock) 26 | if (Resetn == 0) 27 | Q <= {n{1'b1}}; // turn OFF all segments on reset 28 | else if (E) 29 | Q <= R; 30 | endmodule 31 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work rmdir /S /Q work 8 | 9 | vlib work 10 | vlog ../tb/*.v 11 | vlog ../*.v 12 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 2 | -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab11/design_files/part8/sim/simfpga.vpi -------------------------------------------------------------------------------- /verilog/lab11/design_files/part8/top.v: -------------------------------------------------------------------------------- 1 | module top (CLOCK_50, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); 2 | 3 | input wire CLOCK_50; // DE-series 50 MHz clock signal 4 | input wire [9:0] SW; // DE-series switches 5 | input wire [3:0] KEY; // DE-series pushbuttons 6 | 7 | output wire [6:0] HEX0; // DE-series HEX displays 8 | output wire [6:0] HEX1; 9 | output wire [6:0] HEX2; 10 | output wire [6:0] HEX3; 11 | output wire [6:0] HEX4; 12 | output wire [6:0] HEX5; 13 | 14 | output wire [9:0] LEDR; // DE-series LEDs 15 | 16 | part8 U1 (KEY[0], SW, CLOCK_50, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR); 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /verilog/lab11/doc/figures/bl_pop.png: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ns 2 | 3 | module testbench (); 4 | reg Clk_tb; 5 | reg R_tb; 6 | reg S_tb; 7 | wire Q_tb; 8 | 9 | initial 10 | begin: CLOCK_GENERATOR 11 | Clk_tb = 1; 12 | forever 13 | begin 14 | #5 Clk_tb = ~Clk_tb; 15 | end 16 | end 17 | 18 | initial 19 | begin 20 | R_tb <= 1; S_tb <= 0; 21 | #20 R_tb <= 0; 22 | #20 S_tb <= 1; 23 | #20 S_tb <= 0; 24 | #20 R_tb <= 1; 25 | end 26 | 27 | part1 p1 (Clk_tb, R_tb, S_tb, Q_tb); 28 | endmodule -------------------------------------------------------------------------------- /verilog/lab3/design_files/part4/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ns 2 | 3 | module testbench (); 4 | reg Clk_tb; 5 | reg D_tb; 6 | wire Qa_tb; 7 | wire Qb_tb; 8 | wire Qc_tb; 9 | 10 | initial 11 | begin: CLOCK_GENERATOR 12 | Clk_tb = 0; 13 | forever 14 | begin 15 | #30 Clk_tb = ~Clk_tb; 16 | end 17 | end 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-------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ns 2 | 3 | module testbench (); 4 | reg [4:0] addr_tb; 5 | reg clock_tb; 6 | reg [3:0] din_tb; 7 | reg wren_tb; 8 | wire [3:0] dout_tb; 9 | 10 | initial 11 | begin: CLOCK_GENERATOR 12 | clock_tb = 0; 13 | forever 14 | begin 15 | #5 clock_tb = ~clock_tb; 16 | end 17 | end 18 | 19 | initial 20 | begin 21 | addr_tb <= 5'b00000; din_tb <= 4'b0000; wren_tb <= 0; 22 | #20 din_tb <= 4'b1010; wren_tb <= 1; 23 | #10 din_tb <= 4'b0000; wren_tb <= 0; 24 | #10 addr_tb <= 5'b11111; din_tb <= 4'b0101; wren_tb <= 1; 25 | #10 addr_tb <= 5'b00000; din_tb <= 4'b0000; wren_tb <= 0; 26 | #10 addr_tb <= 5'b11111; 27 | end 28 | 29 | ram32x4 ram (addr_tb, clock_tb, din_tb, wren_tb, dout_tb); 30 | endmodule -------------------------------------------------------------------------------- /verilog/lab8/doc/figures/figure1.fm: -------------------------------------------------------------------------------- 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../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE0-CV/part2.Verilog/part2.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part2" 24 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part1.Verilog/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # create the default "work" library 5 | vlib work; 6 | 7 | # compile the Verilog source code in the parent folder 8 | vlog -nolock ../*.v 9 | # compile the Verilog code of the testbench 10 | vlog -nolock *.v 11 | # start the Simulator, including some libraries that may be needed 12 | vsim work.testbench -Lf 220model -Lf altera_mf_ver -Lf verilog 13 | # show waveforms specified in wave.do 14 | do wave.do 15 | # advance the simulation the desired amount of time 16 | run 360 ns 17 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part1.Verilog/Simulator/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module testbench ( ); 4 | 5 | parameter CLOCK_PERIOD = 20; 6 | 7 | reg [15:0] Instruction; 8 | reg Run; 9 | wire Done; 10 | 11 | reg CLOCK_50; 12 | initial begin 13 | CLOCK_50 <= 1'b0; 14 | end // initial 15 | always @ (*) 16 | begin : Clock_Generator 17 | #((CLOCK_PERIOD) / 2) CLOCK_50 <= ~CLOCK_50; 18 | end 19 | 20 | reg Resetn; 21 | initial begin 22 | Resetn <= 1'b0; 23 | #20 Resetn <= 1'b1; 24 | end // initial 25 | 26 | initial begin 27 | Run <= 1'b0; Instruction <= 16'b0000000000000000; 28 | #20 Run <= 1'b1; Instruction <= 16'b0001000000011100; // mv r0, #28 29 | #20 Run <= 1'b0; 30 | #20 Run <= 1'b1; Instruction <= 16'b0011001011111111; // mvt r1, #0xFF00 31 | #20 Run <= 1'b0; 32 | #20 Run <= 1'b1; Instruction <= 16'b0101001011111111; // add r1, #0xFF 33 | #20 Run <= 1'b0; 34 | #60 Run <= 1'b1; Instruction <= 16'b0110001000000000; // sub r1, r0 35 | #20 Run <= 1'b0; 36 | #60 Run <= 1'b1; Instruction <= 16'b0101001000000001; // add r1, #1 37 | #20 Run <= 1'b0; 38 | end // initial 39 | 40 | proc U1 (Instruction, Resetn, CLOCK_50, Run, Done); 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part1.Verilog/Simulator/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -label Resetn /testbench/Resetn 4 | add wave -noupdate -label CLOCK_50 /testbench/CLOCK_50 5 | add wave -noupdate -label Run /testbench/Run 6 | add wave -noupdate -label Instruction -radix hexadecimal /testbench/Instruction 7 | add wave -noupdate -divider proc 8 | add wave -noupdate -label Resetn /testbench/U1/Resetn 9 | add wave -noupdate -label Clock /testbench/U1/Clock 10 | add wave -noupdate -label Run /testbench/U1/Run 11 | add wave -noupdate -label DIN -radix hexadecimal /testbench/U1/DIN 12 | add wave -noupdate -label Done /testbench/U1/Done 13 | add wave -noupdate -label IR -radix hexadecimal /testbench/U1/IR 14 | add wave -noupdate -label Tstep_Q /testbench/U1/Tstep_Q 15 | add wave -noupdate -label r0 -radix hexadecimal /testbench/U1/r0 16 | add wave -noupdate -label r1 -radix hexadecimal /testbench/U1/r1 17 | add wave -noupdate -label A -radix hexadecimal /testbench/U1/A 18 | add wave -noupdate -label G -radix hexadecimal /testbench/U1/G 19 | add wave -noupdate -label BusWires -radix hexadecimal /testbench/U1/BusWires 20 | TreeUpdate [SetDefaultTree] 21 | WaveRestoreCursors {{Cursor 1} {260000 ps} 0} 22 | quietly wave cursor active 1 23 | configure wave -namecolwidth 98 24 | configure wave -valuecolwidth 40 25 | configure wave -justifyvalue left 26 | configure wave -signalnamewidth 0 27 | configure wave -snapdistance 10 28 | configure wave -datasetprefix 0 29 | configure wave -rowmargin 4 30 | configure wave -childrowmargin 2 31 | configure wave -gridoffset 0 32 | configure wave -gridperiod 1 33 | configure wave -griddelta 40 34 | configure wave -timeline 0 35 | configure wave -timelineunits ns 36 | update 37 | WaveRestoreZoom {62500 ps} {312500 ps} 38 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | # in case Quartus generated an "empty black box" file for the memory, delete it 10 | if {[file exists ../inst_mem_bb.v]} { 11 | file delete ../inst_mem_bb.v 12 | } 13 | 14 | # create the default "work" library 15 | vlib work; 16 | 17 | # compile the Verilog source code in the parent folder 18 | vlog -nolock ../*.v 19 | # compile the Verilog code of the testbench 20 | vlog -nolock *.v 21 | # start the Simulator 22 | vsim work.testbench -Lf 220model -Lf altera_mf_ver -Lf verilog 23 | # show waveforms specified in wave.do 24 | do wave.do 25 | # advance the simulation the desired amount of time 26 | run 400 ns 27 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/Simulator/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -label KEY /testbench/KEY 4 | add wave -noupdate -label SW /testbench/SW 5 | add wave -noupdate -label counter -radix hexadecimal /testbench/U1/U3/Q 6 | add wave -noupdate -label MClock /testbench/U1/U3/Clock 7 | add wave -noupdate -divider proc 8 | add wave -noupdate -label PClock /testbench/U1/U1/Clock 9 | add wave -noupdate -label Resetn /testbench/U1/U1/Resetn 10 | add wave -noupdate -label Run /testbench/U1/U1/Run 11 | add wave -noupdate -label IR -radix hexadecimal /testbench/U1/U1/IR 12 | add wave -noupdate -label Done /testbench/U1/U1/Done 13 | add wave -noupdate -label inst_mem -radix hexadecimal /testbench/U1/U2/q 14 | add wave -noupdate -label FSM /testbench/U1/U1/Tstep_Q 15 | add wave -noupdate -label r0 -radix hexadecimal /testbench/U1/U1/r0 16 | add wave -noupdate -label r1 -radix hexadecimal /testbench/U1/U1/r1 17 | TreeUpdate [SetDefaultTree] 18 | WaveRestoreCursors {{Cursor 1} {70000 ps} 0} 19 | quietly wave cursor active 1 20 | configure wave -namecolwidth 92 21 | configure wave -valuecolwidth 66 22 | configure wave -justifyvalue left 23 | configure wave -signalnamewidth 0 24 | configure wave -snapdistance 10 25 | configure wave -datasetprefix 0 26 | configure wave -rowmargin 4 27 | configure wave -childrowmargin 2 28 | configure wave -gridoffset 0 29 | configure wave -gridperiod 1 30 | configure wave -griddelta 40 31 | configure wave -timeline 0 32 | configure wave -timelineunits ns 33 | update 34 | WaveRestoreZoom {25326 ps} {325326 ps} 35 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/inst_mem.mif: -------------------------------------------------------------------------------- 1 | DEPTH = 32; 2 | WIDTH = 16; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = BIN; 5 | CONTENT 6 | BEGIN 7 | 00 : 0001000000011100; % mv r0, #28 % 8 | 01 : 0011001011111111; % mvt r1, #0xFF % 9 | 02 : 0101001011111111; % add r1, #0xFF % 10 | 03 : 0110001000000000; % sub r1, r0 % 11 | 04 : 0101001000000001; % add r1, #1 % 12 | 05 : 0000000000000000; 13 | 06 : 0000000000000000; 14 | 07 : 0000000000000000; 15 | 08 : 0000000000000000; 16 | 09 : 0000000000000000; 17 | 0A : 0000000000000000; 18 | 0B : 0000000000000000; 19 | 0C : 0000000000000000; 20 | 0D : 0000000000000000; 21 | 0E : 0000000000000000; 22 | 0F : 0000000000000000; 23 | 10 : 0000000000000000; 24 | 11 : 0000000000000000; 25 | 12 : 0000000000000000; 26 | 13 : 0000000000000000; 27 | 14 : 0000000000000000; 28 | 15 : 0000000000000000; 29 | 16 : 0000000000000000; 30 | 17 : 0000000000000000; 31 | 18 : 0000000000000000; 32 | 19 : 0000000000000000; 33 | 1A : 0000000000000000; 34 | 1B : 0000000000000000; 35 | 1C : 0000000000000000; 36 | 1D : 0000000000000000; 37 | 1E : 0000000000000000; 38 | 1F : 0000000000000000; 39 | END; 40 | 41 | 42 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/part2.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSEMA5F31) Path("C:/Users/profb/Dropbox/UofT/Courses/ece243_19/Labs/Lab1/solutions/part2.Verilog/") File("part2.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/part2.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part2" 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/part2.v: -------------------------------------------------------------------------------- 1 | // Reset with SW[0]. Clock counter and memory with KEY[0]. Clock 2 | // each instuction into the processor with KEY[1]. SW[9] is the Run input. 3 | // Use KEY[0] to advance the memory as needed before each processor KEY[1] 4 | // clock cycle. 5 | module part2 (KEY, SW, LEDR); 6 | input [1:0] KEY; 7 | input [9:0] SW; 8 | output [9:0] LEDR; 9 | 10 | wire Done, Resetn, PClock, MClock, Run; 11 | wire [15:0] DIN; 12 | wire [4:0] pc; 13 | 14 | assign Resetn = SW[0]; 15 | assign MClock = KEY[0]; 16 | assign PClock = KEY[1]; 17 | assign Run = SW[9]; 18 | 19 | proc U1 (DIN, Resetn, PClock, Run, Done); 20 | assign LEDR[0] = Done; 21 | assign LEDR[9] = Run; 22 | 23 | inst_mem U2 (pc, MClock, DIN); 24 | count5 U3 (Resetn, MClock, pc); 25 | endmodule 26 | 27 | module count5 (Resetn, Clock, Q); 28 | input Resetn, Clock; 29 | output reg [4:0] Q; 30 | 31 | always @ (posedge Clock, negedge Resetn) 32 | if (Resetn == 0) 33 | Q <= 5'b00000; 34 | else 35 | Q <= Q + 1'b1; 36 | endmodule 37 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/proc.v: -------------------------------------------------------------------------------- 1 | // use your processor from Part 1 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work rmdir /S /Q work 8 | 9 | vlib work 10 | vlog -nolock ../tb/*.v 11 | if exist ../*.v ( 12 | vlog -nolock ../*.v 13 | ) 14 | if exist ../*.sv ( 15 | vlog -nolock ../*.sv 16 | ) 17 | if exist ../*.vhd ( 18 | vcom -nolock ../*.vhd 19 | ) 20 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | ) 10 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/verilog/lab9/design_files/DE1-SoC/part2.Verilog/sim/simfpga.vpi -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE1-SoC/part2.Verilog/top.v: -------------------------------------------------------------------------------- 1 | module top (CLOCK_50, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); 2 | 3 | input CLOCK_50; // DE-series 50 MHz clock signal 4 | input wire [9:0] SW; // DE-series switches 5 | input wire [3:0] KEY; // DE-series pushbuttons 6 | 7 | output wire [6:0] HEX0; // DE-series HEX displays 8 | output wire [6:0] HEX1; 9 | output wire [6:0] HEX2; 10 | output wire [6:0] HEX3; 11 | output wire [6:0] HEX4; 12 | output wire [6:0] HEX5; 13 | 14 | output wire [9:0] LEDR; // DE-series LEDs 15 | 16 | part2 U1 (KEY[1:0], SW, LEDR); 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE10-Lite/part1.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE10-Lite/part2.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE10-Lite/part2.Verilog/part2.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part2" 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE10-Standard/part1.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE10-Standard/part2.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE10-Standard/part2.Verilog/part2.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSXFC6D6F31) Path("C:/Users/brownste/Dropbox/U_Program/Laboratory_Exercises/Digital_Logic/verilog/Exercise9/solutions/DE10-Standard/part2.Verilog/") File("part2.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE10-Standard/part2.Verilog/part2.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part2" 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE2-115/part1.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE2-115/part2.Verilog/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /verilog/lab9/design_files/DE2-115/part2.Verilog/part2.qpf: -------------------------------------------------------------------------------- 1 | # Revisions 2 | 3 | PROJECT_REVISION = "part2" 4 | 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4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE0-CV/part4.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE0-CV/part4.VHDL/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE0-CV/part5.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE0-CV/part5.VHDL/part5.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part5" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | # in case Quartus generated an "empty black box" file for the memory, delete it 10 | if {[file exists ../inst_mem_bb.vhd]} { 11 | file delete ../inst_mem_bb.vhd 12 | } 13 | 14 | if {[file exists work]} { 15 | file delete -force work 16 | } 17 | 18 | # create the default work folder 19 | vlib work 20 | 21 | # compile the VHDL source code in the parent folder 22 | vcom -nolock ../*.vhd 23 | # compile the VHDL code of the testbench 24 | vcom -nolock *.vht 25 | # start the Simulator, including some libraries that may be needed 26 | vsim work.testbench -Lf 220model -Lf altera_mf 27 | # show waveforms specified in wave.do 28 | do wave.do 29 | 30 | # suppress annoying VHDL warnings 31 | set StdArithNoWarnings 1 32 | set NumericStdNoWarnings 1 33 | 34 | # advance the simulation the desired amount of time 35 | run 1800 ns 36 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/Simulator/testbench.vht: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_signed.all; 4 | 5 | ENTITY testbench IS 6 | END testbench; 7 | 8 | ARCHITECTURE Behavior OF testbench IS 9 | COMPONENT part3 10 | PORT ( KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 11 | SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 12 | CLOCK_50 : IN STD_LOGIC; 13 | LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); 14 | END COMPONENT; 15 | 16 | SIGNAL CLOCK_50 : STD_LOGIC; 17 | SIGNAL SW : STD_LOGIC_VECTOR(9 DOWNTO 0); 18 | SIGNAL KEY : STD_LOGIC_VECTOR(0 DOWNTO 0); 19 | SIGNAL LEDR : STD_LOGIC_VECTOR(9 DOWNTO 0); 20 | CONSTANT clock_period : time := 20 ns; 21 | 22 | BEGIN 23 | clock_process: PROCESS 24 | BEGIN 25 | CLOCK_50 <= '0'; 26 | WAIT FOR clock_period / 2; 27 | CLOCK_50 <= '1'; 28 | WAIT FOR clock_period / 2; 29 | END PROCESS; 30 | 31 | KEY_process: PROCESS 32 | BEGIN 33 | KEY <= "0"; 34 | WAIT FOR 20 ns; -- perform reset 35 | KEY <= "1"; 36 | WAIT; 37 | END PROCESS; 38 | 39 | SW_process: PROCESS 40 | BEGIN 41 | SW <= "0000000000"; 42 | WAIT FOR 20 ns; -- wait until after reset 43 | SW <= "1010101010"; -- provide an LEDR pattern 44 | WAIT FOR 560 ns; 45 | SW <= "1101010101"; -- provide another LEDR pattern 46 | WAIT; 47 | END PROCESS; 48 | 49 | U1: part3 PORT MAP (KEY, SW, CLOCK_50, LEDR); 50 | END; 51 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/flipflop.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | 4 | ENTITY flipflop IS 5 | PORT ( D, Resetn, Clock : IN STD_LOGIC; 6 | Q : OUT STD_LOGIC); 7 | END flipflop; 8 | 9 | ARCHITECTURE Behavior OF flipflop IS 10 | BEGIN 11 | PROCESS (Clock) 12 | BEGIN 13 | IF (Clock'EVENT AND Clock = '1') THEN 14 | IF (Resetn = '0') THEN 15 | Q <= '0'; 16 | ELSE 17 | Q <= D; 18 | END IF; 19 | END IF; 20 | END PROCESS; 21 | END Behavior; 22 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/inst_mem.mif: -------------------------------------------------------------------------------- 1 | WIDTH = 16; 2 | DEPTH = 256; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = HEX; 5 | 6 | CONTENT 7 | BEGIN 8 | 0 : 3610; % mvt r3, #0x1000 % 9 | 1 : 3830; % mvt r4, #0x3000 % 10 | 2 : 8004; % ld r0, [r4] % 11 | 3 : a003; % st r0, [r3] % 12 | 4 : 1e02; % mv r7, #0x0002 % 13 | END; 14 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/part3.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CSEMA5F31) Path("C:/Users/profb/Dropbox/UofT/Courses/ece243_19/Labs/Lab2/solutions/DE1-SoC/part3.Verilog/") File("part3.sof") MfrSpec(OpMask(1)); 8 | P ActionCode(Ign) 9 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/part3.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work rmdir /S /Q work 8 | 9 | vlib work 10 | vlog -nolock ../tb/*.v 11 | if exist ../*.v ( 12 | vlog -nolock ../*.v 13 | ) 14 | if exist ../*.sv ( 15 | vlog -nolock ../*.sv 16 | ) 17 | if exist ../*.vhd ( 18 | vcom -nolock ../*.vhd 19 | ) 20 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | ) 10 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab10/design_files/DE1-SoC/part3.VHDL/sim/simfpga.vpi -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/sw_led.s: -------------------------------------------------------------------------------- 1 | .define LED_ADDRESS 0x10 2 | .define SW_ADDRESS 0x30 3 | 4 | // Read SW switches and display on LEDs 5 | mvt r3, #LED_ADDRESS // point to LED port 6 | mvt r4, #SW_ADDRESS // point to SW port 7 | MAIN: ld r0, [r4] // read SW values 8 | st r0, [r3] // light up LEDs 9 | mv pc, #MAIN 10 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part3.VHDL/top.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_unsigned.all; 4 | 5 | ENTITY Top IS 6 | PORT ( 7 | CLOCK_50 : IN STD_LOGIC; -- DE-series 50 MHz clock signal 8 | KEY : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); -- DE-series pushbuttons 9 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); -- DE-series switches 10 | HEX0 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); -- DE-series HEX displays 11 | HEX1 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 12 | HEX2 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 13 | HEX3 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 14 | HEX4 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 15 | HEX5 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 16 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) -- DE-series LEDs 17 | ); 18 | END Top; 19 | 20 | ARCHITECTURE Behavior OF Top IS 21 | COMPONENT part3 22 | PORT ( 23 | KEY : IN STD_LOGIC_VECTOR( 0 DOWNTO 0); 24 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); 25 | CLOCK_50 : IN STD_LOGIC; 26 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) 27 | ); 28 | END COMPONENT; 29 | BEGIN 30 | 31 | U1: part3 PORT MAP (KEY(0 DOWNTO 0), SW, CLOCK_50, LEDR); 32 | HEX0 <= "1111111"; 33 | HEX1 <= "1111111"; 34 | HEX2 <= "1111111"; 35 | HEX3 <= "1111111"; 36 | HEX4 <= "1111111"; 37 | HEX5 <= "1111111"; 38 | 39 | END Behavior; 40 | 41 | 42 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | # in case Quartus generated an "empty black box" file for the memory, delete it 10 | if {[file exists ../inst_mem_bb.vhd]} { 11 | file delete ../inst_mem_bb.vhd 12 | } 13 | 14 | if {[file exists work]} { 15 | file delete -force work 16 | } 17 | 18 | # create the default work folder 19 | vlib work 20 | 21 | # compile the VHDL source code in the parent folder 22 | vcom -nolock ../*.vhd 23 | # compile the VHDL code of the testbench 24 | vcom -nolock *.vht 25 | # start the Simulator, including some libraries that may be needed 26 | vsim work.testbench -Lf 220model -Lf altera_mf 27 | # show waveforms specified in wave.do 28 | do wave.do 29 | 30 | # suppress annoying VHDL warnings 31 | set StdArithNoWarnings 1 32 | set NumericStdNoWarnings 1 33 | 34 | # advance the simulation the desired amount of time 35 | run 5500 ns 36 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/flipflop.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | 4 | ENTITY flipflop IS 5 | PORT ( D, Resetn, Clock : IN STD_LOGIC; 6 | Q : OUT STD_LOGIC); 7 | END flipflop; 8 | 9 | ARCHITECTURE Behavior OF flipflop IS 10 | BEGIN 11 | PROCESS (Clock) 12 | BEGIN 13 | IF (Clock'EVENT AND Clock = '1') THEN 14 | IF (Resetn = '0') THEN 15 | Q <= '0'; 16 | ELSE 17 | Q <= D; 18 | END IF; 19 | END IF; 20 | END PROCESS; 21 | END Behavior; 22 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/inst_mem.mif: -------------------------------------------------------------------------------- 1 | WIDTH = 16; 2 | DEPTH = 256; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = HEX; 5 | 6 | CONTENT 7 | BEGIN 8 | 0 : 0a07; % mv r5, r7 % 9 | 1 : 1e0c; % mv r7, #0x000c % 10 | 2 : 3420; % mvt r2, #0x2000 % 11 | 3 : 161b; % mv r3, #0x001b % 12 | 4 : 3830; % mvt r4, #0x3000 % 13 | 5 : 8004; % ld r0, [r4] % 14 | 6 : d007; % and r0, #0x0007 % 15 | 7 : 4400; % add r2, r0 % 16 | 8 : 4600; % add r3, r0 % 17 | 9 : 8003; % ld r0, [r3] % 18 | a : a002; % st r0, [r2] % 19 | b : 1e02; % mv r7, #0x0002 % 20 | c : 1000; % mv r0, #0x0000 % 21 | d : 3220; % mvt r1, #0x2000 % 22 | e : a001; % st r0, [r1] % 23 | f : 5201; % add r1, #0x0001 % 24 | 10 : a001; % st r0, [r1] % 25 | 11 : 5201; % add r1, #0x0001 % 26 | 12 : a001; % st r0, [r1] % 27 | 13 : 5201; % add r1, #0x0001 % 28 | 14 : a001; % st r0, [r1] % 29 | 15 : 5201; % add r1, #0x0001 % 30 | 16 : a001; % st r0, [r1] % 31 | 17 : 5201; % add r1, #0x0001 % 32 | 18 : a001; % st r0, [r1] % 33 | 19 : 5a01; % add r5, #0x0001 % 34 | 1a : 0e05; % mv r7, r5 % 35 | 1b : 003f; % data % 36 | 1c : 0006; % data % 37 | 1d : 005b; % data % 38 | 1e : 004f; % data % 39 | 1f : 0066; % data % 40 | 20 : 006d; % data % 41 | END; 42 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/part4.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CSEMA5F31) Path("C:/Users/profb/Dropbox/UofT/Courses/ece243_19/Labs/Lab2/solutions/DE1-SoC/part4.Verilog/") File("part4.sof") MfrSpec(OpMask(1)); 8 | P ActionCode(Ign) 9 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/proc.vhd: -------------------------------------------------------------------------------- 1 | ... use your processor code from Part III 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/seg7.vhd: -------------------------------------------------------------------------------- 1 | -- Data written to registers R0 to R5 are sent to the H digits 2 | LIBRARY ieee; 3 | USE ieee.std_logic_1164.all; 4 | 5 | ENTITY seg7 IS 6 | PORT ( Data : IN STD_LOGIC_VECTOR(6 DOWNTO 0); 7 | Addr : IN STD_LOGIC_VECTOR(2 DOWNTO 0); 8 | Sel, Resetn, Clock : IN STD_LOGIC; 9 | H5, H4, H3, H2, H1, H0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); 10 | END seg7; 11 | 12 | ARCHITECTURE Behavior OF seg7 IS 13 | COMPONENT regne 14 | GENERIC ( n : INTEGER := 7); 15 | PORT ( R : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); 16 | Clock, Resetn, E : IN STD_LOGIC; 17 | Q : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); 18 | END COMPONENT; 19 | 20 | SIGNAL nData : STD_LOGIC_VECTOR(6 DOWNTO 0); 21 | SIGNAL W : STD_LOGIC_VECTOR(5 DOWNTO 0); 22 | BEGIN 23 | nData <= NOT Data; 24 | 25 | W(0) <= '1' WHEN (Sel = '1' AND (Addr = "000")) ELSE '0'; 26 | reg_R0: regne PORT MAP (nData, Clock, Resetn, W(0), H0); 27 | -- ... fill in the rest of the code for ports H1, ..., H5 28 | END Behavior; 29 | 30 | LIBRARY ieee; 31 | USE ieee.std_logic_1164.all; 32 | 33 | ENTITY regne IS 34 | GENERIC ( n : INTEGER := 7); 35 | PORT ( R : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); 36 | Clock, Resetn, E : IN STD_LOGIC; 37 | Q : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); 38 | END regne; 39 | 40 | ARCHITECTURE Behavior OF regne IS 41 | BEGIN 42 | PROCESS (Clock) 43 | BEGIN 44 | IF Clock'EVENT AND Clock = '1' THEN 45 | IF Resetn = '0' THEN 46 | Q <= (OTHERS => '1'); -- turn OFF all segments 47 | ELSIF E = '1' THEN 48 | Q <= R; 49 | END IF; 50 | END IF; 51 | END PROCESS; 52 | END Behavior; 53 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work rmdir /S /Q work 8 | 9 | vlib work 10 | vlog -nolock ../tb/*.v 11 | if exist ../*.v ( 12 | vlog -nolock ../*.v 13 | ) 14 | if exist ../*.sv ( 15 | vlog -nolock ../*.sv 16 | ) 17 | if exist ../*.vhd ( 18 | vcom -nolock ../*.vhd 19 | ) 20 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | ) 10 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab10/design_files/DE1-SoC/part4.VHDL/sim/simfpga.vpi -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part4.VHDL/top.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_unsigned.all; 4 | 5 | ENTITY Top IS 6 | PORT ( 7 | CLOCK_50 : IN STD_LOGIC; -- DE-series 50 MHz clock signal 8 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); -- DE-series switches 9 | KEY : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); -- DE-series pushbuttons 10 | HEX0 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); -- DE-series HEX displays 11 | HEX1 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 12 | HEX2 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 13 | HEX3 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 14 | HEX4 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 15 | HEX5 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 16 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) -- DE-series LEDs 17 | ); 18 | END Top; 19 | 20 | ARCHITECTURE Behavior OF Top IS 21 | COMPONENT part4 22 | PORT ( 23 | KEY : IN STD_LOGIC_VECTOR( 0 DOWNTO 0); 24 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); 25 | CLOCK_50 : IN STD_LOGIC; 26 | HEX0 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 27 | HEX1 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 28 | HEX2 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 29 | HEX3 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 30 | HEX4 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 31 | HEX5 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 32 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) 33 | ); 34 | END COMPONENT; 35 | BEGIN 36 | 37 | U1: part4 PORT MAP (KEY(0 DOWNTO 0), SW, CLOCK_50, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); 38 | 39 | END Behavior; 40 | 41 | 42 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | # in case Quartus generated an "empty black box" file for the memory, delete it 10 | if {[file exists ../inst_mem_bb.vhd]} { 11 | file delete ../inst_mem_bb.vhd 12 | } 13 | 14 | if {[file exists work]} { 15 | file delete -force work 16 | } 17 | 18 | # create the default work folder 19 | vlib work 20 | 21 | # compile the VHDL source code in the parent folder 22 | vcom -nolock ../*.vhd 23 | # compile the VHDL code of the testbench 24 | vcom -nolock *.vht 25 | # start the Simulator, including some libraries that may be needed 26 | vsim work.testbench -Lf 220model -Lf altera_mf 27 | # show waveforms specified in wave.do 28 | do wave.do 29 | 30 | # suppress annoying VHDL warnings 31 | set StdArithNoWarnings 1 32 | set NumericStdNoWarnings 1 33 | 34 | # advance the simulation the desired amount of time 35 | run 2850 ns 36 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/Simulator/testbench.vht: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_signed.all; 4 | 5 | ENTITY testbench IS 6 | END testbench; 7 | 8 | ARCHITECTURE Behavior OF testbench IS 9 | COMPONENT part5 10 | PORT ( KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 11 | SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 12 | CLOCK_50 : IN STD_LOGIC; 13 | HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); 14 | LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); 15 | END COMPONENT; 16 | 17 | SIGNAL CLOCK_50 : STD_LOGIC; 18 | SIGNAL SW : STD_LOGIC_VECTOR(9 DOWNTO 0); 19 | SIGNAL KEY : STD_LOGIC_VECTOR(0 DOWNTO 0); 20 | SIGNAL HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 : STD_LOGIC_VECTOR(6 DOWNTO 0); 21 | SIGNAL LEDR : STD_LOGIC_VECTOR(9 DOWNTO 0); 22 | CONSTANT clock_period : time := 20 ns; 23 | 24 | BEGIN 25 | clock_process: PROCESS 26 | BEGIN 27 | CLOCK_50 <= '0'; 28 | WAIT FOR clock_period / 2; 29 | CLOCK_50 <= '1'; 30 | WAIT FOR clock_period / 2; 31 | END PROCESS; 32 | 33 | KEY_process: PROCESS 34 | BEGIN 35 | KEY <= "0"; 36 | WAIT FOR 20 ns; -- perform reset 37 | KEY <= "1"; 38 | WAIT; 39 | END PROCESS; 40 | 41 | SW_process: PROCESS 42 | BEGIN 43 | SW <= "0000000000"; 44 | WAIT FOR 40 ns; 45 | SW <= "1000000000"; 46 | WAIT; 47 | END PROCESS; 48 | 49 | U1: part5 PORT MAP (KEY, SW, CLOCK_50, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR); 50 | END; 51 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/Simulator/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -label Clock /testbench/CLOCK_50 4 | add wave -noupdate -label KEY /testbench/KEY 5 | add wave -noupdate -label SW /testbench/SW 6 | add wave -noupdate -divider proc 7 | add wave -noupdate -label Clock /testbench/U1/U3/Clock 8 | add wave -noupdate -label IR -radix hexadecimal /testbench/U1/U3/IR 9 | add wave -noupdate -label W /testbench/U1/U3/W 10 | add wave -noupdate -label Done /testbench/U1/U3/Done 11 | add wave -noupdate -label PC -radix hexadecimal /testbench/U1/U3/PC 12 | add wave -noupdate -label ADDR -radix hexadecimal /testbench/U1/U3/ADDR 13 | add wave -noupdate -label DIN -radix hexadecimal /testbench/U1/U3/DIN 14 | add wave -noupdate -label FSM /testbench/U1/U3/Tstep_Q 15 | add wave -noupdate -label R0 -radix hexadecimal /testbench/U1/U3/r0 16 | add wave -noupdate -label Buswires -radix hexadecimal /testbench/U1/U3/BusWires 17 | add wave -noupdate -label G -radix hexadecimal /testbench/U1/U3/G 18 | add wave -noupdate -label Sel /testbench/U1/U3/Sel 19 | add wave -noupdate -label z /testbench/U1/U3/z 20 | add wave -noupdate -label c /testbench/U1/U3/c 21 | add wave -noupdate -label n /testbench/U1/U3/n 22 | TreeUpdate [SetDefaultTree] 23 | WaveRestoreCursors {{Cursor 1} {361786 ps} 0} 24 | quietly wave cursor active 1 25 | configure wave -namecolwidth 89 26 | configure wave -valuecolwidth 64 27 | configure wave -justifyvalue left 28 | configure wave -signalnamewidth 0 29 | configure wave -snapdistance 10 30 | configure wave -datasetprefix 0 31 | configure wave -rowmargin 4 32 | configure wave -childrowmargin 2 33 | configure wave -gridoffset 0 34 | configure wave -gridperiod 1 35 | configure wave -griddelta 40 36 | configure wave -timeline 0 37 | configure wave -timelineunits ns 38 | update 39 | WaveRestoreZoom {204645 ps} {477515 ps} 40 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/branches.s: -------------------------------------------------------------------------------- 1 | MAIN: mv r0, #2 2 | LOOP: sub r0, #1 // subtract to test bne 3 | bne LOOP 4 | beq T1 // r0 == 0, test beq 5 | mv pc, #DEAD 6 | T1: mvt r0, #0xFF 7 | add r0, #0xFF // r0 = 0xFFFF 8 | bcc T2 // carry = 0, test bcc 9 | mv pc, #DEAD 10 | T2: add r0, #1 11 | bcs T3 // carry = 1, test bcs 12 | mv pc, #DEAD 13 | T3: bpl T4 14 | mv pc, #DEAD 15 | T4: add r0, #-1 16 | bmi T5 17 | mv pc, #DEAD 18 | T5: b MAIN 19 | DEAD: mv pc, #DEAD 20 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/flipflop.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | 4 | ENTITY flipflop IS 5 | PORT ( D, Resetn, Clock : IN STD_LOGIC; 6 | Q : OUT STD_LOGIC); 7 | END flipflop; 8 | 9 | ARCHITECTURE Behavior OF flipflop IS 10 | BEGIN 11 | PROCESS (Clock) 12 | BEGIN 13 | IF (Clock'EVENT AND Clock = '1') THEN 14 | IF (Resetn = '0') THEN 15 | Q <= '0'; 16 | ELSE 17 | Q <= D; 18 | END IF; 19 | END IF; 20 | END PROCESS; 21 | END Behavior; 22 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/inst_mem.mif: -------------------------------------------------------------------------------- 1 | WIDTH = 16; 2 | DEPTH = 256; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = HEX; 5 | 6 | CONTENT 7 | BEGIN 8 | 0 : 1002; % mv r0, #0x0002 % 9 | 1 : 7001; % sub r0, #0x0001 % 10 | 2 : 25fe; % bne 1 % 11 | 3 : 2201; % beq 5 % 12 | 4 : 1e12; % mv r7, #0x0012 % 13 | 5 : 30ff; % mvt r0, #0xff00 % 14 | 6 : 50ff; % add r0, #0x00ff % 15 | 7 : 2601; % bcc 9 % 16 | 8 : 1e12; % mv r7, #0x0012 % 17 | 9 : 5001; % add r0, #0x0001 % 18 | a : 2801; % bcs c % 19 | b : 1e12; % mv r7, #0x0012 % 20 | c : 2a01; % bpl e % 21 | d : 1e12; % mv r7, #0x0012 % 22 | e : 51ff; % add r0, #0xffff % 23 | f : 2c01; % bmi 11 % 24 | 10 : 1e12; % mv r7, #0x0012 % 25 | 11 : 21ee; % b 0 % 26 | 12 : 1e12; % mv r7, #0x0012 % 27 | END; 28 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/part5.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(5CSEMA5F31) Path("C:/Users/profb/Dropbox/UofT/Courses/ece243_19/Labs/Lab2/solutions/DE1-SoC/part5.Verilog/") File("part5.sof") MfrSpec(OpMask(1)); 8 | P ActionCode(Ign) 9 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/part5.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part5" 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/proc.vhd: -------------------------------------------------------------------------------- 1 | ... use your processor code from Part III, and add support for b{cond} 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work ( 8 | rmdir /S /Q work 9 | ) 10 | 11 | vlib work 12 | vlog -nolock ../tb/*.v 13 | if exist ../*.v ( 14 | vlog -nolock ../*.v 15 | ) 16 | if exist ../*.sv ( 17 | vlog -nolock ../*.sv 18 | ) 19 | if exist ../*.vhd ( 20 | vcom -nolock ../*.vhd 21 | ) 22 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | ) 10 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab10/design_files/DE1-SoC/part5.VHDL/sim/simfpga.vpi -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/sw_led.s: -------------------------------------------------------------------------------- 1 | .define LED_ADDRESS 0x10 2 | .define SW_ADDRESS 0x30 3 | 4 | // Read SW switches and display on LEDs 5 | mvt r3, #LED_ADDRESS // point to LED port 6 | mvt r4, #SW_ADDRESS // point to SW port 7 | MAIN: ld r0, [r4] // read SW values 8 | st r0, [r3] // light up LEDs 9 | mv pc, #MAIN 10 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE1-SoC/part5.VHDL/top.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_unsigned.all; 4 | 5 | ENTITY Top IS 6 | PORT ( 7 | CLOCK_50 : IN STD_LOGIC; -- DE-series 50 MHz clock signal 8 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); -- DE-series switches 9 | KEY : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); -- DE-series pushbuttons 10 | HEX0 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); -- DE-series HEX displays 11 | HEX1 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 12 | HEX2 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 13 | HEX3 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 14 | HEX4 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 15 | HEX5 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 16 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) -- DE-series LEDs 17 | ); 18 | END Top; 19 | 20 | ARCHITECTURE Behavior OF Top IS 21 | COMPONENT part5 22 | PORT ( 23 | KEY : IN STD_LOGIC_VECTOR( 0 DOWNTO 0); 24 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); 25 | CLOCK_50 : IN STD_LOGIC; 26 | HEX0 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 27 | HEX1 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 28 | HEX2 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 29 | HEX3 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 30 | HEX4 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 31 | HEX5 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 32 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) 33 | ); 34 | END COMPONENT; 35 | BEGIN 36 | 37 | U1: part5 PORT MAP (KEY(0 DOWNTO 0), SW, CLOCK_50, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); 38 | 39 | END Behavior; 40 | 41 | 42 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Lite/part3.VHDL/part3.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Lite/part4.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Lite/part4.VHDL/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Lite/part5.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Lite/part5.VHDL/part5.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part5" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Standard/part3.VHDL/part3.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSXFC6D6F31) Path("C:/Users/profb/Dropbox/U_Program/Laboratory_Exercises/Digital_Logic/vhdl/Exercise10/solutions/DE10-Standard/part3.VHDL/") File("part3.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Standard/part3.VHDL/part3.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Standard/part4.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Standard/part4.VHDL/part4.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSXFC6D6F31) Path("C:/Users/profb/Dropbox/U_Program/Laboratory_Exercises/Digital_Logic/vhdl/Exercise10/solutions/DE10-Standard/part4.VHDL/") File("part4.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Standard/part4.VHDL/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Standard/part5.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Standard/part5.VHDL/part5.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSXFC6D6F31) Path("C:/Users/profb/Dropbox/U_Program/Laboratory_Exercises/Digital_Logic/vhdl/Exercise10/solutions/DE10-Standard/part5.VHDL/") File("part5.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE10-Standard/part5.VHDL/part5.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part5" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE2-115/part3.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE2-115/part3.VHDL/part3.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part3" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE2-115/part4.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE2-115/part4.VHDL/part4.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part4" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE2-115/part5.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab10/design_files/DE2-115/part5.VHDL/part5.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part5" 24 | -------------------------------------------------------------------------------- /vhdl/lab10/doc/figures/figure12_F.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab10/doc/figures/figure12_F.pdf -------------------------------------------------------------------------------- /vhdl/lab10/doc/figures/figure13.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab10/doc/figures/figure13.pdf -------------------------------------------------------------------------------- /vhdl/lab10/doc/figures/figure14.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab10/doc/figures/figure14.pdf -------------------------------------------------------------------------------- /vhdl/lab10/doc/figures/part3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab10/doc/figures/part3.png -------------------------------------------------------------------------------- /vhdl/lab10/doc/figures/part5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab10/doc/figures/part5.png -------------------------------------------------------------------------------- /vhdl/lab11/design_files/barrel/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | 10 | # in case Quartus generated an "empty black box" file for the memory, delete it 11 | if {[file exists ../inst_mem_bb.vhd]} { 12 | file delete ../inst_mem_bb.vhd 13 | } 14 | 15 | if {[file exists work]} { 16 | file delete -force work 17 | } 18 | 19 | # create the default "work" library 20 | vlib work; 21 | 22 | # compile the VHDL source code in the parent folder 23 | vcom -2008 -nolock ../*.vhd 24 | # compile the VHDL code of the testbench 25 | vcom -2008 -nolock *.vht 26 | # compile any Verilog code 27 | vlog -nolock ../*.v 28 | # start the Simulator 29 | vsim work.testbench -Lf 220model -Lf altera_mf 30 | # show waveforms specified in wave.do 31 | do wave.do 32 | 33 | # suppress annoying VHDL warnings 34 | set StdArithNoWarnings 1 35 | set NumericStdNoWarnings 1 36 | 37 | # advance the simulation the desired amount of time 38 | run 20000 ns 39 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/barrel/Simulator/testbench.vht: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_signed.all; 4 | 5 | ENTITY testbench IS 6 | END testbench; 7 | 8 | ARCHITECTURE Behavior OF testbench IS 9 | COMPONENT top 10 | PORT ( shift_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 11 | A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 12 | BusWires : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 13 | B : OUT STD_LOGIC_VECTOR(16 DOWNTO 0) ); 14 | END COMPONENT; 15 | 16 | SIGNAL shift_type : STD_LOGIC_VECTOR(1 DOWNTO 0); 17 | SIGNAL A : STD_LOGIC_VECTOR(15 DOWNTO 0); 18 | SIGNAL BusWires : STD_LOGIC_VECTOR(3 DOWNTO 0); 19 | SIGNAL B : STD_LOGIC_VECTOR (16 DOWNTO 0); 20 | -- shift types 21 | CONSTANT lsl : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; 22 | CONSTANT lsr : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; 23 | CONSTANT asr : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; 24 | CONSTANT rotate : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; 25 | 26 | BEGIN 27 | main_process: PROCESS 28 | BEGIN 29 | shift_type <= lsl; A <= "1111000011110000"; BusWires <= "0000"; 30 | WAIT FOR 20 ns; 31 | BusWires <= "0001"; 32 | WAIT FOR 20 ns; 33 | shift_type <= lsr; 34 | WAIT FOR 20 ns; 35 | shift_type <= lsr; BusWires <= "0100"; 36 | WAIT FOR 20 ns; 37 | shift_type <= lsr; 38 | WAIT FOR 20 ns; 39 | shift_type <= asr; BusWires <= "0000"; 40 | WAIT FOR 20 ns; 41 | BusWires <= "0100"; 42 | WAIT FOR 20 ns; 43 | shift_type <= rotate; BusWires <= "0000"; 44 | WAIT FOR 20 ns; 45 | BusWires <= "0100"; 46 | WAIT FOR 20 ns; 47 | BusWires <= "1000"; 48 | WAIT FOR 20 ns; 49 | WAIT; 50 | END PROCESS; 51 | 52 | U1: top PORT MAP (shift_type, A, BusWires, B); 53 | END; 54 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/barrel/Simulator/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -label shift_type /testbench/U1/shift_type 4 | add wave -noupdate -label A -radix hexadecimal /testbench/U1/A 5 | add wave -noupdate -label BusWires -radix hexadecimal /testbench/U1/BusWires 6 | add wave -noupdate -label B -radix hexadecimal /testbench/U1/B 7 | TreeUpdate [SetDefaultTree] 8 | WaveRestoreCursors {{Cursor 1} {350000 ps} 0} 9 | quietly wave cursor active 1 10 | configure wave -namecolwidth 99 11 | configure wave -valuecolwidth 64 12 | configure wave -justifyvalue left 13 | configure wave -signalnamewidth 0 14 | configure wave -snapdistance 10 15 | configure wave -datasetprefix 0 16 | configure wave -rowmargin 4 17 | configure wave -childrowmargin 2 18 | configure wave -gridoffset 0 19 | configure wave -gridperiod 1 20 | configure wave -griddelta 40 21 | configure wave -timeline 0 22 | configure wave -timelineunits ns 23 | update 24 | WaveRestoreZoom {19681420 ps} {20016768 ps} 25 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/barrel/barrel.v: -------------------------------------------------------------------------------- 1 | // This module specifies a barrel shifter that can perform lsl, lsr, asr, and ror 2 | module barrel (shift_type, shift, data_in, data_out); 3 | input wire [1:0] shift_type; 4 | input wire [3:0] shift; 5 | input wire [15:0] data_in; 6 | output reg [16:0] data_out; 7 | 8 | parameter lsl = 2'b00, lsr = 2'b01, asr = 2'b10, ror = 2'b11; 9 | 10 | always @(*) 11 | if (shift_type == lsl) 12 | data_out = {1'b0, data_in} << shift; 13 | else if (shift_type == lsr) 14 | data_out = {1'b0, data_in} >> shift; 15 | else if (shift_type == asr) 16 | data_out = {{16{data_in[15]}},data_in} >> shift; // sign extend 17 | else // ror 18 | data_out = ({1'b0, data_in} >> shift) | ({1'b0, data_in} << (16 - shift)); 19 | endmodule 20 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/barrel/top.vhd: -------------------------------------------------------------------------------- 1 | -- This top-level file shows you how to instantiate the barrel shift Verilog module 2 | -- in your processor VHDL code. In this example, shift_type would be extracted from 3 | -- the machine code of the shift instruction currently being executed in the processor. 4 | -- It would be either 00 (lsl), 01 (lsr), 10 (asr), or 11 (ror). The signal A represents 5 | -- the content of register A in the ALU (the first operand of a shift instruction). The 6 | -- signal BusWires represents Op2 of the shift instruction (which would be on the 7 | -- processor's BusWires(3 DOWNTO 0). Finally, B represents the output of the barrel 8 | -- shifter, which would be the output of your ALU (that gets loaded into register G) 9 | -- when executing a shift instruction. 10 | 11 | -- Note: the testbench.tcl script for this example, in the Simulator folder, compiles 12 | -- both the VHDL and Verilog code included in this example. 13 | 14 | LIBRARY ieee; 15 | USE ieee.std_logic_1164.all; 16 | 17 | ENTITY top IS 18 | PORT ( shift_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 19 | A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 20 | BusWires : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 21 | B : OUT STD_LOGIC_VECTOR(16 DOWNTO 0) ); 22 | END top; 23 | 24 | ARCHITECTURE Behavior OF top IS 25 | COMPONENT barrel 26 | PORT ( shift_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 27 | shift : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 28 | data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 29 | data_out : OUT STD_LOGIC_VECTOR(16 DOWNTO 0)); 30 | END COMPONENT; 31 | BEGIN 32 | 33 | ALUshift: barrel PORT MAP (shift_type, BusWires(3 DOWNTO 0), A, B); 34 | 35 | END Behavior; 36 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/figure_26.s: -------------------------------------------------------------------------------- 1 | START: mvt sp, #0x10 // sp = 0x1000 = 4096 2 | mv r4, =0x0F0F 3 | push r4 4 | bl SUBR 5 | pop r4 6 | END: b END 7 | 8 | SUBR: sub r4, r4 9 | mv pc, lr 10 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/figure_28.s: -------------------------------------------------------------------------------- 1 | START: mv r0, #4 2 | mv r4, =0x0F0F 3 | lsl r4, #1 // lsl with Op2 = #D 4 | lsr r4, #1 // lsr with Op2 = #D 5 | lsl r4, r0 // lsl with Op2 = rY 6 | asr r4, #1 // asr with Op2 = #D 7 | ror r4, r0 // ror with Op2 = rY 8 | END: b END 9 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/Readme.txt: -------------------------------------------------------------------------------- 1 | The files part8.qsf and part8.cdf are suitable for the DE1-SoC board. If you 2 | are using a different board, then these files should be changed as needed. 3 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | 10 | # in case Quartus generated an "empty black box" file for the memory, delete it 11 | if {[file exists ../inst_mem_bb.vhd]} { 12 | file delete ../inst_mem_bb.vhd 13 | } 14 | 15 | if {[file exists work]} { 16 | file delete -force work 17 | } 18 | 19 | # create the default "work" library 20 | vlib work; 21 | 22 | # compile the VHDL source code in the parent folder 23 | vcom -2008 -nolock ../*.vhd 24 | # compile the VHDL code of the testbench 25 | vcom -2008 -nolock *.vht 26 | # compile any Verilog code 27 | vlog -nolock ../*.v 28 | # start the Simulator 29 | vsim work.testbench -Lf 220model -Lf altera_mf 30 | # show waveforms specified in wave.do 31 | do wave.do 32 | 33 | # suppress annoying VHDL warnings 34 | set StdArithNoWarnings 1 35 | set NumericStdNoWarnings 1 36 | 37 | # advance the simulation the desired amount of time 38 | run 20000 ns 39 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/Simulator/testbench.vht: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_signed.all; 4 | 5 | ENTITY testbench IS 6 | END testbench; 7 | 8 | ARCHITECTURE Behavior OF testbench IS 9 | COMPONENT part8 10 | PORT ( KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 11 | SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 12 | CLOCK_50 : IN STD_LOGIC; 13 | HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); 14 | LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); 15 | END COMPONENT; 16 | 17 | SIGNAL CLOCK_50 : STD_LOGIC; 18 | SIGNAL SW : STD_LOGIC_VECTOR(9 DOWNTO 0); 19 | SIGNAL KEY : STD_LOGIC_VECTOR(0 DOWNTO 0); 20 | SIGNAL HEX5, HEX4, HEX3, HEX2, HEX1, HEX0 : STD_LOGIC_VECTOR(6 DOWNTO 0); 21 | SIGNAL LEDR : STD_LOGIC_VECTOR(9 DOWNTO 0); 22 | CONSTANT clock_period : time := 20 ns; 23 | 24 | BEGIN 25 | clock_process: PROCESS 26 | BEGIN 27 | CLOCK_50 <= '0'; 28 | WAIT FOR clock_period / 2; 29 | CLOCK_50 <= '1'; 30 | WAIT FOR clock_period / 2; 31 | END PROCESS; 32 | 33 | KEY_process: PROCESS 34 | BEGIN 35 | KEY <= "0"; 36 | WAIT FOR 20 ns; -- perform reset 37 | KEY <= "1"; 38 | WAIT; 39 | END PROCESS; 40 | 41 | SW_process: PROCESS 42 | BEGIN 43 | SW <= "0000000000"; 44 | WAIT FOR 40 ns; 45 | SW <= "1000000001"; 46 | WAIT; 47 | END PROCESS; 48 | 49 | U1: part8 PORT MAP (KEY, SW, CLOCK_50, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR); 50 | END; 51 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/flipflop.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | 4 | ENTITY flipflop IS 5 | PORT ( D, Resetn, Clock : IN STD_LOGIC; 6 | Q : OUT STD_LOGIC); 7 | END flipflop; 8 | 9 | ARCHITECTURE Behavior OF flipflop IS 10 | BEGIN 11 | PROCESS (Clock) 12 | BEGIN 13 | IF (Clock'EVENT AND Clock = '1') THEN 14 | IF (Resetn = '0') THEN 15 | Q <= '0'; 16 | ELSE 17 | Q <= D; 18 | END IF; 19 | END IF; 20 | END PROCESS; 21 | END Behavior; 22 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/part8.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part8" 2 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/proc.vhd: -------------------------------------------------------------------------------- 1 | 2 | ... put your processor code here 3 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/regn.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | 4 | ENTITY regn IS 5 | GENERIC ( n : INTEGER := 16); 6 | PORT ( R : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); 7 | Resetn, E, Clock : IN STD_LOGIC; 8 | Q : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); 9 | END regn; 10 | 11 | ARCHITECTURE Behavior OF regn IS 12 | BEGIN 13 | PROCESS (Clock) 14 | BEGIN 15 | IF Clock'EVENT AND Clock = '1' THEN 16 | IF Resetn = '0' THEN 17 | Q <= (OTHERS => '0'); 18 | ELSIF E = '1' THEN 19 | Q <= R; 20 | END IF; 21 | END IF; 22 | END PROCESS; 23 | END Behavior; 24 | 25 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | 8 | rem Some editors make .vhd~ backup files. These files match *.vhd in 9 | rem .bat scripts, so rem temporarily move them before compiling 10 | if exist ..\*.vhd~ ( 11 | mkdir tmp_vhd~ 12 | copy ..\*.vhd~ tmp_vhd~ 13 | del ..\*.vhd~ 14 | ) 15 | 16 | vlib work 17 | vlog -nolock ../tb/*.v 18 | if exist ../*.v ( 19 | vlog -nolock ../*.v 20 | ) 21 | if exist ../*.sv ( 22 | vlog -nolock ../*.sv 23 | ) 24 | if exist ../*.vhd ( 25 | vcom -nolock ../*.vhd 26 | ) 27 | 28 | rem If .vhd~ backup files were removed, restore them 29 | if exist tmp_vhd~ ( 30 | copy tmp_vhd~\*.vhd~ ..\ 31 | del /q tmp_vhd~ 32 | rmdir tmp_vhd~ 33 | ) 34 | 35 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | ) 10 | -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab11/design_files/part8/sim/simfpga.vpi -------------------------------------------------------------------------------- /vhdl/lab11/design_files/part8/top.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_unsigned.all; 4 | 5 | ENTITY Top IS 6 | PORT ( 7 | CLOCK_50 : IN STD_LOGIC; -- DE-series 50 MHz clock signal 8 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); -- DE-series switches 9 | KEY : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); -- DE-series pushbuttons 10 | HEX0 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); -- DE-series HEX displays 11 | HEX1 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 12 | HEX2 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 13 | HEX3 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 14 | HEX4 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 15 | HEX5 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 16 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) -- DE-series LEDs 17 | ); 18 | END Top; 19 | 20 | ARCHITECTURE Behavior OF Top IS 21 | COMPONENT part8 22 | PORT ( 23 | KEY : IN STD_LOGIC_VECTOR( 0 DOWNTO 0); 24 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); 25 | CLOCK_50 : IN STD_LOGIC; 26 | HEX0 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 27 | HEX1 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 28 | HEX2 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 29 | HEX3 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 30 | HEX4 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 31 | HEX5 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 32 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) 33 | ); 34 | END COMPONENT; 35 | BEGIN 36 | 37 | U1: part8 PORT MAP (KEY(0 DOWNTO 0), SW, CLOCK_50, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR); 38 | 39 | END Behavior; 40 | 41 | 42 | -------------------------------------------------------------------------------- /vhdl/lab11/doc/figures/bl_pop.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab11/doc/figures/bl_pop.png -------------------------------------------------------------------------------- /vhdl/lab11/doc/figures/part3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab11/doc/figures/part3.png -------------------------------------------------------------------------------- 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process; 25 | 26 | -- signals 27 | process 28 | begin 29 | r_tb <= '1'; s_tb <= '0'; 30 | wait for 10 ns; 31 | r_tb <= '0'; 32 | wait for 20 ns; 33 | s_tb <= '1'; 34 | wait for 20 ns; 35 | s_tb <= '0'; 36 | wait for 20 ns; 37 | r_tb <= '1'; 38 | wait for 20 ns; 39 | r_tb <= '0'; 40 | wait for 60 ns; 41 | end process; 42 | end tb ; -------------------------------------------------------------------------------- /vhdl/lab3/design_files/part4/testbench.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | 5 | entity testbench is 6 | end testbench; 7 | 8 | architecture tb of testbench is 9 | constant T_clk : time := 60 ns; 10 | signal clk_tb, D_tb : std_logic; -- inputs 11 | signal Qa_tb, Qb_tb, Qc_tb : std_logic; -- outputs 12 | begin 13 | -- connecting testbench signals 14 | UUT : entity work.part4 port map ( Clk => clk_tb, D => D_tb, Qa => Qa_tb, Qb => Qb_tb, Qc => Qc_tb ); 15 | 16 | -- continuous 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/vhdl/lab8/design_files/testbench.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | 5 | entity testbench is 6 | end testbench; 7 | 8 | architecture tb of testbench is 9 | constant T_clk : time := 10 ns; 10 | signal clk_tb, wren_tb : std_logic; -- inputs 11 | signal addr_tb : std_logic_vector(4 downto 0); 12 | signal din_tb : std_logic_vector(3 downto 0); 13 | signal dout_tb : std_logic_vector(3 downto 0); -- outputs 14 | begin 15 | -- connecting testbench signals 16 | UUT : entity work.part1 port map ( Clock => clk_tb, Write => wren_tb, DataIn => din_tb, Address => addr_tb, DataOut => dout_tb ); 17 | 18 | -- continuous clock 19 | 20 | process 21 | begin 22 | clk_tb <= '0'; 23 | wait for T_clk/2; 24 | clk_tb <= '1'; 25 | wait for T_clk/2; 26 | end process; 27 | 28 | -- signals 29 | process 30 | begin 31 | addr_tb <= "00000"; din_tb <= "0000"; wren_tb <= '0'; 32 | wait for 20 ns; 33 | din_tb <= "1010"; wren_tb <= '1'; 34 | wait for 10 ns; 35 | din_tb <= "0000"; wren_tb <= '0'; 36 | wait for 10 ns; 37 | addr_tb <= "11111"; din_tb <= "0101"; wren_tb <= '1'; 38 | wait for 10 ns; 39 | addr_tb <= "00000"; din_tb <= "0000"; wren_tb <= '0'; 40 | wait for 10 ns; 41 | addr_tb <= "11111"; 42 | wait for 50 ns; 43 | end process; 44 | end tb ; -------------------------------------------------------------------------------- /vhdl/lab8/doc/figures/figure1.fm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab8/doc/figures/figure1.fm -------------------------------------------------------------------------------- /vhdl/lab8/doc/figures/figure1.pdf: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE0-CV/part1.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE0-CV/part2.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE0-CV/part2.VHDL/part2.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part2" 24 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part1.VHDL/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # create the default "work" library 5 | vlib work; 6 | 7 | # compile the VHDL source code in the parent folder 8 | vcom -nolock ../*.vhd 9 | # compile the VHDL code of the testbench 10 | vcom -nolock *.vht 11 | # start the Simulator, including some libraries that may be needed 12 | vsim work.testbench -Lf 220model -Lf altera_mf 13 | # show waveforms specified in wave.do 14 | do wave.do 15 | # advance the simulation the desired amount of time 16 | run 350 ns 17 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part1.VHDL/Simulator/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -label Resetn /testbench/Resetn 4 | add wave -noupdate -label CLOCK_50 /testbench/CLOCK_50 5 | add wave -noupdate -label Run /testbench/Run 6 | add wave -noupdate -label Instruction -radix hexadecimal /testbench/Instruction 7 | add wave -noupdate -divider proc 8 | add wave -noupdate -label Resetn /testbench/U1/Resetn 9 | add wave -noupdate -label Clock /testbench/U1/Clock 10 | add wave -noupdate -label Run /testbench/U1/Run 11 | add wave -noupdate -label DIN -radix hexadecimal /testbench/U1/DIN 12 | add wave -noupdate -label Done /testbench/U1/Done 13 | add wave -noupdate -label IR -radix hexadecimal /testbench/U1/IR 14 | add wave -noupdate -label Tstep_Q /testbench/U1/Tstep_Q 15 | add wave -noupdate -label r0 -radix hexadecimal /testbench/U1/r0 16 | add wave -noupdate -label r1 -radix hexadecimal /testbench/U1/r1 17 | add wave -noupdate -label A -radix hexadecimal /testbench/U1/A 18 | add wave -noupdate -label G -radix hexadecimal /testbench/U1/G 19 | add wave -noupdate -label Sel /testbench/U1/Sel 20 | add wave -noupdate -label BusWires -radix hexadecimal /testbench/U1/BusWires 21 | TreeUpdate [SetDefaultTree] 22 | WaveRestoreCursors {{Cursor 1} {30000 ps} 0} 23 | quietly wave cursor active 1 24 | configure wave -namecolwidth 98 25 | configure wave -valuecolwidth 40 26 | configure wave -justifyvalue left 27 | configure wave -signalnamewidth 0 28 | configure wave -snapdistance 10 29 | configure wave -datasetprefix 0 30 | configure wave -rowmargin 4 31 | configure wave -childrowmargin 2 32 | configure wave -gridoffset 0 33 | configure wave -gridperiod 1 34 | configure wave -griddelta 40 35 | configure wave -timeline 0 36 | configure wave -timelineunits ns 37 | update 38 | WaveRestoreZoom {0 ps} {261194 ps} 39 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/Simulator/testbench.tcl: -------------------------------------------------------------------------------- 1 | # stop any simulation that is currently running 2 | quit -sim 3 | 4 | # if simulating with a MIF file, copy it to the working folder. Assumes inst_mem.mif 5 | if {[file exists ../inst_mem.mif]} { 6 | file delete inst_mem.mif 7 | file copy ../inst_mem.mif . 8 | } 9 | # in case Quartus generated an "empty black box" file for the memory, delete it 10 | if {[file exists ../inst_mem_bb.vhd]} { 11 | file delete ../inst_mem_bb.vhd 12 | } 13 | 14 | 15 | # create the default "work" library 16 | vlib work; 17 | 18 | # compile the VHDL source code in the parent folder 19 | vcom -nolock ../*.vhd 20 | # compile the VHDL code of the testbench 21 | vcom -nolock *.vht 22 | # start the Simulator, including some libraries that may be needed 23 | vsim work.testbench -Lf 220model -Lf altera_mf 24 | # show waveforms specified in wave.do 25 | do wave.do 26 | # advance the simulation the desired amount of time 27 | run 400 ns 28 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/Simulator/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -label KEY /testbench/KEY 4 | add wave -noupdate -label SW /testbench/SW 5 | add wave -noupdate -label counter -radix hexadecimal /testbench/U1/U3/Q 6 | add wave -noupdate -label MClock /testbench/U1/U3/Clock 7 | add wave -noupdate -divider proc 8 | add wave -noupdate -label PClock /testbench/U1/U1/Clock 9 | add wave -noupdate -label Resetn /testbench/U1/U1/Resetn 10 | add wave -noupdate -label Run /testbench/U1/U1/Run 11 | add wave -noupdate -label IR -radix hexadecimal /testbench/U1/U1/IR 12 | add wave -noupdate -label Done /testbench/U1/U1/Done 13 | add wave -noupdate -label inst_mem -radix hexadecimal /testbench/U1/U2/q 14 | add wave -noupdate -label FSM /testbench/U1/U1/Tstep_Q 15 | add wave -noupdate -label R0 -radix hexadecimal /testbench/U1/U1/R0 16 | add wave -noupdate -label R1 -radix hexadecimal /testbench/U1/U1/R1 17 | TreeUpdate [SetDefaultTree] 18 | WaveRestoreCursors {{Cursor 1} {70000 ps} 0} 19 | quietly wave cursor active 1 20 | configure wave -namecolwidth 92 21 | configure wave -valuecolwidth 66 22 | configure wave -justifyvalue left 23 | configure wave -signalnamewidth 0 24 | configure wave -snapdistance 10 25 | configure wave -datasetprefix 0 26 | configure wave -rowmargin 4 27 | configure wave -childrowmargin 2 28 | configure wave -gridoffset 0 29 | configure wave -gridperiod 1 30 | configure wave -griddelta 40 31 | configure wave -timeline 0 32 | configure wave -timelineunits ns 33 | update 34 | WaveRestoreZoom {25326 ps} {325326 ps} 35 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/inst_mem.mif: -------------------------------------------------------------------------------- 1 | DEPTH = 32; 2 | WIDTH = 16; 3 | ADDRESS_RADIX = HEX; 4 | DATA_RADIX = BIN; 5 | CONTENT 6 | BEGIN 7 | 00 : 0001000000011100; % mv r0, #28 % 8 | 01 : 0011001011111111; % mvt r1, #0xFF % 9 | 02 : 0101001011111111; % add r1, #0xFF % 10 | 03 : 0110001000000000; % sub r1, r0 % 11 | 04 : 0101001000000001; % add r1, #1 % 12 | 05 : 0000000000000000; 13 | 06 : 0000000000000000; 14 | 07 : 0000000000000000; 15 | 08 : 0000000000000000; 16 | 09 : 0000000000000000; 17 | 0A : 0000000000000000; 18 | 0B : 0000000000000000; 19 | 0C : 0000000000000000; 20 | 0D : 0000000000000000; 21 | 0E : 0000000000000000; 22 | 0F : 0000000000000000; 23 | 10 : 0000000000000000; 24 | 11 : 0000000000000000; 25 | 12 : 0000000000000000; 26 | 13 : 0000000000000000; 27 | 14 : 0000000000000000; 28 | 15 : 0000000000000000; 29 | 16 : 0000000000000000; 30 | 17 : 0000000000000000; 31 | 18 : 0000000000000000; 32 | 19 : 0000000000000000; 33 | 1A : 0000000000000000; 34 | 1B : 0000000000000000; 35 | 1C : 0000000000000000; 36 | 1D : 0000000000000000; 37 | 1E : 0000000000000000; 38 | 1F : 0000000000000000; 39 | END; 40 | 41 | 42 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/part2.qpf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2005 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | 17 | QUARTUS_VERSION = "5.0" 18 | DATE = "19:53:00 July 09, 2005" 19 | 20 | 21 | # Revisions 22 | 23 | PROJECT_REVISION = "part2" 24 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/proc.vhd: -------------------------------------------------------------------------------- 1 | -- use your processor from Part 1 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/sim/run_compile.bat: -------------------------------------------------------------------------------- 1 | if exist ..\inst_mem.mif ( 2 | copy /Y ..\inst_mem.mif . 3 | ) 4 | if exist ..\inst_mem_bb.v ( 5 | del ..\inst_mem_bb.v 6 | ) 7 | if exist work rmdir /S /Q work 8 | 9 | vlib work 10 | vlog -nolock ../tb/*.v 11 | if exist ../*.v ( 12 | vlog -nolock ../*.v 13 | ) 14 | if exist ../*.sv ( 15 | vlog -nolock ../*.sv 16 | ) 17 | if exist ../*.vhd ( 18 | vcom -nolock ../*.vhd 19 | ) 20 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/sim/run_sim.bat: -------------------------------------------------------------------------------- 1 | if exist ../top.v ( 2 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 3 | ) 4 | if exist ../top.sv ( 5 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf_ver -Lf verilog -c -do "run -all" tb 6 | ) 7 | if exist ../top.vhd ( 8 | vsim -pli simfpga.vpi -Lf 220model -Lf altera_mf -t 1ns -c -do "set StdArithNoWarnings 1" -do "set NumericStdNoWarnings 1" -do "run -all" tb 9 | ) 10 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/sim/simfpga.vpi: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/design_files/DE1-SoC/part2.VHDL/sim/simfpga.vpi -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE1-SoC/part2.VHDL/top.vhd: -------------------------------------------------------------------------------- 1 | LIBRARY ieee; 2 | USE ieee.std_logic_1164.all; 3 | USE ieee.std_logic_unsigned.all; 4 | 5 | ENTITY Top IS 6 | PORT ( 7 | CLOCK_50 : IN STD_LOGIC; -- DE-series 50 MHz clock signal 8 | KEY : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); -- DE-series pushbuttons 9 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); -- DE-series switches 10 | HEX0 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); -- DE-series HEX displays 11 | HEX1 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 12 | HEX2 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 13 | HEX3 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 14 | HEX4 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 15 | HEX5 : OUT STD_LOGIC_VECTOR( 6 DOWNTO 0); 16 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) -- DE-series LEDs 17 | ); 18 | END Top; 19 | 20 | ARCHITECTURE Behavior OF Top IS 21 | COMPONENT part2 22 | PORT ( 23 | KEY : IN STD_LOGIC_VECTOR( 1 DOWNTO 0); 24 | SW : IN STD_LOGIC_VECTOR( 9 DOWNTO 0); 25 | LEDR : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0) 26 | ); 27 | END COMPONENT; 28 | BEGIN 29 | 30 | U1: part2 PORT MAP (KEY(1 DOWNTO 0), SW, LEDR); 31 | HEX0 <= "1111111"; 32 | HEX1 <= "1111111"; 33 | HEX2 <= "1111111"; 34 | HEX3 <= "1111111"; 35 | HEX4 <= "1111111"; 36 | HEX5 <= "1111111"; 37 | 38 | END Behavior; 39 | 40 | 41 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE10-Lite/part1.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | see ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE10-Lite/part2.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | see ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE10-Lite/part2.VHDL/part2.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part2" 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE10-Standard/part1.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | see ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE10-Standard/part2.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | see ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE10-Standard/part2.VHDL/part2.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Ign) 7 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 8 | P ActionCode(Cfg) 9 | Device PartName(5CSXFC6D6F31) Path("C:/Users/brownste/Dropbox/U_Program/Laboratory_Exercises/Digital_Logic/vhdl/Exercise9/solutions/DE10-Standard/part2.VHDL/") File("part2.sof") MfrSpec(OpMask(1)); 10 | 11 | ChainEnd; 12 | 13 | AlteraBegin; 14 | ChainType(JTAG); 15 | AlteraEnd; 16 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE10-Standard/part2.VHDL/part2.qpf: -------------------------------------------------------------------------------- 1 | PROJECT_REVISION = "part2" 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE2-115/part1.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE2-115/part2.VHDL/Readme.txt: -------------------------------------------------------------------------------- 1 | See ../DE1-SoC for source files 2 | -------------------------------------------------------------------------------- /vhdl/lab9/design_files/DE2-115/part2.VHDL/part2.qpf: -------------------------------------------------------------------------------- 1 | # Revisions 2 | 3 | PROJECT_REVISION = "part2" 4 | -------------------------------------------------------------------------------- /vhdl/lab9/doc/figures/figure1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/doc/figures/figure1.pdf -------------------------------------------------------------------------------- /vhdl/lab9/doc/figures/figure3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/doc/figures/figure3.png -------------------------------------------------------------------------------- /vhdl/lab9/doc/figures/figure4.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/doc/figures/figure4.pdf -------------------------------------------------------------------------------- /vhdl/lab9/doc/figures/figure7.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/doc/figures/figure7.png -------------------------------------------------------------------------------- /vhdl/lab9/doc/figures/figure8.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/doc/figures/figure8.png -------------------------------------------------------------------------------- /vhdl/lab9/doc/figures/figure9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/doc/figures/figure9.png -------------------------------------------------------------------------------- /vhdl/lab9/doc/figures/figure_ROM.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/doc/figures/figure_ROM.pdf -------------------------------------------------------------------------------- /vhdl/lab9/doc/figures/figuresim2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgacademy/Lab_Exercises_Digital_Logic/a2bf4e4ae48e7313d38e9e75aa822e586f279b96/vhdl/lab9/doc/figures/figuresim2.png --------------------------------------------------------------------------------