├── .github └── workflows │ └── regression-tests.yml ├── .gitignore ├── .readthedocs.yaml ├── .test_durations ├── AUTHORS ├── LICENSE ├── README.md ├── docs ├── Makefile ├── make.bat ├── requirements.txt └── source │ ├── conf.py │ ├── contents.rst │ ├── glossary.rst │ └── index.rst ├── src ├── axi │ ├── lib │ │ └── taxi │ ├── rtl │ │ ├── taxi_axi_if.sv │ │ ├── taxi_axi_ram.sv │ │ ├── taxi_axi_register.f │ │ ├── taxi_axi_register.sv │ │ ├── taxi_axi_register_rd.sv │ │ ├── taxi_axi_register_wr.sv │ │ ├── taxi_axil_dp_ram.sv │ │ ├── taxi_axil_if.sv │ │ ├── taxi_axil_ram.sv │ │ ├── taxi_axil_register.f │ │ ├── taxi_axil_register.sv │ │ ├── taxi_axil_register_rd.sv │ │ └── taxi_axil_register_wr.sv │ └── tb │ │ ├── taxi_axi_ram │ │ ├── Makefile │ │ ├── test_taxi_axi_ram.py │ │ └── test_taxi_axi_ram.sv │ │ ├── taxi_axi_register │ │ ├── Makefile │ │ ├── test_taxi_axi_register.py │ │ └── test_taxi_axi_register.sv │ │ ├── taxi_axil_dp_ram │ │ ├── Makefile │ │ ├── test_taxi_axil_dp_ram.py │ │ └── test_taxi_axil_dp_ram.sv │ │ ├── taxi_axil_ram │ │ ├── Makefile │ │ ├── test_taxi_axil_ram.py │ │ └── test_taxi_axil_ram.sv │ │ └── taxi_axil_register │ │ ├── Makefile │ │ ├── test_taxi_axil_register.py │ │ └── test_taxi_axil_register.sv ├── axis │ ├── lib │ │ └── taxi │ ├── rtl │ │ ├── taxi_axis_adapter.sv │ │ ├── taxi_axis_arb_mux.f │ │ ├── taxi_axis_arb_mux.sv │ │ ├── taxi_axis_async_fifo.f │ │ ├── taxi_axis_async_fifo.sv │ │ ├── taxi_axis_async_fifo_adapter.f │ │ ├── taxi_axis_async_fifo_adapter.sv │ │ ├── taxi_axis_broadcast.sv │ │ ├── taxi_axis_cobs_decode.sv │ │ ├── taxi_axis_cobs_encode.f │ │ ├── taxi_axis_cobs_encode.sv │ │ ├── taxi_axis_fifo.sv │ │ ├── taxi_axis_fifo_adapter.f │ │ ├── taxi_axis_fifo_adapter.sv │ │ ├── taxi_axis_if.sv │ │ ├── taxi_axis_mux.sv │ │ ├── taxi_axis_pipeline_fifo.sv │ │ ├── taxi_axis_pipeline_register.f │ │ ├── taxi_axis_pipeline_register.sv │ │ └── taxi_axis_register.sv │ ├── syn │ │ └── vivado │ │ │ └── taxi_axis_async_fifo.tcl │ └── tb │ │ ├── taxi_axis_adapter │ │ ├── Makefile │ │ ├── test_taxi_axis_adapter.py │ │ └── test_taxi_axis_adapter.sv │ │ ├── taxi_axis_arb_mux │ │ ├── Makefile │ │ ├── test_taxi_axis_arb_mux.py │ │ └── test_taxi_axis_arb_mux.sv │ │ ├── taxi_axis_async_fifo │ │ ├── Makefile │ │ ├── test_taxi_axis_async_fifo.py │ │ └── test_taxi_axis_async_fifo.sv │ │ ├── taxi_axis_async_fifo_adapter │ │ ├── Makefile │ │ ├── test_taxi_axis_async_fifo_adapter.py │ │ └── test_taxi_axis_async_fifo_adapter.sv │ │ ├── taxi_axis_broadcast │ │ ├── Makefile │ │ ├── test_taxi_axis_broadcast.py │ │ └── test_taxi_axis_broadcast.sv │ │ ├── taxi_axis_cobs_decode │ │ ├── Makefile │ │ ├── test_taxi_axis_cobs_decode.py │ │ └── test_taxi_axis_cobs_decode.sv │ │ ├── taxi_axis_cobs_encode │ │ ├── Makefile │ │ ├── test_taxi_axis_cobs_encode.py │ │ └── test_taxi_axis_cobs_encode.sv │ │ ├── taxi_axis_fifo │ │ ├── Makefile │ │ ├── test_taxi_axis_fifo.py │ │ └── test_taxi_axis_fifo.sv │ │ ├── taxi_axis_fifo_adapter │ │ ├── Makefile │ │ ├── test_taxi_axis_fifo_adapter.py │ │ └── test_taxi_axis_fifo_adapter.sv │ │ ├── taxi_axis_mux │ │ ├── Makefile │ │ ├── test_taxi_axis_mux.py │ │ └── test_taxi_axis_mux.sv │ │ ├── taxi_axis_pipeline_fifo │ │ ├── Makefile │ │ ├── test_taxi_axis_pipeline_fifo.py │ │ └── test_taxi_axis_pipeline_fifo.sv │ │ ├── taxi_axis_pipeline_register │ │ ├── Makefile │ │ ├── test_taxi_axis_pipeline_register.py │ │ └── test_taxi_axis_pipeline_register.sv │ │ └── taxi_axis_register │ │ ├── Makefile │ │ ├── test_taxi_axis_register.py │ │ └── test_taxi_axis_register.sv ├── eth │ ├── example │ │ ├── ADM_PCIE_9V3 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga │ │ │ │ └── Makefile │ │ │ │ ├── fpga_10g │ │ │ │ └── Makefile │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── Alveo │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga_AU200 │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU200_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU250 │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU250_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU280 │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU280_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU45N │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU45N_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU50 │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU50_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU55C │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU55C_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU55N │ │ │ │ └── Makefile │ │ │ │ ├── fpga_AU55N_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_VCU1525 │ │ │ │ └── Makefile │ │ │ │ ├── fpga_VCU1525_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_X3522 │ │ │ │ └── Makefile │ │ │ │ ├── fpga_X3522_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_au200.xdc │ │ │ │ ├── fpga_au280.xdc │ │ │ │ ├── fpga_au45n.xdc │ │ │ │ ├── fpga_au50.xdc │ │ │ │ ├── fpga_au55.xdc │ │ │ │ ├── fpga_x3522.xdc │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga_au200.sv │ │ │ │ ├── fpga_au280.sv │ │ │ │ ├── fpga_au45n.sv │ │ │ │ ├── fpga_au50.sv │ │ │ │ ├── fpga_au55.sv │ │ │ │ ├── fpga_core.sv │ │ │ │ └── fpga_x3522.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── Arty │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga │ │ │ │ └── Makefile │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ └── test_fpga_core.py │ │ ├── HTG940 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── eth_rgmii.xdc │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga_vu13p │ │ │ │ └── Makefile │ │ │ │ ├── fpga_vu9p │ │ │ │ └── Makefile │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ └── test_fpga_core.py │ │ ├── KC705 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── eth_gmii.xdc │ │ │ │ ├── eth_rgmii.xdc │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga_gmii_1g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── fpga_rgmii_1g │ │ │ │ ├── Makefile │ │ │ │ ├── config.tcl │ │ │ │ └── generate_bit_iodelay.tcl │ │ │ │ ├── fpga_sgmii_1g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── ip │ │ │ │ ├── basex_pcs_pma_0.tcl │ │ │ │ └── sgmii_pcs_pma_0.tcl │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ └── test_fpga_core.py │ │ ├── KCU105 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga_10g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── fpga_1g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── ip │ │ │ │ ├── basex_pcs_pma_0.tcl │ │ │ │ ├── basex_pcs_pma_1.tcl │ │ │ │ └── sgmii_pcs_pma_0.tcl │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── KR260 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── eth_rgmii.xdc │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga_10g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── fpga_1g │ │ │ │ ├── Makefile │ │ │ │ ├── config.tcl │ │ │ │ └── generate_bit_iodelay.tcl │ │ │ │ ├── ip │ │ │ │ └── basex_pcs_pma_0.tcl │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── Nexus_K3P_Q │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga │ │ │ │ └── Makefile │ │ │ │ ├── fpga_10g │ │ │ │ └── Makefile │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── Nexus_K3P_S │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga_K35 │ │ │ │ └── Makefile │ │ │ │ ├── fpga_K3P │ │ │ │ └── Makefile │ │ │ │ ├── fpga_K3P_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_k35.xdc │ │ │ │ ├── fpga_k3p.xdc │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga_core.sv │ │ │ │ ├── fpga_k35.sv │ │ │ │ └── fpga_k3p.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── VCU108 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga │ │ │ │ └── Makefile │ │ │ │ ├── fpga_10g │ │ │ │ └── Makefile │ │ │ │ ├── ip │ │ │ │ └── sgmii_pcs_pma_0.tcl │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── VCU118 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga │ │ │ │ └── Makefile │ │ │ │ ├── fpga_10g │ │ │ │ └── Makefile │ │ │ │ ├── ip │ │ │ │ └── sgmii_pcs_pma_0.tcl │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── XUPP3R │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga_XUPP3R │ │ │ │ └── Makefile │ │ │ │ ├── fpga_XUPP3R_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_XUSP3S │ │ │ │ └── Makefile │ │ │ │ ├── fpga_XUSP3S_10g │ │ │ │ └── Makefile │ │ │ │ ├── fpga_xupp3r.xdc │ │ │ │ ├── fpga_xusp3s.xdc │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga_core.sv │ │ │ │ ├── fpga_xupp3r.sv │ │ │ │ └── fpga_xusp3s.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── ZCU102 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga_10g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── fpga_1g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── ip │ │ │ │ ├── basex_pcs_pma_0.tcl │ │ │ │ └── basex_pcs_pma_1.tcl │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── ZCU106 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga_10g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── fpga_1g │ │ │ │ ├── Makefile │ │ │ │ └── config.tcl │ │ │ │ ├── ip │ │ │ │ ├── basex_pcs_pma_0.tcl │ │ │ │ └── basex_pcs_pma_1.tcl │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ ├── ZCU111 │ │ │ └── fpga │ │ │ │ ├── README.md │ │ │ │ ├── common │ │ │ │ └── vivado.mk │ │ │ │ ├── fpga.xdc │ │ │ │ ├── fpga │ │ │ │ └── Makefile │ │ │ │ ├── fpga_10g │ │ │ │ └── Makefile │ │ │ │ ├── lib │ │ │ │ └── taxi │ │ │ │ ├── rtl │ │ │ │ ├── fpga.sv │ │ │ │ └── fpga_core.sv │ │ │ │ └── tb │ │ │ │ └── fpga_core │ │ │ │ ├── Makefile │ │ │ │ ├── baser.py │ │ │ │ └── test_fpga_core.py │ │ └── fb2CG │ │ │ └── fpga │ │ │ ├── README.md │ │ │ ├── common │ │ │ └── vivado.mk │ │ │ ├── fpga.xdc │ │ │ ├── fpga │ │ │ └── Makefile │ │ │ ├── fpga_10g │ │ │ └── Makefile │ │ │ ├── lib │ │ │ └── taxi │ │ │ ├── rtl │ │ │ ├── fpga.sv │ │ │ └── fpga_core.sv │ │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ ├── baser.py │ │ │ └── test_fpga_core.py │ ├── lib │ │ └── taxi │ ├── rtl │ │ ├── taxi_axis_baser_rx_64.sv │ │ ├── taxi_axis_baser_tx_64.sv │ │ ├── taxi_axis_gmii_rx.sv │ │ ├── taxi_axis_gmii_tx.sv │ │ ├── taxi_axis_xgmii_rx_32.sv │ │ ├── taxi_axis_xgmii_rx_64.sv │ │ ├── taxi_axis_xgmii_tx_32.sv │ │ ├── taxi_axis_xgmii_tx_64.sv │ │ ├── taxi_eth_mac_10g.f │ │ ├── taxi_eth_mac_10g.sv │ │ ├── taxi_eth_mac_10g_fifo.f │ │ ├── taxi_eth_mac_10g_fifo.sv │ │ ├── taxi_eth_mac_1g.f │ │ ├── taxi_eth_mac_1g.sv │ │ ├── taxi_eth_mac_1g_fifo.f │ │ ├── taxi_eth_mac_1g_fifo.sv │ │ ├── taxi_eth_mac_1g_gmii.f │ │ ├── taxi_eth_mac_1g_gmii.sv │ │ ├── taxi_eth_mac_1g_gmii_fifo.f │ │ ├── taxi_eth_mac_1g_gmii_fifo.sv │ │ ├── taxi_eth_mac_1g_rgmii.f │ │ ├── taxi_eth_mac_1g_rgmii.sv │ │ ├── taxi_eth_mac_1g_rgmii_fifo.f │ │ ├── taxi_eth_mac_1g_rgmii_fifo.sv │ │ ├── taxi_eth_mac_mii.f │ │ ├── taxi_eth_mac_mii.sv │ │ ├── taxi_eth_mac_mii_fifo.f │ │ ├── taxi_eth_mac_mii_fifo.sv │ │ ├── taxi_eth_mac_phy_10g.f │ │ ├── taxi_eth_mac_phy_10g.sv │ │ ├── taxi_eth_mac_phy_10g_fifo.f │ │ ├── taxi_eth_mac_phy_10g_fifo.sv │ │ ├── taxi_eth_mac_phy_10g_rx.f │ │ ├── taxi_eth_mac_phy_10g_rx.sv │ │ ├── taxi_eth_mac_phy_10g_tx.f │ │ ├── taxi_eth_mac_phy_10g_tx.sv │ │ ├── taxi_eth_mac_stats.f │ │ ├── taxi_eth_mac_stats.sv │ │ ├── taxi_eth_phy_10g.f │ │ ├── taxi_eth_phy_10g.sv │ │ ├── taxi_eth_phy_10g_rx.f │ │ ├── taxi_eth_phy_10g_rx.sv │ │ ├── taxi_eth_phy_10g_rx_ber_mon.sv │ │ ├── taxi_eth_phy_10g_rx_frame_sync.sv │ │ ├── taxi_eth_phy_10g_rx_if.f │ │ ├── taxi_eth_phy_10g_rx_if.sv │ │ ├── taxi_eth_phy_10g_rx_watchdog.sv │ │ ├── taxi_eth_phy_10g_tx.f │ │ ├── taxi_eth_phy_10g_tx.sv │ │ ├── taxi_eth_phy_10g_tx_if.f │ │ ├── taxi_eth_phy_10g_tx_if.sv │ │ ├── taxi_gmii_phy_if.f │ │ ├── taxi_gmii_phy_if.sv │ │ ├── taxi_mac_ctrl_rx.sv │ │ ├── taxi_mac_ctrl_tx.sv │ │ ├── taxi_mac_pause_ctrl_rx.sv │ │ ├── taxi_mac_pause_ctrl_tx.sv │ │ ├── taxi_mii_phy_if.f │ │ ├── taxi_mii_phy_if.sv │ │ ├── taxi_rgmii_phy_if.f │ │ ├── taxi_rgmii_phy_if.sv │ │ ├── taxi_xgmii_baser_dec_64.sv │ │ ├── taxi_xgmii_baser_enc_64.sv │ │ └── us │ │ │ ├── taxi_eth_mac_25g_us.f │ │ │ ├── taxi_eth_mac_25g_us.sv │ │ │ ├── taxi_eth_mac_25g_us_ch.sv │ │ │ ├── taxi_eth_phy_25g_us_gt.f │ │ │ ├── taxi_eth_phy_25g_us_gt.sv │ │ │ ├── taxi_eth_phy_25g_us_gt_ll.f │ │ │ ├── taxi_eth_phy_25g_us_gt_ll.sv │ │ │ ├── taxi_eth_phy_25g_us_gth_10g_156.tcl │ │ │ ├── taxi_eth_phy_25g_us_gth_10g_161.tcl │ │ │ ├── taxi_eth_phy_25g_us_gth_10g_322.tcl │ │ │ ├── taxi_eth_phy_25g_us_gty_10g_156.tcl │ │ │ ├── taxi_eth_phy_25g_us_gty_10g_161.tcl │ │ │ ├── taxi_eth_phy_25g_us_gty_10g_322.tcl │ │ │ ├── taxi_eth_phy_25g_us_gty_25g_156.tcl │ │ │ ├── taxi_eth_phy_25g_us_gty_25g_161.tcl │ │ │ └── taxi_eth_phy_25g_us_gty_25g_322.tcl │ ├── syn │ │ └── vivado │ │ │ ├── taxi_eth_mac_fifo.tcl │ │ │ └── taxi_rgmii_phy_if.tcl │ └── tb │ │ ├── baser.py │ │ ├── taxi_axis_baser_rx_64 │ │ ├── Makefile │ │ ├── baser.py │ │ ├── test_taxi_axis_baser_rx_64.py │ │ └── test_taxi_axis_baser_rx_64.sv │ │ ├── taxi_axis_baser_tx_64 │ │ ├── Makefile │ │ ├── baser.py │ │ ├── test_taxi_axis_baser_tx_64.py │ │ └── test_taxi_axis_baser_tx_64.sv │ │ ├── taxi_axis_gmii_rx │ │ ├── Makefile │ │ ├── test_taxi_axis_gmii_rx.py │ │ └── test_taxi_axis_gmii_rx.sv │ │ ├── taxi_axis_gmii_tx │ │ ├── Makefile │ │ ├── test_taxi_axis_gmii_tx.py │ │ └── test_taxi_axis_gmii_tx.sv │ │ ├── taxi_axis_xgmii_rx_32 │ │ ├── Makefile │ │ ├── test_taxi_axis_xgmii_rx_32.py │ │ └── test_taxi_axis_xgmii_rx_32.sv │ │ ├── taxi_axis_xgmii_rx_64 │ │ ├── Makefile │ │ ├── test_taxi_axis_xgmii_rx_64.py │ │ └── test_taxi_axis_xgmii_rx_64.sv │ │ ├── taxi_axis_xgmii_tx_32 │ │ ├── Makefile │ │ ├── test_taxi_axis_xgmii_tx_32.py │ │ └── test_taxi_axis_xgmii_tx_32.sv │ │ ├── taxi_axis_xgmii_tx_64 │ │ ├── Makefile │ │ ├── test_taxi_axis_xgmii_tx_64.py │ │ └── test_taxi_axis_xgmii_tx_64.sv │ │ ├── taxi_eth_mac_10g │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_10g.py │ │ └── test_taxi_eth_mac_10g.sv │ │ ├── taxi_eth_mac_10g_fifo │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_10g_fifo.py │ │ └── test_taxi_eth_mac_10g_fifo.sv │ │ ├── taxi_eth_mac_1g │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_1g.py │ │ └── test_taxi_eth_mac_1g.sv │ │ ├── taxi_eth_mac_1g_fifo │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_1g_fifo.py │ │ └── test_taxi_eth_mac_1g_fifo.sv │ │ ├── taxi_eth_mac_1g_gmii │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_1g_gmii.py │ │ └── test_taxi_eth_mac_1g_gmii.sv │ │ ├── taxi_eth_mac_1g_gmii_fifo │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_1g_gmii_fifo.py │ │ └── test_taxi_eth_mac_1g_gmii_fifo.sv │ │ ├── taxi_eth_mac_1g_rgmii │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_1g_rgmii.py │ │ └── test_taxi_eth_mac_1g_rgmii.sv │ │ ├── taxi_eth_mac_1g_rgmii_fifo │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_1g_rgmii_fifo.py │ │ └── test_taxi_eth_mac_1g_rgmii_fifo.sv │ │ ├── taxi_eth_mac_mii │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_mii.py │ │ └── test_taxi_eth_mac_mii.sv │ │ ├── taxi_eth_mac_mii_fifo │ │ ├── Makefile │ │ ├── test_taxi_eth_mac_mii_fifo.py │ │ └── test_taxi_eth_mac_mii_fifo.sv │ │ ├── taxi_eth_mac_phy_10g │ │ ├── Makefile │ │ ├── baser.py │ │ ├── test_taxi_eth_mac_phy_10g.py │ │ └── test_taxi_eth_mac_phy_10g.sv │ │ ├── taxi_eth_mac_phy_10g_fifo │ │ ├── Makefile │ │ ├── baser.py │ │ ├── test_taxi_eth_mac_phy_10g_fifo.py │ │ └── test_taxi_eth_mac_phy_10g_fifo.sv │ │ ├── taxi_eth_phy_10g │ │ ├── Makefile │ │ ├── baser.py │ │ └── test_taxi_eth_phy_10g.py │ │ ├── taxi_mac_ctrl_rx │ │ ├── Makefile │ │ ├── test_taxi_mac_ctrl_rx.py │ │ └── test_taxi_mac_ctrl_rx.sv │ │ ├── taxi_mac_ctrl_tx │ │ ├── Makefile │ │ ├── test_taxi_mac_ctrl_tx.py │ │ └── test_taxi_mac_ctrl_tx.sv │ │ ├── taxi_mac_pause_ctrl_rx │ │ ├── Makefile │ │ └── test_taxi_mac_pause_ctrl_rx.py │ │ ├── taxi_mac_pause_ctrl_tx │ │ ├── Makefile │ │ └── test_taxi_mac_pause_ctrl_tx.py │ │ ├── taxi_xgmii_baser_dec_64 │ │ ├── Makefile │ │ ├── baser.py │ │ └── test_taxi_xgmii_baser_dec_64.py │ │ └── taxi_xgmii_baser_enc_64 │ │ ├── Makefile │ │ ├── baser.py │ │ └── test_taxi_xgmii_baser_enc_64.py ├── hip │ └── rtl │ │ └── us │ │ ├── taxi_gt_qpll_reset.sv │ │ ├── taxi_gt_rx_reset.sv │ │ ├── taxi_gt_tx_reset.sv │ │ └── taxi_mmcm_frac.sv ├── io │ └── rtl │ │ ├── taxi_debounce_switch.sv │ │ ├── taxi_iddr.sv │ │ ├── taxi_led_sreg.sv │ │ ├── taxi_oddr.sv │ │ ├── taxi_ssio_ddr_in.sv │ │ ├── taxi_ssio_ddr_in_diff.sv │ │ ├── taxi_ssio_ddr_out.sv │ │ ├── taxi_ssio_ddr_out_diff.sv │ │ ├── taxi_ssio_sdr_in.sv │ │ ├── taxi_ssio_sdr_in_diff.sv │ │ ├── taxi_ssio_sdr_out.sv │ │ └── taxi_ssio_sdr_out_diff.sv ├── lfsr │ ├── rtl │ │ ├── taxi_lfsr.sv │ │ ├── taxi_lfsr_crc.sv │ │ ├── taxi_lfsr_descramble.sv │ │ ├── taxi_lfsr_prbs_check.sv │ │ ├── taxi_lfsr_prbs_gen.sv │ │ └── taxi_lfsr_scramble.sv │ └── tb │ │ ├── taxi_lfsr │ │ ├── Makefile │ │ └── test_taxi_lfsr.py │ │ ├── taxi_lfsr_crc │ │ ├── Makefile │ │ └── test_taxi_lfsr_crc.py │ │ ├── taxi_lfsr_descramble │ │ ├── Makefile │ │ └── test_taxi_lfsr_descramble.py │ │ ├── taxi_lfsr_prbs_check │ │ ├── Makefile │ │ └── test_taxi_lfsr_prbs_check.py │ │ ├── taxi_lfsr_prbs_gen │ │ ├── Makefile │ │ └── test_taxi_lfsr_prbs_gen.py │ │ └── taxi_lfsr_scramble │ │ ├── Makefile │ │ └── test_taxi_lfsr_scramble.py ├── lss │ ├── lib │ │ └── taxi │ ├── rtl │ │ ├── taxi_i2c_master.sv │ │ ├── taxi_i2c_single_reg.sv │ │ ├── taxi_mdio_master.sv │ │ ├── taxi_uart.f │ │ ├── taxi_uart.sv │ │ ├── taxi_uart_brg.sv │ │ ├── taxi_uart_rx.sv │ │ └── taxi_uart_tx.sv │ └── tb │ │ ├── taxi_i2c_master │ │ ├── Makefile │ │ ├── test_taxi_i2c_master.py │ │ └── test_taxi_i2c_master.sv │ │ ├── taxi_i2c_single_reg │ │ ├── Makefile │ │ ├── test_taxi_i2c_single_reg.py │ │ └── test_taxi_i2c_single_reg.sv │ │ └── taxi_uart │ │ ├── Makefile │ │ ├── test_taxi_uart.py │ │ └── test_taxi_uart.sv ├── pcie │ ├── lib │ │ └── taxi │ ├── rtl │ │ ├── taxi_pcie_axil_master.sv │ │ ├── taxi_pcie_axil_master_minimal.sv │ │ └── taxi_pcie_tlp_if.sv │ └── tb │ │ ├── pcie_if.py │ │ ├── taxi_pcie_axil_master │ │ ├── Makefile │ │ ├── pcie_if.py │ │ ├── test_taxi_pcie_axil_master.py │ │ └── test_taxi_pcie_axil_master.sv │ │ └── taxi_pcie_axil_master_minimal │ │ ├── Makefile │ │ ├── pcie_if.py │ │ ├── test_taxi_pcie_axil_master_minimal.py │ │ └── test_taxi_pcie_axil_master_minimal.sv ├── prim │ ├── rtl │ │ ├── taxi_arbiter.sv │ │ └── taxi_penc.sv │ └── tb │ │ ├── taxi_arbiter │ │ ├── Makefile │ │ └── test_taxi_arbiter.py │ │ └── taxi_penc │ │ ├── Makefile │ │ └── test_taxi_penc.py ├── ptp │ ├── lib │ │ └── taxi │ ├── rtl │ │ ├── taxi_ptp_clock.sv │ │ ├── taxi_ptp_clock_cdc.sv │ │ ├── taxi_ptp_perout.sv │ │ ├── taxi_ptp_td_leaf.sv │ │ ├── taxi_ptp_td_phc.sv │ │ └── taxi_ptp_td_rel2tod.sv │ ├── syn │ │ └── vivado │ │ │ ├── taxi_ptp_clock_cdc.tcl │ │ │ ├── taxi_ptp_td_leaf.tcl │ │ │ └── taxi_ptp_td_rel2tod.tcl │ └── tb │ │ ├── ptp_td.py │ │ ├── taxi_ptp_clock │ │ ├── Makefile │ │ └── test_taxi_ptp_clock.py │ │ ├── taxi_ptp_clock_cdc │ │ ├── Makefile │ │ └── test_taxi_ptp_clock_cdc.py │ │ ├── taxi_ptp_perout │ │ ├── Makefile │ │ └── test_taxi_ptp_perout.py │ │ ├── taxi_ptp_td_leaf │ │ ├── Makefile │ │ ├── ptp_td.py │ │ └── test_taxi_ptp_td_leaf.py │ │ ├── taxi_ptp_td_phc │ │ ├── Makefile │ │ ├── ptp_td.py │ │ └── test_taxi_ptp_td_phc.py │ │ └── taxi_ptp_td_rel2tod │ │ ├── Makefile │ │ ├── ptp_td.py │ │ ├── test_taxi_ptp_td_rel2tod.py │ │ └── test_taxi_ptp_td_rel2tod.sv ├── stats │ ├── lib │ │ └── taxi │ ├── rtl │ │ ├── taxi_stats_collect.sv │ │ ├── taxi_stats_counter.sv │ │ └── taxi_stats_strings_full.sv │ └── tb │ │ ├── taxi_stats_collect │ │ ├── Makefile │ │ ├── test_taxi_stats_collect.py │ │ └── test_taxi_stats_collect.sv │ │ ├── taxi_stats_counter │ │ ├── Makefile │ │ ├── test_taxi_stats_counter.py │ │ └── test_taxi_stats_counter.sv │ │ └── taxi_stats_strings_full │ │ ├── Makefile │ │ ├── test_taxi_stats_strings_full.py │ │ └── test_taxi_stats_strings_full.sv ├── sync │ ├── rtl │ │ ├── taxi_sync_reset.sv │ │ └── taxi_sync_signal.sv │ └── syn │ │ └── vivado │ │ ├── taxi_sync_reset.tcl │ │ └── taxi_sync_signal.tcl └── xfcp │ ├── lib │ └── taxi │ ├── rtl │ ├── taxi_xfcp_if_uart.f │ ├── taxi_xfcp_if_uart.sv │ ├── taxi_xfcp_mod_axi.f │ ├── taxi_xfcp_mod_axi.sv │ ├── taxi_xfcp_mod_axil.sv │ ├── taxi_xfcp_mod_i2c_master.f │ ├── taxi_xfcp_mod_i2c_master.sv │ ├── taxi_xfcp_mod_stats.f │ ├── taxi_xfcp_mod_stats.sv │ ├── taxi_xfcp_switch.f │ └── taxi_xfcp_switch.sv │ └── tb │ ├── taxi_xfcp_if_uart │ ├── Makefile │ ├── test_taxi_xfcp_if_uart.py │ ├── test_taxi_xfcp_if_uart.sv │ └── xfcp.py │ ├── taxi_xfcp_mod_axi │ ├── Makefile │ ├── test_taxi_xfcp_mod_axi.py │ ├── test_taxi_xfcp_mod_axi.sv │ └── xfcp.py │ ├── taxi_xfcp_mod_axil │ ├── Makefile │ ├── test_taxi_xfcp_mod_axil.py │ ├── test_taxi_xfcp_mod_axil.sv │ └── xfcp.py │ ├── taxi_xfcp_mod_i2c_master │ ├── Makefile │ ├── test_taxi_xfcp_mod_i2c_master.py │ ├── test_taxi_xfcp_mod_i2c_master.sv │ └── xfcp.py │ ├── taxi_xfcp_switch │ ├── Makefile │ ├── test_taxi_xfcp_switch.py │ ├── test_taxi_xfcp_switch.sv │ └── xfcp.py │ └── xfcp.py └── tox.ini /.github/workflows/regression-tests.yml: -------------------------------------------------------------------------------- 1 | name: Regression Tests 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | build: 7 | name: Python (${{ matrix.group }}/20) 8 | runs-on: ubuntu-24.04 9 | 10 | strategy: 11 | matrix: 12 | group: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] 13 | 14 | steps: 15 | - name: Check disk usage 16 | run: df -h 17 | 18 | - name: Check out repository 19 | uses: actions/checkout@v3 20 | 21 | - name: Install Verilator 22 | uses: v0xnihili/install-verilator-action@main 23 | with: 24 | version: v5.034 25 | 26 | - name: Install Python dependencies 27 | run: | 28 | python -m pip install --upgrade pip 29 | pip install tox tox-gh-actions 30 | 31 | - name: Check disk usage 32 | run: df -h 33 | 34 | - name: Test with tox 35 | run: tox -- -n auto --verbose --splits 20 --group ${{ matrix.group }} --splitting-algorithm least_duration 36 | 37 | - name: Check disk usage 38 | run: df -h 39 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.bak 3 | *.lxt 4 | *.fst 5 | *.pyc 6 | *.vvp 7 | 8 | -------------------------------------------------------------------------------- /.readthedocs.yaml: -------------------------------------------------------------------------------- 1 | # Read the Docs configuration file 2 | # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details 3 | 4 | version: 2 5 | 6 | build: 7 | os: ubuntu-24.04 8 | tools: 9 | python: "3.13" 10 | 11 | python: 12 | install: 13 | - requirements: docs/requirements.txt 14 | 15 | sphinx: 16 | configuration: docs/source/conf.py 17 | 18 | formats: all 19 | 20 | -------------------------------------------------------------------------------- /AUTHORS: -------------------------------------------------------------------------------- 1 | Alex Forencich 2 | -------------------------------------------------------------------------------- /docs/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = source 9 | BUILDDIR = build 10 | 11 | # Put it first so that "make" without argument is like "make help". 12 | help: 13 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 14 | 15 | .PHONY: help Makefile 16 | 17 | # Catch-all target: route all unknown targets to Sphinx using the new 18 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 19 | %: Makefile 20 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 21 | -------------------------------------------------------------------------------- /docs/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | if "%1" == "" goto help 14 | 15 | %SPHINXBUILD% >NUL 2>NUL 16 | if errorlevel 9009 ( 17 | echo. 18 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 19 | echo.installed, then set the SPHINXBUILD environment variable to point 20 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 21 | echo.may add the Sphinx directory to PATH. 22 | echo. 23 | echo.If you don't have Sphinx installed, grab it from 24 | echo.https://www.sphinx-doc.org/ 25 | exit /b 1 26 | ) 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | sphinx 2 | sphinx_rtd_theme 3 | sphinxcontrib-email 4 | sphinxcontrib-svg2pdfconverter 5 | -------------------------------------------------------------------------------- /docs/source/contents.rst: -------------------------------------------------------------------------------- 1 | .. _contents: 2 | 3 | ======== 4 | Contents 5 | ======== 6 | 7 | .. toctree:: 8 | :numbered: 9 | :includehidden: 10 | 11 | index 12 | glossary 13 | -------------------------------------------------------------------------------- /docs/source/glossary.rst: -------------------------------------------------------------------------------- 1 | .. _glossary: 2 | 3 | ======== 4 | Glossary 5 | ======== 6 | 7 | .. glossary:: 8 | 9 | AXI 10 | Advanced eXtensible Interface 11 | 12 | BAR 13 | Base Address Register 14 | 15 | CDC 16 | Clock Domain Crossing 17 | 18 | CRC 19 | Cyclic Redundancy Check 20 | 21 | DMA 22 | Direct Memory Access 23 | 24 | FPGA 25 | Field-Programmable Gate Array 26 | 27 | I2C 28 | Inter-Intergrated Circuit 29 | 30 | JTAG 31 | Joint Test Action Group 32 | 33 | LFSR 34 | Linear Feedback Shift Register 35 | 36 | MAC 37 | Media Access Control(ler) 38 | 39 | MSI 40 | Message-Signaled Interrupt 41 | 42 | NIC 43 | Network Interface Controller 44 | 45 | PCI 46 | Peripheral Component Interconnect 47 | 48 | PCIe 49 | PCI Express 50 | 51 | PHY 52 | PHYsical layer (interface) 53 | 54 | PRBS 55 | Pseudorandom Binary Sequence 56 | 57 | PTP 58 | Precision Time Protocol (IEEE 1588) 59 | 60 | RSS 61 | Receive Side Scaling 62 | 63 | UART 64 | Universal Asynchronous Receiver/Transmitter 65 | -------------------------------------------------------------------------------- /src/axi/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../ -------------------------------------------------------------------------------- /src/axi/rtl/taxi_axi_register.f: -------------------------------------------------------------------------------- 1 | taxi_axi_register.sv 2 | taxi_axi_register_wr.sv 3 | taxi_axi_register_rd.sv 4 | taxi_axi_if.sv 5 | -------------------------------------------------------------------------------- /src/axi/rtl/taxi_axil_register.f: -------------------------------------------------------------------------------- 1 | taxi_axil_register.sv 2 | taxi_axil_register_wr.sv 3 | taxi_axil_register_rd.sv 4 | taxi_axil_if.sv 5 | -------------------------------------------------------------------------------- /src/axi/tb/taxi_axi_ram/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axi_ram 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(RTL_DIR)/taxi_axi_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | export PARAM_DATA_W := 32 37 | export PARAM_ADDR_W := 16 38 | export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) 39 | export PARAM_PIPELINE_OUTPUT := 0 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4 RAM testbench 17 | */ 18 | module test_taxi_axi_ram # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter DATA_W = 32, 22 | parameter ADDR_W = 16, 23 | parameter STRB_W = (DATA_W/8), 24 | parameter ID_W = 8, 25 | parameter PIPELINE_OUTPUT = 0 26 | /* verilator lint_on WIDTHTRUNC */ 27 | ) 28 | (); 29 | 30 | logic clk; 31 | logic rst; 32 | 33 | taxi_axi_if #( 34 | .DATA_W(DATA_W), 35 | .ADDR_W(ADDR_W+16), 36 | .STRB_W(STRB_W), 37 | .ID_W(ID_W) 38 | ) s_axi(); 39 | 40 | taxi_axi_ram #( 41 | .ADDR_W(ADDR_W), 42 | .PIPELINE_OUTPUT(PIPELINE_OUTPUT) 43 | ) 44 | uut ( 45 | .clk(clk), 46 | .rst(rst), 47 | 48 | /* 49 | * AXI4-Lite slave interface 50 | */ 51 | .s_axi_wr(s_axi), 52 | .s_axi_rd(s_axi) 53 | ); 54 | 55 | endmodule 56 | 57 | `resetall 58 | -------------------------------------------------------------------------------- /src/axi/tb/taxi_axil_dp_ram/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axil_dp_ram 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | export PARAM_DATA_W := 32 37 | export PARAM_ADDR_W := 16 38 | export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) 39 | export PARAM_PIPELINE_OUTPUT := 0 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4 lite dual-port RAM testbench 17 | */ 18 | module test_taxi_axil_dp_ram # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter DATA_W = 32, 22 | parameter ADDR_W = 16, 23 | parameter STRB_W = (DATA_W/8), 24 | parameter PIPELINE_OUTPUT = 0 25 | /* verilator lint_on WIDTHTRUNC */ 26 | ) 27 | (); 28 | 29 | logic a_clk; 30 | logic a_rst; 31 | logic b_clk; 32 | logic b_rst; 33 | 34 | taxi_axil_if #( 35 | .DATA_W(DATA_W), 36 | .ADDR_W(ADDR_W+16), 37 | .STRB_W(STRB_W) 38 | ) s_axil_a(), s_axil_b(); 39 | 40 | taxi_axil_dp_ram #( 41 | .ADDR_W(ADDR_W), 42 | .PIPELINE_OUTPUT(PIPELINE_OUTPUT) 43 | ) 44 | uut ( 45 | /* 46 | * Port A 47 | */ 48 | .a_clk(a_clk), 49 | .a_rst(a_rst), 50 | .s_axil_wr_a(s_axil_a), 51 | .s_axil_rd_a(s_axil_a), 52 | 53 | /* 54 | * Port B 55 | */ 56 | .b_clk(b_clk), 57 | .b_rst(b_rst), 58 | .s_axil_wr_b(s_axil_b), 59 | .s_axil_rd_b(s_axil_b) 60 | ); 61 | 62 | endmodule 63 | 64 | `resetall 65 | -------------------------------------------------------------------------------- /src/axi/tb/taxi_axil_ram/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axil_ram 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(RTL_DIR)/taxi_axil_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | export PARAM_DATA_W := 32 37 | export PARAM_ADDR_W := 16 38 | export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) 39 | export PARAM_PIPELINE_OUTPUT := 0 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4 lite RAM testbench 17 | */ 18 | module test_taxi_axil_ram # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter DATA_W = 32, 22 | parameter ADDR_W = 16, 23 | parameter STRB_W = (DATA_W/8), 24 | parameter PIPELINE_OUTPUT = 0 25 | /* verilator lint_on WIDTHTRUNC */ 26 | ) 27 | (); 28 | 29 | logic clk; 30 | logic rst; 31 | 32 | taxi_axil_if #( 33 | .DATA_W(DATA_W), 34 | .ADDR_W(ADDR_W+16), 35 | .STRB_W(STRB_W) 36 | ) s_axil(); 37 | 38 | taxi_axil_ram #( 39 | .ADDR_W(ADDR_W), 40 | .PIPELINE_OUTPUT(PIPELINE_OUTPUT) 41 | ) 42 | uut ( 43 | .clk(clk), 44 | .rst(rst), 45 | 46 | /* 47 | * AXI4-Lite slave interface 48 | */ 49 | .s_axil_wr(s_axil), 50 | .s_axil_rd(s_axil) 51 | ); 52 | 53 | endmodule 54 | 55 | `resetall 56 | -------------------------------------------------------------------------------- /src/axis/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../ -------------------------------------------------------------------------------- /src/axis/rtl/taxi_axis_arb_mux.f: -------------------------------------------------------------------------------- 1 | taxi_axis_arb_mux.sv 2 | taxi_axis_if.sv 3 | ../lib/taxi/src/prim/rtl/taxi_arbiter.sv 4 | ../lib/taxi/src/prim/rtl/taxi_penc.sv 5 | -------------------------------------------------------------------------------- /src/axis/rtl/taxi_axis_async_fifo.f: -------------------------------------------------------------------------------- 1 | taxi_axis_async_fifo.sv 2 | ../lib/taxi/src/sync/rtl/taxi_sync_reset.sv 3 | ../lib/taxi/src/sync/rtl/taxi_sync_signal.sv 4 | taxi_axis_if.sv 5 | -------------------------------------------------------------------------------- /src/axis/rtl/taxi_axis_async_fifo_adapter.f: -------------------------------------------------------------------------------- 1 | taxi_axis_async_fifo_adapter.sv 2 | taxi_axis_async_fifo.f 3 | taxi_axis_adapter.sv 4 | -------------------------------------------------------------------------------- /src/axis/rtl/taxi_axis_cobs_encode.f: -------------------------------------------------------------------------------- 1 | taxi_axis_cobs_encode.sv 2 | taxi_axis_fifo.sv 3 | taxi_axis_if.sv 4 | -------------------------------------------------------------------------------- /src/axis/rtl/taxi_axis_fifo_adapter.f: -------------------------------------------------------------------------------- 1 | taxi_axis_fifo_adapter.sv 2 | taxi_axis_fifo.sv 3 | taxi_axis_adapter.sv 4 | taxi_axis_if.sv 5 | -------------------------------------------------------------------------------- /src/axis/rtl/taxi_axis_pipeline_register.f: -------------------------------------------------------------------------------- 1 | taxi_axis_pipeline_register.sv 2 | taxi_axis_register.sv 3 | taxi_axis_if.sv 4 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream FIFO testbench 17 | */ 18 | module test_taxi_axis_adapter # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter S_DATA_W = 8, 22 | parameter logic S_KEEP_EN = (S_DATA_W>8), 23 | parameter S_KEEP_W = ((S_DATA_W+7)/8), 24 | parameter logic S_STRB_EN = 0, 25 | parameter M_DATA_W = 8, 26 | parameter logic M_KEEP_EN = (M_DATA_W>8), 27 | parameter M_KEEP_W = ((M_DATA_W+7)/8), 28 | parameter logic M_STRB_EN = 0, 29 | parameter logic ID_EN = 0, 30 | parameter ID_W = 8, 31 | parameter logic DEST_EN = 0, 32 | parameter DEST_W = 8, 33 | parameter logic USER_EN = 1, 34 | parameter USER_W = 1 35 | /* verilator lint_on WIDTHTRUNC */ 36 | ) 37 | (); 38 | 39 | logic clk; 40 | logic rst; 41 | 42 | taxi_axis_if #( 43 | .DATA_W(S_DATA_W), 44 | .KEEP_EN(S_KEEP_EN), 45 | .KEEP_W(S_KEEP_W), 46 | .STRB_EN(S_STRB_EN), 47 | .LAST_EN(1'b1), 48 | .ID_EN(ID_EN), 49 | .ID_W(ID_W), 50 | .DEST_EN(DEST_EN), 51 | .DEST_W(DEST_W), 52 | .USER_EN(USER_EN), 53 | .USER_W(USER_W) 54 | ) s_axis(); 55 | 56 | taxi_axis_if #( 57 | .DATA_W(M_DATA_W), 58 | .KEEP_EN(M_KEEP_EN), 59 | .KEEP_W(M_KEEP_W), 60 | .STRB_EN(M_STRB_EN), 61 | .LAST_EN(1'b1), 62 | .ID_EN(ID_EN), 63 | .ID_W(ID_W), 64 | .DEST_EN(DEST_EN), 65 | .DEST_W(DEST_W), 66 | .USER_EN(USER_EN), 67 | .USER_W(USER_W) 68 | ) m_axis(); 69 | 70 | taxi_axis_adapter 71 | uut ( 72 | .clk(clk), 73 | .rst(rst), 74 | 75 | /* 76 | * AXI4-Stream input (sink) 77 | */ 78 | .s_axis(s_axis), 79 | 80 | /* 81 | * AXI4-Stream output (source) 82 | */ 83 | .m_axis(m_axis) 84 | ); 85 | 86 | endmodule 87 | 88 | `resetall 89 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream broadcaster testbench 17 | */ 18 | module test_taxi_axis_broadcast # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter M_COUNT = 4, 22 | parameter DATA_W = 8, 23 | parameter logic KEEP_EN = (DATA_W>8), 24 | parameter KEEP_W = ((DATA_W+7)/8), 25 | parameter logic STRB_EN = 1'b0, 26 | parameter logic LAST_EN = 1'b1, 27 | parameter logic ID_EN = 1'b0, 28 | parameter ID_W = 8, 29 | parameter logic DEST_EN = 1'b0, 30 | parameter DEST_W = 8, 31 | parameter logic USER_EN = 1'b1, 32 | parameter USER_W = 1 33 | /* verilator lint_on WIDTHTRUNC */ 34 | ) 35 | (); 36 | 37 | logic clk; 38 | logic rst; 39 | 40 | taxi_axis_if #( 41 | .DATA_W(DATA_W), 42 | .KEEP_EN(KEEP_EN), 43 | .KEEP_W(KEEP_W), 44 | .STRB_EN(STRB_EN), 45 | .LAST_EN(LAST_EN), 46 | .ID_EN(ID_EN), 47 | .ID_W(ID_W), 48 | .DEST_EN(DEST_EN), 49 | .DEST_W(DEST_W), 50 | .USER_EN(USER_EN), 51 | .USER_W(USER_W) 52 | ) s_axis(), m_axis[M_COUNT](); 53 | 54 | taxi_axis_broadcast #( 55 | .M_COUNT(M_COUNT) 56 | ) 57 | uut ( 58 | .clk(clk), 59 | .rst(rst), 60 | 61 | /* 62 | * AXI4-Stream input (sink) 63 | */ 64 | .s_axis(s_axis), 65 | 66 | /* 67 | * AXI4-Stream output (source) 68 | */ 69 | .m_axis(m_axis) 70 | ); 71 | 72 | endmodule 73 | 74 | `resetall 75 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_cobs_decode/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2021-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axis_cobs_decode 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | #export PARAM_APPEND_ZERO := 0 37 | 38 | ifeq ($(SIM), icarus) 39 | PLUSARGS += -fst 40 | 41 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 42 | else ifeq ($(SIM), verilator) 43 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 44 | 45 | ifeq ($(WAVES), 1) 46 | COMPILE_ARGS += --trace-fst 47 | VERILATOR_TRACE = 1 48 | endif 49 | endif 50 | 51 | include $(shell cocotb-config --makefiles)/Makefile.sim 52 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream COBS decoder testbench 17 | */ 18 | module test_taxi_axis_cobs_decode(); 19 | 20 | logic clk; 21 | logic rst; 22 | 23 | taxi_axis_if #( 24 | .DATA_W(8), 25 | .LAST_EN(1), 26 | .USER_EN(1), 27 | .USER_W(1) 28 | ) s_axis(), m_axis(); 29 | 30 | taxi_axis_cobs_decode 31 | uut ( 32 | .clk(clk), 33 | .rst(rst), 34 | 35 | /* 36 | * AXI4-Stream input (sink) 37 | */ 38 | .s_axis(s_axis), 39 | 40 | /* 41 | * AXI4-Stream output (source) 42 | */ 43 | .m_axis(m_axis) 44 | ); 45 | 46 | endmodule 47 | 48 | `resetall 49 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_cobs_encode/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2021-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axis_cobs_encode 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f 27 | 28 | # handle file list files 29 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 30 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 31 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 32 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 33 | 34 | # module parameters 35 | export PARAM_APPEND_ZERO := 0 36 | 37 | ifeq ($(SIM), icarus) 38 | PLUSARGS += -fst 39 | 40 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 41 | else ifeq ($(SIM), verilator) 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 43 | 44 | ifeq ($(WAVES), 1) 45 | COMPILE_ARGS += --trace-fst 46 | VERILATOR_TRACE = 1 47 | endif 48 | endif 49 | 50 | include $(shell cocotb-config --makefiles)/Makefile.sim 51 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream COBS encoder testbench 17 | */ 18 | module test_taxi_axis_cobs_encode # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter logic APPEND_ZERO = 1'b1 22 | /* verilator lint_on WIDTHTRUNC */ 23 | ) 24 | (); 25 | 26 | logic clk; 27 | logic rst; 28 | 29 | taxi_axis_if #( 30 | .DATA_W(8), 31 | .LAST_EN(1), 32 | .USER_EN(1), 33 | .USER_W(1) 34 | ) s_axis(), m_axis(); 35 | 36 | taxi_axis_cobs_encode #( 37 | .APPEND_ZERO(APPEND_ZERO) 38 | ) 39 | uut ( 40 | .clk(clk), 41 | .rst(rst), 42 | 43 | /* 44 | * AXI4-Stream input (sink) 45 | */ 46 | .s_axis(s_axis), 47 | 48 | /* 49 | * AXI4-Stream output (source) 50 | */ 51 | .m_axis(m_axis) 52 | ); 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream multiplexer testbench 17 | */ 18 | module test_taxi_axis_mux # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter S_COUNT = 4, 22 | parameter DATA_W = 8, 23 | parameter logic KEEP_EN = (DATA_W>8), 24 | parameter KEEP_W = ((DATA_W+7)/8), 25 | parameter logic STRB_EN = 1'b0, 26 | parameter logic LAST_EN = 1'b1, 27 | parameter logic ID_EN = 1'b0, 28 | parameter ID_W = 8, 29 | parameter logic DEST_EN = 1'b0, 30 | parameter DEST_W = 8, 31 | parameter logic USER_EN = 1'b1, 32 | parameter USER_W = 1 33 | /* verilator lint_on WIDTHTRUNC */ 34 | ) 35 | (); 36 | 37 | logic clk; 38 | logic rst; 39 | 40 | taxi_axis_if #( 41 | .DATA_W(DATA_W), 42 | .KEEP_EN(KEEP_EN), 43 | .KEEP_W(KEEP_W), 44 | .STRB_EN(STRB_EN), 45 | .LAST_EN(LAST_EN), 46 | .ID_EN(ID_EN), 47 | .ID_W(ID_W), 48 | .DEST_EN(DEST_EN), 49 | .DEST_W(DEST_W), 50 | .USER_EN(USER_EN), 51 | .USER_W(USER_W) 52 | ) s_axis[S_COUNT](), m_axis(); 53 | 54 | logic enable; 55 | logic [$clog2(S_COUNT)-1:0] select; 56 | 57 | taxi_axis_mux #( 58 | .S_COUNT(S_COUNT) 59 | ) 60 | uut ( 61 | .clk(clk), 62 | .rst(rst), 63 | 64 | /* 65 | * AXI4-Stream input (sink) 66 | */ 67 | .s_axis(s_axis), 68 | 69 | /* 70 | * AXI4-Stream output (source) 71 | */ 72 | .m_axis(m_axis), 73 | 74 | /* 75 | * Control 76 | */ 77 | .enable(enable), 78 | .select(select) 79 | ); 80 | 81 | endmodule 82 | 83 | `resetall 84 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream pipeline FIFO testbench 17 | */ 18 | module test_taxi_axis_pipeline_fifo # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter DATA_W = 8, 22 | parameter logic KEEP_EN = (DATA_W>8), 23 | parameter KEEP_W = ((DATA_W+7)/8), 24 | parameter logic STRB_EN = 1'b0, 25 | parameter logic LAST_EN = 1'b1, 26 | parameter logic ID_EN = 1'b0, 27 | parameter ID_W = 8, 28 | parameter logic DEST_EN = 1'b0, 29 | parameter DEST_W = 8, 30 | parameter logic USER_EN = 1'b1, 31 | parameter USER_W = 1, 32 | parameter LENGTH = 2 33 | /* verilator lint_on WIDTHTRUNC */ 34 | ) 35 | (); 36 | 37 | logic clk; 38 | logic rst; 39 | 40 | taxi_axis_if #( 41 | .DATA_W(DATA_W), 42 | .KEEP_EN(KEEP_EN), 43 | .KEEP_W(KEEP_W), 44 | .STRB_EN(STRB_EN), 45 | .LAST_EN(LAST_EN), 46 | .ID_EN(ID_EN), 47 | .ID_W(ID_W), 48 | .DEST_EN(DEST_EN), 49 | .DEST_W(DEST_W), 50 | .USER_EN(USER_EN), 51 | .USER_W(USER_W) 52 | ) s_axis(), m_axis(); 53 | 54 | taxi_axis_pipeline_fifo #( 55 | .LENGTH(LENGTH) 56 | ) 57 | uut ( 58 | .clk(clk), 59 | .rst(rst), 60 | 61 | /* 62 | * AXI4-Stream input (sink) 63 | */ 64 | .s_axis(s_axis), 65 | 66 | /* 67 | * AXI4-Stream output (source) 68 | */ 69 | .m_axis(m_axis) 70 | ); 71 | 72 | endmodule 73 | 74 | `resetall 75 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream pipeline register testbench 17 | */ 18 | module test_taxi_axis_pipeline_register # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter DATA_W = 8, 22 | parameter logic KEEP_EN = (DATA_W>8), 23 | parameter KEEP_W = ((DATA_W+7)/8), 24 | parameter logic STRB_EN = 1'b0, 25 | parameter logic LAST_EN = 1'b1, 26 | parameter logic ID_EN = 1'b0, 27 | parameter ID_W = 8, 28 | parameter logic DEST_EN = 1'b0, 29 | parameter DEST_W = 8, 30 | parameter logic USER_EN = 1'b1, 31 | parameter USER_W = 1, 32 | parameter REG_TYPE = 2, 33 | parameter LENGTH = 2 34 | /* verilator lint_on WIDTHTRUNC */ 35 | ) 36 | (); 37 | 38 | logic clk; 39 | logic rst; 40 | 41 | taxi_axis_if #( 42 | .DATA_W(DATA_W), 43 | .KEEP_EN(KEEP_EN), 44 | .KEEP_W(KEEP_W), 45 | .STRB_EN(STRB_EN), 46 | .LAST_EN(LAST_EN), 47 | .ID_EN(ID_EN), 48 | .ID_W(ID_W), 49 | .DEST_EN(DEST_EN), 50 | .DEST_W(DEST_W), 51 | .USER_EN(USER_EN), 52 | .USER_W(USER_W) 53 | ) s_axis(), m_axis(); 54 | 55 | taxi_axis_pipeline_register #( 56 | .REG_TYPE(REG_TYPE), 57 | .LENGTH(LENGTH) 58 | ) 59 | uut ( 60 | .clk(clk), 61 | .rst(rst), 62 | 63 | /* 64 | * AXI4-Stream input (sink) 65 | */ 66 | .s_axis(s_axis), 67 | 68 | /* 69 | * AXI4-Stream output (source) 70 | */ 71 | .m_axis(m_axis) 72 | ); 73 | 74 | endmodule 75 | 76 | `resetall 77 | -------------------------------------------------------------------------------- /src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream register testbench 17 | */ 18 | module test_taxi_axis_register # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter DATA_W = 8, 22 | parameter logic KEEP_EN = (DATA_W>8), 23 | parameter KEEP_W = ((DATA_W+7)/8), 24 | parameter logic STRB_EN = 1'b0, 25 | parameter logic LAST_EN = 1'b1, 26 | parameter logic ID_EN = 1'b0, 27 | parameter ID_W = 8, 28 | parameter logic DEST_EN = 1'b0, 29 | parameter DEST_W = 8, 30 | parameter logic USER_EN = 1'b1, 31 | parameter USER_W = 1, 32 | parameter REG_TYPE = 2 33 | /* verilator lint_on WIDTHTRUNC */ 34 | ) 35 | (); 36 | 37 | logic clk; 38 | logic rst; 39 | 40 | taxi_axis_if #( 41 | .DATA_W(DATA_W), 42 | .KEEP_EN(KEEP_EN), 43 | .KEEP_W(KEEP_W), 44 | .STRB_EN(STRB_EN), 45 | .LAST_EN(LAST_EN), 46 | .ID_EN(ID_EN), 47 | .ID_W(ID_W), 48 | .DEST_EN(DEST_EN), 49 | .DEST_W(DEST_W), 50 | .USER_EN(USER_EN), 51 | .USER_W(USER_W) 52 | ) s_axis(), m_axis(); 53 | 54 | taxi_axis_register #( 55 | .REG_TYPE(REG_TYPE) 56 | ) 57 | uut ( 58 | .clk(clk), 59 | .rst(rst), 60 | 61 | /* 62 | * AXI4-Stream input (sink) 63 | */ 64 | .s_axis(s_axis), 65 | 66 | /* 67 | * AXI4-Stream output (source) 68 | */ 69 | .m_axis(m_axis) 70 | ); 71 | 72 | endmodule 73 | 74 | `resetall 75 | -------------------------------------------------------------------------------- /src/eth/example/ADM_PCIE_9V3/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for ADM-PCIE-9V3 2 | 3 | ## Introduction 4 | 5 | This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board. 6 | 7 | The design places looped-back MACs on the QSFP28 ports. 8 | 9 | * QSFP28 10 | * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers 11 | 12 | ## Board details 13 | 14 | * FPGA: xcvu3p-ffvc1517-2-i 15 | * 25GBASE-R PHY: Soft PCS with GTY transceivers 16 | 17 | ## Licensing 18 | 19 | * Toolchain 20 | * Vivado Enterprise (requires license) 21 | * IP 22 | * No licensed vendor IP or 3rd party IP 23 | 24 | ## How to build 25 | 26 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 27 | 28 | ## How to test 29 | 30 | Run `make program` to program the board with Vivado. 31 | 32 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 33 | -------------------------------------------------------------------------------- /src/eth/example/ADM_PCIE_9V3/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/Alveo/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for Alveo 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo series. 6 | 7 | The design places looped-back MACs on the Ethernet ports, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (3 Mbaud) 11 | * DSFP/QSFP28 12 | * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers 13 | 14 | ## Board details 15 | 16 | * FPGA 17 | * AU45N/SN1000: xcu26-vsva1365-2LV-e 18 | * AU50: xcu50-fsvh2104-2-e 19 | * AU55C: xcu55c-fsvh2892-2L-e 20 | * AU55N/C1100: xcu55n-fsvh2892-2L-e 21 | * AU200: xcu200-fsgd2104-2-e 22 | * AU250: xcu250-fsgd2104-2-e 23 | * AU280: xcu280-fsvh2892-2L-e 24 | * VCU1525: xcvu9p-fsgd2104-2L-e 25 | * X3/X3522: xcux35-vsva1365-3-e 26 | * USB UART 27 | * AU45N/SN1000: FTDI FT4232H (DMB-2) 28 | * AU50: FTDI FT4232H (3 via DMB-1) 29 | * AU55C: FTDI FT4232H (2 onboard, all 3 via DMB-1) 30 | * AU55N/C1100: FTDI FT4232H (2 onboard, all 3 via DMB-1) 31 | * AU200: FTDI FT4232H 32 | * AU250: FTDI FT4232H 33 | * AU280: FTDI FT4232H 34 | * VCU1525: FTDI FT4232H 35 | * X3/X3522: FTDI FT4232H (DMB-2) 36 | * 25GBASE-R PHY: Soft PCS with GTY transceivers 37 | 38 | ## Licensing 39 | 40 | * Toolchain 41 | * Vivado Standard (enterprise license not required) 42 | * IP 43 | * No licensed vendor IP or 3rd party IP 44 | 45 | ## How to build 46 | 47 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 48 | 49 | ## How to test 50 | 51 | Run `make program` to program the board with Vivado. 52 | 53 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 54 | -------------------------------------------------------------------------------- /src/eth/example/Alveo/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/Alveo/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/Arty/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for Arty A7 2 | 3 | ## Introduction 4 | 5 | This example design targets the Digilent Arty A7 FPGA board. 6 | 7 | The design places a looped-back MAC on the BASE-T port, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (3 Mbaud) 11 | * RJ-45 Ethernet port with TI DP83848J PHY 12 | * Looped-back MAC via MII 13 | 14 | ## Board details 15 | 16 | * FPGA: XC7A35TICSG324-1L 17 | * USB UART: FTDI FT2232H 18 | * PHY: TI DP83848J via MII 19 | 20 | ## Licensing 21 | 22 | * Toolchain 23 | * Vivado Standard (enterprise license not required) 24 | * IP 25 | * No licensed vendor IP or 3rd party IP 26 | 27 | ## How to build 28 | 29 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 30 | 31 | ## How to test 32 | 33 | Run `make program` to program the board with Vivado. 34 | 35 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 36 | -------------------------------------------------------------------------------- /src/eth/example/Arty/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/HTG940/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for HTG-940 2 | 3 | ## Introduction 4 | 5 | This example design targets the HiTech Global HTG-940 FPGA board. 6 | 7 | The design places a looped-back MAC on the BASE-T port, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (921600 baud) 11 | * RJ-45 Ethernet ports with TI DP83867IRPAP PHY 12 | * Looped-back MAC via RGMII 13 | 14 | ## Board details 15 | 16 | * FPGA: xcvu9p-flgb2104-2-e 17 | * USB UART: Silicon Labs CP2103 18 | * 1000BASE-T PHY: TI DP83867IRPAP via RGMII 19 | 20 | ## Licensing 21 | 22 | * Toolchain 23 | * Vivado Enterprise (requires license) 24 | * IP 25 | * No licensed vendor IP or 3rd party IP 26 | 27 | ## How to build 28 | 29 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 30 | 31 | ## How to test 32 | 33 | Run `make program` to program the board with Vivado. 34 | 35 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 36 | -------------------------------------------------------------------------------- /src/eth/example/HTG940/fpga/eth_rgmii.xdc: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # Ethernet constraints 10 | 11 | # IDELAY from PHY chip (RGMII) 12 | set_property DELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_bit[*].idelay_inst}] 13 | 14 | # MMCM phase (RGMII) 15 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 16 | -------------------------------------------------------------------------------- /src/eth/example/HTG940/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/eth_gmii.xdc: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # Ethernet constraints 10 | 11 | # BUFGMUX outputs (GMII) 12 | set_clock_groups -physically_exclusive -group clk_mmcm_out -group phy_tx_clk 13 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/eth_rgmii.xdc: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # Ethernet constraints 10 | 11 | # IDELAY from PHY chip (RGMII) 12 | set_property IDELAY_VALUE 0 [get_cells {phy_if.phy_rx_ctl_idelay phy_if.phy_rxd_idelay_bit[*].idelay_inst}] 13 | 14 | # MMCM phase (RGMII) 15 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 16 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/fpga_gmii_1g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # Type of PHY on RJ-45 10/100/1000BASE-T port (GMII, RGMII, or SGMII) 12 | dict set params BASET_PHY_TYPE "GMII" 13 | 14 | # Invert polarity for SFP+ cage 15 | # KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped 16 | dict set params SFP_INVERT "1" 17 | # KC705 rev 1.1: diff pairs to SFP+ are correct 18 | #dict set params SFP_INVERT "0" 19 | 20 | # apply parameters to top-level 21 | set param_list {} 22 | dict for {name value} $params { 23 | lappend param_list $name=$value 24 | } 25 | 26 | set_property generic $param_list [get_filesets sources_1] 27 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/fpga_rgmii_1g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # Type of PHY on RJ-45 10/100/1000BASE-T port (GMII, RGMII, or SGMII) 12 | dict set params BASET_PHY_TYPE "RGMII" 13 | 14 | # Invert polarity for SFP+ cage 15 | # KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped 16 | dict set params SFP_INVERT "1" 17 | # KC705 rev 1.1: diff pairs to SFP+ are correct 18 | #dict set params SFP_INVERT "0" 19 | 20 | # apply parameters to top-level 21 | set param_list {} 22 | dict for {name value} $params { 23 | lappend param_list $name=$value 24 | } 25 | 26 | set_property generic $param_list [get_filesets sources_1] 27 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/fpga_rgmii_1g/generate_bit_iodelay.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # Generate bit file with different IODELAY settings without rebuilding the full project 10 | 11 | open_project fpga.xpr 12 | open_run impl_1 13 | 14 | # IDELAY from PHY chip (RGMII) 15 | set_property IDELAY_VALUE 0 [get_cells {phy_if.phy_rx_ctl_idelay phy_if.phy_rxd_idelay_bit[*].idelay_inst}] 16 | 17 | # MMCM phase (RGMII) 18 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 19 | 20 | write_bitstream -force fpga.bit 21 | exit 22 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/fpga_sgmii_1g/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # FPGA settings 10 | FPGA_PART = xc7k325tffg900-2 11 | FPGA_TOP = fpga 12 | FPGA_ARCH = kintex7 13 | 14 | RTL_DIR = ../rtl 15 | LIB_DIR = ../lib 16 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 17 | 18 | # Files for synthesis 19 | SYN_FILES = $(RTL_DIR)/fpga.sv 20 | SYN_FILES += $(RTL_DIR)/fpga_core.sv 21 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f 22 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f 23 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv 24 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f 25 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 26 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 27 | SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv 28 | 29 | # XDC files 30 | XDC_FILES = ../fpga.xdc 31 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl 32 | XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl 33 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl 34 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl 35 | 36 | # IP 37 | IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl 38 | IP_TCL_FILES += ../ip/basex_pcs_pma_0.tcl 39 | 40 | # Configuration 41 | CONFIG_TCL_FILES = ./config.tcl 42 | 43 | include ../common/vivado.mk 44 | 45 | program: $(PROJECT).bit 46 | echo "open_hw_manager" > program.tcl 47 | echo "connect_hw_server" >> program.tcl 48 | echo "open_hw_target" >> program.tcl 49 | echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl 50 | echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl 51 | echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl 52 | echo "program_hw_devices [current_hw_device]" >> program.tcl 53 | echo "exit" >> program.tcl 54 | vivado -nojournal -nolog -mode batch -source program.tcl 55 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/fpga_sgmii_1g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # Type of PHY on RJ-45 10/100/1000BASE-T port (GMII, RGMII, or SGMII) 12 | dict set params BASET_PHY_TYPE "SGMII" 13 | 14 | # Invert polarity for SFP+ cage 15 | # KC705 rev 1.0: diff pairs to SFP+ are polarity-swapped 16 | dict set params SFP_INVERT "1" 17 | # KC705 rev 1.1: diff pairs to SFP+ are correct 18 | #dict set params SFP_INVERT "0" 19 | 20 | # apply parameters to top-level 21 | set param_list {} 22 | dict for {name value} $params { 23 | lappend param_list $name=$value 24 | } 25 | 26 | set_property generic $param_list [get_filesets sources_1] 27 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/ip/basex_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {1000BASEX} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.Auto_Negotiation {false} \ 16 | CONFIG.TransceiverControl {true} \ 17 | CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \ 18 | ] [get_ips basex_pcs_pma_0] 19 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/ip/sgmii_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {SGMII} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 16 | ] [get_ips sgmii_pcs_pma_0] 17 | -------------------------------------------------------------------------------- /src/eth/example/KC705/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/KCU105/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for KCU105 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx KCU105 FPGA board. 6 | 7 | The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (921600 baud) 11 | * RJ-45 Ethernet port with Marvell 88E1111 PHY 12 | * Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES 13 | * SFP+ cages 14 | * Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTH transceiver 15 | * Looped-back 10GBASE-R MAC via GTH transceiver 16 | 17 | ## Board details 18 | 19 | * FPGA: xcku040-ffva1156-2-e 20 | * USB UART: Silicon Labs CP2105 SCI 21 | * 1000BASE-T PHY: Marvell 88E1111 via SGMII 22 | * 1000BASE-X PHY: Xilinx PCS/PMA core via GTH transceiver 23 | * 10GBASE-R PHY: Soft PCS with GTH transceiver 24 | 25 | ## Licensing 26 | 27 | * Toolchain 28 | * Vivado Enterprise (requires license) 29 | * IP 30 | * No licensed vendor IP or 3rd party IP 31 | 32 | ## How to build 33 | 34 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 35 | 36 | ## How to test 37 | 38 | Run `make program` to program the board with Vivado. 39 | 40 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 41 | -------------------------------------------------------------------------------- /src/eth/example/KCU105/fpga/fpga_10g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # SFP+ rate 12 | # 0 for 1G, 1 for 10G 13 | dict set params SFP_RATE "1" 14 | 15 | # apply parameters to top-level 16 | set param_list {} 17 | dict for {name value} $params { 18 | lappend param_list $name=$value 19 | } 20 | 21 | set_property generic $param_list [get_filesets sources_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/KCU105/fpga/fpga_1g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # SFP+ rate 12 | # 0 for 1G, 1 for 10G 13 | dict set params SFP_RATE "0" 14 | 15 | # apply parameters to top-level 16 | set param_list {} 17 | dict for {name value} $params { 18 | lappend param_list $name=$value 19 | } 20 | 21 | set_property generic $param_list [get_filesets sources_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/KCU105/fpga/ip/basex_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {1000BASEX} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.Auto_Negotiation {false} \ 16 | CONFIG.TransceiverControl {false} \ 17 | CONFIG.RefClkRate {156.25} \ 18 | CONFIG.DrpClkRate {62.5} \ 19 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 20 | CONFIG.GT_Location {X0Y10} \ 21 | ] [get_ips basex_pcs_pma_0] 22 | -------------------------------------------------------------------------------- /src/eth/example/KCU105/fpga/ip/basex_pcs_pma_1.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_1 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {1000BASEX} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.Auto_Negotiation {false} \ 16 | CONFIG.TransceiverControl {false} \ 17 | CONFIG.RefClkRate {156.25} \ 18 | CONFIG.DrpClkRate {62.5} \ 19 | CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \ 20 | CONFIG.GT_Location {X0Y9} \ 21 | ] [get_ips basex_pcs_pma_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/KCU105/fpga/ip/sgmii_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {SGMII} \ 13 | CONFIG.Physical_Interface {LVDS} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 16 | CONFIG.LvdsRefClk {625} \ 17 | ] [get_ips sgmii_pcs_pma_0] 18 | -------------------------------------------------------------------------------- /src/eth/example/KCU105/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/KCU105/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for KR260 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx KR260 FPGA board. 6 | 7 | The design places looped-back MACs on the BASE-T ports and SFP+ cage. 8 | 9 | * RJ-45 Ethernet ports with TI DP83867CSRGZ PHY 10 | * Looped-back MAC via RGMII 11 | * SFP+ cage 12 | * Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTH transceiver 13 | * Looped-back 10GBASE-R MAC via GTH transceiver 14 | 15 | ## Board details 16 | 17 | * FPGA: xck26-sfvc784-2LV-c 18 | * 1000BASE-T PHY: TI DP83867CSRGZ via RGMII 19 | * 1000BASE-X PHY: Xilinx PCS/PMA core via GTH transceiver 20 | * 10GBASE-R PHY: Soft PCS with GTH transceiver 21 | 22 | ## Licensing 23 | 24 | * Toolchain 25 | * Vivado Standard (enterprise license not required) 26 | * IP 27 | * No licensed vendor IP or 3rd party IP 28 | 29 | ## How to build 30 | 31 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 32 | 33 | ## How to test 34 | 35 | Run `make program` to program the board with Vivado. 36 | 37 | To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification. 38 | 39 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 40 | -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/eth_rgmii.xdc: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # Ethernet constraints 10 | 11 | # IDELAY from PHY chip (RGMII) 12 | set_property DELAY_VALUE 0 [get_cells {phy2_rx_ctl_idelay phy2_rxd_idelay_bit[*].idelay_inst}] 13 | set_property DELAY_VALUE 0 [get_cells {phy3_rx_ctl_idelay phy3_rxd_idelay_bit[*].idelay_inst}] 14 | 15 | # MMCM phase (RGMII) 16 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 17 | -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # FPGA settings 10 | FPGA_PART = xck26-sfvc784-2LV-c 11 | FPGA_TOP = fpga 12 | FPGA_ARCH = zynquplus 13 | 14 | RTL_DIR = ../rtl 15 | LIB_DIR = ../lib 16 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 17 | 18 | # Files for synthesis 19 | SYN_FILES = $(RTL_DIR)/fpga.sv 20 | SYN_FILES += $(RTL_DIR)/fpga_core.sv 21 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f 22 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f 23 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 24 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 25 | 26 | # XDC files 27 | XDC_FILES = ../fpga.xdc 28 | XDC_FILES += ../eth_rgmii.xdc 29 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl 30 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl 31 | XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl 32 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl 33 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl 34 | 35 | # IP 36 | IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl 37 | 38 | # Configuration 39 | CONFIG_TCL_FILES = ./config.tcl 40 | 41 | include ../common/vivado.mk 42 | 43 | program: $(PROJECT).bit 44 | echo "open_hw_manager" > program.tcl 45 | echo "connect_hw_server" >> program.tcl 46 | echo "open_hw_target" >> program.tcl 47 | echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl 48 | echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl 49 | echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl 50 | echo "program_hw_devices [current_hw_device]" >> program.tcl 51 | echo "exit" >> program.tcl 52 | vivado -nojournal -nolog -mode batch -source program.tcl 53 | -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/fpga_10g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # SFP+ rate 12 | # 0 for 1G, 1 for 10G 13 | dict set params SFP_RATE "1" 14 | 15 | # apply parameters to top-level 16 | set param_list {} 17 | dict for {name value} $params { 18 | lappend param_list $name=$value 19 | } 20 | 21 | set_property generic $param_list [get_filesets sources_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/fpga_1g/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # FPGA settings 10 | FPGA_PART = xck26-sfvc784-2LV-c 11 | FPGA_TOP = fpga 12 | FPGA_ARCH = zynquplus 13 | 14 | RTL_DIR = ../rtl 15 | LIB_DIR = ../lib 16 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 17 | 18 | # Files for synthesis 19 | SYN_FILES = $(RTL_DIR)/fpga.sv 20 | SYN_FILES += $(RTL_DIR)/fpga_core.sv 21 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f 22 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f 23 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 24 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 25 | 26 | # XDC files 27 | XDC_FILES = ../fpga.xdc 28 | XDC_FILES += ../eth_rgmii.xdc 29 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_rgmii_phy_if.tcl 30 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl 31 | XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl 32 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl 33 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl 34 | 35 | # IP 36 | IP_TCL_FILES = ../ip/basex_pcs_pma_0.tcl 37 | 38 | # Configuration 39 | CONFIG_TCL_FILES = ./config.tcl 40 | 41 | include ../common/vivado.mk 42 | 43 | program: $(PROJECT).bit 44 | echo "open_hw_manager" > program.tcl 45 | echo "connect_hw_server" >> program.tcl 46 | echo "open_hw_target" >> program.tcl 47 | echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl 48 | echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl 49 | echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl 50 | echo "program_hw_devices [current_hw_device]" >> program.tcl 51 | echo "exit" >> program.tcl 52 | vivado -nojournal -nolog -mode batch -source program.tcl 53 | -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/fpga_1g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # SFP+ rate 12 | # 0 for 1G, 1 for 10G 13 | dict set params SFP_RATE "0" 14 | 15 | # apply parameters to top-level 16 | set param_list {} 17 | dict for {name value} $params { 18 | lappend param_list $name=$value 19 | } 20 | 21 | set_property generic $param_list [get_filesets sources_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/fpga_1g/generate_bit_iodelay.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # Generate bit file with different IODELAY settings without rebuilding the full project 10 | 11 | open_project fpga.xpr 12 | open_run impl_1 13 | 14 | # IDELAY from PHY chip (RGMII) 15 | set_property DELAY_VALUE 0 [get_cells {phy2_rx_ctl_idelay phy2_rxd_idelay_bit[*].idelay_inst}] 16 | set_property DELAY_VALUE 0 [get_cells {phy3_rx_ctl_idelay phy3_rxd_idelay_bit[*].idelay_inst}] 17 | 18 | # MMCM phase (RGMII) 19 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 20 | 21 | write_bitstream -force fpga.bit 22 | exit 23 | -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/ip/basex_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {1000BASEX} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.Auto_Negotiation {false} \ 16 | CONFIG.TransceiverControl {false} \ 17 | CONFIG.RefClkRate {156.25} \ 18 | CONFIG.DrpClkRate {62.5} \ 19 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 20 | CONFIG.GT_Location {X0Y6} \ 21 | ] [get_ips basex_pcs_pma_0] 22 | -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/KR260/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_Q/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for Nexus K3P-Q (ExaNIC X100) 2 | 3 | ## Introduction 4 | 5 | This example design targets the Cisco Nexus K3P-Q (ExaNIC X100) FPGA board. 6 | 7 | The design places looped-back MACs on the QSFP28 cages. 8 | 9 | * QSFP28 cages 10 | * Looped-back 10GBASE-R or 25GBASE-R MAC via GTH or GTY transceiver 11 | 12 | ## Board details 13 | 14 | * FPGA: xcku3p-ffvb676-2-e 15 | * 25GBASE-R PHY: Soft PCS with GTH or GTY transceiver 16 | 17 | ## Licensing 18 | 19 | * Toolchain 20 | * Vivado Standard (enterprise license not required) 21 | * IP 22 | * No licensed vendor IP or 3rd party IP 23 | 24 | ## How to build 25 | 26 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 27 | 28 | ## How to test 29 | 30 | Run `make program` to program the board with Vivado. 31 | 32 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 33 | -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_Q/fpga/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # FPGA settings 10 | FPGA_PART = xcku3p-ffvb676-2-e 11 | FPGA_TOP = fpga 12 | FPGA_ARCH = kintexuplus 13 | 14 | RTL_DIR = ../rtl 15 | LIB_DIR = ../lib 16 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 17 | 18 | # Files for synthesis 19 | SYN_FILES = $(RTL_DIR)/fpga.sv 20 | SYN_FILES += $(RTL_DIR)/fpga_core.sv 21 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f 22 | SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f 23 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 24 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 25 | SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv 26 | 27 | # XDC files 28 | XDC_FILES = ../fpga.xdc 29 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl 30 | XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl 31 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl 32 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl 33 | 34 | # IP 35 | IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl 36 | 37 | # Configuration 38 | # CONFIG_TCL_FILES = ./config.tcl 39 | 40 | include ../common/vivado.mk 41 | 42 | program: $(PROJECT).bit 43 | echo "open_hw_manager" > program.tcl 44 | echo "connect_hw_server" >> program.tcl 45 | echo "open_hw_target" >> program.tcl 46 | echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl 47 | echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl 48 | echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl 49 | echo "program_hw_devices [current_hw_device]" >> program.tcl 50 | echo "exit" >> program.tcl 51 | vivado -nojournal -nolog -mode batch -source program.tcl 52 | -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_Q/fpga/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # FPGA settings 10 | FPGA_PART = xcku3p-ffvb676-2-e 11 | FPGA_TOP = fpga 12 | FPGA_ARCH = kintexuplus 13 | 14 | RTL_DIR = ../rtl 15 | LIB_DIR = ../lib 16 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 17 | 18 | # Files for synthesis 19 | SYN_FILES = $(RTL_DIR)/fpga.sv 20 | SYN_FILES += $(RTL_DIR)/fpga_core.sv 21 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f 22 | SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f 23 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 24 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 25 | SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv 26 | 27 | # XDC files 28 | XDC_FILES = ../fpga.xdc 29 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl 30 | XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl 31 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl 32 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl 33 | 34 | # IP 35 | IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl 36 | 37 | # Configuration 38 | # CONFIG_TCL_FILES = ./config.tcl 39 | 40 | include ../common/vivado.mk 41 | 42 | program: $(PROJECT).bit 43 | echo "open_hw_manager" > program.tcl 44 | echo "connect_hw_server" >> program.tcl 45 | echo "open_hw_target" >> program.tcl 46 | echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl 47 | echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl 48 | echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl 49 | echo "program_hw_devices [current_hw_device]" >> program.tcl 50 | echo "exit" >> program.tcl 51 | vivado -nojournal -nolog -mode batch -source program.tcl 52 | -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_Q/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = fpga_core 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 29 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 30 | 31 | # handle file list files 32 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 33 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 34 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 35 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 36 | 37 | # module parameters 38 | export PARAM_SIM := "1'b1" 39 | export PARAM_VENDOR := "\"XILINX\"" 40 | export PARAM_FAMILY := "\"kintexuplus\"" 41 | 42 | ifeq ($(SIM), icarus) 43 | PLUSARGS += -fst 44 | 45 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 46 | else ifeq ($(SIM), verilator) 47 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 48 | 49 | ifeq ($(WAVES), 1) 50 | COMPILE_ARGS += --trace-fst 51 | VERILATOR_TRACE = 1 52 | endif 53 | endif 54 | 55 | include $(shell cocotb-config --makefiles)/Makefile.sim 56 | -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_S/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for Nexus K35-S/K3P-S (ExaNIC X10/X25) 2 | 3 | ## Introduction 4 | 5 | This example design targets the Cisco Nexus K35-S/K3P-S (ExaNIC X10/X25) FPGA board. 6 | 7 | The design places looped-back MACs on the SFP+ cages. 8 | 9 | * SFP+ cages 10 | * Looped-back 10GBASE-R or 25GBASE-R MAC via GTH or GTY transceiver 11 | 12 | ## Board details 13 | 14 | * FPGA: 15 | * K35-S/X10: xcku035-fbva676-2-e 16 | * K3P-S/X235: xcku3p-ffvb676-2-e 17 | * 25GBASE-R PHY: Soft PCS with GTH or GTY transceiver 18 | 19 | ## Licensing 20 | 21 | * Toolchain 22 | * Vivado Standard (enterprise license not required) 23 | * IP 24 | * No licensed vendor IP or 3rd party IP 25 | 26 | ## How to build 27 | 28 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 29 | 30 | ## How to test 31 | 32 | Run `make program` to program the board with Vivado. 33 | 34 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 35 | -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_S/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = fpga_core 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 29 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 30 | 31 | # handle file list files 32 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 33 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 34 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 35 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 36 | 37 | # module parameters 38 | export PARAM_SIM := "1'b1" 39 | export PARAM_VENDOR := "\"XILINX\"" 40 | export PARAM_FAMILY := "\"kintexuplus\"" 41 | 42 | ifeq ($(SIM), icarus) 43 | PLUSARGS += -fst 44 | 45 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 46 | else ifeq ($(SIM), verilator) 47 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 48 | 49 | ifeq ($(WAVES), 1) 50 | COMPILE_ARGS += --trace-fst 51 | VERILATOR_TRACE = 1 52 | endif 53 | endif 54 | 55 | include $(shell cocotb-config --makefiles)/Makefile.sim 56 | -------------------------------------------------------------------------------- /src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/VCU108/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for VCU108 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU108 FPGA board. 6 | 7 | The design places looped-back MACs on the BASE-T and QSFP28 ports, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (921600 baud) 11 | * RJ-45 Ethernet port with Marvell 88E1111 PHY 12 | * Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES 13 | * QSFP28 14 | * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers 15 | 16 | ## Board details 17 | 18 | * FPGA: xcvu095-ffva2104-2-e 19 | * USB UART: Silicon Labs CP2105 SCI 20 | * 1000BASE-T PHY: Marvell 88E1111 via SGMII 21 | * 25GBASE-R PHY: Soft PCS with GTY transceivers 22 | 23 | ## Licensing 24 | 25 | * Toolchain 26 | * Vivado Enterprise (requires license) 27 | * IP 28 | * No licensed vendor IP or 3rd party IP 29 | 30 | ## How to build 31 | 32 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 33 | 34 | ## How to test 35 | 36 | Run `make program` to program the board with Vivado. 37 | 38 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 39 | -------------------------------------------------------------------------------- /src/eth/example/VCU108/fpga/ip/sgmii_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {SGMII} \ 13 | CONFIG.Physical_Interface {LVDS} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 16 | CONFIG.LvdsRefClk {625} \ 17 | ] [get_ips sgmii_pcs_pma_0] 18 | -------------------------------------------------------------------------------- /src/eth/example/VCU108/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/VCU108/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/VCU118/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for VCU118 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU118 FPGA board. 6 | 7 | The design places looped-back MACs on the BASE-T and QSFP28 ports, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (921600 baud) 11 | * RJ-45 Ethernet port with TI DP83867ISRGZ PHY 12 | * Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES 13 | * QSFP28 14 | * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers 15 | 16 | ## Board details 17 | 18 | * FPGA: xcvu9p-flga2104-2L-e 19 | * USB UART: Silicon Labs CP2105 SCI 20 | * 1000BASE-T PHY: TI DP83867ISRGZ via SGMII 21 | * 25GBASE-R PHY: Soft PCS with GTY transceivers 22 | 23 | ## Licensing 24 | 25 | * Toolchain 26 | * Vivado Enterprise (requires license) 27 | * IP 28 | * No licensed vendor IP or 3rd party IP 29 | 30 | ## How to build 31 | 32 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 33 | 34 | ## How to test 35 | 36 | Run `make program` to program the board with Vivado. 37 | 38 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 39 | -------------------------------------------------------------------------------- /src/eth/example/VCU118/fpga/ip/sgmii_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {SGMII} \ 13 | CONFIG.Physical_Interface {LVDS} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 16 | CONFIG.LvdsRefClk {625} \ 17 | CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ 18 | CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ 19 | CONFIG.Tx_In_Upper_Nibble {0} \ 20 | ] [get_ips sgmii_pcs_pma_0] 21 | -------------------------------------------------------------------------------- /src/eth/example/VCU118/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/VCU118/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/XUPP3R/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for XUP-P3R/XUSP3S 2 | 3 | ## Introduction 4 | 5 | This example design targets the BittWare XUP-P3R/XUSP3S FPGA board. 6 | 7 | The design places looped-back MACs on the QSFP28 ports, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (3 Mbaud) 11 | * QSFP28 12 | * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers 13 | 14 | ## Board details 15 | 16 | * FPGA: xcvu9p-flga2104-2L-e 17 | * XUP-P3R: xcvu9p-flgb2104-2-e 18 | * XUSP3S: xcvu095-ffvb2104-2-e 19 | * USB UART: FTDI FT232R 20 | * 25GBASE-R PHY: Soft PCS with GTY transceivers 21 | 22 | ## Licensing 23 | 24 | * Toolchain 25 | * Vivado Enterprise (requires license) 26 | * IP 27 | * No licensed vendor IP or 3rd party IP 28 | 29 | ## How to build 30 | 31 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 32 | 33 | ## How to test 34 | 35 | Run `make program` to program the board with Vivado. 36 | 37 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 38 | -------------------------------------------------------------------------------- /src/eth/example/XUPP3R/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/XUPP3R/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/ZCU102/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for ZCU102 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU102 FPGA board. 6 | 7 | The design places looped-back MACs on the SFP+ ports, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (2 Mbaud) 11 | * Looped-back UART 12 | * QSFP28 13 | * Looped-back 10GBASE-R MACs via GTH transceivers 14 | 15 | ## Board details 16 | 17 | * FPGA: xczu9eg-ffvb1156-2-e 18 | * USB UART: Silicon Labs CP2108 19 | * 10GBASE-R PHY: Soft PCS with GTH transceivers 20 | 21 | ## Licensing 22 | 23 | * Toolchain 24 | * Vivado Enterprise (requires license) 25 | * IP 26 | * No licensed vendor IP or 3rd party IP 27 | 28 | ## How to build 29 | 30 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 31 | 32 | ## How to test 33 | 34 | Run `make program` to program the board with Vivado. 35 | 36 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 37 | -------------------------------------------------------------------------------- /src/eth/example/ZCU102/fpga/fpga_10g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # SFP+ rate 12 | # 0 for 1G, 1 for 10G 13 | dict set params SFP_RATE "1" 14 | 15 | # apply parameters to top-level 16 | set param_list {} 17 | dict for {name value} $params { 18 | lappend param_list $name=$value 19 | } 20 | 21 | set_property generic $param_list [get_filesets sources_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/ZCU102/fpga/fpga_1g/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # FPGA settings 10 | FPGA_PART = xczu9eg-ffvb1156-2-e 11 | FPGA_TOP = fpga 12 | FPGA_ARCH = zynquplus 13 | 14 | RTL_DIR = ../rtl 15 | LIB_DIR = ../lib 16 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 17 | 18 | # Files for synthesis 19 | SYN_FILES = $(RTL_DIR)/fpga.sv 20 | SYN_FILES += $(RTL_DIR)/fpga_core.sv 21 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f 22 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f 23 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv 24 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f 25 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 26 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 27 | SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv 28 | 29 | # XDC files 30 | XDC_FILES = ../fpga.xdc 31 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl 32 | XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl 33 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl 34 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl 35 | 36 | # IP 37 | IP_TCL_FILES = ../ip/basex_pcs_pma_0.tcl 38 | IP_TCL_FILES += ../ip/basex_pcs_pma_1.tcl 39 | 40 | # Configuration 41 | CONFIG_TCL_FILES = ./config.tcl 42 | 43 | include ../common/vivado.mk 44 | 45 | program: $(FPGA_TOP).bit 46 | echo "open_hw_manager" > program.tcl 47 | echo "connect_hw_server" >> program.tcl 48 | echo "open_hw_target" >> program.tcl 49 | echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl 50 | echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl 51 | echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl 52 | echo "program_hw_devices [current_hw_device]" >> program.tcl 53 | echo "exit" >> program.tcl 54 | vivado -nojournal -nolog -mode batch -source program.tcl 55 | 56 | -------------------------------------------------------------------------------- /src/eth/example/ZCU102/fpga/fpga_1g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # SFP+ rate 12 | # 0 for 1G, 1 for 10G 13 | dict set params SFP_RATE "0" 14 | 15 | # apply parameters to top-level 16 | set param_list {} 17 | dict for {name value} $params { 18 | lappend param_list $name=$value 19 | } 20 | 21 | set_property generic $param_list [get_filesets sources_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/ZCU102/fpga/ip/basex_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {1000BASEX} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.Auto_Negotiation {false} \ 16 | CONFIG.TransceiverControl {false} \ 17 | CONFIG.RefClkRate {156.25} \ 18 | CONFIG.DrpClkRate {62.5} \ 19 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 20 | CONFIG.GT_Location {X0Y10} \ 21 | ] [get_ips basex_pcs_pma_0] 22 | -------------------------------------------------------------------------------- /src/eth/example/ZCU102/fpga/ip/basex_pcs_pma_1.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_1 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {1000BASEX} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.Auto_Negotiation {false} \ 16 | CONFIG.TransceiverControl {false} \ 17 | CONFIG.RefClkRate {156.25} \ 18 | CONFIG.DrpClkRate {62.5} \ 19 | CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \ 20 | CONFIG.GT_Location {X0Y9} \ 21 | ] [get_ips basex_pcs_pma_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/ZCU102/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/ZCU102/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/ZCU106/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for ZCU106 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU106 FPGA board. 6 | 7 | The design places looped-back MACs on the SFP+ ports, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (2 Mbaud) 11 | * QSFP28 12 | * Looped-back 10GBASE-R MACs via GTH transceivers 13 | 14 | ## Board details 15 | 16 | * FPGA: xczu7ev-ffvc1156-2-e 17 | * USB UART: Silicon Labs CP2108 18 | * 10GBASE-R PHY: Soft PCS with GTH transceivers 19 | 20 | ## Licensing 21 | 22 | * Toolchain 23 | * Vivado Standard (enterprise license not required) 24 | * IP 25 | * No licensed vendor IP or 3rd party IP 26 | 27 | ## How to build 28 | 29 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 30 | 31 | ## How to test 32 | 33 | Run `make program` to program the board with Vivado. 34 | 35 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 36 | -------------------------------------------------------------------------------- /src/eth/example/ZCU106/fpga/fpga_10g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # SFP+ rate 12 | # 0 for 1G, 1 for 10G 13 | dict set params SFP_RATE "1" 14 | 15 | # apply parameters to top-level 16 | set param_list {} 17 | dict for {name value} $params { 18 | lappend param_list $name=$value 19 | } 20 | 21 | set_property generic $param_list [get_filesets sources_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/ZCU106/fpga/fpga_1g/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # FPGA settings 10 | FPGA_PART = xczu7ev-ffvc1156-2-e 11 | FPGA_TOP = fpga 12 | FPGA_ARCH = zynquplus 13 | 14 | RTL_DIR = ../rtl 15 | LIB_DIR = ../lib 16 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 17 | 18 | # Files for synthesis 19 | SYN_FILES = $(RTL_DIR)/fpga.sv 20 | SYN_FILES += $(RTL_DIR)/fpga_core.sv 21 | SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f 22 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f 23 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv 24 | SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f 25 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 26 | SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 27 | SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv 28 | 29 | # XDC files 30 | XDC_FILES = ../fpga.xdc 31 | XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl 32 | XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl 33 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl 34 | XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl 35 | 36 | # IP 37 | IP_TCL_FILES = ../ip/basex_pcs_pma_0.tcl 38 | IP_TCL_FILES += ../ip/basex_pcs_pma_1.tcl 39 | 40 | # Configuration 41 | CONFIG_TCL_FILES = ./config.tcl 42 | 43 | include ../common/vivado.mk 44 | 45 | program: $(FPGA_TOP).bit 46 | echo "open_hw_manager" > program.tcl 47 | echo "connect_hw_server" >> program.tcl 48 | echo "open_hw_target" >> program.tcl 49 | echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl 50 | echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl 51 | echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl 52 | echo "program_hw_devices [current_hw_device]" >> program.tcl 53 | echo "exit" >> program.tcl 54 | vivado -nojournal -nolog -mode batch -source program.tcl 55 | 56 | -------------------------------------------------------------------------------- /src/eth/example/ZCU106/fpga/fpga_1g/config.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | set params [dict create] 10 | 11 | # SFP+ rate 12 | # 0 for 1G, 1 for 10G 13 | dict set params SFP_RATE "0" 14 | 15 | # apply parameters to top-level 16 | set param_list {} 17 | dict for {name value} $params { 18 | lappend param_list $name=$value 19 | } 20 | 21 | set_property generic $param_list [get_filesets sources_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/ZCU106/fpga/ip/basex_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {1000BASEX} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.Auto_Negotiation {false} \ 16 | CONFIG.TransceiverControl {false} \ 17 | CONFIG.RefClkRate {156.25} \ 18 | CONFIG.DrpClkRate {62.5} \ 19 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 20 | CONFIG.GT_Location {X0Y10} \ 21 | ] [get_ips basex_pcs_pma_0] 22 | -------------------------------------------------------------------------------- /src/eth/example/ZCU106/fpga/ip/basex_pcs_pma_1.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_1 10 | 11 | set_property -dict [list \ 12 | CONFIG.Standard {1000BASEX} \ 13 | CONFIG.Physical_Interface {Transceiver} \ 14 | CONFIG.Management_Interface {false} \ 15 | CONFIG.Auto_Negotiation {false} \ 16 | CONFIG.TransceiverControl {false} \ 17 | CONFIG.RefClkRate {156.25} \ 18 | CONFIG.DrpClkRate {62.5} \ 19 | CONFIG.SupportLevel {Include_Shared_Logic_in_Example_Design} \ 20 | CONFIG.GT_Location {X0Y9} \ 21 | ] [get_ips basex_pcs_pma_1] 22 | -------------------------------------------------------------------------------- /src/eth/example/ZCU106/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/ZCU106/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/ZCU111/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for ZCU111 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU111 FPGA board. 6 | 7 | The design places looped-back MACs on the SFP+ ports, as well as XFCP on the USB UART for monitoring and control. 8 | 9 | * USB UART 10 | * XFCP (3 Mbaud) 11 | * QSFP28 12 | * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers 13 | 14 | ## Board details 15 | 16 | * FPGA: xczu28dr-ffvg1517-2-e 17 | * USB UART: FTDI FT4232H 18 | * 25GBASE-R PHY: Soft PCS with GTY transceivers 19 | 20 | ## Licensing 21 | 22 | * Toolchain 23 | * Vivado Enterprise (requires license) 24 | * IP 25 | * No licensed vendor IP or 3rd party IP 26 | 27 | ## How to build 28 | 29 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 30 | 31 | ## Board configuration 32 | 33 | For correct operation, several DIP switches need to be set correctly. 34 | 35 | DIP switch settings: 36 | 37 | * SW6: all ON (select JTAG boot) 38 | 39 | ## How to test 40 | 41 | Run `make program` to program the board with Vivado. 42 | 43 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 44 | -------------------------------------------------------------------------------- /src/eth/example/ZCU111/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/ZCU111/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/example/fb2CG/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Taxi Example Design for fb2CG@KU15P 2 | 3 | ## Introduction 4 | 5 | This example design targets the Silicom fb2CG@KU15P FPGA board. 6 | 7 | The design places looped-back MACs on the QSFP28 ports. 8 | 9 | * QSFP28 10 | * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers 11 | 12 | ## Board details 13 | 14 | * FPGA: xcku15p-ffve1760-2-e 15 | * 25GBASE-R PHY: Soft PCS with GTY transceivers 16 | 17 | ## Licensing 18 | 19 | * Toolchain 20 | * Vivado Enterprise (requires license) 21 | * IP 22 | * No licensed vendor IP or 3rd party IP 23 | 24 | ## How to build 25 | 26 | Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. 27 | 28 | ## How to test 29 | 30 | Run `make program` to program the board with Vivado. 31 | 32 | To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. 33 | -------------------------------------------------------------------------------- /src/eth/example/fb2CG/fpga/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../../../../ -------------------------------------------------------------------------------- /src/eth/example/fb2CG/fpga/tb/fpga_core/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: MIT 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = fpga_core 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv 29 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv 30 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_led_sreg.sv 31 | 32 | # handle file list files 33 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 34 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 35 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 36 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 37 | 38 | # module parameters 39 | export PARAM_SIM := "1'b1" 40 | export PARAM_VENDOR := "\"XILINX\"" 41 | export PARAM_FAMILY := "\"kintexuplus\"" 42 | 43 | ifeq ($(SIM), icarus) 44 | PLUSARGS += -fst 45 | 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 47 | else ifeq ($(SIM), verilator) 48 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 49 | 50 | ifeq ($(WAVES), 1) 51 | COMPILE_ARGS += --trace-fst 52 | VERILATOR_TRACE = 1 53 | endif 54 | endif 55 | 56 | include $(shell cocotb-config --makefiles)/Makefile.sim 57 | -------------------------------------------------------------------------------- /src/eth/example/fb2CG/fpga/tb/fpga_core/baser.py: -------------------------------------------------------------------------------- 1 | ../../lib/taxi/src/eth/tb/baser.py -------------------------------------------------------------------------------- /src/eth/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../ -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_10g.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_10g.sv 2 | taxi_axis_xgmii_rx_64.sv 3 | taxi_axis_xgmii_tx_64.sv 4 | taxi_axis_xgmii_rx_32.sv 5 | taxi_axis_xgmii_tx_32.sv 6 | taxi_eth_mac_stats.f 7 | taxi_mac_ctrl_tx.sv 8 | taxi_mac_ctrl_rx.sv 9 | taxi_mac_pause_ctrl_tx.sv 10 | taxi_mac_pause_ctrl_rx.sv 11 | ../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv 12 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 13 | ../lib/taxi/src/sync/rtl/taxi_sync_signal.sv 14 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_10g_fifo.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_10g_fifo.sv 2 | taxi_eth_mac_10g.f 3 | ../lib/taxi/src/ptp/rtl/taxi_ptp_clock_cdc.sv 4 | ../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f 5 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_1g.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_1g.sv 2 | taxi_axis_gmii_rx.sv 3 | taxi_axis_gmii_tx.sv 4 | taxi_eth_mac_stats.f 5 | taxi_mac_ctrl_tx.sv 6 | taxi_mac_ctrl_rx.sv 7 | taxi_mac_pause_ctrl_tx.sv 8 | taxi_mac_pause_ctrl_rx.sv 9 | ../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv 10 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 11 | ../lib/taxi/src/sync/rtl/taxi_sync_signal.sv 12 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_1g_fifo.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_1g_fifo.sv 2 | taxi_eth_mac_1g.f 3 | ../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_1g_gmii.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_1g_gmii.sv 2 | taxi_eth_mac_1g.f 3 | taxi_gmii_phy_if.f 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_1g_gmii_fifo.sv 2 | taxi_eth_mac_1g_gmii.f 3 | ../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_1g_rgmii.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_1g_rgmii.sv 2 | taxi_eth_mac_1g.f 3 | taxi_rgmii_phy_if.f 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_1g_rgmii_fifo.sv 2 | taxi_eth_mac_1g_rgmii.f 3 | ../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_mii.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_mii.sv 2 | taxi_eth_mac_1g.f 3 | taxi_mii_phy_if.f 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_mii_fifo.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_mii_fifo.sv 2 | taxi_eth_mac_mii.f 3 | ../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_phy_10g.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_phy_10g.sv 2 | taxi_eth_mac_phy_10g_rx.f 3 | taxi_eth_mac_phy_10g_tx.f 4 | taxi_eth_mac_stats.f 5 | taxi_mac_ctrl_tx.sv 6 | taxi_mac_ctrl_rx.sv 7 | taxi_mac_pause_ctrl_tx.sv 8 | taxi_mac_pause_ctrl_rx.sv 9 | ../lib/taxi/src/sync/rtl/taxi_sync_signal.sv 10 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_phy_10g_fifo.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_phy_10g_fifo.sv 2 | taxi_eth_mac_phy_10g.f 3 | ../lib/taxi/src/ptp/rtl/taxi_ptp_clock_cdc.sv 4 | ../lib/taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.f 5 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_phy_10g_rx.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_phy_10g_rx.sv 2 | taxi_eth_phy_10g_rx_if.f 3 | taxi_axis_baser_rx_64.sv 4 | ../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv 5 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 6 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_phy_10g_tx.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_phy_10g_tx.sv 2 | taxi_eth_phy_10g_tx_if.f 3 | taxi_axis_baser_tx_64.sv 4 | ../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv 5 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 6 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_mac_stats.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_stats.sv 2 | ../lib/taxi/src/axis/rtl/taxi_axis_async_fifo.f 3 | ../lib/taxi/src/axis/rtl/taxi_axis_arb_mux.f 4 | ../lib/taxi/src/stats/rtl/taxi_stats_collect.sv 5 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_phy_10g.f: -------------------------------------------------------------------------------- 1 | taxi_eth_phy_10g.sv 2 | taxi_eth_phy_10g_rx.f 3 | taxi_eth_phy_10g_tx.f 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_phy_10g_rx.f: -------------------------------------------------------------------------------- 1 | taxi_eth_phy_10g_rx.sv 2 | taxi_eth_phy_10g_rx_if.f 3 | taxi_xgmii_baser_dec_64.sv 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_phy_10g_rx_if.f: -------------------------------------------------------------------------------- 1 | taxi_eth_phy_10g_rx_if.sv 2 | taxi_eth_phy_10g_rx_ber_mon.sv 3 | taxi_eth_phy_10g_rx_frame_sync.sv 4 | taxi_eth_phy_10g_rx_watchdog.sv 5 | ../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv 6 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_phy_10g_tx.f: -------------------------------------------------------------------------------- 1 | taxi_eth_phy_10g_tx.sv 2 | taxi_eth_phy_10g_tx_if.f 3 | taxi_xgmii_baser_enc_64.sv 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_eth_phy_10g_tx_if.f: -------------------------------------------------------------------------------- 1 | taxi_eth_phy_10g_tx_if.sv 2 | ../lib/taxi/src/lfsr/rtl/taxi_lfsr.sv 3 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_gmii_phy_if.f: -------------------------------------------------------------------------------- 1 | taxi_gmii_phy_if.sv 2 | ../lib/taxi/src/io/rtl/taxi_ssio_sdr_in.sv 3 | ../lib/taxi/src/io/rtl/taxi_ssio_sdr_out.sv 4 | ../lib/taxi/src/io/rtl/taxi_oddr.sv 5 | ../lib/taxi/src/sync/rtl/taxi_sync_reset.sv 6 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_mii_phy_if.f: -------------------------------------------------------------------------------- 1 | taxi_mii_phy_if.sv 2 | ../lib/taxi/src/io/rtl/taxi_ssio_sdr_in.sv 3 | ../lib/taxi/src/sync/rtl/taxi_sync_reset.sv 4 | -------------------------------------------------------------------------------- /src/eth/rtl/taxi_rgmii_phy_if.f: -------------------------------------------------------------------------------- 1 | taxi_rgmii_phy_if.sv 2 | ../lib/taxi/src/io/rtl/taxi_ssio_ddr_in.sv 3 | ../lib/taxi/src/io/rtl/taxi_iddr.sv 4 | ../lib/taxi/src/io/rtl/taxi_oddr.sv 5 | ../lib/taxi/src/sync/rtl/taxi_sync_reset.sv 6 | -------------------------------------------------------------------------------- /src/eth/rtl/us/taxi_eth_mac_25g_us.f: -------------------------------------------------------------------------------- 1 | taxi_eth_mac_25g_us.sv 2 | taxi_eth_mac_25g_us_ch.sv 3 | taxi_eth_phy_25g_us_gt.f 4 | taxi_eth_phy_25g_us_gt_ll.f 5 | ../taxi_eth_mac_phy_10g.f 6 | -------------------------------------------------------------------------------- /src/eth/rtl/us/taxi_eth_phy_25g_us_gt.f: -------------------------------------------------------------------------------- 1 | taxi_eth_phy_25g_us_gt.sv 2 | ../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv 3 | ../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv 4 | ../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv 5 | ../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv 6 | ../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv 7 | -------------------------------------------------------------------------------- /src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.f: -------------------------------------------------------------------------------- 1 | taxi_eth_phy_25g_us_gt_ll.sv 2 | ../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv 3 | ../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv 4 | ../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv 5 | ../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv 6 | ../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv 7 | -------------------------------------------------------------------------------- /src/eth/syn/vivado/taxi_eth_mac_fifo.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2019-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # Ethernet MAC with FIFO timing constraints 10 | 11 | foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "taxi_eth_mac_(10g|1g)_((gmii|rgmii|mii)_)?fifo(__\w+__\d+)?" || 12 | REF_NAME =~ "taxi_eth_mac_(10g|1g)_((gmii|rgmii|mii)_)?fifo(__\w+__\d+)?")}] { 13 | puts "Inserting timing constraints for Ethernet MAC with FIFO instance $inst" 14 | 15 | set sync_ffs [get_cells -hier -regexp ".*/rx_sync_reg_\[1234\]_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] 16 | 17 | if {[llength $sync_ffs]} { 18 | set_property ASYNC_REG TRUE $sync_ffs 19 | 20 | set src_clk [get_clocks -of_objects [get_pins $inst/rx_sync_reg_1_reg[*]/C]] 21 | 22 | set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] 23 | 24 | set_max_delay -from [get_cells $inst/rx_sync_reg_1_reg[*]] -to [get_cells $inst/rx_sync_reg_2_reg[*]] -datapath_only $src_clk_period 25 | } 26 | 27 | set sync_ffs [get_cells -hier -regexp ".*/tx_sync_reg_\[1234\]_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] 28 | 29 | if {[llength $sync_ffs]} { 30 | set_property ASYNC_REG TRUE $sync_ffs 31 | 32 | set src_clk [get_clocks -of_objects [get_pins $inst/tx_sync_reg_1_reg[*]/C]] 33 | 34 | set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] 35 | 36 | set_max_delay -from [get_cells $inst/tx_sync_reg_1_reg[*]] -to [get_cells $inst/tx_sync_reg_2_reg[*]] -datapath_only $src_clk_period 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /src/eth/syn/vivado/taxi_rgmii_phy_if.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2019-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # RGMII PHY IF timing constraints 10 | 11 | foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "taxi_rgmii_phy_if(__\w+__\d+)?" || 12 | REF_NAME =~ "taxi_rgmii_phy_if(__\w+__\d+)?")}] { 13 | puts "Inserting timing constraints for taxi_rgmii_phy_if instance $inst" 14 | 15 | # clock output 16 | set_property ASYNC_REG TRUE [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst] 17 | 18 | set src_clk [get_clocks -of_objects [get_pins $inst/rgmii_tx_clk_1_reg_reg/C]] 19 | 20 | set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] 21 | 22 | set_max_delay -from [get_cells $inst/rgmii_tx_clk_1_reg_reg] -to [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4] 23 | set_max_delay -from [get_cells $inst/rgmii_tx_clk_2_reg_reg] -to [get_cells $inst/clk_oddr_inst/oddr[0].oddr_inst] -datapath_only [expr $src_clk_period/4] 24 | } 25 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_axis_baser_rx_64/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2021-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axis_baser_rx_64 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_DATA_W := 64 38 | export PARAM_HDR_W := 2 39 | export PARAM_GBX_IF_EN := 1 40 | export PARAM_PTP_TS_EN := 1 41 | export PARAM_PTP_TS_FMT_TOD := 1 42 | 43 | ifeq ($(SIM), icarus) 44 | PLUSARGS += -fst 45 | 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 47 | else ifeq ($(SIM), verilator) 48 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 49 | 50 | ifeq ($(WAVES), 1) 51 | COMPILE_ARGS += --trace-fst 52 | VERILATOR_TRACE = 1 53 | endif 54 | endif 55 | 56 | include $(shell cocotb-config --makefiles)/Makefile.sim 57 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_axis_baser_rx_64/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /src/eth/tb/taxi_axis_baser_tx_64/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /src/eth/tb/taxi_axis_gmii_rx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axis_gmii_rx 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_DATA_W := 8 38 | export PARAM_PTP_TS_EN := 1 39 | export PARAM_PTP_TS_W := 96 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_axis_gmii_tx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axis_gmii_tx 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_DATA_W := 8 38 | export PARAM_PADDING_EN := 1 39 | export PARAM_MIN_FRAME_LEN := 64 40 | export PARAM_PTP_TS_EN := 1 41 | export PARAM_PTP_TS_W := 96 42 | export PARAM_TX_TAG_W := 16 43 | export PARAM_TX_CPL_CTRL_IN_TUSER := 1 44 | 45 | ifeq ($(SIM), icarus) 46 | PLUSARGS += -fst 47 | 48 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 49 | else ifeq ($(SIM), verilator) 50 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 51 | 52 | ifeq ($(WAVES), 1) 53 | COMPILE_ARGS += --trace-fst 54 | VERILATOR_TRACE = 1 55 | endif 56 | endif 57 | 58 | include $(shell cocotb-config --makefiles)/Makefile.sim 59 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_axis_xgmii_rx_32/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axis_xgmii_rx_32 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_DATA_W := 32 38 | export PARAM_PTP_TS_EN := 1 39 | export PARAM_PTP_TS_W := 96 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_axis_xgmii_rx_64/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_axis_xgmii_rx_64 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/lfsr/rtl/taxi_lfsr.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_DATA_W := 64 38 | export PARAM_PTP_TS_EN := 1 39 | export PARAM_PTP_TS_FMT_TOD := 1 40 | export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96) 41 | 42 | ifeq ($(SIM), icarus) 43 | PLUSARGS += -fst 44 | 45 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 46 | else ifeq ($(SIM), verilator) 47 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 48 | 49 | ifeq ($(WAVES), 1) 50 | COMPILE_ARGS += --trace-fst 51 | VERILATOR_TRACE = 1 52 | endif 53 | endif 54 | 55 | include $(shell cocotb-config --makefiles)/Makefile.sim 56 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_eth_mac_phy_10g/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /src/eth/tb/taxi_eth_mac_phy_10g_fifo/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /src/eth/tb/taxi_eth_phy_10g/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /src/eth/tb/taxi_mac_ctrl_rx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_mac_ctrl_rx 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | export PARAM_DATA_W := 8 37 | export PARAM_ID_W := 8 38 | export PARAM_DEST_W := 8 39 | export PARAM_USER_W := 1 40 | export PARAM_USE_READY := 1 41 | export PARAM_MCF_PARAMS_SIZE := 18 42 | 43 | ifeq ($(SIM), icarus) 44 | PLUSARGS += -fst 45 | 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 47 | else ifeq ($(SIM), verilator) 48 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 49 | 50 | ifeq ($(WAVES), 1) 51 | COMPILE_ARGS += --trace-fst 52 | VERILATOR_TRACE = 1 53 | endif 54 | endif 55 | 56 | include $(shell cocotb-config --makefiles)/Makefile.sim 57 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_mac_ctrl_tx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_mac_ctrl_tx 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | export PARAM_DATA_W := 8 37 | export PARAM_ID_W := 8 38 | export PARAM_DEST_W := 8 39 | export PARAM_USER_W := 1 40 | export PARAM_MCF_PARAMS_SIZE := 18 41 | 42 | ifeq ($(SIM), icarus) 43 | PLUSARGS += -fst 44 | 45 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 46 | else ifeq ($(SIM), verilator) 47 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 48 | 49 | ifeq ($(WAVES), 1) 50 | COMPILE_ARGS += --trace-fst 51 | VERILATOR_TRACE = 1 52 | endif 53 | endif 54 | 55 | include $(shell cocotb-config --makefiles)/Makefile.sim 56 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_mac_pause_ctrl_rx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_mac_pause_ctrl_rx 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_MCF_PARAMS_SIZE := 18 35 | export PARAM_PFC_EN := "1'b1" 36 | 37 | ifeq ($(SIM), icarus) 38 | PLUSARGS += -fst 39 | 40 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 41 | else ifeq ($(SIM), verilator) 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 43 | 44 | ifeq ($(WAVES), 1) 45 | COMPILE_ARGS += --trace-fst 46 | VERILATOR_TRACE = 1 47 | endif 48 | endif 49 | 50 | include $(shell cocotb-config --makefiles)/Makefile.sim 51 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_mac_pause_ctrl_tx/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_mac_pause_ctrl_tx 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_MCF_PARAMS_SIZE := 18 35 | export PARAM_PFC_EN := "1'b1" 36 | 37 | ifeq ($(SIM), icarus) 38 | PLUSARGS += -fst 39 | 40 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 41 | else ifeq ($(SIM), verilator) 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 43 | 44 | ifeq ($(WAVES), 1) 45 | COMPILE_ARGS += --trace-fst 46 | VERILATOR_TRACE = 1 47 | endif 48 | endif 49 | 50 | include $(shell cocotb-config --makefiles)/Makefile.sim 51 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_xgmii_baser_dec_64/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2021-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_xgmii_baser_dec_64 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_DATA_W := 64 35 | export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 ) 36 | export PARAM_HDR_W := 2 37 | export PARAM_GBX_IF_EN := 0 38 | 39 | ifeq ($(SIM), icarus) 40 | PLUSARGS += -fst 41 | 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 43 | else ifeq ($(SIM), verilator) 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 45 | 46 | ifeq ($(WAVES), 1) 47 | COMPILE_ARGS += --trace-fst 48 | VERILATOR_TRACE = 1 49 | endif 50 | endif 51 | 52 | include $(shell cocotb-config --makefiles)/Makefile.sim -------------------------------------------------------------------------------- /src/eth/tb/taxi_xgmii_baser_dec_64/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /src/eth/tb/taxi_xgmii_baser_enc_64/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2021-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_xgmii_baser_enc_64 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_DATA_W := 64 35 | export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 ) 36 | export PARAM_HDR_W := 2 37 | export PARAM_GBX_IF_EN := 0 38 | 39 | ifeq ($(SIM), icarus) 40 | PLUSARGS += -fst 41 | 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 43 | else ifeq ($(SIM), verilator) 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 45 | 46 | ifeq ($(WAVES), 1) 47 | COMPILE_ARGS += --trace-fst 48 | VERILATOR_TRACE = 1 49 | endif 50 | endif 51 | 52 | include $(shell cocotb-config --makefiles)/Makefile.sim 53 | -------------------------------------------------------------------------------- /src/eth/tb/taxi_xgmii_baser_enc_64/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /src/hip/rtl/us/taxi_gt_qpll_reset.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * GT QPLL reset controller for UltraScale/UltraScale+ GTH/GTY 17 | */ 18 | module taxi_gt_qpll_reset # 19 | ( 20 | parameter logic QPLL_PD = 1'b0, 21 | parameter CNT_W = 8 22 | ) 23 | ( 24 | input wire logic clk, 25 | input wire logic rst, 26 | 27 | /* 28 | * GT 29 | */ 30 | output wire logic gt_qpll_reset_out, 31 | output wire logic gt_qpll_pd_out, 32 | input wire logic gt_qpll_lock_in, 33 | 34 | /* 35 | * Control/status 36 | */ 37 | input wire logic qpll_reset_in = 1'b0, 38 | input wire logic qpll_pd_in = QPLL_PD, 39 | output wire logic qpll_lock_out 40 | ); 41 | 42 | logic qpll_reset_reg = 1'b1; 43 | logic qpll_pd_reg = QPLL_PD; 44 | 45 | logic [CNT_W-1:0] qpll_reset_cnt_reg = '0; 46 | 47 | assign gt_qpll_reset_out = qpll_reset_reg; 48 | assign gt_qpll_pd_out = qpll_pd_reg; 49 | 50 | always_ff @(posedge clk) begin 51 | qpll_pd_reg <= qpll_pd_in; 52 | 53 | if (&qpll_reset_cnt_reg) begin 54 | qpll_reset_reg <= 1'b0; 55 | end else begin 56 | qpll_reset_cnt_reg <= qpll_reset_cnt_reg + 1; 57 | qpll_reset_reg <= 1'b1; 58 | end 59 | 60 | if (qpll_reset_in || qpll_pd_reg) begin 61 | qpll_reset_cnt_reg <= 0; 62 | end 63 | 64 | if (rst) begin 65 | qpll_reset_reg <= 1'b1; 66 | qpll_pd_reg <= QPLL_PD; 67 | qpll_reset_cnt_reg <= '0; 68 | end 69 | end 70 | 71 | taxi_sync_signal #( 72 | .WIDTH(1), 73 | .N(2) 74 | ) 75 | qpll_lock_sync_inst ( 76 | .clk(clk), 77 | .in(gt_qpll_lock_in), 78 | .out(qpll_lock_out) 79 | ); 80 | 81 | endmodule 82 | 83 | `resetall 84 | -------------------------------------------------------------------------------- /src/io/rtl/taxi_debounce_switch.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2014-2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * Synchronizes switch and button inputs with a slow sampled shift register 17 | */ 18 | module taxi_debounce_switch #( 19 | // width of the input and output signals 20 | parameter WIDTH = 1, 21 | // length of shift register 22 | parameter N = 3, 23 | // clock division factor 24 | parameter RATE = 125000 25 | ) 26 | ( 27 | input wire logic clk, 28 | input wire logic rst, 29 | 30 | input wire logic [WIDTH-1:0] in, 31 | output wire logic [WIDTH-1:0] out 32 | ); 33 | 34 | localparam CNT_W = $clog2(RATE); 35 | 36 | logic [CNT_W-1:0] cnt_reg = '0; 37 | logic strb_reg = 1'b0; 38 | 39 | logic [N-1:0] debounce_reg[WIDTH-1:0]; 40 | 41 | logic [WIDTH-1:0] state_reg = '0; 42 | 43 | assign out = state_reg; 44 | 45 | always_ff @(posedge clk) begin 46 | strb_reg <= 1'b0; 47 | 48 | if (cnt_reg) begin 49 | cnt_reg <= cnt_reg - 1; 50 | end else begin 51 | cnt_reg <= RATE-1; 52 | strb_reg <= 1'b1; 53 | end 54 | 55 | if (strb_reg) begin 56 | for (integer k = 0; k < WIDTH; k = k + 1) begin 57 | debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; 58 | end 59 | end 60 | 61 | for (integer k = 0; k < WIDTH; k = k + 1) begin 62 | if (|debounce_reg[k] == 0) begin 63 | state_reg[k] <= 1'b0; 64 | end else if (&debounce_reg[k] == 1) begin 65 | state_reg[k] <= 1'b1; 66 | end 67 | end 68 | 69 | if (rst) begin 70 | cnt_reg <= '0; 71 | state_reg <= '0; 72 | 73 | for (integer k = 0; k < WIDTH; k = k + 1) begin 74 | debounce_reg[k] <= '0; 75 | end 76 | end 77 | end 78 | 79 | endmodule 80 | 81 | `resetall 82 | -------------------------------------------------------------------------------- /src/io/rtl/taxi_ssio_ddr_out.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2016-2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * Generic source synchronous DDR output 17 | */ 18 | module taxi_ssio_ddr_out # 19 | ( 20 | // simulation (set to avoid vendor primitives) 21 | parameter logic SIM = 1'b0, 22 | // vendor ("GENERIC", "XILINX", "ALTERA") 23 | parameter string VENDOR = "XILINX", 24 | // device family 25 | parameter string FAMILY = "virtex7", 26 | // Use 90 degree clock for transmit 27 | parameter logic USE_CLK90 = 1'b1, 28 | // Width of register in bits 29 | parameter WIDTH = 1 30 | ) 31 | ( 32 | input wire logic clk, 33 | input wire logic clk90, 34 | 35 | input wire logic [WIDTH-1:0] input_d1, 36 | input wire logic [WIDTH-1:0] input_d2, 37 | 38 | output wire logic output_clk, 39 | output wire logic [WIDTH-1:0] output_q 40 | ); 41 | 42 | wire ref_clk = USE_CLK90 ? clk90 : clk; 43 | 44 | taxi_oddr #( 45 | .SIM(SIM), 46 | .VENDOR(VENDOR), 47 | .FAMILY(FAMILY), 48 | .WIDTH(1) 49 | ) 50 | clk_oddr_inst ( 51 | .clk(ref_clk), 52 | .d1(1'b1), 53 | .d2(1'b0), 54 | .q(output_clk) 55 | ); 56 | 57 | taxi_oddr #( 58 | .SIM(SIM), 59 | .VENDOR(VENDOR), 60 | .FAMILY(FAMILY), 61 | .WIDTH(WIDTH) 62 | ) 63 | data_oddr_inst ( 64 | .clk(clk), 65 | .d1(input_d1), 66 | .d2(input_d2), 67 | .q(output_q) 68 | ); 69 | 70 | endmodule 71 | 72 | `resetall 73 | -------------------------------------------------------------------------------- /src/io/rtl/taxi_ssio_sdr_out.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2016-2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * Generic source synchronous SDR output 17 | */ 18 | module taxi_ssio_sdr_out # 19 | ( 20 | // simulation (set to avoid vendor primitives) 21 | parameter logic SIM = 1'b0, 22 | // vendor ("GENERIC", "XILINX", "ALTERA") 23 | parameter string VENDOR = "XILINX", 24 | // device family 25 | parameter string FAMILY = "virtex7", 26 | // Width of register in bits 27 | parameter WIDTH = 1 28 | ) 29 | ( 30 | input wire logic clk, 31 | 32 | input wire logic [WIDTH-1:0] input_d, 33 | 34 | output wire logic output_clk, 35 | output wire logic [WIDTH-1:0] output_q 36 | ); 37 | 38 | taxi_oddr #( 39 | .SIM(SIM), 40 | .VENDOR(VENDOR), 41 | .FAMILY(FAMILY), 42 | .WIDTH(1) 43 | ) 44 | clk_oddr_inst ( 45 | .clk(clk), 46 | .d1(1'b0), 47 | .d2(1'b1), 48 | .q(output_clk) 49 | ); 50 | 51 | (* IOB = "TRUE" *) 52 | logic [WIDTH-1:0] output_q_reg = '0; 53 | 54 | assign output_q = output_q_reg; 55 | 56 | always_ff @(posedge clk) begin 57 | output_q_reg <= input_d; 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /src/lfsr/tb/taxi_lfsr/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | 18 | DUT = taxi_lfsr 19 | COCOTB_TEST_MODULES = test_$(DUT) 20 | COCOTB_TOPLEVEL = $(DUT) 21 | MODULE = $(COCOTB_TEST_MODULES) 22 | TOPLEVEL = $(COCOTB_TOPLEVEL) 23 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 24 | 25 | # handle file list files 26 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 27 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 28 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 29 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 30 | 31 | # module parameters 32 | export PARAM_LFSR_W ?= 32 33 | export PARAM_LFSR_POLY ?= "32'h4c11db7" 34 | export PARAM_LFSR_GALOIS ?= "1'b1" 35 | export PARAM_LFSR_FEED_FORWARD ?= "1'b0" 36 | export PARAM_REVERSE ?= "1'b1" 37 | export PARAM_DATA_W ?= 8 38 | 39 | ifeq ($(SIM), icarus) 40 | PLUSARGS += -fst 41 | 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 43 | else ifeq ($(SIM), verilator) 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 45 | 46 | ifeq ($(WAVES), 1) 47 | COMPILE_ARGS += --trace-fst 48 | VERILATOR_TRACE = 1 49 | endif 50 | endif 51 | 52 | include $(shell cocotb-config --makefiles)/Makefile.sim 53 | -------------------------------------------------------------------------------- /src/lfsr/tb/taxi_lfsr_crc/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | 18 | DUT = taxi_lfsr_crc 19 | COCOTB_TEST_MODULES = test_$(DUT) 20 | COCOTB_TOPLEVEL = $(DUT) 21 | MODULE = $(COCOTB_TEST_MODULES) 22 | TOPLEVEL = $(COCOTB_TOPLEVEL) 23 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 24 | VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv 25 | 26 | # handle file list files 27 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 28 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 29 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 30 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 31 | 32 | # module parameters 33 | export PARAM_LFSR_W ?= 32 34 | export PARAM_LFSR_POLY ?= "32'h4c11db7" 35 | export PARAM_LFSR_INIT ?= "'1" 36 | export PARAM_LFSR_GALOIS ?= "1'b1" 37 | export PARAM_REVERSE ?= "1'b1" 38 | export PARAM_INVERT ?= "1'b1" 39 | export PARAM_DATA_W ?= 8 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/lfsr/tb/taxi_lfsr_descramble/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | 18 | DUT = taxi_lfsr_descramble 19 | COCOTB_TEST_MODULES = test_$(DUT) 20 | COCOTB_TOPLEVEL = $(DUT) 21 | MODULE = $(COCOTB_TEST_MODULES) 22 | TOPLEVEL = $(COCOTB_TOPLEVEL) 23 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 24 | VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv 25 | 26 | # handle file list files 27 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 28 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 29 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 30 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 31 | 32 | # module parameters 33 | export PARAM_LFSR_W ?= 58 34 | export PARAM_LFSR_POLY ?= "58'h8000000001" 35 | export PARAM_LFSR_INIT ?= "'1" 36 | export PARAM_LFSR_GALOIS ?= "1'b0" 37 | export PARAM_REVERSE ?= "1'b1" 38 | export PARAM_DATA_W ?= 8 39 | 40 | ifeq ($(SIM), icarus) 41 | PLUSARGS += -fst 42 | 43 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 44 | else ifeq ($(SIM), verilator) 45 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 46 | 47 | ifeq ($(WAVES), 1) 48 | COMPILE_ARGS += --trace-fst 49 | VERILATOR_TRACE = 1 50 | endif 51 | endif 52 | 53 | include $(shell cocotb-config --makefiles)/Makefile.sim 54 | -------------------------------------------------------------------------------- /src/lfsr/tb/taxi_lfsr_prbs_check/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | 18 | DUT = taxi_lfsr_prbs_check 19 | COCOTB_TEST_MODULES = test_$(DUT) 20 | COCOTB_TOPLEVEL = $(DUT) 21 | MODULE = $(COCOTB_TEST_MODULES) 22 | TOPLEVEL = $(COCOTB_TOPLEVEL) 23 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 24 | VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv 25 | 26 | # handle file list files 27 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 28 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 29 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 30 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 31 | 32 | # module parameters 33 | export PARAM_LFSR_W ?= 31 34 | export PARAM_LFSR_POLY ?= "31'h10000001" 35 | export PARAM_LFSR_INIT ?= "'1" 36 | export PARAM_LFSR_GALOIS ?= "1'b0" 37 | export PARAM_REVERSE ?= "1'b0" 38 | export PARAM_INVERT ?= "1'b1" 39 | export PARAM_DATA_W ?= 8 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/lfsr/tb/taxi_lfsr_prbs_gen/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | 18 | DUT = taxi_lfsr_prbs_gen 19 | COCOTB_TEST_MODULES = test_$(DUT) 20 | COCOTB_TOPLEVEL = $(DUT) 21 | MODULE = $(COCOTB_TEST_MODULES) 22 | TOPLEVEL = $(COCOTB_TOPLEVEL) 23 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 24 | VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv 25 | 26 | # handle file list files 27 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 28 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 29 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 30 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 31 | 32 | # module parameters 33 | export PARAM_LFSR_W ?= 31 34 | export PARAM_LFSR_POLY ?= "31'h10000001" 35 | export PARAM_LFSR_INIT ?= "'1" 36 | export PARAM_LFSR_GALOIS ?= "1'b0" 37 | export PARAM_REVERSE ?= "1'b0" 38 | export PARAM_INVERT ?= "1'b1" 39 | export PARAM_DATA_W ?= 8 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/lfsr/tb/taxi_lfsr_scramble/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | 18 | DUT = taxi_lfsr_scramble 19 | COCOTB_TEST_MODULES = test_$(DUT) 20 | COCOTB_TOPLEVEL = $(DUT) 21 | MODULE = $(COCOTB_TEST_MODULES) 22 | TOPLEVEL = $(COCOTB_TOPLEVEL) 23 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 24 | VERILOG_SOURCES += $(RTL_DIR)/taxi_lfsr.sv 25 | 26 | # handle file list files 27 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 28 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 29 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 30 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 31 | 32 | # module parameters 33 | export PARAM_LFSR_W ?= 58 34 | export PARAM_LFSR_POLY ?= "58'h8000000001" 35 | export PARAM_LFSR_INIT ?= "'1" 36 | export PARAM_LFSR_GALOIS ?= "1'b0" 37 | export PARAM_REVERSE ?= "1'b1" 38 | export PARAM_DATA_W ?= 8 39 | 40 | ifeq ($(SIM), icarus) 41 | PLUSARGS += -fst 42 | 43 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 44 | else ifeq ($(SIM), verilator) 45 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 46 | 47 | ifeq ($(WAVES), 1) 48 | COMPILE_ARGS += --trace-fst 49 | VERILATOR_TRACE = 1 50 | endif 51 | endif 52 | 53 | include $(shell cocotb-config --makefiles)/Makefile.sim 54 | -------------------------------------------------------------------------------- /src/lss/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../ -------------------------------------------------------------------------------- /src/lss/rtl/taxi_uart.f: -------------------------------------------------------------------------------- 1 | taxi_uart.sv 2 | taxi_uart_rx.sv 3 | taxi_uart_tx.sv 4 | taxi_uart_brg.sv 5 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 6 | -------------------------------------------------------------------------------- /src/lss/rtl/taxi_uart_brg.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream UART baud rate generator 17 | */ 18 | module taxi_uart_brg #( 19 | parameter PRE_W = 16 20 | ) 21 | ( 22 | input wire logic clk, 23 | input wire logic rst, 24 | 25 | /* 26 | * Baud rate pulse out 27 | */ 28 | output wire logic baud_clk, 29 | 30 | /* 31 | * Configuration 32 | */ 33 | input wire logic [PRE_W-1:0] prescale 34 | ); 35 | 36 | localparam FRAC_W = 3; 37 | localparam INT_W = PRE_W - FRAC_W; 38 | 39 | logic [INT_W-1:0] prescale_int_reg = 0; 40 | logic [FRAC_W-1:0] prescale_frac_reg = 0; 41 | logic frac_ovf_reg = 1'b0; 42 | logic baud_clk_reg = 1'b0; 43 | 44 | assign baud_clk = baud_clk_reg; 45 | 46 | always_ff @(posedge clk) begin 47 | frac_ovf_reg <= 1'b0; 48 | baud_clk_reg <= 1'b0; 49 | 50 | if (frac_ovf_reg) begin 51 | // delay extra cycle 52 | frac_ovf_reg <= 1'b0; 53 | end else if (prescale_int_reg != 0) begin 54 | prescale_int_reg <= prescale_int_reg - 1; 55 | end else begin 56 | prescale_int_reg <= prescale[FRAC_W +: INT_W] - 1; 57 | {frac_ovf_reg, prescale_frac_reg} <= prescale_frac_reg + prescale[FRAC_W-1:0]; 58 | baud_clk_reg <= 1'b1; 59 | end 60 | 61 | if (rst) begin 62 | prescale_int_reg <= 0; 63 | prescale_frac_reg <= 0; 64 | baud_clk_reg <= 0; 65 | end 66 | end 67 | 68 | endmodule 69 | 70 | `resetall 71 | -------------------------------------------------------------------------------- /src/lss/tb/taxi_i2c_master/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ns 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_i2c_master 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | # export PARAM_DEFAULT_PRESCALE := 1 37 | 38 | ifeq ($(SIM), icarus) 39 | PLUSARGS += -fst 40 | 41 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 42 | else ifeq ($(SIM), verilator) 43 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 44 | 45 | ifeq ($(WAVES), 1) 46 | COMPILE_ARGS += --trace-fst 47 | VERILATOR_TRACE = 1 48 | endif 49 | endif 50 | 51 | include $(shell cocotb-config --makefiles)/Makefile.sim 52 | -------------------------------------------------------------------------------- /src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * I2C master testbench 17 | */ 18 | module test_taxi_i2c_master 19 | (); 20 | 21 | logic clk; 22 | logic rst; 23 | 24 | taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) s_axis_cmd(); 25 | taxi_axis_if #(.DATA_W(8)) s_axis_data(); 26 | taxi_axis_if #(.DATA_W(8)) m_axis_data(); 27 | 28 | logic scl_i; 29 | logic scl_o; 30 | logic sda_i; 31 | logic sda_o; 32 | 33 | logic busy; 34 | logic bus_control; 35 | logic bus_active; 36 | logic missed_ack; 37 | 38 | logic [15:0] prescale; 39 | logic stop_on_idle; 40 | 41 | taxi_i2c_master 42 | uut ( 43 | .clk(clk), 44 | .rst(rst), 45 | 46 | /* 47 | * Host interface 48 | */ 49 | .s_axis_cmd(s_axis_cmd), 50 | .s_axis_data(s_axis_data), 51 | .m_axis_data(m_axis_data), 52 | 53 | /* 54 | * I2C interface 55 | */ 56 | .scl_i(scl_i), 57 | .scl_o(scl_o), 58 | .sda_i(sda_i), 59 | .sda_o(sda_o), 60 | 61 | /* 62 | * Status 63 | */ 64 | .busy(busy), 65 | .bus_control(bus_control), 66 | .bus_active(bus_active), 67 | .missed_ack(missed_ack), 68 | 69 | /* 70 | * Configuration 71 | */ 72 | .prescale(prescale), 73 | .stop_on_idle(stop_on_idle) 74 | ); 75 | 76 | endmodule 77 | 78 | `resetall 79 | -------------------------------------------------------------------------------- /src/lss/tb/taxi_i2c_single_reg/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ns 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_i2c_single_reg 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | 28 | # handle file list files 29 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 30 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 31 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 32 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 33 | 34 | # module parameters 35 | export PARAM_FILTER_LEN := 4 36 | export PARAM_DEV_ADDR := $(shell echo $$((0x70)) ) 37 | 38 | ifeq ($(SIM), icarus) 39 | PLUSARGS += -fst 40 | 41 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 42 | else ifeq ($(SIM), verilator) 43 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 44 | 45 | ifeq ($(WAVES), 1) 46 | COMPILE_ARGS += --trace-fst 47 | VERILATOR_TRACE = 1 48 | endif 49 | endif 50 | 51 | include $(shell cocotb-config --makefiles)/Makefile.sim 52 | -------------------------------------------------------------------------------- /src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * I2C single register testbench 17 | */ 18 | module test_taxi_i2c_single_reg # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter FILTER_LEN = 4, 22 | parameter logic [6:0] DEV_ADDR = 7'h70 23 | /* verilator lint_on WIDTHTRUNC */ 24 | ) 25 | (); 26 | 27 | logic clk; 28 | logic rst; 29 | 30 | logic scl_i; 31 | logic scl_o; 32 | logic sda_i; 33 | logic sda_o; 34 | 35 | logic [7:0] data_in; 36 | logic data_latch; 37 | logic [7:0] data_out; 38 | 39 | taxi_i2c_single_reg #( 40 | .FILTER_LEN(FILTER_LEN), 41 | .DEV_ADDR(DEV_ADDR) 42 | ) 43 | uut ( 44 | .clk(clk), 45 | .rst(rst), 46 | 47 | /* 48 | * I2C interface 49 | */ 50 | .scl_i(scl_i), 51 | .scl_o(scl_o), 52 | .sda_i(sda_i), 53 | .sda_o(sda_o), 54 | 55 | /* 56 | * Data register 57 | */ 58 | .data_in(data_in), 59 | .data_latch(data_latch), 60 | .data_out(data_out) 61 | ); 62 | 63 | endmodule 64 | 65 | `resetall 66 | -------------------------------------------------------------------------------- /src/lss/tb/taxi_uart/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ns 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_uart 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f 27 | 28 | # handle file list files 29 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 30 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 31 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 32 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 33 | 34 | # module parameters 35 | export PARAM_PRE_W := 16 36 | export PARAM_DATA_W := 8 37 | 38 | ifeq ($(SIM), icarus) 39 | PLUSARGS += -fst 40 | 41 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 42 | else ifeq ($(SIM), verilator) 43 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 44 | 45 | ifeq ($(WAVES), 1) 46 | COMPILE_ARGS += --trace-fst 47 | VERILATOR_TRACE = 1 48 | endif 49 | endif 50 | 51 | include $(shell cocotb-config --makefiles)/Makefile.sim 52 | -------------------------------------------------------------------------------- /src/lss/tb/taxi_uart/test_taxi_uart.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * AXI4-Stream FIFO testbench 17 | */ 18 | module test_taxi_uart # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter PRE_W = 16, 22 | parameter DATA_W = 8 23 | /* verilator lint_on WIDTHTRUNC */ 24 | ) 25 | (); 26 | 27 | logic clk; 28 | logic rst; 29 | 30 | taxi_axis_if #(.DATA_W(DATA_W)) s_axis_tx(); 31 | taxi_axis_if #(.DATA_W(DATA_W)) m_axis_rx(); 32 | 33 | logic rxd; 34 | logic txd; 35 | 36 | logic tx_busy; 37 | logic rx_busy; 38 | logic rx_overrun_error; 39 | logic rx_frame_error; 40 | 41 | logic [PRE_W-1:0] prescale; 42 | 43 | taxi_uart #( 44 | .PRE_W(PRE_W) 45 | ) 46 | uut ( 47 | .clk(clk), 48 | .rst(rst), 49 | 50 | /* 51 | * AXI4-Stream input (sink) 52 | */ 53 | .s_axis_tx(s_axis_tx), 54 | 55 | /* 56 | * AXI4-Stream output (source) 57 | */ 58 | .m_axis_rx(m_axis_rx), 59 | 60 | /* 61 | * UART interface 62 | */ 63 | .rxd(rxd), 64 | .txd(txd), 65 | 66 | /* 67 | * Status 68 | */ 69 | .tx_busy(tx_busy), 70 | .rx_busy(rx_busy), 71 | .rx_overrun_error(rx_overrun_error), 72 | .rx_frame_error(rx_frame_error), 73 | 74 | /* 75 | * Configuration 76 | */ 77 | .prescale(prescale) 78 | ); 79 | 80 | endmodule 81 | 82 | `resetall 83 | -------------------------------------------------------------------------------- /src/pcie/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../ -------------------------------------------------------------------------------- /src/pcie/rtl/taxi_pcie_tlp_if.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: MIT 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | interface taxi_pcie_tlp_if #( 12 | parameter SEGS = 1, 13 | parameter SEG_DATA_W = 256, 14 | parameter SEG_EMPTY_W = $clog2(SEG_DATA_W/32), 15 | parameter HDR_W = 128, 16 | parameter FUNC_NUM_W = 8, 17 | parameter SEQ_NUM_W = 6 18 | ) 19 | (); 20 | logic [SEGS-1:0][SEG_DATA_W-1:0] data; 21 | logic [SEGS-1:0][SEG_EMPTY_W-1:0] empty; 22 | logic [SEGS-1:0][HDR_W-1:0] hdr; 23 | logic [SEGS-1:0][SEQ_NUM_W-1:0] seq; 24 | logic [SEGS-1:0][2:0] bar_id; 25 | logic [SEGS-1:0][FUNC_NUM_W-1:0] func_num; 26 | logic [SEGS-1:0][3:0] error; 27 | logic [SEGS-1:0] valid; 28 | logic [SEGS-1:0] sop; 29 | logic [SEGS-1:0] eop; 30 | logic ready; 31 | 32 | modport src ( 33 | output data, 34 | output empty, 35 | output hdr, 36 | output seq, 37 | output bar_id, 38 | output func_num, 39 | output error, 40 | output valid, 41 | output sop, 42 | output eop, 43 | input ready 44 | ); 45 | 46 | modport snk ( 47 | input data, 48 | input empty, 49 | input hdr, 50 | input seq, 51 | input bar_id, 52 | input func_num, 53 | input error, 54 | input valid, 55 | input sop, 56 | input eop, 57 | output ready 58 | ); 59 | 60 | modport mon ( 61 | input data, 62 | input empty, 63 | input hdr, 64 | input seq, 65 | input bar_id, 66 | input func_num, 67 | input error, 68 | input valid, 69 | input sop, 70 | input eop, 71 | input ready 72 | ); 73 | 74 | endinterface 75 | -------------------------------------------------------------------------------- /src/pcie/tb/taxi_pcie_axil_master/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2021-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_pcie_axil_master 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(RTL_DIR)/taxi_pcie_tlp_if.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_TLP_SEG_DATA_W := 64 38 | export PARAM_TLP_HDR_W := 128 39 | export PARAM_TLP_SEGS := 1 40 | export PARAM_AXIL_DATA_W := 32 41 | export PARAM_AXIL_ADDR_W := 64 42 | export PARAM_TLP_FORCE_64_BIT_ADDR := 0 43 | 44 | ifeq ($(SIM), icarus) 45 | PLUSARGS += -fst 46 | 47 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 48 | else ifeq ($(SIM), verilator) 49 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 50 | 51 | ifeq ($(WAVES), 1) 52 | COMPILE_ARGS += --trace-fst 53 | VERILATOR_TRACE = 1 54 | endif 55 | endif 56 | 57 | include $(shell cocotb-config --makefiles)/Makefile.sim 58 | -------------------------------------------------------------------------------- /src/pcie/tb/taxi_pcie_axil_master/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * PCIe AXI Lite Master testbench 17 | */ 18 | module test_taxi_pcie_axil_master # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter TLP_SEG_DATA_W = 64, 22 | parameter TLP_HDR_W = 128, 23 | parameter TLP_SEGS = 1, 24 | parameter AXIL_DATA_W = 32, 25 | parameter AXIL_ADDR_W = 64, 26 | parameter logic TLP_FORCE_64_BIT_ADDR = 1'b0 27 | /* verilator lint_on WIDTHTRUNC */ 28 | ) 29 | (); 30 | 31 | logic clk; 32 | logic rst; 33 | 34 | taxi_pcie_tlp_if #( 35 | .SEGS(TLP_SEGS), 36 | .SEG_DATA_W(TLP_SEG_DATA_W), 37 | .HDR_W(TLP_HDR_W), 38 | .FUNC_NUM_W(8) 39 | ) rx_req_tlp(), tx_cpl_tlp(); 40 | 41 | taxi_axil_if #( 42 | .DATA_W(AXIL_DATA_W), 43 | .ADDR_W(AXIL_ADDR_W), 44 | .AWUSER_EN(1'b0), 45 | .WUSER_EN(1'b0), 46 | .BUSER_EN(1'b0), 47 | .ARUSER_EN(1'b0), 48 | .RUSER_EN(1'b0) 49 | ) m_axil(); 50 | 51 | logic [7:0] bus_num; 52 | 53 | logic stat_err_cor; 54 | logic stat_err_uncor; 55 | 56 | taxi_pcie_axil_master #( 57 | .TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR) 58 | ) 59 | uut ( 60 | .clk(clk), 61 | .rst(rst), 62 | 63 | /* 64 | * TLP input (request) 65 | */ 66 | .rx_req_tlp(rx_req_tlp), 67 | 68 | /* 69 | * TLP output (completion) 70 | */ 71 | .tx_cpl_tlp(tx_cpl_tlp), 72 | 73 | /* 74 | * AXI Lite Master output 75 | */ 76 | .m_axil_wr(m_axil), 77 | .m_axil_rd(m_axil), 78 | 79 | /* 80 | * Configuration 81 | */ 82 | .bus_num(bus_num), 83 | 84 | /* 85 | * Status 86 | */ 87 | .stat_err_cor(stat_err_cor), 88 | .stat_err_uncor(stat_err_uncor) 89 | ); 90 | 91 | endmodule 92 | 93 | `resetall 94 | -------------------------------------------------------------------------------- /src/pcie/tb/taxi_pcie_axil_master_minimal/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2021-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_pcie_axil_master_minimal 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(RTL_DIR)/taxi_pcie_tlp_if.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_TLP_SEG_DATA_W := 64 38 | export PARAM_TLP_HDR_W := 128 39 | export PARAM_TLP_SEGS := 1 40 | export PARAM_AXIL_DATA_W := 32 41 | export PARAM_AXIL_ADDR_W := 64 42 | export PARAM_TLP_FORCE_64_BIT_ADDR := 0 43 | 44 | ifeq ($(SIM), icarus) 45 | PLUSARGS += -fst 46 | 47 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 48 | else ifeq ($(SIM), verilator) 49 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 50 | 51 | ifeq ($(WAVES), 1) 52 | COMPILE_ARGS += --trace-fst 53 | VERILATOR_TRACE = 1 54 | endif 55 | endif 56 | 57 | include $(shell cocotb-config --makefiles)/Makefile.sim 58 | -------------------------------------------------------------------------------- /src/pcie/tb/taxi_pcie_axil_master_minimal/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * PCIe AXI Lite Master (minimal) testbench 17 | */ 18 | module test_taxi_pcie_axil_master_minimal # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter TLP_SEG_DATA_W = 64, 22 | parameter TLP_HDR_W = 128, 23 | parameter TLP_SEGS = 1, 24 | parameter AXIL_DATA_W = 32, 25 | parameter AXIL_ADDR_W = 64, 26 | parameter logic TLP_FORCE_64_BIT_ADDR = 1'b0 27 | /* verilator lint_on WIDTHTRUNC */ 28 | ) 29 | (); 30 | 31 | logic clk; 32 | logic rst; 33 | 34 | taxi_pcie_tlp_if #( 35 | .SEGS(TLP_SEGS), 36 | .SEG_DATA_W(TLP_SEG_DATA_W), 37 | .HDR_W(TLP_HDR_W), 38 | .FUNC_NUM_W(8) 39 | ) rx_req_tlp(), tx_cpl_tlp(); 40 | 41 | taxi_axil_if #( 42 | .DATA_W(AXIL_DATA_W), 43 | .ADDR_W(AXIL_ADDR_W), 44 | .AWUSER_EN(1'b0), 45 | .WUSER_EN(1'b0), 46 | .BUSER_EN(1'b0), 47 | .ARUSER_EN(1'b0), 48 | .RUSER_EN(1'b0) 49 | ) m_axil(); 50 | 51 | logic [7:0] bus_num; 52 | 53 | logic stat_err_cor; 54 | logic stat_err_uncor; 55 | 56 | taxi_pcie_axil_master_minimal #( 57 | .TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR) 58 | ) 59 | uut ( 60 | .clk(clk), 61 | .rst(rst), 62 | 63 | /* 64 | * TLP input (request) 65 | */ 66 | .rx_req_tlp(rx_req_tlp), 67 | 68 | /* 69 | * TLP output (completion) 70 | */ 71 | .tx_cpl_tlp(tx_cpl_tlp), 72 | 73 | /* 74 | * AXI Lite Master output 75 | */ 76 | .m_axil_wr(m_axil), 77 | .m_axil_rd(m_axil), 78 | 79 | /* 80 | * Configuration 81 | */ 82 | .bus_num(bus_num), 83 | 84 | /* 85 | * Status 86 | */ 87 | .stat_err_cor(stat_err_cor), 88 | .stat_err_uncor(stat_err_uncor) 89 | ); 90 | 91 | endmodule 92 | 93 | `resetall 94 | -------------------------------------------------------------------------------- /src/prim/tb/taxi_arbiter/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | 18 | DUT = taxi_arbiter 19 | COCOTB_TEST_MODULES = test_$(DUT) 20 | COCOTB_TOPLEVEL = $(DUT) 21 | MODULE = $(COCOTB_TEST_MODULES) 22 | TOPLEVEL = $(COCOTB_TOPLEVEL) 23 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 24 | VERILOG_SOURCES += $(RTL_DIR)/taxi_penc.sv 25 | 26 | # handle file list files 27 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 28 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 29 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 30 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 31 | 32 | # module parameters 33 | export PARAM_PORTS := 32 34 | export PARAM_ARM_ROUND_ROBIN := "1'b1" 35 | export PARAM_ARM_BLOCK := "1'b1" 36 | export PARAM_ARM_BLOCK_ACK := "1'b0" 37 | export PARAM_LSB_HIGH_PRIO := "1'b0" 38 | 39 | ifeq ($(SIM), icarus) 40 | PLUSARGS += -fst 41 | 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 43 | else ifeq ($(SIM), verilator) 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 45 | 46 | ifeq ($(WAVES), 1) 47 | COMPILE_ARGS += --trace-fst 48 | VERILATOR_TRACE = 1 49 | endif 50 | endif 51 | 52 | include $(shell cocotb-config --makefiles)/Makefile.sim 53 | -------------------------------------------------------------------------------- /src/prim/tb/taxi_penc/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | 18 | DUT = taxi_penc 19 | COCOTB_TEST_MODULES = test_$(DUT) 20 | COCOTB_TOPLEVEL = $(DUT) 21 | MODULE = $(COCOTB_TEST_MODULES) 22 | TOPLEVEL = $(COCOTB_TOPLEVEL) 23 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 24 | 25 | # handle file list files 26 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 27 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 28 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 29 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 30 | 31 | # module parameters 32 | export PARAM_WIDTH := 32 33 | export PARAM_LSB_HIGH_PRIO := "1'b0" 34 | 35 | ifeq ($(SIM), icarus) 36 | PLUSARGS += -fst 37 | 38 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 39 | else ifeq ($(SIM), verilator) 40 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 41 | 42 | ifeq ($(WAVES), 1) 43 | COMPILE_ARGS += --trace-fst 44 | VERILATOR_TRACE = 1 45 | endif 46 | endif 47 | 48 | include $(shell cocotb-config --makefiles)/Makefile.sim 49 | -------------------------------------------------------------------------------- /src/ptp/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../ -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_clock/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_ptp_clock 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_PERIOD_NS_W := 4 35 | export PARAM_OFFSET_NS_W := 4 36 | export PARAM_FNS_W := 16 37 | export PARAM_PERIOD_NS_NUM := 32 38 | export PARAM_PERIOD_NS_DENOM := 5 39 | export PARAM_PIPELINE_OUTPUT := 0 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_clock_cdc/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_ptp_clock_cdc 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_TS_W := 96 35 | export PARAM_NS_W := 4 36 | export PARAM_LOG_RATE := 3 37 | export PARAM_PIPELINE_OUTPUT := 0 38 | 39 | ifeq ($(SIM), icarus) 40 | PLUSARGS += -fst 41 | 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 43 | else ifeq ($(SIM), verilator) 44 | COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH 45 | 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_perout/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_ptp_perout 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_FNS_EN := "1'b1" 35 | export PARAM_OUT_START_S := 0 36 | export PARAM_OUT_START_NS := 0 37 | export PARAM_OUT_START_FNS := 0 38 | export PARAM_OUT_PERIOD_S := 1 39 | export PARAM_OUT_PERIOD_NS := 0 40 | export PARAM_OUT_PERIOD_FNS := 0 41 | export PARAM_OUT_WIDTH_S := 0 42 | export PARAM_OUT_WIDTH_NS := 1000 43 | export PARAM_OUT_WIDTH_FNS := 0 44 | 45 | ifeq ($(SIM), icarus) 46 | PLUSARGS += -fst 47 | 48 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 49 | else ifeq ($(SIM), verilator) 50 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 51 | 52 | ifeq ($(WAVES), 1) 53 | COMPILE_ARGS += --trace-fst 54 | VERILATOR_TRACE = 1 55 | endif 56 | endif 57 | 58 | include $(shell cocotb-config --makefiles)/Makefile.sim 59 | -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_td_leaf/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_ptp_td_leaf 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_TS_REL_EN := "1'b1" 35 | export PARAM_TS_TOD_EN := "1'b1" 36 | export PARAM_TS_FNS_W := 16 37 | export PARAM_TS_REL_NS_W := 48 38 | export PARAM_TS_TOD_S_W := 48 39 | export PARAM_TS_REL_W := $(shell expr $(PARAM_TS_REL_NS_W) + $(PARAM_TS_FNS_W)) 40 | export PARAM_TS_TOD_W := $(shell expr $(PARAM_TS_TOD_S_W) + 32 + $(PARAM_TS_FNS_W)) 41 | export PARAM_TD_SDI_PIPELINE := 2 42 | 43 | ifeq ($(SIM), icarus) 44 | PLUSARGS += -fst 45 | 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 47 | else ifeq ($(SIM), verilator) 48 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 49 | 50 | ifeq ($(WAVES), 1) 51 | COMPILE_ARGS += --trace-fst 52 | VERILATOR_TRACE = 1 53 | endif 54 | endif 55 | 56 | include $(shell cocotb-config --makefiles)/Makefile.sim 57 | -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_td_leaf/ptp_td.py: -------------------------------------------------------------------------------- 1 | ../ptp_td.py -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_td_phc/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2023-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_ptp_td_phc 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = $(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 26 | 27 | # handle file list files 28 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 29 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 30 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 31 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 32 | 33 | # module parameters 34 | export PARAM_PERIOD_NS_NUM := 32 35 | export PARAM_PERIOD_NS_DENOM := 5 36 | 37 | ifeq ($(SIM), icarus) 38 | PLUSARGS += -fst 39 | 40 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 41 | else ifeq ($(SIM), verilator) 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 43 | 44 | ifeq ($(WAVES), 1) 45 | COMPILE_ARGS += --trace-fst 46 | VERILATOR_TRACE = 1 47 | endif 48 | endif 49 | 50 | include $(shell cocotb-config --makefiles)/Makefile.sim 51 | -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_td_phc/ptp_td.py: -------------------------------------------------------------------------------- 1 | ../ptp_td.py -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_td_rel2tod/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2024-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_ptp_td_rel2tod 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | export PARAM_TS_FNS_W := 16 37 | export PARAM_TS_REL_NS_W := 32 38 | export PARAM_TS_TOD_S_W := 48 39 | export PARAM_TD_SDI_PIPELINE := 2 40 | 41 | ifeq ($(SIM), icarus) 42 | PLUSARGS += -fst 43 | 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 45 | else ifeq ($(SIM), verilator) 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 47 | 48 | ifeq ($(WAVES), 1) 49 | COMPILE_ARGS += --trace-fst 50 | VERILATOR_TRACE = 1 51 | endif 52 | endif 53 | 54 | include $(shell cocotb-config --makefiles)/Makefile.sim 55 | -------------------------------------------------------------------------------- /src/ptp/tb/taxi_ptp_td_rel2tod/ptp_td.py: -------------------------------------------------------------------------------- 1 | ../ptp_td.py -------------------------------------------------------------------------------- /src/stats/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../ -------------------------------------------------------------------------------- /src/stats/tb/taxi_stats_collect/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2021-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_stats_collect 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 28 | 29 | # handle file list files 30 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 31 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 32 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 33 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 34 | 35 | # module parameters 36 | export PARAM_CNT := 8 37 | export PARAM_INC_W := 8 38 | export PARAM_ID_BASE := 0 39 | export PARAM_UPDATE_PERIOD := 128 40 | export PARAM_STR_EN := 1 41 | export PARAM_PREFIX_STR := "\"BLK\"" 42 | export PARAM_STAT_INC_W := 16 43 | export PARAM_STAT_ID_W := $(shell python -c "print(($(PARAM_CNT)-1).bit_length())") 44 | 45 | ifeq ($(SIM), icarus) 46 | PLUSARGS += -fst 47 | 48 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 49 | else ifeq ($(SIM), verilator) 50 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 51 | 52 | ifeq ($(WAVES), 1) 53 | COMPILE_ARGS += --trace-fst 54 | VERILATOR_TRACE = 1 55 | endif 56 | endif 57 | 58 | include $(shell cocotb-config --makefiles)/Makefile.sim 59 | -------------------------------------------------------------------------------- /src/stats/tb/taxi_stats_collect/test_taxi_stats_collect.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * Statistics collector testbench 17 | */ 18 | module test_taxi_stats_collect # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter CNT = 8, 22 | parameter INC_W = 8, 23 | parameter ID_BASE = 0, 24 | parameter UPDATE_PERIOD = 128, 25 | parameter logic STR_EN = 1'b1, 26 | parameter logic [8*8-1:0] PREFIX_STR = "BLK", 27 | parameter STAT_INC_W = 16, 28 | parameter STAT_ID_W = $clog2(CNT) 29 | /* verilator lint_on WIDTHTRUNC */ 30 | ) 31 | (); 32 | 33 | logic clk; 34 | logic rst; 35 | 36 | logic [INC_W-1:0] stat_inc[CNT]; 37 | logic [0:0] stat_valid[CNT]; 38 | logic [8*8-1:0] stat_str[CNT]; 39 | 40 | taxi_axis_if #( 41 | .DATA_W(STAT_INC_W), 42 | .KEEP_EN(0), 43 | .KEEP_W(1), 44 | .ID_EN(1), 45 | .ID_W(STAT_ID_W), 46 | .USER_EN(1), 47 | .USER_W(1) 48 | ) m_axis_stat(); 49 | 50 | logic gate; 51 | logic update; 52 | 53 | taxi_stats_collect #( 54 | .CNT(CNT), 55 | .INC_W(INC_W), 56 | .ID_BASE(ID_BASE), 57 | .UPDATE_PERIOD(UPDATE_PERIOD), 58 | .STR_EN(STR_EN), 59 | .PREFIX_STR(PREFIX_STR) 60 | ) 61 | uut ( 62 | .clk(clk), 63 | .rst(rst), 64 | 65 | /* 66 | * Increment inputs 67 | */ 68 | .stat_inc(stat_inc), 69 | .stat_valid(stat_valid), 70 | .stat_str(stat_str), 71 | 72 | /* 73 | * Statistics increment output 74 | */ 75 | .m_axis_stat(m_axis_stat), 76 | 77 | /* 78 | * Control inputs 79 | */ 80 | .gate(gate), 81 | .update(update) 82 | ); 83 | 84 | endmodule 85 | 86 | `resetall 87 | -------------------------------------------------------------------------------- /src/stats/tb/taxi_stats_counter/test_taxi_stats_counter.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * Statistics counter testbench 17 | */ 18 | module test_taxi_stats_counter # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter STAT_COUNT_W = 32, 22 | parameter PIPELINE = 2, 23 | parameter STAT_INC_W = 16, 24 | parameter STAT_ID_W = 8, 25 | parameter AXIL_DATA_W = 32, 26 | parameter AXIL_ADDR_W = STAT_ID_W + $clog2((STAT_COUNT_W+7)/8) 27 | /* verilator lint_on WIDTHTRUNC */ 28 | ) 29 | (); 30 | 31 | logic clk; 32 | logic rst; 33 | 34 | taxi_axis_if #( 35 | .DATA_W(STAT_INC_W), 36 | .KEEP_EN(0), 37 | .KEEP_W(1), 38 | .ID_EN(1), 39 | .ID_W(STAT_ID_W) 40 | ) s_axis_stat(); 41 | 42 | taxi_axil_if #( 43 | .DATA_W(AXIL_DATA_W), 44 | .ADDR_W(AXIL_ADDR_W) 45 | ) s_axil(); 46 | 47 | taxi_stats_counter #( 48 | .STAT_COUNT_W(STAT_COUNT_W), 49 | .PIPELINE(PIPELINE) 50 | ) 51 | uut ( 52 | .clk(clk), 53 | .rst(rst), 54 | 55 | /* 56 | * Statistics increment input 57 | */ 58 | .s_axis_stat(s_axis_stat), 59 | 60 | /* 61 | * AXI Lite register interface 62 | */ 63 | .s_axil_wr(s_axil), 64 | .s_axil_rd(s_axil) 65 | ); 66 | 67 | endmodule 68 | 69 | `resetall 70 | -------------------------------------------------------------------------------- /src/stats/tb/taxi_stats_strings_full/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_stats_strings_full 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_PIPELINE := 2 38 | export PARAM_STAT_INC_W := 16 39 | export PARAM_STAT_ID_W := 8 40 | export PARAM_AXIL_DATA_W := 32 41 | export PARAM_AXIL_ADDR_W := $(shell python -c "print($(PARAM_STAT_ID_W)+4)") 42 | 43 | ifeq ($(SIM), icarus) 44 | PLUSARGS += -fst 45 | 46 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 47 | else ifeq ($(SIM), verilator) 48 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 49 | 50 | ifeq ($(WAVES), 1) 51 | COMPILE_ARGS += --trace-fst 52 | VERILATOR_TRACE = 1 53 | endif 54 | endif 55 | 56 | include $(shell cocotb-config --makefiles)/Makefile.sim 57 | -------------------------------------------------------------------------------- /src/stats/tb/taxi_stats_strings_full/test_taxi_stats_strings_full.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * Statistics counter testbench 17 | */ 18 | module test_taxi_stats_strings_full # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter PIPELINE = 2, 22 | parameter STAT_INC_W = 16, 23 | parameter STAT_ID_W = 8, 24 | parameter AXIL_DATA_W = 32, 25 | parameter AXIL_ADDR_W = STAT_ID_W + 4 26 | /* verilator lint_on WIDTHTRUNC */ 27 | ) 28 | (); 29 | 30 | logic clk; 31 | logic rst; 32 | 33 | taxi_axis_if #( 34 | .DATA_W(STAT_INC_W), 35 | .KEEP_EN(0), 36 | .KEEP_W(1), 37 | .ID_EN(1), 38 | .ID_W(STAT_ID_W) 39 | ) s_axis_stat(); 40 | 41 | taxi_axil_if #( 42 | .DATA_W(AXIL_DATA_W), 43 | .ADDR_W(AXIL_ADDR_W) 44 | ) s_axil(); 45 | 46 | taxi_stats_strings_full #( 47 | .PIPELINE(PIPELINE) 48 | ) 49 | uut ( 50 | .clk(clk), 51 | .rst(rst), 52 | 53 | /* 54 | * Statistics increment input 55 | */ 56 | .s_axis_stat(s_axis_stat), 57 | 58 | /* 59 | * AXI Lite register interface 60 | */ 61 | .s_axil_wr(s_axil), 62 | .s_axil_rd(s_axil) 63 | ); 64 | 65 | assign s_axis_stat.tready = 1'b1; 66 | 67 | endmodule 68 | 69 | `resetall 70 | -------------------------------------------------------------------------------- /src/sync/rtl/taxi_sync_reset.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2014-2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * Synchronizes an active-high asynchronous reset signal to a given clock by 17 | * using a pipeline of N registers. 18 | */ 19 | module taxi_sync_reset # 20 | ( 21 | // depth of synchronizer 22 | parameter N = 2 23 | ) 24 | ( 25 | input wire logic clk, 26 | input wire logic rst, 27 | 28 | output wire logic out 29 | ); 30 | 31 | (* async_reg="true", srl_style="register", shreg_extract="no" *) 32 | logic [N-1:0] sync_reg = '1; 33 | 34 | assign out = sync_reg[N-1]; 35 | 36 | always_ff @(posedge clk or posedge rst) begin 37 | if (rst) begin 38 | sync_reg <= '1; 39 | end else begin 40 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 41 | end 42 | end 43 | 44 | endmodule 45 | 46 | `resetall 47 | -------------------------------------------------------------------------------- /src/sync/rtl/taxi_sync_signal.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2014-2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * Synchronizes an asynchronous signal to a given clock by using a pipeline of 17 | * two registers. 18 | */ 19 | module taxi_sync_signal #( 20 | // width of the input and output signals 21 | parameter WIDTH = 1, 22 | // depth of synchronizer 23 | parameter N = 2 24 | ) 25 | ( 26 | input wire logic clk, 27 | 28 | input wire logic [WIDTH-1:0] in, 29 | output wire logic [WIDTH-1:0] out 30 | ); 31 | 32 | (* async_reg="true", srl_style="register", shreg_extract="no" *) 33 | logic [WIDTH-1:0] sync_reg[N-1:0]; 34 | 35 | assign out = sync_reg[N-1]; 36 | 37 | always_ff @(posedge clk) begin 38 | sync_reg[0] <= in; 39 | for (integer k = 1; k < N; k = k + 1) begin 40 | sync_reg[k] <= sync_reg[k-1]; 41 | end 42 | end 43 | 44 | endmodule 45 | 46 | `resetall 47 | -------------------------------------------------------------------------------- /src/sync/syn/vivado/taxi_sync_reset.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # reset synchronizer timing constraints 10 | 11 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_reset || REF_NAME == taxi_sync_reset)}] { 12 | puts "Inserting timing constraints for taxi_sync_reset instance $inst" 13 | 14 | # reset synchronization 15 | set reset_ffs [get_cells -quiet -hier "sync_reg_reg[*]" -filter "PARENT == $inst"] 16 | 17 | set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}] 18 | } 19 | -------------------------------------------------------------------------------- /src/sync/syn/vivado/taxi_sync_signal.tcl: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2020-2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | # 8 | 9 | # signal synchronizer timing constraints 10 | 11 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_sync_signal || REF_NAME == taxi_sync_signal)}] { 12 | puts "Inserting timing constraints for taxi_sync_signal instance $inst" 13 | 14 | set_false_path -to [get_cells -hier "sync_reg_reg[0][*]" -filter "PARENT == $inst"] 15 | } 16 | -------------------------------------------------------------------------------- /src/xfcp/lib/taxi: -------------------------------------------------------------------------------- 1 | ../../../ -------------------------------------------------------------------------------- /src/xfcp/rtl/taxi_xfcp_if_uart.f: -------------------------------------------------------------------------------- 1 | taxi_xfcp_if_uart.sv 2 | ../lib/taxi/src/lss/rtl/taxi_uart.f 3 | ../lib/taxi/src/axis/rtl/taxi_axis_fifo.sv 4 | ../lib/taxi/src/axis/rtl/taxi_axis_cobs_encode.f 5 | ../lib/taxi/src/axis/rtl/taxi_axis_cobs_decode.sv -------------------------------------------------------------------------------- /src/xfcp/rtl/taxi_xfcp_mod_axi.f: -------------------------------------------------------------------------------- 1 | taxi_xfcp_mod_axi.sv 2 | taxi_xfcp_mod_axil.sv 3 | ../lib/taxi/src/axi/rtl/taxi_axi_if.sv 4 | ../lib/taxi/src/axi/rtl/taxi_axil_if.sv 5 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 6 | -------------------------------------------------------------------------------- /src/xfcp/rtl/taxi_xfcp_mod_i2c_master.f: -------------------------------------------------------------------------------- 1 | taxi_xfcp_mod_i2c_master.sv 2 | ../lib/taxi/src/lss/rtl/taxi_i2c_master.sv 3 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 4 | -------------------------------------------------------------------------------- /src/xfcp/rtl/taxi_xfcp_mod_stats.f: -------------------------------------------------------------------------------- 1 | taxi_xfcp_mod_stats.sv 2 | taxi_xfcp_mod_axil.sv 3 | taxi_xfcp_switch.f 4 | ../lib/taxi/src/stats/rtl/taxi_stats_counter.sv 5 | ../lib/taxi/src/stats/rtl/taxi_stats_strings_full.sv 6 | ../lib/taxi/src/axi/rtl/taxi_axil_if.sv 7 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 8 | -------------------------------------------------------------------------------- /src/xfcp/rtl/taxi_xfcp_switch.f: -------------------------------------------------------------------------------- 1 | taxi_xfcp_switch.sv 2 | ../lib/taxi/src/prim/rtl/taxi_arbiter.sv 3 | ../lib/taxi/src/prim/rtl/taxi_penc.sv 4 | ../lib/taxi/src/axis/rtl/taxi_axis_if.sv 5 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_if_uart/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_xfcp_if_uart 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f 27 | 28 | # handle file list files 29 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 30 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 31 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 32 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 33 | 34 | # module parameters 35 | export PARAM_PRE_W := 16 36 | export PARAM_TX_FIFO_DEPTH := 512 37 | export PARAM_RX_FIFO_DEPTH := 512 38 | 39 | ifeq ($(SIM), icarus) 40 | PLUSARGS += -fst 41 | 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 43 | else ifeq ($(SIM), verilator) 44 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 45 | 46 | ifeq ($(WAVES), 1) 47 | COMPILE_ARGS += --trace-fst 48 | VERILATOR_TRACE = 1 49 | endif 50 | endif 51 | 52 | include $(shell cocotb-config --makefiles)/Makefile.sim 53 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * XFCP Interface (UART) testbench 17 | */ 18 | module test_taxi_xfcp_if_uart # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter PRE_W = 16, 22 | parameter TX_FIFO_DEPTH = 512, 23 | parameter RX_FIFO_DEPTH = 512 24 | /* verilator lint_on WIDTHTRUNC */ 25 | ) 26 | (); 27 | 28 | logic clk; 29 | logic rst; 30 | 31 | logic uart_rxd; 32 | logic uart_txd; 33 | 34 | taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_dsp_ds(), xfcp_dsp_us(); 35 | 36 | logic [PRE_W-1:0] prescale; 37 | 38 | taxi_xfcp_if_uart #( 39 | .PRE_W(PRE_W), 40 | .TX_FIFO_DEPTH(TX_FIFO_DEPTH), 41 | .RX_FIFO_DEPTH(RX_FIFO_DEPTH) 42 | ) 43 | uut ( 44 | .clk(clk), 45 | .rst(rst), 46 | 47 | /* 48 | * UART interface 49 | */ 50 | .uart_rxd(uart_rxd), 51 | .uart_txd(uart_txd), 52 | 53 | /* 54 | * XFCP downstream port 55 | */ 56 | .xfcp_dsp_ds(xfcp_dsp_ds), 57 | .xfcp_dsp_us(xfcp_dsp_us), 58 | 59 | /* 60 | * Configuration 61 | */ 62 | .prescale(prescale) 63 | ); 64 | 65 | endmodule 66 | 67 | `resetall 68 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_if_uart/xfcp.py: -------------------------------------------------------------------------------- 1 | ../xfcp.py -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_mod_axi/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_xfcp_mod_axi 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f 27 | 28 | # handle file list files 29 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 30 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 31 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 32 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 33 | 34 | # module parameters 35 | export PARAM_COUNT_SIZE := 16 36 | export PARAM_AXI_DATA_W := 32 37 | export PARAM_AXI_ADDR_W := 32 38 | export PARAM_AXI_STRB_W := $(shell expr $(PARAM_AXI_DATA_W) / 8 ) 39 | 40 | ifeq ($(SIM), icarus) 41 | PLUSARGS += -fst 42 | 43 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 44 | else ifeq ($(SIM), verilator) 45 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 46 | 47 | ifeq ($(WAVES), 1) 48 | COMPILE_ARGS += --trace-fst 49 | VERILATOR_TRACE = 1 50 | endif 51 | endif 52 | 53 | include $(shell cocotb-config --makefiles)/Makefile.sim 54 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * XFCP AXI module testbench 17 | */ 18 | module test_taxi_xfcp_mod_axi # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter COUNT_SIZE = 16, 22 | parameter AXI_DATA_W = 32, 23 | parameter AXI_ADDR_W = 32, 24 | parameter AXI_STRB_W = (AXI_DATA_W/8) 25 | /* verilator lint_on WIDTHTRUNC */ 26 | ) 27 | (); 28 | 29 | logic clk; 30 | logic rst; 31 | 32 | taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us(); 33 | 34 | taxi_axi_if #( 35 | .DATA_W(AXI_DATA_W), 36 | .ADDR_W(AXI_ADDR_W), 37 | .STRB_W(AXI_STRB_W) 38 | ) m_axi(); 39 | 40 | taxi_xfcp_mod_axi #( 41 | .COUNT_SIZE(COUNT_SIZE) 42 | ) 43 | uut ( 44 | .clk(clk), 45 | .rst(rst), 46 | 47 | /* 48 | * XFCP upstream port 49 | */ 50 | .xfcp_usp_ds(xfcp_usp_ds), 51 | .xfcp_usp_us(xfcp_usp_us), 52 | 53 | /* 54 | * AXI master interface 55 | */ 56 | .m_axi_wr(m_axi), 57 | .m_axi_rd(m_axi) 58 | ); 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_mod_axil/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_xfcp_mod_axil 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv 27 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axi/rtl/taxi_axil_if.sv 28 | VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv 29 | 30 | # handle file list files 31 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 32 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 33 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 34 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 35 | 36 | # module parameters 37 | export PARAM_COUNT_SIZE := 16 38 | export PARAM_AXIL_DATA_W := 32 39 | export PARAM_AXIL_ADDR_W := 32 40 | export PARAM_AXIL_STRB_W := $(shell expr $(PARAM_AXIL_DATA_W) / 8 ) 41 | 42 | ifeq ($(SIM), icarus) 43 | PLUSARGS += -fst 44 | 45 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 46 | else ifeq ($(SIM), verilator) 47 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 48 | 49 | ifeq ($(WAVES), 1) 50 | COMPILE_ARGS += --trace-fst 51 | VERILATOR_TRACE = 1 52 | endif 53 | endif 54 | 55 | include $(shell cocotb-config --makefiles)/Makefile.sim 56 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * XFCP AXI lite module testbench 17 | */ 18 | module test_taxi_xfcp_mod_axil # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter COUNT_SIZE = 16, 22 | parameter AXIL_DATA_W = 32, 23 | parameter AXIL_ADDR_W = 32, 24 | parameter AXIL_STRB_W = (AXIL_DATA_W/8) 25 | /* verilator lint_on WIDTHTRUNC */ 26 | ) 27 | (); 28 | 29 | logic clk; 30 | logic rst; 31 | 32 | taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us(); 33 | 34 | taxi_axil_if #( 35 | .DATA_W(AXIL_DATA_W), 36 | .ADDR_W(AXIL_ADDR_W), 37 | .STRB_W(AXIL_STRB_W) 38 | ) m_axil(); 39 | 40 | taxi_xfcp_mod_axil #( 41 | .COUNT_SIZE(COUNT_SIZE) 42 | ) 43 | uut ( 44 | .clk(clk), 45 | .rst(rst), 46 | 47 | /* 48 | * XFCP upstream port 49 | */ 50 | .xfcp_usp_ds(xfcp_usp_ds), 51 | .xfcp_usp_us(xfcp_usp_us), 52 | 53 | /* 54 | * AXI lite master interface 55 | */ 56 | .m_axil_wr(m_axil), 57 | .m_axil_rd(m_axil) 58 | ); 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_mod_i2c_master/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_xfcp_mod_i2c_master 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f 27 | 28 | # handle file list files 29 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 30 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 31 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 32 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 33 | 34 | # module parameters 35 | export PARAM_DEFAULT_PRESCALE := $(shell expr 125000000 / 400000 / 4 ) 36 | 37 | ifeq ($(SIM), icarus) 38 | PLUSARGS += -fst 39 | 40 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 41 | else ifeq ($(SIM), verilator) 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 43 | 44 | ifeq ($(WAVES), 1) 45 | COMPILE_ARGS += --trace-fst 46 | VERILATOR_TRACE = 1 47 | endif 48 | endif 49 | 50 | include $(shell cocotb-config --makefiles)/Makefile.sim 51 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * XFCP I2C master module testbench 17 | */ 18 | module test_taxi_xfcp_mod_i2c_master # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter logic [15:0] DEFAULT_PRESCALE = 125000000/400000/4 22 | /* verilator lint_on WIDTHTRUNC */ 23 | ) 24 | (); 25 | 26 | logic clk; 27 | logic rst; 28 | 29 | taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us(); 30 | 31 | logic i2c_scl_i; 32 | logic i2c_scl_o; 33 | logic i2c_sda_i; 34 | logic i2c_sda_o; 35 | 36 | taxi_xfcp_mod_i2c_master #( 37 | .DEFAULT_PRESCALE(DEFAULT_PRESCALE) 38 | ) 39 | uut ( 40 | .clk(clk), 41 | .rst(rst), 42 | 43 | /* 44 | * XFCP upstream port 45 | */ 46 | .xfcp_usp_ds(xfcp_usp_ds), 47 | .xfcp_usp_us(xfcp_usp_us), 48 | 49 | /* 50 | * I2C interface 51 | */ 52 | .i2c_scl_i(i2c_scl_i), 53 | .i2c_scl_o(i2c_scl_o), 54 | .i2c_sda_i(i2c_sda_i), 55 | .i2c_sda_o(i2c_sda_o) 56 | ); 57 | 58 | endmodule 59 | 60 | `resetall 61 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_switch/Makefile: -------------------------------------------------------------------------------- 1 | # SPDX-License-Identifier: CERN-OHL-S-2.0 2 | # 3 | # Copyright (c) 2025 FPGA Ninja, LLC 4 | # 5 | # Authors: 6 | # - Alex Forencich 7 | 8 | TOPLEVEL_LANG = verilog 9 | 10 | SIM ?= verilator 11 | WAVES ?= 0 12 | 13 | COCOTB_HDL_TIMEUNIT = 1ns 14 | COCOTB_HDL_TIMEPRECISION = 1ps 15 | 16 | RTL_DIR = ../../rtl 17 | LIB_DIR = ../../lib 18 | TAXI_SRC_DIR = $(LIB_DIR)/taxi/src 19 | 20 | DUT = taxi_xfcp_switch 21 | COCOTB_TEST_MODULES = test_$(DUT) 22 | COCOTB_TOPLEVEL = test_$(DUT) 23 | MODULE = $(COCOTB_TEST_MODULES) 24 | TOPLEVEL = $(COCOTB_TOPLEVEL) 25 | VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv 26 | VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f 27 | 28 | # handle file list files 29 | process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) 30 | process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) 31 | uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) 32 | VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) 33 | 34 | # module parameters 35 | export PARAM_PORTS := 4 36 | 37 | ifeq ($(SIM), icarus) 38 | PLUSARGS += -fst 39 | 40 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) 41 | else ifeq ($(SIM), verilator) 42 | COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) 43 | 44 | ifeq ($(WAVES), 1) 45 | COMPILE_ARGS += --trace-fst 46 | VERILATOR_TRACE = 1 47 | endif 48 | endif 49 | 50 | include $(shell cocotb-config --makefiles)/Makefile.sim 51 | -------------------------------------------------------------------------------- /src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.sv: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: CERN-OHL-S-2.0 2 | /* 3 | 4 | Copyright (c) 2025 FPGA Ninja, LLC 5 | 6 | Authors: 7 | - Alex Forencich 8 | 9 | */ 10 | 11 | `resetall 12 | `timescale 1ns / 1ps 13 | `default_nettype none 14 | 15 | /* 16 | * XFCP switch testbench 17 | */ 18 | module test_taxi_xfcp_switch # 19 | ( 20 | /* verilator lint_off WIDTHTRUNC */ 21 | parameter PORTS = 4 22 | /* verilator lint_on WIDTHTRUNC */ 23 | ) 24 | (); 25 | 26 | logic clk; 27 | logic rst; 28 | 29 | taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us(); 30 | taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_dsp_ds[PORTS](), xfcp_dsp_us[PORTS](); 31 | 32 | taxi_xfcp_switch #( 33 | .PORTS(PORTS) 34 | ) 35 | uut ( 36 | .clk(clk), 37 | .rst(rst), 38 | 39 | /* 40 | * XFCP upstream port 41 | */ 42 | .xfcp_usp_ds(xfcp_usp_ds), 43 | .xfcp_usp_us(xfcp_usp_us), 44 | 45 | /* 46 | * XFCP downstream ports 47 | */ 48 | .xfcp_dsp_ds(xfcp_dsp_ds), 49 | .xfcp_dsp_us(xfcp_dsp_us) 50 | ); 51 | 52 | endmodule 53 | 54 | `resetall 55 | -------------------------------------------------------------------------------- /tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [testenv] 9 | deps = 10 | pytest == 8.3.4 11 | pytest-xdist == 3.6.1 12 | pytest-split == 0.10.0 13 | cocotb == 1.9.2 14 | cocotb-bus == 0.2.1 15 | cocotb-test == 0.2.6 16 | cocotbext-axi == 0.1.24 17 | cocotbext-eth == 0.1.22 18 | cocotbext-i2c == 0.1.0 19 | cocotbext-pcie == 0.2.14 20 | cocotbext-uart == 0.1.2 21 | scapy == 2.6.1 22 | 23 | commands = 24 | pytest {posargs:-n auto --verbose} 25 | 26 | # pytest configuration 27 | [pytest] 28 | testpaths = 29 | src 30 | norecursedirs = 31 | lib 32 | addopts = 33 | --import-mode importlib 34 | --------------------------------------------------------------------------------