├── LICENSE ├── README.md └── rtl ├── DTEngine.sv ├── DTEngine_defines.vh ├── DTPU.sv ├── DTPUCluster.sv ├── FPAdder_2cycles_latency.v ├── FPAddersReduceTree.sv ├── FPAggregator.v ├── Mem1in2out.v ├── PipelinedMUX.sv ├── RLS.v ├── delay.v └── dualport_mem.v /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/README.md -------------------------------------------------------------------------------- /rtl/DTEngine.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/DTEngine.sv -------------------------------------------------------------------------------- /rtl/DTEngine_defines.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/DTEngine_defines.vh -------------------------------------------------------------------------------- /rtl/DTPU.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/DTPU.sv -------------------------------------------------------------------------------- /rtl/DTPUCluster.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/DTPUCluster.sv -------------------------------------------------------------------------------- /rtl/FPAdder_2cycles_latency.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/FPAdder_2cycles_latency.v -------------------------------------------------------------------------------- /rtl/FPAddersReduceTree.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/FPAddersReduceTree.sv -------------------------------------------------------------------------------- /rtl/FPAggregator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/FPAggregator.v -------------------------------------------------------------------------------- /rtl/Mem1in2out.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/Mem1in2out.v -------------------------------------------------------------------------------- /rtl/PipelinedMUX.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/PipelinedMUX.sv -------------------------------------------------------------------------------- /rtl/RLS.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/RLS.v -------------------------------------------------------------------------------- /rtl/delay.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/delay.v -------------------------------------------------------------------------------- /rtl/dualport_mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/fpgasystems/DecisionTrees/HEAD/rtl/dualport_mem.v --------------------------------------------------------------------------------