├── doc ├── Schematic │ ├── FWFT-FIFO.pdf │ ├── OVC_status.pdf │ ├── Sw_alloc_first_in_first_arbiter.pdf │ ├── input_buffer.pdf │ ├── prop_router.pdf │ ├── request_mask.pdf │ ├── router.pdf │ └── sw_in.pdf └── usermanual.pdf └── noc_based_mpsoc ├── DE2_115_pin_assignments.csv ├── clk50.sdc ├── mpsoc.qpf ├── mpsoc.qsf ├── mpsoc.qws ├── mpsoc_nativelink_simulation.rpt ├── output_files └── mpsoc.sof ├── simulation └── modelsim │ └── sw │ └── ram │ ├── cpu00_00.mif │ ├── cpu00_01.mif │ ├── cpu00_02.mif │ ├── cpu00_03.mif │ ├── cpu01_00.mif │ ├── cpu01_01.mif │ ├── cpu01_02.mif │ ├── cpu01_03.mif │ ├── cpu02_00.mif │ ├── cpu02_01.mif │ ├── cpu02_02.mif │ ├── cpu02_03.mif │ ├── cpu03_00.mif │ ├── cpu03_01.mif │ ├── cpu03_02.mif │ ├── cpu03_03.mif │ └── send.mif ├── src ├── IP_core │ ├── IP_testbench.v │ ├── aeMB_IP.v │ ├── aeMB_mpsoc.v │ ├── altera_reset_synchronizer.v │ ├── bus_addr_cmp.v │ ├── ext_int.v │ ├── gpio.v │ ├── int_ctrl.v │ ├── ip_testbench.v │ ├── prog_ram.v │ ├── reset_jtag.v │ ├── sdram │ │ ├── .qsys_edit │ │ │ ├── filters.xml │ │ │ └── preferences.xml │ │ ├── sdram.qsys │ │ ├── simulation │ │ │ ├── aldec │ │ │ │ └── rivierapro_setup.tcl │ │ │ ├── cadence │ │ │ │ ├── cds.lib │ │ │ │ ├── cds_libs │ │ │ │ │ ├── rst_controller.cds.lib │ │ │ │ │ ├── sdram_controller.cds.lib │ │ │ │ │ └── up_clocks_0.cds.lib │ │ │ │ ├── hdl.var │ │ │ │ └── ncsim_setup.sh │ │ │ ├── mentor │ │ │ │ └── msim_setup.tcl │ │ │ ├── sdram.sip │ │ │ ├── sdram.v │ │ │ ├── submodules │ │ │ │ ├── MT48LC8M16A2.V │ │ │ │ ├── altera_reset_controller.sdc │ │ │ │ ├── altera_reset_controller.v │ │ │ │ ├── altera_reset_synchronizer.v │ │ │ │ ├── sdram_sdram_controller.v │ │ │ │ ├── sdram_sdram_controller_test_component.v │ │ │ │ └── sdram_up_clocks_0.v │ │ │ └── synopsys │ │ │ │ ├── vcs │ │ │ │ └── vcs_setup.sh │ │ │ │ └── vcsmx │ │ │ │ ├── synopsys_sim.setup │ │ │ │ └── vcsmx_setup.sh │ │ ├── synthesis │ │ │ ├── sdram.qip │ │ │ ├── sdram.v │ │ │ └── submodules │ │ │ │ ├── altera_reset_controller.sdc │ │ │ │ ├── altera_reset_controller.v │ │ │ │ ├── altera_reset_synchronizer.v │ │ │ │ ├── sdram_sdram_controller.v │ │ │ │ ├── sdram_sdram_controller_test_component.v │ │ │ │ └── sdram_up_clocks_0.v │ │ └── testbench │ │ │ ├── sdram.ipx │ │ │ ├── sdram_tb.html │ │ │ ├── sdram_tb.qsys │ │ │ └── sdram_tb │ │ │ └── simulation │ │ │ ├── sdram_tb.v │ │ │ └── submodules │ │ │ ├── altera_avalon_clock_source.sv │ │ │ ├── altera_avalon_reset_source.sv │ │ │ ├── altera_reset_controller.sdc │ │ │ ├── altera_reset_controller.v │ │ │ ├── altera_reset_synchronizer.v │ │ │ ├── altera_sdram_partner_module.v │ │ │ ├── sdram.v │ │ │ ├── sdram_sdram_controller.v │ │ │ ├── sdram_sdram_controller_test_component.v │ │ │ ├── sdram_up_clocks_0.v │ │ │ └── verbosity_pkg.sv │ ├── signal_holder.v │ ├── timer.v │ └── wishbone_bus.v ├── MPSoC_top.v ├── NoC │ ├── Dimitrakopoulos_arbiter.v │ ├── MUX.v │ ├── arbiter.v │ ├── cross_bar.v │ ├── dual_port_ram.v │ ├── ext_ram_nic.v │ ├── fifo_buffer.v │ ├── fwft_fifo.v │ ├── mask.v │ ├── min_number.v │ ├── ni.v │ ├── ovc_status.v │ ├── route_compute.v │ ├── router.v │ ├── sdram_core.v │ ├── sw_alloc_first_arbiter.v │ ├── sw_alloc_second_arbiter.v │ ├── sw_out.v │ ├── sw_sep_alloc.v │ ├── switch_in.v │ └── tasks.v ├── SoC_IP_top.v ├── aemb │ ├── aeMB2_brcc.v │ ├── aeMB2_bsft.v │ ├── aeMB2_ctrl.v │ ├── aeMB2_dparam.v │ ├── aeMB2_dwbif.v │ ├── aeMB2_edk62.v │ ├── aeMB2_edk63.v │ ├── aeMB2_exec.v │ ├── aeMB2_gprf.v │ ├── aeMB2_iche.v │ ├── aeMB2_iche.v.bak │ ├── aeMB2_intu.v │ ├── aeMB2_iwbif.v │ ├── aeMB2_iwbif.v.bak │ ├── aeMB2_memif.v │ ├── aeMB2_mult.v │ ├── aeMB2_pipe.v │ ├── aeMB2_regs.v │ ├── aeMB2_sim.v │ ├── aeMB2_sim.v.bak │ ├── aeMB2_sparam.v │ ├── aeMB2_spsram.v │ ├── aeMB2_tpsram.v │ ├── aeMB2_xslif.v │ ├── aeMB_bpcu.v │ ├── aeMB_core.v │ ├── aeMB_ctrl.v │ ├── aeMB_edk32.v │ ├── aeMB_ibuf.v │ ├── aeMB_regf.v │ ├── aeMB_sim.v │ └── aeMB_xecu.v ├── define.v ├── my_functions.v ├── parameter.v ├── testbench_mpsoc.v ├── testbench_noc.v └── testbench_soc.v └── sw ├── compile ├── aemb.specs ├── aemb │ ├── core.hh │ ├── heap.hh │ ├── hook.hh │ ├── msr.hh │ ├── semaphore.hh │ ├── stack.hh │ ├── stdio.hh │ └── thread.hh ├── custom_crt │ ├── crt0.s │ └── crtinit.s ├── gccrom ├── ihex │ ├── Makefile │ ├── ihex.c │ ├── ihex2mif │ ├── main.c │ └── out.mif ├── orsocdef.h ├── out │ ├── dump.vmem │ ├── ram0.mif │ ├── rom │ └── rom.dump ├── system.h └── xilinx.ld ├── compile_mpsoc ├── compile_soc ├── mpsoc_code ├── cpu00_00.c ├── cpu00_01.c ├── cpu00_02.c ├── cpu00_03.c ├── cpu01_00.c ├── cpu01_01.c ├── cpu01_02.c ├── cpu01_03.c ├── cpu02_00.c ├── cpu02_01.c ├── cpu02_02.c ├── cpu02_03.c ├── cpu03_00.c ├── cpu03_01.c ├── cpu03_02.c ├── cpu03_03.c └── do ├── prog_memories ├── ram ├── cpu00_00.mif ├── cpu00_01.mif ├── cpu00_02.mif ├── cpu00_03.mif ├── cpu01_00.mif ├── cpu01_01.mif ├── cpu01_02.mif ├── cpu01_03.mif ├── cpu02_00.mif ├── cpu02_01.mif ├── cpu02_02.mif ├── cpu02_03.mif ├── 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