├── doc ├── Schematic │ ├── FWFT-FIFO.pdf │ ├── OVC_status.pdf │ ├── Sw_alloc_first_in_first_arbiter.pdf │ ├── input_buffer.pdf │ ├── prop_router.pdf │ ├── request_mask.pdf │ ├── router.pdf │ └── sw_in.pdf └── usermanual.pdf └── noc_based_mpsoc ├── DE2_115_pin_assignments.csv ├── clk50.sdc ├── mpsoc.qpf ├── mpsoc.qsf ├── mpsoc.qws ├── mpsoc_nativelink_simulation.rpt ├── output_files └── mpsoc.sof ├── simulation └── modelsim │ └── sw │ └── ram │ ├── cpu00_00.mif │ ├── cpu00_01.mif │ ├── cpu00_02.mif │ ├── cpu00_03.mif │ ├── cpu01_00.mif │ ├── cpu01_01.mif │ ├── cpu01_02.mif │ ├── cpu01_03.mif │ ├── cpu02_00.mif │ ├── cpu02_01.mif │ ├── cpu02_02.mif │ ├── cpu02_03.mif │ ├── cpu03_00.mif │ ├── cpu03_01.mif │ ├── cpu03_02.mif │ ├── cpu03_03.mif │ └── send.mif ├── src ├── IP_core │ ├── IP_testbench.v │ ├── aeMB_IP.v │ ├── aeMB_mpsoc.v │ ├── altera_reset_synchronizer.v │ ├── bus_addr_cmp.v │ ├── ext_int.v │ ├── gpio.v │ ├── int_ctrl.v │ ├── ip_testbench.v │ ├── prog_ram.v │ ├── reset_jtag.v │ ├── sdram │ │ ├── .qsys_edit │ │ │ ├── filters.xml │ │ │ └── preferences.xml │ │ ├── sdram.qsys │ │ ├── simulation │ │ │ ├── aldec │ │ │ │ └── rivierapro_setup.tcl │ │ │ ├── cadence │ │ │ │ ├── cds.lib │ │ │ │ ├── cds_libs │ │ │ │ │ ├── rst_controller.cds.lib │ │ │ │ │ ├── sdram_controller.cds.lib │ │ │ │ │ └── up_clocks_0.cds.lib │ │ │ │ ├── hdl.var │ │ │ │ └── ncsim_setup.sh │ │ │ ├── mentor │ │ │ │ └── msim_setup.tcl │ │ │ ├── sdram.sip │ │ │ ├── sdram.v │ │ │ ├── submodules │ │ │ │ ├── MT48LC8M16A2.V │ │ │ │ ├── altera_reset_controller.sdc │ │ │ │ ├── altera_reset_controller.v │ │ │ │ ├── altera_reset_synchronizer.v │ │ │ │ ├── sdram_sdram_controller.v │ │ │ │ ├── sdram_sdram_controller_test_component.v │ │ │ │ └── sdram_up_clocks_0.v │ │ │ └── synopsys │ │ │ │ ├── vcs │ │ │ │ └── vcs_setup.sh │ │ │ │ └── vcsmx │ │ │ │ ├── synopsys_sim.setup │ │ │ │ └── vcsmx_setup.sh │ │ ├── synthesis │ │ │ ├── sdram.qip │ │ │ ├── sdram.v │ │ │ └── submodules │ │ │ │ ├── altera_reset_controller.sdc │ │ │ │ ├── altera_reset_controller.v │ │ │ │ ├── altera_reset_synchronizer.v │ │ │ │ ├── sdram_sdram_controller.v │ │ │ │ ├── sdram_sdram_controller_test_component.v │ │ │ │ └── sdram_up_clocks_0.v │ │ └── testbench │ │ │ ├── sdram.ipx │ │ │ ├── sdram_tb.html │ │ │ ├── sdram_tb.qsys │ │ │ └── sdram_tb │ │ │ └── simulation │ │ │ ├── sdram_tb.v │ │ │ └── submodules │ │ │ ├── altera_avalon_clock_source.sv │ │ │ ├── altera_avalon_reset_source.sv │ │ │ ├── altera_reset_controller.sdc │ │ │ ├── altera_reset_controller.v │ │ │ ├── altera_reset_synchronizer.v │ │ │ ├── altera_sdram_partner_module.v │ │ │ ├── sdram.v │ │ │ ├── sdram_sdram_controller.v │ │ │ ├── sdram_sdram_controller_test_component.v │ │ │ ├── sdram_up_clocks_0.v │ │ │ └── verbosity_pkg.sv │ ├── signal_holder.v │ ├── timer.v │ └── wishbone_bus.v ├── MPSoC_top.v ├── NoC │ ├── Dimitrakopoulos_arbiter.v │ ├── MUX.v │ ├── arbiter.v │ ├── cross_bar.v │ ├── dual_port_ram.v │ ├── ext_ram_nic.v │ ├── fifo_buffer.v │ ├── fwft_fifo.v │ ├── mask.v │ ├── min_number.v │ ├── ni.v │ ├── ovc_status.v │ ├── route_compute.v │ ├── router.v │ ├── sdram_core.v │ ├── sw_alloc_first_arbiter.v │ ├── sw_alloc_second_arbiter.v │ ├── sw_out.v │ ├── sw_sep_alloc.v │ ├── switch_in.v │ └── tasks.v ├── SoC_IP_top.v ├── aemb │ ├── aeMB2_brcc.v │ ├── aeMB2_bsft.v │ ├── aeMB2_ctrl.v │ ├── aeMB2_dparam.v │ ├── aeMB2_dwbif.v │ ├── aeMB2_edk62.v │ ├── aeMB2_edk63.v │ ├── aeMB2_exec.v │ ├── aeMB2_gprf.v │ ├── aeMB2_iche.v │ ├── aeMB2_iche.v.bak │ ├── aeMB2_intu.v │ ├── aeMB2_iwbif.v │ ├── aeMB2_iwbif.v.bak │ ├── aeMB2_memif.v │ ├── aeMB2_mult.v │ ├── aeMB2_pipe.v │ ├── aeMB2_regs.v │ ├── aeMB2_sim.v │ ├── aeMB2_sim.v.bak │ ├── aeMB2_sparam.v │ ├── aeMB2_spsram.v │ ├── aeMB2_tpsram.v │ ├── aeMB2_xslif.v │ ├── aeMB_bpcu.v │ ├── aeMB_core.v │ ├── aeMB_ctrl.v │ ├── aeMB_edk32.v │ ├── aeMB_ibuf.v │ ├── aeMB_regf.v │ ├── aeMB_sim.v │ └── aeMB_xecu.v ├── define.v ├── my_functions.v ├── parameter.v ├── testbench_mpsoc.v ├── testbench_noc.v └── testbench_soc.v └── sw ├── compile ├── aemb.specs ├── aemb │ ├── core.hh │ ├── heap.hh │ ├── hook.hh │ ├── msr.hh │ ├── semaphore.hh │ ├── stack.hh │ ├── stdio.hh │ └── thread.hh ├── custom_crt │ ├── crt0.s │ └── crtinit.s ├── gccrom ├── ihex │ ├── Makefile │ ├── ihex.c │ ├── ihex2mif │ ├── main.c │ └── out.mif ├── orsocdef.h ├── out │ ├── dump.vmem │ ├── ram0.mif │ ├── rom │ └── rom.dump ├── system.h └── xilinx.ld ├── compile_mpsoc ├── compile_soc ├── mpsoc_code ├── cpu00_00.c ├── cpu00_01.c ├── cpu00_02.c ├── cpu00_03.c ├── cpu01_00.c ├── cpu01_01.c ├── cpu01_02.c ├── cpu01_03.c ├── cpu02_00.c ├── cpu02_01.c ├── cpu02_02.c ├── cpu02_03.c ├── cpu03_00.c ├── cpu03_01.c ├── cpu03_02.c ├── cpu03_03.c └── do ├── prog_memories ├── ram ├── cpu00_00.mif ├── cpu00_01.mif ├── cpu00_02.mif ├── cpu00_03.mif ├── cpu01_00.mif ├── cpu01_01.mif ├── cpu01_02.mif ├── cpu01_03.mif ├── cpu02_00.mif ├── cpu02_01.mif ├── cpu02_02.mif ├── cpu02_03.mif ├── cpu03_00.mif ├── cpu03_01.mif ├── cpu03_02.mif ├── cpu03_03.mif └── send.mif ├── soc_code └── soc.c └── tcl └── prog.tcl /doc/Schematic/FWFT-FIFO.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/an-fpga-implementation-of-low-latency-noc-based-mpsoc/3d72f1b026eeb6a47f23c81992718af315b342f6/doc/Schematic/FWFT-FIFO.pdf -------------------------------------------------------------------------------- /doc/Schematic/OVC_status.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/an-fpga-implementation-of-low-latency-noc-based-mpsoc/3d72f1b026eeb6a47f23c81992718af315b342f6/doc/Schematic/OVC_status.pdf -------------------------------------------------------------------------------- /doc/Schematic/Sw_alloc_first_in_first_arbiter.pdf: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /doc/usermanual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/an-fpga-implementation-of-low-latency-noc-based-mpsoc/3d72f1b026eeb6a47f23c81992718af315b342f6/doc/usermanual.pdf -------------------------------------------------------------------------------- /noc_based_mpsoc/clk50.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 13 [get_ports CLOCK_50] 2 | -------------------------------------------------------------------------------- /noc_based_mpsoc/mpsoc.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.0.0 Build 156 04/24/2013 SJ Full Version 21 | # Date created = 17:41:22 December 25, 2013 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.0" 26 | DATE = "17:41:22 December 25, 2013" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "mpsoc" 31 | -------------------------------------------------------------------------------- /noc_based_mpsoc/mpsoc.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/an-fpga-implementation-of-low-latency-noc-based-mpsoc/3d72f1b026eeb6a47f23c81992718af315b342f6/noc_based_mpsoc/mpsoc.qws -------------------------------------------------------------------------------- /noc_based_mpsoc/mpsoc_nativelink_simulation.rpt: -------------------------------------------------------------------------------- 1 | Info: Start Nativelink Simulation process 2 | Info: NativeLink has detected Verilog design -- Verilog simulation models will be used 3 | 4 | ========= EDA Simulation Settings ===================== 5 | 6 | Sim Mode : RTL 7 | Family : cycloneive 8 | Quartus root : /home/alireza/altera/quartus/linux64/ 9 | Quartus sim root : /home/alireza/altera/quartus/eda/sim_lib 10 | Simulation Tool : modelsim-altera 11 | Simulation Language : verilog 12 | Simulation Mode : GUI 13 | Sim Output File : 14 | Sim SDF file : 15 | Sim dir : simulation/modelsim 16 | 17 | ======================================================= 18 | 19 | Info: Starting NativeLink simulation with ModelSim-Altera software 20 | Sourced NativeLink script /home/alireza/altera/quartus/common/tcl/internal/nativelink/modelsim.tcl 21 | Warning: File mpsoc_run_msim_rtl_verilog.do already exists - backing up current file as mpsoc_run_msim_rtl_verilog.do.bak11 22 | Info: Spawning ModelSim-Altera Simulation software 23 | -------------------------------------------------------------------------------- /noc_based_mpsoc/output_files/mpsoc.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/an-fpga-implementation-of-low-latency-noc-based-mpsoc/3d72f1b026eeb6a47f23c81992718af315b342f6/noc_based_mpsoc/output_files/mpsoc.sof -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/IP_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module IP_testbench (); 4 | parameter SEVEN_SEG_NUM = 8; 5 | 6 | reg clk,reset,sys_ena_i,sys_int_i; 7 | wire [(SEVEN_SEG_NUM*7)-1:0] seven_segment; 8 | 9 | aeMB_SOC #( 10 | .SEVEN_SEG_NUM (SEVEN_SEG_NUM ) 11 | ) 12 | the_soc 13 | 14 | ( 15 | 16 | .clk (clk), 17 | .reset (reset), 18 | .sys_int_i (sys_int_i), 19 | .sys_ena_i (sys_ena_i), 20 | .seven_segment (seven_segment) 21 | ); 22 | 23 | initial begin 24 | clk = 1'b0; 25 | forever clk = # 10 ~clk; 26 | end 27 | 28 | initial begin 29 | reset =1'b0; 30 | sys_ena_i =1'b1; 31 | sys_int_i = 1'b0; 32 | 33 | # 50 34 | @(posedge clk ) # 1 reset =1'b1; 35 | 36 | #100 37 | @(posedge clk ) # 1 reset =1'b0; 38 | 39 | 40 | 41 | 42 | 43 | 44 | end 45 | 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/bus_addr_cmp.v: -------------------------------------------------------------------------------- 1 | /********************************************************************* 2 | 3 | File: bus_addr_cmp.v 4 | 5 | Copyright (C) 2014 Alireza Monemi 6 | 7 | This program is free software: you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation, either version 3 of the License, or 10 | (at your option) any later version. 11 | 12 | This program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License 18 | along with this program. If not, see . 19 | 20 | 21 | Purpose: 22 | wishbone bus address comparator 23 | 24 | Info: monemi@fkegraduate.utm.my 25 | 26 | ****************************************************************/ 27 | 28 | 29 | 30 | module bus_addr_cmp #( 31 | parameter RAM_EN = 1, 32 | parameter NOC_EN = 1, 33 | parameter GPIO_EN = 1, 34 | parameter EXT_INT_EN = 1, 35 | parameter TIMER_EN = 1, 36 | parameter INT_CTRL_EN = 1, 37 | //parameter NEW_DEV_EN = 1, 38 | parameter ADDR_PERFIX_ = 8, 39 | parameter SLAVE_NUM_ = 3 40 | ) 41 | ( 42 | input [ADDR_PERFIX_-1 : 0] addr_in, 43 | output [SLAVE_NUM_-1 : 0] cmp_out 44 | ); 45 | 46 | `define ADD_BUS_LOCALPARAM 1 47 | `include "../parameter.v" 48 | 49 | 50 | 51 | wire [ADDR_PERFIX-1: 0] base_start_addr [SLAVE_NUM-1 : 0]; 52 | wire [ADDR_PERFIX-1: 0] base_end_addr [SLAVE_NUM-1 : 0]; 53 | 54 | genvar k; 55 | generate 56 | for (k=0;k= base_start_addr [k] ) & ( addr_in < base_end_addr[k] ); 89 | 90 | end//for 91 | endgenerate 92 | 93 | 94 | endmodule 95 | 96 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/ext_int.v: -------------------------------------------------------------------------------- 1 | module ext_int #( 2 | parameter EXT_INT_NUM = 3,//max 32 3 | parameter ADDR_WIDTH = 3, 4 | parameter SEL_WIDTH = 4, 5 | parameter DATA_WIDTH = EXT_INT_NUM 6 | 7 | )( 8 | input clk, 9 | input reset, 10 | //wishbone bus interface 11 | input [DATA_WIDTH-1 : 0] sa_dat_i, 12 | input [SEL_WIDTH-1 : 0] sa_sel_i, 13 | input [ADDR_WIDTH-1 : 0] sa_addr_i, 14 | input sa_stb_i, 15 | input sa_we_i, 16 | output [DATA_WIDTH-1 : 0] sa_dat_o, 17 | output reg sa_ack_o, 18 | //interrupt ports 19 | input [EXT_INT_NUM-1 : 0] ext_int_i, 20 | output ext_int_o //output to the interrupt controller 21 | 22 | ); 23 | 24 | //interrupt registers 25 | 26 | localparam [ADDR_WIDTH-1 : 0] GER_REG_ADDR = 0; 27 | localparam [ADDR_WIDTH-1 : 0] IER_RISING_REG_ADDR = 1; 28 | localparam [ADDR_WIDTH-1 : 0] IER_FALLING_REG_ADDR = 2; 29 | localparam [ADDR_WIDTH-1 : 0] ISR_REG_ADDR = 3; 30 | localparam [ADDR_WIDTH-1 : 0] PIN_REG_ADDR = 4; 31 | 32 | 33 | reg ger,ger_next; 34 | reg [EXT_INT_NUM-1 : 0] ier_rise,ier_fall,isr,read,int_reg1,int_reg2;//2 35 | reg [EXT_INT_NUM-1 : 0] ier_rise_next,ier_fall_next,isr_next,read_next,int_reg1_next,int_reg2_next; 36 | 37 | wire [EXT_INT_NUM-1 : 0] triggered,rise_edge,fall_edge; 38 | 39 | assign rise_edge = (ger)? ier_rise & ~int_reg2 & int_reg1 : {EXT_INT_NUM{1'b0}}; 40 | assign fall_edge = (ger)? ier_fall & int_reg2 & ~int_reg1 : {EXT_INT_NUM{1'b0}}; 41 | 42 | assign triggered = rise_edge | fall_edge; 43 | 44 | always @ (posedge clk or posedge reset) begin 45 | if(reset) begin 46 | ger <= 1'b0; 47 | ier_rise <= {EXT_INT_NUM{1'b0}}; 48 | ier_fall <= {EXT_INT_NUM{1'b0}}; 49 | isr <= {EXT_INT_NUM{1'b0}}; 50 | read <= {EXT_INT_NUM{1'b0}}; 51 | int_reg1 <= {EXT_INT_NUM{1'b0}}; 52 | int_reg2 <= {EXT_INT_NUM{1'b0}}; 53 | sa_ack_o <= 1'b0; 54 | 55 | end else begin 56 | ger <= ger_next; 57 | ier_rise <= ier_rise_next; 58 | ier_fall <= ier_fall_next; 59 | isr <= isr_next; 60 | read <= read_next; 61 | int_reg1 <= int_reg1_next; 62 | int_reg2 <= int_reg2_next; 63 | sa_ack_o <= sa_stb_i && ~sa_ack_o; 64 | end// 65 | end//always 66 | 67 | always@(*) begin 68 | int_reg2_next = int_reg1; 69 | int_reg1_next = ext_int_i; 70 | ger_next = ger; 71 | ier_rise_next = ier_rise; 72 | ier_fall_next = ier_fall; 73 | isr_next = isr | triggered; // set isr if the intrrupt is triggered 74 | read_next = read; 75 | if(sa_stb_i && sa_we_i ) begin 76 | if( sa_addr_i == GER_REG_ADDR ) ger_next = sa_dat_i[0]; 77 | if( sa_addr_i == IER_RISING_REG_ADDR ) ier_rise_next = sa_dat_i[EXT_INT_NUM-1'b1 : 0]; 78 | if( sa_addr_i == IER_FALLING_REG_ADDR ) ier_fall_next = sa_dat_i[EXT_INT_NUM-1'b1 : 0]; 79 | if( sa_addr_i == ISR_REG_ADDR ) isr_next = isr & ~sa_dat_i[EXT_INT_NUM-1'b1 : 0];// reset isr by writting 1 80 | end 81 | if(sa_stb_i && ~sa_we_i) begin 82 | case(sa_addr_i) 83 | GER_REG_ADDR: read_next = {{(EXT_INT_NUM-1){1'b0}},ger}; 84 | IER_RISING_REG_ADDR: read_next = ier_rise; 85 | IER_FALLING_REG_ADDR: read_next = ier_fall; 86 | ISR_REG_ADDR: read_next = isr; 87 | PIN_REG_ADDR: read_next = ext_int_i; 88 | default read_next = read; 89 | endcase 90 | end 91 | end//always 92 | 93 | 94 | 95 | assign sa_dat_o = read; 96 | assign ext_int_o = |isr; 97 | 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/int_ctrl.v: -------------------------------------------------------------------------------- 1 | module int_ctrl #( 2 | parameter NOC_EN = 0, 3 | parameter EXT_INT_EN = 1, 4 | parameter TIMER_EN = 1, 5 | parameter INT_NUM = 32, 6 | parameter DATA_WIDTH = 32, 7 | parameter SEL_WIDTH = 4, 8 | parameter ADDR_WIDTH = 3 9 | 10 | 11 | ) 12 | ( 13 | input clk, 14 | input reset, 15 | // wishbone interface 16 | input [DATA_WIDTH-1 : 0] sa_dat_i, 17 | input [SEL_WIDTH-1 : 0] sa_sel_i, 18 | input [ADDR_WIDTH-1 : 0] sa_addr_i, 19 | input sa_stb_i, 20 | input sa_we_i, 21 | output [DATA_WIDTH-1 : 0] sa_dat_o, 22 | output reg sa_ack_o, 23 | //intruupt interface 24 | input [INT_NUM-1 : 0 ] int_i, 25 | output int_o 26 | 27 | 28 | ); 29 | localparam [ADDR_WIDTH-1 : 0] MER_REG_ADDR = 0; 30 | localparam [ADDR_WIDTH-1 : 0] IER_REG_ADDR = 1; 31 | localparam [ADDR_WIDTH-1 : 0] IAR_REG_ADDR = 2; 32 | localparam [ADDR_WIDTH-1 : 0] IPR_REG_ADDR = 3; 33 | 34 | localparam LD_ZERO = (INT_NUM >2 )? INT_NUM-2 : 0; 35 | localparam DATA_BUS_MASK = (EXT_INT_EN <<2) + (TIMER_EN << 1)+ NOC_EN ; 36 | //internal register 37 | reg [INT_NUM-1 : 0] ipr,ier,iar; 38 | reg [INT_NUM-1 : 0] ipr_next,ier_next,iar_next; 39 | reg [INT_NUM-1 : 0] read,read_next; 40 | reg [1:0] mer,mer_next; 41 | 42 | wire [INT_NUM-1:0] sa_dat_i_masked, int_i_masked; 43 | 44 | assign sa_dat_i_masked = sa_dat_i & DATA_BUS_MASK [INT_NUM-1:0]; 45 | assign int_i_masked = int_i & DATA_BUS_MASK [INT_NUM-1:0]; 46 | always@(*) begin 47 | mer_next = mer; 48 | ier_next = ier; 49 | iar_next = iar & ~ int_i_masked; 50 | ipr_next = (ipr | int_i_masked) & ier; 51 | 52 | read_next = read; 53 | if(sa_stb_i ) 54 | if(sa_we_i ) begin 55 | case(sa_addr_i) 56 | MER_REG_ADDR: mer_next = sa_dat_i[1:0]; 57 | IER_REG_ADDR: ier_next = sa_dat_i_masked[INT_NUM-1 : 0]; 58 | IAR_REG_ADDR: begin 59 | iar_next = iar | sa_dat_i_masked[INT_NUM-1 : 0];//set iar by writting 1 60 | ipr_next = ipr & ~sa_dat_i_masked[INT_NUM-1 : 0];//reset ipr by writting 1 61 | end 62 | default: ipr_next = ipr | int_i_masked; 63 | endcase 64 | end//we 65 | else begin 66 | case(sa_addr_i) 67 | MER_REG_ADDR: read_next = {{LD_ZERO{1'b0}},mer}; 68 | IER_REG_ADDR: read_next = ier; 69 | IAR_REG_ADDR: read_next = iar; 70 | IPR_REG_ADDR: read_next = ipr; 71 | default: read_next = read; 72 | endcase 73 | end 74 | end//stb 75 | 76 | always @(posedge clk) begin 77 | if(reset)begin 78 | mer <= 2'b0; 79 | ier <= {INT_NUM{1'b0}}; 80 | iar <= {INT_NUM{1'b0}}; 81 | ipr <= {INT_NUM{1'b0}}; 82 | read <= {INT_NUM{1'b0}}; 83 | sa_ack_o <= 1'b0; 84 | end else begin 85 | mer <= mer_next; 86 | ier <= ier_next; 87 | iar <= iar_next; 88 | ipr <= ipr_next; 89 | read <= read_next; 90 | sa_ack_o <= sa_stb_i && ~sa_ack_o; 91 | end 92 | end 93 | 94 | assign int_o = ((mer == 2'b11) && (ier & ipr) ) ? 1'b1 :1'b0; 95 | assign sa_dat_o = {{(DATA_WIDTH-INT_NUM){1'b0}},read}; 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/reset_jtag.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %In-System Sources and Probes% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsource_probe 5 | 6 | // ============================================================ 7 | // File Name: reset_jtag.v 8 | // Megafunction Name(s): 9 | // altsource_probe 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 13.0.0 Build 156 04/24/2013 SJ Full Version 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2013 Altera Corporation 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, Altera MegaCore Function License 29 | //Agreement, or other applicable license agreement, including, 30 | //without limitation, that your use is for the sole purpose of 31 | //programming logic devices manufactured by Altera and sold by 32 | //Altera or its authorized distributors. Please refer to the 33 | //applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module reset_jtag ( 40 | probe, 41 | source); 42 | 43 | input [0:0] probe; 44 | output [0:0] source; 45 | 46 | wire [0:0] sub_wire0; 47 | wire [0:0] source = sub_wire0[0:0]; 48 | 49 | altsource_probe altsource_probe_component ( 50 | .probe (probe), 51 | .source (sub_wire0) 52 | // synopsys translate_off 53 | , 54 | .clrn (), 55 | .ena (), 56 | .ir_in (), 57 | .ir_out (), 58 | .jtag_state_cdr (), 59 | .jtag_state_cir (), 60 | .jtag_state_e1dr (), 61 | .jtag_state_sdr (), 62 | .jtag_state_tlr (), 63 | .jtag_state_udr (), 64 | .jtag_state_uir (), 65 | .raw_tck (), 66 | .source_clk (), 67 | .source_ena (), 68 | .tdi (), 69 | .tdo (), 70 | .usr1 () 71 | // synopsys translate_on 72 | ); 73 | defparam 74 | altsource_probe_component.enable_metastability = "NO", 75 | altsource_probe_component.instance_id = "RST", 76 | altsource_probe_component.probe_width = 1, 77 | altsource_probe_component.sld_auto_instance_index = "NO", 78 | altsource_probe_component.sld_instance_index = 127, 79 | altsource_probe_component.source_initial_value = " 0", 80 | altsource_probe_component.source_width = 1; 81 | 82 | 83 | endmodule 84 | 85 | // ============================================================ 86 | // CNX file retrieval info 87 | // ============================================================ 88 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 89 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 90 | // Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO" 91 | // Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" 92 | // Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "1" 93 | // Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO" 94 | // Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "127" 95 | // Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" 96 | // Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "1" 97 | // Retrieval info: USED_PORT: probe 0 0 1 0 INPUT NODEFVAL "probe[0..0]" 98 | // Retrieval info: USED_PORT: source 0 0 1 0 OUTPUT NODEFVAL "source[0..0]" 99 | // Retrieval info: CONNECT: @probe 0 0 1 0 probe 0 0 1 0 100 | // Retrieval info: CONNECT: source 0 0 1 0 @source 0 0 1 0 101 | // Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.v TRUE 102 | // Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.inc FALSE 103 | // Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.cmp FALSE 104 | // Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.bsf FALSE 105 | // Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_inst.v FALSE 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_bb.v TRUE 107 | // Retrieval info: LIB_FILE: altera_mf 108 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/.qsys_edit/filters.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE rst_controller ./libraries/rst_controller/ 13 | DEFINE up_clocks_0 ./libraries/up_clocks_0/ 14 | DEFINE sdram_controller ./libraries/sdram_controller/ 15 | DEFINE altera_ver ./libraries/altera_ver/ 16 | DEFINE lpm_ver ./libraries/lpm_ver/ 17 | DEFINE sgate_ver ./libraries/sgate_ver/ 18 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 19 | DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/ 20 | DEFINE cycloneive_ver ./libraries/cycloneive_ver/ 21 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/cadence/cds_libs/rst_controller.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE rst_controller ./../libraries/rst_controller/ 19 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/cadence/cds_libs/sdram_controller.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE sdram_controller ./../libraries/sdram_controller/ 19 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/cadence/cds_libs/up_clocks_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE cycloneive_ver ./../libraries/cycloneive_ver/ 18 | DEFINE up_clocks_0 ./../libraries/up_clocks_0/ 19 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/cadence/ncsim_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2013 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 13.0 156 linux 2013.08.15.18:11:32 16 | 17 | # ---------------------------------------- 18 | # ncsim - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # initialize variables 22 | TOP_LEVEL_NAME="sdram" 23 | QSYS_SIMDIR="./../" 24 | QUARTUS_INSTALL_DIR="/home/alireza/altera/quartus/" 25 | SKIP_FILE_COPY=0 26 | SKIP_DEV_COM=0 27 | SKIP_COM=0 28 | SKIP_ELAB=0 29 | SKIP_SIM=0 30 | USER_DEFINED_ELAB_OPTIONS="" 31 | USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\"" 32 | 33 | # ---------------------------------------- 34 | # overwrite variables - DO NOT MODIFY! 35 | # This block evaluates each command line argument, typically used for 36 | # overwriting variables. An example usage: 37 | # sh _setup.sh SKIP_ELAB=1 SKIP_SIM=1 38 | for expression in "$@"; do 39 | eval $expression 40 | if [ $? -ne 0 ]; then 41 | echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 42 | exit $? 43 | fi 44 | done 45 | 46 | # ---------------------------------------- 47 | # create compilation libraries 48 | mkdir -p ./libraries/work/ 49 | mkdir -p ./libraries/rst_controller/ 50 | mkdir -p ./libraries/up_clocks_0/ 51 | mkdir -p ./libraries/sdram_controller/ 52 | mkdir -p ./libraries/altera_ver/ 53 | mkdir -p ./libraries/lpm_ver/ 54 | mkdir -p ./libraries/sgate_ver/ 55 | mkdir -p ./libraries/altera_mf_ver/ 56 | mkdir -p ./libraries/altera_lnsim_ver/ 57 | mkdir -p ./libraries/cycloneive_ver/ 58 | 59 | # ---------------------------------------- 60 | # copy RAM/ROM files to simulation directory 61 | 62 | # ---------------------------------------- 63 | # compile device library files 64 | if [ $SKIP_DEV_COM -eq 0 ]; then 65 | ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver 66 | ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver 67 | ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver 68 | ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver 69 | ncvlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver 70 | ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver 71 | fi 72 | 73 | # ---------------------------------------- 74 | # compile design files in correct order 75 | if [ $SKIP_COM -eq 0 ]; then 76 | ncvlog "$QSYS_SIMDIR/submodules/altera_reset_controller.v" -work rst_controller -cdslib ./cds_libs/rst_controller.cds.lib 77 | ncvlog "$QSYS_SIMDIR/submodules/altera_reset_synchronizer.v" -work rst_controller -cdslib ./cds_libs/rst_controller.cds.lib 78 | ncvlog "$QSYS_SIMDIR/submodules/sdram_up_clocks_0.v" -work up_clocks_0 -cdslib ./cds_libs/up_clocks_0.cds.lib 79 | ncvlog "$QSYS_SIMDIR/submodules/sdram_sdram_controller_test_component.v" -work sdram_controller -cdslib ./cds_libs/sdram_controller.cds.lib 80 | ncvlog "$QSYS_SIMDIR/submodules/sdram_sdram_controller.v" -work sdram_controller -cdslib ./cds_libs/sdram_controller.cds.lib 81 | ncvlog "$QSYS_SIMDIR/sdram.v" 82 | fi 83 | 84 | # ---------------------------------------- 85 | # elaborate top level design 86 | if [ $SKIP_ELAB -eq 0 ]; then 87 | ncelab -access +w+r+c -namemap_mixgen $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME 88 | fi 89 | 90 | # ---------------------------------------- 91 | # simulate 92 | if [ $SKIP_SIM -eq 0 ]; then 93 | eval ncsim -licqueue $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME 94 | fi 95 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/sdram.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "sdram" -library "lib_sdram" -name IP_TOOL_NAME "Qsys" 2 | set_global_assignment -entity "sdram" -library "lib_sdram" -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -entity "sdram" -library "lib_sdram" -name IP_TOOL_ENV "Qsys" 4 | set_global_assignment -library "lib_sdram" -name SPD_FILE [file join $::quartus(sip_path) "../../sdram.spd"] 5 | set_global_assignment -library "lib_sdram" -name MISC_FILE [file join $::quartus(sip_path) "../../sdram.qsys"] 6 | 7 | set_global_assignment -library "lib_sdram" -name MISC_FILE [file join $::quartus(sip_path) "sdram.v"] 8 | set_global_assignment -library "lib_sdram" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_reset_controller.v"] 9 | set_global_assignment -library "lib_sdram" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_reset_synchronizer.v"] 10 | set_global_assignment -library "lib_sdram" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_reset_controller.sdc"] 11 | set_global_assignment -library "lib_sdram" -name MISC_FILE [file join $::quartus(sip_path) "submodules/sdram_up_clocks_0.v"] 12 | set_global_assignment -library "lib_sdram" -name MISC_FILE [file join $::quartus(sip_path) "submodules/sdram_sdram_controller_test_component.v"] 13 | set_global_assignment -library "lib_sdram" -name MISC_FILE [file join $::quartus(sip_path) "submodules/sdram_sdram_controller.v"] 14 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2013 Altera Corporation. All rights reserved. 2 | # Your use of Altera Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Altera Program License Subscription 7 | # Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Altera and sold by 10 | # Altera or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | foreach_in_collection aclr_pin $aclr_collection { 22 | set aclr_counter [expr $aclr_counter + 1] 23 | } 24 | foreach_in_collection clrn_pin $clrn_collection { 25 | set clrn_counter [expr $clrn_counter + 1] 26 | } 27 | if {$aclr_counter > 0} { 28 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 29 | } 30 | 31 | if {$clrn_counter > 0} { 32 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 33 | } 34 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/submodules/altera_reset_controller.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | 19 | // -------------------------------------- 20 | // Reset controller 21 | // 22 | // Combines all the input resets and synchronizes 23 | // the result to the clk. 24 | // -------------------------------------- 25 | 26 | `timescale 1 ns / 1 ns 27 | 28 | module altera_reset_controller 29 | #( 30 | parameter NUM_RESET_INPUTS = 6, 31 | parameter OUTPUT_RESET_SYNC_EDGES = "deassert", 32 | parameter SYNC_DEPTH = 2 33 | ) 34 | ( 35 | // -------------------------------------- 36 | // We support up to 16 reset inputs, for now 37 | // -------------------------------------- 38 | input reset_in0, 39 | input reset_in1, 40 | input reset_in2, 41 | input reset_in3, 42 | input reset_in4, 43 | input reset_in5, 44 | input reset_in6, 45 | input reset_in7, 46 | input reset_in8, 47 | input reset_in9, 48 | input reset_in10, 49 | input reset_in11, 50 | input reset_in12, 51 | input reset_in13, 52 | input reset_in14, 53 | input reset_in15, 54 | 55 | input clk, 56 | output reset_out 57 | ); 58 | 59 | localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); 60 | 61 | wire merged_reset; 62 | 63 | // -------------------------------------- 64 | // "Or" all the input resets together 65 | // -------------------------------------- 66 | assign merged_reset = ( 67 | reset_in0 | 68 | reset_in1 | 69 | reset_in2 | 70 | reset_in3 | 71 | reset_in4 | 72 | reset_in5 | 73 | reset_in6 | 74 | reset_in7 | 75 | reset_in8 | 76 | reset_in9 | 77 | reset_in10 | 78 | reset_in11 | 79 | reset_in12 | 80 | reset_in13 | 81 | reset_in14 | 82 | reset_in15 83 | ); 84 | 85 | // -------------------------------------- 86 | // And if required, synchronize it to the required clock domain, 87 | // with the correct synchronization type 88 | // -------------------------------------- 89 | generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin 90 | 91 | assign reset_out = merged_reset; 92 | 93 | end else begin 94 | 95 | altera_reset_synchronizer 96 | #( 97 | .DEPTH (SYNC_DEPTH), 98 | .ASYNC_RESET(ASYNC_RESET) 99 | ) 100 | alt_rst_sync_uq1 101 | ( 102 | .clk (clk), 103 | .reset_in (merged_reset), 104 | .reset_out (reset_out) 105 | ); 106 | 107 | end 108 | endgenerate 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/submodules/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/synopsys/vcs/vcs_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2013 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 13.0 156 linux 2013.08.15.18:11:32 16 | 17 | # ---------------------------------------- 18 | # vcs - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # initialize variables 22 | TOP_LEVEL_NAME="sdram" 23 | QSYS_SIMDIR="./../../" 24 | QUARTUS_INSTALL_DIR="/home/alireza/altera/quartus/" 25 | SKIP_FILE_COPY=0 26 | SKIP_ELAB=0 27 | SKIP_SIM=0 28 | USER_DEFINED_ELAB_OPTIONS="" 29 | USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" 30 | # ---------------------------------------- 31 | # overwrite variables - DO NOT MODIFY! 32 | # This block evaluates each command line argument, typically used for 33 | # overwriting variables. An example usage: 34 | # sh _setup.sh SKIP_ELAB=1 SKIP_SIM=1 35 | for expression in "$@"; do 36 | eval $expression 37 | if [ $? -ne 0 ]; then 38 | echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 39 | exit $? 40 | fi 41 | done 42 | 43 | # ---------------------------------------- 44 | # copy RAM/ROM files to simulation directory 45 | 46 | vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $USER_DEFINED_ELAB_OPTIONS \ 47 | -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \ 48 | -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \ 49 | -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \ 50 | -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \ 51 | $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \ 52 | -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v \ 53 | $QSYS_SIMDIR/submodules/altera_reset_controller.v \ 54 | $QSYS_SIMDIR/submodules/altera_reset_synchronizer.v \ 55 | $QSYS_SIMDIR/submodules/sdram_up_clocks_0.v \ 56 | $QSYS_SIMDIR/submodules/sdram_sdram_controller_test_component.v \ 57 | $QSYS_SIMDIR/submodules/sdram_sdram_controller.v \ 58 | $QSYS_SIMDIR/sdram.v \ 59 | -top $TOP_LEVEL_NAME 60 | # ---------------------------------------- 61 | # simulate 62 | if [ $SKIP_SIM -eq 0 ]; then 63 | ./simv $USER_DEFINED_SIM_OPTIONS 64 | fi 65 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | rst_controller: ./libraries/rst_controller/ 6 | up_clocks_0: ./libraries/up_clocks_0/ 7 | sdram_controller: ./libraries/sdram_controller/ 8 | altera_ver: ./libraries/altera_ver/ 9 | lpm_ver: ./libraries/lpm_ver/ 10 | sgate_ver: ./libraries/sgate_ver/ 11 | altera_mf_ver: ./libraries/altera_mf_ver/ 12 | altera_lnsim_ver: ./libraries/altera_lnsim_ver/ 13 | cycloneive_ver: ./libraries/cycloneive_ver/ 14 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/simulation/synopsys/vcsmx/vcsmx_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2013 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 13.0 156 linux 2013.08.15.18:11:32 16 | 17 | # ---------------------------------------- 18 | # vcsmx - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # initialize variables 22 | TOP_LEVEL_NAME="sdram" 23 | QSYS_SIMDIR="./../../" 24 | QUARTUS_INSTALL_DIR="/home/alireza/altera/quartus/" 25 | SKIP_FILE_COPY=0 26 | SKIP_DEV_COM=0 27 | SKIP_COM=0 28 | SKIP_ELAB=0 29 | SKIP_SIM=0 30 | USER_DEFINED_ELAB_OPTIONS="" 31 | USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" 32 | 33 | # ---------------------------------------- 34 | # overwrite variables - DO NOT MODIFY! 35 | # This block evaluates each command line argument, typically used for 36 | # overwriting variables. An example usage: 37 | # sh _setup.sh SKIP_ELAB=1 SKIP_SIM=1 38 | for expression in "$@"; do 39 | eval $expression 40 | if [ $? -ne 0 ]; then 41 | echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 42 | exit $? 43 | fi 44 | done 45 | 46 | # ---------------------------------------- 47 | # create compilation libraries 48 | mkdir -p ./libraries/work/ 49 | mkdir -p ./libraries/rst_controller/ 50 | mkdir -p ./libraries/up_clocks_0/ 51 | mkdir -p ./libraries/sdram_controller/ 52 | mkdir -p ./libraries/altera_ver/ 53 | mkdir -p ./libraries/lpm_ver/ 54 | mkdir -p ./libraries/sgate_ver/ 55 | mkdir -p ./libraries/altera_mf_ver/ 56 | mkdir -p ./libraries/altera_lnsim_ver/ 57 | mkdir -p ./libraries/cycloneive_ver/ 58 | 59 | # ---------------------------------------- 60 | # copy RAM/ROM files to simulation directory 61 | 62 | # ---------------------------------------- 63 | # compile device library files 64 | if [ $SKIP_DEV_COM -eq 0 ]; then 65 | vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver 66 | vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver 67 | vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver 68 | vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver 69 | vlogan +v2k -sverilog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver 70 | vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver 71 | fi 72 | 73 | # ---------------------------------------- 74 | # compile design files in correct order 75 | if [ $SKIP_COM -eq 0 ]; then 76 | vlogan +v2k "$QSYS_SIMDIR/submodules/altera_reset_controller.v" -work rst_controller 77 | vlogan +v2k "$QSYS_SIMDIR/submodules/altera_reset_synchronizer.v" -work rst_controller 78 | vlogan +v2k "$QSYS_SIMDIR/submodules/sdram_up_clocks_0.v" -work up_clocks_0 79 | vlogan +v2k "$QSYS_SIMDIR/submodules/sdram_sdram_controller_test_component.v" -work sdram_controller 80 | vlogan +v2k "$QSYS_SIMDIR/submodules/sdram_sdram_controller.v" -work sdram_controller 81 | vlogan +v2k "$QSYS_SIMDIR/sdram.v" 82 | fi 83 | 84 | # ---------------------------------------- 85 | # elaborate top level design 86 | if [ $SKIP_ELAB -eq 0 ]; then 87 | vcs -lca -t ps $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME 88 | fi 89 | 90 | # ---------------------------------------- 91 | # simulate 92 | if [ $SKIP_SIM -eq 0 ]; then 93 | ./simv $USER_DEFINED_SIM_OPTIONS 94 | fi 95 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/synthesis/sdram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "sdram" -library "sdram" -name IP_TOOL_NAME "Qsys" 2 | set_global_assignment -entity "sdram" -library "sdram" -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -entity "sdram" -library "sdram" -name IP_TOOL_ENV "Qsys" 4 | set_global_assignment -library "sdram" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../sdram.sopcinfo"] 5 | set_instance_assignment -entity "sdram" -library "sdram" -name SLD_INFO "QSYS_NAME sdram HAS_SOPCINFO 1 GENERATION_ID 1376561493" 6 | set_global_assignment -library "sdram" -name MISC_FILE [file join $::quartus(qip_path) "../../sdram.cmp"] 7 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 8 | set_global_assignment -library "sdram" -name MISC_FILE [file join $::quartus(qip_path) "../../sdram.qsys"] 9 | 10 | set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "sdram.v"] 11 | #set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"] 12 | set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"] 13 | #set_global_assignment -library "sdram" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"] 14 | set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sdram_up_clocks_0.v"] 15 | #set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sdram_sdram_controller_test_component.v"] 16 | set_global_assignment -library "sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/sdram_sdram_controller.v"] 17 | 18 | #set_global_assignment -entity "altera_reset_controller" -library "sdram" -name IP_TOOL_NAME "altera_reset_controller" 19 | #set_global_assignment -entity "altera_reset_controller" -library "sdram" -name IP_TOOL_VERSION "13.0" 20 | #set_global_assignment -entity "altera_reset_controller" -library "sdram" -name IP_TOOL_ENV "Qsys" 21 | set_global_assignment -entity "sdram_sdram_controller" -library "sdram" -name IP_TOOL_NAME "altera_avalon_new_sdram_controller" 22 | set_global_assignment -entity "sdram_sdram_controller" -library "sdram" -name IP_TOOL_VERSION "13.0.1" 23 | set_global_assignment -entity "sdram_sdram_controller" -library "sdram" -name IP_TOOL_ENV "Qsys" 24 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/synthesis/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2013 Altera Corporation. All rights reserved. 2 | # Your use of Altera Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Altera Program License Subscription 7 | # Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Altera and sold by 10 | # Altera or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | foreach_in_collection aclr_pin $aclr_collection { 22 | set aclr_counter [expr $aclr_counter + 1] 23 | } 24 | foreach_in_collection clrn_pin $clrn_collection { 25 | set clrn_counter [expr $clrn_counter + 1] 26 | } 27 | if {$aclr_counter > 0} { 28 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 29 | } 30 | 31 | if {$clrn_counter > 0} { 32 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 33 | } 34 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/synthesis/submodules/altera_reset_controller.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | 19 | // -------------------------------------- 20 | // Reset controller 21 | // 22 | // Combines all the input resets and synchronizes 23 | // the result to the clk. 24 | // -------------------------------------- 25 | 26 | `timescale 1 ns / 1 ns 27 | 28 | module altera_reset_controller 29 | #( 30 | parameter NUM_RESET_INPUTS = 6, 31 | parameter OUTPUT_RESET_SYNC_EDGES = "deassert", 32 | parameter SYNC_DEPTH = 2 33 | ) 34 | ( 35 | // -------------------------------------- 36 | // We support up to 16 reset inputs, for now 37 | // -------------------------------------- 38 | input reset_in0, 39 | input reset_in1, 40 | input reset_in2, 41 | input reset_in3, 42 | input reset_in4, 43 | input reset_in5, 44 | input reset_in6, 45 | input reset_in7, 46 | input reset_in8, 47 | input reset_in9, 48 | input reset_in10, 49 | input reset_in11, 50 | input reset_in12, 51 | input reset_in13, 52 | input reset_in14, 53 | input reset_in15, 54 | 55 | input clk, 56 | output reset_out 57 | ); 58 | 59 | localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); 60 | 61 | wire merged_reset; 62 | 63 | // -------------------------------------- 64 | // "Or" all the input resets together 65 | // -------------------------------------- 66 | assign merged_reset = ( 67 | reset_in0 | 68 | reset_in1 | 69 | reset_in2 | 70 | reset_in3 | 71 | reset_in4 | 72 | reset_in5 | 73 | reset_in6 | 74 | reset_in7 | 75 | reset_in8 | 76 | reset_in9 | 77 | reset_in10 | 78 | reset_in11 | 79 | reset_in12 | 80 | reset_in13 | 81 | reset_in14 | 82 | reset_in15 83 | ); 84 | 85 | // -------------------------------------- 86 | // And if required, synchronize it to the required clock domain, 87 | // with the correct synchronization type 88 | // -------------------------------------- 89 | generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin 90 | 91 | assign reset_out = merged_reset; 92 | 93 | end else begin 94 | 95 | altera_reset_synchronizer 96 | #( 97 | .DEPTH (SYNC_DEPTH), 98 | .ASYNC_RESET(ASYNC_RESET) 99 | ) 100 | alt_rst_sync_uq1 101 | ( 102 | .clk (clk), 103 | .reset_in (merged_reset), 104 | .reset_out (reset_out) 105 | ); 106 | 107 | end 108 | endgenerate 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/synthesis/submodules/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/testbench/sdram.ipx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/testbench/sdram_tb/simulation/submodules/altera_avalon_clock_source.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $File: //acds/rel/13.0/ip/sopc/components/verification/altera_avalon_clock_source/altera_avalon_clock_source.sv $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | //------------------------------------------------------------------------------ 19 | // Clock generator 20 | 21 | `timescale 1ns / 1ps 22 | 23 | module altera_avalon_clock_source (clk); 24 | output clk; 25 | 26 | parameter CLOCK_RATE = 10; // clock rate in MHz / kHz / Hz depends on the clock unit 27 | parameter CLOCK_UNIT = 1000000; // clock unit MHz / kHz / Hz 28 | 29 | // synthesis translate_off 30 | import verbosity_pkg::*; 31 | 32 | localparam HALF_CLOCK_PERIOD = 1000000000.000000/(CLOCK_RATE*CLOCK_UNIT*2); // half clock period in ns 33 | 34 | logic clk = 1'b0; 35 | 36 | string message = "*uninitialized*"; 37 | string freq_unit = (CLOCK_UNIT == 1)? "Hz" : 38 | (CLOCK_UNIT == 1000)? "kHz" : "MHz"; 39 | bit run_state = 1'b1; 40 | 41 | function automatic void __hello(); 42 | $sformat(message, "%m: - Hello from altera_clock_source."); 43 | print(VERBOSITY_INFO, message); 44 | $sformat(message, "%m: - $Revision: #1 $"); 45 | print(VERBOSITY_INFO, message); 46 | $sformat(message, "%m: - $Date: 2013/02/11 $"); 47 | print(VERBOSITY_INFO, message); 48 | $sformat(message, "%m: - CLOCK_RATE = %0d %s", CLOCK_RATE, freq_unit); 49 | print(VERBOSITY_INFO, message); 50 | print_divider(VERBOSITY_INFO); 51 | endfunction 52 | 53 | function automatic string get_version(); // public 54 | // Return BFM version as a string of three integers separated by periods. 55 | // For example, version 9.1 sp1 is encoded as "9.1.1". 56 | string ret_version = "13.0"; 57 | return ret_version; 58 | endfunction 59 | 60 | task automatic clock_start(); // public 61 | // Turn the clock on. By default the clock is initially turned on. 62 | $sformat(message, "%m: Clock started"); 63 | print(VERBOSITY_INFO, message); 64 | run_state = 1; 65 | endtask 66 | 67 | task automatic clock_stop(); // public 68 | // Turn the clock off. 69 | $sformat(message, "%m: Clock stopped"); 70 | print(VERBOSITY_INFO, message); 71 | run_state = 0; 72 | endtask 73 | 74 | function automatic get_run_state(); // public 75 | // Return the state of the clock source: running=1, stopped=0 76 | return run_state; 77 | endfunction 78 | 79 | initial begin 80 | __hello(); 81 | end 82 | 83 | always begin 84 | #HALF_CLOCK_PERIOD; 85 | clk = run_state; 86 | 87 | #HALF_CLOCK_PERIOD; 88 | clk = 1'b0; 89 | end 90 | // synthesis translate_on 91 | 92 | endmodule 93 | 94 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/testbench/sdram_tb/simulation/submodules/altera_avalon_reset_source.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $File: //acds/rel/13.0/ip/sopc/components/verification/altera_avalon_reset_source/altera_avalon_reset_source.sv $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | //------------------------------------------------------------------------------ 19 | // Reset generator 20 | 21 | `timescale 1ns / 1ns 22 | 23 | module altera_avalon_reset_source ( 24 | clk, 25 | reset 26 | ); 27 | input clk; 28 | output reset; 29 | 30 | parameter ASSERT_HIGH_RESET = 1; // reset assertion level is high by default 31 | parameter INITIAL_RESET_CYCLES = 0; // deassert after number of clk cycles 32 | 33 | // synthesis translate_off 34 | import verbosity_pkg::*; 35 | 36 | logic reset = ASSERT_HIGH_RESET ? 1'b0 : 1'b1; 37 | 38 | string message = "*uninitialized*"; 39 | 40 | int clk_ctr = 0; 41 | 42 | always @(posedge clk) begin 43 | clk_ctr <= clk_ctr + 1; 44 | end 45 | 46 | always @(*) 47 | if (clk_ctr == INITIAL_RESET_CYCLES) 48 | reset_deassert(); 49 | 50 | 51 | function automatic void __hello(); 52 | $sformat(message, "%m: - Hello from altera_reset_source"); 53 | print(VERBOSITY_INFO, message); 54 | $sformat(message, "%m: - $Revision: #1 $"); 55 | print(VERBOSITY_INFO, message); 56 | $sformat(message, "%m: - $Date: 2013/02/11 $"); 57 | print(VERBOSITY_INFO, message); 58 | $sformat(message, "%m: - ASSERT_HIGH_RESET = %0d", ASSERT_HIGH_RESET); 59 | print(VERBOSITY_INFO, message); 60 | $sformat(message, "%m: - INITIAL_RESET_CYCLES = %0d", INITIAL_RESET_CYCLES); 61 | print(VERBOSITY_INFO, message); 62 | print_divider(VERBOSITY_INFO); 63 | endfunction 64 | 65 | function automatic string get_version(); // public 66 | // Return BFM version as a string of three integers separated by periods. 67 | // For example, version 9.1 sp1 is encoded as "9.1.1". 68 | string ret_version = "13.0"; 69 | return ret_version; 70 | endfunction 71 | 72 | task automatic reset_assert(); // public 73 | $sformat(message, "%m: Reset asserted"); 74 | print(VERBOSITY_INFO, message); 75 | 76 | if (ASSERT_HIGH_RESET > 0) begin 77 | reset = 1'b1; 78 | end else begin 79 | reset = 1'b0; 80 | end 81 | endtask 82 | 83 | task automatic reset_deassert(); // public 84 | $sformat(message, "%m: Reset deasserted"); 85 | print(VERBOSITY_INFO, message); 86 | 87 | if (ASSERT_HIGH_RESET > 0) begin 88 | reset = 1'b0; 89 | end else begin 90 | reset = 1'b1; 91 | end 92 | endtask 93 | 94 | initial begin 95 | __hello(); 96 | if (INITIAL_RESET_CYCLES > 0) 97 | reset_assert(); 98 | end 99 | // synthesis translate_on 100 | 101 | endmodule 102 | 103 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/testbench/sdram_tb/simulation/submodules/altera_reset_controller.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2013 Altera Corporation. All rights reserved. 2 | # Your use of Altera Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Altera Program License Subscription 7 | # Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Altera and sold by 10 | # Altera or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # +--------------------------------------------------- 15 | # | Cut the async clear paths 16 | # +--------------------------------------------------- 17 | set aclr_counter 0 18 | set clrn_counter 0 19 | set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 20 | set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 21 | foreach_in_collection aclr_pin $aclr_collection { 22 | set aclr_counter [expr $aclr_counter + 1] 23 | } 24 | foreach_in_collection clrn_pin $clrn_collection { 25 | set clrn_counter [expr $clrn_counter + 1] 26 | } 27 | if {$aclr_counter > 0} { 28 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] 29 | } 30 | 31 | if {$clrn_counter > 0} { 32 | set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] 33 | } 34 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/testbench/sdram_tb/simulation/submodules/altera_reset_controller.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | 19 | // -------------------------------------- 20 | // Reset controller 21 | // 22 | // Combines all the input resets and synchronizes 23 | // the result to the clk. 24 | // -------------------------------------- 25 | 26 | `timescale 1 ns / 1 ns 27 | 28 | module altera_reset_controller 29 | #( 30 | parameter NUM_RESET_INPUTS = 6, 31 | parameter OUTPUT_RESET_SYNC_EDGES = "deassert", 32 | parameter SYNC_DEPTH = 2 33 | ) 34 | ( 35 | // -------------------------------------- 36 | // We support up to 16 reset inputs, for now 37 | // -------------------------------------- 38 | input reset_in0, 39 | input reset_in1, 40 | input reset_in2, 41 | input reset_in3, 42 | input reset_in4, 43 | input reset_in5, 44 | input reset_in6, 45 | input reset_in7, 46 | input reset_in8, 47 | input reset_in9, 48 | input reset_in10, 49 | input reset_in11, 50 | input reset_in12, 51 | input reset_in13, 52 | input reset_in14, 53 | input reset_in15, 54 | 55 | input clk, 56 | output reset_out 57 | ); 58 | 59 | localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); 60 | 61 | wire merged_reset; 62 | 63 | // -------------------------------------- 64 | // "Or" all the input resets together 65 | // -------------------------------------- 66 | assign merged_reset = ( 67 | reset_in0 | 68 | reset_in1 | 69 | reset_in2 | 70 | reset_in3 | 71 | reset_in4 | 72 | reset_in5 | 73 | reset_in6 | 74 | reset_in7 | 75 | reset_in8 | 76 | reset_in9 | 77 | reset_in10 | 78 | reset_in11 | 79 | reset_in12 | 80 | reset_in13 | 81 | reset_in14 | 82 | reset_in15 83 | ); 84 | 85 | // -------------------------------------- 86 | // And if required, synchronize it to the required clock domain, 87 | // with the correct synchronization type 88 | // -------------------------------------- 89 | generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin 90 | 91 | assign reset_out = merged_reset; 92 | 93 | end else begin 94 | 95 | altera_reset_synchronizer 96 | #( 97 | .DEPTH (SYNC_DEPTH), 98 | .ASYNC_RESET(ASYNC_RESET) 99 | ) 100 | alt_rst_sync_uq1 101 | ( 102 | .clk (clk), 103 | .reset_in (merged_reset), 104 | .reset_out (reset_out) 105 | ); 106 | 107 | end 108 | endgenerate 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/sdram/testbench/sdram_tb/simulation/submodules/altera_reset_synchronizer.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2013 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/13.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2013/02/11 $ 17 | // $Author: swbranch $ 18 | 19 | // ----------------------------------------------- 20 | // Reset Synchronizer 21 | // ----------------------------------------------- 22 | `timescale 1 ns / 1 ns 23 | 24 | module altera_reset_synchronizer 25 | #( 26 | parameter ASYNC_RESET = 1, 27 | parameter DEPTH = 2 28 | ) 29 | ( 30 | input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, 31 | 32 | input clk, 33 | output reset_out 34 | ); 35 | 36 | // ----------------------------------------------- 37 | // Synchronizer register chain. We cannot reuse the 38 | // standard synchronizer in this implementation 39 | // because our timing constraints are different. 40 | // 41 | // Instead of cutting the timing path to the d-input 42 | // on the first flop we need to cut the aclr input. 43 | // 44 | // We omit the "preserve" attribute on the final 45 | // output register, so that the synthesis tool can 46 | // duplicate it where needed. 47 | // ----------------------------------------------- 48 | (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; 49 | reg altera_reset_synchronizer_int_chain_out; 50 | 51 | generate if (ASYNC_RESET) begin 52 | 53 | // ----------------------------------------------- 54 | // Assert asynchronously, deassert synchronously. 55 | // ----------------------------------------------- 56 | always @(posedge clk or posedge reset_in) begin 57 | if (reset_in) begin 58 | altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; 59 | altera_reset_synchronizer_int_chain_out <= 1'b1; 60 | end 61 | else begin 62 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 63 | altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; 64 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 65 | end 66 | end 67 | 68 | assign reset_out = altera_reset_synchronizer_int_chain_out; 69 | 70 | end else begin 71 | 72 | // ----------------------------------------------- 73 | // Assert synchronously, deassert synchronously. 74 | // ----------------------------------------------- 75 | always @(posedge clk) begin 76 | altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; 77 | altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; 78 | altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; 79 | end 80 | 81 | assign reset_out = altera_reset_synchronizer_int_chain_out; 82 | 83 | end 84 | endgenerate 85 | 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/signal_holder.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | `include "../define.v" 5 | 6 | module signal_holder # ( 7 | parameter DELAY_COUNT = 1000, 8 | parameter COUNTER_WIDTH = log2(DELAY_COUNT) 9 | ) 10 | ( 11 | input reset_in, 12 | input clk, 13 | output reg reset_out 14 | ); 15 | 16 | `LOG2 17 | 18 | reg [COUNTER_WIDTH-1 :0] counter; 19 | 20 | always@(posedge clk or posedge reset_in) 21 | begin 22 | if(reset_in)begin 23 | reset_out <= 1'b1; 24 | counter <={COUNTER_WIDTH{1'b0}}; 25 | end else begin 26 | if(counter == DELAY_COUNT) begin 27 | reset_out <= 1'b0; 28 | end else begin 29 | reset_out <= 1'b1; 30 | counter <= counter +1'b1; 31 | end 32 | end 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/IP_core/timer.v: -------------------------------------------------------------------------------- 1 | 2 | `include "../define.v" 3 | 4 | module timer #( 5 | parameter DATA_WIDTH = 32, 6 | parameter COUNTER_WIDTH = 32, 7 | parameter SEL_WIDTH = 4, 8 | parameter ADDR_WIDTH = 3 9 | 10 | 11 | 12 | )( 13 | input clk, 14 | input reset, 15 | // wishbone interface 16 | input [DATA_WIDTH-1 : 0] sa_dat_i, 17 | input [SEL_WIDTH-1 : 0] sa_sel_i, 18 | input [ADDR_WIDTH-1 : 0] sa_addr_i, 19 | input sa_stb_i, 20 | input sa_we_i, 21 | output [DATA_WIDTH-1 : 0] sa_dat_o, 22 | output reg sa_ack_o, 23 | //intruupt interface 24 | output irq 25 | ); 26 | 27 | `LOG2 28 | 29 | localparam TCSR_REG_ADDR = 0; //timer control register 30 | localparam TLR_REG_ADDR = 1; //timer load register 31 | localparam TCMP_REG_ADDR = 2;// timer compare value register 32 | 33 | localparam MAX_CLK_DEV = 256; 34 | localparam DEV_COUNT_WIDTH= log2(MAX_CLK_DEV); 35 | localparam DEV_CTRL_WIDTH = log2(DEV_COUNT_WIDTH); 36 | 37 | localparam TCSR_REG_WIDTH = 4+DEV_CTRL_WIDTH; 38 | localparam TCR_REG_WIDTH = TCSR_REG_WIDTH-1; 39 | /*************************** 40 | tcr: timer control register 41 | bit 42 | 43 | 6-3: clk_dev_ctrl 44 | 3 : timer_isr 45 | 2 : rst_on_cmp_value 46 | 1 : int_enble_on_cmp_value 47 | 0 : timer enable 48 | 49 | 50 | 51 | 52 | ***************************/ 53 | reg [TCSR_REG_WIDTH-1 : 0] tcsr; 54 | wire [TCSR_REG_WIDTH-1 : 0] tcsr_next; //timer control register 55 | reg [TCR_REG_WIDTH-1 : 0] tcr_next; 56 | reg timer_isr_next; 57 | 58 | reg [DEV_COUNT_WIDTH-1 : 0] clk_dev_counter,clk_dev_counter_next; 59 | 60 | wire [DEV_COUNT_WIDTH-1 : 0] dev_one_hot; 61 | wire [DEV_COUNT_WIDTH-2 : 0] dev_cmp_val; 62 | 63 | wire timer_en,int_en,rst_on_cmp,timer_isr; 64 | wire clk_dev_rst,counter_rst; 65 | wire [DEV_CTRL_WIDTH-1 : 0] clk_dev_ctrl; 66 | 67 | 68 | 69 | reg [COUNTER_WIDTH-1 : 0] counter,counter_next,cmp,cmp_next,read,read_next; 70 | 71 | 72 | 73 | assign {timer_isr,clk_dev_ctrl,rst_on_cmp,int_en,timer_en} = tcsr; 74 | assign dev_cmp_val = dev_one_hot[DEV_COUNT_WIDTH-1 : 1]; 75 | assign clk_dev_rst = clk_dev_counter == dev_cmp_val; 76 | assign counter_rst = (rst_on_cmp)? (counter == cmp) : 1'b0; 77 | assign sa_dat_o = read; 78 | assign irq = timer_isr; 79 | assign tcsr_next ={timer_isr_next,tcr_next}; 80 | bcd_to_one_hot #( 81 | .BCD_WIDTH (DEV_CTRL_WIDTH), 82 | .ONE_HOT_WIDTH (DEV_COUNT_WIDTH) 83 | ) 84 | conv 85 | ( 86 | .bcd_code (clk_dev_ctrl), 87 | .one_hot_code (dev_one_hot) 88 | ); 89 | 90 | always @(posedge clk or posedge reset) begin 91 | if(reset) begin 92 | counter <= {COUNTER_WIDTH{1'b0}}; 93 | cmp <= {COUNTER_WIDTH{1'b1}}; 94 | clk_dev_counter <= {DEV_COUNT_WIDTH{1'b0}}; 95 | tcsr <= {TCR_REG_WIDTH{1'b0}}; 96 | read <= {COUNTER_WIDTH{1'b0}}; 97 | sa_ack_o <= 1'b0; 98 | end else begin 99 | counter <= counter_next; 100 | cmp <= cmp_next; 101 | clk_dev_counter <= clk_dev_counter_next; 102 | tcsr <= tcsr_next; 103 | read <= read_next; 104 | sa_ack_o <= sa_stb_i && ~sa_ack_o; 105 | end 106 | end 107 | 108 | always@(*)begin 109 | counter_next = counter; 110 | clk_dev_counter_next = clk_dev_counter; 111 | timer_isr_next =(timer_isr | (counter_rst & clk_dev_rst) ) & int_en; 112 | tcr_next = tcsr[TCR_REG_WIDTH-1 : 0]; 113 | cmp_next = cmp; 114 | read_next = read; 115 | //counters 116 | if(timer_en)begin 117 | if(clk_dev_rst) begin 118 | clk_dev_counter_next = {DEV_COUNT_WIDTH{1'b0}}; 119 | if(counter_rst) begin 120 | counter_next = {COUNTER_WIDTH{1'b0}}; 121 | end else begin 122 | counter_next = counter +1'b1; 123 | end // count_rst 124 | end else begin 125 | clk_dev_counter_next = clk_dev_counter +1'b1; 126 | end //dev_rst 127 | end//time_en 128 | 129 | if(sa_stb_i )begin 130 | if(sa_we_i ) begin 131 | case(sa_addr_i) 132 | TCSR_REG_ADDR: begin 133 | tcr_next = sa_dat_i[TCR_REG_WIDTH-1 : 0]; 134 | timer_isr_next = timer_isr & ~sa_dat_i[TCSR_REG_WIDTH-1];// reset isr by writting 1 135 | end 136 | TLR_REG_ADDR: counter_next = sa_dat_i[COUNTER_WIDTH-1 : 0]; 137 | TCMP_REG_ADDR: cmp_next = sa_dat_i[COUNTER_WIDTH-1 : 0]; 138 | default: cmp_next = cmp; 139 | endcase 140 | end//we 141 | else begin 142 | case(sa_addr_i) 143 | TCSR_REG_ADDR: read_next = tcsr; 144 | TLR_REG_ADDR: read_next = counter; 145 | TCMP_REG_ADDR: read_next = cmp; 146 | default: read_next = read; 147 | endcase 148 | end 149 | end//stb 150 | end//always 151 | 152 | 153 | 154 | endmodule 155 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/NoC/Dimitrakopoulos_arbiter.v: -------------------------------------------------------------------------------- 1 | /* 2 | *************************************************** 3 | * Round-robin arbiter with variable priority vector 4 | * --------------------- 5 | * G. Dimitrakopoulos 6 | * Nov. 2008 7 | *************************************************** 8 | */ 9 | `timescale 1ns/1ps 10 | `include "../define.v" 11 | 12 | module arbiter #( 13 | parameter ARBITER_WIDTH =8, 14 | parameter CHOISE = 1 // 0 blind round-robin and 1 true round robin 15 | ) 16 | ( 17 | clk, 18 | reset, 19 | request, 20 | grant, 21 | anyGrant 22 | ); 23 | 24 | `LOG2 25 | localparam N = ARBITER_WIDTH; 26 | localparam S = log2(ARBITER_WIDTH); // ceil of log_2 of N - put manually 27 | 28 | 29 | // I/O interface 30 | input clk; 31 | input reset; 32 | input [N-1:0] request; 33 | output [N-1:0] grant; 34 | output anyGrant; 35 | 36 | // internal pointers 37 | reg [N-1:0] priority_reg; // one-hot priority vector 38 | 39 | 40 | // Outputs of combinational logic - real wires - declared as regs for use in a alway block 41 | // Better to change to wires and use generate statements in the future 42 | 43 | reg [N-1:0] g[S:0]; // S levels of priority generate 44 | reg [N-1:0] p[S-1:0]; // S-1 levels of priority propagate 45 | 46 | // internal synonym wires of true outputs anyGrant and grant 47 | wire anyGnt; 48 | wire [N-1:0] gnt; 49 | 50 | assign anyGrant = anyGnt; 51 | assign grant = gnt; 52 | 53 | 54 | 55 | 56 | ///////////////////////////////////////////////// 57 | // Parallel prefix arbitration phase 58 | ///////////////////////////////////////////////// 59 | integer i,j; 60 | 61 | // arbitration phase 62 | always@(request or priority_reg) 63 | begin 64 | // transfer request vector to the fireset propagate positions 65 | p[0] = {~request[N-2:0], ~request[N-1]}; 66 | 67 | // transfer priority vector to the fireset generate positions 68 | g[0] = priority_reg; 69 | 70 | // fireset log_2n - 1 prefix levels 71 | for (i=1; i < S; i = i + 1) begin 72 | for (j = 0; j < N ; j = j + 1) begin 73 | if (j-2**(i-1) < 0) begin 74 | g[i][j] = g[i-1][j] | (p[i-1][j] & g[i-1][N+j-2**(i-1)]); 75 | p[i][j] = p[i-1][j] & p[i-1][N+j-2**(i-1)]; 76 | end else begin 77 | g[i][j] = g[i-1][j] | (p[i-1][j] & g[i-1][j-2**(i-1)]); 78 | p[i][j] = p[i-1][j] & p[i-1][j-2**(i-1)]; 79 | end 80 | end 81 | end 82 | 83 | // last prefix level 84 | for (j = 0; j < N; j = j + 1) begin 85 | if (j-2**(S-1) < 0) 86 | g[S][j] = g[S-1][j] | (p[S-1][j] & g[S-1][N+j-2**(S-1)]); 87 | else 88 | g[S][j] = g[S-1][j] | (p[S-1][j] & g[S-1][j-2**(S-1)]); 89 | end 90 | end 91 | 92 | // any grant generation at last prefix level 93 | assign anyGnt = ~(p[S-1][N-1] & p[S-1][N/2-1]); 94 | 95 | // output stage logic 96 | assign gnt = request & g[S]; 97 | 98 | 99 | ///////////////////////////////////////////////// 100 | // Pointer update logic 101 | // ------------------------ 102 | // Version 1 - blind round robin CHOISE = 0 103 | // Priority visits each input in a circural manner irrespective the granted output 104 | // ------------------------ 105 | // Version 2 - true round robin CHOISE = 1 106 | // Priority moves next to the granted output 107 | // ------------------------ 108 | // Priority moves only when a grant was given, i.e., at least one active request 109 | ////////////////////////////////////////////////// 110 | 111 | always@(posedge clk or posedge reset) 112 | begin 113 | if (reset == 1'b1) begin 114 | priority_reg <= 1; 115 | end else begin 116 | // update pointers only if at leas one match exists 117 | if (anyGnt == 1'b1) begin 118 | if (CHOISE == 0) begin // blind circular round robin 119 | // shift left one-hot priority vector 120 | priority_reg[N-1:1] <= priority_reg[N-2:0]; 121 | priority_reg[0] <= priority_reg[N-1]; 122 | end else begin // true round robin 123 | // shift left one-hot grant vector 124 | priority_reg[N-1:1] <= grant[N-2:0]; 125 | priority_reg[0] <= grant[N-1]; 126 | end 127 | end 128 | end 129 | end 130 | 131 | 132 | endmodule 133 | 134 | 135 | /************************ 136 | 137 | fixed priority one hot arbiter 138 | 139 | 140 | **************************/ 141 | 142 | module fixed_arbiter#( 143 | parameter ARBITER_WIDTH=8 144 | 145 | ) 146 | ( 147 | input [ARBITER_WIDTH-1 : 0]request, 148 | output[ARBITER_WIDTH-1 : 0]grant 149 | ); 150 | 151 | assign grant[0]=request[0]; 152 | genvar i; 153 | generate 154 | for(i=1;i. 18 | 19 | 20 | Purpose: 21 | An small First Word Fall Through FIFO. The code will use LUTs 22 | and optimized for low LUTs utilization. 23 | 24 | Info: monemi@fkegraduate.utm.my 25 | 26 | 27 | *******************************************************************/ 28 | 29 | `include "../define.v" 30 | `timescale 1ns/1ps 31 | module fwft_fifo #( 32 | parameter WIDTH = 1, 33 | parameter MAX_DEPTH_BITS = 2 34 | ) 35 | ( 36 | input [WIDTH-1:0] din, // Data in 37 | input wr_en, // Write enable 38 | input rd_en, // Read the next word 39 | output reg [WIDTH-1:0] dout, // Data out 40 | output full, 41 | output nearly_full, 42 | output recieve_more_than_0, 43 | output recieve_more_than_1, 44 | input reset, 45 | input clk 46 | 47 | ); 48 | 49 | 50 | 51 | `LOG2 52 | 53 | localparam DEPTH_WIDTH = log2(MAX_DEPTH_BITS +1); 54 | 55 | wire [MAX_DEPTH_BITS-2 : 0] mux_in [WIDTH-1 :0]; 56 | wire [DEPTH_WIDTH-1 : 0] mux_sel; 57 | wire [WIDTH-1 : 0] mux_out; 58 | 59 | wire empty; 60 | reg [MAX_DEPTH_BITS-2 : 0] shiftreg [WIDTH-1 :0]; 61 | reg [DEPTH_WIDTH-1 : 0] depth; 62 | 63 | wire out_sel ; 64 | wire out_ld ; 65 | wire [WIDTH-1 : 0] dout_next; 66 | 67 | 68 | genvar i; 69 | generate 70 | for(i=0;i2) begin 72 | always @(posedge clk ) begin 73 | //if (reset) begin 74 | // shiftreg[i] <= {MAX_DEPTH_BITS{1'b0}}; 75 | //end else begin 76 | if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH_BITS-3 : 0] ,din[i]}; 77 | //end 78 | end 79 | end else begin 80 | always @(posedge clk ) begin 81 | //if (reset) begin 82 | // shiftreg[i] <= {MAX_DEPTH_BITS{1'b0}}; 83 | //end else begin 84 | if(wr_en) shiftreg[i] <= din[i]; 85 | //end 86 | end //always 87 | end //else 88 | assign mux_in[i] = shiftreg[i]; 89 | assign mux_out[i] = mux_in[i][mux_sel]; 90 | assign dout_next[i] = (out_sel) ? mux_out[i] : din[i]; 91 | end //for 92 | endgenerate 93 | 94 | 95 | always @(posedge clk) begin 96 | if (reset) begin 97 | depth <= {DEPTH_WIDTH{1'b0}}; 98 | end else begin 99 | if (wr_en & ~rd_en) depth <= 100 | // synthesis translate_off 101 | #1 102 | // synthesis translate_on 103 | depth + 1'h1; 104 | else if (~wr_en & rd_en) depth <= 105 | // synthesis translate_off 106 | #1 107 | // synthesis translate_on 108 | depth - 1'h1; 109 | 110 | end 111 | end//always 112 | 113 | 114 | always @(posedge clk or posedge reset) begin 115 | if (reset) begin 116 | dout <= {WIDTH{1'b0}}; 117 | end else begin 118 | if (out_ld) dout <= dout_next; 119 | end 120 | end//always 121 | 122 | 123 | assign full = depth == MAX_DEPTH_BITS; 124 | assign nearly_full = depth >= MAX_DEPTH_BITS-1; 125 | assign empty = depth == 'h0; 126 | assign recieve_more_than_0 = ~ empty; 127 | assign recieve_more_than_1 = ~( depth == 0 || depth== 1 ); 128 | assign out_sel = (recieve_more_than_1) ? 1'b1 : 1'b0; 129 | assign out_ld = (depth !=0 )? rd_en : wr_en; 130 | assign mux_sel = depth-2'd2; 131 | 132 | // synthesis translate_off 133 | always @(posedge clk) 134 | begin 135 | if (wr_en && full) begin 136 | $display("%t ERROR: Attempt to write to full FIFO: %m", $time); 137 | end 138 | if (rd_en && !recieve_more_than_0) begin 139 | $display("%t ERROR: Attempt to read an empty FIFO: %m", $time); 140 | end 141 | end // always @ (posedge clk) 142 | // synthesis translate_on 143 | 144 | 145 | 146 | 147 | 148 | 149 | endmodule 150 | 151 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/NoC/mask.v: -------------------------------------------------------------------------------- 1 | /********************************************************************** 2 | File: mask.v 3 | 4 | Copyright (C) 2013 Alireza Monemi 5 | 6 | This program is free software: you can redistribute it and/or modify 7 | it under the terms of the GNU General Public License as published by 8 | the Free Software Foundation, either version 3 of the License, or 9 | (at your option) any later version. 10 | 11 | This program is distributed in the hope that it will be useful, 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | GNU General Public License for more details. 15 | 16 | You should have received a copy of the GNU General Public License 17 | along with this program. If not, see . 18 | 19 | 20 | Purpose: 21 | masking the input port requests in following conditions: 22 | 1- the request is from the IVC which has been assigned to an 23 | OVC but there is no empty place on the assigned OVC 24 | 2- the request is from the IVC which has not yet been assigned 25 | any OVC and the destination port has no empty VC 26 | 27 | Info: monemi@fkegraduate.utm.my 28 | 29 | ********************************************************************/ 30 | 31 | 32 | `include "../define.v" 33 | module ivc_request_mask #( 34 | parameter PORT_NUM = 5, 35 | parameter PORT_SEL_WIDTH = PORT_NUM-1,//assum that no port whants to send a packet to itself! 36 | parameter PORT_SEL_BCD_WIDTH = log2(PORT_SEL_WIDTH) 37 | ) 38 | ( 39 | input [PORT_SEL_WIDTH-1 :0] ovc_available, 40 | input [PORT_SEL_BCD_WIDTH-1 :0] port_sel_bcd, 41 | input ovc_not_assigned, 42 | input tail_flit, 43 | input ivc_not_empty, 44 | //input ivc_recieved_more_than_one_flit, 45 | input [1 :0] ovc_status, 46 | input ivc_granted, 47 | output ivc_request, 48 | input clk, 49 | input reset 50 | ); 51 | 52 | `LOG2 53 | 54 | wire [PORT_SEL_WIDTH-1 : 0] port_sel_available; 55 | wire not_assigned_req_allowed; 56 | wire assigned_reg_allowed; 57 | wire not_assigned_request; 58 | wire assigned_request; 59 | wire not_assigned_request_exsist; 60 | wire assigned_request_exsist; 61 | wire request1; 62 | wire request2; 63 | wire request; 64 | reg full; 65 | reg nearlly_full; 66 | reg has_two_empty_place; 67 | reg sent_one_or_two_request; 68 | reg sent_two_requests; 69 | wire assigned_not_allowed1; 70 | wire assigned_not_allowed2; 71 | wire assigned_not_allowed3; 72 | reg ivc_granted_reg; 73 | reg has_less_than_2; 74 | 75 | //assign port_sel_available = port_sel & ovc_available; 76 | //assign not_assigned_req_allowed = | port_sel_available; 77 | assign not_assigned_req_allowed = ovc_available[port_sel_bcd]; 78 | assign not_assigned_request_exsist = request & ovc_not_assigned; 79 | assign not_assigned_request = not_assigned_request_exsist & not_assigned_req_allowed; 80 | assign assigned_request_exsist = request & ~ovc_not_assigned; 81 | assign assigned_request = assigned_request_exsist & assigned_reg_allowed; 82 | assign ivc_request = assigned_request | not_assigned_request; 83 | assign request = ivc_not_empty ; 84 | assign assigned_not_allowed1 = full; 85 | assign assigned_not_allowed2 = nearlly_full & ivc_granted_reg; 86 | assign assigned_reg_allowed = ~(assigned_not_allowed1 | assigned_not_allowed2 ); 87 | 88 | always @(posedge clk or posedge reset)begin 89 | if(reset) begin 90 | full <= 1'b0; 91 | nearlly_full <= 1'b0; 92 | ivc_granted_reg <= 1'b0; 93 | end else begin 94 | full <= ovc_status[1]; 95 | nearlly_full <= ovc_status[0]; 96 | ivc_granted_reg <= ivc_granted; 97 | end 98 | end//always 99 | endmodule 100 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/NoC/min_number.v: -------------------------------------------------------------------------------- 1 | `include "../define.v" 2 | 3 | module minimum_number#( 4 | parameter NUM_OF_INPUTS = 8, 5 | parameter DATA_WIDTH = 5, 6 | parameter IN_ARRAY_WIDTH = NUM_OF_INPUTS * DATA_WIDTH 7 | ) 8 | ( 9 | input [IN_ARRAY_WIDTH-1 : 0] in_array, 10 | output [NUM_OF_INPUTS-1 : 0] min_out 11 | ); 12 | 13 | `LOG2 14 | localparam COMP_PARAL_NUM = log2(NUM_OF_INPUTS); 15 | 16 | wire [DATA_WIDTH-1 : 0] numbers [NUM_OF_INPUTS-1 :0]; 17 | wire [DATA_WIDTH-1 : 0] first_in_array [NUM_OF_INPUTS-2 :0]; 18 | wire [DATA_WIDTH-1 : 0] second_in_array [NUM_OF_INPUTS-2 :0]; 19 | wire [DATA_WIDTH-1 : 0] min_out_array [NUM_OF_INPUTS-2 :0]; 20 | wire [NUM_OF_INPUTS-2 : 0] comp; 21 | wire [NUM_OF_INPUTS-2 : 0] comp_not; 22 | wire [(NUM_OF_INPUTS-1)*2-1 : 0] comp_all; 23 | wire [NUM_OF_INPUTS-1 : 0] min_out_gen [COMP_PARAL_NUM-1 :0]; 24 | wire [COMP_PARAL_NUM-1 : 0] min_out_t [NUM_OF_INPUTS-1 :0]; 25 | 26 | genvar i,j; 27 | generate 28 | if(NUM_OF_INPUTS==1)begin 29 | assign min_out = 1'b1; 30 | end 31 | else begin //(vc num >1) 32 | 33 | 34 | for(i=0;i<(NUM_OF_INPUTS/2);i=i+1) begin :min_detect_loop1 35 | assign first_in_array [i] = numbers [i*2]; 36 | assign second_in_array [i] = numbers [(i*2)+1]; 37 | end //for 38 | for(i=0;i<((NUM_OF_INPUTS/2)-1);i=i+1) begin :min_detect_loop2 39 | assign first_in_array [i+(NUM_OF_INPUTS/2)] = min_out_array [i*2]; 40 | assign second_in_array [i+(NUM_OF_INPUTS/2)] = min_out_array [(i*2)+1]; 41 | end //for 42 | for(i=0;i<(NUM_OF_INPUTS-1);i=i+1) begin :min_detect_loop3 43 | 44 | two_in_min_detect#( 45 | .DATA_WIDTH(DATA_WIDTH) 46 | ) 47 | min_detect 48 | ( 49 | .first_in (first_in_array[i]), 50 | .second_in (second_in_array[i]), 51 | .comp (comp[i]), 52 | .min_out (min_out_array[i]) 53 | ); 54 | 55 | end //for 56 | 57 | 58 | assign comp_not = ~ comp; 59 | for(i=0;i<(NUM_OF_INPUTS-1);i=i+1) begin :comp_loop 60 | assign comp_all[i*2+1 : i*2] = {comp[i] ,comp_not[i]}; 61 | end//for 62 | 63 | for (j=0; j< COMP_PARAL_NUM ; j=j+1)begin: min_out_loop1 64 | for(i=0; i1) 81 | endgenerate 82 | 83 | endmodule 84 | 85 | 86 | 87 | //detecting the minumom of two input 88 | module two_in_min_detect#( 89 | parameter DATA_WIDTH = 4 90 | ) 91 | ( 92 | input [DATA_WIDTH-1 :0] first_in, 93 | input [DATA_WIDTH-1 :0] second_in, 94 | output comp, 95 | output [DATA_WIDTH-1 :0] min_out 96 | ); 97 | 98 | assign comp = (first_in <= second_in); 99 | assign min_out = (comp)? first_in : second_in; 100 | 101 | endmodule 102 | 103 | 104 | /********************************** 105 | 106 | 107 | compar all numbers in prallel. needs more hardware cost 108 | but it is faster when the total numbers is big 109 | 110 | ***********************************/ 111 | 112 | 113 | module fast_minimum_number#( 114 | parameter NUM_OF_INPUTS = 8, 115 | parameter DATA_WIDTH = 5, 116 | parameter IN_ARRAY_WIDTH = NUM_OF_INPUTS * DATA_WIDTH 117 | ) 118 | ( 119 | input [IN_ARRAY_WIDTH-1 : 0] in_array, 120 | output [NUM_OF_INPUTS-1 : 0] min_out 121 | ); 122 | 123 | genvar i,j; 124 | wire [DATA_WIDTH-1 : 0] numbers [NUM_OF_INPUTS-1 :0]; 125 | wire [NUM_OF_INPUTS-2 : 0] comp_array [NUM_OF_INPUTS-1 :0]; 126 | 127 | generate 128 | if(NUM_OF_INPUTS==1)begin 129 | assign min_out = 1'b1; 130 | end 131 | else begin //(vc num >1) 132 | for(i=0; ij) assign comp_array [i][j] = ~ comp_array [j][i-1]; 136 | else assign comp_array [i] [j] = numbers[i]<= numbers[j+1]; 137 | end//for j 138 | assign min_out[i]= & comp_array[i]; 139 | end//for i 140 | end//else 141 | endgenerate 142 | 143 | endmodule 144 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/NoC/sw_alloc_first_arbiter.v: -------------------------------------------------------------------------------- 1 | /********************************************************************** 2 | File: sw_alloc_first_arbiter.v 3 | 4 | Copyright (C) 2013 Alireza Monemi 5 | 6 | This program is free software: you can redistribute it and/or modify 7 | it under the terms of the GNU General Public License as published by 8 | the Free Software Foundation, either version 3 of the License, or 9 | (at your option) any later version. 10 | 11 | This program is distributed in the hope that it will be useful, 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | GNU General Public License for more details. 15 | 16 | You should have received a copy of the GNU General Public License 17 | along with this program. If not, see . 18 | 19 | 20 | Purpose: 21 | The first arbitartion stage in switch allocator 22 | 23 | Info: monemi@fkegraduate.utm.my 24 | 25 | ********************************************************************/ 26 | 27 | 28 | 29 | `include "../define.v" 30 | module sw_alloc_first_arbiter#( 31 | parameter VC_NUM_PER_PORT = 4, 32 | parameter PORT_NUM = 5, 33 | parameter PORT_SEL_WIDTH = PORT_NUM-1,//assumed that no port request for itself! 34 | parameter PORT_SEL_BCD_WIDTH = log2(PORT_SEL_WIDTH), 35 | parameter TOTAL_VC_NUM = VC_NUM_PER_PORT*PORT_NUM, 36 | parameter PORT_SEL_ARRAY_WIDTH = VC_NUM_PER_PORT * PORT_SEL_BCD_WIDTH, 37 | parameter PORT_CAND_ARRAY_WIDTH = PORT_SEL_WIDTH* PORT_NUM, 38 | parameter ALL_VC_NUM = VC_NUM_PER_PORT* PORT_NUM 39 | 40 | 41 | ) 42 | 43 | ( 44 | 45 | input [PORT_SEL_ARRAY_WIDTH-1 : 0] port_selects, 46 | input [VC_NUM_PER_PORT-1 : 0] in_vc_requests, 47 | input [PORT_SEL_WIDTH-1 : 0] port_granted, 48 | 49 | output[VC_NUM_PER_PORT-1 : 0] candidate_in_vc, 50 | output[PORT_SEL_WIDTH-1 : 0] candidate_port, 51 | output[VC_NUM_PER_PORT-1 : 0] in_vc_granted, 52 | output any_vc_granted, 53 | 54 | input clk, 55 | input reset 56 | 57 | ); 58 | `LOG2 59 | localparam PORT_SEL_HOT_ARRAY_WIDTH = VC_NUM_PER_PORT * PORT_SEL_WIDTH; 60 | 61 | 62 | wire [PORT_SEL_HOT_ARRAY_WIDTH-1 :0] port_sel_hot_array; 63 | 64 | genvar i; 65 | generate 66 | for(i=0;i. 18 | 19 | 20 | Purpose: 21 | The second arbitartion stage in switch allocator 22 | 23 | Info: monemi@fkegraduate.utm.my 24 | 25 | ************************************************************************/ 26 | 27 | module sw_alloc_second_arbiter #( 28 | parameter VC_NUM_PER_PORT = 4, 29 | parameter PORT_NUM = 5, 30 | parameter ARBITER_WIDTH = PORT_NUM-1,//assumed that no port request for itself! 31 | parameter PORT_REQ_WIDTH = PORT_NUM* ARBITER_WIDTH 32 | ) 33 | 34 | ( 35 | 36 | input [PORT_REQ_WIDTH-1 : 0] port_requests, 37 | output[PORT_REQ_WIDTH-1 : 0] port_granted, 38 | output[PORT_NUM-1 : 0] any_grants, 39 | input clk, 40 | input reset 41 | 42 | ); 43 | 44 | wire [ARBITER_WIDTH -1 : 0] request [PORT_NUM-1 : 0] ; 45 | wire [ARBITER_WIDTH -1 : 0] grant [PORT_NUM-1 : 0] ; 46 | 47 | 48 | 49 | genvar i,j; 50 | generate 51 | for(i=0;ij)begin: hh 70 | assign request[i][j] = port_requests[(j*ARBITER_WIDTH )+i-1] ; 71 | assign port_granted[(j*ARBITER_WIDTH)+i-1] = grant [i][j] ; 72 | end 73 | //if(i==j) wires are left disconnected 74 | 75 | end 76 | 77 | 78 | end//for 79 | endgenerate 80 | 81 | 82 | 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/NoC/sw_out.v: -------------------------------------------------------------------------------- 1 | /********************************************************************** 2 | File: switch_out.v 3 | 4 | Copyright (C) 2013 Alireza Monemi 5 | 6 | This program is free software: you can redistribute it and/or modify 7 | it under the terms of the GNU General Public License as published by 8 | the Free Software Foundation, either version 3 of the License, or 9 | (at your option) any later version. 10 | 11 | This program is distributed in the hope that it will be useful, 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | GNU General Public License for more details. 15 | 16 | You should have received a copy of the GNU General Public License 17 | along with this program. If not, see . 18 | 19 | 20 | Purpose: 21 | The output switch. Just connects crossbar to the router output port. 22 | using wire or pipeline registers. note the the credit counter and OVC 23 | status are moved to OVC status module. 24 | 25 | Info: monemi@fkegraduate.utm.my 26 | ************************************************************************/ 27 | 28 | module sw_out#( 29 | parameter VC_NUM_PER_PORT = 4, 30 | parameter PORT_NUM = 5, 31 | parameter PYLD_WIDTH = 32, 32 | parameter FLIT_TYPE_WIDTH = 2, 33 | parameter SW_OUTPUT_REGISTERED = 0, // 1: registered , 0 not registered 34 | parameter PORT_SEL_WIDTH = PORT_NUM-1,//assum that no port whants to send a packet to itself! 35 | parameter VC_ID_WIDTH = VC_NUM_PER_PORT, 36 | parameter FLIT_WIDTH = PYLD_WIDTH+ FLIT_TYPE_WIDTH+VC_ID_WIDTH 37 | ) 38 | ( 39 | input in_wr_en, 40 | input [FLIT_WIDTH-1 :0] flit_in, 41 | 42 | output reg out_wr_en, 43 | output reg [FLIT_WIDTH-1 :0] flit_out, 44 | 45 | input clk, 46 | input reset 47 | ); 48 | 49 | generate 50 | if (SW_OUTPUT_REGISTERED) begin 51 | always @(posedge clk or posedge reset)begin 52 | if(reset)begin 53 | out_wr_en <=1'b0; 54 | flit_out <={FLIT_WIDTH{1'b0}}; 55 | end else begin 56 | out_wr_en <= in_wr_en; 57 | flit_out <= flit_in; 58 | 59 | end 60 | end//always 61 | end else begin 62 | 63 | always @(*)begin 64 | out_wr_en = in_wr_en; 65 | flit_out = flit_in; 66 | end//always 67 | 68 | end 69 | endgenerate 70 | endmodule 71 | 72 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/NoC/sw_sep_alloc.v: -------------------------------------------------------------------------------- 1 | /********************************************************************** 2 | File:sw_sep_alloc.v 3 | 4 | Copyright (C) 2013 Alireza Monemi 5 | 6 | This program is free software: you can redistribute it and/or modify 7 | it under the terms of the GNU General Public License as published by 8 | the Free Software Foundation, either version 3 of the License, or 9 | (at your option) any later version. 10 | 11 | This program is distributed in the hope that it will be useful, 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | GNU General Public License for more details. 15 | 16 | You should have received a copy of the GNU General Public License 17 | along with this program. If not, see . 18 | 19 | 20 | Purpose: 21 | The switch first in rateable allocator 22 | 23 | Info: monemi@fkegraduate.utm.my 24 | 25 | ********************************************************/ 26 | 27 | 28 | `include "../define.v" 29 | module sw_sep_alloc #( 30 | parameter VC_NUM_PER_PORT = 4, 31 | parameter PORT_NUM = 5, 32 | parameter PORT_SEL_WIDTH = PORT_NUM-1,//assumed that no port request for itself! 33 | parameter PORT_SEL_BCD_WIDTH = log2(PORT_SEL_WIDTH), 34 | parameter TOTAL_VC_NUM = VC_NUM_PER_PORT*PORT_NUM, 35 | parameter PORT_SEL_ARRAY_WIDTH = TOTAL_VC_NUM * PORT_SEL_BCD_WIDTH, 36 | parameter PORT_CAND_ARRAY_WIDTH = PORT_SEL_WIDTH* PORT_NUM, 37 | parameter ALL_VC_NUM = VC_NUM_PER_PORT* PORT_NUM 38 | ) 39 | 40 | ( 41 | input [PORT_SEL_ARRAY_WIDTH-1 : 0] port_selects_array, 42 | input [ALL_VC_NUM-1 : 0] in_vc_requests_array, 43 | output [ALL_VC_NUM-1 : 0] candidate_in_vc_array, 44 | output [PORT_CAND_ARRAY_WIDTH-1 : 0] candidate_port_array, 45 | output [ALL_VC_NUM-1 : 0] in_vc_granted_array, 46 | output [PORT_NUM-1 : 0] any_vc_granted_array, 47 | output reg [PORT_CAND_ARRAY_WIDTH-1 : 0] crossbar_granted_port_array, 48 | output [PORT_CAND_ARRAY_WIDTH-1 : 0] isw_granted_port_array, 49 | output reg [PORT_NUM-1 : 0] out_port_wr_en_array, 50 | input clk, 51 | input reset 52 | 53 | ); 54 | `LOG2 55 | localparam FIRST_ARBITER_PORT_SEL_WIDTH = VC_NUM_PER_PORT * PORT_SEL_BCD_WIDTH; 56 | 57 | 58 | wire [PORT_NUM-1 : 0] any_grants; 59 | wire [PORT_CAND_ARRAY_WIDTH-1 : 0] candidate_port_wire; 60 | 61 | 62 | 63 | assign candidate_port_array = candidate_port_wire; 64 | 65 | genvar i,j; 66 | generate 67 | 68 | 69 | for(i=0;i< PORT_NUM;i=i+1) begin :first_arbitter_loop 70 | //first arbiters 71 | 72 | 73 | sw_alloc_first_arbiter#( 74 | .VC_NUM_PER_PORT (VC_NUM_PER_PORT), 75 | .PORT_NUM (PORT_NUM) 76 | 77 | ) 78 | the_sw_alloc_first_arbiter 79 | ( 80 | .port_selects (port_selects_array [(i+1)*FIRST_ARBITER_PORT_SEL_WIDTH-1 :i*FIRST_ARBITER_PORT_SEL_WIDTH]), 81 | .in_vc_requests (in_vc_requests_array [(i+1)*VC_NUM_PER_PORT-1 :i*VC_NUM_PER_PORT ]), 82 | .port_granted (isw_granted_port_array [(i+1)*PORT_SEL_WIDTH-1 :i*PORT_SEL_WIDTH ]), 83 | .candidate_in_vc (candidate_in_vc_array [(i+1)*VC_NUM_PER_PORT-1 :i*VC_NUM_PER_PORT ]), 84 | .candidate_port (candidate_port_wire [(i+1)*PORT_SEL_WIDTH-1 :i*PORT_SEL_WIDTH ]), 85 | .in_vc_granted (in_vc_granted_array [(i+1)*VC_NUM_PER_PORT-1 :i*VC_NUM_PER_PORT ]), 86 | .any_vc_granted (any_vc_granted_array [i]), 87 | .clk (clk), 88 | .reset (reset) 89 | ); 90 | 91 | 92 | 93 | 94 | end//for 95 | endgenerate 96 | 97 | 98 | //second arbiters 99 | sw_alloc_second_arbiter #( 100 | .VC_NUM_PER_PORT (VC_NUM_PER_PORT), 101 | .PORT_NUM (PORT_NUM) 102 | ) 103 | the_sw_alloc_second_arbiter 104 | ( 105 | 106 | .port_requests (candidate_port_wire), 107 | .port_granted (isw_granted_port_array), 108 | .any_grants (any_grants), 109 | .clk (clk), 110 | .reset (reset) 111 | 112 | ); 113 | 114 | always @(posedge clk or posedge reset)begin 115 | if (reset) begin 116 | crossbar_granted_port_array <= {PORT_CAND_ARRAY_WIDTH{1'b0}}; 117 | out_port_wr_en_array <= {PORT_NUM{1'b0}}; 118 | end else begin 119 | crossbar_granted_port_array <= isw_granted_port_array; 120 | out_port_wr_en_array <= any_grants; 121 | 122 | end 123 | end//always 124 | 125 | endmodule 126 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/SoC_IP_top.v: -------------------------------------------------------------------------------- 1 | /********************************************************************* 2 | 3 | File: SoC_IP_top.v 4 | 5 | Copyright (C) 2014 Alireza Monemi 6 | 7 | This program is free software: you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation, either version 3 of the License, or 10 | (at your option) any later version. 11 | 12 | This program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License 18 | along with this program. If not, see . 19 | 20 | 21 | Purpose: 22 | The top module for SoC with one aeMB processor, wishbone bus, gpio 23 | and timer 24 | 25 | 26 | Info: monemi@fkegraduate.utm.my 27 | 28 | ****************************************************************/ 29 | 30 | 31 | module SoC_IP_top ( 32 | input CLOCK_50, 33 | input [3 : 0] KEY, 34 | output [3 : 0] LEDG, 35 | output [6 : 0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 36 | 37 | 38 | ); 39 | 40 | 41 | 42 | parameter SEVEN_SEG_NUM = 8; 43 | 44 | parameter AEMB_RAM_WIDTH_IN_WORD = `AEMB_RAM_WIDTH_IN_WORD_DEF; 45 | parameter RAM_EN = 1; 46 | parameter GPIO_EN = 1; 47 | parameter EXT_INT_EN = 1; 48 | parameter TIMER_EN = 1; 49 | parameter INT_CTRL_EN = 1; 50 | 51 | 52 | //gpio parameters 53 | parameter IO_EN = 0; 54 | parameter I_EN = 0; 55 | parameter O_EN = 1; 56 | 57 | parameter IO_PORT_WIDTH = "0"; 58 | parameter I_PORT_WIDTH = "0"; 59 | parameter O_PORT_WIDTH = "7,7,7,7,7,7,7,7"; 60 | 61 | 62 | //external int parameters 63 | parameter EXT_INT_NUM = 3;//max 32 64 | 65 | 66 | 67 | wire [(SEVEN_SEG_NUM *7)-1 :0] seven_segment; 68 | wire [2 :0] ext_int_i; 69 | wire reset,reset_in,sys_en,sys_en_n; 70 | wire clk; 71 | 72 | 73 | assign sys_en = ~ sys_en_n; 74 | assign clk = CLOCK_50; 75 | assign LEDG[0] = reset; 76 | assign LEDG[3:1]= ext_int_i; 77 | assign {HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0} = seven_segment; 78 | assign reset_in = ~KEY[0]; 79 | assign ext_int_i = ~KEY[3:1]; 80 | 81 | 82 | signal_holder #( 83 | .DELAY_COUNT(1000) 84 | ) 85 | hold_reset 86 | ( 87 | .reset_in (reset_in), 88 | .clk (clk), 89 | .reset_out (reset) 90 | ); 91 | 92 | signal_holder #( 93 | .DELAY_COUNT(100) 94 | ) 95 | hold_en 96 | ( 97 | .reset_in (reset), 98 | .clk (clk), 99 | .reset_out (sys_en_n) 100 | ); 101 | 102 | 103 | aeMB_IP #( 104 | .AEMB_RAM_WIDTH_IN_WORD (AEMB_RAM_WIDTH_IN_WORD ), 105 | .RAM_EN (RAM_EN), 106 | .NOC_EN (0), 107 | .GPIO_EN (GPIO_EN), 108 | .EXT_INT_EN (EXT_INT_EN), 109 | .TIMER_EN (TIMER_EN), 110 | .INT_CTRL_EN (INT_CTRL_EN), 111 | .IO_EN (IO_EN), 112 | .I_EN (I_EN), 113 | .O_EN (O_EN), 114 | .IO_PORT_WIDTH (IO_PORT_WIDTH), 115 | .I_PORT_WIDTH (I_PORT_WIDTH), 116 | .O_PORT_WIDTH (O_PORT_WIDTH), 117 | .EXT_INT_NUM (EXT_INT_NUM), 118 | .SW_X_ADDR(0), 119 | .SW_Y_ADDR(0) 120 | )IP 121 | ( 122 | .clk (clk), 123 | .reset_in(reset), 124 | .sys_ena_i(sys_en), 125 | .ext_int_i(ext_int_i), 126 | .gpio_io(), 127 | .gpio_i(), 128 | .gpio_o(seven_segment) 129 | ); 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | endmodule 140 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/aemb/aeMB2_brcc.v: -------------------------------------------------------------------------------- 1 | /* $Id: aeMB2_brcc.v,v 1.3 2008-04-26 01:09:05 sybreon Exp $ 2 | ** 3 | ** AEMB2 EDK 6.2 COMPATIBLE CORE 4 | ** Copyright (C) 2004-2008 Shawn Tan 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | /** 22 | * Branch Condition Checker 23 | * @file aeMB2_brcc.v 24 | 25 | * This controls the decision to branch/delay. The actualy branch 26 | target is calculated in the ALU. 27 | 28 | */ 29 | `timescale 1ns/1ps 30 | module aeMB2_brcc (/*AUTOARG*/ 31 | // Outputs 32 | bra_ex, 33 | // Inputs 34 | opd_of, ra_of, rd_of, opc_of, gclk, grst, dena, iena, gpha 35 | ); 36 | parameter AEMB_HTX = 1; 37 | 38 | input [31:0] opd_of; 39 | input [4:0] ra_of; 40 | input [4:0] rd_of; 41 | input [5:0] opc_of; 42 | 43 | output [1:0] bra_ex; 44 | 45 | // SYS signals 46 | input gclk, 47 | grst, 48 | dena, 49 | iena, 50 | gpha; 51 | 52 | /*AUTOREG*/ 53 | // Beginning of automatic regs (for this module's undeclared outputs) 54 | reg [1:0] bra_ex; 55 | // End of automatics 56 | 57 | // TODO: replace comparators with logic 58 | 59 | /* Branch Control */ 60 | wire wRTD = (opc_of == 6'o55); 61 | wire wBCC = (opc_of == 6'o47) | (opc_of == 6'o57); 62 | wire wBRU = (opc_of == 6'o46) | (opc_of == 6'o56); 63 | 64 | wire wBEQ = (opd_of == 32'd0); 65 | wire wBLT = opd_of[31]; 66 | wire wBLE = wBLT | wBEQ; 67 | wire wBNE = ~wBEQ; 68 | wire wBGE = ~wBLT; 69 | wire wBGT = ~wBLE; 70 | 71 | reg xcc; 72 | 73 | always @(/*AUTOSENSE*/rd_of or wBEQ or wBGE or wBGT or wBLE or wBLT 74 | or wBNE) begin 75 | case (rd_of[2:0]) 76 | 3'o0: xcc <= wBEQ; 77 | 3'o1: xcc <= wBNE; 78 | 3'o2: xcc <= wBLT; 79 | 3'o3: xcc <= wBLE; 80 | 3'o4: xcc <= wBGT; 81 | 3'o5: xcc <= wBGE; 82 | default: xcc <= 1'bX; 83 | endcase // case (rd_of[2:0]) 84 | end // always @ (... 85 | 86 | always @(posedge gclk) 87 | if (grst) begin 88 | /*AUTORESET*/ 89 | // Beginning of autoreset for uninitialized flops 90 | bra_ex <= 2'h0; 91 | // End of automatics 92 | end else if (dena) begin 93 | bra_ex[1] <= #1 (wRTD | wBRU | (wBCC & xcc)); // branch 94 | bra_ex[0] <= #1 (wBRU) ? ra_of[4] : rd_of[4]; // delay 95 | end 96 | 97 | endmodule // aeMB2_brcc 98 | 99 | /* 100 | $Log: not supported by cvs2svn $ 101 | Revision 1.2 2008/04/20 16:34:32 sybreon 102 | Basic version with some features left out. 103 | 104 | Revision 1.1 2008/04/18 00:21:52 sybreon 105 | Initial import. 106 | */ -------------------------------------------------------------------------------- /noc_based_mpsoc/src/aemb/aeMB2_dparam.v: -------------------------------------------------------------------------------- 1 | /* $Id: aeMB2_dparam.v,v 1.1 2008-04-26 17:57:43 sybreon Exp $ 2 | ** 3 | ** AEMB2 EDK 6.2 COMPATIBLE CORE 4 | ** Copyright (C) 2004-2008 Shawn Tan 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | /** 22 | * @file aeMB2_dparam.v 23 | * @brief On-chip dual-port asynchronous SRAM. 24 | 25 | * This will be implemented as distributed RAM with one read/write 26 | port and one read-only port. 27 | 28 | */ 29 | 30 | // 32x64 = 77 31 | // 64x32 = 146 32 | `timescale 1ns/1ps 33 | module aeMB2_dparam (/*AUTOARG*/ 34 | // Outputs 35 | dat_o, xdat_o, 36 | // Inputs 37 | adr_i, dat_i, wre_i, xadr_i, xdat_i, xwre_i, clk_i, ena_i 38 | ) ; 39 | parameter AW = 5; // 32 40 | parameter DW = 2; // x2 41 | 42 | // PORT A - READ/WRITE 43 | output [DW-1:0] dat_o; 44 | input [AW-1:0] adr_i; 45 | input [DW-1:0] dat_i; 46 | input wre_i; 47 | 48 | // PORT X - READ ONLY 49 | output [DW-1:0] xdat_o; 50 | input [AW-1:0] xadr_i; 51 | input [DW-1:0] xdat_i; 52 | input xwre_i; 53 | 54 | // SYSCON 55 | input clk_i, 56 | ena_i; 57 | 58 | /*AUTOREG*/ 59 | reg [DW-1:0] rRAM [(1< 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | /** 22 | * Two Cycle Multiplier Unit 23 | * @file aeMB2_mult.v 24 | 25 | * This implements a 2 cycle multipler to increase clock speed. The 26 | multiplier architecture is left to the synthesis tool. Modify this 27 | to instantiate specific multipliers. 28 | 29 | */ 30 | 31 | // 30 LUTS @ 20 MHZ 32 | `timescale 1ns/1ps 33 | module aeMB2_mult (/*AUTOARG*/ 34 | // Outputs 35 | mul_mx, 36 | // Inputs 37 | opa_of, opb_of, opc_of, gclk, grst, dena, gpha 38 | ); 39 | parameter AEMB_MUL = 1; ///< implement multiplier 40 | 41 | output [31:0] mul_mx; 42 | 43 | input [31:0] opa_of; 44 | input [31:0] opb_of; 45 | input [5:0] opc_of; 46 | 47 | // SYS signals 48 | input gclk, 49 | grst, 50 | dena, 51 | gpha; 52 | 53 | /*AUTOREG*/ 54 | 55 | reg [31:0] rOPA, rOPB; 56 | reg [31:0] rMUL0, 57 | rMUL1; 58 | 59 | always @(posedge gclk) 60 | if (grst) begin 61 | /*AUTORESET*/ 62 | // Beginning of autoreset for uninitialized flops 63 | rMUL0 <= 32'h0; 64 | rMUL1 <= 32'h0; 65 | rOPA <= 32'h0; 66 | rOPB <= 32'h0; 67 | // End of automatics 68 | end else if (dena) begin 69 | //rMUL1 <= #1 rMUL0; 70 | rMUL1 <= #1 rMUL0; //rOPA * rOPB; 71 | rMUL0 <= #1 (opa_of * opb_of); 72 | rOPA <= #1 opa_of; 73 | rOPB <= #1 opb_of; 74 | end 75 | 76 | assign mul_mx = (AEMB_MUL[0]) ? rMUL1 : 32'hX; 77 | 78 | endmodule // aeMB2_mult 79 | 80 | /* 81 | $Log: not supported by cvs2svn $ 82 | Revision 1.4 2008/04/26 17:57:43 sybreon 83 | Minor performance improvements. 84 | 85 | Revision 1.3 2008/04/26 01:09:06 sybreon 86 | Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. 87 | 88 | Revision 1.2 2008/04/20 16:34:32 sybreon 89 | Basic version with some features left out. 90 | 91 | Revision 1.1 2008/04/18 00:21:52 sybreon 92 | Initial import. 93 | */ -------------------------------------------------------------------------------- /noc_based_mpsoc/src/aemb/aeMB2_pipe.v: -------------------------------------------------------------------------------- 1 | /* $Id: aeMB2_pipe.v,v 1.4 2008-05-01 08:32:58 sybreon Exp $ 2 | ** 3 | ** AEMB2 EDK 6.2 COMPATIBLE CORE 4 | ** Copyright (C) 2004-2008 Shawn Tan 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | /** 22 | * System signal controller 23 | * @file aeMB2_pipe.v 24 | 25 | * Generates clock, reset, and enable signals. Hardware clock/reset 26 | managers can be instantiated here. 27 | 28 | */ 29 | `timescale 1ns/1ps 30 | module aeMB2_pipe (/*AUTOARG*/ 31 | // Outputs 32 | brk_if, gpha, gclk, grst, dena, iena, 33 | // Inputs 34 | bra_ex, dwb_fb, xwb_fb, ich_fb, fet_fb, msr_ex, exc_dwb, exc_iwb, 35 | exc_ill, sys_clk_i, sys_int_i, sys_rst_i, sys_ena_i 36 | ); 37 | parameter AEMB_HTX = 1; 38 | 39 | output [1:0] brk_if; 40 | input [1:0] bra_ex; 41 | input dwb_fb; 42 | input xwb_fb; 43 | input ich_fb; 44 | input fet_fb; 45 | input [9:0] msr_ex; 46 | 47 | output gpha, 48 | gclk, 49 | grst, 50 | dena, 51 | iena; 52 | 53 | input [1:0] exc_dwb; 54 | input exc_iwb; 55 | input exc_ill; 56 | 57 | input sys_clk_i, 58 | sys_int_i, 59 | sys_rst_i, 60 | sys_ena_i; 61 | 62 | /*AUTOREG*/ 63 | // Beginning of automatic regs (for this module's undeclared outputs) 64 | reg [1:0] brk_if; 65 | reg gpha; 66 | // End of automatics 67 | reg [1:0] rst; 68 | reg por; 69 | reg fet; 70 | reg hit; 71 | 72 | // Instantiate clock/reset managers 73 | assign gclk = sys_clk_i; 74 | assign grst = !rst[1]; 75 | 76 | // run instruction side pipeline 77 | assign iena = ich_fb & 78 | xwb_fb & 79 | dwb_fb & 80 | sys_ena_i; 81 | // run data side pipeline 82 | assign dena = iena; 83 | 84 | // interrupt process - latches onto any interrupt until it is handled 85 | reg int_lat; ///< interrupt latch 86 | 87 | always @(posedge sys_clk_i) 88 | if (sys_rst_i) begin 89 | /*AUTORESET*/ 90 | // Beginning of autoreset for uninitialized flops 91 | int_lat <= 1'h0; 92 | // End of automatics 93 | end else begin 94 | int_lat <= #1 msr_ex[1] & (int_lat | sys_int_i); 95 | end 96 | 97 | // exception process - exceptions handled immediately 98 | wire exc_lat; ///< exception latch 99 | assign exc_lat = exc_ill | exc_dwb[1]; 100 | 101 | always @(posedge gclk) 102 | if (grst) begin 103 | /*AUTORESET*/ 104 | // Beginning of autoreset for uninitialized flops 105 | brk_if <= 2'h0; 106 | // End of automatics 107 | end else if (dena) begin 108 | brk_if[1] <= #1 exc_lat & msr_ex[8] & !msr_ex[9]; // HIGH PRIORITY - exception 109 | brk_if[0] <= #1 !exc_lat & !msr_ex[9] & !msr_ex[3] & int_lat; // LOW PRIORITY - interrupt (not BIP/EIP) 110 | end 111 | 112 | // RESET DELAY 113 | always @(posedge sys_clk_i) 114 | if (sys_rst_i) begin 115 | /*AUTORESET*/ 116 | // Beginning of autoreset for uninitialized flops 117 | rst <= 2'h0; 118 | // End of automatics 119 | end else begin 120 | rst <= #1 {rst[0], !sys_rst_i}; 121 | end 122 | 123 | // PHASE TOGGLE 124 | always @(posedge sys_clk_i) 125 | if (sys_rst_i) begin 126 | /*AUTORESET*/ 127 | // Beginning of autoreset for uninitialized flops 128 | gpha <= 1'h0; 129 | // End of automatics 130 | end else if (dena | grst) begin 131 | gpha <= #1 !gpha; 132 | end 133 | 134 | endmodule // aeMB2_pipe 135 | 136 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/aemb/aeMB2_regs.v: -------------------------------------------------------------------------------- 1 | /* $Id: aeMB2_regs.v,v 1.4 2008-04-26 17:57:43 sybreon Exp $ 2 | ** 3 | ** AEMB2 EDK 6.2 COMPATIBLE CORE 4 | ** Copyright (C) 2004-2008 Shawn Tan 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | /** 22 | * Register File Wrapper 23 | * @file aeMB2_regs.v 24 | 25 | * A collection of general purpose and special function registers. 26 | 27 | */ 28 | 29 | // 200@207 30 | `timescale 1ns/1ps 31 | module aeMB2_regs (/*AUTOARG*/ 32 | // Outputs 33 | opd_if, opb_if, opa_if, 34 | // Inputs 35 | xwb_mx, sfr_mx, sel_mx, rpc_mx, rd_of, rd_ex, mux_of, mux_ex, 36 | mul_mx, ich_dat, grst, gpha, gclk, dwb_mx, dena, bsf_mx, alu_mx 37 | ); 38 | 39 | parameter AEMB_HTX = 1; 40 | 41 | /*AUTOOUTPUT*/ 42 | // Beginning of automatic outputs (from unused autoinst outputs) 43 | output [31:0] opa_if; // From gprf0 of aeMB2_gprf.v 44 | output [31:0] opb_if; // From gprf0 of aeMB2_gprf.v 45 | output [31:0] opd_if; // From gprf0 of aeMB2_gprf.v 46 | // End of automatics 47 | /*AUTOINPUT*/ 48 | // Beginning of automatic inputs (from unused autoinst inputs) 49 | input [31:0] alu_mx; // To gprf0 of aeMB2_gprf.v 50 | input [31:0] bsf_mx; // To gprf0 of aeMB2_gprf.v 51 | input dena; // To gprf0 of aeMB2_gprf.v 52 | input [31:0] dwb_mx; // To gprf0 of aeMB2_gprf.v 53 | input gclk; // To gprf0 of aeMB2_gprf.v 54 | input gpha; // To gprf0 of aeMB2_gprf.v 55 | input grst; // To gprf0 of aeMB2_gprf.v 56 | input [31:0] ich_dat; // To gprf0 of aeMB2_gprf.v 57 | input [31:0] mul_mx; // To gprf0 of aeMB2_gprf.v 58 | input [2:0] mux_ex; // To gprf0 of aeMB2_gprf.v 59 | input [2:0] mux_of; // To gprf0 of aeMB2_gprf.v 60 | input [4:0] rd_ex; // To gprf0 of aeMB2_gprf.v 61 | input [4:0] rd_of; // To gprf0 of aeMB2_gprf.v 62 | input [31:2] rpc_mx; // To gprf0 of aeMB2_gprf.v 63 | input [3:0] sel_mx; // To gprf0 of aeMB2_gprf.v 64 | input [31:0] sfr_mx; // To gprf0 of aeMB2_gprf.v 65 | input [31:0] xwb_mx; // To gprf0 of aeMB2_gprf.v 66 | // End of automatics 67 | /*AUTOWIRE*/ 68 | 69 | // TODO: Add special function registers 70 | 71 | aeMB2_gprf 72 | #(/*AUTOINSTPARAM*/ 73 | // Parameters 74 | .AEMB_HTX (AEMB_HTX)) 75 | gprf0 76 | (/*AUTOINST*/ 77 | // Outputs 78 | .opa_if (opa_if[31:0]), 79 | .opb_if (opb_if[31:0]), 80 | .opd_if (opd_if[31:0]), 81 | // Inputs 82 | .mux_of (mux_of[2:0]), 83 | .mux_ex (mux_ex[2:0]), 84 | .ich_dat (ich_dat[31:0]), 85 | .rd_of (rd_of[4:0]), 86 | .rd_ex (rd_ex[4:0]), 87 | .sel_mx (sel_mx[3:0]), 88 | .rpc_mx (rpc_mx[31:2]), 89 | .xwb_mx (xwb_mx[31:0]), 90 | .dwb_mx (dwb_mx[31:0]), 91 | .alu_mx (alu_mx[31:0]), 92 | .sfr_mx (sfr_mx[31:0]), 93 | .mul_mx (mul_mx[31:0]), 94 | .bsf_mx (bsf_mx[31:0]), 95 | .gclk (gclk), 96 | .grst (grst), 97 | .dena (dena), 98 | .gpha (gpha)); 99 | 100 | endmodule // aeMB2_regs 101 | 102 | /* 103 | $Log: not supported by cvs2svn $ 104 | Revision 1.3 2008/04/26 01:09:06 sybreon 105 | Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. 106 | 107 | Revision 1.2 2008/04/21 12:11:38 sybreon 108 | Passes arithmetic tests with single thread. 109 | 110 | Revision 1.1 2008/04/18 00:21:52 sybreon 111 | Initial import. 112 | */ -------------------------------------------------------------------------------- /noc_based_mpsoc/src/aemb/aeMB2_sparam.v: -------------------------------------------------------------------------------- 1 | /* $Id: aeMB2_sparam.v,v 1.2 2008-04-26 01:09:06 sybreon Exp $ 2 | ** 3 | ** AEMB2 EDK 6.2 COMPATIBLE CORE 4 | ** Copyright (C) 2004-2008 Shawn Tan 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | /** 22 | * @file aeMB2_sparam.v 23 | * @brief On-chip single-port asynchronous SRAM. 24 | 25 | * This will be implemented as distributed RAM. 26 | 27 | */ 28 | `timescale 1ns/1ps 29 | module aeMB2_sparam (/*AUTOARG*/ 30 | // Outputs 31 | dat_o, 32 | // Inputs 33 | adr_i, dat_i, wre_i, clk_i, ena_i 34 | ) ; 35 | parameter AW = 5; // 32 36 | parameter DW = 2; // x2 37 | 38 | // PORT A - READ/WRITE 39 | output [DW-1:0] dat_o; 40 | input [AW-1:0] adr_i; 41 | input [DW-1:0] dat_i; 42 | input wre_i; 43 | 44 | // SYSCON 45 | input clk_i, ena_i; 46 | 47 | /*AUTOREG*/ 48 | 49 | reg [DW-1:0] rRAM [(1< 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | 22 | /** 23 | * @file aeMB2_spsram.v 24 | * @brief On-chip singla-port synchronous SRAM. 25 | 26 | * Infer a write-before-read block RAM. 27 | 28 | * NOTES: Quartus (<=7.2) does not infer a block RAM with read enable. 29 | 30 | */ 31 | `timescale 1ns/1ps 32 | module aeMB2_spsram (/*AUTOARG*/ 33 | // Outputs 34 | dat_o, 35 | // Inputs 36 | adr_i, dat_i, wre_i, ena_i, rst_i, clk_i 37 | ) ; 38 | parameter AW = 8; 39 | parameter DW = 32; 40 | 41 | // PORT A - READ/WRITE 42 | output [DW-1:0] dat_o; 43 | input [AW-1:0] adr_i; 44 | input [DW-1:0] dat_i; 45 | input wre_i, 46 | ena_i, 47 | rst_i, 48 | clk_i; 49 | 50 | /*AUTOREG*/ 51 | // Beginning of automatic regs (for this module's undeclared outputs) 52 | reg [DW-1:0] dat_o; 53 | // End of automatics 54 | reg [DW:1] rRAM [(1< 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | /** 22 | * @file aeMB2_tpsram.v 23 | * @brief On-chip two-port synchronous SRAM. 24 | 25 | * Port A is used for writing and port B is used for reading 26 | * ONLY. Output buffers are cleared during reset. NOTE: Quartus 27 | * (<=7.2) does not infer a correct SYNCRAM block with read enable. 28 | 29 | */ 30 | `timescale 1ns/1ps 31 | module aeMB2_tpsram (/*AUTOARG*/ 32 | // Outputs 33 | dat_o, xdat_o, 34 | // Inputs 35 | adr_i, dat_i, wre_i, ena_i, rst_i, clk_i, xadr_i, xdat_i, xwre_i, 36 | xena_i, xrst_i, xclk_i 37 | ) ; 38 | parameter AW = 8; // 256 39 | parameter DW = 32; // x32 40 | 41 | // PORT A - WRITE 42 | output [DW-1:0] dat_o; 43 | input [AW-1:0] adr_i; 44 | input [DW-1:0] dat_i; 45 | input wre_i, 46 | ena_i, 47 | rst_i, 48 | clk_i; 49 | 50 | // PORT X - READ 51 | output [DW-1:0] xdat_o; 52 | input [AW-1:0] xadr_i; 53 | input [DW-1:0] xdat_i; 54 | input xwre_i, 55 | xena_i, 56 | xrst_i, 57 | xclk_i; 58 | 59 | /*AUTOREG*/ 60 | // Beginning of automatic regs (for this module's undeclared outputs) 61 | reg [DW-1:0] xdat_o; 62 | // End of automatics 63 | reg [DW:1] rRAM [(1< 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU Lesser General Public License as 10 | ** published by the Free Software Foundation, either version 3 of the 11 | ** License, or (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General 16 | ** Public License for more details. 17 | ** 18 | ** You should have received a copy of the GNU Lesser General Public 19 | ** License along with AEMB. If not, see . 20 | */ 21 | /** 22 | * Accelerator Interface 23 | * @file aeMB2_xslif.v 24 | 25 | * This sets up the Wishbone control signals for the XSL bus 26 | interface. This is a non optional bus interface. Bus transactions 27 | are independent of the pipeline. 28 | 29 | */ 30 | 31 | `timescale 1ns/1ps 32 | module aeMB2_xslif (/*AUTOARG*/ 33 | // Outputs 34 | xwb_adr_o, xwb_dat_o, xwb_sel_o, xwb_tag_o, xwb_stb_o, xwb_cyc_o, 35 | xwb_wre_o, xwb_fb, xwb_mx, 36 | // Inputs 37 | xwb_dat_i, xwb_ack_i, imm_of, opc_of, opa_of, gclk, grst, dena, 38 | gpha 39 | ); 40 | parameter AEMB_XSL = 1; ///< implement XSEL bus (ignored) 41 | parameter AEMB_XWB = 3; ///< XSEL bus width 42 | 43 | // XWB control signals 44 | output [AEMB_XWB-1:2] xwb_adr_o; 45 | output [31:0] xwb_dat_o; 46 | output [3:0] xwb_sel_o; 47 | output xwb_tag_o; 48 | output xwb_stb_o, 49 | xwb_cyc_o, 50 | xwb_wre_o; 51 | input [31:0] xwb_dat_i; 52 | input xwb_ack_i; 53 | 54 | // INTERNAL 55 | output xwb_fb; 56 | output [31:0] xwb_mx; 57 | input [15:0] imm_of; 58 | input [5:0] opc_of; 59 | input [31:0] opa_of; 60 | 61 | // SYS signals 62 | input gclk, 63 | grst, 64 | dena, 65 | gpha; 66 | 67 | /*AUTOREG*/ 68 | // Beginning of automatic regs (for this module's undeclared outputs) 69 | reg [AEMB_XWB-1:2] xwb_adr_o; 70 | reg [31:0] xwb_dat_o; 71 | reg [31:0] xwb_mx; 72 | reg xwb_stb_o; 73 | reg xwb_tag_o; 74 | reg xwb_wre_o; 75 | // End of automatics 76 | 77 | // FIXME: perform NGET/NPUT non-blocking operations 78 | assign xwb_fb = (xwb_stb_o ~^ xwb_ack_i); 79 | 80 | // XSEL bus 81 | reg [31:0] xwb_lat; 82 | 83 | always @(posedge gclk) 84 | if (grst) begin 85 | /*AUTORESET*/ 86 | // Beginning of autoreset for uninitialized flops 87 | xwb_adr_o <= {(1+(AEMB_XWB-1)-(2)){1'b0}}; 88 | xwb_dat_o <= 32'h0; 89 | xwb_mx <= 32'h0; 90 | xwb_tag_o <= 1'h0; 91 | xwb_wre_o <= 1'h0; 92 | // End of automatics 93 | end else if (dena) begin 94 | 95 | xwb_adr_o <= #1 imm_of[11:0]; // FSLx 96 | xwb_wre_o <= #1 imm_of[15]; // PUT 97 | xwb_tag_o <= #1 imm_of[13]; // cGET/cPUT 98 | 99 | xwb_dat_o <= #1 opa_of; // Latch output 100 | 101 | xwb_mx <= #1 (xwb_ack_i) ? 102 | xwb_dat_i : // stalled from XWB 103 | xwb_lat; // Latch earlier 104 | 105 | end // if (dena) 106 | 107 | assign xwb_sel_o = 4'hF; 108 | 109 | // Independent on pipeline 110 | reg xBLK; 111 | 112 | always @(posedge gclk) 113 | if (grst) begin 114 | /*AUTORESET*/ 115 | // Beginning of autoreset for uninitialized flops 116 | xwb_lat <= 32'h0; 117 | // End of automatics 118 | end else if (xwb_ack_i) begin 119 | xwb_lat <= #1 xwb_dat_i; 120 | end 121 | 122 | always @(posedge gclk) 123 | if (grst) begin 124 | /*AUTORESET*/ 125 | // Beginning of autoreset for uninitialized flops 126 | xBLK <= 1'h0; 127 | xwb_stb_o <= 1'h0; 128 | // End of automatics 129 | end else if (xwb_fb) begin 130 | xBLK <= #1 imm_of[14]; // nGET/nPUT 131 | xwb_stb_o <= #1 (dena) ? !opc_of[5] & opc_of[4] & opc_of[3] & opc_of[1] : // GET/PUT 132 | (xwb_stb_o & !xwb_ack_i); 133 | end 134 | 135 | assign xwb_cyc_o = xwb_stb_o; 136 | //assign xwb_stb_o = (AEMB_XSL[0]) ? xSTB : 1'bX; 137 | 138 | endmodule // aeMB2_xslif 139 | 140 | /* 141 | $Log: not supported by cvs2svn $ 142 | Revision 1.6 2008/04/27 16:04:12 sybreon 143 | Fixed minor typos. 144 | 145 | Revision 1.5 2008/04/26 17:57:43 sybreon 146 | Minor performance improvements. 147 | 148 | Revision 1.4 2008/04/26 01:09:06 sybreon 149 | Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. 150 | 151 | Revision 1.3 2008/04/21 12:11:38 sybreon 152 | Passes arithmetic tests with single thread. 153 | 154 | Revision 1.2 2008/04/20 16:34:32 sybreon 155 | Basic version with some features left out. 156 | 157 | Revision 1.1 2008/04/18 00:21:52 sybreon 158 | Initial import. 159 | */ 160 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/parameter.v: -------------------------------------------------------------------------------- 1 | /********************************************************************* 2 | 3 | File: parameter.v 4 | 5 | Copyright (C) 2014 Alireza Monemi 6 | 7 | This program is free software: you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation, either version 3 of the License, or 10 | (at your option) any later version. 11 | 12 | This program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License 18 | along with this program. If not, see . 19 | 20 | 21 | Purpose: 22 | aeMB Ip core parameter defination 23 | 24 | Info: monemi@fkegraduate.utm.my 25 | *********************************************************************/ 26 | 27 | 28 | 29 | //slave device number 30 | 31 | 32 | 33 | `ifdef ADD_BUS_LOCALPARAM 34 | localparam ADDR_PERFIX = 8; 35 | 36 | // Total number of master port in wishbone bus. The aeMB has two master port. To add new device 37 | // update its as : MASTER_NUM = 2+NOC_EN + (NEW_DEV_EN * number of master port the new device has) 38 | localparam MASTER_NUM = 2+NOC_EN; //number of master port 39 | 40 | //Total number of slave port. 41 | // To add new device, update its as : SLAVE_NUM = old_value + (NEW_DEV_EN * number of slave port the new device has) 42 | localparam SLAVE_NUM = RAM_EN + GPIO_EN + NOC_EN + EXT_INT_EN + TIMER_EN + INT_CTRL_EN; 43 | 44 | 45 | // addrees range definition 46 | localparam RAM_ADDR_START = 8'H00; // 32'H00000000 to 32'H3FFFFFFF 47 | localparam RAM_BK_NUM = 8'H3F; 48 | 49 | 50 | localparam NOC_ADDR_START = 8'H40; // 32'H40000000 to 32'H40FFFFFF 51 | localparam NOC_BK_NUM = 8'H01; 52 | 53 | localparam GPIO_ADDR_START = 8'H41; // 32'H41000000 to 32'H41FFFFFF 54 | localparam GPIO_BK_NUM = 8'H01; 55 | 56 | 57 | localparam EXT_INT_ADDR_START = 8'H42; // 32'H42000000 to 32'H42FFFFFF 58 | localparam EXT_INT_BK_NUM = 8'H01; 59 | 60 | localparam TIMER_ADDR_START = 8'H43; // 32'H43000000 to 32'H43FFFFFF 61 | localparam TIMER_BK_NUM = 8'H01; 62 | 63 | localparam INT_CTRL_ADDR_START = 8'H44; // 32'H44000000 to 32'H44FFFFFF 64 | localparam INT_CTRL_BK_NUM = 8'H01; 65 | //add new device addr range here 66 | 67 | 68 | // salve and master conection port definition 69 | 70 | 71 | localparam RAM_ID = 0; 72 | localparam RAM_ID_E = 0; 73 | 74 | localparam NOC_S_ID = ( NOC_EN ) ? RAM_ID_E + 1 : 255; 75 | localparam NOC_S_ID_E = RAM_ID_E + NOC_EN; 76 | 77 | localparam GPIO_ID = ( GPIO_EN ) ? NOC_S_ID_E + 1 : 255; 78 | localparam GPIO_ID_E = NOC_S_ID_E + GPIO_EN ; 79 | 80 | localparam EXT_INT_ID = (EXT_INT_EN) ? GPIO_ID_E +1 : 255; 81 | localparam EXT_INT_ID_E = GPIO_ID_E + EXT_INT_EN; 82 | 83 | localparam TIMER_ID = (TIMER_EN) ? EXT_INT_ID_E +1 : 255; 84 | localparam TIMER_ID_E = EXT_INT_ID_E + TIMER_EN; 85 | 86 | localparam INT_CTRL_ID = (INT_CTRL_EN) ? TIMER_ID_E +1 : 255; 87 | localparam INT_CTRL_ID_E = TIMER_ID_E + INT_CTRL_EN; 88 | 89 | //localparam NEW_ID = (NEW_EN) ? LAST_ID_E +1 : 255; 90 | //localparam NEW_ID_E = LAST_ID_E + NEW_EN; 91 | 92 | //master device number 93 | localparam IWB_ID = 0; 94 | localparam IWB_ERR_EN = 0; 95 | localparam IWB_RTY_EN = 0; 96 | 97 | 98 | localparam DWB_ID = 1; 99 | localparam DWB_ERR_EN = 0; 100 | localparam DWB_RTY_EN = 0; 101 | 102 | localparam NOC_M_ID = ( NOC_EN ) ? 2 : 255; 103 | localparam NOC_M_ID_E = 2 + NOC_EN; 104 | localparam NOC_M_ERR_EN = 0; 105 | localparam NOC_M_RTY_EN = 0; 106 | 107 | localparam ERR_EN_ARRAY = (IWB_ERR_EN << IWB_ERR_EN)| 108 | (DWB_ERR_EN << DWB_ERR_EN)| 109 | ((NOC_EN*NOC_M_ERR_EN)<< NOC_M_ID) ; 110 | 111 | localparam RTY_EN_ARRAY = (IWB_RTY_EN << IWB_RTY_EN)| 112 | (DWB_RTY_EN << DWB_RTY_EN)| 113 | ((NOC_EN&NOC_M_RTY_EN)<< NOC_M_ID) ; 114 | 115 | localparam NI_BASE_ADDR = {NOC_ADDR_START,{32-ADDR_PERFIX{1'b0}}}; 116 | `endif 117 | 118 | 119 | 120 | 121 | 122 | -------------------------------------------------------------------------------- /noc_based_mpsoc/src/testbench_soc.v: -------------------------------------------------------------------------------- 1 | /********************************************************************* 2 | 3 | File: testbench_soc.v 4 | 5 | Copyright (C) 2014 Alireza Monemi 6 | 7 | This program is free software: you can redistribute it and/or modify 8 | it under the terms of the GNU General Public License as published by 9 | the Free Software Foundation, either version 3 of the License, or 10 | (at your option) any later version. 11 | 12 | This program is distributed in the hope that it will be useful, 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | GNU General Public License for more details. 16 | 17 | You should have received a copy of the GNU General Public License 18 | along with this program. If not, see . 19 | 20 | 21 | Purpose: 22 | A testbench for top-level design. This testbench can be used to simulate 23 | a real life application. running the ./soc_run file in sw folder 24 | will copy the generated mif file in simulation folder which will be read 25 | by modelsim. 26 | 27 | Info: monemi@fkegraduate.utm.my 28 | *********************************************************************/ 29 | 30 | `timescale 1ns/1ps 31 | 32 | 33 | module testbench_soc (); 34 | reg clk,reset; 35 | wire [3 : 0] KEY; 36 | wire [3 : 0] LEDG; 37 | wire [6 : 0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; 38 | reg [2: 0] ext_int; 39 | 40 | 41 | 42 | SoC_IP_top IP( 43 | .CLOCK_50 (clk), 44 | .KEY (KEY), 45 | .LEDG (LEDG), 46 | .HEX0 (HEX0), 47 | .HEX1 (HEX1), 48 | .HEX2 (HEX2), 49 | .HEX3 (HEX3), 50 | .HEX4 (HEX4), 51 | .HEX5 (HEX5), 52 | .HEX6 (HEX6), 53 | .HEX7 (HEX7) 54 | 55 | ); 56 | 57 | assign KEY= {ext_int,~reset}; 58 | 59 | 60 | 61 | 62 | initial begin 63 | clk = 1'b0; 64 | forever clk = #10 ~clk; 65 | end 66 | 67 | initial begin 68 | ext_int=0; 69 | reset=1; 70 | #50 71 | reset=0; 72 | 73 | #300000 74 | ext_int = 1; 75 | #50 76 | ext_int = 0; 77 | 78 | end 79 | 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/aemb/core.hh: -------------------------------------------------------------------------------- 1 | /* $Id: core.hh,v 1.5 2008-05-31 17:02:04 sybreon Exp $ 2 | ** 3 | ** AEMB2 HI-PERFORMANCE CPU 4 | ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU General Public License as published by 10 | ** the Free Software Foundation, either version 3 of the License, or 11 | ** (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 | ** License for more details. 17 | ** 18 | ** You should have received a copy of the GNU General Public License 19 | ** along with AEMB. If not, see . 20 | */ 21 | 22 | /** 23 | General AEMB2 core library 24 | @file core.hh 25 | */ 26 | 27 | #ifdef __MICROBLAZE__ 28 | 29 | #include "aemb/msr.hh" 30 | #include "aemb/stack.hh" 31 | #include "aemb/heap.hh" 32 | #include "aemb/thread.hh" 33 | #include "aemb/hook.hh" 34 | #include "aemb/stdio.hh" 35 | #include "aemb/semaphore.hh" 36 | 37 | #endif 38 | 39 | /* 40 | $Log: not supported by cvs2svn $ 41 | Revision 1.4 2008/04/28 20:29:15 sybreon 42 | Made files C compatible under C++. 43 | 44 | Revision 1.3 2008/04/27 16:33:42 sybreon 45 | License change to GPL3. 46 | 47 | Revision 1.2 2008/04/26 19:31:35 sybreon 48 | Made headers C compatible. 49 | 50 | Revision 1.1 2008/04/09 19:48:37 sybreon 51 | Added new C++ files 52 | 53 | */ 54 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/aemb/heap.hh: -------------------------------------------------------------------------------- 1 | /* $Id: heap.hh,v 1.6 2008-04-28 20:29:15 sybreon Exp $ 2 | ** 3 | ** AEMB2 HI-PERFORMANCE CPU 4 | ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU General Public License as published by 10 | ** the Free Software Foundation, either version 3 of the License, or 11 | ** (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 | ** License for more details. 17 | ** 18 | ** You should have received a copy of the GNU General Public License 19 | ** along with AEMB. If not, see . 20 | */ 21 | 22 | /** 23 | Basic heap related functions 24 | @file heap.hh 25 | */ 26 | 27 | #ifndef _AEMB_HEAP_HH 28 | #define _AEMB_HEAP_HH 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | /** 35 | Extracts the heap size from the linker 36 | @return heap size 37 | */ 38 | 39 | inline int aembGetHeapSize() 40 | { 41 | int tmp; 42 | asm ("la %0, r0, _HEAP_SIZE":"=r"(tmp)); 43 | return tmp; 44 | } 45 | 46 | /** 47 | Extracts the heap end from the linker 48 | @return heap end 49 | */ 50 | 51 | inline int aembGetHeapEnd() 52 | { 53 | int tmp; 54 | asm ("la %0, r0, _heap_end":"=r"(tmp)); 55 | return tmp; 56 | } 57 | 58 | /** 59 | Extracts the heap top from the linker 60 | @return heap top 61 | */ 62 | 63 | inline int aembGetHeapTop() 64 | { 65 | int tmp; 66 | asm ("la %0, r0, _heap":"=r"(tmp)); 67 | return tmp; 68 | } 69 | 70 | #ifdef __cplusplus 71 | } 72 | #endif 73 | 74 | #endif 75 | 76 | /* 77 | $Log: not supported by cvs2svn $ 78 | Revision 1.5 2008/04/27 16:33:42 sybreon 79 | License change to GPL3. 80 | 81 | Revision 1.4 2008/04/26 19:31:35 sybreon 82 | Made headers C compatible. 83 | 84 | Revision 1.3 2008/04/26 18:05:22 sybreon 85 | Minor cosmetic changes. 86 | 87 | Revision 1.2 2008/04/20 16:35:53 sybreon 88 | Added C/C++ compatible #ifdef statements 89 | 90 | Revision 1.1 2008/04/09 19:48:37 sybreon 91 | Added new C++ files 92 | 93 | */ 94 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/aemb/msr.hh: -------------------------------------------------------------------------------- 1 | /* $Id: msr.hh,v 1.9 2008-04-28 20:29:15 sybreon Exp $ 2 | ** 3 | ** AEMB2 HI-PERFORMANCE CPU 4 | ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU General Public License as published by 10 | ** the Free Software Foundation, either version 3 of the License, or 11 | ** (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 | ** License for more details. 17 | ** 18 | ** You should have received a copy of the GNU General Public License 19 | ** along with AEMB. If not, see . 20 | */ 21 | 22 | /** 23 | Basic MSR functions 24 | @file msr.hh 25 | 26 | These functions provide read/write access to the Machine Status 27 | Register. It also contains the bit definitions of the register. 28 | */ 29 | 30 | #ifndef _AEMB_MSR_HH 31 | #define _AEMB_MSR_HH 32 | 33 | // STANDARD BITS 34 | #define AEMB_MSR_BE (1 << 0) ///< Buslock Enable 35 | #define AEMB_MSR_IE (1 << 1) ///< Interrupt Enable 36 | #define AEMB_MSR_C (1 << 2) ///< Arithmetic Carry 37 | #define AEMB_MSR_BIP (1 << 3) ///< Break in Progress 38 | #define AEMB_MSR_EE (1 << 8) ///< Exception Enable 39 | #define AEMB_MSR_EIP (1 << 9) ///< Exception in Progress 40 | 41 | #define AEMB_MSR_ITE (1 << 5) ///< Instruction Cache Enable 42 | #define AEMB_MSR_DZ (1 << 6) ///< Division by Zero 43 | #define AEMB_MSR_DTE (1 << 7) ///< Data Cache Enable 44 | 45 | // CUSTOM BITS 46 | #define AEMB_MSR_MTX (1 << 4) ///< Hardware Mutex 47 | #define AEMB_MSR_PHA (1 << 29) ///< Hardware Thread Phase 48 | #define AEMB_MSR_HTX (1 << 30) ///< Hardware Threads Extension 49 | #define AEMB_MSR_CC (1 << 31) ///< Carry Copy 50 | 51 | #ifdef __cplusplus 52 | extern "C" { 53 | #endif 54 | 55 | /** 56 | Read the value of the MSR register 57 | @return register contents 58 | */ 59 | 60 | inline int aembGetMSR() 61 | { 62 | int rmsr; 63 | asm volatile ("mfs %0, rmsr":"=r"(rmsr)); 64 | return rmsr; 65 | } 66 | 67 | /** 68 | Write a value to the MSR register 69 | @param rmsr value to write 70 | */ 71 | 72 | inline void aembPutMSR(int rmsr) 73 | { 74 | asm volatile ("mts rmsr, %0"::"r"(rmsr)); 75 | } 76 | 77 | /** 78 | Read and clear the MSR 79 | @param rmsk clear mask 80 | @return msr value 81 | */ 82 | 83 | inline int aembClrMSR(const short rmsk) 84 | { 85 | int tmp; 86 | //asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory"); 87 | return tmp; 88 | } 89 | 90 | /** 91 | Read and set the MSR 92 | @param rmsk set mask 93 | @return msr value 94 | */ 95 | 96 | inline int aembSetMSR(const short rmsk) 97 | { 98 | int tmp; 99 | //asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory"); 100 | return tmp; 101 | } 102 | 103 | /** Enable global interrupts */ 104 | inline int aembEnableInterrupts() 105 | { 106 | int msr; 107 | asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_IE)); 108 | return msr; 109 | } 110 | 111 | /** Disable global interrupts */ 112 | inline int aembDisableInterrupts() 113 | { 114 | int msr; 115 | asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_IE)); 116 | return msr; 117 | } 118 | 119 | /** Enable global exception */ 120 | inline int aembEnableException() 121 | { 122 | int msr; 123 | asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_EE)); 124 | return msr; 125 | } 126 | 127 | /** Disable global exception */ 128 | inline int aembDisableException() 129 | { 130 | int msr; 131 | asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_EE)); 132 | return msr; 133 | } 134 | 135 | /** Enable data caches */ 136 | inline int aembEnableDataTag() 137 | { 138 | int msr; 139 | asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE)); 140 | return msr; 141 | } 142 | 143 | /** Disable data caches */ 144 | inline int aembDisableDataTag() 145 | { 146 | int msr; 147 | asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_DTE)); 148 | return msr; 149 | } 150 | 151 | /** Enable inst caches */ 152 | inline int aembEnableInstTag() 153 | { 154 | int msr; 155 | asm volatile ("msrset %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE)); 156 | return msr; 157 | } 158 | 159 | /** Disable inst caches */ 160 | inline int aembDisableInstTag() 161 | { 162 | int msr; 163 | asm volatile ("msrclr %0, %1":"=r"(msr):"K"(AEMB_MSR_ITE)); 164 | return msr; 165 | } 166 | 167 | #ifdef __cplusplus 168 | } 169 | #endif 170 | 171 | #endif 172 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/aemb/semaphore.hh: -------------------------------------------------------------------------------- 1 | /* $Id: semaphore.hh,v 1.1 2008-04-28 20:29:15 sybreon Exp $ 2 | ** 3 | ** AEMB2 HI-PERFORMANCE CPU 4 | ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU General Public License as published by 10 | ** the Free Software Foundation, either version 3 of the License, or 11 | ** (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 | ** License for more details. 17 | ** 18 | ** You should have received a copy of the GNU General Public License 19 | ** along with AEMB. If not, see . 20 | */ 21 | 22 | /** 23 | General semaphore library 24 | @file semaphore.hh 25 | */ 26 | 27 | #include "aemb/thread.hh" 28 | 29 | #ifndef _AEMB_SEMAPHORE_HH 30 | #define _AEMB_SEMAPHORE_HH 31 | 32 | #ifdef __cplusplus 33 | extern "C" { 34 | #endif 35 | 36 | // TODO: Extend this library to include threading mechanisms such as 37 | // semaphores, mutexes and such. 38 | 39 | /** 40 | Semaphore struct. 41 | Presently implemented as software solution but a hardware one may be 42 | required as the threads are hardware. 43 | */ 44 | 45 | typedef int semaphore; 46 | 47 | /** 48 | Software Semaphore Signal. 49 | 50 | Increment the semaphore and run. This is a software mechanism. 51 | */ 52 | inline void aembSignal(volatile semaphore _sem) 53 | { 54 | _aembLockMTX(); 55 | _sem++; 56 | _aembFreeMTX(); 57 | } 58 | 59 | /** 60 | Software Semaphore Wait. 61 | 62 | Decrement the semaphore and block if < 0. This is a software 63 | mechanism. 64 | */ 65 | inline void aembWait(volatile semaphore _sem) 66 | { 67 | _aembLockMTX(); 68 | _sem--; 69 | _aembFreeMTX(); 70 | while (_sem < 0); 71 | } 72 | 73 | semaphore __mutex_rendezvous0 = 0; ///< internal rendezvous mutex 74 | semaphore __mutex_rendezvous1 = 1; ///< internal rendezvous mutex 75 | 76 | /** 77 | Implements a simple rendezvous mechanism 78 | */ 79 | /* 80 | inline void aembRendezvous() 81 | { 82 | if (isThread1()) 83 | { 84 | wait(__mutex_rendezvous0); 85 | signal(__mutex_rendezvous1); 86 | } 87 | else 88 | { 89 | signal(__mutex_rendezvous0); 90 | wait(__mutex_rendezvous1); 91 | } 92 | } 93 | */ 94 | 95 | #ifdef __cplusplus 96 | } 97 | #endif 98 | 99 | #endif 100 | 101 | /* 102 | $log$ 103 | */ 104 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/aemb/stack.hh: -------------------------------------------------------------------------------- 1 | /* $Id: stack.hh,v 1.8 2008-04-28 20:29:15 sybreon Exp $ 2 | ** 3 | ** AEMB2 HI-PERFORMANCE CPU 4 | ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU General Public License as published by 10 | ** the Free Software Foundation, either version 3 of the License, or 11 | ** (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 | ** License for more details. 17 | ** 18 | ** You should have received a copy of the GNU General Public License 19 | ** along with AEMB. If not, see . 20 | */ 21 | 22 | /** 23 | Basic stack related functions 24 | @file stack.hh 25 | */ 26 | 27 | #ifndef _AEMB_STACK_HH 28 | #define _AEMB_STACK_HH 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | /** 35 | Reads the size of the memory space allocated for the stack in bytes. 36 | @return size of stack 37 | */ 38 | 39 | inline int aembGetStackSize() 40 | { 41 | int tmp; 42 | asm ("la %0, r0, _STACK_SIZE":"=r"(tmp)); 43 | return tmp; 44 | } 45 | 46 | /** 47 | Reads the end of the memory space allocated for the stack. This is 48 | where the stack ends. 49 | @return end of stack 50 | */ 51 | 52 | inline int aembGetStackEnd() 53 | { 54 | int tmp; 55 | asm ("la %0, r0, _stack_end":"=r"(tmp)); 56 | return tmp; 57 | } 58 | 59 | /** 60 | Reads the top of the memory space allocated for the stack. This is 61 | where the stack starts. 62 | @return top of stack 63 | */ 64 | 65 | inline int aembGetStackTop() 66 | { 67 | int tmp; 68 | asm ("la %0, r0, _stack":"=r"(tmp)); 69 | return tmp; 70 | } 71 | 72 | /** 73 | Reads register R1 which is the designated stack pointer. 74 | @return stack pointer 75 | */ 76 | 77 | inline int aembGetStack() 78 | { 79 | int tmp; 80 | asm ("addk %0, r0, r1":"=r"(tmp)); 81 | return tmp; 82 | } 83 | 84 | /** 85 | Sets register R1 to the new stack pointer. 86 | @param stk new stack pointer 87 | @return new stack pointer 88 | */ 89 | 90 | inline int aembSetStack(int stk) 91 | { 92 | asm ("addk r1, r0, %0"::"r"(stk)); 93 | return stk; 94 | } 95 | 96 | /** 97 | Duplicates the stack 98 | @param newp new stack pointer 99 | @param oldp old stack pointer 100 | @param endp end of the stack 101 | */ 102 | 103 | inline void aembDupStack(unsigned int *newp, unsigned int *oldp, unsigned int *endp) 104 | { 105 | while (oldp < endp) 106 | { 107 | // copy the stack content 108 | *newp = *oldp; 109 | // this increments 1 word (not 1 byte) 110 | newp++; 111 | oldp++; 112 | } 113 | } 114 | 115 | #ifdef __cplusplus 116 | } 117 | #endif 118 | 119 | #endif 120 | 121 | /* 122 | $Log: not supported by cvs2svn $ 123 | Revision 1.7 2008/04/27 16:33:42 sybreon 124 | License change to GPL3. 125 | 126 | Revision 1.6 2008/04/27 16:04:42 sybreon 127 | Minor cosmetic changes. 128 | 129 | Revision 1.5 2008/04/26 19:31:35 sybreon 130 | Made headers C compatible. 131 | 132 | Revision 1.4 2008/04/26 18:04:31 sybreon 133 | Updated software to freeze T0 and run T1. 134 | 135 | Revision 1.3 2008/04/23 14:19:39 sybreon 136 | Fixed minor bugs. 137 | Initial use of hardware mutex. 138 | 139 | Revision 1.2 2008/04/20 16:35:53 sybreon 140 | Added C/C++ compatible #ifdef statements 141 | 142 | Revision 1.1 2008/04/09 19:48:37 sybreon 143 | Added new C++ files 144 | 145 | */ 146 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/aemb/stdio.hh: -------------------------------------------------------------------------------- 1 | /* $Id: stdio.hh,v 1.5 2008-04-28 20:29:15 sybreon Exp $ 2 | ** 3 | ** AEMB2 HI-PERFORMANCE CPU 4 | ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU General Public License as published by 10 | ** the Free Software Foundation, either version 3 of the License, or 11 | ** (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 | ** License for more details. 17 | ** 18 | ** You should have received a copy of the GNU General Public License 19 | ** along with AEMB. If not, see . 20 | */ 21 | 22 | /** 23 | Basic standard I/O functions 24 | @file stdio.hh 25 | 26 | These functions provide function prototypes for outbyte/inbyte 27 | which are required by the linker during compile time. These 28 | functions can be defined anywhere else in code but should not be 29 | inlined. 30 | */ 31 | 32 | #ifndef _AEMB_STDIO_HH 33 | #define _AEMB_STDIO_HH 34 | 35 | #ifdef __cplusplus 36 | extern "C" { 37 | #endif 38 | 39 | /** 40 | Default stdout prototype. 41 | @param c char 42 | 43 | This is used to output characters to LCD or UART. 44 | */ 45 | 46 | void outbyte(char c); 47 | 48 | /** 49 | Default stdin prototype. 50 | @return char 51 | 52 | This is used to read characters in from UART or keyboard. 53 | */ 54 | 55 | char inbyte(); 56 | 57 | #ifdef __cplusplus 58 | } 59 | #endif 60 | 61 | #endif 62 | 63 | /* 64 | $Log: not supported by cvs2svn $ 65 | Revision 1.4 2008/04/27 16:33:42 sybreon 66 | License change to GPL3. 67 | 68 | Revision 1.3 2008/04/26 19:31:35 sybreon 69 | Made headers C compatible. 70 | 71 | Revision 1.2 2008/04/26 18:05:22 sybreon 72 | Minor cosmetic changes. 73 | 74 | Revision 1.1 2008/04/09 19:48:37 sybreon 75 | Added new C++ files 76 | 77 | */ 78 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/aemb/thread.hh: -------------------------------------------------------------------------------- 1 | /* $Id: thread.hh,v 1.10 2008-04-28 20:29:15 sybreon Exp $ 2 | ** 3 | ** AEMB2 HI-PERFORMANCE CPU 4 | ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap 5 | ** 6 | ** This file is part of AEMB. 7 | ** 8 | ** AEMB is free software: you can redistribute it and/or modify it 9 | ** under the terms of the GNU General Public License as published by 10 | ** the Free Software Foundation, either version 3 of the License, or 11 | ** (at your option) any later version. 12 | ** 13 | ** AEMB is distributed in the hope that it will be useful, but WITHOUT 14 | ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 | ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 | ** License for more details. 17 | ** 18 | ** You should have received a copy of the GNU General Public License 19 | ** along with AEMB. If not, see . 20 | */ 21 | 22 | /** 23 | Basic thread functions 24 | @file thread.hh 25 | 26 | These functions deal with the various hardware threads. It also 27 | provides simple mechanisms for toggling semaphores. 28 | */ 29 | 30 | #include "aemb/msr.hh" 31 | 32 | #ifndef _AEMB_THREAD_HH 33 | #define _AEMB_THREAD_HH 34 | 35 | #ifdef __cplusplus 36 | extern "C" { 37 | #endif 38 | 39 | /** 40 | Checks to see if currently executing Thread 1 41 | @return true if is Thread 1 42 | */ 43 | 44 | inline int aembIsThread1() 45 | { 46 | int rmsr = aembGetMSR(); 47 | return ((rmsr & AEMB_MSR_PHA)); 48 | } 49 | 50 | /** 51 | Checks to see if currently executing Thread 0 52 | @return true if is Thread 0 53 | */ 54 | 55 | inline int aembIsThread0() 56 | { 57 | int rmsr = aembGetMSR(); 58 | return (!(rmsr & AEMB_MSR_PHA)); 59 | } 60 | 61 | /** 62 | Checks to see if it is multi-threaded or not. 63 | @return true if thread capable 64 | */ 65 | inline int aembIsThreaded() 66 | { 67 | int rmsr = aembGetMSR(); 68 | return (rmsr & AEMB_MSR_HTX); 69 | } 70 | 71 | /** 72 | Hardware Mutex Signal. 73 | Unlock the hardware mutex, which is unlocked on reset. 74 | */ 75 | inline void _aembFreeMTX() 76 | { 77 | int tmp; 78 | asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(AEMB_MSR_MTX)); 79 | } 80 | 81 | /** 82 | Hardware Mutex Wait. 83 | 84 | Waits until the hardware mutex is unlocked. This should be used 85 | as part of a larger software mutex mechanism. 86 | */ 87 | inline void _aembLockMTX() 88 | { 89 | int rmsr; 90 | do 91 | { 92 | asm volatile ("msrset %0, %1":"=r"(rmsr):"K"(AEMB_MSR_MTX)); 93 | } 94 | while (rmsr & AEMB_MSR_MTX); 95 | } 96 | 97 | #ifdef __cplusplus 98 | } 99 | #endif 100 | 101 | #endif 102 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/custom_crt/crt0.s: -------------------------------------------------------------------------------- 1 | ###################################-*-asm*- 2 | # 3 | # Copyright (c) 2001 Xilinx, Inc. All rights reserved. 4 | # 5 | # Xilinx, Inc. 6 | # 7 | # XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 8 | # COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 9 | # ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 10 | # STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 11 | # IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 12 | # FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 13 | # XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 14 | # THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 15 | # ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 16 | # FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 17 | # AND FITNESS FOR A PARTICULAR PURPOSE. 18 | # 19 | # crt0.s 20 | # 21 | # Default C run-time initialization for MicroBlaze standalone 22 | # executables (compiled with -xl-mode-executable or no switches) 23 | # 24 | # $Id: crt0.s,v 1.7.2.6 2005/11/15 23:32:53 salindac Exp $ 25 | # 26 | ####################################### 27 | 28 | /* 29 | 30 | MicroBlaze Vector Map for standalone executables 31 | 32 | Address Vector type Label 33 | ------- ----------- ------ 34 | 35 | # 0x00 # (-- IMM --) 36 | # 0x04 # Reset _start1 37 | 38 | # 0x08 # (-- IMM --) 39 | # 0x0c # Software Exception _exception_handler 40 | 41 | # 0x10 # (-- IMM --) 42 | # 0x14 # Hardware Interrupt _interrupt_handler 43 | 44 | # 0x18 # (-- IMM --) 45 | # 0x1C # Breakpoint Exception (-- Don't Care --) 46 | 47 | # 0x20 # (-- IMM --) 48 | # 0x24 # Hardware Exception _hw_exception_handler 49 | 50 | */ 51 | 52 | 53 | .globl _start 54 | .section .vectors.reset, "ax" 55 | .align 2 56 | _start: 57 | brai _start1 58 | 59 | .section .vectors.sw_exception, "ax" 60 | .align 2 61 | _vector_sw_exception: 62 | brai _exception_handler 63 | 64 | .section .vectors.interrupt, "ax" 65 | .align 2 66 | _vector_interrupt: 67 | brai _interrupt_handler 68 | 69 | .section .vectors.hw_exception, "ax" 70 | .align 2 71 | _vector_hw_exception: 72 | brai _hw_exception_handler 73 | 74 | .section .text 75 | .globl _start1 76 | .align 2 77 | _start1: 78 | la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */ 79 | la r2, r0, _SDA2_BASE_ 80 | la r1, r0, _stack-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */ 81 | 82 | brlid r15, _crtinit /* Initialize BSS and run program */ 83 | nop 84 | 85 | brlid r15, exit /* Call exit with the return value of main */ 86 | addik r5, r3, 0 87 | 88 | /* Control does not reach here */ 89 | 90 | /* 91 | _exit 92 | Our simple _exit 93 | */ 94 | .globl _exit 95 | .align 2 96 | .ent _exit 97 | _exit: 98 | bri 0 99 | .end _exit 100 | 101 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/custom_crt/crtinit.s: -------------------------------------------------------------------------------- 1 | ###################################-*-asm*- 2 | # 3 | # Copyright (c) 2001 Xilinx, Inc. All rights reserved. 4 | # 5 | # Xilinx, Inc. 6 | # 7 | # XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 8 | # COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 9 | # ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 10 | # STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 11 | # IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 12 | # FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 13 | # XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 14 | # THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 15 | # ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 16 | # FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 17 | # AND FITNESS FOR A PARTICULAR PURPOSE. 18 | # 19 | # crtinit.s 20 | # 21 | # Default second stage of C run-time initialization 22 | # 23 | # $Id: crtinit.s,v 1.5.2.7 2006/07/05 18:53:54 vasanth Exp $ 24 | # 25 | ####################################### 26 | 27 | .globl _crtinit 28 | .align 2 29 | .ent _crtinit 30 | 31 | _crtinit: 32 | addi r1, r1, -20 /* Save Link register */ 33 | swi r15, r1, 0 34 | 35 | addi r6, r0, __sbss_start /* clear SBSS */ 36 | addi r7, r0, __sbss_end 37 | rsub r18, r6, r7 38 | blei r18, .Lendsbss 39 | 40 | .Lloopsbss: 41 | swi r0, r6, 0 42 | addi r6, r6, 4 43 | rsub r18, r6, r7 44 | bgti r18, .Lloopsbss 45 | .Lendsbss: 46 | 47 | addi r6, r0, __bss_start /* clear BSS */ 48 | addi r7, r0, __bss_end 49 | rsub r18, r6, r7 50 | blei r18, .Lendbss 51 | .Lloopbss: 52 | swi r0, r6, 0 53 | addi r6, r6, 4 54 | rsub r18, r6, r7 55 | bgti r18, .Lloopbss 56 | .Lendbss: 57 | 58 | brlid r15, _program_init /* Initialize the program */ 59 | nop 60 | 61 | # brlid r15, __init /* Invoke language initialization functions */ 62 | # nop 63 | 64 | addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */ 65 | addi r7, r0, 0 66 | brlid r15, main /* Execute the program */ 67 | addi r5, r0, 0 68 | 69 | addik r19, r3, 0 /* Save return value */ 70 | 71 | # brlid r15, __fini /* Invoke language cleanup functions */ 72 | # nop 73 | 74 | brlid r15, _program_clean /* Cleanup the program */ 75 | nop 76 | 77 | lw r15, r1, r0 /* Return back to CRT */ 78 | 79 | addik r3, r19, 0 /* Restore return value */ 80 | rtsd r15, 8 81 | addi r1, r1, 20 82 | .end _crtinit 83 | 84 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/gccrom: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # $Id: gccrom,v 1.18 2008-05-01 08:35:04 sybreon Exp $ 3 | 4 | # Compile using C pre-processor 5 | ELFFILE="out/rom" 6 | XILFLAGS="-mtune=v5.00 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul " 7 | CXXFLAGS="-O2 -nostartfiles " 8 | LNKFLAGS="-Wl,-defsym -Wl,_STACK_SIZE=0x400 -Wl,-defsym -Wl,_HEAP_SIZE=0x400 -T xilinx.ld" 9 | LIBFLAGS="" 10 | INCFLAGS="-Icc/" 11 | RAMSIZE="3FFF" #for aeMB ramwith of 12 12 | 13 | INPUT="custom_crt/crt0.s custom_crt/crtinit.s" 14 | 15 | mb-g++ $XILFLAGS $CXXFLAGS $LNKFLAGS $LIBFLAGS $INCFLAGS -specs=aemb.specs $INPUT $@ -o $ELFFILE && \ 16 | #echo "xgcc=$?" && \ 17 | 18 | 19 | # Create a text listing of the compiled code 20 | mb-objdump -dDSCz $ELFFILE > $ELFFILE.dump && \ 21 | #echo "dump=$?" && \ 22 | 23 | # Convert the ELF file to an SREC file 24 | mb-objcopy -O srec $ELFFILE $ELFFILE.srec && \ 25 | #echo "copy=$?" && \ 26 | 27 | # Generate a Verilog VMEM file from the SREC file 28 | srec_cat $ELFFILE.srec -fill 0xFF -within $ELFFILE.srec --range-pad 4 -o out/dump.vmem -vmem 32 && \ 29 | #echo "srec=$?" && \ 30 | 31 | 32 | # Convert the ELF file to an IHEX file 33 | mb-objcopy -O ihex $ELFFILE $ELFFILE.ihex && \ 34 | #echo "copy2ihex=$?" && \ 35 | 36 | # Generate a MIF file from the IHEX file 37 | ihex/ihex2mif -f $ELFFILE.ihex -e $RAMSIZE -o out/ram0.mif && \ 38 | echo "ihex2mif=$?" && \ 39 | 40 | 41 | 42 | # Generate a Verilog VMEM file from the SREC file 43 | #srec_cat $ELFFILE.srec -o ../sim/dump.vmem -vmem 32 && \ 44 | #echo "srec=$?" && \ 45 | 46 | # echo the checksum 47 | MD5=$(sha1sum $ELFFILE | cut -c1-32) && \ 48 | echo "sha1=$MD5" && \ 49 | 50 | # Cleanup code 51 | rm $ELFFILE.srec && rm $ELFFILE.ihex 52 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/ihex/Makefile: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | all: 3 | gcc main.c -o ihex2mif 4 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/ihex/ihex2mif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/an-fpga-implementation-of-low-latency-noc-based-mpsoc/3d72f1b026eeb6a47f23c81992718af315b342f6/noc_based_mpsoc/sw/compile/ihex/ihex2mif -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/ihex/main.c: -------------------------------------------------------------------------------- 1 | #include "ihex.c" 2 | #include 3 | #include 4 | 5 | #define DEFAULT_OUT_FILE_NAME "out.mif" 6 | #define DEAFULT_END_SIZE "1FFF" 7 | 8 | int memory[65536]; /* the memory is global */ 9 | unsigned int end_addr_int; 10 | FILE * in, * out; 11 | char *file_name, *end_addr, *out_file_name ; 12 | 13 | void usage (void) 14 | { 15 | printf("Usage: ./ihex2mif \n"); 16 | printf("\nOptions: \n"); 17 | printf(" -e : end memory address .\n"); 18 | printf(" -f : input ihex file .\n"); 19 | 20 | } 21 | 22 | void processArgs (int argc, char **argv ) 23 | { 24 | char c; 25 | 26 | opterr = 0; 27 | 28 | while ((c = getopt (argc, argv, "e:f:o:h")) != -1) 29 | { 30 | switch (c) 31 | { 32 | case 'e': 33 | end_addr = optarg; 34 | break; 35 | case 'f': 36 | file_name = optarg; 37 | break; 38 | case 'o': 39 | out_file_name = optarg; 40 | break; 41 | case 'h': 42 | usage(); 43 | exit(1); 44 | break; 45 | case '?': 46 | if (isprint (optopt)) 47 | fprintf (stderr, "Unknown option `-%c'.\n", optopt); 48 | else 49 | fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt); 50 | default: 51 | usage(); 52 | exit(1); 53 | } 54 | } 55 | } 56 | 57 | void update_out_file(void); 58 | int main ( int argc, char **argv ){ 59 | 60 | processArgs (argc,argv ); 61 | if (file_name == NULL) {usage();exit(1);} 62 | if (end_addr == NULL) end_addr = DEAFULT_END_SIZE; 63 | if (out_file_name == NULL) out_file_name = DEFAULT_OUT_FILE_NAME; 64 | //printf("filename=%s & size=%s\n",file_name, end_addr); 65 | sscanf(end_addr, "%x", &end_addr_int); 66 | //printf("%u\n", end_addr_int); 67 | out=fopen(out_file_name,"wb"); 68 | if(out==NULL){printf("Output file cannot be created"); exit(1);} 69 | load_file(file_name); 70 | update_out_file(); 71 | 72 | 73 | fclose(out); 74 | 75 | return 0; 76 | } 77 | 78 | 79 | void update_out_file(void){ 80 | unsigned int ram_addr=0,zero_count,ram_data,i; 81 | fprintf(out,"-- Copyright (C) 2013 Alireza Monemi\n\n"); 82 | fprintf(out,"WIDTH=32;\nDEPTH=%d;\nADDRESS_RADIX=HEX;\nDATA_RADIX=HEX;\n\nCONTENT BEGIN\n", (end_addr_int>>2)+1); 83 | while(ram_addr>2,ram_data); 102 | }else if (zero_count == 1){ 103 | fprintf(out,"\t%08X\t:\t%08X;\n" , (ram_addr>>2),0); 104 | if(ram_data!=0)fprintf(out,"\t%08X\t:\t%08X;\n" , (ram_addr>>2)+1,ram_data); 105 | 106 | } 107 | else { 108 | fprintf(out,"\t[%08X..%08X]\t:\t00000000;\n" ,ram_addr>>2, (ram_addr>>2)+ zero_count-1); 109 | if(ram_data!=0)fprintf(out,"\t%08X\t:\t%08X;\n" , (ram_addr>>2)+ zero_count,ram_data); 110 | } 111 | ram_addr+=(zero_count<<2)+4; 112 | 113 | 114 | 115 | 116 | } 117 | fprintf(out,"END;"); 118 | 119 | return; 120 | } 121 | 122 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/orsocdef.h: -------------------------------------------------------------------------------- 1 | #ifndef _ORSOCDEF_ 2 | #define _ORSOCDEF_ 3 | 4 | /******************************************************************************/ 5 | /* T Y P E D E F S */ 6 | /******************************************************************************/ 7 | 8 | typedef unsigned int uint; 9 | 10 | /******************************************************************************/ 11 | /* M A C R O S */ 12 | /******************************************************************************/ 13 | 14 | /* Max and min functions */ 15 | 16 | #define MIN(a,b) (((a)<(b))?(a):(b)) 17 | #define MAX(a,b) (((a)>(b))?(a):(b)) 18 | 19 | /* the nuldelimiter of a string */ 20 | 21 | #define NUL3 '\n' 22 | 23 | #define OK 1 24 | #define NOK 0 25 | 26 | /* nullpointer is defined if not already done */ 27 | 28 | #ifndef NULL 29 | #define NULL (void *)0 30 | #endif 31 | 32 | /* define min and max for all types */ 33 | 34 | #define INT8_MAX 0x7F 35 | #define UINT8_MAX 0xFF 36 | #define INT16_MAX 0x7FFF 37 | #define UINT16_MAX 0xFFFF 38 | #define INT32_MAX 0x7FFFFFFF 39 | #define UINT32_MAX 0xFFFFFFFF 40 | #define FALSE 0 41 | #define TRUE !FALSE 42 | 43 | /******************************************************************************/ 44 | /* R E G I S T E R A C C E S S M A C R O S */ 45 | /******************************************************************************/ 46 | 47 | #define REG8(add) *((volatile unsigned char *) (add)) 48 | #define REG16(add) *((volatile unsigned short *) (add)) 49 | #define REG32(add) *((volatile unsigned long *) (add)) 50 | 51 | 52 | /******************************************************************************/ 53 | /* G C C C O M P I L E R */ 54 | /******************************************************************************/ 55 | 56 | #if defined (__GNUC__) 57 | 58 | //typedef unsigned char bool; 59 | 60 | typedef signed char int8; 61 | typedef signed short int16; 62 | typedef signed long int32; 63 | 64 | typedef unsigned char uint8; 65 | typedef unsigned short uint16; 66 | typedef unsigned long uint32; 67 | 68 | typedef unsigned char char8; 69 | typedef unsigned short char16; 70 | 71 | 72 | #else 73 | 74 | #error Undefined compiler used ! 75 | 76 | #endif 77 | 78 | #endif 79 | 80 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/out/dump.vmem: -------------------------------------------------------------------------------- 1 | /* out/rom.srec */ 2 | @00000000 B8080050 3 | @00000002 B808017C 4 | @00000004 B808018C 5 | @00000008 B8080184 6 | @00000014 31A004C0 304003B8 30200D30 B9F40014 80000000 B9F40140 30A30000 7 | @0000001B B8000000 2021FFEC F9E10000 20C004C0 20E004C0 06463800 BC720014 8 | @00000022 F8060000 20C60004 06463800 BC92FFF4 20C004C0 20E0053C 06463800 9 | @00000029 BC720014 F8060000 20C60004 06463800 BC92FFF4 B9F400E4 80000000 10 | @00000030 20C00000 20E00000 B9F40024 20A00000 32630000 B9F400C0 80000000 11 | @00000037 C9E10000 30730000 B60F0008 20210014 E8A003B8 E8E003C0 E94003C4 12 | @0000003E B00000F8 312004C0 B0001A00 31000000 30600001 F8650000 10C00000 13 | @00000045 E8650000 30800002 30630001 F8650000 10642000 F88304C0 30840002 14 | @0000004C AA44001E BE32FFF4 10642000 F90004C0 F9270000 BC26FFD0 E86A0000 15 | @00000053 A4C30001 BC26FFC4 E86A0000 A4C30001 BC26FFB8 B800FFE8 B8000008 16 | @0000005A 80000000 BE25FFFC 30A5FFFF B60F0008 80000000 B6110000 80000000 17 | @00000061 B6910000 80000000 B62E0000 80000000 B60F0008 80000000 B60F0008 18 | @00000068 80000000 3021FFE0 10C00000 FA61001C F9E10000 B9F40024 12650000 19 | @0000006F E8A003AC E8650028 BC03000C 99FC1800 80000000 B9F4FE9C 10B30000 20 | @00000076 E86003AC 3021FFC8 FB410030 FB610034 F9E10000 FA61001C FAC10020 21 | @0000007D FAE10024 FB010028 FB21002C EB030048 13650000 BE180050 13460000 22 | @00000084 E8780004 EB380088 3263FFFF BC53003C 64930402 30640008 12D81800 23 | @0000008B BE060074 12F92000 BC1900C0 E8770080 1643D000 BC1200EC 3273FFFF 24 | @00000092 32F7FFFC AA53FFFF BE32FFE8 32D6FFFC E9E10000 EA61001C EAC10020 25 | @00000099 EAE10024 EB010028 EB21002C EB410030 EB610034 B60F0008 30210038 26 | @000000A0 E8B70000 99FC3800 80000000 3273FFFF 32F7FFFC AA53FFFF BE12FFC0 27 | @000000A7 32D6FFFC E8780004 E8F60000 3063FFFF 16439800 BC120074 F8160000 28 | @000000AE BC07FFD4 BE190058 30800001 E8790100 44849C00 84641800 BC030044 29 | @000000B5 E8790104 84641800 BC23FFA4 E8D70000 99FC3800 10BB0000 B810FFA4 30 | @000000BC 3273FFFF 3273FFFF AA53FFFF BE12FF5C 3273FFFF AA53FFFF BE32FFF0 31 | @000000C3 3273FFFF B800FF48 99FC3800 3273FFFF B810FF78 32F7FFFC FA780004 32 | @000000CA B800FF90 E8780004 E8F60000 3063FFFF 16439800 BC120054 F8160000 33 | @000000D1 BC07FF00 BC190038 30800001 E8790100 44849C00 84641800 BC030024 34 | @000000D8 E8790104 84641800 BC230030 E8D70000 99FC3800 10BB0000 B810FED0 35 | @000000DF 3273FFFF 99FC3800 3273FFFF B810FEC4 32F7FFFC FA780004 B800FFB0 36 | @000000E6 E8B70000 99FC3800 3273FFFF B810FEA8 32F7FFFC 000003CC 4300FFFF 37 | @000000EE 41000000 40000000 40000004 40000008 000003CC 00000000 00000000 38 | @000000F5 00000000 00000000 00000000 00000000 00000000 00000000 000003B0 39 | @000000FC 00000000 00000000 00000000 00000000 00000000 00000000 00000000 40 | @00000103 00000000 00000000 00000000 00000000 00000000 00000000 00000000 41 | @0000010A 00000000 00000000 00000000 00000000 00000000 00000000 00000000 42 | @00000111 00000000 00000000 00000000 00000000 00000000 00000000 00000000 43 | @00000118 00000000 00000000 00000000 00000000 00000000 00000000 00000000 44 | @0000011F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 45 | @00000126 00000000 00000000 00000000 00000000 00000000 00000000 00000000 46 | @0000012D 00000000 00000000 47 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile/out/rom: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/an-fpga-implementation-of-low-latency-noc-based-mpsoc/3d72f1b026eeb6a47f23c81992718af315b342f6/noc_based_mpsoc/sw/compile/out/rom -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile_mpsoc: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | rm -Rf ram/*.mif 4 | rm -Rf ../simulation/modelsim/sw/ram/*.mif 5 | cd mpsoc_code 6 | for i in $(ls *.c); do 7 | echo item: $i 8 | cp $i ../compile/code.c 9 | cd ../compile 10 | ./gccrom code.c 11 | cp out/ram0.mif ../ram/${i%.*}.mif 12 | cp out/ram0.mif ../../simulation/modelsim/sw/ram/${i%.*}.mif 13 | rm code.c 14 | cd ../mpsoc_code 15 | done 16 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/compile_soc: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | rm -Rf ram/*.mif 4 | rm -Rf ../simulation/modelsim/sw/ram/*.mif 5 | cd soc_code 6 | cp soc.c ../compile/code.c 7 | cd ../compile 8 | ./gccrom code.c 9 | cp out/ram0.mif ../ram/cpu00_00.mif 10 | cp out/ram0.mif ../../simulation/modelsim/sw/ram/cpu00_00.mif 11 | rm code.c 12 | cd ../soc_code 13 | 14 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu00_00.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | 4 | #include "system.h" 5 | 6 | 7 | 8 | 9 | #define EXT_INT_1 (1<<0) 10 | #define EXT_INT_2 (1<<1) 11 | #define EXT_INT_3 (1<<2) 12 | 13 | 14 | 15 | const unsigned int seven_seg_tab [16] = {0x3F,0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x6F,0x77,0x7C,0x39,0x5E, 0x79,0x71}; 16 | 17 | void delay(unsigned int); 18 | void ni_ISR ( void ); 19 | void timer_ISR( void ); 20 | void ext_int_ISR( void ); 21 | 22 | /*! 23 | * Assembly macro to enable MSR_IE 24 | */ 25 | void aemb_enable_interrupt () 26 | { 27 | int msr, tmp; 28 | asm volatile ("mfs %0, rmsr;" 29 | "ori %1, %0, 0x02;" 30 | "mts rmsr, %1;" 31 | : "=r"(msr) 32 | : "r" (tmp) 33 | ); 34 | } 35 | 36 | 37 | void myISR( void ) __attribute__ ((interrupt_handler)); 38 | 39 | 40 | unsigned int i=0; 41 | 42 | void myISR( void ) 43 | { 44 | if( INTC_IPR & NI_INT ) ni_ISR(); 45 | if( INTC_IPR & TIMER_INT ) timer_ISR(); 46 | if( INTC_IPR & EXT_INT) ext_int_ISR(); 47 | INTC_IAR = INTC_IPR; // Acknowledge Interrupts 48 | } 49 | 50 | 51 | void timer_ISR( void ) 52 | { 53 | // Do Stuff Here 54 | i++; 55 | TCSR0 = TCSR0; 56 | // Acknogledge Interrupt In Timer (Clear pending bit) 57 | } 58 | 59 | 60 | 61 | void ext_int_ISR( void ) 62 | { 63 | // Do Stuff Here 64 | if(EXT_INT_ISR & EXT_INT_1) i=0xDEADBEAF; 65 | if(EXT_INT_ISR & EXT_INT_2) i=0x12345678; 66 | if(EXT_INT_ISR & EXT_INT_3) i=0xAAAAAAAA; 67 | EXT_INT_ISR = EXT_INT_ISR; 68 | // Clear any pending button interrupts 69 | } 70 | 71 | unsigned int ni_buffer [32]; 72 | 73 | void ni_ISR( void ) 74 | { 75 | // Do Stuff Here 76 | save_pck (ni_buffer, 32); 77 | i += 0x11111111; 78 | NIC_ST = NIC_ST; 79 | 80 | // Clear any pending button interrupts 81 | } 82 | 83 | 84 | int main() 85 | { 86 | unsigned int j,hex_val; 87 | i=0; 88 | 89 | 90 | 91 | 92 | EXT_INT_IER_RISE = EXT_INT_1 | EXT_INT_2 | EXT_INT_3; 93 | EXT_INT_GER = 0x3; 94 | 95 | TCMP0 = 50000000; 96 | TCSR0 = ( TIMER_EN | TIMER_INT_EN | TIMER_RST_ON_CMP); 97 | 98 | INTC_IER= EXT_INT | TIMER_INT | NI_INT; 99 | INTC_MER= 0x3; 100 | 101 | 102 | 103 | aemb_enable_interrupt (); 104 | while(1) 105 | { 106 | for(j=0;j<8;j++) 107 | { 108 | hex_val = (i>>(j*4))&0xF; 109 | gpio_o_wr(j,~seven_seg_tab[hex_val]); 110 | } 111 | 112 | delay(50000); 113 | }//while 114 | return 0; 115 | 116 | 117 | 118 | } 119 | 120 | 121 | 122 | 123 | void delay ( unsigned int num ){ 124 | 125 | while (num>0){ 126 | num--; 127 | asm volatile ("nop"); 128 | } 129 | return; 130 | 131 | } 132 | 133 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu00_01.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | #define BUFFER_SIZE 31 6 | 7 | unsigned int buffer [BUFFER_SIZE]; 8 | 9 | #define DES_X 2 10 | #define DES_Y 1 11 | 12 | 13 | void delay(unsigned int); 14 | 15 | 16 | 17 | 18 | 19 | 20 | int main() 21 | { 22 | unsigned int status=0; 23 | int i; 24 | 25 | while(1){ 26 | for (i=1;i0){ 42 | num--; 43 | asm volatile ("nop"); 44 | } 45 | return; 46 | 47 | } 48 | 49 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu00_02.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | 10 | 11 | 12 | 13 | int main() 14 | { 15 | int blk,i,pass=1; 16 | unsigned int buffer[18]; 17 | while(1) 18 | { 19 | //gpio_o_wr(0,1); 20 | //delay(1000000); 21 | //gpio_o_wr(0,0); 22 | //delay(1000000); 23 | for(blk=0; blk<4;blk++){ 24 | for(i=0;i<16;i++){ 25 | buffer[i+2]= (blk+1)*i; 26 | } 27 | write_on_ram_with_ack(buffer,blk*16,16); 28 | 29 | } 30 | for(blk=0; blk<4;blk++){ 31 | read_from_ram(buffer,blk*16,16); 32 | for(i=0;i<16;i++){ 33 | if(buffer[i+1] != (blk+1)*i) pass=0; 34 | } 35 | } 36 | 37 | gpio_o_wr(0,pass); 38 | 39 | 40 | while(1); 41 | 42 | }//while 43 | return 0; 44 | } 45 | 46 | 47 | 48 | 49 | void delay ( unsigned int num ){ 50 | 51 | while (num>0){ 52 | num--; 53 | asm volatile ("nop"); 54 | } 55 | return; 56 | 57 | } 58 | 59 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu00_03.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(50000); 16 | gpio_o_wr(0,0); 17 | delay(50000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu01_00.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | unsigned int buffer [32]; 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | int main() 20 | { 21 | int i; 22 | for (i=1;i<32;i++) buffer [i] = i; 23 | for (i=1;i<32;i++) { 24 | delay(5000000); 25 | send_pck (0,0,buffer,30,0x00); 26 | wait_for_sending_pck(); 27 | delay(50000000); 28 | send_pck (0,0,buffer,31,0x00); 29 | wait_for_sending_pck(); 30 | } 31 | while(1) 32 | { 33 | gpio_o_wr(0,1); 34 | delay(500000); 35 | 36 | 37 | 38 | gpio_o_wr(0,0); 39 | delay(500000); 40 | }//while 41 | return 0; 42 | } 43 | 44 | 45 | 46 | 47 | void delay ( unsigned int num ){ 48 | 49 | while (num>0){ 50 | num--; 51 | asm volatile ("nop"); 52 | } 53 | return; 54 | 55 | } 56 | 57 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu01_01.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(5000000); 16 | gpio_o_wr(0,0); 17 | delay(5000000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu01_02.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(3000000); 16 | gpio_o_wr(0,0); 17 | delay(3000000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu01_03.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(50000); 16 | gpio_o_wr(0,0); 17 | delay(50000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu02_00.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(200000); 16 | gpio_o_wr(0,0); 17 | delay(200000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu02_01.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | #define BUFFER_SIZE 31 6 | 7 | void delay(unsigned int); 8 | 9 | unsigned int buffer [BUFFER_SIZE]; 10 | 11 | 12 | 13 | 14 | int main(void){ 15 | 16 | 17 | unsigned int status=0; 18 | 19 | 20 | while(1){ 21 | wait_for_getting_pck(); 22 | save_pck (buffer,BUFFER_SIZE); 23 | 24 | } 25 | return 0; 26 | } 27 | 28 | 29 | 30 | 31 | void delay ( unsigned int num ){ 32 | 33 | while (num>0){ 34 | num--; 35 | asm volatile ("nop"); 36 | } 37 | return; 38 | 39 | } 40 | 41 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu02_02.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(50000); 16 | gpio_o_wr(0,0); 17 | delay(50000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu02_03.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(50000); 16 | gpio_o_wr(0,0); 17 | delay(50000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu03_00.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(50000); 16 | gpio_o_wr(0,0); 17 | delay(50000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu03_01.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | #define BUFFER_SIZE 31 6 | void delay(unsigned int); 7 | 8 | unsigned int buffer [BUFFER_SIZE]; 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | int main(void){ 20 | 21 | 22 | unsigned int status=0; 23 | 24 | 25 | while(1){ 26 | wait_for_getting_pck(); 27 | save_pck (buffer,BUFFER_SIZE); 28 | 29 | } 30 | return 0; 31 | } 32 | 33 | 34 | 35 | 36 | 37 | void delay ( unsigned int num ){ 38 | 39 | while (num>0){ 40 | num--; 41 | asm volatile ("nop"); 42 | } 43 | return; 44 | 45 | } 46 | 47 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu03_02.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(50000); 16 | gpio_o_wr(0,0); 17 | delay(50000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/cpu03_03.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | #include "system.h" 4 | 5 | 6 | void delay(unsigned int); 7 | 8 | 9 | int main() 10 | { 11 | 12 | while(1) 13 | { 14 | gpio_o_wr(0,1); 15 | delay(50000); 16 | gpio_o_wr(0,0); 17 | delay(50000); 18 | }//while 19 | return 0; 20 | } 21 | 22 | 23 | 24 | 25 | void delay ( unsigned int num ){ 26 | 27 | while (num>0){ 28 | num--; 29 | asm volatile ("nop"); 30 | } 31 | return; 32 | 33 | } 34 | 35 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/mpsoc_code/do: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | for x in 0 1 2 3 ; do 3 | for y in 0 1 2 3; do 4 | echo "cpu0${x}_0$y.c" 5 | rm cpu0$x_$y.c 6 | cp cpu.c "cpu0${x}_0$y.c" 7 | done 8 | done 9 | 10 | # echo item: cpu0$x$y.c 11 | #cp cpu00_001.c cpu0$x_$y.c 12 | #done 13 | 14 | 15 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/prog_memories: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | cd tcl 3 | quartus_stp -t prog.tcl 4 | cd .. 5 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/soc_code/soc.c: -------------------------------------------------------------------------------- 1 | #include "orsocdef.h" 2 | #include 3 | 4 | #include "system.h" 5 | 6 | 7 | 8 | 9 | #define EXT_INT_1 (1<<0) 10 | #define EXT_INT_2 (1<<1) 11 | #define EXT_INT_3 (1<<2) 12 | 13 | 14 | 15 | const unsigned int seven_seg_tab [16] = {0x3F,0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x6F,0x77,0x7C,0x39,0x5E, 0x79,0x71}; 16 | 17 | void delay(unsigned int); 18 | void ni_ISR ( void ); 19 | void timer_ISR( void ); 20 | void ext_int_ISR( void ); 21 | 22 | /*! 23 | * Assembly macro to enable MSR_IE 24 | */ 25 | void aemb_enable_interrupt () 26 | { 27 | int msr, tmp; 28 | asm volatile ("mfs %0, rmsr;" 29 | "ori %1, %0, 0x02;" 30 | "mts rmsr, %1;" 31 | : "=r"(msr) 32 | : "r" (tmp) 33 | ); 34 | } 35 | 36 | 37 | void myISR( void ) __attribute__ ((interrupt_handler)); 38 | 39 | 40 | unsigned int i; 41 | 42 | void myISR( void ) 43 | { 44 | if( INTC_IPR & NI_INT ) ni_ISR(); 45 | if( INTC_IPR & TIMER_INT ) timer_ISR(); 46 | if( INTC_IPR & EXT_INT) ext_int_ISR(); 47 | INTC_IAR = INTC_IPR; // Acknowledge Interrupts 48 | } 49 | 50 | 51 | void timer_ISR( void ) 52 | { 53 | // Do Stuff Here 54 | i++; 55 | TCSR0 = TCSR0; 56 | // Acknogledge Interrupt In Timer (Clear pending bit) 57 | } 58 | 59 | 60 | 61 | void ext_int_ISR( void ) 62 | { 63 | // Do Stuff Here 64 | if(EXT_INT_ISR & EXT_INT_1) i=0xDEADBEAF; 65 | if(EXT_INT_ISR & EXT_INT_2) i=0x12345678; 66 | if(EXT_INT_ISR & EXT_INT_3) i=0xAAAAAAAA; 67 | EXT_INT_ISR = EXT_INT_ISR; 68 | // Clear any pending button interrupts 69 | } 70 | 71 | unsigned int ni_buffer [32]; 72 | 73 | void ni_ISR( void ) 74 | { 75 | // Do Stuff Here 76 | save_pck (ni_buffer, 32); 77 | NIC_ST = NIC_ST; 78 | // Clear any pending button interrupts 79 | } 80 | 81 | 82 | int main() 83 | { 84 | unsigned int j,hex_val; 85 | i=0; 86 | 87 | 88 | 89 | 90 | EXT_INT_IER_RISE=EXT_INT_1 | EXT_INT_2 | EXT_INT_3; 91 | EXT_INT_GER = 0x3; 92 | 93 | TCMP0 = 50000000; 94 | TCSR0 = ( TIMER_EN | TIMER_INT_EN | TIMER_RST_ON_CMP); 95 | 96 | INTC_IER= EXT_INT | TIMER_INT; 97 | INTC_MER= 0x3; 98 | 99 | 100 | 101 | aemb_enable_interrupt (); 102 | while(1) 103 | { 104 | for(j=0;j<8;j++) 105 | { 106 | hex_val = (i>>(j*4))&0xF; 107 | gpio_o_wr(j,~seven_seg_tab[hex_val]); 108 | } 109 | 110 | delay(50000); 111 | }//while 112 | return 0; 113 | 114 | 115 | 116 | } 117 | 118 | 119 | 120 | 121 | void delay ( unsigned int num ){ 122 | 123 | while (num>0){ 124 | num--; 125 | asm volatile ("nop"); 126 | } 127 | return; 128 | 129 | } 130 | 131 | -------------------------------------------------------------------------------- /noc_based_mpsoc/sw/tcl/prog.tcl: -------------------------------------------------------------------------------- 1 | #/usr/bin/tclsh 2 | 3 | proc hold_reset {} { 4 | global device_name usb 5 | start_insystem_source_probe -device_name $device_name -hardware_name $usb 6 | write_source_data -instance_index 127 -value 0x1 -value_in_hex 7 | end_insystem_source_probe 8 | } 9 | 10 | proc release_reset {} { 11 | global device_name usb 12 | start_insystem_source_probe -device_name $device_name -hardware_name $usb 13 | write_source_data -instance_index 127 -value 0x0 -value_in_hex 14 | end_insystem_source_probe 15 | } 16 | 17 | ## Setup USB hardware - assumes only USB Blaster is installed and 18 | ## an FPGA is the only device in the JTAG chain 19 | set usb [lindex [get_hardware_names] 0] 20 | set device_name [lindex [get_device_names -hardware_name $usb] 0] 21 | 22 | puts $usb 23 | puts $device_name 24 | 25 | #reset all processors 26 | hold_reset 27 | 28 | 29 | # Initiate a editing sequence 30 | begin_memory_edit -hardware_name $usb -device_name $device_name 31 | 32 | foreach instance \ 33 | [get_editable_mem_instances -hardware_name $usb -device_name $device_name] { 34 | set inst_name [lindex $instance 5] 35 | set inst_index [lindex $instance 0] 36 | #puts $inst_name 37 | #puts $inst_index 38 | set xx [string range $inst_name 0 1] 39 | set yy [string range $inst_name 2 end] 40 | #puts $xx 41 | #puts $yy 42 | set ram_file_name ../ram/cpu${xx}_${yy}.mif 43 | 44 | #update prog memory 45 | if {[file exists $ram_file_name] == 1} { 46 | puts "memory ${inst_name} is programed with $ram_file_name" 47 | update_content_to_memory_from_file -instance_index $inst_index -mem_file_path $ram_file_name -mem_file_type mif 48 | } 49 | 50 | } 51 | 52 | 53 | 54 | 55 | #set xx 0 56 | #set yy 0 57 | # for {set yy 0} {$yy<$Y_NODE_NUM} {incr yy} { 58 | # for {set xx 0} {$xx<$X_NODE_NUM} {incr xx} { 59 | # set ram_file_name [format "ram/cpu%02d_%02d.mif" $xx $yy] 60 | # set mem_index [format "%02d%02d" $xx $yy] 61 | 62 | #update prog memory 63 | # update_content_to_memory_from_file -instance_index $mem_index -mem_file_path $ram_file_name -mem_file_type mif 64 | 65 | #puts $ram_file_name\n 66 | #puts $mem_index\n 67 | 68 | # }} 69 | 70 | 71 | 72 | 73 | 74 | #End the editing sequence 75 | end_memory_edit 76 | 77 | #release reset 78 | release_reset 79 | --------------------------------------------------------------------------------