├── README.txt ├── doc └── PR200_trm_rev1.6.pdf └── src ├── dma_axi32 ├── README.txt ├── dma_axi32.v ├── dma_axi32_apb_mux.v ├── dma_axi32_ch_reg_params.v ├── dma_axi32_core0.v ├── dma_axi32_core0_arbiter.v ├── dma_axi32_core0_axim_cmd.v ├── dma_axi32_core0_axim_rd.v ├── dma_axi32_core0_axim_rdata.v ├── dma_axi32_core0_axim_resp.v ├── dma_axi32_core0_axim_timeout.v ├── dma_axi32_core0_axim_wdata.v ├── dma_axi32_core0_axim_wr.v ├── dma_axi32_core0_ch.v ├── dma_axi32_core0_ch_calc.v ├── dma_axi32_core0_ch_calc_addr.v ├── dma_axi32_core0_ch_calc_joint.v ├── dma_axi32_core0_ch_calc_size.v ├── dma_axi32_core0_ch_empty.v ├── dma_axi32_core0_ch_fifo.v ├── dma_axi32_core0_ch_fifo_ctrl.v ├── dma_axi32_core0_ch_fifo_ptr.v ├── dma_axi32_core0_ch_offsets.v ├── dma_axi32_core0_ch_outs.v ├── dma_axi32_core0_ch_periph_mux.v ├── dma_axi32_core0_ch_rd_slicer.v ├── dma_axi32_core0_ch_reg.v ├── dma_axi32_core0_ch_reg_size.v ├── dma_axi32_core0_ch_remain.v ├── dma_axi32_core0_ch_wr_slicer.v ├── dma_axi32_core0_channels.v ├── dma_axi32_core0_channels_apb_mux.v ├── dma_axi32_core0_channels_mux.v ├── dma_axi32_core0_ctrl.v ├── dma_axi32_core0_top.v ├── dma_axi32_core0_wdt.v ├── dma_axi32_defines.v ├── dma_axi32_dual_core.v ├── dma_axi32_reg.v ├── dma_axi32_reg_core0.v ├── dma_axi32_reg_params.v ├── filelist.txt ├── prgen_delay.v ├── prgen_demux8.v ├── prgen_fifo.v ├── prgen_joint_stall.v ├── prgen_min2.v ├── prgen_min3.v ├── prgen_mux8.v ├── prgen_or8.v ├── prgen_rawstat.v ├── prgen_scatter8_1.v ├── prgen_stall.v └── prgen_swap_32.v └── dma_axi64 ├── README.txt ├── dma_axi64.v ├── dma_axi64_apb_mux.v ├── dma_axi64_ch_reg_params.v ├── dma_axi64_core0.v ├── dma_axi64_core0_arbiter.v ├── dma_axi64_core0_axim_cmd.v ├── dma_axi64_core0_axim_rd.v ├── dma_axi64_core0_axim_rdata.v ├── dma_axi64_core0_axim_resp.v ├── dma_axi64_core0_axim_timeout.v ├── dma_axi64_core0_axim_wdata.v ├── dma_axi64_core0_axim_wr.v ├── dma_axi64_core0_ch.v ├── dma_axi64_core0_ch_calc.v ├── dma_axi64_core0_ch_calc_addr.v ├── dma_axi64_core0_ch_calc_joint.v ├── dma_axi64_core0_ch_calc_size.v ├── dma_axi64_core0_ch_empty.v ├── dma_axi64_core0_ch_fifo.v ├── dma_axi64_core0_ch_fifo_ctrl.v ├── dma_axi64_core0_ch_fifo_ptr.v ├── dma_axi64_core0_ch_offsets.v ├── dma_axi64_core0_ch_outs.v ├── dma_axi64_core0_ch_periph_mux.v ├── dma_axi64_core0_ch_rd_slicer.v ├── dma_axi64_core0_ch_reg.v ├── dma_axi64_core0_ch_reg_size.v ├── dma_axi64_core0_ch_remain.v ├── dma_axi64_core0_ch_wr_slicer.v ├── dma_axi64_core0_channels.v ├── dma_axi64_core0_channels_apb_mux.v ├── dma_axi64_core0_channels_mux.v ├── dma_axi64_core0_ctrl.v ├── dma_axi64_core0_top.v ├── dma_axi64_core0_wdt.v ├── dma_axi64_defines.v ├── dma_axi64_dual_core.v ├── dma_axi64_reg.v ├── dma_axi64_reg_core0.v ├── dma_axi64_reg_params.v ├── filelist.txt ├── prgen_delay.v ├── prgen_demux8.v ├── prgen_fifo.v ├── prgen_joint_stall.v ├── prgen_min2.v ├── prgen_min3.v ├── prgen_mux8.v ├── prgen_or8.v ├── prgen_rawstat.v ├── prgen_scatter8_1.v ├── prgen_stall.v ├── prgen_swap_32.v └── prgen_swap_64.v /README.txt: -------------------------------------------------------------------------------- 1 | 2 | ------------------------------ Remark ---------------------------------------- 3 | We will be very happy to receive any kind of feedback regarding our tools and cores. 4 | We will also be willing to support any company intending to integrate our cores into their project. 5 | For any questions / remarks / suggestions / bugs please contact info@provartec.com. 6 | ------------------------------------------------------------------------------ 7 | 8 | Opencores.org project - DMA AXI 9 | 10 | This core is based on the Provartec PR200 IP - 'Generic High performance dual-core AXI DMA' 11 | 12 | The original IP is a configurable, generic AXI DMA written in RobustVerilog. 13 | 14 | This project contains two Verilog cores, one a 32-bit build and the other a 64-bit build. 15 | 16 | To view the complete IP - http://www.provartec.com/ipproducts/56 17 | -------------------------------------------------------------------------------- /doc/PR200_trm_rev1.6.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/dma_axi/bdd0b77559c6410b0a48799026453e3a9fd7b0d3/doc/PR200_trm_rev1.6.pdf -------------------------------------------------------------------------------- /src/dma_axi32/README.txt: -------------------------------------------------------------------------------- 1 | 2 | Opencores.org project - DMA AXI - 32 bit build 3 | 4 | This core is based on the Provartec PR200 IP - 'Generic High performance dual-core AXI DMA' 5 | 6 | Build with the following parameters: 7 | - Single channel 8 | - Single interrupt bit 9 | - One AXI port (simultaneous read and write) 10 | - AXI data 32 bits 11 | - data FIFO 32 bytes 12 | - AXI address bits 32 13 | - AXI outstanding write commands - 2 14 | - AXI outstanding read commands - 2 15 | - Block support - no 16 | - Scheduler - no 17 | - Priority modes - no 18 | - Joint mode - yes 19 | - Independent mode - yes 20 | - Outstanding mode - no 21 | - Tokens - yes 22 | - AHB timeout - yes 23 | - Watchdog timer - yes 24 | - Peripheral control - yes 25 | - Command lists - yes 26 | - Endianess support - yes 27 | 28 | To view the complete IP - http://www.provartec.com/ipproducts/56 29 | For any questions / remarks / suggestions / bugs please contact info@provartec.com. 30 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_apb_mux.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:50 2011 33 | //-- 34 | //-- Source file: dma_apb_mux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_apb_mux (clk,reset,pclken,psel,penable,pwrite,paddr,prdata,pslverr,pready,psel0,prdata0,pslverr0,psel1,prdata1,pslverr1,psel_reg,prdata_reg,pslverr_reg); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input pclken; 45 | input psel; 46 | input penable; 47 | input pwrite; 48 | input [12:11] paddr; 49 | output [31:0] prdata; 50 | output pslverr; 51 | output pready; 52 | 53 | output psel0; 54 | input [31:0] prdata0; 55 | input pslverr0; 56 | 57 | output psel1; 58 | input [31:0] prdata1; 59 | input pslverr1; 60 | 61 | output psel_reg; 62 | input [31:0] prdata_reg; 63 | input pslverr_reg; 64 | 65 | wire [31:0] prdata_pre; 66 | wire pslverr_pre; 67 | 68 | 69 | reg pready; 70 | 71 | 72 | assign psel0 = pclken & psel & (paddr[12:11] == 2'b00); 73 | assign psel1 = pclken & psel & (paddr[12:11] == 2'b01); 74 | assign psel_reg = pclken & psel & (paddr[12] == 1'b1); 75 | 76 | assign prdata_pre = prdata0 | prdata1 | prdata_reg; 77 | assign pslverr_pre = pslverr0 | pslverr1 | pslverr_reg; 78 | 79 | assign prdata = prdata_pre; 80 | assign pslverr = pslverr_pre; 81 | 82 | 83 | always @(posedge clk or posedge reset) 84 | if (reset) 85 | pready <= #1 1'b0; 86 | else if (pclken) 87 | pready <= #1 psel & (~penable); 88 | 89 | 90 | endmodule 91 | 92 | 93 | 94 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_ch_reg_params.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: dma_ch_reg_params.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | parameter CMD_LINE0 = 8'h00; 40 | parameter CMD_LINE1 = 8'h04; 41 | parameter CMD_LINE2 = 8'h08; 42 | parameter CMD_LINE3 = 8'h0C; 43 | parameter STATIC_LINE0 = 8'h10; 44 | parameter STATIC_LINE1 = 8'h14; 45 | parameter STATIC_LINE2 = 8'h18; 46 | parameter STATIC_LINE3 = 8'h1C; 47 | parameter STATIC_LINE4 = 8'h20; 48 | 49 | parameter RESTRICT = 8'h2C; 50 | parameter RD_OFFSETS = 8'h30; 51 | parameter WR_OFFSETS = 8'h34; 52 | parameter FIFO_FULLNESS = 8'h38; 53 | parameter CMD_OUTS = 8'h3C; 54 | 55 | parameter CH_ENABLE = 8'h40; 56 | parameter CH_START = 8'h44; 57 | parameter CH_ACTIVE = 8'h48; 58 | parameter CH_CMD_COUNTER = 8'h50; 59 | 60 | parameter INT_RAWSTAT = 8'hA0; 61 | parameter INT_CLEAR = 8'hA4; 62 | parameter INT_ENABLE = 8'hA8; 63 | parameter INT_STATUS = 8'hAC; 64 | 65 | 66 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_arbiter.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:51 2011 33 | //-- 34 | //-- Source file: dma_core_arbiter.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_arbiter(clk,reset,enable,joint_mode,page_cross,joint_req,prio_top,prio_high,prio_top_num,prio_high_num,hold,ch_ready,ch_active,finish,ch_go_out,ch_num,ch_last); 40 | 41 | parameter CH_LAST = 1-1; 42 | 43 | input clk; 44 | input reset; 45 | 46 | input enable; 47 | 48 | input joint_mode; 49 | input page_cross; 50 | input joint_req; 51 | input prio_top; 52 | input prio_high; 53 | input [2:0] prio_top_num; 54 | input [2:0] prio_high_num; 55 | input hold; 56 | 57 | input [7:0] ch_ready; 58 | input [7:0] ch_active; 59 | input finish; 60 | output ch_go_out; 61 | output [2:0] ch_num; 62 | output ch_last; 63 | 64 | 65 | 66 | reg [7:0] current_active; 67 | wire current_ready_only; 68 | wire ch_last_pre; 69 | wire ch_last; 70 | wire ready; 71 | wire next_ready; 72 | wire next_ready0; 73 | wire next_ready1; 74 | wire prio_top_ready; 75 | wire prio_high_ready; 76 | reg in_prog; 77 | wire ch_go_pre; 78 | wire ch_go_pre_d; 79 | wire ch_go_top_pre; 80 | wire ch_go_high_pre; 81 | wire ch_go; 82 | wire ch_go_d; 83 | wire ch_go_top; 84 | wire ch_go_high; 85 | wire ch_go_next; 86 | wire hold_d; 87 | wire advance_next; 88 | wire [2:0] ch_num_pre; 89 | wire [3:0] next_ch_num0_pre; 90 | wire [3:0] next_ch_num0_pre2; 91 | wire [2:0] next_ch_num0; 92 | wire [3:0] next_ch_num1_pre; 93 | wire [3:0] next_ch_num1_pre2; 94 | wire [2:0] next_ch_num1; 95 | wire [2:0] next_ch_num_pre; 96 | 97 | assign ch_go_out = 'd1; 98 | assign ch_num = 'd0; 99 | assign ch_last = 'd1; 100 | 101 | 102 | 103 | endmodule 104 | 105 | 106 | 107 | 108 | 109 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_axim_rdata.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:52 2011 33 | //-- 34 | //-- Source file: dma_core_axim_rdata.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_axim_rdata(clk,reset,joint_stall,ch_fifo_wr,ch_fifo_wdata,ch_fifo_wsize,ch_fifo_wr_num,rd_transfer_num,rd_transfer,rd_transfer_size,rd_burst_cmd,load_wr,load_wr_num,load_wr_cycle,load_wdata,rd_clr_line,rd_clr_line_num,ARVALID,ARREADY,ARID,RID,RDATA,RLAST,RVALID,RREADY,RREADY_out); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input joint_stall; 45 | 46 | output ch_fifo_wr; 47 | output [32-1:0] ch_fifo_wdata; 48 | output [3-1:0] ch_fifo_wsize; 49 | output [2:0] ch_fifo_wr_num; 50 | output [2:0] rd_transfer_num; 51 | output rd_transfer; 52 | input [3-1:0] rd_transfer_size; 53 | output rd_burst_cmd; 54 | output load_wr; 55 | output [2:0] load_wr_num; 56 | output [1:0] load_wr_cycle; 57 | output [32-1:0] load_wdata; 58 | output rd_clr_line; 59 | output [2:0] rd_clr_line_num; 60 | 61 | input ARVALID; 62 | input ARREADY; 63 | input [`CMD_BITS-1:0] ARID; 64 | input [`CMD_BITS-1:0] RID; 65 | input [32-1:0] RDATA; 66 | input RLAST; 67 | input RVALID; 68 | input RREADY; 69 | output RREADY_out; 70 | 71 | 72 | reg [1:0] load_wr_cycle; 73 | wire load_cmd_id; 74 | wire rd_clr_line_pre; 75 | wire rd_clr_line_pre_d; 76 | reg [2:0] ch_fifo_wr_num_d; 77 | reg [2:0] rd_clr_line_num; 78 | 79 | 80 | 81 | 82 | 83 | assign load_cmd_id = RID[3]; 84 | 85 | assign RREADY_out = (~rd_clr_line_pre) & (~rd_clr_line_pre_d) & (~joint_stall); 86 | 87 | assign rd_transfer_num = RID[2:0]; 88 | 89 | assign rd_transfer = RVALID & RREADY & (~load_cmd_id); 90 | 91 | assign rd_burst_cmd = rd_transfer & RID[5]; 92 | 93 | assign ch_fifo_wr = rd_transfer; 94 | 95 | assign ch_fifo_wdata = RDATA; 96 | 97 | assign ch_fifo_wsize = rd_transfer_size; 98 | 99 | assign ch_fifo_wr_num = RID[2:0]; 100 | 101 | 102 | assign rd_clr_line_pre = RVALID & RREADY & RLAST & RID[6] & (~RID[3]); 103 | 104 | prgen_delay #(1) delay_clr(.clk(clk), .reset(reset), .din(rd_clr_line_pre), .dout(rd_clr_line_pre_d)); 105 | prgen_delay #(1) delay_clr2(.clk(clk), .reset(reset), .din(rd_clr_line_pre_d), .dout(rd_clr_line)); 106 | 107 | always @(posedge clk or posedge reset) 108 | if (reset) 109 | ch_fifo_wr_num_d <= #1 3'b000; 110 | else if (rd_clr_line_pre) 111 | ch_fifo_wr_num_d <= #1 ch_fifo_wr_num; 112 | 113 | always @(posedge clk or posedge reset) 114 | if (reset) 115 | rd_clr_line_num <= #1 3'b000; 116 | else if (rd_clr_line_pre_d) 117 | rd_clr_line_num <= #1 ch_fifo_wr_num_d; 118 | 119 | assign load_wr = RVALID & RREADY & load_cmd_id; 120 | 121 | assign load_wr_num = RID[2:0]; 122 | 123 | assign load_wdata = RDATA; 124 | 125 | 126 | always @(posedge clk or posedge reset) 127 | if (reset) 128 | load_wr_cycle <= #1 2'b00; 129 | else if (load_wr & load_wr_cycle[0] & 1'b0) 130 | load_wr_cycle <= #1 2'b00; 131 | else if (load_wr) 132 | load_wr_cycle <= #1 load_wr_cycle + 1'b1; 133 | 134 | 135 | 136 | 137 | endmodule 138 | 139 | 140 | 141 | 142 | 143 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_axim_resp.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:52 2011 33 | //-- 34 | //-- Source file: dma_core_axim_resp.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_axim_resp(clk,reset,slverr,decerr,clr,clr_last,ch_num_resp,resp_full,AID,AVALID,AREADY,RESP,ID,VALID,READY,LAST); 40 | 41 | parameter CMD_DEPTH = 8; 42 | 43 | input clk; 44 | input reset; 45 | 46 | output slverr; 47 | output decerr; 48 | output clr; 49 | output clr_last; 50 | output [2:0] ch_num_resp; 51 | output resp_full; 52 | 53 | 54 | input [`CMD_BITS-1:0] AID; 55 | input AVALID; 56 | input AREADY; 57 | input [1:0] RESP; 58 | output [`CMD_BITS-1:0] ID; 59 | input VALID; 60 | input READY; 61 | input LAST; 62 | 63 | 64 | 65 | parameter RESP_SLVERR = 2'b10; 66 | parameter RESP_DECERR = 2'b11; 67 | 68 | 69 | wire clr_pre; 70 | wire [2:0] ch_num_resp_pre; 71 | wire clr_last_pre; 72 | wire slverr_pre; 73 | wire decerr_pre; 74 | reg [2:0] ch_num_resp; 75 | 76 | wire resp_push; 77 | wire resp_pop; 78 | wire resp_empty; 79 | wire resp_full; 80 | wire [`CMD_BITS-1:0] ID; 81 | 82 | 83 | assign resp_push = AVALID & AREADY; 84 | assign resp_pop = VALID & READY & LAST; 85 | 86 | assign clr_pre = resp_pop; 87 | 88 | assign ch_num_resp_pre = ID[2:0] ; 89 | 90 | assign slverr_pre = clr_pre & RESP == RESP_SLVERR; 91 | assign decerr_pre = clr_pre & RESP == RESP_DECERR; 92 | 93 | assign clr_last_pre = clr_pre & ID[3]; 94 | 95 | prgen_delay #(1) delay_clr(.clk(clk), .reset(reset), .din(clr_pre), .dout(clr)); 96 | prgen_delay #(1) delay_clr_last(.clk(clk), .reset(reset), .din(clr_last_pre), .dout(clr_last)); 97 | prgen_delay #(1) delay_slverr(.clk(clk), .reset(reset), .din(slverr_pre), .dout(slverr)); 98 | prgen_delay #(1) delay_decerr(.clk(clk), .reset(reset), .din(decerr_pre), .dout(decerr)); 99 | 100 | always @(posedge clk or posedge reset) 101 | if (reset) 102 | ch_num_resp <= #1 3'b000; 103 | else if (clr_pre) 104 | ch_num_resp <= #1 ch_num_resp_pre; 105 | 106 | 107 | 108 | prgen_fifo #(`CMD_BITS, CMD_DEPTH) 109 | resp_fifo( 110 | .clk(clk), 111 | .reset(reset), 112 | .push(resp_push), 113 | .pop(resp_pop), 114 | .din(AID), 115 | .dout(ID), 116 | .empty(resp_empty), 117 | .full(resp_full) 118 | ); 119 | 120 | 121 | endmodule 122 | 123 | 124 | 125 | 126 | 127 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_axim_timeout.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:52 2011 33 | //-- 34 | //-- Source file: dma_core_axim_timeout.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_axim_timeout(clk,reset,VALID,READY,ID,axim_timeout_num,axim_timeout); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input VALID; 45 | input READY; 46 | input [`CMD_BITS-1:0] ID; 47 | 48 | output [2:0] axim_timeout_num; 49 | output axim_timeout; 50 | 51 | 52 | 53 | reg [`TIMEOUT_BITS-1:0] counter; 54 | 55 | 56 | assign axim_timeout_num = ID[2:0]; 57 | 58 | assign axim_timeout = (counter == 'd0); 59 | 60 | 61 | always @(posedge clk or posedge reset) 62 | if (reset) 63 | counter <= #1 {`TIMEOUT_BITS{1'b1}}; 64 | else if (VALID & READY) 65 | counter <= #1 {`TIMEOUT_BITS{1'b1}}; 66 | else if (VALID) 67 | counter <= #1 counter - 1'b1; 68 | 69 | 70 | 71 | endmodule 72 | 73 | 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_ch_calc_addr.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: dma_ch_calc_addr.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_ch_calc_addr(clk,reset,ch_update_d,load_in_prog,load_addr,go_next_line,burst_start,incr,start_addr,frame_width,x_size,burst_size,burst_addr); 40 | 41 | 42 | input clk; 43 | input reset; 44 | 45 | input ch_update_d; 46 | input load_in_prog; 47 | input [32-1:0] load_addr; 48 | 49 | input go_next_line; 50 | input burst_start; 51 | input incr; 52 | input [32-1:0] start_addr; 53 | input [`FRAME_BITS-1:0] frame_width; 54 | input [`X_BITS-1:0] x_size; 55 | input [7-1:0] burst_size; 56 | output [32-1:0] burst_addr; 57 | 58 | 59 | reg [32-1:0] burst_addr; 60 | 61 | wire go_next_line_d; 62 | reg [`FRAME_BITS-1:0] frame_width_diff_reg; 63 | wire [`FRAME_BITS-1:0] frame_width_diff; 64 | 65 | 66 | 67 | assign frame_width_diff = {`FRAME_BITS{1'b0}}; 68 | assign go_next_line_d = 1'b0; 69 | 70 | 71 | always @(posedge clk or posedge reset) 72 | if (reset) 73 | burst_addr <= #1 {32{1'b0}}; 74 | else if (load_in_prog) 75 | burst_addr <= #1 load_addr; 76 | else if (ch_update_d) 77 | burst_addr <= #1 start_addr; 78 | else if (burst_start & incr) 79 | burst_addr <= #1 burst_addr + burst_size; 80 | else if (go_next_line_d & incr) 81 | burst_addr <= #1 burst_addr + frame_width_diff; 82 | 83 | 84 | endmodule 85 | 86 | 87 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_ch_fifo.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:54 2011 33 | //-- 34 | //-- Source file: dma_ch_fifo.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_ch_fifo (CLK,WR,RD,WR_ADDR,RD_ADDR,DIN,BSEL,DOUT); 40 | 41 | 42 | input CLK; 43 | 44 | input WR; 45 | input RD; 46 | input [5-2-1:0] WR_ADDR; 47 | input [5-2-1:0] RD_ADDR; 48 | input [32-1:0] DIN; 49 | input [4-1:0] BSEL; 50 | output [32-1:0] DOUT; 51 | 52 | 53 | reg [32-1:0] Mem [8-1:0]; 54 | wire [32-1:0] BitSEL; 55 | wire [32-1:0] DIN_BitSEL; 56 | reg [32-1:0] DOUT; 57 | 58 | assign BitSEL = {{8{BSEL[3]}} , {8{BSEL[2]}} , {8{BSEL[1]}} , {8{BSEL[0]}}}; 59 | 60 | 61 | assign DIN_BitSEL = (Mem[WR_ADDR] & ~BitSEL) | (DIN & BitSEL); 62 | 63 | always @(posedge CLK) 64 | if (WR) 65 | Mem[WR_ADDR] <= #1 DIN_BitSEL; 66 | 67 | 68 | always @(posedge CLK) 69 | if (RD) 70 | DOUT <= #1 Mem[RD_ADDR]; 71 | 72 | 73 | endmodule 74 | 75 | 76 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_ch_offsets.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: dma_ch_offsets.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_ch_offsets(clk,reset,ch_update,burst_start,burst_last,burst_size,load_req_in_prog,x_size,y_size,x_offset,y_offset,x_remain,clr_remain,ch_end,go_next_line,incr,clr_line,line_empty,empty,start_align,width_align,align); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input ch_update; 45 | input burst_start; 46 | input burst_last; 47 | input [7-1:0] burst_size; 48 | input load_req_in_prog; 49 | 50 | input [10-1:0] x_size; 51 | input [10-`X_BITS-1:0] y_size; 52 | 53 | output [10-1:0] x_offset; 54 | output [10-`X_BITS-1:0] y_offset; 55 | output [10-1:0] x_remain; 56 | output [10-`X_BITS-1:0] clr_remain; 57 | output ch_end; 58 | output go_next_line; 59 | input incr; 60 | input clr_line; 61 | output line_empty; 62 | output empty; 63 | 64 | input [2-1:0] start_align; 65 | input [2-1:0] width_align; 66 | output [2-1:0] align; 67 | 68 | 69 | wire update_line; 70 | wire go_next_line; 71 | wire line_end_pre; 72 | wire line_empty; 73 | reg [10-1:0] x_remain; 74 | wire ch_end_pre; 75 | reg ch_end; 76 | wire ch_update_d; 77 | 78 | 79 | 80 | assign ch_end_pre = burst_start & burst_last; 81 | assign go_next_line = 1'b0; 82 | assign line_empty = 1'b0; 83 | assign empty = ch_end_pre | ch_end; 84 | 85 | 86 | always @(posedge clk or posedge reset) 87 | if (reset) 88 | ch_end <= #1 1'b0; 89 | else if (ch_update) 90 | ch_end <= #1 1'b0; 91 | else if (ch_end_pre) 92 | ch_end <= #1 1'b1; 93 | 94 | always @(posedge clk or posedge reset) 95 | if (reset) 96 | x_remain <= #1 {10{1'b0}}; 97 | else if (ch_update | go_next_line) 98 | x_remain <= #1 x_size; 99 | else if (burst_start & (~load_req_in_prog)) 100 | x_remain <= #1 x_remain - burst_size; 101 | 102 | 103 | assign x_offset = {10{1'b0}}; 104 | assign y_offset = {10-`X_BITS{1'b0}}; 105 | assign clr_remain = {10-`X_BITS{1'b0}}; 106 | assign align = start_align; 107 | 108 | 109 | 110 | endmodule 111 | 112 | 113 | 114 | 115 | 116 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_ch_outs.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: dma_ch_outs.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_ch_outs(clk,reset,cmd,clr,outs_max,outs,outs_empty,stall,timeout); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input cmd; 45 | input clr; 46 | input [`OUT_BITS-1:0] outs_max; 47 | output [`OUT_BITS-1:0] outs; 48 | output outs_empty; 49 | output stall; 50 | output timeout; 51 | 52 | 53 | reg [`OUT_BITS-1:0] outs; 54 | wire [`OUT_BITS-1:0] outs_pre; 55 | reg stall; 56 | reg [`TIMEOUT_BITS-1:0] counter; 57 | 58 | 59 | 60 | assign outs_empty = outs == 'd0; 61 | 62 | assign outs_pre = outs + cmd - clr; 63 | 64 | always @(posedge clk or posedge reset) 65 | if (reset) 66 | outs <= #1 'd0; 67 | else if (cmd | clr) 68 | outs <= #1 outs_pre; 69 | 70 | 71 | always @(posedge clk or posedge reset) 72 | if (reset) 73 | stall <= #1 1'b0; 74 | else if (|outs_max) 75 | stall <= #1 outs >= outs_max; 76 | 77 | 78 | 79 | assign timeout = (counter == 'd0); 80 | 81 | always @(posedge clk or posedge reset) 82 | if (reset) 83 | counter <= #1 {`TIMEOUT_BITS{1'b1}}; 84 | else if (clr) 85 | counter <= #1 {`TIMEOUT_BITS{1'b1}}; 86 | else if (|outs) 87 | counter <= #1 counter - 1'b1; 88 | 89 | 90 | endmodule 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_ch_periph_mux.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:54 2011 33 | //-- 34 | //-- Source file: dma_ch_periph_mux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | 40 | module dma_axi32_core0_ch_periph_mux(clk,reset,clken,periph_req,periph_clr,periph_ready,periph_num,clr_valid,clr); 41 | 42 | input clk; 43 | input reset; 44 | input clken; 45 | 46 | input [31:1] periph_req; 47 | output [31:1] periph_clr; 48 | output periph_ready; 49 | input [4:0] periph_num; 50 | input clr_valid; 51 | input clr; 52 | 53 | 54 | reg [31:1] periph_clr; 55 | wire [31:0] periph_req_full; 56 | wire periph_ready_pre; 57 | 58 | 59 | always @(/*AUTOSENSE*/clken or clr or clr_valid or periph_num) 60 | begin 61 | periph_clr = {31{1'b0}}; 62 | 63 | periph_clr[periph_num] = clr & clr_valid & clken; 64 | end 65 | 66 | 67 | assign periph_req_full = {periph_req, 1'b1}; //bit 0 is memory 68 | assign periph_ready_pre = periph_req_full[periph_num]; 69 | 70 | prgen_delay #(1) delay_ready (.clk(clk), .reset(reset), .din(periph_ready_pre), .dout(periph_ready)); 71 | 72 | 73 | endmodule 74 | 75 | 76 | 77 | 78 | 79 | 80 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_ch_reg_size.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: dma_ch_reg_size.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_ch_reg_size(clk,reset,update,start_addr,burst_max_size_reg,burst_max_size_other,allow_full_burst,allow_full_fifo,joint_flush,burst_max_size); 40 | 41 | parameter MAX_BURST = 1 ? 64 : 128; //16 strobes 42 | parameter HALF_BYTES = 32/2; 43 | parameter LARGE_FIFO = 32 > MAX_BURST; 44 | parameter SMALL_FIFO = 32 == 16; 45 | 46 | input clk; 47 | input reset; 48 | 49 | input update; 50 | 51 | input [32-1:0] start_addr; 52 | input [7-1:0] burst_max_size_reg; 53 | input [7-1:0] burst_max_size_other; 54 | 55 | input allow_full_burst; 56 | input allow_full_fifo; 57 | input joint_flush; 58 | output [7-1:0] burst_max_size; 59 | 60 | 61 | 62 | wire [7-1:0] burst_max_size_fifo; 63 | wire [7-1:0] burst_max_size_pre; 64 | reg [7-1:0] burst_max_size; 65 | 66 | 67 | 68 | 69 | assign burst_max_size_fifo = 70 | allow_full_burst | LARGE_FIFO ? MAX_BURST : 71 | joint_flush & SMALL_FIFO ? HALF_BYTES : 72 | (burst_max_size_other > HALF_BYTES) & (burst_max_size_reg > HALF_BYTES) & (burst_max_size_other != burst_max_size_reg) 73 | ? HALF_BYTES : 74 | allow_full_fifo ? 32 : HALF_BYTES; 75 | 76 | 77 | prgen_min2 #(7) min2_max( 78 | .a(burst_max_size_reg), 79 | .b(burst_max_size_fifo), 80 | .min(burst_max_size_pre) 81 | ); 82 | 83 | always @(posedge clk or posedge reset) 84 | if (reset) 85 | burst_max_size <= #1 {7{1'b0}}; 86 | else if (update) 87 | burst_max_size <= #1 burst_max_size_pre > MAX_BURST ? MAX_BURST : burst_max_size_pre; 88 | 89 | 90 | endmodule 91 | 92 | 93 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_ch_remain.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: dma_ch_remain.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_ch_remain(clk,reset,ch_update,wr_outstanding,rd_outstanding,load_req_in_prog,rd_line_cmd,rd_burst_start,rd_burst_size,rd_transfer,rd_transfer_size,wr_clr_line,wr_burst_start,wr_burst_size,wr_transfer,wr_transfer_size,rd_gap,wr_fullness); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input ch_update; 45 | input wr_outstanding; 46 | input rd_outstanding; 47 | input load_req_in_prog; 48 | 49 | input rd_line_cmd; 50 | input rd_burst_start; 51 | input [7-1:0] rd_burst_size; 52 | input rd_transfer; 53 | input [3-1:0] rd_transfer_size; 54 | 55 | input wr_clr_line; 56 | input wr_burst_start; 57 | input [7-1:0] wr_burst_size; 58 | input wr_transfer; 59 | input [3-1:0] wr_transfer_size; 60 | 61 | output [5:0] rd_gap; 62 | output [5:0] wr_fullness; 63 | 64 | 65 | 66 | wire rd_line_cmd_valid; 67 | reg [5+1:0] rd_gap_reg; //signed 68 | reg [5+1:0] wr_fullness_reg; //signed 69 | 70 | wire rd_burst_qual; 71 | wire wr_burst_qual; 72 | reg [7-1:0] rd_burst_size_valid; 73 | wire [3-1:0] rd_transfer_size_valid; 74 | wire [3-1:0] wr_transfer_size_valid; 75 | reg [7-1:0] wr_burst_size_valid; 76 | 77 | 78 | 79 | 80 | assign rd_line_cmd_valid = rd_line_cmd & rd_burst_start; 81 | 82 | assign rd_burst_qual = rd_burst_start & (~load_req_in_prog); 83 | assign wr_burst_qual = wr_burst_start; 84 | 85 | always @(posedge clk or posedge reset) 86 | if (reset) 87 | rd_burst_size_valid <= #1 {7{1'b0}}; 88 | else if (rd_burst_qual) 89 | rd_burst_size_valid <= #1 rd_burst_size; 90 | else 91 | rd_burst_size_valid <= #1 {7{1'b0}}; 92 | 93 | always @(posedge clk or posedge reset) 94 | if (reset) 95 | wr_burst_size_valid <= #1 {7{1'b0}}; 96 | else if (wr_burst_qual) 97 | wr_burst_size_valid <= #1 wr_burst_size; 98 | else 99 | wr_burst_size_valid <= #1 {7{1'b0}}; 100 | 101 | assign rd_transfer_size_valid = {3{rd_transfer}} & rd_transfer_size; 102 | assign wr_transfer_size_valid = {3{wr_transfer}} & wr_transfer_size; 103 | 104 | 105 | //for rd bursts 106 | always @(posedge clk or posedge reset) 107 | if (reset) 108 | rd_gap_reg <= #1 {1'b0, 1'b1, {5{1'b0}}}; 109 | else if (ch_update) 110 | rd_gap_reg <= #1 {1'b0, 1'b1, {5{1'b0}}}; 111 | else 112 | rd_gap_reg <= #1 rd_gap_reg - 113 | rd_burst_size_valid + 114 | wr_transfer_size_valid; 115 | 116 | 117 | assign rd_gap = rd_gap_reg[5+1] ? 'd0 : rd_gap_reg[5:0]; 118 | 119 | 120 | //for wr bursts 121 | always @(posedge clk or posedge reset) 122 | if (reset) 123 | wr_fullness_reg <= #1 {5+1{1'b0}}; 124 | else if (ch_update) 125 | wr_fullness_reg <= #1 {5+1{1'b0}}; 126 | else 127 | wr_fullness_reg <= #1 wr_fullness_reg - 128 | wr_burst_size_valid + 129 | rd_transfer_size_valid; 130 | 131 | 132 | assign wr_fullness = wr_fullness_reg[5+1] ? 'd0 : wr_fullness_reg[5:0]; 133 | 134 | endmodule 135 | 136 | 137 | 138 | 139 | 140 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_channels_apb_mux.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:52 2011 33 | //-- 34 | //-- Source file: dma_core_channels_apb_mux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_channels_apb_mux (clk,reset,pclken,psel,penable,paddr,prdata,pslverr,ch_psel,ch_prdata,ch_pslverr); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input pclken; 45 | input psel; 46 | input penable; 47 | input [10:8] paddr; 48 | output [31:0] prdata; 49 | output pslverr; 50 | 51 | output [7:0] ch_psel; 52 | input [32*8-1:0] ch_prdata; 53 | input [7:0] ch_pslverr; 54 | 55 | 56 | wire [2:0] paddr_sel; 57 | reg [2:0] paddr_sel_d; 58 | 59 | 60 | 61 | always @(posedge clk or posedge reset) 62 | if (reset) 63 | paddr_sel_d <= #1 3'b000; 64 | else if (psel & (~penable)) 65 | paddr_sel_d <= #1 paddr_sel; 66 | else if ((~psel) & pclken) //release for empty channels after error 67 | paddr_sel_d <= #1 3'b000; 68 | 69 | 70 | 71 | assign paddr_sel = paddr[10:8]; 72 | 73 | prgen_demux8 #(1) mux_psel( 74 | .sel(paddr_sel), 75 | .x(psel), 76 | .ch_x(ch_psel) 77 | ); 78 | 79 | 80 | prgen_mux8 #(32) mux_prdata( 81 | .sel(paddr_sel_d), 82 | 83 | .ch_x(ch_prdata), 84 | .x(prdata) 85 | ); 86 | 87 | 88 | assign pslverr = ch_pslverr[paddr_sel_d]; 89 | 90 | endmodule 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_core0_wdt.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:50 2011 33 | //-- 34 | //-- Source file: dma_core_wdt.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi32_core0_wdt(clk,reset,ch_active,rd_burst_start,rd_ch_num,wr_burst_start,wr_ch_num,wdt_timeout,wdt_ch_num); 40 | 41 | 42 | input clk; 43 | input reset; 44 | 45 | input [7:0] ch_active; 46 | input rd_burst_start; 47 | input [2:0] rd_ch_num; 48 | input wr_burst_start; 49 | input [2:0] wr_ch_num; 50 | 51 | output wdt_timeout; 52 | output [2:0] wdt_ch_num; 53 | 54 | 55 | 56 | reg [`WDT_BITS-1:0] counter; 57 | reg [2:0] wdt_ch_num; 58 | wire current_ch_active; 59 | wire current_burst_start; 60 | wire advance; 61 | wire idle; 62 | 63 | 64 | 65 | assign idle = ch_active == 8'd0; 66 | 67 | assign current_ch_active = ch_active[wdt_ch_num]; 68 | 69 | assign current_burst_start = 70 | (rd_burst_start & (rd_ch_num == wdt_ch_num)) | 71 | (wr_burst_start & (wr_ch_num == wdt_ch_num)); 72 | 73 | assign advance = (!current_ch_active) | current_burst_start | wdt_timeout; 74 | 75 | 76 | always @(posedge clk or posedge reset) 77 | if (reset) 78 | wdt_ch_num <= #1 3'd0; 79 | else if (advance) 80 | wdt_ch_num <= #1 wdt_ch_num + 1'b1; 81 | 82 | 83 | 84 | 85 | assign wdt_timeout = (counter == 'd0); 86 | 87 | 88 | always @(posedge clk or posedge reset) 89 | if (reset) 90 | counter <= #1 {`WDT_BITS{1'b1}}; 91 | else if (advance | idle) 92 | counter <= #1 {`WDT_BITS{1'b1}}; 93 | else 94 | counter <= #1 counter - 1'b1; 95 | 96 | 97 | endmodule 98 | 99 | 100 | 101 | 102 | 103 | 104 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_defines.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:50 2011 33 | //-- 34 | //-- Source file: dma_defines.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | `define FRAME_BITS 12 40 | `define X_BITS 8 41 | `define TOKEN_BITS 6 42 | `define OUT_BITS 4 43 | `define DELAY_BITS 3 44 | `define CMD_CNT_BITS 12 45 | `define INT_CNT_BITS 4 46 | `define WAIT_BITS 12 47 | `define TIMEOUT_BITS 10 48 | `define WDT_BITS 11 49 | `define CMD_BITS 7 50 | `define ID_BITS 1 51 | `define LEN_BITS 4 52 | `define SIZE_BITS 2 53 | 54 | `define ID_END_LINE 6 55 | `define ID_LAST 3 56 | 57 | 58 | 59 | 60 | -------------------------------------------------------------------------------- /src/dma_axi32/dma_axi32_reg_params.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:50 2011 33 | //-- 34 | //-- Source file: dma_reg_params.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | 40 | parameter PROC0_STATUS = 8'h00; 41 | parameter PROC1_STATUS = 8'h04; 42 | parameter PROC2_STATUS = 8'h08; 43 | parameter PROC3_STATUS = 8'h0C; 44 | parameter PROC4_STATUS = 8'h10; 45 | parameter PROC5_STATUS = 8'h14; 46 | parameter PROC6_STATUS = 8'h18; 47 | parameter PROC7_STATUS = 8'h1C; 48 | parameter CORE0_JOINT = 8'h30; 49 | parameter CORE1_JOINT = 8'h34; 50 | parameter CORE0_PRIO = 8'h38; 51 | parameter CORE1_PRIO = 8'h3C; 52 | parameter CORE0_CLKDIV = 8'h40; 53 | parameter CORE1_CLKDIV = 8'h44; 54 | parameter CORE0_START = 8'h48; 55 | parameter CORE1_START = 8'h4C; 56 | parameter PERIPH_RX_CTRL = 8'h50; 57 | parameter PERIPH_TX_CTRL = 8'h54; 58 | parameter IDLE = 8'hD0; 59 | parameter USER_DEF_STAT = 8'hE0; 60 | parameter USER_DEF0_STAT0 = 8'hF0; 61 | parameter USER_DEF0_STAT1 = 8'hF4; 62 | parameter USER_DEF1_STAT0 = 8'hF8; 63 | parameter USER_DEF1_STAT1 = 8'hFC; 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | -------------------------------------------------------------------------------- /src/dma_axi32/filelist.txt: -------------------------------------------------------------------------------- 1 | 2 | dma_axi32.v 3 | dma_axi32_dual_core.v 4 | dma_axi32_apb_mux.v 5 | dma_axi32_reg.v 6 | dma_axi32_reg_core0.v 7 | prgen_scatter8_1.v 8 | dma_axi32_core0_top.v 9 | dma_axi32_core0.v 10 | dma_axi32_core0_wdt.v 11 | dma_axi32_core0_arbiter.v 12 | dma_axi32_core0_ctrl.v 13 | dma_axi32_core0_axim_wr.v 14 | dma_axi32_core0_axim_cmd.v 15 | dma_axi32_core0_axim_timeout.v 16 | dma_axi32_core0_axim_wdata.v 17 | prgen_joint_stall.v 18 | prgen_fifo.v 19 | prgen_stall.v 20 | dma_axi32_core0_axim_resp.v 21 | dma_axi32_core0_axim_rd.v 22 | dma_axi32_core0_axim_rdata.v 23 | dma_axi32_core0_channels.v 24 | dma_axi32_core0_channels_apb_mux.v 25 | dma_axi32_core0_channels_mux.v 26 | prgen_or8.v 27 | prgen_mux8.v 28 | prgen_demux8.v 29 | dma_axi32_core0_ch.v 30 | dma_axi32_core0_ch_reg.v 31 | dma_axi32_core0_ch_reg_size.v 32 | prgen_rawstat.v 33 | dma_axi32_core0_ch_offsets.v 34 | dma_axi32_core0_ch_remain.v 35 | dma_axi32_core0_ch_outs.v 36 | dma_axi32_core0_ch_calc.v 37 | dma_axi32_core0_ch_calc_addr.v 38 | dma_axi32_core0_ch_calc_size.v 39 | prgen_min3.v 40 | prgen_min2.v 41 | dma_axi32_core0_ch_calc_joint.v 42 | dma_axi32_core0_ch_periph_mux.v 43 | dma_axi32_core0_ch_fifo_ctrl.v 44 | dma_axi32_core0_ch_wr_slicer.v 45 | prgen_swap_32.v 46 | dma_axi32_core0_ch_rd_slicer.v 47 | dma_axi32_core0_ch_fifo_ptr.v 48 | dma_axi32_core0_ch_fifo.v 49 | dma_axi32_core0_ch_empty.v 50 | prgen_delay.v 51 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_delay.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:54 2011 33 | //-- 34 | //-- Source file: prgen_delay.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_delay(clk,reset,din,dout); 40 | 41 | 42 | input clk; 43 | input reset; 44 | 45 | input din; 46 | output dout; 47 | 48 | parameter DELAY = 2; 49 | 50 | 51 | reg [DELAY:0] shift_reg; 52 | 53 | always @(posedge clk or posedge reset) 54 | if (reset) 55 | shift_reg <= #1 {DELAY+1{1'b0}}; 56 | else 57 | shift_reg <= #1 {shift_reg[DELAY-1:0], din}; 58 | 59 | assign dout = shift_reg[DELAY-1]; 60 | 61 | 62 | endmodule 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_demux8.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:52 2011 33 | //-- 34 | //-- Source file: prgen_demux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | 40 | module prgen_demux8(sel,x,ch_x); 41 | 42 | parameter WIDTH = 8; 43 | 44 | 45 | input [3-1:0] sel; 46 | input [WIDTH-1:0] x; 47 | output [8*WIDTH-1:0] ch_x; 48 | 49 | 50 | reg [8*WIDTH-1:0] ch_x; 51 | 52 | 53 | 54 | always @(/*AUTOSENSE*/sel or x) 55 | begin 56 | ch_x = {8*WIDTH{1'b0}}; 57 | 58 | case (sel) 59 | 3'd0 : ch_x[WIDTH-1+WIDTH*0:WIDTH*0] = x; 60 | 3'd1 : ch_x[WIDTH-1+WIDTH*1:WIDTH*1] = x; 61 | 3'd2 : ch_x[WIDTH-1+WIDTH*2:WIDTH*2] = x; 62 | 3'd3 : ch_x[WIDTH-1+WIDTH*3:WIDTH*3] = x; 63 | 3'd4 : ch_x[WIDTH-1+WIDTH*4:WIDTH*4] = x; 64 | 3'd5 : ch_x[WIDTH-1+WIDTH*5:WIDTH*5] = x; 65 | 3'd6 : ch_x[WIDTH-1+WIDTH*6:WIDTH*6] = x; 66 | 3'd7 : ch_x[WIDTH-1+WIDTH*7:WIDTH*7] = x; 67 | 68 | default : 69 | ch_x[WIDTH-1:0] = x; 70 | endcase 71 | end 72 | 73 | 74 | endmodule 75 | 76 | 77 | 78 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_joint_stall.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:51 2011 33 | //-- 34 | //-- Source file: prgen_joint_stall.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_joint_stall(clk,reset,joint_req_out,rd_transfer,rd_transfer_size,ch_fifo_rd,data_fullness_pre,HOLD,joint_fifo_rd_valid,rd_transfer_size_joint,rd_transfer_full,joint_stall); 40 | 41 | parameter SIZE_BITS = 1; 42 | 43 | input clk; 44 | input reset; 45 | 46 | input joint_req_out; 47 | input rd_transfer; 48 | input [SIZE_BITS-1:0] rd_transfer_size; 49 | input ch_fifo_rd; 50 | input [2:0] data_fullness_pre; 51 | input HOLD; 52 | 53 | output joint_fifo_rd_valid; 54 | output [SIZE_BITS-1:0] rd_transfer_size_joint; 55 | output rd_transfer_full; 56 | output joint_stall; 57 | 58 | 59 | 60 | 61 | wire rd_transfer_joint; 62 | wire joint_fifo_rd; 63 | wire joint_fifo_rd_valid; 64 | wire [2:0] count_ch_fifo_pre; 65 | reg [2:0] count_ch_fifo; 66 | wire joint_stall_pre; 67 | reg joint_stall_reg; 68 | wire joint_not_ready_pre; 69 | wire joint_not_ready; 70 | wire [SIZE_BITS-1:0] rd_transfer_size_joint; 71 | wire rd_transfer_full; 72 | reg [2:0] joint_rd_stall_num; 73 | wire joint_rd_stall; 74 | 75 | 76 | 77 | 78 | assign rd_transfer_joint = joint_req_out & rd_transfer; 79 | 80 | prgen_delay #(2) delay_joint_fifo_rd (.clk(clk), .reset(reset), .din(rd_transfer_joint), .dout(joint_fifo_rd)); 81 | 82 | assign count_ch_fifo_pre = count_ch_fifo + rd_transfer_joint - ch_fifo_rd; 83 | 84 | //count fullness of channel's fifo 85 | always @(posedge clk or posedge reset) 86 | if (reset) 87 | count_ch_fifo <= #1 3'd0; 88 | else if (joint_req_out & (rd_transfer_joint | ch_fifo_rd)) 89 | count_ch_fifo <= #1 count_ch_fifo_pre; 90 | 91 | //prevent read channel to overflow the channel's fifo 92 | assign joint_stall_pre = joint_req_out & ((count_ch_fifo_pre > 'd2) | ((count_ch_fifo_pre == 'd2) & (data_fullness_pre > 'd1)) | HOLD); 93 | 94 | //prevent write channel to overflow the wr data fifo 95 | assign joint_not_ready_pre = joint_req_out & (data_fullness_pre > 'd1) & (~(rd_transfer_joint & joint_stall_pre)); 96 | 97 | 98 | always @(posedge clk or posedge reset) 99 | if (reset) 100 | joint_stall_reg <= #1 1'b0; 101 | else if (joint_stall_pre) 102 | joint_stall_reg <= #1 1'b1; 103 | else if (count_ch_fifo_pre == 'd0) 104 | joint_stall_reg <= #1 1'b0; 105 | 106 | assign joint_stall = joint_stall_reg | (joint_req_out & HOLD); 107 | 108 | prgen_delay #(1) delay_joint_not_ready (.clk(clk), .reset(reset), .din(joint_not_ready_pre), .dout(joint_not_ready)); 109 | 110 | 111 | prgen_fifo #(SIZE_BITS, 2) 112 | rd_transfer_fifo( 113 | .clk(clk), 114 | .reset(reset), 115 | .push(rd_transfer_joint), 116 | .pop(joint_fifo_rd_valid), 117 | .din(rd_transfer_size), 118 | .dout(rd_transfer_size_joint), 119 | .empty(), 120 | .full(rd_transfer_full) 121 | ); 122 | 123 | prgen_stall #(3) stall_joint_fifo_rd (.clk(clk), .reset(reset), .din(joint_fifo_rd), .stall(joint_not_ready), .dout(joint_fifo_rd_valid)); 124 | 125 | 126 | endmodule 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_min2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: prgen_min2.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_min2(a,b,min); 40 | 41 | parameter WIDTH = 8; 42 | 43 | input [WIDTH-1:0] a; 44 | input [WIDTH-1:0] b; 45 | 46 | output [WIDTH-1:0] min; 47 | 48 | 49 | assign min = a < b ? a : b; 50 | 51 | endmodule 52 | 53 | 54 | 55 | 56 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_min3.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: prgen_min3.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_min3(clk,reset,a,b,c,min); 40 | 41 | parameter WIDTH = 8; 42 | 43 | input clk; 44 | input reset; 45 | input [WIDTH-1:0] a; 46 | input [WIDTH-1:0] b; 47 | input [WIDTH-1:0] c; 48 | 49 | output [WIDTH-1:0] min; 50 | 51 | wire [WIDTH-1:0] min_ab_pre; 52 | reg [WIDTH-1:0] min_ab; 53 | reg [WIDTH-1:0] min_c; 54 | 55 | 56 | prgen_min2 #(WIDTH) min2_ab( 57 | .a(a), 58 | .b(b), 59 | .min(min_ab_pre) 60 | ); 61 | 62 | prgen_min2 #(WIDTH) min2_abc( 63 | .a(min_ab), 64 | .b(min_c), 65 | .min(min) 66 | ); 67 | 68 | always @(posedge clk or posedge reset) 69 | if (reset) 70 | begin 71 | min_ab <= #1 {WIDTH{1'b0}}; 72 | min_c <= #1 {WIDTH{1'b0}}; 73 | end 74 | else 75 | begin 76 | min_ab <= #1 min_ab_pre; 77 | min_c <= #1 c; 78 | end 79 | 80 | endmodule 81 | 82 | 83 | 84 | 85 | 86 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_mux8.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:52 2011 33 | //-- 34 | //-- Source file: prgen_mux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | 40 | module prgen_mux8(sel,ch_x,x); 41 | 42 | parameter WIDTH = 8; 43 | 44 | 45 | input [3-1:0] sel; 46 | input [8*WIDTH-1:0] ch_x; 47 | output [WIDTH-1:0] x; 48 | 49 | 50 | reg [WIDTH-1:0] x; 51 | 52 | 53 | always @(/*AUTOSENSE*/ch_x or sel) 54 | begin 55 | case (sel) 56 | 3'd0 :x = ch_x[WIDTH-1+WIDTH*0:WIDTH*0]; 57 | 3'd1 :x = ch_x[WIDTH-1+WIDTH*1:WIDTH*1]; 58 | 3'd2 :x = ch_x[WIDTH-1+WIDTH*2:WIDTH*2]; 59 | 3'd3 :x = ch_x[WIDTH-1+WIDTH*3:WIDTH*3]; 60 | 3'd4 :x = ch_x[WIDTH-1+WIDTH*4:WIDTH*4]; 61 | 3'd5 :x = ch_x[WIDTH-1+WIDTH*5:WIDTH*5]; 62 | 3'd6 :x = ch_x[WIDTH-1+WIDTH*6:WIDTH*6]; 63 | 3'd7 :x = ch_x[WIDTH-1+WIDTH*7:WIDTH*7]; 64 | 65 | default : 66 | x = ch_x[WIDTH-1:0]; 67 | endcase 68 | end 69 | 70 | 71 | endmodule 72 | 73 | 74 | 75 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_or8.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:52 2011 33 | //-- 34 | //-- Source file: prgen_or.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_or8(ch_x,x); 40 | 41 | parameter WIDTH = 8; 42 | 43 | 44 | input [8*WIDTH-1:0] ch_x; 45 | output [WIDTH-1:0] x; 46 | 47 | 48 | assign x = 49 | ch_x[WIDTH-1+WIDTH*0:WIDTH*0] | 50 | ch_x[WIDTH-1+WIDTH*1:WIDTH*1] | 51 | ch_x[WIDTH-1+WIDTH*2:WIDTH*2] | 52 | ch_x[WIDTH-1+WIDTH*3:WIDTH*3] | 53 | ch_x[WIDTH-1+WIDTH*4:WIDTH*4] | 54 | ch_x[WIDTH-1+WIDTH*5:WIDTH*5] | 55 | ch_x[WIDTH-1+WIDTH*6:WIDTH*6] | 56 | ch_x[WIDTH-1+WIDTH*7:WIDTH*7] ; 57 | 58 | endmodule 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_rawstat.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:53 2011 33 | //-- 34 | //-- Source file: prgen_rawstat.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_rawstat (clk,reset,clear,write,pwdata,int_bus,rawstat); 40 | 41 | parameter SIZE = 32; 42 | 43 | input clk; 44 | input reset; 45 | 46 | input clear; 47 | input write; 48 | input [SIZE-1:0] pwdata; 49 | input [SIZE-1:0] int_bus; 50 | 51 | output [SIZE-1:0] rawstat; 52 | 53 | 54 | 55 | reg [SIZE-1:0] rawstat; 56 | wire [SIZE-1:0] write_bus; 57 | wire [SIZE-1:0] clear_bus; 58 | 59 | 60 | assign write_bus = {SIZE{write}} & pwdata; 61 | assign clear_bus = {SIZE{clear}} & pwdata; 62 | 63 | 64 | always @(posedge clk or posedge reset) 65 | if (reset) 66 | rawstat <= #1 {SIZE{1'b0}}; 67 | else 68 | rawstat <= #1 (rawstat | int_bus | write_bus) & (~clear_bus); 69 | 70 | endmodule 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_scatter8_1.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:50 2011 33 | //-- 34 | //-- Source file: prgen_scatter.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_scatter8_1(ch_x,x); 40 | 41 | parameter CH_NUM = 0; 42 | 43 | 44 | input [8*1-1:0] ch_x; 45 | output [8-1:0] x; 46 | 47 | 48 | assign x = { 49 | ch_x[CH_NUM+7], 50 | ch_x[CH_NUM+6], 51 | ch_x[CH_NUM+5], 52 | ch_x[CH_NUM+4], 53 | ch_x[CH_NUM+3], 54 | ch_x[CH_NUM+2], 55 | ch_x[CH_NUM+1], 56 | ch_x[CH_NUM+0]}; 57 | 58 | 59 | endmodule 60 | 61 | 62 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_stall.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:51 2011 33 | //-- 34 | //-- Source file: prgen_stall.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_stall(clk,reset,din,stall,dout); 40 | 41 | parameter DEPTH = 1; 42 | 43 | input clk; 44 | input reset; 45 | 46 | input din; 47 | input stall; 48 | output dout; 49 | 50 | 51 | 52 | reg [DEPTH-1:0] count; 53 | wire pend; 54 | 55 | 56 | always @(posedge clk or posedge reset) 57 | if (reset) 58 | count <= #1 {DEPTH{1'b0}}; 59 | else if (pend & (~stall)) 60 | count <= #1 count - 1'b1; 61 | else if (din & stall) 62 | count <= #1 count + 1'b1; 63 | 64 | assign pend = (|count); 65 | assign dout = (din | pend) & (~stall); 66 | 67 | 68 | 69 | 70 | 71 | endmodule 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | -------------------------------------------------------------------------------- /src/dma_axi32/prgen_swap_32.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:34:54 2011 33 | //-- 34 | //-- Source file: prgen_swap32.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_swap32 (end_swap,data_in,data_out,bsel_in,bsel_out); 40 | 41 | input [1:0] end_swap; 42 | input [31:0] data_in; 43 | output [31:0] data_out; 44 | input [3:0] bsel_in; 45 | output [3:0] bsel_out; 46 | 47 | 48 | reg [31:0] data_out; 49 | reg [3:0] bsel_out; 50 | 51 | 52 | 53 | always @(/*AUTOSENSE*/data_in or end_swap) 54 | begin 55 | case (end_swap[1:0]) 56 | 2'b00 : data_out = data_in; 57 | 2'b01 : data_out = {data_in[23:16], data_in[31:24], data_in[7:0], data_in[15:8]}; 58 | 2'b10 : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]}; 59 | 2'b11 : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]}; 60 | endcase 61 | end 62 | 63 | always @(/*AUTOSENSE*/bsel_in or end_swap) 64 | begin 65 | case (end_swap[1:0]) 66 | 2'b00 : bsel_out = bsel_in; 67 | 2'b01 : bsel_out = {bsel_in[2], bsel_in[3], bsel_in[0], bsel_in[1]}; 68 | 2'b10 : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]}; 69 | 2'b11 : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]}; 70 | endcase 71 | end 72 | 73 | 74 | endmodule 75 | 76 | 77 | 78 | -------------------------------------------------------------------------------- /src/dma_axi64/README.txt: -------------------------------------------------------------------------------- 1 | 2 | Opencores.org project - DMA AXI - 64 bit build 3 | 4 | This core is based on the Provartec PR200 IP - 'Generic High performance dual-core AXI DMA' 5 | 6 | Build with the following parameters: 7 | - Single channel 8 | - Single interrupt bit 9 | - One AXI port (simultaneous read and write) 10 | - AXI data 64 bits 11 | - data FIFO 32 bytes 12 | - AXI address bits 32 13 | - AXI outstanding write commands - 4 14 | - AXI outstanding read commands - 4 15 | - Block support - no 16 | - Scheduler - no 17 | - Priority modes - no 18 | - Joint mode - yes 19 | - Independent mode - yes 20 | - Outstanding mode - no 21 | - Tokens - yes 22 | - AHB timeout - yes 23 | - Watchdog timer - yes 24 | - Peripheral control - yes 25 | - Command lists - yes 26 | - Endianess support - yes 27 | 28 | To view the complete IP - http://www.provartec.com/ipproducts/56 29 | For any questions / remarks / suggestions / bugs please contact info@provartec.com. 30 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_apb_mux.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:53 2011 33 | //-- 34 | //-- Source file: dma_apb_mux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_apb_mux (clk,reset,pclken,psel,penable,pwrite,paddr,prdata,pslverr,pready,psel0,prdata0,pslverr0,psel1,prdata1,pslverr1,psel_reg,prdata_reg,pslverr_reg); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input pclken; 45 | input psel; 46 | input penable; 47 | input pwrite; 48 | input [12:11] paddr; 49 | output [31:0] prdata; 50 | output pslverr; 51 | output pready; 52 | 53 | output psel0; 54 | input [31:0] prdata0; 55 | input pslverr0; 56 | 57 | output psel1; 58 | input [31:0] prdata1; 59 | input pslverr1; 60 | 61 | output psel_reg; 62 | input [31:0] prdata_reg; 63 | input pslverr_reg; 64 | 65 | wire [31:0] prdata_pre; 66 | wire pslverr_pre; 67 | 68 | 69 | reg pready; 70 | 71 | 72 | assign psel0 = pclken & psel & (paddr[12:11] == 2'b00); 73 | assign psel1 = pclken & psel & (paddr[12:11] == 2'b01); 74 | assign psel_reg = pclken & psel & (paddr[12] == 1'b1); 75 | 76 | assign prdata_pre = prdata0 | prdata1 | prdata_reg; 77 | assign pslverr_pre = pslverr0 | pslverr1 | pslverr_reg; 78 | 79 | assign prdata = prdata_pre; 80 | assign pslverr = pslverr_pre; 81 | 82 | 83 | always @(posedge clk or posedge reset) 84 | if (reset) 85 | pready <= #1 1'b0; 86 | else if (pclken) 87 | pready <= #1 psel & (~penable); 88 | 89 | 90 | endmodule 91 | 92 | 93 | 94 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_ch_reg_params.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:56 2011 33 | //-- 34 | //-- Source file: dma_ch_reg_params.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | parameter CMD_LINE0 = 8'h00; 40 | parameter CMD_LINE1 = 8'h04; 41 | parameter CMD_LINE2 = 8'h08; 42 | parameter CMD_LINE3 = 8'h0C; 43 | parameter STATIC_LINE0 = 8'h10; 44 | parameter STATIC_LINE1 = 8'h14; 45 | parameter STATIC_LINE2 = 8'h18; 46 | parameter STATIC_LINE3 = 8'h1C; 47 | parameter STATIC_LINE4 = 8'h20; 48 | 49 | parameter RESTRICT = 8'h2C; 50 | parameter RD_OFFSETS = 8'h30; 51 | parameter WR_OFFSETS = 8'h34; 52 | parameter FIFO_FULLNESS = 8'h38; 53 | parameter CMD_OUTS = 8'h3C; 54 | 55 | parameter CH_ENABLE = 8'h40; 56 | parameter CH_START = 8'h44; 57 | parameter CH_ACTIVE = 8'h48; 58 | parameter CH_CMD_COUNTER = 8'h50; 59 | 60 | parameter INT_RAWSTAT = 8'hA0; 61 | parameter INT_CLEAR = 8'hA4; 62 | parameter INT_ENABLE = 8'hA8; 63 | parameter INT_STATUS = 8'hAC; 64 | 65 | 66 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_arbiter.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:54 2011 33 | //-- 34 | //-- Source file: dma_core_arbiter.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_arbiter(clk,reset,enable,joint_mode,page_cross,joint_req,prio_top,prio_high,prio_top_num,prio_high_num,hold,ch_ready,ch_active,finish,ch_go_out,ch_num,ch_last); 40 | 41 | parameter CH_LAST = 1-1; 42 | 43 | input clk; 44 | input reset; 45 | 46 | input enable; 47 | 48 | input joint_mode; 49 | input page_cross; 50 | input joint_req; 51 | input prio_top; 52 | input prio_high; 53 | input [2:0] prio_top_num; 54 | input [2:0] prio_high_num; 55 | input hold; 56 | 57 | input [7:0] ch_ready; 58 | input [7:0] ch_active; 59 | input finish; 60 | output ch_go_out; 61 | output [2:0] ch_num; 62 | output ch_last; 63 | 64 | 65 | 66 | reg [7:0] current_active; 67 | wire current_ready_only; 68 | wire ch_last_pre; 69 | wire ch_last; 70 | wire ready; 71 | wire next_ready; 72 | wire next_ready0; 73 | wire next_ready1; 74 | wire prio_top_ready; 75 | wire prio_high_ready; 76 | reg in_prog; 77 | wire ch_go_pre; 78 | wire ch_go_pre_d; 79 | wire ch_go_top_pre; 80 | wire ch_go_high_pre; 81 | wire ch_go; 82 | wire ch_go_d; 83 | wire ch_go_top; 84 | wire ch_go_high; 85 | wire ch_go_next; 86 | wire hold_d; 87 | wire advance_next; 88 | wire [2:0] ch_num_pre; 89 | wire [3:0] next_ch_num0_pre; 90 | wire [3:0] next_ch_num0_pre2; 91 | wire [2:0] next_ch_num0; 92 | wire [3:0] next_ch_num1_pre; 93 | wire [3:0] next_ch_num1_pre2; 94 | wire [2:0] next_ch_num1; 95 | wire [2:0] next_ch_num_pre; 96 | 97 | assign ch_go_out = 'd1; 98 | assign ch_num = 'd0; 99 | assign ch_last = 'd1; 100 | 101 | 102 | 103 | endmodule 104 | 105 | 106 | 107 | 108 | 109 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_axim_resp.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:55 2011 33 | //-- 34 | //-- Source file: dma_core_axim_resp.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_axim_resp(clk,reset,slverr,decerr,clr,clr_last,ch_num_resp,resp_full,AID,AVALID,AREADY,RESP,ID,VALID,READY,LAST); 40 | 41 | parameter CMD_DEPTH = 8; 42 | 43 | input clk; 44 | input reset; 45 | 46 | output slverr; 47 | output decerr; 48 | output clr; 49 | output clr_last; 50 | output [2:0] ch_num_resp; 51 | output resp_full; 52 | 53 | 54 | input [`CMD_BITS-1:0] AID; 55 | input AVALID; 56 | input AREADY; 57 | input [1:0] RESP; 58 | output [`CMD_BITS-1:0] ID; 59 | input VALID; 60 | input READY; 61 | input LAST; 62 | 63 | 64 | 65 | parameter RESP_SLVERR = 2'b10; 66 | parameter RESP_DECERR = 2'b11; 67 | 68 | 69 | wire clr_pre; 70 | wire [2:0] ch_num_resp_pre; 71 | wire clr_last_pre; 72 | wire slverr_pre; 73 | wire decerr_pre; 74 | reg [2:0] ch_num_resp; 75 | 76 | wire resp_push; 77 | wire resp_pop; 78 | wire resp_empty; 79 | wire resp_full; 80 | wire [`CMD_BITS-1:0] ID; 81 | 82 | 83 | assign resp_push = AVALID & AREADY; 84 | assign resp_pop = VALID & READY & LAST; 85 | 86 | assign clr_pre = resp_pop; 87 | 88 | assign ch_num_resp_pre = ID[2:0] ; 89 | 90 | assign slverr_pre = clr_pre & RESP == RESP_SLVERR; 91 | assign decerr_pre = clr_pre & RESP == RESP_DECERR; 92 | 93 | assign clr_last_pre = clr_pre & ID[3]; 94 | 95 | prgen_delay #(1) delay_clr(.clk(clk), .reset(reset), .din(clr_pre), .dout(clr)); 96 | prgen_delay #(1) delay_clr_last(.clk(clk), .reset(reset), .din(clr_last_pre), .dout(clr_last)); 97 | prgen_delay #(1) delay_slverr(.clk(clk), .reset(reset), .din(slverr_pre), .dout(slverr)); 98 | prgen_delay #(1) delay_decerr(.clk(clk), .reset(reset), .din(decerr_pre), .dout(decerr)); 99 | 100 | always @(posedge clk or posedge reset) 101 | if (reset) 102 | ch_num_resp <= #1 3'b000; 103 | else if (clr_pre) 104 | ch_num_resp <= #1 ch_num_resp_pre; 105 | 106 | 107 | 108 | prgen_fifo #(`CMD_BITS, CMD_DEPTH) 109 | resp_fifo( 110 | .clk(clk), 111 | .reset(reset), 112 | .push(resp_push), 113 | .pop(resp_pop), 114 | .din(AID), 115 | .dout(ID), 116 | .empty(resp_empty), 117 | .full(resp_full) 118 | ); 119 | 120 | 121 | endmodule 122 | 123 | 124 | 125 | 126 | 127 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_axim_timeout.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:55 2011 33 | //-- 34 | //-- Source file: dma_core_axim_timeout.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_axim_timeout(clk,reset,VALID,READY,ID,axim_timeout_num,axim_timeout); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input VALID; 45 | input READY; 46 | input [`CMD_BITS-1:0] ID; 47 | 48 | output [2:0] axim_timeout_num; 49 | output axim_timeout; 50 | 51 | 52 | 53 | reg [`TIMEOUT_BITS-1:0] counter; 54 | 55 | 56 | assign axim_timeout_num = ID[2:0]; 57 | 58 | assign axim_timeout = (counter == 'd0); 59 | 60 | 61 | always @(posedge clk or posedge reset) 62 | if (reset) 63 | counter <= #1 {`TIMEOUT_BITS{1'b1}}; 64 | else if (VALID & READY) 65 | counter <= #1 {`TIMEOUT_BITS{1'b1}}; 66 | else if (VALID) 67 | counter <= #1 counter - 1'b1; 68 | 69 | 70 | 71 | endmodule 72 | 73 | 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_ch_calc_addr.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:56 2011 33 | //-- 34 | //-- Source file: dma_ch_calc_addr.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_ch_calc_addr(clk,reset,ch_update_d,load_in_prog,load_addr,go_next_line,burst_start,incr,start_addr,frame_width,x_size,burst_size,burst_addr); 40 | 41 | 42 | input clk; 43 | input reset; 44 | 45 | input ch_update_d; 46 | input load_in_prog; 47 | input [32-1:0] load_addr; 48 | 49 | input go_next_line; 50 | input burst_start; 51 | input incr; 52 | input [32-1:0] start_addr; 53 | input [`FRAME_BITS-1:0] frame_width; 54 | input [`X_BITS-1:0] x_size; 55 | input [8-1:0] burst_size; 56 | output [32-1:0] burst_addr; 57 | 58 | 59 | reg [32-1:0] burst_addr; 60 | 61 | wire go_next_line_d; 62 | reg [`FRAME_BITS-1:0] frame_width_diff_reg; 63 | wire [`FRAME_BITS-1:0] frame_width_diff; 64 | 65 | 66 | 67 | assign frame_width_diff = {`FRAME_BITS{1'b0}}; 68 | assign go_next_line_d = 1'b0; 69 | 70 | 71 | always @(posedge clk or posedge reset) 72 | if (reset) 73 | burst_addr <= #1 {32{1'b0}}; 74 | else if (load_in_prog) 75 | burst_addr <= #1 load_addr; 76 | else if (ch_update_d) 77 | burst_addr <= #1 start_addr; 78 | else if (burst_start & incr) 79 | burst_addr <= #1 burst_addr + burst_size; 80 | else if (go_next_line_d & incr) 81 | burst_addr <= #1 burst_addr + frame_width_diff; 82 | 83 | 84 | endmodule 85 | 86 | 87 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_ch_fifo.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:57 2011 33 | //-- 34 | //-- Source file: dma_ch_fifo.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_ch_fifo (CLK,WR,RD,WR_ADDR,RD_ADDR,DIN,BSEL,DOUT); 40 | 41 | 42 | input CLK; 43 | 44 | input WR; 45 | input RD; 46 | input [5-3-1:0] WR_ADDR; 47 | input [5-3-1:0] RD_ADDR; 48 | input [64-1:0] DIN; 49 | input [8-1:0] BSEL; 50 | output [64-1:0] DOUT; 51 | 52 | 53 | reg [64-1:0] Mem [4-1:0]; 54 | wire [64-1:0] BitSEL; 55 | wire [64-1:0] DIN_BitSEL; 56 | reg [64-1:0] DOUT; 57 | 58 | assign BitSEL = {{8{BSEL[7]}} , {8{BSEL[6]}} , {8{BSEL[5]}} , {8{BSEL[4]}} , {8{BSEL[3]}} , {8{BSEL[2]}} , {8{BSEL[1]}} , {8{BSEL[0]}}}; 59 | 60 | 61 | assign DIN_BitSEL = (Mem[WR_ADDR] & ~BitSEL) | (DIN & BitSEL); 62 | 63 | always @(posedge CLK) 64 | if (WR) 65 | Mem[WR_ADDR] <= #1 DIN_BitSEL; 66 | 67 | 68 | always @(posedge CLK) 69 | if (RD) 70 | DOUT <= #1 Mem[RD_ADDR]; 71 | 72 | 73 | endmodule 74 | 75 | 76 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_ch_offsets.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:56 2011 33 | //-- 34 | //-- Source file: dma_ch_offsets.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_ch_offsets(clk,reset,ch_update,burst_start,burst_last,burst_size,load_req_in_prog,x_size,y_size,x_offset,y_offset,x_remain,clr_remain,ch_end,go_next_line,incr,clr_line,line_empty,empty,start_align,width_align,align); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input ch_update; 45 | input burst_start; 46 | input burst_last; 47 | input [8-1:0] burst_size; 48 | input load_req_in_prog; 49 | 50 | input [10-1:0] x_size; 51 | input [10-`X_BITS-1:0] y_size; 52 | 53 | output [10-1:0] x_offset; 54 | output [10-`X_BITS-1:0] y_offset; 55 | output [10-1:0] x_remain; 56 | output [10-`X_BITS-1:0] clr_remain; 57 | output ch_end; 58 | output go_next_line; 59 | input incr; 60 | input clr_line; 61 | output line_empty; 62 | output empty; 63 | 64 | input [3-1:0] start_align; 65 | input [3-1:0] width_align; 66 | output [3-1:0] align; 67 | 68 | 69 | wire update_line; 70 | wire go_next_line; 71 | wire line_end_pre; 72 | wire line_empty; 73 | reg [10-1:0] x_remain; 74 | wire ch_end_pre; 75 | reg ch_end; 76 | wire ch_update_d; 77 | 78 | 79 | 80 | assign ch_end_pre = burst_start & burst_last; 81 | assign go_next_line = 1'b0; 82 | assign line_empty = 1'b0; 83 | assign empty = ch_end_pre | ch_end; 84 | 85 | 86 | always @(posedge clk or posedge reset) 87 | if (reset) 88 | ch_end <= #1 1'b0; 89 | else if (ch_update) 90 | ch_end <= #1 1'b0; 91 | else if (ch_end_pre) 92 | ch_end <= #1 1'b1; 93 | 94 | always @(posedge clk or posedge reset) 95 | if (reset) 96 | x_remain <= #1 {10{1'b0}}; 97 | else if (ch_update | go_next_line) 98 | x_remain <= #1 x_size; 99 | else if (burst_start & (~load_req_in_prog)) 100 | x_remain <= #1 x_remain - burst_size; 101 | 102 | 103 | assign x_offset = {10{1'b0}}; 104 | assign y_offset = {10-`X_BITS{1'b0}}; 105 | assign clr_remain = {10-`X_BITS{1'b0}}; 106 | assign align = start_align; 107 | 108 | 109 | 110 | endmodule 111 | 112 | 113 | 114 | 115 | 116 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_ch_outs.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:56 2011 33 | //-- 34 | //-- Source file: dma_ch_outs.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_ch_outs(clk,reset,cmd,clr,outs_max,outs,outs_empty,stall,timeout); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input cmd; 45 | input clr; 46 | input [`OUT_BITS-1:0] outs_max; 47 | output [`OUT_BITS-1:0] outs; 48 | output outs_empty; 49 | output stall; 50 | output timeout; 51 | 52 | 53 | reg [`OUT_BITS-1:0] outs; 54 | wire [`OUT_BITS-1:0] outs_pre; 55 | reg stall; 56 | reg [`TIMEOUT_BITS-1:0] counter; 57 | 58 | 59 | 60 | assign outs_empty = outs == 'd0; 61 | 62 | assign outs_pre = outs + cmd - clr; 63 | 64 | always @(posedge clk or posedge reset) 65 | if (reset) 66 | outs <= #1 'd0; 67 | else if (cmd | clr) 68 | outs <= #1 outs_pre; 69 | 70 | 71 | always @(posedge clk or posedge reset) 72 | if (reset) 73 | stall <= #1 1'b0; 74 | else if (|outs_max) 75 | stall <= #1 outs >= outs_max; 76 | 77 | 78 | 79 | assign timeout = (counter == 'd0); 80 | 81 | always @(posedge clk or posedge reset) 82 | if (reset) 83 | counter <= #1 {`TIMEOUT_BITS{1'b1}}; 84 | else if (clr) 85 | counter <= #1 {`TIMEOUT_BITS{1'b1}}; 86 | else if (|outs) 87 | counter <= #1 counter - 1'b1; 88 | 89 | 90 | endmodule 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_ch_periph_mux.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:57 2011 33 | //-- 34 | //-- Source file: dma_ch_periph_mux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | 40 | module dma_axi64_core0_ch_periph_mux(clk,reset,clken,periph_req,periph_clr,periph_ready,periph_num,clr_valid,clr); 41 | 42 | input clk; 43 | input reset; 44 | input clken; 45 | 46 | input [31:1] periph_req; 47 | output [31:1] periph_clr; 48 | output periph_ready; 49 | input [4:0] periph_num; 50 | input clr_valid; 51 | input clr; 52 | 53 | 54 | reg [31:1] periph_clr; 55 | wire [31:0] periph_req_full; 56 | wire periph_ready_pre; 57 | 58 | 59 | always @(/*AUTOSENSE*/clken or clr or clr_valid or periph_num) 60 | begin 61 | periph_clr = {31{1'b0}}; 62 | 63 | periph_clr[periph_num] = clr & clr_valid & clken; 64 | end 65 | 66 | 67 | assign periph_req_full = {periph_req, 1'b1}; //bit 0 is memory 68 | assign periph_ready_pre = periph_req_full[periph_num]; 69 | 70 | prgen_delay #(1) delay_ready (.clk(clk), .reset(reset), .din(periph_ready_pre), .dout(periph_ready)); 71 | 72 | 73 | endmodule 74 | 75 | 76 | 77 | 78 | 79 | 80 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_ch_reg_size.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:56 2011 33 | //-- 34 | //-- Source file: dma_ch_reg_size.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_ch_reg_size(clk,reset,update,start_addr,burst_max_size_reg,burst_max_size_other,allow_full_burst,allow_full_fifo,joint_flush,burst_max_size); 40 | 41 | parameter MAX_BURST = 0 ? 64 : 128; //16 strobes 42 | parameter HALF_BYTES = 32/2; 43 | parameter LARGE_FIFO = 32 > MAX_BURST; 44 | parameter SMALL_FIFO = 32 == 16; 45 | 46 | input clk; 47 | input reset; 48 | 49 | input update; 50 | 51 | input [32-1:0] start_addr; 52 | input [8-1:0] burst_max_size_reg; 53 | input [8-1:0] burst_max_size_other; 54 | 55 | input allow_full_burst; 56 | input allow_full_fifo; 57 | input joint_flush; 58 | output [8-1:0] burst_max_size; 59 | 60 | 61 | 62 | wire [8-1:0] burst_max_size_fifo; 63 | wire [8-1:0] burst_max_size_pre; 64 | reg [8-1:0] burst_max_size; 65 | 66 | 67 | 68 | 69 | assign burst_max_size_fifo = 70 | allow_full_burst | LARGE_FIFO ? MAX_BURST : 71 | joint_flush & SMALL_FIFO ? HALF_BYTES : 72 | (burst_max_size_other > HALF_BYTES) & (burst_max_size_reg > HALF_BYTES) & (burst_max_size_other != burst_max_size_reg) 73 | ? HALF_BYTES : 74 | allow_full_fifo ? 32 : HALF_BYTES; 75 | 76 | 77 | prgen_min2 #(8) min2_max( 78 | .a(burst_max_size_reg), 79 | .b(burst_max_size_fifo), 80 | .min(burst_max_size_pre) 81 | ); 82 | 83 | always @(posedge clk or posedge reset) 84 | if (reset) 85 | burst_max_size <= #1 {8{1'b0}}; 86 | else if (update) 87 | burst_max_size <= #1 burst_max_size_pre > MAX_BURST ? MAX_BURST : burst_max_size_pre; 88 | 89 | 90 | endmodule 91 | 92 | 93 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_ch_remain.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:56 2011 33 | //-- 34 | //-- Source file: dma_ch_remain.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_ch_remain(clk,reset,ch_update,wr_outstanding,rd_outstanding,load_req_in_prog,rd_line_cmd,rd_burst_start,rd_burst_size,rd_transfer,rd_transfer_size,wr_clr_line,wr_burst_start,wr_burst_size,wr_transfer,wr_transfer_size,rd_gap,wr_fullness); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input ch_update; 45 | input wr_outstanding; 46 | input rd_outstanding; 47 | input load_req_in_prog; 48 | 49 | input rd_line_cmd; 50 | input rd_burst_start; 51 | input [8-1:0] rd_burst_size; 52 | input rd_transfer; 53 | input [4-1:0] rd_transfer_size; 54 | 55 | input wr_clr_line; 56 | input wr_burst_start; 57 | input [8-1:0] wr_burst_size; 58 | input wr_transfer; 59 | input [4-1:0] wr_transfer_size; 60 | 61 | output [5:0] rd_gap; 62 | output [5:0] wr_fullness; 63 | 64 | 65 | 66 | wire rd_line_cmd_valid; 67 | reg [5+1:0] rd_gap_reg; //signed 68 | reg [5+1:0] wr_fullness_reg; //signed 69 | 70 | wire rd_burst_qual; 71 | wire wr_burst_qual; 72 | reg [8-1:0] rd_burst_size_valid; 73 | wire [4-1:0] rd_transfer_size_valid; 74 | wire [4-1:0] wr_transfer_size_valid; 75 | reg [8-1:0] wr_burst_size_valid; 76 | 77 | 78 | 79 | 80 | assign rd_line_cmd_valid = rd_line_cmd & rd_burst_start; 81 | 82 | assign rd_burst_qual = rd_burst_start & (~load_req_in_prog); 83 | assign wr_burst_qual = wr_burst_start; 84 | 85 | always @(posedge clk or posedge reset) 86 | if (reset) 87 | rd_burst_size_valid <= #1 {8{1'b0}}; 88 | else if (rd_burst_qual) 89 | rd_burst_size_valid <= #1 rd_burst_size; 90 | else 91 | rd_burst_size_valid <= #1 {8{1'b0}}; 92 | 93 | always @(posedge clk or posedge reset) 94 | if (reset) 95 | wr_burst_size_valid <= #1 {8{1'b0}}; 96 | else if (wr_burst_qual) 97 | wr_burst_size_valid <= #1 wr_burst_size; 98 | else 99 | wr_burst_size_valid <= #1 {8{1'b0}}; 100 | 101 | assign rd_transfer_size_valid = {4{rd_transfer}} & rd_transfer_size; 102 | assign wr_transfer_size_valid = {4{wr_transfer}} & wr_transfer_size; 103 | 104 | 105 | //for rd bursts 106 | always @(posedge clk or posedge reset) 107 | if (reset) 108 | rd_gap_reg <= #1 {1'b0, 1'b1, {5{1'b0}}}; 109 | else if (ch_update) 110 | rd_gap_reg <= #1 {1'b0, 1'b1, {5{1'b0}}}; 111 | else 112 | rd_gap_reg <= #1 rd_gap_reg - 113 | rd_burst_size_valid + 114 | wr_transfer_size_valid; 115 | 116 | 117 | assign rd_gap = rd_gap_reg[5+1] ? 'd0 : rd_gap_reg[5:0]; 118 | 119 | 120 | //for wr bursts 121 | always @(posedge clk or posedge reset) 122 | if (reset) 123 | wr_fullness_reg <= #1 {5+1{1'b0}}; 124 | else if (ch_update) 125 | wr_fullness_reg <= #1 {5+1{1'b0}}; 126 | else 127 | wr_fullness_reg <= #1 wr_fullness_reg - 128 | wr_burst_size_valid + 129 | rd_transfer_size_valid; 130 | 131 | 132 | assign wr_fullness = wr_fullness_reg[5+1] ? 'd0 : wr_fullness_reg[5:0]; 133 | 134 | endmodule 135 | 136 | 137 | 138 | 139 | 140 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_channels_apb_mux.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:55 2011 33 | //-- 34 | //-- Source file: dma_core_channels_apb_mux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_channels_apb_mux (clk,reset,pclken,psel,penable,paddr,prdata,pslverr,ch_psel,ch_prdata,ch_pslverr); 40 | 41 | input clk; 42 | input reset; 43 | 44 | input pclken; 45 | input psel; 46 | input penable; 47 | input [10:8] paddr; 48 | output [31:0] prdata; 49 | output pslverr; 50 | 51 | output [7:0] ch_psel; 52 | input [32*8-1:0] ch_prdata; 53 | input [7:0] ch_pslverr; 54 | 55 | 56 | wire [2:0] paddr_sel; 57 | reg [2:0] paddr_sel_d; 58 | 59 | 60 | 61 | always @(posedge clk or posedge reset) 62 | if (reset) 63 | paddr_sel_d <= #1 3'b000; 64 | else if (psel & (~penable)) 65 | paddr_sel_d <= #1 paddr_sel; 66 | else if ((~psel) & pclken) //release for empty channels after error 67 | paddr_sel_d <= #1 3'b000; 68 | 69 | 70 | 71 | assign paddr_sel = paddr[10:8]; 72 | 73 | prgen_demux8 #(1) mux_psel( 74 | .sel(paddr_sel), 75 | .x(psel), 76 | .ch_x(ch_psel) 77 | ); 78 | 79 | 80 | prgen_mux8 #(32) mux_prdata( 81 | .sel(paddr_sel_d), 82 | 83 | .ch_x(ch_prdata), 84 | .x(prdata) 85 | ); 86 | 87 | 88 | assign pslverr = ch_pslverr[paddr_sel_d]; 89 | 90 | endmodule 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_core0_wdt.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:53 2011 33 | //-- 34 | //-- Source file: dma_core_wdt.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module dma_axi64_core0_wdt(clk,reset,ch_active,rd_burst_start,rd_ch_num,wr_burst_start,wr_ch_num,wdt_timeout,wdt_ch_num); 40 | 41 | 42 | input clk; 43 | input reset; 44 | 45 | input [7:0] ch_active; 46 | input rd_burst_start; 47 | input [2:0] rd_ch_num; 48 | input wr_burst_start; 49 | input [2:0] wr_ch_num; 50 | 51 | output wdt_timeout; 52 | output [2:0] wdt_ch_num; 53 | 54 | 55 | 56 | reg [`WDT_BITS-1:0] counter; 57 | reg [2:0] wdt_ch_num; 58 | wire current_ch_active; 59 | wire current_burst_start; 60 | wire advance; 61 | wire idle; 62 | 63 | 64 | 65 | assign idle = ch_active == 8'd0; 66 | 67 | assign current_ch_active = ch_active[wdt_ch_num]; 68 | 69 | assign current_burst_start = 70 | (rd_burst_start & (rd_ch_num == wdt_ch_num)) | 71 | (wr_burst_start & (wr_ch_num == wdt_ch_num)); 72 | 73 | assign advance = (!current_ch_active) | current_burst_start | wdt_timeout; 74 | 75 | 76 | always @(posedge clk or posedge reset) 77 | if (reset) 78 | wdt_ch_num <= #1 3'd0; 79 | else if (advance) 80 | wdt_ch_num <= #1 wdt_ch_num + 1'b1; 81 | 82 | 83 | 84 | 85 | assign wdt_timeout = (counter == 'd0); 86 | 87 | 88 | always @(posedge clk or posedge reset) 89 | if (reset) 90 | counter <= #1 {`WDT_BITS{1'b1}}; 91 | else if (advance | idle) 92 | counter <= #1 {`WDT_BITS{1'b1}}; 93 | else 94 | counter <= #1 counter - 1'b1; 95 | 96 | 97 | endmodule 98 | 99 | 100 | 101 | 102 | 103 | 104 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_defines.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:53 2011 33 | //-- 34 | //-- Source file: dma_defines.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | `define FRAME_BITS 12 40 | `define X_BITS 8 41 | `define TOKEN_BITS 6 42 | `define OUT_BITS 4 43 | `define DELAY_BITS 3 44 | `define CMD_CNT_BITS 12 45 | `define INT_CNT_BITS 4 46 | `define WAIT_BITS 12 47 | `define TIMEOUT_BITS 10 48 | `define WDT_BITS 11 49 | `define CMD_BITS 7 50 | `define ID_BITS 1 51 | `define LEN_BITS 4 52 | `define SIZE_BITS 2 53 | 54 | `define ID_END_LINE 6 55 | `define ID_LAST 3 56 | 57 | 58 | 59 | 60 | -------------------------------------------------------------------------------- /src/dma_axi64/dma_axi64_reg_params.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:53 2011 33 | //-- 34 | //-- Source file: dma_reg_params.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | 40 | parameter PROC0_STATUS = 8'h00; 41 | parameter PROC1_STATUS = 8'h04; 42 | parameter PROC2_STATUS = 8'h08; 43 | parameter PROC3_STATUS = 8'h0C; 44 | parameter PROC4_STATUS = 8'h10; 45 | parameter PROC5_STATUS = 8'h14; 46 | parameter PROC6_STATUS = 8'h18; 47 | parameter PROC7_STATUS = 8'h1C; 48 | parameter CORE0_JOINT = 8'h30; 49 | parameter CORE1_JOINT = 8'h34; 50 | parameter CORE0_PRIO = 8'h38; 51 | parameter CORE1_PRIO = 8'h3C; 52 | parameter CORE0_CLKDIV = 8'h40; 53 | parameter CORE1_CLKDIV = 8'h44; 54 | parameter CORE0_START = 8'h48; 55 | parameter CORE1_START = 8'h4C; 56 | parameter PERIPH_RX_CTRL = 8'h50; 57 | parameter PERIPH_TX_CTRL = 8'h54; 58 | parameter IDLE = 8'hD0; 59 | parameter USER_DEF_STAT = 8'hE0; 60 | parameter USER_DEF0_STAT0 = 8'hF0; 61 | parameter USER_DEF0_STAT1 = 8'hF4; 62 | parameter USER_DEF1_STAT0 = 8'hF8; 63 | parameter USER_DEF1_STAT1 = 8'hFC; 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | -------------------------------------------------------------------------------- /src/dma_axi64/filelist.txt: -------------------------------------------------------------------------------- 1 | dma_axi64.v 2 | dma_axi64_dual_core.v 3 | dma_axi64_apb_mux.v 4 | dma_axi64_reg.v 5 | dma_axi64_reg_core0.v 6 | prgen_scatter8_1.v 7 | dma_axi64_core0_top.v 8 | dma_axi64_core0.v 9 | dma_axi64_core0_wdt.v 10 | dma_axi64_core0_arbiter.v 11 | dma_axi64_core0_ctrl.v 12 | dma_axi64_core0_axim_wr.v 13 | dma_axi64_core0_axim_cmd.v 14 | dma_axi64_core0_axim_timeout.v 15 | dma_axi64_core0_axim_wdata.v 16 | prgen_joint_stall.v 17 | prgen_fifo.v 18 | prgen_stall.v 19 | dma_axi64_core0_axim_resp.v 20 | dma_axi64_core0_axim_rd.v 21 | dma_axi64_core0_axim_rdata.v 22 | dma_axi64_core0_channels.v 23 | dma_axi64_core0_channels_apb_mux.v 24 | dma_axi64_core0_channels_mux.v 25 | prgen_or8.v 26 | prgen_mux8.v 27 | prgen_demux8.v 28 | dma_axi64_core0_ch.v 29 | dma_axi64_core0_ch_reg.v 30 | dma_axi64_core0_ch_reg_size.v 31 | prgen_rawstat.v 32 | dma_axi64_core0_ch_offsets.v 33 | dma_axi64_core0_ch_remain.v 34 | dma_axi64_core0_ch_outs.v 35 | dma_axi64_core0_ch_calc.v 36 | dma_axi64_core0_ch_calc_addr.v 37 | dma_axi64_core0_ch_calc_size.v 38 | prgen_min3.v 39 | prgen_min2.v 40 | dma_axi64_core0_ch_calc_joint.v 41 | dma_axi64_core0_ch_periph_mux.v 42 | dma_axi64_core0_ch_fifo_ctrl.v 43 | dma_axi64_core0_ch_wr_slicer.v 44 | prgen_swap_64.v 45 | prgen_swap_32.v 46 | dma_axi64_core0_ch_rd_slicer.v 47 | dma_axi64_core0_ch_fifo_ptr.v 48 | dma_axi64_core0_ch_fifo.v 49 | dma_axi64_core0_ch_empty.v 50 | prgen_delay.v 51 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_delay.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:57 2011 33 | //-- 34 | //-- Source file: prgen_delay.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_delay(clk,reset,din,dout); 40 | 41 | 42 | input clk; 43 | input reset; 44 | 45 | input din; 46 | output dout; 47 | 48 | parameter DELAY = 2; 49 | 50 | 51 | reg [DELAY:0] shift_reg; 52 | 53 | always @(posedge clk or posedge reset) 54 | if (reset) 55 | shift_reg <= #1 {DELAY+1{1'b0}}; 56 | else 57 | shift_reg <= #1 {shift_reg[DELAY-1:0], din}; 58 | 59 | assign dout = shift_reg[DELAY-1]; 60 | 61 | 62 | endmodule 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_demux8.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:55 2011 33 | //-- 34 | //-- Source file: prgen_demux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | 40 | module prgen_demux8(sel,x,ch_x); 41 | 42 | parameter WIDTH = 8; 43 | 44 | 45 | input [3-1:0] sel; 46 | input [WIDTH-1:0] x; 47 | output [8*WIDTH-1:0] ch_x; 48 | 49 | 50 | reg [8*WIDTH-1:0] ch_x; 51 | 52 | 53 | 54 | always @(/*AUTOSENSE*/sel or x) 55 | begin 56 | ch_x = {8*WIDTH{1'b0}}; 57 | 58 | case (sel) 59 | 3'd0 : ch_x[WIDTH-1+WIDTH*0:WIDTH*0] = x; 60 | 3'd1 : ch_x[WIDTH-1+WIDTH*1:WIDTH*1] = x; 61 | 3'd2 : ch_x[WIDTH-1+WIDTH*2:WIDTH*2] = x; 62 | 3'd3 : ch_x[WIDTH-1+WIDTH*3:WIDTH*3] = x; 63 | 3'd4 : ch_x[WIDTH-1+WIDTH*4:WIDTH*4] = x; 64 | 3'd5 : ch_x[WIDTH-1+WIDTH*5:WIDTH*5] = x; 65 | 3'd6 : ch_x[WIDTH-1+WIDTH*6:WIDTH*6] = x; 66 | 3'd7 : ch_x[WIDTH-1+WIDTH*7:WIDTH*7] = x; 67 | 68 | default : 69 | ch_x[WIDTH-1:0] = x; 70 | endcase 71 | end 72 | 73 | 74 | endmodule 75 | 76 | 77 | 78 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_joint_stall.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:54 2011 33 | //-- 34 | //-- Source file: prgen_joint_stall.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_joint_stall(clk,reset,joint_req_out,rd_transfer,rd_transfer_size,ch_fifo_rd,data_fullness_pre,HOLD,joint_fifo_rd_valid,rd_transfer_size_joint,rd_transfer_full,joint_stall); 40 | 41 | parameter SIZE_BITS = 1; 42 | 43 | input clk; 44 | input reset; 45 | 46 | input joint_req_out; 47 | input rd_transfer; 48 | input [SIZE_BITS-1:0] rd_transfer_size; 49 | input ch_fifo_rd; 50 | input [2:0] data_fullness_pre; 51 | input HOLD; 52 | 53 | output joint_fifo_rd_valid; 54 | output [SIZE_BITS-1:0] rd_transfer_size_joint; 55 | output rd_transfer_full; 56 | output joint_stall; 57 | 58 | 59 | 60 | 61 | wire rd_transfer_joint; 62 | wire joint_fifo_rd; 63 | wire joint_fifo_rd_valid; 64 | wire [2:0] count_ch_fifo_pre; 65 | reg [2:0] count_ch_fifo; 66 | wire joint_stall_pre; 67 | reg joint_stall_reg; 68 | wire joint_not_ready_pre; 69 | wire joint_not_ready; 70 | wire [SIZE_BITS-1:0] rd_transfer_size_joint; 71 | wire rd_transfer_full; 72 | reg [2:0] joint_rd_stall_num; 73 | wire joint_rd_stall; 74 | 75 | 76 | 77 | 78 | assign rd_transfer_joint = joint_req_out & rd_transfer; 79 | 80 | prgen_delay #(2) delay_joint_fifo_rd (.clk(clk), .reset(reset), .din(rd_transfer_joint), .dout(joint_fifo_rd)); 81 | 82 | assign count_ch_fifo_pre = count_ch_fifo + rd_transfer_joint - ch_fifo_rd; 83 | 84 | //count fullness of channel's fifo 85 | always @(posedge clk or posedge reset) 86 | if (reset) 87 | count_ch_fifo <= #1 3'd0; 88 | else if (joint_req_out & (rd_transfer_joint | ch_fifo_rd)) 89 | count_ch_fifo <= #1 count_ch_fifo_pre; 90 | 91 | //prevent read channel to overflow the channel's fifo 92 | assign joint_stall_pre = joint_req_out & ((count_ch_fifo_pre > 'd2) | ((count_ch_fifo_pre == 'd2) & (data_fullness_pre > 'd1)) | HOLD); 93 | 94 | //prevent write channel to overflow the wr data fifo 95 | assign joint_not_ready_pre = joint_req_out & (data_fullness_pre > 'd1) & (~(rd_transfer_joint & joint_stall_pre)); 96 | 97 | 98 | always @(posedge clk or posedge reset) 99 | if (reset) 100 | joint_stall_reg <= #1 1'b0; 101 | else if (joint_stall_pre) 102 | joint_stall_reg <= #1 1'b1; 103 | else if (count_ch_fifo_pre == 'd0) 104 | joint_stall_reg <= #1 1'b0; 105 | 106 | assign joint_stall = joint_stall_reg | (joint_req_out & HOLD); 107 | 108 | prgen_delay #(1) delay_joint_not_ready (.clk(clk), .reset(reset), .din(joint_not_ready_pre), .dout(joint_not_ready)); 109 | 110 | 111 | prgen_fifo #(SIZE_BITS, 2) 112 | rd_transfer_fifo( 113 | .clk(clk), 114 | .reset(reset), 115 | .push(rd_transfer_joint), 116 | .pop(joint_fifo_rd_valid), 117 | .din(rd_transfer_size), 118 | .dout(rd_transfer_size_joint), 119 | .empty(), 120 | .full(rd_transfer_full) 121 | ); 122 | 123 | prgen_stall #(3) stall_joint_fifo_rd (.clk(clk), .reset(reset), .din(joint_fifo_rd), .stall(joint_not_ready), .dout(joint_fifo_rd_valid)); 124 | 125 | 126 | endmodule 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_min2.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:57 2011 33 | //-- 34 | //-- Source file: prgen_min2.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_min2(a,b,min); 40 | 41 | parameter WIDTH = 8; 42 | 43 | input [WIDTH-1:0] a; 44 | input [WIDTH-1:0] b; 45 | 46 | output [WIDTH-1:0] min; 47 | 48 | 49 | assign min = a < b ? a : b; 50 | 51 | endmodule 52 | 53 | 54 | 55 | 56 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_min3.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:56 2011 33 | //-- 34 | //-- Source file: prgen_min3.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_min3(clk,reset,a,b,c,min); 40 | 41 | parameter WIDTH = 8; 42 | 43 | input clk; 44 | input reset; 45 | input [WIDTH-1:0] a; 46 | input [WIDTH-1:0] b; 47 | input [WIDTH-1:0] c; 48 | 49 | output [WIDTH-1:0] min; 50 | 51 | wire [WIDTH-1:0] min_ab_pre; 52 | reg [WIDTH-1:0] min_ab; 53 | reg [WIDTH-1:0] min_c; 54 | 55 | 56 | prgen_min2 #(WIDTH) min2_ab( 57 | .a(a), 58 | .b(b), 59 | .min(min_ab_pre) 60 | ); 61 | 62 | prgen_min2 #(WIDTH) min2_abc( 63 | .a(min_ab), 64 | .b(min_c), 65 | .min(min) 66 | ); 67 | 68 | always @(posedge clk or posedge reset) 69 | if (reset) 70 | begin 71 | min_ab <= #1 {WIDTH{1'b0}}; 72 | min_c <= #1 {WIDTH{1'b0}}; 73 | end 74 | else 75 | begin 76 | min_ab <= #1 min_ab_pre; 77 | min_c <= #1 c; 78 | end 79 | 80 | endmodule 81 | 82 | 83 | 84 | 85 | 86 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_mux8.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:55 2011 33 | //-- 34 | //-- Source file: prgen_mux.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | 40 | module prgen_mux8(sel,ch_x,x); 41 | 42 | parameter WIDTH = 8; 43 | 44 | 45 | input [3-1:0] sel; 46 | input [8*WIDTH-1:0] ch_x; 47 | output [WIDTH-1:0] x; 48 | 49 | 50 | reg [WIDTH-1:0] x; 51 | 52 | 53 | always @(/*AUTOSENSE*/ch_x or sel) 54 | begin 55 | case (sel) 56 | 3'd0 :x = ch_x[WIDTH-1+WIDTH*0:WIDTH*0]; 57 | 3'd1 :x = ch_x[WIDTH-1+WIDTH*1:WIDTH*1]; 58 | 3'd2 :x = ch_x[WIDTH-1+WIDTH*2:WIDTH*2]; 59 | 3'd3 :x = ch_x[WIDTH-1+WIDTH*3:WIDTH*3]; 60 | 3'd4 :x = ch_x[WIDTH-1+WIDTH*4:WIDTH*4]; 61 | 3'd5 :x = ch_x[WIDTH-1+WIDTH*5:WIDTH*5]; 62 | 3'd6 :x = ch_x[WIDTH-1+WIDTH*6:WIDTH*6]; 63 | 3'd7 :x = ch_x[WIDTH-1+WIDTH*7:WIDTH*7]; 64 | 65 | default : 66 | x = ch_x[WIDTH-1:0]; 67 | endcase 68 | end 69 | 70 | 71 | endmodule 72 | 73 | 74 | 75 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_or8.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:55 2011 33 | //-- 34 | //-- Source file: prgen_or.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_or8(ch_x,x); 40 | 41 | parameter WIDTH = 8; 42 | 43 | 44 | input [8*WIDTH-1:0] ch_x; 45 | output [WIDTH-1:0] x; 46 | 47 | 48 | assign x = 49 | ch_x[WIDTH-1+WIDTH*0:WIDTH*0] | 50 | ch_x[WIDTH-1+WIDTH*1:WIDTH*1] | 51 | ch_x[WIDTH-1+WIDTH*2:WIDTH*2] | 52 | ch_x[WIDTH-1+WIDTH*3:WIDTH*3] | 53 | ch_x[WIDTH-1+WIDTH*4:WIDTH*4] | 54 | ch_x[WIDTH-1+WIDTH*5:WIDTH*5] | 55 | ch_x[WIDTH-1+WIDTH*6:WIDTH*6] | 56 | ch_x[WIDTH-1+WIDTH*7:WIDTH*7] ; 57 | 58 | endmodule 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_rawstat.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:56 2011 33 | //-- 34 | //-- Source file: prgen_rawstat.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_rawstat (clk,reset,clear,write,pwdata,int_bus,rawstat); 40 | 41 | parameter SIZE = 32; 42 | 43 | input clk; 44 | input reset; 45 | 46 | input clear; 47 | input write; 48 | input [SIZE-1:0] pwdata; 49 | input [SIZE-1:0] int_bus; 50 | 51 | output [SIZE-1:0] rawstat; 52 | 53 | 54 | 55 | reg [SIZE-1:0] rawstat; 56 | wire [SIZE-1:0] write_bus; 57 | wire [SIZE-1:0] clear_bus; 58 | 59 | 60 | assign write_bus = {SIZE{write}} & pwdata; 61 | assign clear_bus = {SIZE{clear}} & pwdata; 62 | 63 | 64 | always @(posedge clk or posedge reset) 65 | if (reset) 66 | rawstat <= #1 {SIZE{1'b0}}; 67 | else 68 | rawstat <= #1 (rawstat | int_bus | write_bus) & (~clear_bus); 69 | 70 | endmodule 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_scatter8_1.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:53 2011 33 | //-- 34 | //-- Source file: prgen_scatter.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_scatter8_1(ch_x,x); 40 | 41 | parameter CH_NUM = 0; 42 | 43 | 44 | input [8*1-1:0] ch_x; 45 | output [8-1:0] x; 46 | 47 | 48 | assign x = { 49 | ch_x[CH_NUM+7], 50 | ch_x[CH_NUM+6], 51 | ch_x[CH_NUM+5], 52 | ch_x[CH_NUM+4], 53 | ch_x[CH_NUM+3], 54 | ch_x[CH_NUM+2], 55 | ch_x[CH_NUM+1], 56 | ch_x[CH_NUM+0]}; 57 | 58 | 59 | endmodule 60 | 61 | 62 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_stall.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:54 2011 33 | //-- 34 | //-- Source file: prgen_stall.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_stall(clk,reset,din,stall,dout); 40 | 41 | parameter DEPTH = 1; 42 | 43 | input clk; 44 | input reset; 45 | 46 | input din; 47 | input stall; 48 | output dout; 49 | 50 | 51 | 52 | reg [DEPTH-1:0] count; 53 | wire pend; 54 | 55 | 56 | always @(posedge clk or posedge reset) 57 | if (reset) 58 | count <= #1 {DEPTH{1'b0}}; 59 | else if (pend & (~stall)) 60 | count <= #1 count - 1'b1; 61 | else if (din & stall) 62 | count <= #1 count + 1'b1; 63 | 64 | assign pend = (|count); 65 | assign dout = (din | pend) & (~stall); 66 | 67 | 68 | 69 | 70 | 71 | endmodule 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_swap_32.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:57 2011 33 | //-- 34 | //-- Source file: prgen_swap32.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_swap32 (end_swap,data_in,data_out,bsel_in,bsel_out); 40 | 41 | input [1:0] end_swap; 42 | input [31:0] data_in; 43 | output [31:0] data_out; 44 | input [3:0] bsel_in; 45 | output [3:0] bsel_out; 46 | 47 | 48 | reg [31:0] data_out; 49 | reg [3:0] bsel_out; 50 | 51 | 52 | 53 | always @(/*AUTOSENSE*/data_in or end_swap) 54 | begin 55 | case (end_swap[1:0]) 56 | 2'b00 : data_out = data_in; 57 | 2'b01 : data_out = {data_in[23:16], data_in[31:24], data_in[7:0], data_in[15:8]}; 58 | 2'b10 : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]}; 59 | 2'b11 : data_out = {data_in[7:0], data_in[15:8], data_in[23:16], data_in[31:24]}; 60 | endcase 61 | end 62 | 63 | always @(/*AUTOSENSE*/bsel_in or end_swap) 64 | begin 65 | case (end_swap[1:0]) 66 | 2'b00 : bsel_out = bsel_in; 67 | 2'b01 : bsel_out = {bsel_in[2], bsel_in[3], bsel_in[0], bsel_in[1]}; 68 | 2'b10 : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]}; 69 | 2'b11 : bsel_out = {bsel_in[0], bsel_in[1], bsel_in[2], bsel_in[3]}; 70 | endcase 71 | end 72 | 73 | 74 | endmodule 75 | 76 | 77 | 78 | -------------------------------------------------------------------------------- /src/dma_axi64/prgen_swap_64.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Author: Eyal Hochberg //// 4 | //// eyal@provartec.com //// 5 | //// //// 6 | //// Downloaded from: http://www.opencores.org //// 7 | ///////////////////////////////////////////////////////////////////// 8 | //// //// 9 | //// Copyright (C) 2010 Provartec LTD //// 10 | //// www.provartec.com //// 11 | //// info@provartec.com //// 12 | //// //// 13 | //// This source file may be used and distributed without //// 14 | //// restriction provided that this copyright statement is not //// 15 | //// removed from the file and that any derivative work contains //// 16 | //// the original copyright notice and the associated disclaimer.//// 17 | //// //// 18 | //// This source file is free software; you can redistribute it //// 19 | //// and/or modify it under the terms of the GNU Lesser General //// 20 | //// Public License as published by the Free Software Foundation.//// 21 | //// //// 22 | //// This source is distributed in the hope that it will be //// 23 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 24 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 25 | //// PURPOSE. See the GNU Lesser General Public License for more//// 26 | //// details. http://www.gnu.org/licenses/lgpl.html //// 27 | //// //// 28 | ///////////////////////////////////////////////////////////////////// 29 | //--------------------------------------------------------- 30 | //-- File generated by RobustVerilog parser 31 | //-- Version: 1.0 32 | //-- Invoked Fri Mar 25 23:36:57 2011 33 | //-- 34 | //-- Source file: prgen_swap64.v 35 | //--------------------------------------------------------- 36 | 37 | 38 | 39 | module prgen_swap64 (end_swap,data_in,data_out,bsel_in,bsel_out); 40 | 41 | input [1:0] end_swap; 42 | input [63:0] data_in; 43 | output [63:0] data_out; 44 | input [7:0] bsel_in; 45 | output [7:0] bsel_out; 46 | 47 | 48 | wire [31:0] data_in_low; 49 | wire [31:0] data_in_high; 50 | wire [31:0] data_out_low; 51 | wire [31:0] data_out_high; 52 | wire [3:0] bsel_in_low; 53 | wire [3:0] bsel_in_high; 54 | wire [3:0] bsel_out_low; 55 | wire [3:0] bsel_out_high; 56 | 57 | 58 | 59 | assign data_in_low = end_swap == 2'b11 ? data_in[63:32] : data_in[31:0]; 60 | assign data_in_high = end_swap == 2'b11 ? data_in[31:0] : data_in[63:32]; 61 | 62 | assign bsel_in_low = end_swap == 2'b11 ? bsel_in[7:4] : bsel_in[3:0]; 63 | assign bsel_in_high = end_swap == 2'b11 ? bsel_in[3:0] : bsel_in[7:4]; 64 | 65 | prgen_swap32 swap32_low( 66 | .end_swap(end_swap), 67 | .data_in(data_in_low), 68 | .data_out(data_out_low), 69 | .bsel_in(bsel_in_low), 70 | .bsel_out(bsel_out_low) 71 | ); 72 | 73 | prgen_swap32 swap32_high( 74 | .end_swap(end_swap), 75 | .data_in(data_in_high), 76 | .data_out(data_out_high), 77 | .bsel_in(bsel_in_high), 78 | .bsel_out(bsel_out_high) 79 | ); 80 | 81 | assign data_out = {data_out_high, data_out_low}; 82 | assign bsel_out = {bsel_out_high, bsel_out_low}; 83 | 84 | endmodule 85 | 86 | 87 | 88 | --------------------------------------------------------------------------------