├── SOC_Design.pdf ├── Verilog ├── sdram.v ├── sdram_mux.v ├── MUX12.V ├── MUX16.V ├── PC.V ├── cmd_ack.v ├── data_in_reg.v ├── sdram_port.v ├── ref_timer.v ├── MEM.V ├── cmd_internal_reg.v ├── ACC.V ├── IR.V ├── ref_ack.v ├── sdram_cntrl.v ├── ras_cas_delay.v ├── dma_fifo.v ├── data_cache_way0.v ├── data_cache_way1.v ├── data_cache_way2.v ├── data_cache_way3.v ├── instruction_cache_way0.v ├── instruction_cache_way1.v ├── instruction_cache_way2.v ├── instruction_cache_way3.v ├── cmd_decoder.v ├── parameter.v ├── data_port.v ├── command_if.v ├── oe_generator.v ├── sdramctrl_rtl.v ├── flash_ctrl.v ├── timer.v ├── ALU.V ├── fsm.v ├── cmd_detector.v ├── cmd_generator.v ├── uart.v ├── dma_cntrl.v ├── dma_internal_reg.v ├── bus_arbiter.v ├── risc.v ├── lru_data_cache.v ├── lru_instruction_cache.v ├── soc.v └── CONTROL.V ├── Test_Bench_Verilog └── Top_level_tb.tf └── Machine_Language └── program.txt /SOC_Design.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/embedded_risc/HEAD/SOC_Design.pdf -------------------------------------------------------------------------------- /Verilog/sdram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/embedded_risc/HEAD/Verilog/sdram.v -------------------------------------------------------------------------------- /Verilog/sdram_mux.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Data Multiplexer 3 | 4 | FILE NAME: sdram_mux.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will generate a multiplexor for SDRAM data path. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module sdram_mux( // Input 24 | sdram_out, 25 | oe, 26 | // Output 27 | dq 28 | ); 29 | 30 | 31 | // Parameter 32 | `include "parameter.v" 33 | 34 | // Input 35 | input [data_size - 1 : 0]sdram_out; 36 | input oe; 37 | 38 | // Output 39 | output [data_size - 1 : 0]dq; 40 | 41 | // Internal wire and reg signals 42 | 43 | 44 | // Assignment 45 | assign dq = oe ? sdram_out : 32'hzzzz_zzzz; 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /Verilog/MUX12.V: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Sub Level Multiplexer Block 3 | 4 | FILE NAME: mux12.v 5 | VERSION: 1.0 6 | DATE: September 28th, 2001 7 | AUTHOR: Hossein Amidi 8 | COMPANY: California Unique Electrical Co. 9 | CODE TYPE: Register Transfer Level 10 | 11 | Instantiations: 12 | 13 | DESCRIPTION: 14 | Sub Level RTL Multiplexer block 15 | 16 | Hossein Amidi 17 | (C) September 2001 18 | California Unique Electric 19 | 20 | ***************************************************************************************/ 21 | 22 | `timescale 1ns / 1ps 23 | 24 | module MUX12 ( // Input 25 | A_in, 26 | B_in, 27 | A_Select, 28 | // Output 29 | Out 30 | ); 31 | 32 | 33 | // Parameter 34 | parameter AddrWidth = 24; 35 | 36 | 37 | // Input 38 | input [AddrWidth - 1 : 0] A_in; 39 | input [AddrWidth - 1 : 0] B_in; 40 | input A_Select; 41 | 42 | // Output 43 | output [AddrWidth - 1 : 0] Out; 44 | 45 | 46 | //Dataflow description of MUX12 47 | assign Out = A_Select ? A_in : B_in; 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /Verilog/MUX16.V: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Sub Level Multiplexer Block 3 | 4 | FILE NAME: mux16.v 5 | VERSION: 1.0 6 | DATE: September 28th, 2001 7 | AUTHOR: Hossein Amidi 8 | COMPANY: California Unique Electrical Co. 9 | CODE TYPE: Register Transfer Level 10 | 11 | Instantiations: 12 | 13 | DESCRIPTION: 14 | Sub Level RTL Multiplexer block 15 | 16 | Hossein Amidi 17 | (C) September 2001 18 | California Unique Electric 19 | 20 | ***************************************************************************************/ 21 | 22 | `timescale 1ns / 1ps 23 | 24 | module MUX16 ( // Input 25 | A_in, 26 | B_in, 27 | A_Select, 28 | // Output 29 | Out 30 | ); 31 | 32 | // Parameter 33 | parameter DataWidth = 32; 34 | parameter AddrWidth = 24; 35 | 36 | // Input 37 | input [AddrWidth - 1 : 0] A_in; 38 | input [DataWidth - 1 : 0] B_in; 39 | input A_Select; 40 | 41 | // Output 42 | output [DataWidth - 1 : 0] Out; 43 | 44 | //Dataflow description of MUX16 45 | 46 | assign Out = A_Select ? B_in : {8'b0, A_in}; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /Verilog/PC.V: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Sub Level Program Counter Block 3 | 4 | FILE NAME: pc.v 5 | VERSION: 1.0 6 | DATE: September 28th, 2001 7 | AUTHOR: Hossein Amidi 8 | COMPANY: California Unique Electrical Co. 9 | CODE TYPE: Register Transfer Level 10 | 11 | Instantiations: 12 | 13 | DESCRIPTION: 14 | Sub Level RTL Program Counter block 15 | 16 | Hossein Amidi 17 | (C) September 2001 18 | California Unique Electric 19 | 20 | ***************************************************************************************/ 21 | 22 | `timescale 1ns / 1ps 23 | 24 | module PC ( // Input 25 | clock, 26 | reset, 27 | PCInEn, 28 | PCDataIn, 29 | // Output 30 | PCDataOut 31 | ); 32 | 33 | // Parameter 34 | parameter AddrWidth = 24; 35 | 36 | // Inputs 37 | input clock; 38 | input reset; 39 | input PCInEn; 40 | input [AddrWidth - 1 : 0] PCDataIn; 41 | 42 | // Outputs 43 | output [AddrWidth - 1 : 0] PCDataOut; 44 | 45 | // Signal Declerations 46 | reg [AddrWidth - 1 : 0] PCDataOut; 47 | 48 | 49 | // Main Block 50 | always @ (posedge reset or negedge clock) 51 | begin 52 | if(reset == 1'b1) 53 | PCDataOut <= 24'h000; 54 | else 55 | if (PCInEn == 1'b1) 56 | PCDataOut <= PCDataIn; 57 | else 58 | PCDataOut <= PCDataOut; 59 | end 60 | endmodule 61 | -------------------------------------------------------------------------------- /Verilog/cmd_ack.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Command Acknowledge 3 | 4 | FILE NAME: cmd_ack.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will generate the command acknowledge signal. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module cmd_ack(// Input 24 | reset, 25 | clk0, 26 | cmack, 27 | load_time, 28 | load_rfcnt, 29 | // Output 30 | cmdack 31 | ); 32 | 33 | 34 | // Parameter 35 | `include "parameter.v" 36 | 37 | // Input 38 | input reset; 39 | input clk0; 40 | input cmack; 41 | input load_time; 42 | input load_rfcnt; 43 | 44 | // Output 45 | output cmdack; 46 | 47 | // Internal wire and reg signals 48 | reg cmdack; 49 | 50 | // Assignment 51 | 52 | // Generating CMDACK Signal 53 | always @(posedge reset or posedge clk0) 54 | begin 55 | if(reset == 1'b1) 56 | cmdack <= 1'b0; 57 | else 58 | begin 59 | if(((cmack == 1'b1) | (load_time == 1'b1) | (load_rfcnt == 1'b1)) & (cmdack == 1'b0)) 60 | cmdack <= 1'b1; 61 | else 62 | cmdack <= 1'b0; 63 | end 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /Verilog/data_in_reg.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Controller Data input register 3 | 4 | FILE NAME: data_in_reg.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It is the Controller input Data Port register block. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module data_in_reg(// Input 24 | reset, 25 | clk0, 26 | dm, 27 | datain, 28 | // Out 29 | dqm, 30 | datain2 31 | ); 32 | 33 | 34 | // Parameter 35 | `include "parameter.v" 36 | 37 | // Input 38 | input reset; 39 | input clk0; 40 | input [dqm_size - 1 : 0]dm; 41 | input [data_size - 1 : 0]datain; 42 | 43 | // Output 44 | output [dqm_size - 1 : 0]dqm; 45 | output [data_size - 1 : 0]datain2; 46 | 47 | 48 | // Internal wires and reg 49 | reg [data_size - 1 : 0]datain1; 50 | reg [data_size - 1 : 0]datain2; 51 | reg [dqm_size - 1 : 0]dqm; 52 | 53 | wire [data_size - 1 : 0]datain; 54 | wire [dqm_size - 1 : 0]dm; 55 | 56 | 57 | 58 | // Assignment 59 | 60 | // Register the input data from the host to match the internal timing 61 | // and avoid metastability issues by double registering it. 62 | always @(posedge reset or posedge clk0) 63 | begin 64 | if(reset == 1'b1) 65 | begin 66 | datain1 <= 32'h0; 67 | datain2 <= 32'h0; 68 | dqm <= 4'h0; 69 | end 70 | else 71 | begin 72 | datain1 <= datain; 73 | datain2 <= datain1; 74 | dqm <= dm; 75 | end 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /Verilog/sdram_port.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Controller, SDRAM Data Port 3 | 4 | FILE NAME: sdram_port.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It is the SDRAM Data Port block. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module sdram_port(// Input 24 | reset, 25 | clk0_2x, 26 | oe, 27 | datain2, 28 | dq, 29 | // Output 30 | sdram_in, 31 | sdram_out 32 | ); 33 | 34 | 35 | // Parameter 36 | `include "parameter.v" 37 | 38 | // Input 39 | input reset; 40 | input clk0_2x; 41 | input oe; 42 | input [data_size - 1 : 0]datain2; 43 | input [data_size - 1 : 0]dq; 44 | 45 | // Output 46 | output [data_size - 1 : 0]sdram_in; 47 | output [data_size - 1 : 0]sdram_out; 48 | 49 | // Internal wires and reg 50 | wire reset; 51 | wire clk0_2x; 52 | wire oe; 53 | wire [data_size - 1 : 0]datain2; 54 | wire [data_size - 1 : 0]dq; 55 | 56 | reg [data_size - 1 : 0]sdram_in; 57 | reg [data_size - 1 : 0]sdram_out; 58 | 59 | 60 | // Assignment 61 | 62 | 63 | // Register the output tri-state bidirectional Data Signals 64 | always @(posedge reset or negedge clk0_2x) 65 | begin 66 | if(reset == 1'b1) 67 | begin 68 | sdram_in <= 32'hzzzzzzzz; 69 | sdram_out <= 32'hzzzzzzzz; 70 | end 71 | else 72 | begin 73 | if(oe == 1'b1) 74 | begin 75 | sdram_out <= datain2; 76 | sdram_in <= 32'hzzzzzzzz; 77 | end 78 | else 79 | if(oe == 1'b0) 80 | begin 81 | sdram_in <= dq; 82 | sdram_out <= 32'hzzzzzzzz; 83 | end 84 | end 85 | end 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /Verilog/ref_timer.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Refresh Timer 3 | 4 | FILE NAME: ref_timer.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will generate the internal refresh counter. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | module ref_timer(// Input 23 | reset, 24 | clk0, 25 | refresh_count, 26 | bur_len, 27 | ref_ack, 28 | // Output 29 | ref_req 30 | ); 31 | 32 | // Parameter 33 | `include "parameter.v" 34 | 35 | // Input 36 | input reset; 37 | input clk0; 38 | input [15:0]refresh_count; 39 | input [burst_size - 1 : 0]bur_len; 40 | input ref_ack; 41 | 42 | // Output 43 | output ref_req; 44 | 45 | // Internal wire and reg signals 46 | reg ref_req; 47 | 48 | reg [15:0]refresh_timer; // 16-bit refresh counter Max. 65536 49 | reg rftimer_zero; 50 | 51 | 52 | // Assignment 53 | 54 | 55 | // Refresh Timer 56 | always @(posedge reset or posedge clk0) 57 | begin 58 | if(reset == 1'b1) 59 | begin 60 | refresh_timer <= 16'h0000; 61 | rftimer_zero <= 1'b0; 62 | ref_req <= 1'b0; 63 | end 64 | else 65 | begin 66 | if(rftimer_zero == 1'b1) 67 | refresh_timer <= refresh_count; 68 | else 69 | if(bur_len != 3'b000) 70 | refresh_timer <= refresh_timer - 1'b1; 71 | if((refresh_timer == 0) & (bur_len != 3'b000)) 72 | begin 73 | rftimer_zero <= 1'b1; 74 | ref_req <= 1'b1; 75 | end 76 | else 77 | if(ref_ack == 1'b1) 78 | begin 79 | rftimer_zero <= 1'b0; 80 | ref_req <= 1'b0; 81 | end 82 | end 83 | end 84 | 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /Verilog/MEM.V: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Sub Level Memory Block 3 | 4 | FILE NAME: mem.v 5 | VERSION: 1.0 6 | DATE: September 28th, 2001 7 | AUTHOR: Hossein Amidi 8 | COMPANY: California Unique Electrical Co. 9 | CODE TYPE: Behavioral Level 10 | 11 | Instantiations: 12 | 13 | DESCRIPTION: 14 | Sub Level Behavioral Memory Block, It uses 12 Address and 16 Data Line 15 | the memory size would be 2 ^ 12 = 4096 * 16-bit wide = 65536 bits. 16 | 65536 bits / 8 = 8192 Byte -> 8K Byte of memory. 17 | 18 | This memory is organized as 4096 locations of 16-bit (2 Byte) wide. 19 | 20 | Hossein Amidi 21 | (C) September 2001 22 | California Unique Electric 23 | 24 | ***************************************************************************************/ 25 | 26 | `timescale 1ns / 1ps 27 | 28 | module MEM (// Input 29 | DataIn, 30 | Address, 31 | MemReq, 32 | RdWrBar, 33 | clock, 34 | // Output 35 | DataOut 36 | ); 37 | 38 | 39 | // Parameter 40 | parameter words = 4096; 41 | parameter AccessTime = 0; 42 | parameter DataWidth = 32; 43 | parameter AddrWidth = 24; 44 | 45 | // Input 46 | input [DataWidth - 1 : 0] DataIn; 47 | input [AddrWidth - 1 : 0] Address; 48 | input MemReq; 49 | input RdWrBar; 50 | input clock; 51 | 52 | // Output 53 | output [DataWidth - 1 : 0] DataOut; 54 | 55 | // Internal Memory Declerations 56 | // 4096 x 16 bit wide 57 | 58 | reg [DataWidth - 1 : 0] MEM_Data [0:words-1]; 59 | 60 | // Signal Declerations 61 | wire [DataWidth - 1 : 0] Data; 62 | 63 | // Assignments 64 | // Read Cycle 65 | assign Data = (MemReq && RdWrBar)? MEM_Data [Address]:32'hz; 66 | assign #AccessTime DataOut = Data; // Delay in a continuous assign 67 | 68 | 69 | // Write Cycle 70 | always @(posedge clock) 71 | begin 72 | if(MemReq && ~RdWrBar) 73 | MEM_Data [Address] <= DataIn; 74 | end 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /Verilog/cmd_internal_reg.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Command Interface Internal Register 3 | 4 | FILE NAME: cmd_internal_reg.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will store the timing and refresh commands into internal registers. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module internal_reg(// Input 24 | reset, 25 | clk0, 26 | load_time, 27 | load_rfcnt, 28 | caddr, 29 | // Output 30 | cas_lat, 31 | ras_cas, 32 | ref_dur, 33 | page_mod, 34 | bur_len, 35 | refresh_count 36 | ); 37 | 38 | 39 | // Parameter 40 | `include "parameter.v" 41 | 42 | // Input 43 | input reset; 44 | input clk0; 45 | input load_time; 46 | input load_rfcnt; 47 | input [padd_size - 1 : 0]caddr; 48 | 49 | // Output 50 | output [cas_size - 1 : 0]cas_lat; 51 | output [rc_size - 1 : 0]ras_cas; 52 | output [ref_dur_size - 1 : 0]ref_dur; 53 | output page_mod; 54 | output [burst_size - 1 : 0]bur_len; 55 | output [15:0]refresh_count; 56 | 57 | // Internal wire and reg signals 58 | reg [cas_size - 1 : 0]cas_lat; 59 | reg [rc_size - 1 : 0]ras_cas; 60 | reg [ref_dur_size - 1 : 0]ref_dur; 61 | reg page_mod; 62 | reg [burst_size - 1 : 0]bur_len; 63 | reg [15:0]refresh_count; 64 | 65 | 66 | // Assignment 67 | 68 | 69 | // Loading Reg1 and Reg2 70 | always @(posedge reset or posedge clk0) 71 | begin 72 | if(reset == 1'b1) 73 | begin 74 | cas_lat <= 2'b00; 75 | ras_cas <= 2'b00; 76 | ref_dur <= 4'b0000; 77 | page_mod <= 1'b0; 78 | bur_len <= 4'b0000; 79 | refresh_count <= 16'h0000; 80 | end 81 | else 82 | begin 83 | if(load_time == 1'b1) 84 | begin 85 | cas_lat <= caddr[1:0]; 86 | ras_cas <= caddr[3:2]; 87 | ref_dur <= caddr[7:4]; 88 | page_mod <= caddr[8]; 89 | bur_len <= caddr[12:9]; 90 | end 91 | 92 | if(load_rfcnt == 1'b1) 93 | refresh_count <= caddr[15:0]; 94 | 95 | end 96 | end 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /Verilog/ACC.V: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Sub Level Accumulator Block 3 | 4 | FILE NAME: acc.v 5 | VERSION: 1.0 6 | DATE: September 28th, 2001 7 | AUTHOR: Hossein Amidi 8 | COMPANY: California Unique Electrical Co. 9 | CODE TYPE: Register Transfer Level 10 | 11 | Instantiations: 12 | 13 | DESCRIPTION: 14 | Sub Level RTL Accumulator block, with zero & negetive flags 15 | 16 | Hossein Amidi 17 | (C) September 2001 18 | California Unique Electric 19 | 20 | ***************************************************************************************/ 21 | 22 | `timescale 1ns / 1ps 23 | 24 | module ACC( // Input 25 | clock, 26 | reset, 27 | ACCInEn, 28 | ACCDataIn, 29 | // Output 30 | ACCNeg, 31 | ACCZero, 32 | ACCDataOut 33 | ); 34 | 35 | 36 | // Parameter 37 | parameter DataWidth = 32; 38 | 39 | // Input 40 | input clock; 41 | input reset; 42 | input ACCInEn; 43 | input [DataWidth - 1 : 0] ACCDataIn; 44 | 45 | // Output 46 | output ACCNeg; 47 | output ACCZero; 48 | output [DataWidth - 1 : 0] ACCDataOut; 49 | 50 | // Signal Declerations 51 | reg [DataWidth - 1 : 0]rACCDataOut; 52 | 53 | // Assignments 54 | assign ACCDataOut = rACCDataOut; 55 | assign ACCNeg = rACCDataOut[31]; 56 | assign ACCZero = ~((((((((((((((((ACCDataOut[0] | ACCDataOut[1]) | 57 | (ACCDataOut[2] | ACCDataOut[3])) | 58 | (ACCDataOut[4] | ACCDataOut[5])) | 59 | (ACCDataOut[6] | ACCDataOut[7])) | 60 | (ACCDataOut[8] | ACCDataOut[9])) | 61 | (ACCDataOut[10] | ACCDataOut[11])) | 62 | (ACCDataOut[12] | ACCDataOut[13])) | 63 | (ACCDataOut[14] | ACCDataOut[15])) | 64 | (ACCDataOut[16] | ACCDataOut[17])) | 65 | (ACCDataOut[18] | ACCDataOut[19])) | 66 | (ACCDataOut[20] | ACCDataOut[21])) | 67 | (ACCDataOut[22] | ACCDataOut[23])) | 68 | (ACCDataOut[24] | ACCDataOut[25])) | 69 | (ACCDataOut[26] | ACCDataOut[27])) | 70 | (ACCDataOut[28] | ACCDataOut[29])) | 71 | (ACCDataOut[30] | ACCDataOut[31])) ; 72 | 73 | 74 | 75 | always @(posedge reset or negedge clock) 76 | begin 77 | if(reset == 1'b1) 78 | rACCDataOut <= 32'h0000; 79 | else 80 | if(ACCInEn == 1'b1) 81 | rACCDataOut <= ACCDataIn; 82 | else 83 | rACCDataOut <= rACCDataOut; 84 | end 85 | endmodule 86 | -------------------------------------------------------------------------------- /Verilog/IR.V: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Sub Level Instruction Register Block 3 | 4 | FILE NAME: ir.v 5 | VERSION: 1.0 6 | DATE: September 28th, 2001 7 | AUTHOR: Hossein Amidi 8 | COMPANY: California Unique Electrical Co. 9 | CODE TYPE: Register Transfer Level 10 | 11 | Instantiations: 12 | 13 | DESCRIPTION: 14 | Sub Level RTL Instruction Register block 15 | 16 | This module generates the OPERAND and OPCODE to be used by 17 | modules ALU and CONTROLLER 18 | Inputs: 19 | 20 | Internal Name Net Name From 21 | ----------------------------------------------------------- 22 | IRDataIn: [15:0] MemDataOut input into cpu module (from memory) 23 | 24 | IRInEn: IRInEn Controller 25 | 26 | clock: clock input into cpu Module (from stimulus.v) 27 | reset: reset input into cpu Module (from stimulus.v) 28 | Outputs: 29 | 30 | Internal Name Net Name Used By 31 | ----------------------------------------------------------- 32 | 33 | OpCode: [3:0] OpCode ALU and Controller 34 | 35 | OperandOut: [11:0] OperandAddress MUX12 36 | 37 | Hossein Amidi 38 | (C) September 2001 39 | California Unique Electric 40 | 41 | ***************************************************************************************/ 42 | 43 | `timescale 1ns / 1ps 44 | 45 | module IR ( // Input 46 | clock, 47 | reset, 48 | IRInEn, 49 | IRDataIn, 50 | // Output 51 | OperandOut, 52 | OpCodeOut 53 | ); 54 | 55 | 56 | // Parameter 57 | parameter DataWidth = 32; 58 | parameter AddrWidth = 24; 59 | parameter OpcodeSize = 8; 60 | 61 | // Input 62 | input [DataWidth - 1 : 0] IRDataIn; 63 | input IRInEn; 64 | input clock; 65 | input reset; 66 | 67 | // Output 68 | output [AddrWidth - 1 : 0] OperandOut; 69 | output [OpcodeSize - 1 : 0] OpCodeOut; 70 | 71 | // Signal Declerations 72 | reg [AddrWidth - 1 : 0] OperandOut; 73 | reg [OpcodeSize - 1 : 0] OpCodeOut; 74 | 75 | 76 | always @ (posedge reset or negedge clock) 77 | begin 78 | if(reset == 1'b1) 79 | begin 80 | OperandOut <= 24'h00_0000; 81 | OpCodeOut <= 8'h00; 82 | end 83 | else 84 | if(IRInEn == 1'b1) 85 | begin 86 | OperandOut <= IRDataIn [23:0]; 87 | OpCodeOut <= IRDataIn [31:24]; 88 | end 89 | else 90 | begin 91 | OperandOut <= OperandOut; 92 | OpCodeOut <= OpCodeOut; 93 | end 94 | end 95 | endmodule 96 | 97 | -------------------------------------------------------------------------------- /Verilog/ref_ack.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Refresh Acknowledge 3 | 4 | FILE NAME: ref_ack.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It is the Refresh Acknowledge block. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module ref_ack(// Input 24 | reset, 25 | clk0, 26 | do_refresh, 27 | do_reada, 28 | do_writea, 29 | do_preacharge, 30 | do_load_mod, 31 | ref_req, 32 | // Output 33 | cmack, 34 | ref_ack 35 | ); 36 | 37 | // Parameter 38 | `include "parameter.v" 39 | 40 | // Input 41 | input reset; 42 | input clk0; 43 | input do_refresh; 44 | input do_reada; 45 | input do_writea; 46 | input do_preacharge; 47 | input do_load_mod; 48 | input ref_req; 49 | 50 | // Output 51 | output cmack; 52 | output ref_ack; 53 | 54 | // Internal wire and reg signals 55 | wire reset; 56 | wire clk0; 57 | wire do_refresh; 58 | wire do_reada; 59 | wire do_writea; 60 | wire do_preacharge; 61 | wire do_load_mod; 62 | wire ref_req; 63 | 64 | reg cmack; 65 | reg ref_ack; 66 | 67 | // Assignment 68 | 69 | // This always block generates the command acknowledge, cmack, signal. 70 | // It also generates the acknowledge signal, ref_ack, that acknowledges 71 | // a refresh request that was generated by the internal refresh timer circuit. 72 | always @(posedge reset or posedge clk0) 73 | begin 74 | 75 | if (reset == 1'b1) 76 | begin 77 | cmack <= 0; 78 | ref_ack <= 0; 79 | end 80 | 81 | else 82 | begin 83 | if (do_refresh == 1 & ref_req == 1) // Internal refresh timer refresh request 84 | ref_ack <= 1; 85 | else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_preacharge == 1) // externa commands 86 | | (do_load_mod)) 87 | cmack <= 1; 88 | else 89 | begin 90 | ref_ack <= 0; 91 | cmack <= 0; 92 | end 93 | end 94 | end 95 | 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /Verilog/sdram_cntrl.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Controller, SDRAM control signals 3 | 4 | FILE NAME: sdram_cntrl.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It is the SDRAM control signals block. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module sdram_cntrl(// Input 24 | reset, 25 | clk0, 26 | wsadd, 27 | wba, 28 | wcs, 29 | wcke, 30 | wras, 31 | wcas, 32 | wwe, 33 | sdram_in, 34 | // Output 35 | add, 36 | ba, 37 | cs, 38 | cke, 39 | ras, 40 | cas, 41 | we, 42 | dataout 43 | ); 44 | 45 | // Parameter 46 | `include "parameter.v" 47 | 48 | // Input 49 | input reset; 50 | input clk0; 51 | input [add_size - 1 : 0]wsadd; 52 | input [ba_size - 1 : 0]wba; 53 | input [cs_size - 1 : 0]wcs; 54 | input wcke; 55 | input wras; 56 | input wcas; 57 | input wwe; 58 | input [data_size - 1 : 0]sdram_in; 59 | 60 | // Output 61 | output [add_size - 1 : 0]add; 62 | output [ba_size - 1 : 0]ba; 63 | output [cs_size - 1 : 0]cs; 64 | output cke; 65 | output ras; 66 | output cas; 67 | output we; 68 | output [data_size - 1 : 0]dataout; 69 | 70 | 71 | // Internal wires and reg 72 | wire reset; 73 | wire clk0; 74 | wire [add_size - 1 : 0]wsadd; 75 | wire [ba_size - 1 : 0]wba; 76 | wire [cs_size - 1 : 0]wcs; 77 | wire wcke; 78 | wire wras; 79 | wire wcas; 80 | wire wwe; 81 | wire [data_size - 1 : 0]sdram_in; 82 | 83 | reg [add_size - 1 : 0]add; 84 | reg [ba_size - 1 : 0]ba; 85 | reg [cs_size - 1 : 0]cs; 86 | reg cke; 87 | reg ras; 88 | reg cas; 89 | reg we; 90 | reg [data_size - 1 : 0]dataout; 91 | 92 | 93 | // Assignment 94 | 95 | 96 | 97 | // SDRAM Memory Control Signals 98 | always @(posedge reset or posedge clk0) 99 | begin 100 | if(reset == 1'b1) 101 | begin 102 | add <= 12'h0; 103 | ba <= 2'b00; 104 | cs <= 2'b00; 105 | cke <= 1'b0; 106 | ras <= 1'b0; 107 | cas <= 1'b0; 108 | we <= 1'b0; 109 | dataout <= 32'h0000_0000; 110 | end 111 | else 112 | begin 113 | add <= wsadd; 114 | ba <= wba; 115 | cs <= wcs; 116 | cke <= wcke; 117 | ras <= wras; 118 | cas <= wcas; 119 | we <= wwe; 120 | dataout <= sdram_in; 121 | end 122 | end 123 | 124 | endmodule 125 | -------------------------------------------------------------------------------- /Verilog/ras_cas_delay.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Ras-to-Cas Delay Counter 3 | 4 | FILE NAME: ras_cas_delay.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It is the RAS-to-CAS Delay Counter block. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module ras_cas_delay(// Input 24 | reset, 25 | clk0, 26 | do_reada, 27 | do_writea, 28 | ras_cas, 29 | // Output 30 | do_rw 31 | ); 32 | 33 | // Parameter 34 | `include "parameter.v" 35 | 36 | // Input 37 | input reset; 38 | input clk0; 39 | input do_reada; 40 | input do_writea; 41 | input [rc_size - 1 : 0]ras_cas; 42 | 43 | // Output 44 | output do_rw; 45 | 46 | // Internal wire and reg signals 47 | wire reset; 48 | wire clk0; 49 | wire do_reada; 50 | wire do_writea; 51 | wire [rc_size - 1 : 0]ras_cas; 52 | 53 | reg do_rw; 54 | reg [3:0]rw_shift; 55 | 56 | 57 | // Assignment 58 | 59 | 60 | 61 | // This always block tracks the time between the activate command and the 62 | // subsequent writea or reada command, RC. The shift register is set using 63 | // the configuration register setting ras_cas. The shift register is loaded with 64 | // a single '1' with the position within the register dependent on ras_cas. 65 | // When the '1' is shifted out of the register it sets so_rw which triggers 66 | // a writea or reada command 67 | // 68 | always @(posedge reset or posedge clk0) 69 | begin 70 | if (reset == 1'b1) 71 | begin 72 | rw_shift <= 0; 73 | do_rw <= 0; 74 | end 75 | 76 | else 77 | begin 78 | 79 | if ((do_reada == 1) | (do_writea == 1)) 80 | begin 81 | if (ras_cas == 1) // Set the shift register 82 | do_rw <= 1; 83 | else if (ras_cas == 2) 84 | rw_shift <= 1; 85 | else if (ras_cas == 3) 86 | rw_shift <= 2; 87 | end 88 | else 89 | begin 90 | rw_shift[2:0] <= rw_shift[3:1]; // perform the shift operation 91 | rw_shift[3] <= 0; 92 | do_rw <= rw_shift[0]; 93 | end 94 | end 95 | end 96 | 97 | 98 | endmodule 99 | -------------------------------------------------------------------------------- /Verilog/dma_fifo.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file dma_fifo.v when simulating 20 | // the core, dma_fifo. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module dma_fifo ( 25 | clk, 26 | sinit, 27 | din, 28 | wr_en, 29 | rd_en, 30 | dout, 31 | full, 32 | empty); // synthesis black_box 33 | 34 | input clk; 35 | input sinit; 36 | input [7 : 0] din; 37 | input wr_en; 38 | input rd_en; 39 | output [7 : 0] dout; 40 | output full; 41 | output empty; 42 | 43 | // synopsys translate_off 44 | 45 | SYNC_FIFO_V2_0 #( 46 | 1, // c_dcount_width 47 | 0, // c_enable_rlocs 48 | 0, // c_has_dcount 49 | 0, // c_has_rd_ack 50 | 0, // c_has_rd_err 51 | 0, // c_has_wr_ack 52 | 0, // c_has_wr_err 53 | 1, // c_memory_type 54 | 0, // c_ports_differ 55 | 1, // c_rd_ack_low 56 | 1, // c_rd_err_low 57 | 8, // c_read_data_width 58 | 512, // c_read_depth 59 | 8, // c_write_data_width 60 | 512, // c_write_depth 61 | 1, // c_wr_ack_low 62 | 1) // c_wr_err_low 63 | inst ( 64 | .CLK(clk), 65 | .SINIT(sinit), 66 | .DIN(din), 67 | .WR_EN(wr_en), 68 | .RD_EN(rd_en), 69 | .DOUT(dout), 70 | .FULL(full), 71 | .EMPTY(empty)); 72 | 73 | 74 | // synopsys translate_on 75 | 76 | // FPGA Express black box declaration 77 | // synopsys attribute fpga_dont_touch "true" 78 | // synthesis attribute fpga_dont_touch of dma_fifo is "true" 79 | 80 | // XST black box declaration 81 | // box_type "black_box" 82 | // synthesis attribute box_type of dma_fifo is "black_box" 83 | 84 | endmodule 85 | 86 | -------------------------------------------------------------------------------- /Verilog/data_cache_way0.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file data_cache_way0.v when simulating 20 | // the core, data_cache_way0. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module data_cache_way0 ( 25 | A, 26 | CLK, 27 | D, 28 | WE, 29 | SPO); // synthesis black_box 30 | 31 | input [4 : 0] A; 32 | input CLK; 33 | input [52 : 0] D; 34 | input WE; 35 | output [52 : 0] SPO; 36 | 37 | // synopsys translate_off 38 | 39 | C_DIST_MEM_V4_1 #( 40 | 5, // c_addr_width 41 | "0", // c_default_data 42 | 1, // c_default_data_radix 43 | 32, // c_depth 44 | 0, // c_family 45 | 1, // c_generate_mif 46 | 1, // c_has_clk 47 | 1, // c_has_d 48 | 0, // c_has_dpo 49 | 0, // c_has_dpra 50 | 0, // c_has_i_ce 51 | 0, // c_has_qdpo 52 | 0, // c_has_qdpo_ce 53 | 0, // c_has_qdpo_clk 54 | 0, // c_has_qdpo_rst 55 | 0, // c_has_qdpo_srst 56 | 0, // c_has_qspo 57 | 0, // c_has_qspo_ce 58 | 0, // c_has_qspo_rst 59 | 0, // c_has_qspo_srst 60 | 0, // c_has_rd_en 61 | 1, // c_has_spo 62 | 0, // c_has_spra 63 | 1, // c_has_we 64 | 0, // c_latency 65 | "data_cache_way0.mif", // c_mem_init_file 66 | 1, // c_mem_type 67 | 0, // c_mux_type 68 | 0, // c_qce_joined 69 | 0, // c_qualify_we 70 | 0, // c_read_mif 71 | 0, // c_reg_a_d_inputs 72 | 0, // c_reg_dpra_input 73 | 0, // c_sync_enable 74 | 53) // c_width 75 | inst ( 76 | .A(A), 77 | .CLK(CLK), 78 | .D(D), 79 | .WE(WE), 80 | .SPO(SPO)); 81 | 82 | 83 | // synopsys translate_on 84 | 85 | // FPGA Express black box declaration 86 | // synopsys attribute fpga_dont_touch "true" 87 | // synthesis attribute fpga_dont_touch of data_cache_way0 is "true" 88 | 89 | // XST black box declaration 90 | // box_type "black_box" 91 | // synthesis attribute box_type of data_cache_way0 is "black_box" 92 | 93 | endmodule 94 | 95 | -------------------------------------------------------------------------------- /Verilog/data_cache_way1.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file data_cache_way1.v when simulating 20 | // the core, data_cache_way1. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module data_cache_way1 ( 25 | A, 26 | CLK, 27 | D, 28 | WE, 29 | SPO); // synthesis black_box 30 | 31 | input [4 : 0] A; 32 | input CLK; 33 | input [52 : 0] D; 34 | input WE; 35 | output [52 : 0] SPO; 36 | 37 | // synopsys translate_off 38 | 39 | C_DIST_MEM_V4_1 #( 40 | 5, // c_addr_width 41 | "0", // c_default_data 42 | 1, // c_default_data_radix 43 | 32, // c_depth 44 | 0, // c_family 45 | 1, // c_generate_mif 46 | 1, // c_has_clk 47 | 1, // c_has_d 48 | 0, // c_has_dpo 49 | 0, // c_has_dpra 50 | 0, // c_has_i_ce 51 | 0, // c_has_qdpo 52 | 0, // c_has_qdpo_ce 53 | 0, // c_has_qdpo_clk 54 | 0, // c_has_qdpo_rst 55 | 0, // c_has_qdpo_srst 56 | 0, // c_has_qspo 57 | 0, // c_has_qspo_ce 58 | 0, // c_has_qspo_rst 59 | 0, // c_has_qspo_srst 60 | 0, // c_has_rd_en 61 | 1, // c_has_spo 62 | 0, // c_has_spra 63 | 1, // c_has_we 64 | 0, // c_latency 65 | "data_cache_way1.mif", // c_mem_init_file 66 | 1, // c_mem_type 67 | 0, // c_mux_type 68 | 0, // c_qce_joined 69 | 0, // c_qualify_we 70 | 0, // c_read_mif 71 | 0, // c_reg_a_d_inputs 72 | 0, // c_reg_dpra_input 73 | 0, // c_sync_enable 74 | 53) // c_width 75 | inst ( 76 | .A(A), 77 | .CLK(CLK), 78 | .D(D), 79 | .WE(WE), 80 | .SPO(SPO)); 81 | 82 | 83 | // synopsys translate_on 84 | 85 | // FPGA Express black box declaration 86 | // synopsys attribute fpga_dont_touch "true" 87 | // synthesis attribute fpga_dont_touch of data_cache_way1 is "true" 88 | 89 | // XST black box declaration 90 | // box_type "black_box" 91 | // synthesis attribute box_type of data_cache_way1 is "black_box" 92 | 93 | endmodule 94 | 95 | -------------------------------------------------------------------------------- /Verilog/data_cache_way2.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file data_cache_way2.v when simulating 20 | // the core, data_cache_way2. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module data_cache_way2 ( 25 | A, 26 | CLK, 27 | D, 28 | WE, 29 | SPO); // synthesis black_box 30 | 31 | input [4 : 0] A; 32 | input CLK; 33 | input [52 : 0] D; 34 | input WE; 35 | output [52 : 0] SPO; 36 | 37 | // synopsys translate_off 38 | 39 | C_DIST_MEM_V4_1 #( 40 | 5, // c_addr_width 41 | "0", // c_default_data 42 | 1, // c_default_data_radix 43 | 32, // c_depth 44 | 0, // c_family 45 | 1, // c_generate_mif 46 | 1, // c_has_clk 47 | 1, // c_has_d 48 | 0, // c_has_dpo 49 | 0, // c_has_dpra 50 | 0, // c_has_i_ce 51 | 0, // c_has_qdpo 52 | 0, // c_has_qdpo_ce 53 | 0, // c_has_qdpo_clk 54 | 0, // c_has_qdpo_rst 55 | 0, // c_has_qdpo_srst 56 | 0, // c_has_qspo 57 | 0, // c_has_qspo_ce 58 | 0, // c_has_qspo_rst 59 | 0, // c_has_qspo_srst 60 | 0, // c_has_rd_en 61 | 1, // c_has_spo 62 | 0, // c_has_spra 63 | 1, // c_has_we 64 | 0, // c_latency 65 | "data_cache_way2.mif", // c_mem_init_file 66 | 1, // c_mem_type 67 | 0, // c_mux_type 68 | 0, // c_qce_joined 69 | 0, // c_qualify_we 70 | 0, // c_read_mif 71 | 0, // c_reg_a_d_inputs 72 | 0, // c_reg_dpra_input 73 | 0, // c_sync_enable 74 | 53) // c_width 75 | inst ( 76 | .A(A), 77 | .CLK(CLK), 78 | .D(D), 79 | .WE(WE), 80 | .SPO(SPO)); 81 | 82 | 83 | // synopsys translate_on 84 | 85 | // FPGA Express black box declaration 86 | // synopsys attribute fpga_dont_touch "true" 87 | // synthesis attribute fpga_dont_touch of data_cache_way2 is "true" 88 | 89 | // XST black box declaration 90 | // box_type "black_box" 91 | // synthesis attribute box_type of data_cache_way2 is "black_box" 92 | 93 | endmodule 94 | 95 | -------------------------------------------------------------------------------- /Verilog/data_cache_way3.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file data_cache_way3.v when simulating 20 | // the core, data_cache_way3. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module data_cache_way3 ( 25 | A, 26 | CLK, 27 | D, 28 | WE, 29 | SPO); // synthesis black_box 30 | 31 | input [4 : 0] A; 32 | input CLK; 33 | input [52 : 0] D; 34 | input WE; 35 | output [52 : 0] SPO; 36 | 37 | // synopsys translate_off 38 | 39 | C_DIST_MEM_V4_1 #( 40 | 5, // c_addr_width 41 | "0", // c_default_data 42 | 1, // c_default_data_radix 43 | 32, // c_depth 44 | 0, // c_family 45 | 1, // c_generate_mif 46 | 1, // c_has_clk 47 | 1, // c_has_d 48 | 0, // c_has_dpo 49 | 0, // c_has_dpra 50 | 0, // c_has_i_ce 51 | 0, // c_has_qdpo 52 | 0, // c_has_qdpo_ce 53 | 0, // c_has_qdpo_clk 54 | 0, // c_has_qdpo_rst 55 | 0, // c_has_qdpo_srst 56 | 0, // c_has_qspo 57 | 0, // c_has_qspo_ce 58 | 0, // c_has_qspo_rst 59 | 0, // c_has_qspo_srst 60 | 0, // c_has_rd_en 61 | 1, // c_has_spo 62 | 0, // c_has_spra 63 | 1, // c_has_we 64 | 0, // c_latency 65 | "data_cache_way3.mif", // c_mem_init_file 66 | 1, // c_mem_type 67 | 0, // c_mux_type 68 | 0, // c_qce_joined 69 | 0, // c_qualify_we 70 | 0, // c_read_mif 71 | 0, // c_reg_a_d_inputs 72 | 0, // c_reg_dpra_input 73 | 0, // c_sync_enable 74 | 53) // c_width 75 | inst ( 76 | .A(A), 77 | .CLK(CLK), 78 | .D(D), 79 | .WE(WE), 80 | .SPO(SPO)); 81 | 82 | 83 | // synopsys translate_on 84 | 85 | // FPGA Express black box declaration 86 | // synopsys attribute fpga_dont_touch "true" 87 | // synthesis attribute fpga_dont_touch of data_cache_way3 is "true" 88 | 89 | // XST black box declaration 90 | // box_type "black_box" 91 | // synthesis attribute box_type of data_cache_way3 is "black_box" 92 | 93 | endmodule 94 | 95 | -------------------------------------------------------------------------------- /Verilog/instruction_cache_way0.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file instruction_cache_way0.v when simulating 20 | // the core, instruction_cache_way0. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module instruction_cache_way0 ( 25 | A, 26 | CLK, 27 | D, 28 | WE, 29 | SPO); // synthesis black_box 30 | 31 | input [4 : 0] A; 32 | input CLK; 33 | input [52 : 0] D; 34 | input WE; 35 | output [52 : 0] SPO; 36 | 37 | // synopsys translate_off 38 | 39 | C_DIST_MEM_V4_1 #( 40 | 5, // c_addr_width 41 | "0", // c_default_data 42 | 1, // c_default_data_radix 43 | 32, // c_depth 44 | 0, // c_family 45 | 1, // c_generate_mif 46 | 1, // c_has_clk 47 | 1, // c_has_d 48 | 0, // c_has_dpo 49 | 0, // c_has_dpra 50 | 0, // c_has_i_ce 51 | 0, // c_has_qdpo 52 | 0, // c_has_qdpo_ce 53 | 0, // c_has_qdpo_clk 54 | 0, // c_has_qdpo_rst 55 | 0, // c_has_qdpo_srst 56 | 0, // c_has_qspo 57 | 0, // c_has_qspo_ce 58 | 0, // c_has_qspo_rst 59 | 0, // c_has_qspo_srst 60 | 0, // c_has_rd_en 61 | 1, // c_has_spo 62 | 0, // c_has_spra 63 | 1, // c_has_we 64 | 0, // c_latency 65 | "instruction_cache_way0.mif", // c_mem_init_file 66 | 1, // c_mem_type 67 | 0, // c_mux_type 68 | 0, // c_qce_joined 69 | 0, // c_qualify_we 70 | 0, // c_read_mif 71 | 0, // c_reg_a_d_inputs 72 | 0, // c_reg_dpra_input 73 | 0, // c_sync_enable 74 | 53) // c_width 75 | inst ( 76 | .A(A), 77 | .CLK(CLK), 78 | .D(D), 79 | .WE(WE), 80 | .SPO(SPO)); 81 | 82 | 83 | // synopsys translate_on 84 | 85 | // FPGA Express black box declaration 86 | // synopsys attribute fpga_dont_touch "true" 87 | // synthesis attribute fpga_dont_touch of instruction_cache_way0 is "true" 88 | 89 | // XST black box declaration 90 | // box_type "black_box" 91 | // synthesis attribute box_type of instruction_cache_way0 is "black_box" 92 | 93 | endmodule 94 | 95 | -------------------------------------------------------------------------------- /Verilog/instruction_cache_way1.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file instruction_cache_way1.v when simulating 20 | // the core, instruction_cache_way1. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module instruction_cache_way1 ( 25 | A, 26 | CLK, 27 | D, 28 | WE, 29 | SPO); // synthesis black_box 30 | 31 | input [4 : 0] A; 32 | input CLK; 33 | input [52 : 0] D; 34 | input WE; 35 | output [52 : 0] SPO; 36 | 37 | // synopsys translate_off 38 | 39 | C_DIST_MEM_V4_1 #( 40 | 5, // c_addr_width 41 | "0", // c_default_data 42 | 1, // c_default_data_radix 43 | 32, // c_depth 44 | 0, // c_family 45 | 1, // c_generate_mif 46 | 1, // c_has_clk 47 | 1, // c_has_d 48 | 0, // c_has_dpo 49 | 0, // c_has_dpra 50 | 0, // c_has_i_ce 51 | 0, // c_has_qdpo 52 | 0, // c_has_qdpo_ce 53 | 0, // c_has_qdpo_clk 54 | 0, // c_has_qdpo_rst 55 | 0, // c_has_qdpo_srst 56 | 0, // c_has_qspo 57 | 0, // c_has_qspo_ce 58 | 0, // c_has_qspo_rst 59 | 0, // c_has_qspo_srst 60 | 0, // c_has_rd_en 61 | 1, // c_has_spo 62 | 0, // c_has_spra 63 | 1, // c_has_we 64 | 0, // c_latency 65 | "instruction_cache_way1.mif", // c_mem_init_file 66 | 1, // c_mem_type 67 | 0, // c_mux_type 68 | 0, // c_qce_joined 69 | 0, // c_qualify_we 70 | 0, // c_read_mif 71 | 0, // c_reg_a_d_inputs 72 | 0, // c_reg_dpra_input 73 | 0, // c_sync_enable 74 | 53) // c_width 75 | inst ( 76 | .A(A), 77 | .CLK(CLK), 78 | .D(D), 79 | .WE(WE), 80 | .SPO(SPO)); 81 | 82 | 83 | // synopsys translate_on 84 | 85 | // FPGA Express black box declaration 86 | // synopsys attribute fpga_dont_touch "true" 87 | // synthesis attribute fpga_dont_touch of instruction_cache_way1 is "true" 88 | 89 | // XST black box declaration 90 | // box_type "black_box" 91 | // synthesis attribute box_type of instruction_cache_way1 is "black_box" 92 | 93 | endmodule 94 | 95 | -------------------------------------------------------------------------------- /Verilog/instruction_cache_way2.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file instruction_cache_way2.v when simulating 20 | // the core, instruction_cache_way2. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module instruction_cache_way2 ( 25 | A, 26 | CLK, 27 | D, 28 | WE, 29 | SPO); // synthesis black_box 30 | 31 | input [4 : 0] A; 32 | input CLK; 33 | input [52 : 0] D; 34 | input WE; 35 | output [52 : 0] SPO; 36 | 37 | // synopsys translate_off 38 | 39 | C_DIST_MEM_V4_1 #( 40 | 5, // c_addr_width 41 | "0", // c_default_data 42 | 1, // c_default_data_radix 43 | 32, // c_depth 44 | 0, // c_family 45 | 1, // c_generate_mif 46 | 1, // c_has_clk 47 | 1, // c_has_d 48 | 0, // c_has_dpo 49 | 0, // c_has_dpra 50 | 0, // c_has_i_ce 51 | 0, // c_has_qdpo 52 | 0, // c_has_qdpo_ce 53 | 0, // c_has_qdpo_clk 54 | 0, // c_has_qdpo_rst 55 | 0, // c_has_qdpo_srst 56 | 0, // c_has_qspo 57 | 0, // c_has_qspo_ce 58 | 0, // c_has_qspo_rst 59 | 0, // c_has_qspo_srst 60 | 0, // c_has_rd_en 61 | 1, // c_has_spo 62 | 0, // c_has_spra 63 | 1, // c_has_we 64 | 0, // c_latency 65 | "instruction_cache_way2.mif", // c_mem_init_file 66 | 1, // c_mem_type 67 | 0, // c_mux_type 68 | 0, // c_qce_joined 69 | 0, // c_qualify_we 70 | 0, // c_read_mif 71 | 0, // c_reg_a_d_inputs 72 | 0, // c_reg_dpra_input 73 | 0, // c_sync_enable 74 | 53) // c_width 75 | inst ( 76 | .A(A), 77 | .CLK(CLK), 78 | .D(D), 79 | .WE(WE), 80 | .SPO(SPO)); 81 | 82 | 83 | // synopsys translate_on 84 | 85 | // FPGA Express black box declaration 86 | // synopsys attribute fpga_dont_touch "true" 87 | // synthesis attribute fpga_dont_touch of instruction_cache_way2 is "true" 88 | 89 | // XST black box declaration 90 | // box_type "black_box" 91 | // synthesis attribute box_type of instruction_cache_way2 is "black_box" 92 | 93 | endmodule 94 | 95 | -------------------------------------------------------------------------------- /Verilog/instruction_cache_way3.v: -------------------------------------------------------------------------------- 1 | /******************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used * 3 | * solely for design, simulation, implementation and creation of * 4 | * design files limited to Xilinx devices or technologies. Use * 5 | * with non-Xilinx devices or technologies is expressly prohibited * 6 | * and immediately terminates your license. * 7 | * * 8 | * Xilinx products are not intended for use in life support * 9 | * appliances, devices, or systems. Use in such applications are * 10 | * expressly prohibited. * 11 | * * 12 | * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * 13 | *******************************************************************/ 14 | 15 | // The synopsys directives "translate_off/translate_on" specified 16 | // below are supported by XST, FPGA Express, Exemplar and Synplicity 17 | // synthesis tools. Ensure they are correct for your synthesis tool(s). 18 | 19 | // You must compile the wrapper file instruction_cache_way3.v when simulating 20 | // the core, instruction_cache_way3. When compiling the wrapper file, be sure to 21 | // reference the XilinxCoreLib Verilog simulation library. For detailed 22 | // instructions, please refer to the "Coregen Users Guide". 23 | 24 | module instruction_cache_way3 ( 25 | A, 26 | CLK, 27 | D, 28 | WE, 29 | SPO); // synthesis black_box 30 | 31 | input [4 : 0] A; 32 | input CLK; 33 | input [52 : 0] D; 34 | input WE; 35 | output [52 : 0] SPO; 36 | 37 | // synopsys translate_off 38 | 39 | C_DIST_MEM_V4_1 #( 40 | 5, // c_addr_width 41 | "0", // c_default_data 42 | 1, // c_default_data_radix 43 | 32, // c_depth 44 | 0, // c_family 45 | 1, // c_generate_mif 46 | 1, // c_has_clk 47 | 1, // c_has_d 48 | 0, // c_has_dpo 49 | 0, // c_has_dpra 50 | 0, // c_has_i_ce 51 | 0, // c_has_qdpo 52 | 0, // c_has_qdpo_ce 53 | 0, // c_has_qdpo_clk 54 | 0, // c_has_qdpo_rst 55 | 0, // c_has_qdpo_srst 56 | 0, // c_has_qspo 57 | 0, // c_has_qspo_ce 58 | 0, // c_has_qspo_rst 59 | 0, // c_has_qspo_srst 60 | 0, // c_has_rd_en 61 | 1, // c_has_spo 62 | 0, // c_has_spra 63 | 1, // c_has_we 64 | 0, // c_latency 65 | "instruction_cache_way3.mif", // c_mem_init_file 66 | 1, // c_mem_type 67 | 0, // c_mux_type 68 | 0, // c_qce_joined 69 | 0, // c_qualify_we 70 | 0, // c_read_mif 71 | 0, // c_reg_a_d_inputs 72 | 0, // c_reg_dpra_input 73 | 0, // c_sync_enable 74 | 53) // c_width 75 | inst ( 76 | .A(A), 77 | .CLK(CLK), 78 | .D(D), 79 | .WE(WE), 80 | .SPO(SPO)); 81 | 82 | 83 | // synopsys translate_on 84 | 85 | // FPGA Express black box declaration 86 | // synopsys attribute fpga_dont_touch "true" 87 | // synthesis attribute fpga_dont_touch of instruction_cache_way3 is "true" 88 | 89 | // XST black box declaration 90 | // box_type "black_box" 91 | // synthesis attribute box_type of instruction_cache_way3 is "black_box" 92 | 93 | endmodule 94 | 95 | -------------------------------------------------------------------------------- /Verilog/cmd_decoder.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Command Interface Decoder 3 | 4 | FILE NAME: cmd_decoder.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will Decode the incoming uProcessor command for internal State Machines. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | 24 | module cmd_decoder(// Input 25 | reset, 26 | clk0, 27 | paddr, 28 | cmd, 29 | cmdack, 30 | // Output 31 | nop, 32 | reada, 33 | writea, 34 | refresh, 35 | preacharge, 36 | load_mod, 37 | load_time, 38 | load_rfcnt, 39 | caddr 40 | ); 41 | 42 | // Parameter 43 | `include "parameter.v" 44 | 45 | // Input 46 | input reset; 47 | input clk0; 48 | input [padd_size - 1 : 0]paddr; 49 | input [cmd_size - 1 : 0]cmd; 50 | input cmdack; 51 | 52 | // Output 53 | output nop; 54 | output reada; 55 | output writea; 56 | output refresh; 57 | output preacharge; 58 | output load_mod; 59 | output load_time; 60 | output load_rfcnt; 61 | output [padd_size - 1 : 0]caddr; 62 | 63 | 64 | // Internal wire and reg signals 65 | reg nop; 66 | reg reada; 67 | reg writea; 68 | reg refresh; 69 | reg preacharge; 70 | reg load_mod; 71 | reg load_time; 72 | reg load_rfcnt; 73 | reg [padd_size - 1 : 0]caddr; 74 | 75 | 76 | // Assignment 77 | 78 | 79 | 80 | //Command Decoder and Address Register 81 | always @(posedge reset or posedge clk0) 82 | begin 83 | if(reset == 1'b1) 84 | begin 85 | nop <= 1'b0; 86 | reada <= 1'b0; 87 | writea <= 1'b0; 88 | refresh <= 1'b0; 89 | preacharge <= 1'b0; 90 | load_mod <= 1'b0; 91 | load_time <= 1'b0; 92 | load_rfcnt <= 1'b0; 93 | caddr <= 24'h00_0000; 94 | end 95 | else 96 | begin 97 | // Register the Address Buss to match the timing 98 | caddr <= paddr; 99 | 100 | if(cmd == 3'b000) 101 | nop <= 1'b1; 102 | else 103 | nop <= 1'b0; 104 | 105 | if(cmd == 3'b001) 106 | reada <= 1'b1; 107 | else 108 | reada <= 1'b0; 109 | 110 | if(cmd == 3'b010) 111 | writea <= 1'b1; 112 | else 113 | writea <= 1'b0; 114 | 115 | if(cmd == 3'b011) 116 | refresh <= 1'b1; 117 | else 118 | refresh <= 1'b0; 119 | 120 | if(cmd == 3'b100) 121 | preacharge <= 1'b1; 122 | else 123 | preacharge <= 1'b0; 124 | 125 | if(cmd == 3'b101) 126 | load_mod <= 1'b1; 127 | else 128 | load_mod <= 1'b0; 129 | 130 | if((cmd == 3'b110) & (load_time == 1'b0) & (cmdack == 1'b0)) 131 | load_time <= 1'b1; 132 | else 133 | load_time <= 1'b0; 134 | 135 | if((cmd == 3'b111) & (load_rfcnt == 1'b0) & (cmdack == 1'b0)) 136 | load_rfcnt <= 1'b1; 137 | else 138 | load_rfcnt <= 1'b0; 139 | end 140 | end 141 | 142 | /* 143 | casex({cmdack,load_rfcnt,load_time,cmd}) 144 | 145 | 6'bx_x_x_000: nop <= 1'b1; 146 | 6'bx_x_x_001: reada <= 1'b1; 147 | 6'bx_x_x_010: writea <= 1'b1; 148 | 6'bx_x_x_011: refresh <= 1'b1; 149 | 6'bx_x_x_100: preacharge <= 1'b1; 150 | 6'bx_x_x_101: load_mod <= 1'b1; 151 | 6'b0_x_0_110: load_time <= 1'b1; 152 | 6'b0_0_x_111: load_rfcnt <= 1'b1; 153 | default: 154 | begin 155 | nop <= 1'b0; 156 | reada <= 1'b0; 157 | writea <= 1'b0; 158 | refresh <= 1'b0; 159 | preacharge <= 1'b0; 160 | load_mod <= 1'b0; 161 | load_time <= 1'b0; 162 | load_rfcnt <= 1'b0; 163 | end 164 | endcase 165 | */ 166 | 167 | endmodule 168 | -------------------------------------------------------------------------------- /Verilog/parameter.v: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Parameters File 3 | 4 | FILE NAME: parameter.v 5 | VERSION: 1.0 6 | DATE: April 8th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Parameter Verilog File 10 | 11 | 12 | Hossein Amidi 13 | (C) April 2002 14 | 15 | ***************************************************************************************/ 16 | 17 | // Parameters 18 | 19 | /****** RISC Processor ******/ 20 | parameter add_size = 12; 21 | parameter padd_size = 24; 22 | parameter cmd_size = 3; 23 | parameter cs_size = 2; 24 | parameter dqm_size = 4; 25 | parameter ba_size = 2; 26 | parameter data_size = 32; 27 | parameter timing_size = 12; 28 | 29 | parameter DataWidth = 32; 30 | parameter AddrWidth = 24; 31 | parameter OpcodeWidth = 8; 32 | parameter StateSize = 2; 33 | 34 | parameter Byte_size = 8; 35 | parameter uart_add = 3; 36 | 37 | /****** SDRAM CNTRL ******/ 38 | parameter burst = 3; 39 | parameter HiZ = 32'hz; 40 | parameter cas_size = 2; 41 | parameter rc_size = 2; 42 | parameter ref_dur_size = 4; 43 | parameter burst_size = 4; 44 | parameter byte_size = 8; 45 | parameter row_size = 12; 46 | parameter col_size = 10; 47 | parameter bank_size = 2; 48 | parameter rowstart = 10; 49 | parameter colstart = 0; 50 | parameter bankstart = 22; 51 | 52 | /****** Bus Arbiter ******/ 53 | parameter arbiter_bus_size = 3; 54 | parameter irq_size = 3; 55 | 56 | /****** DMA CNTRL ******/ 57 | parameter dma_reg_addr = 3; 58 | parameter dma_reg_depth = 8; 59 | parameter dma_reg_width = 32; 60 | parameter dma_fifo_width = 8; 61 | parameter dma_fifo_depth = 32; 62 | parameter dma_counter_size = 5; 63 | parameter fifo_size = 8; 64 | 65 | /****** UART ******/ 66 | parameter uart_reg_depth = 8; 67 | parameter uart_reg_width = 32; 68 | parameter uart_cnt_size = 3; 69 | parameter ser_in_cnt = 3; 70 | parameter ser_out_cnt = 3; 71 | 72 | /****** LRU Cache ******/ 73 | parameter cache_reg_depth = 8; 74 | parameter cache_reg_width = 32; 75 | parameter cache_line_size = 53; 76 | parameter cache_valid = 2; 77 | parameter cache_tag = 19; 78 | 79 | /****** Timer ******/ 80 | parameter timer_reg_depth = 4; 81 | parameter timer_reg_width = 32; 82 | parameter timer_addr_size = 2; 83 | parameter timer_size = 32; 84 | 85 | /****** Flash CNTRL ******/ 86 | parameter flash_size = 8; 87 | parameter flash_reg_width = 32; 88 | parameter flash_reg_depth = 8; 89 | 90 | /*********************************************************************/ 91 | 92 | /****************************** MEMORY Map ***************************/ 93 | /* Total of 16MB of Memory for Both Data and Instruction and */ 94 | /* internal Register mapping */ 95 | /* */ 96 | /*********************************************************************/ 97 | 98 | // FLASH Memory 64K x 8-bit, 512Kbit (F 0x000000 T 0x07FFFF) 99 | parameter flash_mem_addr_map = 24'h000000; 100 | 101 | 102 | // DMA Regiseters 8 x 32-bit (F 0x080000 T 0x080007) 103 | parameter dma_reg_addr_map = 24'h080000; 104 | 105 | // Flash Regiseters 8 x 32-bit (F 0x080008 T 0x08000F) 106 | parameter flash_reg_addr_map = 24'h080008; 107 | 108 | // Data Cache Regiseters 8 x 32-bit (F 0x080010 T 0x080017) 109 | parameter data_cache_reg_addr_map = 24'h080010; 110 | 111 | // Instruction Cache Regiseters 8 x 32-bit (F 0x080018 T 0x08001F) 112 | parameter instruction_cache_reg_addr_map = 24'h080018; 113 | 114 | // Timer Regiseters 4 x 32-bit (F 0x080020 T 0x080023) 115 | parameter timer_reg_addr_map = 24'h080020; 116 | 117 | // UART Regiseters 8 x 32-bit (F 0x080024 T 0x08002B) 118 | parameter uart_reg_addr_map = 24'h080024; 119 | 120 | 121 | // SDRAM Memory 8M x 32-bit using 2M x 8-bit x 4 bank IC's. 122 | // (F 0x7FFFFF T 0xFFFFFF) 123 | parameter sdram_mem_addr_map = 24'h7FFFFF; 124 | 125 | 126 | -------------------------------------------------------------------------------- /Verilog/data_port.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Controller Data Port Block 3 | 4 | FILE NAME: data_port.v 5 | VERSION: 1.0 6 | DATE: April 8nd, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It is the Data Port block. 13 | 14 | It will instantiate the following blocks in the ASIC: 15 | 16 | 1) Data input register 17 | 2) SDRAM control signals 18 | 3) SDRAM Data port 19 | 4) SDRAM Data port Multiplexor 20 | 21 | Hossein Amidi 22 | (C) April 2002 23 | 24 | *********************************************************/ 25 | 26 | // DEFINES 27 | `timescale 1ns / 10ps 28 | 29 | module data_port(// Input 30 | reset, 31 | clk0, 32 | clk0_2x, 33 | dm, 34 | oe, 35 | datain, 36 | wsadd, 37 | wba, 38 | wcs, 39 | wcke, 40 | wras, 41 | wcas, 42 | wwe, 43 | // Out 44 | dqm, 45 | dataout, 46 | add, 47 | ba, 48 | cs, 49 | cke, 50 | ras, 51 | cas, 52 | we, 53 | // Inout 54 | dq 55 | ); 56 | 57 | 58 | // Parameter 59 | `include "parameter.v" 60 | 61 | // Input 62 | input reset; 63 | input clk0; 64 | input clk0_2x; 65 | input [dqm_size - 1 : 0]dm; 66 | input oe; 67 | input [data_size - 1 : 0]datain; 68 | input [add_size - 1 : 0]wsadd; 69 | input [ba_size - 1 : 0]wba; 70 | input [cs_size - 1 : 0]wcs; 71 | input wcke; 72 | input wras; 73 | input wcas; 74 | input wwe; 75 | 76 | // Output 77 | output [dqm_size - 1 : 0]dqm; 78 | output [data_size - 1 : 0]dataout; 79 | output [add_size - 1 : 0]add; 80 | output [ba_size - 1 : 0]ba; 81 | output [cs_size - 1 : 0]cs; 82 | output cke; 83 | output ras; 84 | output cas; 85 | output we; 86 | 87 | // Inout 88 | inout [data_size - 1 : 0]dq; 89 | 90 | // Internal wires and reg 91 | wire reset; 92 | wire clk0; 93 | wire [dqm_size - 1 : 0]dm; 94 | wire [data_size - 1 : 0]datain; 95 | wire [dqm_size - 1 : 0]dqm; 96 | wire [data_size - 1 : 0]datain2; 97 | 98 | wire [add_size - 1 : 0]wsadd; 99 | wire [ba_size - 1 : 0]wba; 100 | wire [cs_size - 1 : 0]wcs; 101 | wire wcke; 102 | wire wras; 103 | wire wcas; 104 | wire wwe; 105 | wire [data_size - 1 : 0]wsdram_in; 106 | 107 | wire [add_size - 1 : 0]add; 108 | wire [ba_size - 1 : 0]ba; 109 | wire [cs_size - 1 : 0]cs; 110 | wire cke; 111 | wire ras; 112 | wire cas; 113 | wire we; 114 | wire [data_size - 1 : 0]dataout; 115 | 116 | wire clk0_2x; 117 | wire oe; 118 | wire [data_size - 1 : 0]dq; 119 | wire [data_size - 1 : 0]sdram_in; 120 | wire [data_size - 1 : 0]sdram_out; 121 | 122 | 123 | // Assignment 124 | 125 | 126 | /***************************** Sub Level Instantiation ********************************/ 127 | 128 | 129 | data_in_reg data_in_reg0(// Input 130 | .reset(reset), 131 | .clk0(clk0), 132 | .dm(dm), 133 | .datain(datain), 134 | // Output 135 | .dqm(dqm), 136 | .datain2(datain2) 137 | ); 138 | 139 | sdram_cntrl sdram_cntrl0(// Input 140 | .reset(reset), 141 | .clk0(clk0), 142 | .wsadd(wsadd), 143 | .wba(wba), 144 | .wcs(wcs), 145 | .wcke(wcke), 146 | .wras(wras), 147 | .wcas(wcas), 148 | .wwe(wwe), 149 | .sdram_in(sdram_in), 150 | // Output 151 | .add(add), 152 | .ba(ba), 153 | .cs(cs), 154 | .cke(cke), 155 | .ras(ras), 156 | .cas(cas), 157 | .we(we), 158 | .dataout(dataout) 159 | ); 160 | 161 | 162 | sdram_port sdram_port0( // Input 163 | .reset(reset), 164 | .clk0_2x(clk0_2x), 165 | .oe(oe), 166 | .datain2(datain2), 167 | .dq(dq), 168 | // Output 169 | .sdram_in(sdram_in), 170 | .sdram_out(sdram_out) 171 | ); 172 | 173 | sdram_mux sdram_mux0(// Input 174 | .sdram_out(sdram_out), 175 | .oe(oe), 176 | // Output 177 | .dq(dq) 178 | ); 179 | 180 | 181 | endmodule 182 | -------------------------------------------------------------------------------- /Verilog/command_if.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Controller Command Interface 3 | 4 | FILE NAME: command_if.v 5 | VERSION: 1.0 6 | DATE: April 8nd, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will decode the uProcessor command, its a command interface block. 13 | 14 | It will instantiate the following blocks in the ASIC: 15 | 16 | 1) Command Decoder 17 | 2) Internal Register 18 | 3) Command Acknowledge 19 | 4) Refresh Timer 20 | 21 | Hossein Amidi 22 | (C) April 2002 23 | 24 | *********************************************************/ 25 | 26 | // DEFINES 27 | `timescale 1ns / 10ps 28 | 29 | module command_if (// Input 30 | reset, 31 | clk0, 32 | paddr, 33 | cmd, 34 | cmack, 35 | ref_ack, 36 | // Output 37 | cmdack, 38 | caddr, 39 | nop, 40 | reada, 41 | writea, 42 | refresh, 43 | preacharge, 44 | load_mod, 45 | cas_lat, 46 | ras_cas, 47 | ref_dur, 48 | page_mod, 49 | bur_len, 50 | ref_req 51 | ); 52 | 53 | // Parameter 54 | `include "parameter.v" 55 | 56 | // Input 57 | input reset; 58 | input clk0; 59 | input [padd_size - 1 : 0]paddr; 60 | input [cmd_size - 1 : 0]cmd; 61 | input cmack; 62 | input ref_ack; 63 | 64 | // Output 65 | output cmdack; 66 | output [padd_size - 1 : 0]caddr; 67 | output nop; 68 | output reada; 69 | output writea; 70 | output refresh; 71 | output preacharge; 72 | output load_mod; 73 | output [cas_size - 1 : 0]cas_lat; 74 | output [rc_size - 1 : 0]ras_cas; 75 | output [ref_dur_size - 1 : 0]ref_dur; 76 | output page_mod; 77 | output [burst_size - 1 : 0]bur_len; 78 | output ref_req; 79 | 80 | // Internal wire and reg signals 81 | 82 | 83 | wire reset; 84 | wire clk0; 85 | wire [padd_size - 1 : 0]paddr; 86 | wire [cmd_size - 1 : 0]cmd; 87 | 88 | wire nop; 89 | wire reada; 90 | wire writea; 91 | wire refresh; 92 | wire preacharge; 93 | wire load_mod; 94 | wire load_time; 95 | wire load_rfcnt; 96 | wire [padd_size - 1 : 0]caddr; 97 | 98 | wire [cas_size - 1 : 0]cas_lat; 99 | wire [rc_size - 1 : 0]ras_cas; 100 | wire [ref_dur_size - 1 : 0]ref_dur; 101 | wire page_mod; 102 | wire [burst_size - 1 : 0]bur_len; 103 | wire [15:0]refresh_count; 104 | 105 | wire cmack; 106 | wire cmdack; 107 | wire ref_ack; 108 | wire ref_req; 109 | 110 | // Assignment 111 | 112 | 113 | /************************************ Sub-Level Instantiation *****************************/ 114 | 115 | cmd_decoder cmd_decoder0( // Input 116 | .reset(reset), 117 | .clk0(clk0), 118 | .paddr(paddr), 119 | .cmd(cmd), 120 | .cmdack(cmdack), 121 | // Output 122 | .nop(nop), 123 | .reada(reada), 124 | .writea(writea), 125 | .refresh(refresh), 126 | .preacharge(preacharge), 127 | .load_mod(load_mod), 128 | .load_time(load_time), 129 | .load_rfcnt(load_rfcnt), 130 | .caddr(caddr) 131 | ); 132 | 133 | 134 | internal_reg internal_reg0( // Input 135 | .reset(reset), 136 | .clk0(clk0), 137 | .load_time(load_time), 138 | .load_rfcnt(load_rfcnt), 139 | .caddr(caddr), 140 | // Output 141 | .cas_lat(cas_lat), 142 | .ras_cas(ras_cas), 143 | .ref_dur(ref_dur), 144 | .page_mod(page_mod), 145 | .bur_len(bur_len), 146 | .refresh_count(refresh_count) 147 | ); 148 | 149 | cmd_ack cmd_ack0(// Input 150 | .reset(reset), 151 | .clk0(clk0), 152 | .cmack(cmack), 153 | .load_time(load_time), 154 | .load_rfcnt(load_rfcnt), 155 | // Output 156 | .cmdack(cmdack) 157 | ); 158 | 159 | 160 | ref_timer ref_timer0(// Input 161 | .reset(reset), 162 | .clk0(clk0), 163 | .refresh_count(refresh_count), 164 | .bur_len(bur_len), 165 | .ref_ack(ref_ack), 166 | // Output 167 | .ref_req(ref_req) 168 | ); 169 | 170 | 171 | endmodule 172 | -------------------------------------------------------------------------------- /Verilog/oe_generator.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Output Enable Generator 3 | 4 | FILE NAME: oe_generator.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will generate the Output Enable signal. 13 | 14 | Hossein Amidi 15 | (C) April 2002 16 | 17 | *********************************************************/ 18 | 19 | // DEFINES 20 | `timescale 1ns / 10ps 21 | 22 | module oe_generator(// Input 23 | reset, 24 | clk0, 25 | page_mod, 26 | do_writea1, 27 | bur_len, 28 | cas_lat, 29 | do_preacharge, 30 | do_reada, 31 | do_refresh, 32 | // Output 33 | oe, 34 | oe4 35 | ); 36 | 37 | 38 | // Parameter 39 | `include "parameter.v" 40 | 41 | // Input 42 | input reset; 43 | input clk0; 44 | input page_mod; 45 | input do_writea1; 46 | input [burst_size - 1 : 0]bur_len; 47 | input [cas_size - 1 : 0]cas_lat; 48 | input do_preacharge; 49 | input do_reada; 50 | input do_refresh; 51 | 52 | // Output 53 | output oe; 54 | output oe4; 55 | 56 | // Internal wire and reg signals 57 | wire reset; 58 | wire clk0; 59 | wire page_mod; 60 | wire do_writea1; 61 | wire [burst_size - 1 : 0]bur_len; 62 | wire [cas_size - 1 : 0]cas_lat; 63 | wire do_preacharge; 64 | wire do_reada; 65 | wire do_refresh; 66 | 67 | reg oe; 68 | reg oe4; 69 | 70 | reg oe1; 71 | reg oe2; 72 | reg oe3; 73 | reg [7:0]oe_shift; 74 | 75 | // Assignment 76 | 77 | 78 | // logic that generates the oe signal for the data path module 79 | // For normal burst write he duration of oe is dependent on the configured burst length. 80 | // For page mode accesses(page_mod=1) the oe signal is turned on at the start of the write command 81 | // and is left on until a preacharge(page burst terminate) is detected. 82 | // 83 | always @(posedge reset or posedge clk0) 84 | begin 85 | if (reset == 1'b1) 86 | begin 87 | oe_shift <= 0; 88 | oe1 <= 0; 89 | oe2 <= 0; 90 | oe <= 0; 91 | end 92 | else 93 | begin 94 | if (page_mod == 0) 95 | begin 96 | if (do_writea1 == 1) 97 | begin 98 | if (bur_len == 1) // Set the shift register to the appropriate 99 | oe_shift <= 0; // value based on burst length. 100 | else if (bur_len == 2) 101 | oe_shift <= 1; 102 | else if (bur_len == 4) 103 | oe_shift <= 7; 104 | else if (bur_len == 8) 105 | oe_shift <= 127; 106 | oe1 <= 1; 107 | end 108 | else 109 | begin 110 | oe_shift[6:0] <= oe_shift[7:1]; // Do the shift operation 111 | oe_shift[7] <= 0; 112 | oe1 <= oe_shift[0]; 113 | oe2 <= oe1; 114 | oe3 <= oe2; 115 | oe4 <= oe3; 116 | if (cas_lat == 2) 117 | oe <= oe3; 118 | else 119 | oe <= oe4; 120 | end 121 | end 122 | else 123 | begin 124 | if (do_writea1 == 1) // oe generation for page mode accesses 125 | oe4 <= 1; 126 | else if (do_preacharge == 1 | do_reada == 1 | do_refresh) 127 | oe4 <= 0; 128 | oe <= oe4; 129 | end 130 | 131 | end 132 | end 133 | 134 | endmodule 135 | -------------------------------------------------------------------------------- /Verilog/sdramctrl_rtl.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Top Level SDRAM Controller ASIC Design Block 3 | 4 | FILE NAME: sdramctrl_rtl.v 5 | VERSION: 1.0 6 | DATE: April 8nd, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of SDRAM Controller ASIC verilog 12 | code. It will instantiate the following blocks in the ASIC: 13 | 14 | 1) Command Interface 15 | 2) Finite State Machine 16 | 3) Data Port 17 | 18 | Hossein Amidi 19 | (C) April 2002 20 | 21 | *********************************************************/ 22 | 23 | // DEFINES 24 | `timescale 1ns / 10ps 25 | 26 | // TOP MODULE 27 | module sdram_ctrl( 28 | // Inputs 29 | clk0, 30 | clk0_2x, 31 | reset, 32 | paddr, 33 | cmd, 34 | dm, 35 | datain, 36 | // Outputs 37 | cmdack, 38 | addr, 39 | cs, 40 | ras, 41 | cas, 42 | we, 43 | dqm, 44 | cke, 45 | ba, 46 | dataout, 47 | // Inouts 48 | dq 49 | ); 50 | 51 | // Parameter 52 | `include "parameter.v" 53 | 54 | 55 | // Inputs 56 | input clk0; 57 | input clk0_2x; 58 | input reset; 59 | input [padd_size - 1 : 0]paddr; 60 | input [cmd_size - 1 : 0]cmd; 61 | input [dqm_size - 1 : 0]dm; 62 | input [data_size - 1 : 0]datain; 63 | 64 | // Outputs 65 | output cmdack; 66 | output [add_size - 1 : 0]addr; 67 | output [cs_size - 1 : 0]cs; 68 | output ras; 69 | output cas; 70 | output we; 71 | output [dqm_size - 1 : 0]dqm; 72 | output cke; 73 | output [ba_size - 1 : 0]ba; 74 | output [data_size - 1 : 0]dataout; 75 | 76 | // Inouts 77 | inout [data_size - 1 : 0]dq; 78 | 79 | 80 | // Signal Declarations 81 | wire clk0; 82 | wire clk0_2x; 83 | wire reset; 84 | wire [padd_size - 1 : 0]paddr; 85 | wire [padd_size - 1 : 0]wpaddr; 86 | wire [cmd_size - 1 : 0]cmd; 87 | wire [dqm_size - 1 : 0]dm; 88 | wire cmack; 89 | 90 | wire cmdack; 91 | wire [add_size - 1 : 0]addr; 92 | wire [cs_size - 1 : 0]cs; 93 | wire ras; 94 | wire cas; 95 | wire we; 96 | wire cke; 97 | wire [ba_size - 1 : 0]ba; 98 | 99 | wire nop; 100 | wire reada; 101 | wire writea; 102 | wire refresh; 103 | wire preacharge; 104 | wire load_mod; 105 | 106 | wire oe; 107 | 108 | wire [cas_size - 1 : 0]cas_lat; 109 | wire [rc_size - 1 : 0]ras_cas; 110 | wire [ref_dur_size - 1 : 0]ref_dur; 111 | wire page_mod; 112 | wire [burst_size - 1 : 0]bur_len; 113 | 114 | wire ref_ack; 115 | wire ref_req; 116 | wire resetn; 117 | 118 | 119 | wire [add_size - 1 : 0]wsadd; 120 | wire [ba_size - 1 : 0]wba; 121 | wire [cs_size - 1 : 0]wcs; 122 | wire wcke; 123 | wire wras; 124 | wire wcas; 125 | wire wwe; 126 | 127 | // Assignment statments 128 | 129 | 130 | /*----------------------------Sub Level Module Instantiation------------------------*/ 131 | 132 | 133 | command_if cmdif_0(// Input 134 | .reset(reset), 135 | .clk0(clk0), 136 | .paddr(paddr), 137 | .cmd(cmd), 138 | .cmack(cmack), 139 | .ref_ack(ref_ack), 140 | // Output 141 | .cmdack(cmdack), 142 | .caddr(wpaddr), 143 | .nop(nop), 144 | .reada(reada), 145 | .writea(writea), 146 | .refresh(refresh), 147 | .preacharge(preacharge), 148 | .load_mod(load_mod), 149 | .cas_lat(cas_lat), 150 | .ras_cas(ras_cas), 151 | .ref_dur(ref_dur), 152 | .page_mod(page_mod), 153 | .bur_len(bur_len), 154 | .ref_req(ref_req) 155 | ); 156 | 157 | fsm fsm_0(// Input 158 | .reset(reset), 159 | .clk0(clk0), 160 | .nop(nop), 161 | .reada(reada), 162 | .writea(writea), 163 | .refresh(refresh), 164 | .preacharge(preacharge), 165 | .load_mod(load_mod), 166 | .caddr(wpaddr), 167 | .cas_lat(cas_lat), 168 | .ras_cas(ras_cas), 169 | .ref_dur(ref_dur), 170 | .page_mod(page_mod), 171 | .bur_len(bur_len), 172 | .ref_req(ref_req), 173 | // Output 174 | .sadd(wsadd), 175 | .cs(wcs), 176 | .ras(wras), 177 | .cas(wcas), 178 | .we(wwe), 179 | .cke(wcke), 180 | .ba(wba), 181 | .oe(oe), 182 | .ref_ack(ref_ack), 183 | .cmack(cmack) 184 | ); 185 | 186 | 187 | data_port data_0( // Input 188 | .reset(reset), 189 | .clk0(clk0), 190 | .clk0_2x(clk0_2x), 191 | .dm(dm), 192 | .oe(oe), 193 | .datain(datain), 194 | .wsadd(wsadd), 195 | .wba(wba), 196 | .wcs(wcs), 197 | .wcke(wcke), 198 | .wras(wras), 199 | .wcas(wcas), 200 | .wwe(wwe), 201 | // Output 202 | .dqm(dqm), 203 | .dataout(dataout), 204 | .add(addr), 205 | .ba(ba), 206 | .cs(cs), 207 | .cke(cke), 208 | .ras(ras), 209 | .cas(cas), 210 | .we(we), 211 | // Inout 212 | .dq(dq) 213 | ); 214 | 215 | endmodule 216 | 217 | 218 | 219 | -------------------------------------------------------------------------------- /Verilog/flash_ctrl.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level UART Device 3 | 4 | FILE NAME: uart.v 5 | VERSION: 1.0 6 | DATE: May 14th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of UART verilog code. 12 | 13 | It will instantiate the following blocks in the ASIC: 14 | 15 | 16 | Hossein Amidi 17 | (C) April 2002 18 | 19 | *********************************************************/ 20 | 21 | // DEFINES 22 | `timescale 1ns / 10ps 23 | 24 | // TOP MODULE 25 | module flash_ctrl(// Inputs 26 | reset, 27 | clk0, 28 | flash_host_addr, 29 | flash_host_cmd, 30 | flash_host_dataout, 31 | flash_datain, 32 | // Outputs 33 | flash_host_datain, 34 | flash_cle, 35 | flash_ale, 36 | flash_ce, 37 | flash_re, 38 | flash_we, 39 | flash_wp, 40 | flash_rb, 41 | flash_irq, 42 | flash_dataout 43 | ); 44 | 45 | 46 | // Parameter 47 | `include "parameter.v" 48 | 49 | // Inputs 50 | input reset; 51 | input clk0; 52 | input [padd_size - 1 : 0]flash_host_addr; 53 | input [cmd_size - 1 : 0]flash_host_cmd; 54 | input [data_size - 1 : 0]flash_host_dataout; 55 | input [flash_size - 1 : 0]flash_datain; 56 | 57 | // Outputs 58 | output [data_size - 1 : 0]flash_host_datain; 59 | output flash_cle; 60 | output flash_ale; 61 | output flash_ce; 62 | output flash_re; 63 | output flash_we; 64 | output flash_wp; 65 | output flash_rb; 66 | output flash_irq; 67 | output [flash_size - 1 : 0]flash_dataout; 68 | 69 | 70 | // Signal Declarations 71 | wire reset; 72 | wire clk0; 73 | wire [padd_size - 1 : 0]flash_host_addr; 74 | wire [cmd_size - 1 : 0]flash_host_cmd; 75 | wire [data_size - 1 : 0]flash_host_dataout; 76 | wire [flash_size - 1 : 0]flash_datain; 77 | 78 | wire [data_size - 1 : 0]flash_host_datain; 79 | reg flash_cle; 80 | reg flash_ale; 81 | reg flash_ce; 82 | reg flash_re; 83 | reg flash_we; 84 | reg flash_wp; 85 | reg flash_rb; 86 | reg flash_irq; 87 | reg [flash_size - 1 : 0]flash_dataout; 88 | 89 | 90 | // Internal Registers 91 | reg [Byte_size - 1 : 0]flash_reg_dataout; 92 | 93 | // Assignment statments 94 | assign flash_host_datain = flash_reg_dataout; 95 | 96 | /***************** Internal Register of Uart configuration *******************/ 97 | reg [flash_reg_width - 1 : 0] flash_register [flash_reg_depth - 1 : 0]; 98 | 99 | 100 | // Circuit for internal Register 101 | always @(posedge reset or posedge clk0) 102 | begin 103 | if(reset == 1'b1) 104 | begin 105 | flash_reg_dataout <= 8'h0; 106 | flash_register[0] <= 8'h0; 107 | flash_register[1] <= 8'h0; 108 | flash_register[2] <= 8'h0; 109 | flash_register[3] <= 8'h0; 110 | flash_register[4] <= 8'h0; 111 | flash_register[5] <= 8'h0; 112 | flash_register[6] <= 8'h0; 113 | flash_register[7] <= 8'h0; 114 | end 115 | else 116 | begin 117 | if(flash_host_cmd == 3'b010) 118 | begin 119 | case(flash_host_addr) 120 | 24'h080008: flash_register[0] <= flash_host_dataout; 121 | 24'h080009: flash_register[1] <= flash_host_dataout; 122 | 24'h08000A: flash_register[2] <= flash_host_dataout; 123 | 24'h08000B: flash_register[3] <= flash_host_dataout; 124 | 24'h08000C: flash_register[4] <= flash_host_dataout; 125 | 24'h08000D: flash_register[5] <= flash_host_dataout; 126 | 24'h08000E: flash_register[6] <= flash_host_dataout; 127 | 24'h08000F: flash_register[7] <= flash_host_dataout; 128 | endcase 129 | end 130 | else 131 | if(flash_host_cmd == 3'b001) 132 | begin 133 | case(flash_host_addr) 134 | 24'h080008: flash_reg_dataout <= flash_register[0]; 135 | 24'h080009: flash_reg_dataout <= flash_register[1]; 136 | 24'h08000A: flash_reg_dataout <= flash_register[2]; 137 | 24'h08000B: flash_reg_dataout <= flash_register[3]; 138 | 24'h08000C: flash_reg_dataout <= flash_register[4]; 139 | 24'h08000D: flash_reg_dataout <= flash_register[5]; 140 | 24'h08000E: flash_reg_dataout <= flash_register[6]; 141 | 24'h08000F: flash_reg_dataout <= flash_register[7]; 142 | endcase 143 | end 144 | end 145 | 146 | end 147 | 148 | 149 | always @(posedge reset or posedge clk0) 150 | begin 151 | if(reset == 1'b1) 152 | begin 153 | flash_cle <= 1'b0; 154 | flash_ale <= 1'b0; 155 | flash_ce <= 1'b0; 156 | flash_re <= 1'b0; 157 | flash_we <= 1'b0; 158 | flash_wp <= 1'b0; 159 | flash_rb <= 1'b0; 160 | flash_irq <= 1'b0; 161 | flash_dataout <= 8'h0; 162 | end 163 | else 164 | begin 165 | flash_cle <= flash_host_addr[7]; 166 | flash_ale <= flash_host_addr[0] & flash_host_cmd[0]; 167 | flash_ce <= flash_host_addr[1] & flash_host_cmd[1]; 168 | flash_re <= flash_host_addr[2] & flash_host_cmd[2]; 169 | flash_we <= flash_host_addr[3]; 170 | flash_wp <= flash_host_addr[4]; 171 | flash_rb <= flash_host_addr[5]; 172 | flash_irq <= flash_host_addr[6]; 173 | flash_dataout <= flash_datain; 174 | end 175 | end 176 | 177 | endmodule 178 | -------------------------------------------------------------------------------- /Verilog/timer.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Timer Device 3 | 4 | FILE NAME: timer.v 5 | VERSION: 1.0 6 | DATE: May 21th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of Timer verilog code. 12 | 13 | It will instantiate the following blocks in the ASIC: 14 | 15 | 16 | Hossein Amidi 17 | (C) April 2002 18 | 19 | *********************************************************/ 20 | 21 | // DEFINES 22 | `timescale 1ns / 10ps 23 | 24 | // TOP MODULE 25 | module timer(// Inputs 26 | reset, 27 | clk0, 28 | timer_host_datain, 29 | timer_cmd, 30 | timer_addr, 31 | // Outputs 32 | timer_host_dataout, 33 | timer_irq 34 | ); 35 | 36 | 37 | // Parameter 38 | `include "parameter.v" 39 | 40 | // Inputs 41 | input reset; 42 | input clk0; 43 | input [data_size - 1 : 0]timer_host_datain; 44 | input [cmd_size - 1 : 0]timer_cmd; 45 | input [padd_size - 1 : 0]timer_addr; 46 | 47 | // Outputs 48 | output [data_size - 1 : 0]timer_host_dataout; 49 | output timer_irq; 50 | 51 | 52 | // Signal Declarations 53 | wire reset; 54 | wire clk0; 55 | wire [data_size - 1 : 0]timer_host_datain; 56 | wire [cmd_size - 1 : 0]timer_cmd; 57 | wire [padd_size - 1 : 0]timer_addr; 58 | 59 | wire [data_size - 1 : 0]timer_host_dataout; 60 | reg timer_irq; 61 | 62 | reg [data_size - 1 : 0]timer_reg_dataout; 63 | reg [timer_size - 1 : 0]timer; 64 | 65 | wire [timer_reg_width - 1 : 0] timer_register0; 66 | wire [timer_reg_width - 1 : 0] timer_register1; 67 | wire [timer_reg_width - 1 : 0] timer_register2; 68 | wire [timer_reg_width - 1 : 0] timer_register3; 69 | 70 | wire timed_out; 71 | wire running; 72 | wire irq_enb; 73 | wire continuous; 74 | wire timer_start; 75 | wire timer_stop; 76 | 77 | // Internal Registers 78 | 79 | /***************** Internal Register of Timer configuration *******************/ 80 | reg [timer_reg_width - 1 : 0] timer_register [timer_reg_depth - 1 : 0]; 81 | 82 | 83 | // Assignment statments 84 | assign timer_host_dataout = timer_reg_dataout; 85 | 86 | // Internal Register Mapping 87 | assign timer_register0 = timer_register[0]; // Status Register 88 | assign timer_register1 = timer_register[1]; // Control Register 89 | assign timer_register2 = timer_register[2]; // Time-Out Period 90 | assign timer_register3 = timer_register[3]; // Snapshot Register 91 | 92 | // Status Register 93 | assign timed_out = timer_register0[0]; 94 | assign running = timer_register0[1]; 95 | 96 | // Control Register 97 | assign irq_enb = timer_register1[0]; 98 | assign continuous = timer_register1[1]; 99 | assign timer_start = timer_register1[2]; 100 | assign timer_stop = timer_register1[3]; 101 | 102 | 103 | // Setting the internal Registers by the Host (CPU) 104 | always @(posedge reset or posedge clk0) 105 | begin 106 | if(reset == 1'b1) 107 | begin 108 | timer_reg_dataout <= 32'h0; 109 | timer_register[0] <= 32'h0; 110 | timer_register[1] <= 32'h0; 111 | timer_register[2] <= 32'h0; 112 | timer_register[3] <= 32'h0; 113 | end 114 | else 115 | begin 116 | if(timer_cmd == 3'b010) 117 | begin 118 | case(timer_addr) 119 | 24'h080020: timer_register[0] <= timer_host_datain; // Status Register 120 | 24'h080021: timer_register[1] <= timer_host_datain; // Control Register 121 | 24'h080022: timer_register[2] <= timer_host_datain; // Time-Out Period 122 | 24'h080023: timer_register[3] <= timer_host_datain; // Timer Snapshot 123 | endcase 124 | end 125 | else 126 | if(timer_cmd == 3'b001) 127 | begin 128 | case(timer_addr) 129 | 24'h080020: timer_reg_dataout <= timer_register[0]; 130 | 24'h080021: timer_reg_dataout <= timer_register[1]; 131 | 24'h080022: timer_reg_dataout <= timer_register[2]; 132 | 24'h080023: timer_reg_dataout <= timer_register[3]; 133 | endcase 134 | end 135 | 136 | // Set the Status Register timed_out bit to one if timer is in continuous mode 137 | // and timer reached the maximum time set by CPU 138 | if((continuous == 1'b1) && (timer == timer_register2)) 139 | timer_register[0] <= timer_register0 & 32'h1; 140 | else 141 | timer_register[0] <= timer_register0 & 32'h0; 142 | 143 | // Set the Status Register running bit to one if the timer started and not reached 144 | // the maximum value 145 | if((timer_start == 1'b1) && (timer_irq == 1'b0)) 146 | timer_register[0] <= timer_register0 & 32'h2; 147 | else 148 | timer_register[0] <= timer_register0 & 32'h0; 149 | 150 | // Set the timer snapshot to current value of timer for CPU to evaluate 151 | timer_register[3] <= timer; 152 | 153 | end 154 | end 155 | 156 | 157 | // 32-bit Timer and it's control signals base on the internal register settings 158 | always @(posedge reset or posedge clk0) 159 | begin 160 | if(reset == 1'b1) 161 | begin 162 | timer <= 32'h0; 163 | end 164 | else 165 | begin 166 | // Star Counting 167 | if((timer_start == 1'b1) && (timer_stop == 1'b0)) 168 | timer <= timer + 1; 169 | else 170 | timer <= timer; 171 | // Stop Counting 172 | if(timer_stop == 1'b1) 173 | timer <= timer; 174 | // Set time to begin (zero) value 175 | if((continuous == 1'b1) && (timer == timer_register2)) 176 | timer <= 32'h0; 177 | // Set the irq pin if the irq_enb is one and timmer reaches the maximum 178 | if((irq_enb == 1'b1) && (timer == timer_register2)) 179 | timer_irq <= 1'b1; 180 | else 181 | timer_irq <= 1'b0; 182 | 183 | end 184 | end 185 | 186 | 187 | endmodule 188 | -------------------------------------------------------------------------------- /Verilog/ALU.V: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Sub Level Arithmatic Logic Unit Block 3 | 4 | FILE NAME: alu.v 5 | VERSION: 1.0 6 | DATE: September 28th, 2001 7 | AUTHOR: Hossein Amidi 8 | COMPANY: California Unique Electrical Co. 9 | CODE TYPE: Register Transfer Level 10 | 11 | Instantiations: 12 | 13 | DESCRIPTION: 14 | Sub Level RTL Arithmatic Logic Unit block 15 | 16 | Hossein Amidi 17 | (C) September 2001 18 | California Unique Electric 19 | 20 | ***************************************************************************************/ 21 | 22 | `timescale 1ns / 1ps 23 | 24 | module ALU (// Input 25 | ALUSrcA, 26 | ALUSrcB, 27 | OpCode, 28 | CurrentState, 29 | // Output 30 | ALUDataOut 31 | ); 32 | 33 | // Parameter 34 | parameter DataWidth = 32; 35 | parameter OpcodeSize = 8; 36 | parameter StateSize = 2; 37 | parameter FunctionSize = 8; 38 | 39 | // Instructions options 40 | parameter LDA = 8'h0; 41 | parameter STO = 8'h1; 42 | parameter ADD = 8'h2; 43 | parameter SUB = 8'h3; 44 | parameter JMP = 8'h4; 45 | parameter JGE = 8'h5; 46 | parameter JNE = 8'h6; 47 | parameter STP = 8'h7; 48 | parameter SHR = 8'h8; 49 | parameter SHL = 8'h9; 50 | parameter AND = 8'ha; 51 | parameter OR = 8'hb; 52 | parameter XOR = 8'hc; 53 | parameter COM = 8'hd; 54 | parameter SWP = 8'he; 55 | parameter NOP = 8'hf; 56 | 57 | // Instruction for Memory Map devices 58 | parameter MAP = 9'h64; 59 | 60 | // Current State options 61 | parameter Init = 2'b00; 62 | parameter InstrFetch = 2'b01; 63 | parameter InstrExec = 2'b10; 64 | 65 | // Function Select options 66 | parameter FnAdd = 8'b0000_0000; 67 | parameter FnSub = 8'b0000_0001; 68 | parameter FnPassB = 8'b0000_0010; 69 | parameter FnIncB = 8'b0000_0011; 70 | parameter FnShtR = 8'b0000_0100; 71 | parameter FnShtL = 8'b0000_0101; 72 | parameter FnAnd = 8'b0000_0110; 73 | parameter FnOr = 8'b0000_0111; 74 | parameter FnXor = 8'b0000_1000; 75 | parameter FnCom = 8'b0000_1001; 76 | parameter FnSwp = 8'b0000_1010; 77 | parameter FnNop = 8'b0000_1011; 78 | 79 | // Input 80 | input [DataWidth - 1 : 0] ALUSrcA; 81 | input [DataWidth - 1 : 0] ALUSrcB; 82 | input [OpcodeSize - 1 : 0] OpCode; 83 | input [StateSize - 1 : 0] CurrentState; 84 | 85 | // Output 86 | output [DataWidth - 1 : 0] ALUDataOut; 87 | 88 | // Signal Assignments 89 | reg [DataWidth - 1 : 0] ALUDataOut; 90 | reg [FunctionSize - 1 : 0] FunctSel; 91 | reg CIn; 92 | 93 | wire [DataWidth - 1 : 0] AIn, BIn; 94 | 95 | 96 | // Assignment 97 | assign AIn = ALUSrcA; 98 | assign BIn = ALUSrcB; 99 | 100 | 101 | 102 | always @(OpCode or CurrentState) 103 | begin 104 | if (CurrentState == InstrFetch) 105 | begin 106 | if (OpCode != STP) // In the Fetch cycle increment PC 107 | begin 108 | FunctSel <= FnIncB; 109 | CIn <= 1; 110 | end 111 | else 112 | begin 113 | FunctSel <= FnPassB; 114 | CIn <= 0; 115 | end 116 | end 117 | else 118 | if(CurrentState == InstrExec) 119 | begin 120 | case (OpCode) 121 | LDA : 122 | begin 123 | FunctSel <= FnPassB; 124 | CIn <= 0; 125 | end 126 | 127 | STO : 128 | begin 129 | FunctSel <= FnAdd; 130 | CIn <= 0; 131 | end 132 | 133 | ADD : 134 | begin 135 | FunctSel <= FnAdd; 136 | CIn <= 0; 137 | end 138 | 139 | SUB : 140 | begin 141 | FunctSel <= FnSub; 142 | CIn <= 0; 143 | end 144 | 145 | JMP : 146 | begin 147 | FunctSel <= FnPassB; 148 | CIn <= 0; 149 | end 150 | 151 | JGE : 152 | begin 153 | FunctSel <= FnPassB; 154 | CIn <= 0; 155 | end 156 | 157 | JNE : 158 | begin 159 | FunctSel <= FnPassB; 160 | CIn <= 0; 161 | end 162 | 163 | STP : 164 | begin 165 | FunctSel <= FnPassB; 166 | CIn <= 0; 167 | end 168 | 169 | SHR : 170 | begin 171 | FunctSel <= FnShtR; 172 | CIn <= 0; 173 | end 174 | 175 | SHL : 176 | begin 177 | FunctSel <= FnShtL; 178 | CIn <= 0; 179 | end 180 | 181 | AND : 182 | begin 183 | FunctSel <= FnAnd; 184 | CIn <= 0; 185 | end 186 | 187 | OR : 188 | begin 189 | FunctSel <= FnOr; 190 | CIn <= 0; 191 | end 192 | 193 | XOR : 194 | begin 195 | FunctSel <= FnXor; 196 | CIn <= 0; 197 | end 198 | 199 | COM : 200 | begin 201 | FunctSel <= FnCom; 202 | CIn <= 0; 203 | end 204 | 205 | SWP : 206 | begin 207 | FunctSel <= FnSwp; 208 | CIn <= 0; 209 | end 210 | 211 | NOP : 212 | begin 213 | FunctSel <= FnNop; 214 | CIn <= 0; 215 | end 216 | 217 | default : ; 218 | endcase 219 | end 220 | end 221 | 222 | 223 | always @(AIn or BIn or CIn or FunctSel) 224 | begin 225 | case (FunctSel) 226 | FnAdd : ALUDataOut <= AIn + BIn; 227 | FnSub : ALUDataOut <= AIn - BIn; 228 | FnPassB : ALUDataOut <= BIn; 229 | FnIncB : ALUDataOut <= BIn + CIn; 230 | FnShtR : ALUDataOut <= AIn >> 1; 231 | FnShtL : ALUDataOut <= AIn << 1; 232 | FnAnd : ALUDataOut <= AIn & BIn; 233 | FnOr : ALUDataOut <= AIn | BIn; 234 | FnXor : ALUDataOut <= AIn ^ BIn; 235 | FnCom : ALUDataOut <= ~BIn; 236 | FnSwp : ALUDataOut <= {BIn[15:0],BIn[31:16]}; 237 | FnNop : ALUDataOut <= BIn; 238 | default : ALUDataOut <= AIn + BIn; 239 | endcase 240 | end 241 | 242 | 243 | endmodule 244 | -------------------------------------------------------------------------------- /Verilog/fsm.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Controller FSM Block 3 | 4 | FILE NAME: fsm.v 5 | VERSION: 1.0 6 | DATE: April 8nd, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It is the signal generator Finite State Machine for SDRAM Controller 13 | 14 | It will instantiate the following blocks in the ASIC: 15 | 16 | 1) Ras-to-CAS Delay counter 17 | 2) Refresh Acknowledge 18 | 3) Output Enbable generator 19 | 4) Command generator 20 | 5) Command detector 21 | 22 | 23 | Hossein Amidi 24 | (C) April 2002 25 | 26 | *********************************************************/ 27 | 28 | // DEFINES 29 | `timescale 1ns / 10ps 30 | 31 | 32 | module fsm(//Input 33 | reset, 34 | clk0, 35 | nop, 36 | reada, 37 | writea, 38 | refresh, 39 | preacharge, 40 | load_mod, 41 | caddr, 42 | cas_lat, 43 | ras_cas, 44 | ref_dur, 45 | page_mod, 46 | bur_len, 47 | ref_req, 48 | // Output 49 | sadd, 50 | cs, 51 | ras, 52 | cas, 53 | we, 54 | cke, 55 | ba, 56 | oe, 57 | ref_ack, 58 | cmack 59 | ); 60 | 61 | 62 | // Parameter 63 | `include "parameter.v" 64 | 65 | // Input 66 | input reset; 67 | input clk0; 68 | input nop; 69 | input reada; 70 | input writea; 71 | input refresh; 72 | input preacharge; 73 | input load_mod; 74 | input [padd_size - 1 : 0]caddr; 75 | input [cas_size - 1 : 0]cas_lat; 76 | input [rc_size - 1 : 0]ras_cas; 77 | input [ref_dur_size - 1 : 0]ref_dur; 78 | input page_mod; 79 | input [burst_size - 1 : 0]bur_len; 80 | input ref_req; 81 | 82 | // Output 83 | output [add_size - 1 : 0]sadd; 84 | output [cs_size - 1 : 0]cs; 85 | output ras; 86 | output cas; 87 | output we; 88 | output cke; 89 | output [ba_size - 1 : 0]ba; 90 | output oe; 91 | output ref_ack; 92 | output cmack; 93 | 94 | // Wires and Reg signals 95 | wire oe; 96 | wire do_nop; 97 | wire do_reada; 98 | wire do_writea; 99 | wire do_writea1; 100 | wire do_refresh; 101 | wire do_preacharge; 102 | wire do_load_mod; 103 | 104 | wire command_done; 105 | wire [7:0] command_delay; 106 | wire do_act; 107 | wire rw_flag; 108 | wire [3:0] rp_shift; 109 | wire rp_done; 110 | 111 | wire [row_size - 1:0] rowaddr; 112 | wire [col_size - 1:0] coladdr; 113 | wire [bank_size - 1:0] bankaddr; 114 | 115 | 116 | wire reset; 117 | wire clk0; 118 | wire [rc_size - 1 : 0]ras_cas; 119 | wire do_rw; 120 | 121 | wire ref_req; 122 | wire cmack; 123 | wire ref_ack; 124 | 125 | 126 | wire page_mod; 127 | 128 | wire [burst_size - 1 : 0]bur_len; 129 | wire [cas_size - 1 : 0]cas_lat; 130 | 131 | wire oe4; 132 | 133 | 134 | // Assignments 135 | assign rowaddr = caddr[rowstart + row_size - 1 : rowstart]; // assignment of the row address bits from sadd 136 | assign coladdr = caddr[colstart + col_size - 1 : colstart]; // assignment of the column address bits 137 | assign bankaddr = caddr[bankstart + bank_size - 1 : bankstart]; // assignment of the bank address bits 138 | 139 | 140 | 141 | /*********************************** Sub Level Instantiation *****************************/ 142 | 143 | ras_cas_delay ras_cas_delay0( // Input 144 | .reset(reset), 145 | .clk0(clk0), 146 | .do_reada(do_reada), 147 | .do_writea(do_writea), 148 | .ras_cas(ras_cas), 149 | // Output 150 | .do_rw(do_rw) 151 | ); 152 | 153 | 154 | ref_ack ref_ack0(// Input 155 | .reset(reset), 156 | .clk0(clk0), 157 | .do_refresh(do_refresh), 158 | .do_reada(do_reada), 159 | .do_writea(do_writea), 160 | .do_preacharge(do_preacharge), 161 | .do_load_mod(do_load_mod), 162 | .ref_req(ref_req), 163 | // Output 164 | .cmack(cmack), 165 | .ref_ack(ref_ack) 166 | ); 167 | 168 | oe_generator oe_gen0(// Input 169 | .reset(reset), 170 | .clk0(clk0), 171 | .page_mod(page_mod), 172 | .do_writea1(do_writea1), 173 | .bur_len(bur_len), 174 | .cas_lat(cas_lat), 175 | .do_preacharge(do_preacharge), 176 | .do_reada(do_reada), 177 | .do_refresh(do_refresh), 178 | // Output 179 | .oe(oe), 180 | .oe4(oe4) 181 | ); 182 | 183 | cmd_generator cmd_generator0( // Input 184 | .reset(reset), 185 | .clk0(clk0), 186 | .do_reada(do_reada), 187 | .do_writea(do_writea), 188 | .do_preacharge(do_preacharge), 189 | .do_rw(do_rw), 190 | .rowaddr(rowaddr), 191 | .coladdr(coladdr), 192 | .bankaddr(bankaddr), 193 | .page_mod(page_mod), 194 | .do_load_mod(do_load_mod), 195 | .do_refresh(do_refresh), 196 | .caddr(caddr), 197 | .do_nop(do_nop), 198 | .rw_flag(rw_flag), 199 | .oe4(oe4), 200 | // Output 201 | .sadd(sadd), 202 | .ba(ba), 203 | .cs(cs), 204 | .ras(ras), 205 | .cas(cas), 206 | .we(we), 207 | .cke(cke) 208 | ); 209 | 210 | 211 | cmd_detector cmd_detector0(// Input 212 | .reset(reset), 213 | .clk0(clk0), 214 | .nop(nop), 215 | .ref_req(ref_req), 216 | .refresh(refresh), 217 | .reada(reada), 218 | .writea(writea), 219 | .preacharge(preacharge), 220 | .load_mod(load_mod), 221 | .ref_dur(ref_dur), 222 | // Output 223 | .do_nop(do_nop), 224 | .do_reada(do_reada), 225 | .do_writea(do_writea), 226 | .do_writea1(do_writea1), 227 | .do_refresh(do_refresh), 228 | .do_preacharge(do_preacharge), 229 | .do_load_mod(do_load_mod), 230 | .rw_flag(rw_flag) 231 | ); 232 | 233 | 234 | endmodule 235 | -------------------------------------------------------------------------------- /Test_Bench_Verilog/Top_level_tb.tf: -------------------------------------------------------------------------------- 1 | /************************************************************ 2 | MODULE: Top Level Test Bench for System On A Chip Design 3 | 4 | FILE NAME: Top_level_tb.tf 5 | DATE: May 28th, 2002 6 | AUTHOR: Hossein Amidi 7 | COMPANY: 8 | CODE TYPE: Behavioral Transfer Level 9 | 10 | DESCRIPTION: This module is the top level Behavioral code of System On a Chip Testbench in 11 | Verilog code. 12 | 13 | It will instantiate the following blocks in the ASIC: 14 | 15 | 1) SOC 16 | 2) SDRAM Behavioral Model 17 | 18 | Hossein Amidi 19 | (C) May 2002 20 | 21 | *********************************************************/ 22 | 23 | // DEFINES 24 | `timescale 1ns / 10ps 25 | 26 | module testbench; 27 | 28 | // Parameter 29 | `include "parameter.v" 30 | 31 | // Inputs 32 | reg clk; 33 | reg reset; 34 | reg irq; 35 | reg ser_rxd; 36 | wire [flash_size - 1 : 0]flash_datain; 37 | 38 | // Outputs 39 | wire [add_size - 1 : 0]addr; 40 | wire [cs_size - 1 : 0]cs; 41 | wire ras; 42 | wire cas; 43 | wire we; 44 | wire [dqm_size - 1 : 0]dqm; 45 | wire cke; 46 | wire [ba_size - 1 : 0]ba; 47 | wire pllclk; 48 | wire halted; 49 | wire ser_txd; 50 | wire flash_cle; 51 | wire flash_ale; 52 | wire flash_ce; 53 | wire flash_re; 54 | wire flash_we; 55 | wire flash_wp; 56 | wire flash_rb; 57 | wire flash_irq; 58 | wire [flash_size - 1 : 0]flash_dataout; 59 | 60 | 61 | // Bidirs 62 | wire [data_size - 1 : 0]dq; 63 | 64 | // Internal wires 65 | integer i; 66 | wire [flash_size - 1 : 0]wflash_dataout; 67 | 68 | reg pre; 69 | reg vdd; 70 | 71 | wire pll_lock; 72 | 73 | wire [data_size - 1 : 0]mem_dataout; 74 | wire [data_size - 1 : 0]mem_datain; 75 | wire [padd_size - 1 : 0]mem_addr; 76 | wire memreq; 77 | wire rdwrbar; 78 | 79 | 80 | 81 | /*---------------------------------Instantiation of Modules-------------------------*/ 82 | 83 | MEM Memory ( // Input 84 | .DataIn(mem_dataout), 85 | .Address(mem_addr), 86 | .MemReq(memreq), 87 | .RdWrBar(rdwrbar), 88 | .clock(pllclk), 89 | // .pll_lock(pll_lock), 90 | // Output 91 | .DataOut(mem_datain) 92 | ); 93 | 94 | 95 | k9f1g08u0m flash_0( // Input 96 | .ceb(flash_ce), 97 | .cle(flash_cle), 98 | .ale(flash_ale), 99 | .web(flash_we), 100 | .reb(flash_re), 101 | .io(wflash_dataout), 102 | .wpb(flash_wp), 103 | .rbb(flash_rb), 104 | .pre(pre), 105 | .vdd(vdd) 106 | ); 107 | 108 | 109 | sdram sdram_0(// Inputs 110 | .Addr(addr), 111 | .Ba(ba), 112 | .Clk(pllclk), 113 | .Cke(cke), 114 | .Cs_n(cs[0]), 115 | .Ras_n(ras), 116 | .Cas_n(cas), 117 | .We_n(we), 118 | .Dqm(dm), 119 | // Inouts 120 | .Dq(dq[7:0]) 121 | ); 122 | 123 | 124 | sdram sdram_1(// Inputs 125 | .Addr(addr), 126 | .Ba(ba), 127 | .Clk(pllclk), 128 | .Cke(cke), 129 | .Cs_n(cs[0]), 130 | .Ras_n(ras), 131 | .Cas_n(cas), 132 | .We_n(we), 133 | .Dqm(dm), 134 | // Inouts 135 | .Dq(dq[15:8]) 136 | ); 137 | 138 | sdram sdram_2(// Inputs 139 | .Addr(addr), 140 | .Ba(ba), 141 | .Clk(pllclk), 142 | .Cke(cke), 143 | .Cs_n(cs[0]), 144 | .Ras_n(ras), 145 | .Cas_n(cas), 146 | .We_n(we), 147 | .Dqm(dm), 148 | // Inouts 149 | .Dq(dq[23:16]) 150 | ); 151 | 152 | 153 | sdram sdram_3(// Inputs 154 | .Addr(addr), 155 | .Ba(ba), 156 | .Clk(pllclk), 157 | .Cke(cke), 158 | .Cs_n(cs[0]), 159 | .Ras_n(ras), 160 | .Cas_n(cas), 161 | .We_n(we), 162 | .Dqm(dm), 163 | // Inouts 164 | .Dq(dq[31:24]) 165 | ); 166 | 167 | soc soc_0 (// Input 168 | .clk(clk), 169 | .reset(reset), 170 | .irq(irq), 171 | .ser_rxd(ser_rxd), 172 | .flash_datain(flash_datain), 173 | .mem_datain(mem_datain), 174 | // Output 175 | .pll_lock(pll_lock), 176 | .addr(addr), 177 | .cs(cs), 178 | .ras(ras), 179 | .cas(cas), 180 | .we(we), 181 | .dqm(dqm), 182 | .cke(cke), 183 | .ba(ba), 184 | .pllclk(pllclk), 185 | .halted(halted), 186 | .ser_txd(ser_txd), 187 | .flash_cle(flash_cle), 188 | .flash_ale(flash_ale), 189 | .flash_ce(flash_ce), 190 | .flash_re(flash_re), 191 | .flash_we(flash_we), 192 | .flash_wp(flash_wp), 193 | .flash_rb(flash_rb), 194 | .flash_irq(flash_irq), 195 | .flash_dataout(flash_dataout), 196 | .mem_dataout(mem_dataout), 197 | .mem_addr(mem_addr), 198 | .mem_req(memreq), 199 | .mem_rdwr(rdwrbar), 200 | // Inout 201 | .dq(dq) 202 | ); 203 | 204 | 205 | 206 | 207 | 208 | initial begin 209 | clk = 0; 210 | reset = 0; 211 | irq = 0; 212 | ser_rxd = 0; 213 | pre = 0; 214 | vdd = 0; 215 | i = 0; 216 | end 217 | 218 | always 219 | begin 220 | #10 clk <= ~clk; 221 | end 222 | 223 | always 224 | begin 225 | #40 ser_rxd <= ~ser_rxd; 226 | end 227 | 228 | 229 | task init; 230 | begin 231 | #10 $display("Reset in process, at time %t",$time); 232 | #40 reset = 1'b1; 233 | $display("Reset is %d, at time %t",reset,$time); 234 | #20 reset = 1'b0; 235 | $display("Reset is %d, at time %t",reset,$time); 236 | $display("PLL Lock is %d, at time %t",soc_0.dll_0.pll_lock,$time); 237 | #150 $display ("Wait for PLL's to Locks, at time %t ", $time); 238 | #80 $display("PLL Lock is %d, at time %t",soc_0.dll_0.pll_lock,$time); 239 | #50 $display ("Setting internal Register of Sub Modules, at time %t", $time); 240 | 241 | #40 $display("Initializing the Memory ..., at time %t",$time); 242 | for( i = 0 ; i < 31; i = i + 1) 243 | Memory.MEM_Data[i] = 32'h0; 244 | for(i = 0; i < 31; i = i + 1) 245 | $display("memory [%0d] = %h ", i, Memory.MEM_Data[i]); 246 | #40 $display("Memory Initialized to known value , at time %t",$time); 247 | 248 | end 249 | endtask 250 | 251 | 252 | task cpu; 253 | begin 254 | #50 255 | $display ("RISC CPU 32-bit Version 1.0. This is the BASIC CONFIDENCE TEST."); 256 | $display ("Loading program memory with %s", "program.txt"); 257 | $readmemb("program.txt",Memory.MEM_Data); 258 | $display ("Memory loading is done ... "); 259 | 260 | for(i = 0; i < 80; i = i + 1) 261 | $display("memory [%0d] = %h ", i, Memory.MEM_Data[i]); 262 | end 263 | endtask 264 | 265 | initial 266 | begin 267 | init; 268 | cpu; 269 | $display ("End of Simulation, at time %t", $time); 270 | #2750 271 | $stop; 272 | $finish; 273 | end 274 | 275 | 276 | endmodule 277 | 278 | -------------------------------------------------------------------------------- /Verilog/cmd_detector.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Command Detector 3 | 4 | FILE NAME: cmd_detector.v 5 | VERSION: 1.0 6 | DATE: May 2nd, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will detect the uProcessor command and create appropriate internal signal 13 | for SDRAM Controller FSM. 14 | 15 | 16 | Hossein Amidi 17 | (C) April 2002 18 | 19 | *********************************************************/ 20 | 21 | // DEFINES 22 | `timescale 1ns / 10ps 23 | 24 | module cmd_detector(// Input 25 | reset, 26 | clk0, 27 | nop, 28 | ref_req, 29 | refresh, 30 | reada, 31 | writea, 32 | preacharge, 33 | load_mod, 34 | ref_dur, 35 | // Output 36 | do_nop, 37 | do_reada, 38 | do_writea, 39 | do_writea1, 40 | do_refresh, 41 | do_preacharge, 42 | do_load_mod, 43 | rw_flag 44 | ); 45 | 46 | 47 | // Parameter 48 | `include "parameter.v" 49 | 50 | // Input 51 | input reset; 52 | input clk0; 53 | input nop; 54 | input ref_req; 55 | input refresh; 56 | input reada; 57 | input writea; 58 | input preacharge; 59 | input load_mod; 60 | input [ref_dur_size - 1 : 0]ref_dur; 61 | 62 | // Output 63 | output do_nop; 64 | output do_reada; 65 | output do_writea; 66 | output do_writea1; 67 | output do_refresh; 68 | output do_preacharge; 69 | output do_load_mod; 70 | output rw_flag; 71 | 72 | // Internal wire and reg signals 73 | wire reset; 74 | wire clk0; 75 | wire nop; 76 | wire ref_req; 77 | wire refresh; 78 | wire reada; 79 | wire writea; 80 | wire preacharge; 81 | wire load_mod; 82 | wire [ref_dur_size - 1 : 0]ref_dur; 83 | 84 | reg do_nop; 85 | reg do_reada; 86 | reg do_writea; 87 | reg do_writea1; 88 | reg do_refresh; 89 | reg do_preacharge; 90 | reg do_load_mod; 91 | reg command_done; 92 | reg [7:0]command_delay; 93 | reg rw_flag; 94 | reg [3:0]rp_shift; 95 | reg rp_done; 96 | 97 | // Assignment 98 | 99 | 100 | // This always block monitors the individual command lines and issues a command 101 | // to the next stage if there currently another command already running. 102 | // 103 | always @(posedge reset or posedge clk0) 104 | begin 105 | if (reset == 1'b1) 106 | begin 107 | do_nop <= 0; 108 | do_reada <= 0; 109 | do_writea <= 0; 110 | do_refresh <= 0; 111 | do_preacharge <= 0; 112 | do_load_mod <= 0; 113 | command_done <= 0; 114 | command_delay <= 8'b0000_0000; 115 | rw_flag <= 0; 116 | rp_shift <= 0; 117 | rp_done <= 0; 118 | end 119 | 120 | else 121 | begin 122 | 123 | // Issue the appropriate command if the sdram is not currently busy 124 | if ((nop == 1) & (command_done == 0) & (do_nop == 0)) // refresh 125 | do_nop <= 1; 126 | else 127 | do_nop <= 0; 128 | 129 | if ((ref_req == 1 | refresh == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0 // refresh 130 | & do_reada == 0 & do_writea == 0) 131 | do_refresh <= 1; 132 | else 133 | do_refresh <= 0; 134 | 135 | if ((reada == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (ref_req == 0)) // reada 136 | do_reada <= 1; 137 | else 138 | do_reada <= 0; 139 | 140 | if ((writea == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (ref_req == 0)) // writea 141 | begin 142 | do_writea <= 1; 143 | do_writea1 <= 1; 144 | end 145 | else 146 | begin 147 | do_writea <= 0; 148 | do_writea1 <= 0; 149 | end 150 | if ((preacharge == 1) & (command_done == 0) & (do_preacharge == 0)) // preacharge 151 | do_preacharge <= 1; 152 | else 153 | do_preacharge <= 0; 154 | 155 | if ((load_mod == 1) & (command_done == 0) & (do_load_mod == 0)) // LOADMODE 156 | do_load_mod <= 1; 157 | else 158 | do_load_mod <= 0; 159 | 160 | // set command_delay shift register and command_done flag 161 | // The command delay shift register is a timer that is used to ensure that 162 | // the SDRAM devices have had sufficient time to finish the last command. 163 | 164 | if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_preacharge == 1) 165 | | (do_load_mod)) 166 | begin 167 | command_delay <= 8'b11111111; 168 | command_done <= 1; 169 | rw_flag <= do_reada; 170 | 171 | end 172 | 173 | else 174 | begin 175 | command_done <= command_delay[0]; // the command_delay shift operation 176 | command_delay[6:0] <= command_delay[7:1]; 177 | command_delay[7] <= 0; 178 | end 179 | 180 | 181 | // start additional timer that is used for the refresh, writea, reada commands 182 | if (command_delay[0] == 0 & command_done == 1) 183 | begin 184 | // rp_shift <= 4'b1111; 185 | rp_shift <= ref_dur; 186 | rp_done <= 1; 187 | end 188 | else 189 | begin 190 | rp_done <= rp_shift[0]; 191 | rp_shift[2:0] <= rp_shift[3:1]; 192 | rp_shift[3] <= 0; 193 | end 194 | end 195 | end 196 | 197 | 198 | 199 | 200 | endmodule 201 | -------------------------------------------------------------------------------- /Verilog/cmd_generator.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level SDRAM Command Genrator 3 | 4 | FILE NAME: cmd_generator.v 5 | VERSION: 1.0 6 | DATE: April 28th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of SDRAM Controller ASIC verilog 12 | code. It will generate the SDRAM control signals. 13 | 14 | 15 | Hossein Amidi 16 | (C) April 2002 17 | 18 | *********************************************************/ 19 | 20 | // DEFINES 21 | `timescale 1ns / 10ps 22 | 23 | module cmd_generator(// Input 24 | reset, 25 | clk0, 26 | do_reada, 27 | do_writea, 28 | do_preacharge, 29 | do_rw, 30 | rowaddr, 31 | coladdr, 32 | bankaddr, 33 | page_mod, 34 | do_load_mod, 35 | do_refresh, 36 | caddr, 37 | do_nop, 38 | rw_flag, 39 | oe4, 40 | // Output 41 | sadd, 42 | ba, 43 | cs, 44 | ras, 45 | cas, 46 | we, 47 | cke 48 | ); 49 | 50 | 51 | // Parameter 52 | `include "parameter.v" 53 | 54 | // Input 55 | input reset; 56 | input clk0; 57 | input do_reada; 58 | input do_writea; 59 | input do_preacharge; 60 | input do_rw; 61 | input [row_size - 1:0] rowaddr; 62 | input [col_size - 1:0] coladdr; 63 | input [bank_size - 1:0] bankaddr; 64 | input page_mod; 65 | input do_load_mod; 66 | input do_refresh; 67 | input [padd_size - 1 : 0]caddr; 68 | input do_nop; 69 | input rw_flag; 70 | input oe4; 71 | 72 | // Output 73 | output [add_size - 1 : 0]sadd; 74 | output [ba_size - 1 : 0]ba; 75 | output [cs_size - 1 : 0]cs; 76 | output ras; 77 | output cas; 78 | output we; 79 | output cke; 80 | 81 | 82 | // Internal wire and reg signals 83 | wire reset; 84 | wire clk0; 85 | wire do_reada; 86 | wire do_writea; 87 | wire do_preacharge; 88 | wire do_rw; 89 | wire [row_size - 1:0] rowaddr; 90 | wire [col_size - 1:0] coladdr; 91 | wire [bank_size - 1:0] bankaddr; 92 | wire page_mod; 93 | wire do_load_mod; 94 | wire do_refresh; 95 | wire [padd_size - 1 : 0]caddr; 96 | wire do_nop; 97 | wire rw_flag; 98 | wire oe4; 99 | 100 | reg [add_size - 1 : 0]sadd; 101 | reg [ba_size - 1 : 0]ba; 102 | reg [cs_size - 1 : 0]cs; 103 | reg ras; 104 | reg cas; 105 | reg we; 106 | reg cke; 107 | 108 | 109 | // Assignment 110 | 111 | 112 | 113 | // This always block generates the address, cs, cke, and command signals(ras,cas,wen) 114 | // 115 | always @(posedge reset or posedge clk0) 116 | begin 117 | if (reset == 1'b1) begin 118 | sadd <= 0; 119 | ba <= 0; 120 | cs <= 1; 121 | ras <= 1; 122 | cas <= 1; 123 | we <= 1; 124 | cke <= 0; 125 | end 126 | else begin 127 | cke <= 1; 128 | 129 | // Generate sadd 130 | 131 | if (do_writea == 1 | do_reada == 1) // ACTIVATE command is being issued, so present the row address 132 | sadd <= rowaddr; 133 | else if ((do_rw == 1) | (do_preacharge == 1)) 134 | sadd[10] <= !page_mod; // set sadd[10] for autopreacharge read/write or for a preacharge all command 135 | else // don't set it if the controller is in page mode. 136 | sadd <= coladdr; // else alway present column address 137 | if (do_preacharge == 1 | do_load_mod == 1) 138 | ba <= 0; // Set ba=0 if performing a preacharge or load_mod command 139 | else 140 | ba <= bankaddr[1:0]; // else set it with the appropriate address bits 141 | 142 | if (do_refresh == 1 | do_preacharge == 1 | do_load_mod == 1) 143 | cs <= 0; // Select both chip selects if performing 144 | else // refresh, preacharge(all) or load_mod 145 | begin 146 | cs[0] <= caddr[padd_size - 1]; // else set the chip selects based off of the 147 | cs[1] <= ~caddr[padd_size - 1]; // msb address bit 148 | end 149 | 150 | 151 | //Generate the appropriate logic levels on ras, cas, and we 152 | //depending on the issued command. 153 | // 154 | if (do_nop == 1) begin // No Operation: RAS=1, CAS=1, WE=1 155 | ras <= 1; 156 | cas <= 1; 157 | we <= 1; 158 | end 159 | else if (do_refresh == 1) begin // refresh: S=00, RAS=0, CAS=0, WE=1 160 | ras <= 0; 161 | cas <= 0; 162 | we <= 1; 163 | end 164 | else if ((do_preacharge == 1) & ((oe4 == 1) | (rw_flag == 1))) begin // burst terminate if write is active 165 | ras <= 1; 166 | cas <= 1; 167 | we <= 0; 168 | end 169 | else if (do_preacharge == 1) begin // preacharge All: S=00, RAS=0, CAS=1, WE=0 170 | ras <= 0; 171 | cas <= 1; 172 | we <= 0; 173 | end 174 | else if (do_load_mod == 1) begin // Mode Write: S=00, RAS=0, CAS=0, WE=0 175 | ras <= 0; 176 | cas <= 0; 177 | we <= 0; 178 | end 179 | else if (do_reada == 1 | do_writea == 1) begin // Activate: S=01 or 10, RAS=0, CAS=1, WE=1 180 | ras <= 0; 181 | cas <= 1; 182 | we <= 1; 183 | end 184 | else if (do_rw == 1) begin // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1 185 | ras <= 1; 186 | cas <= 0; 187 | we <= rw_flag; 188 | end 189 | else begin // No Operation: RAS=1, CAS=1, WE=1 190 | ras <= 1; 191 | cas <= 1; 192 | we <= 1; 193 | end 194 | end 195 | end 196 | 197 | 198 | 199 | endmodule 200 | -------------------------------------------------------------------------------- /Machine_Language/program.txt: -------------------------------------------------------------------------------- 1 | 0000_0000_0000_0000_0000_0000_0000_0111 //000 00 000007 LDA acc <- (7) start testing the dma Registers 2 | 0000_0001_0000_1000_0000_0000_0000_0001 //001 01 080001 STO (80001) <- acc 3 | 0000_0000_0000_0000_0000_0000_0000_1000 //002 00 000008 LDA acc <- (8) 4 | 0000_0001_0000_1000_0000_0000_0000_0010 //003 01 080002 STO (80002) <- acc 5 | 0000_0000_0000_0000_0000_0000_0000_1001 //004 00 000009 LDA acc <- (9) 6 | 0000_0001_0000_1000_0000_0000_0000_0011 //005 01 080003 STO (80003) <- acc 7 | 0000_0100_0000_0000_0000_0000_0000_1010 //006 04 00000a JMP (00A) 8 | 0000_0000_0000_0000_0000_0000_0001_0000 //007 Value is 10 9 | 0000_0000_0000_0000_0000_0000_0001_0001 //008 Value is 11 10 | 0000_0000_0000_0000_0000_0000_0001_0010 //009 Value is 12 11 | 0000_0000_0000_1000_0000_0000_0000_0001 //00a 01 080001 LDA acc <- (80001) 12 | 0000_0000_0000_1000_0000_0000_0000_0010 //00b 01 080002 LDA acc <- (80002) 13 | 0000_0000_0000_1000_0000_0000_0000_0011 //00c 01 080003 LDA acc <- (80003) end testing the dma Registers 14 | 0000_0000_0000_0000_0000_0000_0001_0100 //00d 00 000014 LDA acc <- (14) start testing the Flash Registers 15 | 0000_0001_0000_1000_0000_0000_0000_1000 //00e 01 080008 STO (80008) <- acc 16 | 0000_0000_0000_0000_0000_0000_0001_0101 //00f 00 000015 LDA acc <- (15) 17 | 0000_0001_0000_1000_0000_0000_0000_1001 //010 01 080009 STO (80009) <- acc 18 | 0000_0000_0000_0000_0000_0000_0001_0110 //011 00 000016 LDA acc <- (16) 19 | 0000_0001_0000_1000_0000_0000_0000_1010 //012 01 08000a STO (8000a) <- acc 20 | 0000_0100_0000_0000_0000_0000_0001_0111 //013 04 000017 JMP (017) 21 | 0000_0000_0000_0000_0000_0000_0001_0011 //014 Value is 13 22 | 0000_0000_0000_0000_0000_0000_0001_0100 //015 Value is 14 23 | 0000_0000_0000_0000_0000_0000_0001_0101 //016 Value is 15 24 | 0000_0000_0000_1000_0000_0000_0000_1000 //017 01 080008 LDA acc <- (80008) 25 | 0000_0000_0000_1000_0000_0000_0000_1001 //018 01 080009 LDA acc <- (80009) 26 | 0000_0000_0000_1000_0000_0000_0000_1010 //019 01 08000a LDA acc <- (8000a) end testing the Flash Registers 27 | 0000_0000_0000_0000_0000_0000_0010_0001 //01a 00 000021 LDA acc <- (21) start testing the D-Cache Registers 28 | 0000_0001_0000_1000_0000_0000_0001_0000 //01b 01 080010 STO (80010) <- acc 29 | 0000_0000_0000_0000_0000_0000_0010_0010 //01c 00 000022 LDA acc <- (22) 30 | 0000_0001_0000_1000_0000_0000_0001_0001 //01d 01 080011 STO (80011) <- acc 31 | 0000_0000_0000_0000_0000_0000_0010_0011 //01e 00 000023 LDA acc <- (23) 32 | 0000_0001_0000_1000_0000_0000_0001_0010 //01f 01 080012 STO (80012) <- acc 33 | 0000_0100_0000_0000_0000_0000_0010_0100 //020 04 000024 JMP (024) 34 | 0000_0000_0000_0000_0000_0000_0001_0110 //021 Value is 16 35 | 0000_0000_0000_0000_0000_0000_0001_0111 //022 Value is 17 36 | 0000_0000_0000_0000_0000_0000_0001_1000 //023 Value is 18 37 | 0000_0000_0000_1000_0000_0000_0001_0000 //024 01 080010 LDA acc <- (80010) 38 | 0000_0000_0000_1000_0000_0000_0001_0001 //025 01 080011 LDA acc <- (80011) 39 | 0000_0000_0000_1000_0000_0000_0001_0010 //026 01 080012 LDA acc <- (80012) end testing the D-Cache Registers 40 | 0000_0000_0000_0000_0000_0000_0010_1110 //027 00 00002e LDA acc <- (2e) start testing the i-Cache Registers 41 | 0000_0001_0000_1000_0000_0000_0001_1001 //028 01 080019 STO (80019) <- acc 42 | 0000_0000_0000_0000_0000_0000_0010_1111 //029 00 00002f LDA acc <- (2f) 43 | 0000_0001_0000_1000_0000_0000_0001_1010 //02a 01 08001A STO (8001A) <- acc 44 | 0000_0000_0000_0000_0000_0000_0011_0000 //02b 00 000030 LDA acc <- (30) 45 | 0000_0001_0000_1000_0000_0000_0001_1011 //02c 01 08001B STO (8001B) <- acc 46 | 0000_0100_0000_0000_0000_0000_0011_0001 //02d 04 000031 JMP (031) 47 | 0000_0000_0000_0000_0000_0000_0001_1001 //02e Value is 19 48 | 0000_0000_0000_0000_0000_0000_0001_1010 //02f Value is 1A 49 | 0000_0000_0000_0000_0000_0000_0001_1011 //030 Value is 1B 50 | 0000_0000_0000_1000_0000_0000_0001_1001 //031 01 080019 LDA acc <- (80019) 51 | 0000_0000_0000_1000_0000_0000_0001_1010 //032 01 08001A LDA acc <- (8001A) 52 | 0000_0000_0000_1000_0000_0000_0001_1011 //033 01 08001B LDA acc <- (8001B) end testing the i-Cache Registers 53 | 0000_0000_0000_0000_0000_0000_0011_1001 //034 00 000039 LDA acc <- (39) start testing the Timer Registers 54 | 0000_0001_0000_1000_0000_0000_0010_0001 //035 01 080021 STO (80021) <- acc 55 | 0000_0000_0000_0000_0000_0000_0011_1010 //036 00 00003a LDA acc <- (3a) 56 | 0000_0001_0000_1000_0000_0000_0010_0010 //037 01 080022 STO (80022) <- acc 57 | 0000_0100_0000_0000_0000_0000_0011_1011 //038 04 00003b JMP (03b) 58 | 0000_0000_0000_0000_0000_0000_0001_1100 //039 Value is 1C 59 | 0000_0000_0000_0000_0000_0000_0001_1101 //03a Value is 1D 60 | 0000_0000_0000_1000_0000_0000_0010_0001 //03b 01 080021 LDA acc <- (80021) 61 | 0000_0000_0000_1000_0000_0000_0010_0010 //03c 01 080022 LDA acc <- (80022) end testing the Timer Registers 62 | 0000_0000_0000_0000_0000_0000_0100_0010 //03d 00 000042 LDA acc <- (42) start testing the UART Registers 63 | 0000_0001_0000_1000_0000_0000_0010_1010 //03e 01 08002A STO (8002A) <- acc 64 | 0000_0000_0000_0000_0000_0000_0100_0011 //03f 00 000043 LDA acc <- (43) 65 | 0000_0001_0000_1000_0000_0000_0010_1011 //040 01 08002B STO (8002B) <- acc 66 | 0000_0100_0000_0000_0000_0000_0100_0100 //041 04 000044 JMP (044) 67 | 0000_0000_0000_0000_0000_0000_0001_1110 //042 Value is 1E 68 | 0000_0000_0000_0000_0000_0000_0001_1111 //043 Value is 1F 69 | 0000_0000_0000_1000_0000_0000_0010_1010 //044 01 08002A LDA acc <- (8002A) 70 | 0000_0000_0000_1000_0000_0000_0010_1011 //045 01 08002B LDA acc <- (8002B) end testing the UART Registers 71 | 0000_0111_0000_0000_0000_0000_0000_0000 //046 07 000000 STP STOP 72 | 73 | /********************************************************* 74 | * This program developed by Hossein Amidi (C) May 2002 * 75 | * It's the Machine Language with Assembly Comment on the* 76 | * side for users to trace each instructions back to the * 77 | * RISC CPU. * 78 | * This CPU Architecture uses a 32-bit Instructions with * 79 | * 256 Opcode (2 ^ 8-bit) and 16MB code and data acce- * 80 | * sibility ( 2 ^ 24-bit). Entire machine Code and data * 81 | * will be stored in the memory space. * 82 | * All the internal Registers for : * 83 | * 1) DMA * 84 | * 2) Data Cache * 85 | * 3) Instruction Cache * 86 | * 4) UART * 87 | * 5) Timer * 88 | * 6) Flash Controller * 89 | * 7) SDRAM Controller * 90 | * will be accessed using a memory map methodology. * 91 | * * 92 | * This program will test internal register for all the * 93 | * above mentioned device's internal registers by doing * 94 | * individual write / read to memory map locations. * 95 | *********************************************************/ -------------------------------------------------------------------------------- /Verilog/uart.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level UART Device 3 | 4 | FILE NAME: uart.v 5 | VERSION: 1.0 6 | DATE: May 14th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of UART verilog code. 12 | 13 | It will instantiate the following blocks in the ASIC: 14 | 15 | 16 | Hossein Amidi 17 | (C) April 2002 18 | 19 | *********************************************************/ 20 | 21 | // DEFINES 22 | `timescale 1ns / 10ps 23 | 24 | // TOP MODULE 25 | module uart(// Inputs 26 | reset, 27 | clk0, 28 | uart_addr, 29 | uart_host_addr, 30 | uart_host_cmd, 31 | uart_cmd, 32 | uart_host_datain, 33 | uart_cs, 34 | uart_rd, 35 | uart_wr, 36 | ser_rxd, 37 | uart_datain, 38 | // Outputs 39 | ser_txd, 40 | uart_host_dataout, 41 | uart_dataout 42 | ); 43 | 44 | 45 | // Parameter 46 | `include "parameter.v" 47 | 48 | // Inputs 49 | input reset; 50 | input clk0; 51 | input [padd_size - 1 : 0]uart_addr; 52 | input [padd_size - 1 : 0]uart_host_addr; 53 | input [cmd_size - 1 : 0]uart_host_cmd; 54 | input [cmd_size - 1 : 0]uart_cmd; 55 | input [data_size - 1 : 0]uart_host_datain; 56 | input uart_cs; 57 | input uart_rd; 58 | input uart_wr; 59 | input ser_rxd; 60 | input [Byte_size - 1 : 0]uart_datain; 61 | 62 | // Outputs 63 | output ser_txd; 64 | output [data_size - 1 : 0]uart_host_dataout; 65 | output [Byte_size - 1 : 0]uart_dataout; 66 | 67 | 68 | // Signal Declarations 69 | wire reset; 70 | wire clk0; 71 | wire [padd_size - 1 : 0]uart_addr; 72 | wire [padd_size - 1 : 0]uart_host_addr; 73 | wire [cmd_size - 1 : 0]uart_host_cmd; 74 | wire [cmd_size - 1 : 0]uart_cmd; 75 | wire [data_size - 1 : 0]uart_host_datain; 76 | wire uart_cs; 77 | wire uart_rd; 78 | wire uart_wr; 79 | wire ser_rxd; 80 | wire [Byte_size - 1 : 0]uart_datain; 81 | 82 | reg ser_txd; 83 | reg [data_size - 1 : 0]uart_host_dataout; 84 | wire [Byte_size - 1 : 0]uart_dataout; 85 | reg [Byte_size - 1 : 0]ruart_dataout; 86 | 87 | // Internal Registers 88 | reg [Byte_size - 1 : 0]uart_reg_dataout; 89 | 90 | 91 | reg [Byte_size -1 : 0]shift_reg_in; 92 | reg [Byte_size -1 : 0]shift_reg_out; 93 | reg [uart_cnt_size - 1 : 0]serin_cnt; 94 | reg [uart_cnt_size - 1 : 0]serout_cnt; 95 | 96 | reg byte_in; 97 | reg byte_out; 98 | 99 | // Assignment statments 100 | assign uart_dataout = ruart_dataout; 101 | 102 | /***************** Internal Register of Uart configuration *******************/ 103 | reg [uart_reg_width - 1 : 0] uart_register [uart_reg_depth - 1 : 0]; 104 | 105 | 106 | // Circuit for internal Register 107 | always @(posedge reset or posedge clk0) 108 | begin 109 | if(reset == 1'b1) 110 | begin 111 | uart_host_dataout <= 32'h0; 112 | uart_register[0] <= 32'h0; 113 | uart_register[1] <= 32'h0; 114 | uart_register[2] <= 32'h0; 115 | uart_register[3] <= 32'h0; 116 | uart_register[4] <= 32'h0; 117 | uart_register[5] <= 32'h0; 118 | uart_register[6] <= 32'h0; 119 | uart_register[7] <= 32'h0; 120 | end 121 | else 122 | begin 123 | if(uart_host_cmd == 3'b010) 124 | begin 125 | case(uart_host_addr) 126 | 24'h080024: uart_register[0] <= uart_host_datain; 127 | 24'h080025: uart_register[1] <= uart_host_datain; 128 | 24'h080026: uart_register[2] <= uart_host_datain; 129 | 24'h080027: uart_register[3] <= uart_host_datain; 130 | 24'h080028: uart_register[4] <= uart_host_datain; 131 | 24'h080029: uart_register[5] <= uart_host_datain; 132 | 24'h08002A: uart_register[6] <= uart_host_datain; 133 | 24'h08002B: uart_register[7] <= uart_host_datain; 134 | endcase 135 | end 136 | else 137 | if(uart_host_cmd == 3'b001) 138 | begin 139 | case(uart_host_addr) 140 | 24'h080024: uart_host_dataout <= uart_register[0]; 141 | 24'h080025: uart_host_dataout <= uart_register[1]; 142 | 24'h080026: uart_host_dataout <= uart_register[2]; 143 | 24'h080027: uart_host_dataout <= uart_register[3]; 144 | 24'h080028: uart_host_dataout <= uart_register[4]; 145 | 24'h080029: uart_host_dataout <= uart_register[5]; 146 | 24'h08002A: uart_host_dataout <= uart_register[6]; 147 | 24'h08002B: uart_host_dataout <= uart_register[7]; 148 | endcase 149 | end 150 | end 151 | 152 | end 153 | 154 | 155 | // Circuit for reciever side 156 | always @(posedge reset or posedge clk0) 157 | begin 158 | if(reset == 1'b1) 159 | begin 160 | shift_reg_in <= 8'h0; 161 | end 162 | else 163 | if((uart_wr == 1'b1) && (uart_rd == 1'b0) && (byte_in == 1'b0)) 164 | begin 165 | shift_reg_in[7] <= shift_reg_in[6]; 166 | shift_reg_in[6] <= shift_reg_in[5]; 167 | shift_reg_in[5] <= shift_reg_in[4]; 168 | shift_reg_in[4] <= shift_reg_in[3]; 169 | shift_reg_in[3] <= shift_reg_in[2]; 170 | shift_reg_in[2] <= shift_reg_in[1]; 171 | shift_reg_in[1] <= shift_reg_in[0]; 172 | shift_reg_in[0] <= ser_rxd; 173 | end 174 | else 175 | shift_reg_in <= shift_reg_in; 176 | end 177 | 178 | 179 | always @(posedge reset or posedge clk0) 180 | begin 181 | if(reset == 1'b1) 182 | ruart_dataout <= 8'h0; 183 | else 184 | if((uart_wr == 1'b1) && (uart_rd == 1'b0) && (byte_in == 1'b1)) 185 | begin 186 | ruart_dataout[0] <= shift_reg_in[0]; 187 | ruart_dataout[1] <= shift_reg_in[1]; 188 | ruart_dataout[2] <= shift_reg_in[2]; 189 | ruart_dataout[3] <= shift_reg_in[3]; 190 | ruart_dataout[4] <= shift_reg_in[4]; 191 | ruart_dataout[5] <= shift_reg_in[5]; 192 | ruart_dataout[6] <= shift_reg_in[6]; 193 | ruart_dataout[7] <= shift_reg_in[7]; 194 | end 195 | end 196 | 197 | 198 | // Circuit for transmitter side 199 | always @(posedge reset or posedge clk0) 200 | begin 201 | if(reset == 1'b1) 202 | begin 203 | shift_reg_out <= 8'h0; 204 | ser_txd <= 1'b0; 205 | end 206 | else 207 | if((uart_wr == 1'b0) && (uart_rd == 1'b1) && (byte_out == 1'b0)) 208 | begin 209 | ser_txd <= shift_reg_out[7]; 210 | shift_reg_out[7] <= shift_reg_out[6]; 211 | shift_reg_out[6] <= shift_reg_out[5]; 212 | shift_reg_out[5] <= shift_reg_out[4]; 213 | shift_reg_out[4] <= shift_reg_out[3]; 214 | shift_reg_out[3] <= shift_reg_out[2]; 215 | shift_reg_out[2] <= shift_reg_out[1]; 216 | shift_reg_out[1] <= shift_reg_out[0]; 217 | end 218 | else 219 | if((uart_wr == 1'b0) && (uart_rd == 1'b1) && (byte_out == 1'b1)) 220 | shift_reg_out <= uart_datain; 221 | end 222 | 223 | 224 | 225 | // Serial Input Byte Counter 226 | always @(posedge reset or posedge clk0) 227 | begin 228 | if(reset == 1'b1) 229 | begin 230 | serin_cnt <= 3'b000; 231 | byte_in <= 1'b0; 232 | end 233 | else 234 | if((uart_cs == 1'b1) && (uart_wr == 1'b1) && (uart_rd == 1'b0)) 235 | serin_cnt <= serin_cnt + 1; 236 | else 237 | if(serin_cnt == 3'b111) 238 | byte_in <= 1'b1; 239 | else 240 | begin 241 | byte_in <= 1'b0; 242 | serin_cnt <= serin_cnt; 243 | end 244 | end 245 | 246 | 247 | // Serial Output Byte Counter 248 | always @(posedge reset or posedge clk0) 249 | begin 250 | if(reset == 1'b1) 251 | begin 252 | serout_cnt <= 3'b000; 253 | byte_out <= 1'b0; 254 | end 255 | else 256 | if((uart_cs == 1'b1) && (uart_wr == 1'b0) && (uart_rd == 1'b1)) 257 | serout_cnt <= serout_cnt + 1; 258 | else 259 | if(serout_cnt == 3'b111) 260 | byte_out <= 1'b1; 261 | else 262 | begin 263 | byte_out <= 1'b0; 264 | serout_cnt <= serout_cnt; 265 | end 266 | end 267 | 268 | endmodule 269 | -------------------------------------------------------------------------------- /Verilog/dma_cntrl.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Direct Memory Access Controller 3 | 4 | FILE NAME: dma_cntrl.v 5 | VERSION: 1.0 6 | DATE: May 7th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of DMA Controller verilog code. 12 | 13 | It will instantiate the following blocks in the ASIC: 14 | 15 | 1) DMA FIFO 16 | 2) DMA Internal Registers 17 | 18 | Hossein Amidi 19 | (C) April 2002 20 | 21 | *********************************************************/ 22 | 23 | // DEFINES 24 | `timescale 1ns / 10ps 25 | 26 | // TOP MODULE 27 | module dma_cntrl( // Inputs 28 | reset, 29 | clk0, 30 | dma_host_addr, 31 | dma_host_cmd, 32 | dma_host_datain, 33 | dma_bus_grant, 34 | dma_rd_datain, 35 | dma_wr_datain, 36 | // Output 37 | dma_host_dataout, 38 | dma_irq, 39 | dma_bus_req, 40 | dma_rd_addr, 41 | dma_wr_addr, 42 | dma_wr_dataout, 43 | dma_rd_cmd, 44 | dma_busy, 45 | uart_cs, 46 | uart_rd, 47 | uart_wr, 48 | dma_rd_dataout 49 | ); 50 | 51 | // Parameter 52 | `include "parameter.v" 53 | 54 | // Inputs 55 | input reset; 56 | input clk0; 57 | input [padd_size - 1 : 0]dma_host_addr; 58 | input [cmd_size - 1 : 0]dma_host_cmd; 59 | input [data_size - 1 : 0]dma_host_datain; 60 | input dma_bus_grant; 61 | input [fifo_size - 1 : 0]dma_rd_datain; 62 | input [fifo_size - 1 : 0]dma_wr_datain; 63 | 64 | // Outputs 65 | output [data_size - 1 : 0]dma_host_dataout; 66 | output dma_irq; 67 | output dma_bus_req; 68 | output [padd_size - 1 : 0]dma_rd_addr; 69 | output [padd_size - 1 : 0]dma_wr_addr; 70 | output [fifo_size - 1 : 0]dma_wr_dataout; 71 | output [cmd_size - 1 : 0]dma_rd_cmd; 72 | output dma_busy; 73 | output uart_cs; 74 | output uart_rd; 75 | output uart_wr; 76 | output [fifo_size - 1 : 0]dma_rd_dataout; 77 | 78 | // Signal Declarations 79 | wire reset; 80 | wire clk0; 81 | wire [padd_size - 1 : 0]dma_host_addr; 82 | wire [cmd_size - 1 : 0]dma_host_cmd; 83 | wire [data_size - 1 : 0]dma_host_datain; 84 | wire dma_bus_grant; 85 | wire [fifo_size - 1 : 0]dma_rd_datain; 86 | wire [fifo_size - 1 : 0]dma_wr_datain; 87 | 88 | wire [data_size - 1 : 0]dma_host_dataout; 89 | wire dma_irq; 90 | wire dma_bus_req; 91 | reg [padd_size - 1 : 0]dma_rd_addr; 92 | reg [padd_size - 1 : 0]dma_wr_addr; 93 | reg [fifo_size - 1 : 0]dma_wr_dataout; 94 | reg [cmd_size - 1 : 0]dma_rd_cmd; 95 | reg [fifo_size - 1 : 0]dma_rd_dataout; 96 | wire [fifo_size - 1 : 0]wdma_rd_dataout; 97 | wire dma_busy; 98 | 99 | reg uart_cs; 100 | reg uart_rd; 101 | reg uart_wr; 102 | 103 | // Internal wire and reg Signals 104 | wire done; 105 | wire busy; 106 | wire reop; 107 | wire weop; 108 | wire len; 109 | 110 | wire byte; 111 | wire hw; 112 | wire word; 113 | wire go; 114 | wire i_en; 115 | wire reen; 116 | wire ween; 117 | wire leen; 118 | wire rcon; 119 | wire wcon; 120 | 121 | reg fifo_rd; 122 | reg fifo_wr; 123 | 124 | reg [dma_fifo_depth - 1 : 0]dma_wr_addr_cnt; 125 | reg [dma_fifo_depth - 1 : 0]dma_rd_addr_cnt; 126 | 127 | wire [dma_fifo_depth - 1 : 0]wdma_wr_addr_cnt; 128 | wire [dma_fifo_depth - 1 : 0]wdma_rd_addr_cnt; 129 | 130 | 131 | wire wr_inc1; 132 | wire wr_inc2; 133 | wire wr_inc4; 134 | 135 | wire rd_inc1; 136 | wire rd_inc2; 137 | wire rd_inc4; 138 | 139 | wire fifo_wr_enb; 140 | wire fifo_rd_enb; 141 | 142 | wire [fifo_size - 1 : 0]fifo_in_data; 143 | wire [fifo_size - 1 : 0]fifo_out_data; 144 | 145 | reg fifo_sel_in; 146 | reg fifo_sel_out; 147 | 148 | 149 | // Assignment statments 150 | assign dma_irq = done; 151 | assign dma_bus_req = go; 152 | assign dma_busy = busy; 153 | assign wdma_wr_addr_cnt = dma_wr_addr_cnt; 154 | assign wdma_rd_addr_cnt = dma_rd_addr_cnt; 155 | 156 | // Muxing the fifo for bidirection functionality 157 | assign fifo_in_data = fifo_sel_in ? dma_wr_datain : dma_rd_datain; 158 | 159 | /********************************** FIFO Instantiation ******************************/ 160 | 161 | dma_fifo dma_fifo0 (// Input 162 | .clk(clk0), 163 | .sinit(reset), 164 | .din(fifo_in_data), 165 | .wr_en(fifo_wr), 166 | .rd_en(fifo_rd), 167 | // Output 168 | .dout(fifo_out_data), 169 | .full(), 170 | .empty() 171 | ); 172 | 173 | 174 | dma_internal_reg dma_internal_reg0(// Input 175 | .reset(reset), 176 | .clk0(clk0), 177 | .dma_host_cmd(dma_host_cmd), 178 | .dma_host_addr(dma_host_addr), 179 | .dma_host_datain(dma_host_datain), 180 | .dma_rd_addr_cnt(wdma_rd_addr_cnt), 181 | .dma_wr_addr_cnt(wdma_wr_addr_cnt), 182 | .fifo_rd(fifo_rd), 183 | .fifo_wr(fifo_wr), 184 | // Output 185 | .dma_host_dataout(dma_host_dataout), 186 | .done(done), 187 | .go(go), 188 | .busy(busy), 189 | .fifo_wr_enb(fifo_wr_enb), 190 | .fifo_rd_enb(fifo_rd_enb), 191 | .wr_inc1(wr_inc1), 192 | .wr_inc2(wr_inc2), 193 | .wr_inc4(wr_in4), 194 | .rd_inc1(rd_inc1), 195 | .rd_inc2(rd_inc2), 196 | .rd_inc4(rd_inc4) 197 | ); 198 | 199 | 200 | // Set the Demultiplexer for the FIFO output port 201 | always @(reset or fifo_sel_out or dma_bus_grant or fifo_out_data) 202 | begin 203 | if(reset == 1'b1) 204 | begin 205 | dma_rd_dataout <= 8'h0; 206 | dma_wr_dataout <= 8'h0; 207 | end 208 | else 209 | if((dma_bus_grant == 1'b1) && (fifo_sel_out == 1'b1)) 210 | dma_wr_dataout <= fifo_out_data; 211 | else 212 | if((dma_bus_grant == 1'b0) && (fifo_sel_out == 1'b0)) 213 | dma_rd_dataout <= fifo_out_data; 214 | end 215 | 216 | 217 | // Increment the DMA Write Slave Address 218 | always @(posedge reset or posedge clk0) 219 | begin 220 | if(reset == 1'b1) 221 | dma_wr_addr_cnt <= 32'h0; 222 | else 223 | if (wr_inc1 == 1'b1) 224 | dma_wr_addr_cnt <= dma_wr_addr_cnt + 1; 225 | else 226 | if (wr_inc2 == 1'b1) 227 | dma_wr_addr_cnt <= dma_wr_addr_cnt + 2; 228 | else 229 | if (wr_inc4 == 1'b1) 230 | dma_wr_addr_cnt <= dma_wr_addr_cnt + 4; 231 | else 232 | dma_wr_addr_cnt <= dma_wr_addr_cnt; 233 | end 234 | 235 | 236 | // Increment the DMA Read Slave Address 237 | always @(posedge reset or posedge clk0) 238 | begin 239 | if(reset == 1'b1) 240 | dma_rd_addr_cnt <= 32'h0; 241 | else 242 | if (rd_inc1 == 1'b1) 243 | dma_rd_addr_cnt <= dma_rd_addr_cnt + 1; 244 | else 245 | if (rd_inc2 == 1'b1) 246 | dma_rd_addr_cnt <= dma_rd_addr_cnt + 2; 247 | else 248 | if (rd_inc4 == 1'b1) 249 | dma_rd_addr_cnt <= dma_rd_addr_cnt + 4; 250 | else 251 | dma_rd_addr_cnt <= dma_rd_addr_cnt; 252 | end 253 | 254 | 255 | // Generating FIFO read and write enable signals 256 | always @(posedge reset or posedge clk0) 257 | begin 258 | if(reset == 1'b1) 259 | begin 260 | fifo_wr <= 1'b0; 261 | fifo_rd <= 1'b0; 262 | fifo_sel_in <= 1'b0; 263 | fifo_sel_out <= 1'b0; 264 | end 265 | else 266 | begin 267 | if((fifo_wr_enb == 1'b1) && (dma_bus_req == 1'b1)) 268 | begin 269 | fifo_sel_in <= 1'b1; 270 | fifo_wr <= 1'b1; 271 | end 272 | else 273 | if((fifo_wr_enb == 1'b1) && (dma_bus_req == 1'b0)) 274 | begin 275 | fifo_sel_in <= 1'b0; 276 | fifo_wr <= 1'b1; 277 | end 278 | else 279 | begin 280 | fifo_sel_in <= 1'b0; 281 | fifo_wr <= 1'b0; 282 | end 283 | 284 | if((fifo_rd_enb == 1'b1) && (dma_bus_req == 1'b1)) 285 | begin 286 | fifo_sel_out <= 1'b0; 287 | fifo_rd <= 1'b1; 288 | end 289 | else 290 | if((fifo_rd_enb == 1'b1) && (dma_bus_req == 1'b0)) 291 | begin 292 | fifo_sel_out <= 1'b1; 293 | fifo_rd <= 1'b1; 294 | end 295 | else 296 | begin 297 | fifo_sel_out <= 1'b0; 298 | fifo_rd <= 1'b0; 299 | end 300 | end 301 | end 302 | 303 | 304 | always @(posedge reset or posedge clk0) 305 | begin 306 | if(reset == 1'b1) 307 | begin 308 | dma_wr_addr <= 24'h0; 309 | dma_rd_addr <= 24'h0; 310 | dma_rd_cmd <= 3'h0; 311 | uart_cs <= 1'b0; 312 | uart_rd <= 1'b0; 313 | uart_wr <= 1'b0; 314 | end 315 | else 316 | begin 317 | dma_wr_addr <= dma_wr_addr_cnt; 318 | if(ween == 1'b1) 319 | begin 320 | uart_cs <= 1'b1; 321 | uart_wr <= 1'b1; 322 | dma_rd_cmd <= 3'b010; 323 | dma_wr_addr <= dma_wr_addr_cnt; 324 | end 325 | else 326 | if(reen == 1'b1) 327 | begin 328 | uart_cs <= 1'b1; 329 | uart_rd <= 1'b1; 330 | dma_rd_cmd <= 3'b001; 331 | dma_rd_addr <= dma_rd_addr_cnt; 332 | end 333 | end 334 | end 335 | 336 | endmodule 337 | -------------------------------------------------------------------------------- /Verilog/dma_internal_reg.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level DMA Internal Register Block 3 | 4 | FILE NAME: dma_internal_reg.v 5 | VERSION: 1.0 6 | DATE: May 20th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the sub level RTL code of DMA Controller Internal 12 | Register verilog code. 13 | 14 | It will instantiate the following blocks in the ASIC: 15 | 16 | 17 | Hossein Amidi 18 | (C) April 2002 19 | 20 | *********************************************************/ 21 | 22 | // DEFINES 23 | `timescale 1ns / 10ps 24 | 25 | // TOP MODULE 26 | module dma_internal_reg(// Inputs 27 | reset, 28 | clk0, 29 | dma_host_cmd, 30 | dma_host_addr, 31 | dma_host_datain, 32 | dma_wr_addr_cnt, 33 | dma_rd_addr_cnt, 34 | fifo_rd, 35 | fifo_wr, 36 | // Output 37 | dma_host_dataout, 38 | done, 39 | go, 40 | busy, 41 | fifo_wr_enb, 42 | fifo_rd_enb, 43 | wr_inc1, 44 | wr_inc2, 45 | wr_inc4, 46 | rd_inc1, 47 | rd_inc2, 48 | rd_inc4 49 | ); 50 | 51 | 52 | // Parameter 53 | `include "parameter.v" 54 | 55 | // Inputs 56 | input reset; 57 | input clk0; 58 | input [padd_size - 1 : 0]dma_host_addr; 59 | input [cmd_size - 1 : 0]dma_host_cmd; 60 | input [data_size - 1 : 0]dma_host_datain; 61 | input [dma_fifo_depth - 1 : 0]dma_wr_addr_cnt; 62 | input [dma_fifo_depth - 1 : 0]dma_rd_addr_cnt; 63 | input fifo_rd; 64 | input fifo_wr; 65 | 66 | 67 | // Outputs 68 | output [data_size - 1 : 0]dma_host_dataout; 69 | output done; 70 | output go; 71 | output busy; 72 | output fifo_wr_enb; 73 | output fifo_rd_enb; 74 | output wr_inc1; 75 | output wr_inc2; 76 | output wr_inc4; 77 | output rd_inc1; 78 | output rd_inc2; 79 | output rd_inc4; 80 | 81 | 82 | // Signal Declarations 83 | wire reset; 84 | wire clk0; 85 | wire [padd_size - 1 : 0]dma_host_addr; 86 | wire [cmd_size - 1 : 0]dma_host_cmd; 87 | wire [data_size - 1 : 0]dma_host_datain; 88 | wire [dma_fifo_depth - 1 : 0]dma_wr_addr_cnt; 89 | wire [dma_fifo_depth - 1 : 0]dma_rd_addr_cnt; 90 | wire fifo_rd; 91 | wire fifo_wr; 92 | 93 | 94 | reg [data_size - 1 : 0]dma_host_dataout; 95 | 96 | 97 | // Internal signals 98 | wire [dma_reg_width - 1 : 0]dma_register0; 99 | wire [dma_reg_width - 1 : 0]dma_register1; 100 | wire [dma_reg_width - 1 : 0]dma_register2; 101 | wire [dma_reg_width - 1 : 0]dma_register3; 102 | wire [dma_reg_width - 1 : 0]dma_register6; 103 | 104 | 105 | wire wr_inc1; 106 | wire wr_inc2; 107 | wire wr_inc4; 108 | 109 | wire rd_inc1; 110 | wire rd_inc2; 111 | wire rd_inc4; 112 | 113 | wire done; 114 | wire busy; 115 | wire reop; 116 | wire weop; 117 | wire len; 118 | 119 | wire byte; 120 | wire hw; 121 | wire word; 122 | wire go; 123 | wire i_en; 124 | wire reen; 125 | wire ween; 126 | wire leen; 127 | wire rcon; 128 | wire wcon; 129 | 130 | wire fifo_wr_enb; 131 | wire fifo_rd_enb; 132 | 133 | /***************** Internal Register of DMA configuration *******************/ 134 | reg [dma_reg_width - 1 : 0] dma_register [dma_reg_depth - 1 : 0]; 135 | 136 | // Assignment statments 137 | 138 | // Increment the write/read counter according to byte, half word or word mode 139 | assign wr_inc1 = (~(dma_register0 == 32'h0) & 140 | ~(dma_register2 == 32'h0) & 141 | (go == 1'b1) & 142 | (word == 1'b0) & 143 | (hw == 1'b0) & 144 | (byte == 1'b1)); 145 | 146 | assign wr_inc2 = (~(dma_register0 == 32'h0) & 147 | ~(dma_register2 == 32'h0) & 148 | (go == 1'b1) & 149 | (word == 1'b0) & 150 | (hw == 1'b1) & 151 | (byte == 1'b0)); 152 | 153 | assign wr_inc4 = (~(dma_register0 == 32'h0) & 154 | ~(dma_register2 == 32'h0) & 155 | (go == 1'b1) & 156 | (word == 1'b1) & 157 | (hw == 1'b0) & 158 | (byte == 1'b0)); 159 | 160 | 161 | assign rd_inc1 = (~(dma_register0 == 32'h0) & 162 | ~(dma_register1 == 32'h0) & 163 | (go == 1'b1) & 164 | (word == 1'b0) & 165 | (hw == 1'b0) & 166 | (byte == 1'b1)); 167 | 168 | assign rd_inc2 = (~(dma_register0 == 32'h0) & 169 | ~(dma_register1 == 32'h0) & 170 | (go == 1'b1) & 171 | (word == 1'b0) & 172 | (hw == 1'b1) & 173 | (byte == 1'b0)); 174 | 175 | assign rd_inc4 = (~(dma_register0 == 32'h0) & 176 | ~(dma_register1 == 32'h0) & 177 | (go == 1'b1) & 178 | (word == 1'b1) & 179 | (hw == 1'b0) & 180 | (byte == 1'b0)); 181 | 182 | 183 | assign fifo_wr_enb = (~(dma_register3 == 32'h0) & 184 | ~(dma_register2 == 32'h0) & 185 | (go == 1'b1)); 186 | 187 | 188 | assign fifo_rd_enb = (~(dma_register3 == 32'h0) & 189 | ~(dma_register1 == 32'h0) & 190 | (go == 1'b1)); 191 | 192 | assign dma_register0 = dma_register[0]; 193 | assign dma_register1 = dma_register[1]; 194 | assign dma_register2 = dma_register[2]; 195 | assign dma_register3 = dma_register[3]; 196 | assign dma_register6 = dma_register[6]; 197 | 198 | 199 | // Bitwise decoding of status register 200 | assign done = dma_register0[0] & 32'd1; 201 | assign busy = dma_register0[1] & 32'd1; 202 | assign reop = dma_register0[2] & 32'd1; 203 | assign weop = dma_register0[3] & 32'd1; 204 | assign len = dma_register0[4] & 32'd1; 205 | 206 | // Bitwise decoding of control register 207 | assign byte = dma_register6[0] & 32'd1; 208 | assign hw = dma_register6[1] & 32'd1; 209 | assign word = dma_register6[2] & 32'd1; 210 | assign go = dma_register6[3] & 32'd1; 211 | assign i_en = dma_register6[4] & 32'd1; 212 | assign reen = dma_register6[5] & 32'd1; 213 | assign ween = dma_register6[6] & 32'd1; 214 | assign leen = dma_register6[7] & 32'd1; 215 | assign rcon = dma_register6[8] & 32'd1; 216 | assign wcon = dma_register6[9] & 32'd1; 217 | 218 | 219 | // Access to internal register by CPU address and command signals (write/read) 220 | always @(posedge reset or posedge clk0) 221 | begin 222 | if(reset == 1'b1) 223 | begin 224 | dma_host_dataout <= 32'h0; 225 | dma_register[0] <= 32'h0; 226 | dma_register[1] <= 32'h0; 227 | dma_register[2] <= 32'h0; 228 | dma_register[3] <= 32'h0; 229 | dma_register[4] <= 32'h0; 230 | dma_register[5] <= 32'h0; 231 | dma_register[6] <= 32'h0; 232 | dma_register[7] <= 32'h0; 233 | end 234 | else 235 | begin 236 | if(dma_host_cmd == 3'b010) // Write from Host to DMA internal Registers 237 | begin 238 | case (dma_host_addr) 239 | 240 | 24'h080000: dma_register[0] <= dma_host_datain; // Status Register 241 | 24'h080001: dma_register[1] <= dma_host_datain; // Read Master Start Address 242 | 24'h080002: dma_register[2] <= dma_host_datain; // Write Master Start Address 243 | 24'h080003: dma_register[3] <= dma_host_datain; // Length in Bytes 244 | 24'h080004: dma_register[4] <= dma_host_datain; // Reserved 245 | 24'h080005: dma_register[5] <= dma_host_datain; // Reserved 246 | 24'h080006: dma_register[6] <= dma_host_datain; // Control 247 | 24'h080007: dma_register[7] <= dma_host_datain; // Reserved 248 | endcase 249 | end 250 | else 251 | if(dma_host_cmd == 3'b001) // Read from DMA internal Registers to Host 252 | begin 253 | case (dma_host_addr) 254 | 255 | 24'h080000: dma_host_dataout <= dma_register[0]; 256 | 24'h080001: dma_host_dataout <= dma_register[1]; 257 | 24'h080002: dma_host_dataout <= dma_register[2]; 258 | 24'h080003: dma_host_dataout <= dma_register[3]; 259 | 24'h080004: dma_host_dataout <= dma_register[4]; 260 | 24'h080005: dma_host_dataout <= dma_register[5]; 261 | 24'h080006: dma_host_dataout <= dma_register[6]; 262 | 24'h080007: dma_host_dataout <= dma_register[7]; 263 | endcase 264 | end 265 | 266 | if(((reop == 1'b1) || (weop == 1'b1) || (len == 32'h0)) && (i_en)) 267 | dma_register[0] <= dma_register[0] | 32'h1; // Set the done pin 268 | 269 | if(~(len == 32'h0)) 270 | dma_register[0] <= dma_register[0] | 32'h2; // Set the busy pin 271 | 272 | if((reen == 1'b1) && (len == 1'b1)) 273 | dma_register[0] <= dma_register[0] | 32'h4; // Set the reop pin 274 | 275 | if((ween == 1'b1) && (len == 1'b1)) 276 | dma_register[0] <= dma_register[0] | 32'h8; // Set the weop pin 277 | 278 | if((dma_register3 == dma_register2) || (dma_register3 == dma_register1)) 279 | dma_register[0] <= dma_register[0] | 32'hf; // Set the len pin 280 | 281 | if(fifo_rd == 1'b1) 282 | dma_register[3] <= dma_register[3] - dma_wr_addr_cnt; 283 | 284 | if(fifo_wr == 1'b1) 285 | dma_register[3] <= dma_register[3] - dma_rd_addr_cnt; 286 | 287 | end 288 | end 289 | 290 | endmodule 291 | -------------------------------------------------------------------------------- /Verilog/bus_arbiter.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level Bus Arbiter Block 3 | 4 | FILE NAME: bus_arbiter.v 5 | VERSION: 1.0 6 | DATE: May 7th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of Bus Arbiter verilog code. 12 | 13 | It will instantiate the following blocks in the ASIC: 14 | 15 | 16 | Hossein Amidi 17 | (C) April 2002 18 | 19 | *********************************************************/ 20 | 21 | // DEFINES 22 | `timescale 1ns / 10ps 23 | 24 | // TOP MODULE 25 | module bus_arbiter(// Inputs 26 | reset, 27 | clk0, 28 | bus_request, 29 | dma_dataout, 30 | dma_addr, 31 | dma_cmd, 32 | dcache_dataout, 33 | dcache_addr, 34 | dcache_cmd, 35 | icache_dataout, 36 | icache_addr, 37 | icache_cmd, 38 | sdram_dataout, 39 | // Outputs 40 | bus_grant, 41 | dma_datain, 42 | dcache_datain, 43 | icache_datain, 44 | sdram_addr, 45 | sdram_cmd, 46 | sdram_datain 47 | ); 48 | 49 | 50 | // Parameter 51 | `include "parameter.v" 52 | 53 | // FSM States 54 | parameter s_idle = 8'b0000_0001, 55 | s_tap1 = 8'b0000_0010, 56 | s_tap2 = 8'b0000_0100, 57 | s_tap3 = 8'b0000_1000, 58 | s_tap4 = 8'b0001_0000, 59 | s_tap5 = 8'b0010_0000, 60 | s_tap6 = 8'b0100_0000, 61 | s_tap7 = 8'b1000_0000; 62 | 63 | 64 | // Inputs 65 | input reset; 66 | input clk0; 67 | input [arbiter_bus_size - 1 : 0]bus_request; 68 | input [fifo_size - 1 : 0]dma_dataout; 69 | input [padd_size - 1 : 0]dma_addr; 70 | input [cmd_size - 1 : 0]dma_cmd; 71 | input [data_size - 1 : 0]dcache_dataout; 72 | input [padd_size - 1 : 0]dcache_addr; 73 | input [cmd_size - 1 : 0]dcache_cmd; 74 | input [data_size - 1 : 0]icache_dataout; 75 | input [padd_size - 1 : 0]icache_addr; 76 | input [cmd_size - 1 : 0]icache_cmd; 77 | input [data_size - 1 : 0]sdram_dataout; 78 | 79 | // Outputs 80 | output [arbiter_bus_size - 1 : 0]bus_grant; 81 | output [fifo_size - 1 : 0]dma_datain; 82 | output [data_size - 1 : 0]dcache_datain; 83 | output [data_size - 1 : 0]icache_datain; 84 | output [padd_size - 1 : 0]sdram_addr; 85 | output [cmd_size - 1 : 0]sdram_cmd; 86 | output [data_size - 1 : 0]sdram_datain; 87 | 88 | // Signal Declarations 89 | wire reset; 90 | wire clk0; 91 | wire [arbiter_bus_size - 1 : 0]bus_request; 92 | wire [fifo_size - 1 : 0]dma_dataout; 93 | wire [padd_size - 1 : 0]dma_addr; 94 | wire [cmd_size - 1 : 0]dma_cmd; 95 | wire [data_size - 1 : 0]dcache_dataout; 96 | wire [padd_size - 1 : 0]dcache_addr; 97 | wire [cmd_size - 1 : 0]dcache_cmd; 98 | wire [data_size - 1 : 0]icache_dataout; 99 | wire [padd_size - 1 : 0]icache_addr; 100 | wire [cmd_size - 1 : 0]icache_cmd; 101 | wire [data_size - 1 : 0]sdram_dataout; 102 | 103 | wire [arbiter_bus_size - 1 : 0]bus_grant; 104 | wire [fifo_size - 1 : 0]dma_datain; 105 | wire [data_size - 1 : 0]dcache_datain; 106 | wire [data_size - 1 : 0]icache_datain; 107 | wire [padd_size - 1 : 0]sdram_addr; 108 | wire [cmd_size - 1 : 0]sdram_cmd; 109 | wire [data_size - 1 : 0]sdram_datain; 110 | 111 | reg [arbiter_bus_size - 1 : 0]rbus_grant; 112 | reg [fifo_size - 1 : 0]rdma_datain; 113 | reg [data_size - 1 : 0]rdcache_datain; 114 | reg [data_size - 1 : 0]ricache_datain; 115 | reg [padd_size - 1 : 0]rsdram_addr; 116 | reg [cmd_size - 1 : 0]rsdram_cmd; 117 | reg [data_size - 1 : 0]rsdram_datain; 118 | 119 | 120 | // State Registers 121 | reg [7:0]state; 122 | 123 | 124 | // Assignment statments 125 | 126 | 127 | assign bus_grant = rbus_grant; 128 | assign dma_datain = rdma_datain; 129 | assign dcache_datain = rdcache_datain; 130 | assign icache_datain = ricache_datain; 131 | assign sdram_addr = rsdram_addr; 132 | assign sdram_cmd = rsdram_cmd; 133 | assign sdram_datain = rsdram_datain; 134 | 135 | 136 | 137 | // FSM Sequential Section ( One-Hot encoding ) 138 | always @(posedge reset or posedge clk0) 139 | begin 140 | if(reset == 1'b1) 141 | state = s_idle; 142 | else 143 | begin 144 | casex({bus_request,state}) 145 | 146 | 11'b000_0000_0001: 147 | state = s_idle; 148 | 11'b001_0000_0001: 149 | state = s_tap1; 150 | 11'b010_0000_0001: 151 | state = s_tap2; 152 | 11'b011_0000_0001: 153 | state = s_tap3; 154 | 11'b100_0000_0001: 155 | state = s_tap4; 156 | 11'b101_0000_0001: 157 | state = s_tap5; 158 | 11'b110_0000_0001: 159 | state = s_tap6; 160 | 11'b111_0000_0001: 161 | state = s_tap7; 162 | 11'b000_0000_0010: 163 | state = s_idle; 164 | 11'b001_0000_0010: 165 | state = s_tap1; 166 | 11'b000_0000_0100: 167 | state = s_idle; 168 | 11'b010_0000_0100: 169 | state = s_tap2; 170 | 11'b001_0000_1000: 171 | state = s_tap1; 172 | 11'b011_0000_1000: 173 | state = s_tap3; 174 | 11'b000_0001_0000: 175 | state = s_idle; 176 | 11'b100_0001_0000: 177 | state = s_tap4; 178 | 11'b101_0010_0000: 179 | state = s_tap5; 180 | 11'b001_0010_0000: 181 | state = s_tap1; 182 | 11'b110_0100_0000: 183 | state = s_tap6; 184 | 11'b010_0100_0000: 185 | state = s_tap2; 186 | 11'b111_1000_0000: 187 | state = s_tap7; 188 | 11'b011_1000_0000: 189 | state = s_tap3; 190 | default: 191 | state = s_idle; 192 | endcase 193 | end 194 | end 195 | 196 | 197 | // FSM Presets State Task Call 198 | always @(reset or state) 199 | state_task( // Input 200 | state, 201 | reset, 202 | // Outuput 203 | rbus_grant, 204 | rdma_datain, 205 | rdcache_datain, 206 | ricache_datain, 207 | rsdram_addr, 208 | rsdram_cmd, 209 | rsdram_datain 210 | ); 211 | 212 | 213 | // FSM Task ( Combinatorial Section ) 214 | task state_task; 215 | 216 | //INPUTS 217 | input [7:0]state; 218 | input reset; 219 | 220 | //OUTPUTS 221 | output [arbiter_bus_size - 1 : 0]rbus_grant; 222 | output [fifo_size - 1 : 0]rdma_datain; 223 | output [data_size - 1 : 0]rdcache_datain; 224 | output [data_size - 1 : 0]ricache_datain; 225 | output [padd_size - 1 : 0]rsdram_addr; 226 | output [cmd_size - 1 : 0]rsdram_cmd; 227 | output [data_size - 1 : 0]rsdram_datain; 228 | 229 | // Signal Declaration 230 | reg [arbiter_bus_size - 1 : 0]rbus_grant; 231 | reg [fifo_size - 1 : 0]rdma_datain; 232 | reg [data_size - 1 : 0]rdcache_datain; 233 | reg [data_size - 1 : 0]ricache_datain; 234 | reg [padd_size - 1 : 0]rsdram_addr; 235 | reg [cmd_size - 1 : 0]rsdram_cmd; 236 | reg [data_size - 1 : 0]rsdram_datain; 237 | 238 | 239 | // Parameter 240 | parameter s_idle = 8'b0000_0001, 241 | s_tap1 = 8'b0000_0010, 242 | s_tap2 = 8'b0000_0100, 243 | s_tap3 = 8'b0000_1000, 244 | s_tap4 = 8'b0001_0000, 245 | s_tap5 = 8'b0010_0000, 246 | s_tap6 = 8'b0100_0000, 247 | s_tap7 = 8'b1000_0000; 248 | 249 | begin 250 | 251 | if(reset == 1'b1) 252 | begin 253 | rbus_grant <= 3'h0; 254 | rdma_datain <= 8'h0; 255 | rdcache_datain <= 32'h0; 256 | ricache_datain <= 32'h0; 257 | rsdram_addr <= 24'h0; 258 | rsdram_cmd <= 3'h0; 259 | rsdram_datain <= 32'h0; 260 | end 261 | else 262 | begin 263 | case(state) 264 | 265 | s_idle: 266 | begin 267 | rbus_grant <= 3'b000; 268 | rdma_datain <= 8'h0; 269 | rdcache_datain <= 32'h0; 270 | ricache_datain <= 32'h0; 271 | rsdram_addr <= 24'h0; 272 | rsdram_cmd <= 3'h0; 273 | rsdram_datain <= 32'h0; 274 | end 275 | 276 | s_tap1: 277 | begin 278 | rbus_grant <= 3'b001; 279 | rdma_datain <= sdram_dataout; 280 | rdcache_datain <= 32'h0; 281 | ricache_datain <= 32'h0; 282 | rsdram_addr <= dma_addr; 283 | rsdram_cmd <= dma_cmd; 284 | rsdram_datain <= dma_dataout; 285 | end 286 | 287 | s_tap2: 288 | begin 289 | rbus_grant <= 3'b010; 290 | rdma_datain <= 8'h0; 291 | rdcache_datain <= sdram_dataout; 292 | ricache_datain <= sdram_dataout; 293 | rsdram_addr <= dcache_addr | icache_addr; 294 | rsdram_cmd <= dcache_cmd | icache_cmd; 295 | rsdram_datain <= dcache_dataout; 296 | end 297 | 298 | s_tap3: 299 | begin 300 | rbus_grant <= 3'b100; 301 | rdma_datain <= 8'h0; 302 | rdcache_datain <= 32'h0; 303 | ricache_datain <= 32'h0; 304 | rsdram_addr <= 24'h0; 305 | rsdram_cmd <= 3'h0; 306 | rsdram_datain <= dcache_dataout; 307 | end 308 | 309 | s_tap4: 310 | begin 311 | rbus_grant <= 3'b100; 312 | rdma_datain <= 8'h0; 313 | rdcache_datain <= 32'h0; 314 | ricache_datain <= 32'h0; 315 | rsdram_addr <= 24'h0; 316 | rsdram_cmd <= 3'h0; 317 | rsdram_datain <= icache_dataout; 318 | end 319 | 320 | s_tap5: 321 | begin 322 | rbus_grant <= 3'b100; 323 | rdma_datain <= 8'h0; 324 | rdcache_datain <= 32'h0; 325 | ricache_datain <= 32'h0; 326 | rsdram_addr <= 24'h0; 327 | rsdram_cmd <= 3'h0; 328 | rsdram_datain <= dcache_dataout; 329 | end 330 | 331 | s_tap6: 332 | begin 333 | rbus_grant <= 3'b100; 334 | rdma_datain <= 8'h0; 335 | rdcache_datain <= 32'h0; 336 | ricache_datain <= 32'h0; 337 | rsdram_addr <= 24'h0; 338 | rsdram_cmd <= 3'h0; 339 | rsdram_datain <= icache_dataout; 340 | end 341 | 342 | s_tap7: 343 | begin 344 | rbus_grant <= 3'b100; 345 | rdma_datain <= 8'h0; 346 | rdcache_datain <= 32'h0; 347 | ricache_datain <= 32'h0; 348 | rsdram_addr <= 24'h0; 349 | rsdram_cmd <= 3'h0; 350 | rsdram_datain <= dma_dataout; 351 | end 352 | 353 | default: 354 | begin 355 | rbus_grant <= 3'b100; 356 | rdma_datain <= 8'h0; 357 | rdcache_datain <= 32'h0; 358 | ricache_datain <= 32'h0; 359 | rsdram_addr <= 24'h0; 360 | rsdram_cmd <= 3'h0; 361 | rsdram_datain <= dcache_dataout; 362 | end 363 | endcase 364 | end 365 | end 366 | endtask 367 | 368 | 369 | endmodule 370 | -------------------------------------------------------------------------------- /Verilog/risc.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Sub Level RISC uProcessor Block 3 | 4 | FILE NAME: risc.v 5 | VERSION: 1.0 6 | DATE: May 7th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of RISC uProcessor verilog code. 12 | 13 | It will instantiate the following blocks in the ASIC: 14 | 15 | 1) Program Counter 16 | 2) Instruction Register 17 | 3) Accumulator 18 | 4) Arithmatic Logic Unit 19 | 5) Multiplexer 20 | 6) Multiplexer 21 | 7) Control Unit 22 | 23 | Hossein Amidi 24 | (C) April 2002 25 | 26 | *********************************************************/ 27 | 28 | // DEFINES 29 | `timescale 1ns / 10ps 30 | 31 | // TOP MODULE 32 | module risc(// Inputs 33 | reset, 34 | clk0, 35 | pll_lock, 36 | interrupt, 37 | cmdack, 38 | dcache_datain, 39 | dcache_hit, 40 | dcache_miss, 41 | icache_datain, 42 | icache_hit, 43 | icache_miss, 44 | dma_datain, 45 | dma_busy, 46 | timer_host_datain, 47 | flash_host_datain, 48 | uart_host_datain, 49 | mem_datain, 50 | // Outputs 51 | paddr, 52 | cmd, 53 | dm, 54 | dcache_request, 55 | icache_request, 56 | dma_dataout, 57 | dcache_dataout, 58 | icache_dataout, 59 | timer_host_dataout, 60 | flash_host_dataout, 61 | uart_host_dataout, 62 | mem_dataout, 63 | mem_req, 64 | mem_rdwr, 65 | halted 66 | ); 67 | 68 | 69 | // Parameter 70 | `include "parameter.v" 71 | 72 | 73 | // Inputs 74 | input reset; 75 | input clk0; 76 | input pll_lock; 77 | input [irq_size - 1 : 0]interrupt; 78 | input cmdack; 79 | input [data_size - 1 : 0]dcache_datain; 80 | input dcache_hit; 81 | input dcache_miss; 82 | input [data_size - 1 : 0]icache_datain; 83 | input icache_hit; 84 | input icache_miss; 85 | input [data_size - 1 : 0]dma_datain; 86 | input dma_busy; 87 | input [data_size - 1 : 0]timer_host_datain; 88 | input [data_size - 1 : 0]flash_host_datain; 89 | input [data_size - 1 : 0]uart_host_datain; 90 | input [data_size - 1 : 0]mem_datain; 91 | 92 | // Outputs 93 | output [padd_size - 1 : 0]paddr; 94 | output [cmd_size - 1 : 0]cmd; 95 | output [dqm_size - 1 : 0]dm; 96 | output dcache_request; 97 | output icache_request; 98 | output [data_size - 1 : 0]dma_dataout; 99 | output [data_size - 1 : 0]dcache_dataout; 100 | output [data_size - 1 : 0]icache_dataout; 101 | output [data_size - 1 : 0]timer_host_dataout; 102 | output halted; 103 | output [data_size - 1 : 0]flash_host_dataout; 104 | output [data_size - 1 : 0]uart_host_dataout; 105 | output [data_size - 1 : 0]mem_dataout; 106 | output mem_req; 107 | output mem_rdwr; 108 | 109 | // Signal Declarations 110 | wire reset; 111 | wire clk0; 112 | wire pll_lock; 113 | wire [irq_size - 1 : 0]interrupt; 114 | wire cmdack; 115 | wire [data_size - 1 : 0]dcache_datain; 116 | wire dcache_hit; 117 | wire dcache_miss; 118 | wire [data_size - 1 : 0]icache_datain; 119 | wire icache_hit; 120 | wire icache_miss; 121 | wire [data_size - 1 : 0]dma_datain; 122 | wire dma_busy; 123 | wire [data_size - 1 : 0]timer_host_datain; 124 | wire [data_size - 1 : 0]flash_host_datain; 125 | wire [data_size - 1 : 0]uart_host_datain; 126 | wire [data_size - 1 : 0]mem_datain; 127 | wire ready; 128 | 129 | 130 | wire [padd_size - 1 : 0]paddr; 131 | reg [cmd_size - 1 : 0]cmd; 132 | reg [dqm_size - 1 : 0]dm; 133 | wire dcache_request; 134 | wire icache_request; 135 | wire [data_size - 1 : 0]dma_dataout; 136 | wire [data_size - 1 : 0]dcache_dataout; 137 | wire [data_size - 1 : 0]icache_dataout; 138 | wire [data_size - 1 : 0]timer_host_dataout; 139 | wire halted; 140 | wire [data_size - 1 : 0]flash_host_dataout; 141 | wire [data_size - 1 : 0]uart_host_dataout; 142 | wire [data_size - 1 : 0]mem_dataout; 143 | wire mem_req; 144 | wire mem_rdwr; 145 | 146 | reg [data_size - 1 : 0]rdma_datain; 147 | reg rdcache_miss; 148 | reg rdcache_hit; 149 | reg [data_size - 1 : 0]rdcache_datain; 150 | reg ricache_miss; 151 | reg ricache_hit; 152 | reg [data_size - 1 : 0]ricache_datain; 153 | reg [irq_size - 1 : 0]rinterrupt; 154 | 155 | 156 | // Assignment statments 157 | 158 | 159 | // Signal Declerations 160 | wire [AddrWidth - 1 : 0] instraddress; 161 | wire [DataWidth - 1 : 0] aludataout; 162 | wire pcinen; 163 | wire [AddrWidth - 1 : 0] operandaddress; 164 | wire [OpcodeWidth - 1 : 0] opcode; 165 | wire [DataWidth - 1 : 0] datain; 166 | wire irinen; 167 | wire [DataWidth - 1 : 0] accdataout; 168 | wire accneg; 169 | wire acczero; 170 | wire accinen; 171 | wire [StateSize - 1 : 0] currentstate; 172 | wire [DataWidth - 1 : 0] mux16out; 173 | wire [AddrWidth - 1 : 0] address; 174 | wire addresssel; 175 | wire alusrcbsel; 176 | wire walusrcbsel; 177 | wire accouten; 178 | 179 | wire memreq; 180 | wire rdwrbar; 181 | 182 | reg Rd_req; 183 | reg Wr_req; 184 | wire [DataWidth - 1 : 0] dataout; 185 | wire Halted; 186 | //wire [DataWidth - 1 : 0] datain; 187 | 188 | 189 | // Assignments 190 | assign halted = Halted; 191 | assign ready = cmdack; 192 | assign paddr = address; 193 | assign datain = dcache_hit ? datain : 32'bz; 194 | assign mem_dataout = accouten? accdataout: 32'bz; 195 | assign Halted = (opcode == 7) ? 1'b1 : 1'b0; 196 | 197 | assign walusrcbsel = alusrcbsel; 198 | 199 | assign dcache_request = Rd_req | Wr_req; 200 | assign icache_request = Rd_req | Wr_req; 201 | 202 | 203 | assign mem_req = memreq; 204 | assign mem_rdwr = rdwrbar; 205 | 206 | assign dma_dataout = mem_dataout; 207 | assign flash_host_dataout = mem_dataout; 208 | assign dcache_dataout = mem_dataout; 209 | assign icache_dataout = mem_dataout; 210 | assign timer_host_dataout = mem_dataout; 211 | assign uart_host_dataout = mem_dataout; 212 | 213 | always @(rdwrbar or memreq) 214 | begin 215 | if((memreq == 1'b1) && (rdwrbar == 1'b1)) 216 | begin 217 | Rd_req = 1'b1; 218 | Wr_req = 1'b0; 219 | end 220 | else 221 | if((memreq == 1'b1) && (rdwrbar == 1'b0)) 222 | begin 223 | Rd_req = 1'b0; 224 | Wr_req = 1'b1; 225 | end 226 | else 227 | begin 228 | Rd_req = 1'b0; 229 | Wr_req = 1'b0; 230 | end 231 | end 232 | 233 | 234 | always @(memreq or Wr_req or Rd_req) 235 | begin 236 | case({memreq, Wr_req, Rd_req}) 237 | 238 | 3'b100: cmd <= 3'b000; // NOP 239 | 3'b101: cmd <= 3'b001; // ReadA 240 | 3'b110: cmd <= 3'b010; // WriteA 241 | 3'b111: cmd <= 3'b011; // Refresh 242 | 3'b000: cmd <= 3'b100; // Preacharge 243 | 3'b001: cmd <= 3'b101; // Load Mode Register 244 | 3'b010: cmd <= 3'b110; // Load Timing Register 245 | 3'b011: cmd <= 3'b111; // Load Refresh Counter 246 | endcase 247 | 248 | end 249 | 250 | always @(posedge reset or posedge clk0) 251 | begin 252 | if (reset == 1'b1) 253 | begin 254 | dm <= 4'h0; 255 | end 256 | else 257 | begin 258 | dm <= {1'b1,rinterrupt}; 259 | end 260 | end 261 | 262 | 263 | always @(posedge reset or posedge clk0) 264 | begin 265 | if(reset == 1'b1) 266 | begin 267 | rdma_datain <= 32'h0; 268 | rdcache_miss <= 1'b0; 269 | rdcache_hit <= 1'b0; 270 | rdcache_datain <= 32'h0; 271 | ricache_miss <= 1'b0; 272 | ricache_hit <= 1'b0; 273 | ricache_datain <= 32'h0; 274 | rinterrupt <= 3'b0; 275 | end 276 | else 277 | begin 278 | rdma_datain <= dma_datain; 279 | rdcache_miss <= dcache_miss; 280 | rdcache_hit <= dcache_hit & rdcache_hit; 281 | rdcache_datain <= dcache_datain; 282 | ricache_miss <= icache_miss; 283 | ricache_hit <= icache_hit & ricache_hit; 284 | ricache_datain <= icache_datain; 285 | rinterrupt <= interrupt; 286 | end 287 | end 288 | 289 | 290 | 291 | 292 | 293 | /***************************** Instantiation **************************/ 294 | 295 | // RISC CPU's Program Counter Instantiation 296 | PC ProgramCounter ( // INPUT 297 | .clock(clk0), 298 | .reset(reset), 299 | .PCInEn(pcinen), 300 | .PCDataIn(aludataout[23:0]), 301 | // OUTPUT 302 | .PCDataOut(instraddress) 303 | ); 304 | 305 | 306 | // RISC CPU's Instruction Register Instantiation 307 | IR InstructionRegister ( // Input 308 | .clock(clk0), 309 | .reset(reset), 310 | .IRInEn(irinen), 311 | .IRDataIn(mem_datain), 312 | // Output 313 | .OperandOut(operandaddress), 314 | .OpCodeOut(opcode) 315 | ); 316 | 317 | 318 | // RISC CPU's Accumulator Instantiation 319 | ACC Accumulator ( // Input 320 | .clock(clk0), 321 | .reset(reset), 322 | .ACCInEn(accinen), 323 | .ACCDataIn(aludataout), 324 | // Output 325 | .ACCNeg(accneg), 326 | .ACCZero(acczero), 327 | .ACCDataOut(accdataout) 328 | ); 329 | 330 | 331 | 332 | // RISC CPU's Arithmatic Logic Unit Instantiation 333 | ALU ALU ( // Input 334 | .ALUSrcA(accdataout), 335 | .ALUSrcB(mux16out), 336 | .OpCode(opcode), 337 | .CurrentState(currentstate), 338 | // Output 339 | .ALUDataOut(aludataout) 340 | ); 341 | 342 | 343 | MUX12 Mux12 ( // Input 344 | .A_in(operandaddress), 345 | .B_in(instraddress), 346 | .A_Select(addresssel), 347 | // Output 348 | .Out(address) 349 | ); 350 | 351 | 352 | MUX16 Mux16 ( // Input 353 | .A_in(address), 354 | .B_in(mem_datain), 355 | .A_Select(walusrcbsel), 356 | // Output 357 | .Out(mux16out) 358 | ); 359 | 360 | 361 | 362 | // RISC CPU's Control Unit Instantiation 363 | CNTRL ControlUnit ( // Input 364 | .clock(clk0), 365 | .reset(reset), 366 | .OpCode(opcode), 367 | .ACCNeg(accneg), 368 | .ACCZero(acczero), 369 | .Grant(pll_lock), 370 | // Output 371 | .NextState(currentstate), 372 | .PCInEn(pcinen), 373 | .IRInEn(irinen), 374 | .ACCInEn(accinen), 375 | .ACCOutEn(accouten), 376 | .MemReq(memreq), 377 | .RdWrBar(rdwrbar), 378 | .AddressSel(addresssel), 379 | .ALUSrcBSel(alusrcbsel) 380 | ); 381 | 382 | endmodule 383 | -------------------------------------------------------------------------------- /Verilog/lru_data_cache.v: -------------------------------------------------------------------------------- 1 | /********************************************************** 2 | MODULE: Sub Level Least Recently Used Data Cache 3 | 4 | FILE NAME: lru_data_cache.v 5 | VERSION: 1.0 6 | DATE: May 7th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of LRU 12 | Data Cache verilog code. 13 | 14 | It will instantiate the following blocks in the ASIC: 15 | 16 | 1) Data Cache Way 0 17 | 2) Data Cache Way 1 18 | 3) Data Cache Way 2 19 | 4) Data Cache Way 3 20 | 21 | 22 | Hossein Amidi 23 | (C) April 2002 24 | 25 | *********************************************************/ 26 | 27 | // DEFINES 28 | `timescale 1ns / 10ps 29 | 30 | // TOP MODULE 31 | module lru_data_cache(// Inputs 32 | reset, 33 | clk0, 34 | cache_host_addr, 35 | cache_host_cmd, 36 | cache_request, 37 | cache_host_datain, 38 | cache_bus_grant, 39 | cache_datain, 40 | // Outputs 41 | cache_host_dataout, 42 | cache_hit, 43 | cache_miss, 44 | cache_bus_request, 45 | cache_addr, 46 | cache_cmd, 47 | cache_dataout 48 | ); 49 | 50 | 51 | // Parameter 52 | `include "parameter.v" 53 | 54 | // Inputs 55 | input reset; 56 | input clk0; 57 | input [padd_size - 1 : 0]cache_host_addr; 58 | input [cmd_size - 1 : 0]cache_host_cmd; 59 | input cache_request; 60 | input [data_size - 1 : 0]cache_host_datain; 61 | input cache_bus_grant; 62 | input [data_size - 1 : 0]cache_datain; 63 | 64 | // Outputs 65 | output [data_size - 1 : 0]cache_host_dataout; 66 | output cache_hit; 67 | output cache_miss; 68 | output cache_bus_request; 69 | output [padd_size - 1 : 0]cache_addr; 70 | output [cmd_size - 1 : 0]cache_cmd; 71 | output [data_size - 1 : 0]cache_dataout; 72 | 73 | // Signal Declarations 74 | wire reset; 75 | wire clk0; 76 | wire [padd_size - 1 : 0]cache_host_addr; 77 | wire [cmd_size - 1 : 0]cache_host_cmd; 78 | wire cache_request; 79 | wire [data_size - 1 : 0]cache_host_datain; 80 | wire cache_bus_grant; 81 | wire [data_size - 1 : 0]cache_datain; 82 | 83 | reg [data_size - 1 : 0]cache_host_dataout; 84 | reg cache_hit; 85 | reg cache_miss; 86 | wire cache_bus_request; 87 | reg [padd_size - 1 : 0]cache_addr; 88 | reg [cmd_size - 1 : 0]cache_cmd; 89 | reg [data_size - 1 : 0]cache_dataout; 90 | 91 | wire [cache_line_size - 1 : 0]data_cache_datain_way0; 92 | wire [cache_line_size - 1 : 0]data_cache_datain_way1; 93 | wire [cache_line_size - 1 : 0]data_cache_datain_way2; 94 | wire [cache_line_size - 1 : 0]data_cache_datain_way3; 95 | wire [cache_line_size - 1 : 0]data_cache_dataout_way0; 96 | wire [cache_line_size - 1 : 0]data_cache_dataout_way1; 97 | wire [cache_line_size - 1 : 0]data_cache_dataout_way2; 98 | wire [cache_line_size - 1 : 0]data_cache_dataout_way3; 99 | 100 | wire cache_wr; 101 | reg [cache_valid - 1 : 0]valid0; 102 | reg [cache_valid - 1 : 0]valid1; 103 | reg [cache_valid - 1 : 0]valid2; 104 | reg [cache_valid - 1 : 0]valid3; 105 | wire [cache_tag - 1 : 0]tag; 106 | wire [cache_tag - 1 : 0]read_tag0; 107 | wire [cache_tag - 1 : 0]read_tag1; 108 | wire [cache_tag - 1 : 0]read_tag2; 109 | wire [cache_tag - 1 : 0]read_tag3; 110 | 111 | /********* Internal Register of Data cache configuration *********/ 112 | reg [cache_reg_width - 1 : 0] cache_register [cache_reg_depth - 1 : 0]; 113 | 114 | 115 | 116 | // Assignment statments 117 | assign cache_bus_request = cache_miss; 118 | assign cache_wr = (cache_host_cmd == 010) ? 1'b1 : 1'b0; 119 | 120 | assign tag = cache_host_addr[23:5]; 121 | assign read_tag0 = data_cache_dataout_way0[50:32]; 122 | assign read_tag1 = data_cache_dataout_way1[50:32]; 123 | assign read_tag2 = data_cache_dataout_way2[50:32]; 124 | assign read_tag3 = data_cache_dataout_way3[50:32]; 125 | assign data_cache_datain_way0 = ({valid0,tag,cache_datain}); 126 | assign data_cache_datain_way1 = ({valid1,tag,cache_datain}); 127 | assign data_cache_datain_way2 = ({valid2,tag,cache_datain}); 128 | assign data_cache_datain_way3 = ({valid3,tag,cache_datain}); 129 | 130 | /********************************** Sub Level Instantiation *********************************/ 131 | 132 | 133 | data_cache_way0 data_cache_way0_0 (// Input 134 | .A(cache_host_addr[4:0]), 135 | .CLK(clk0), 136 | .D(data_cache_datain_way0), 137 | .WE(cache_wr), 138 | .SPO(data_cache_dataout_way0)); 139 | 140 | 141 | data_cache_way1 data_cache_way1_0 (// Input 142 | .A(cache_host_addr[4:0]), 143 | .CLK(clk0), 144 | .D(data_cache_datain_way1), 145 | .WE(cache_wr), 146 | .SPO(data_cache_dataout_way1)); 147 | 148 | 149 | data_cache_way2 data_cache_way2_0 (// Input 150 | .A(cache_host_addr[4:0]), 151 | .CLK(clk0), 152 | .D(data_cache_datain_way2), 153 | .WE(cache_wr), 154 | .SPO(data_cache_dataout_way2)); 155 | 156 | 157 | data_cache_way3 data_cache_way3_0 (// Input 158 | .A(cache_host_addr[4:0]), 159 | .CLK(clk0), 160 | .D(data_cache_datain_way3), 161 | .WE(cache_wr), 162 | .SPO(data_cache_dataout_way3)); 163 | 164 | 165 | 166 | // Generate the LRU talbe 167 | always @(posedge reset or posedge clk0) 168 | begin 169 | if(reset == 1'b1) 170 | begin 171 | valid0 <= 2'b00; 172 | valid1 <= 2'b00; 173 | valid2 <= 2'b10; 174 | valid3 <= 2'b10; 175 | end 176 | else 177 | if((cache_wr == 1'b1) && (valid0 == 2'b00)) 178 | valid0 <= 2'b01; 179 | else 180 | if((cache_wr == 1'b1) && (valid0 == 2'b01)) 181 | valid0 <= 2'b00; 182 | else 183 | if((cache_wr == 1'b1) && (valid1 == 2'b00)) 184 | valid1 <= 2'b01; 185 | else 186 | if((cache_wr == 1'b1) && (valid1 == 2'b01)) 187 | valid1 <= 2'b00; 188 | else 189 | if((cache_wr == 1'b1) && (valid2 == 2'b10)) 190 | valid2 <= 2'b11; 191 | else 192 | if((cache_wr == 1'b1) && (valid2 == 2'b11)) 193 | valid2 <= 2'b10; 194 | else 195 | if((cache_wr == 1'b1) && (valid3 == 2'b10)) 196 | valid3 <= 2'b11; 197 | else 198 | if((cache_wr == 1'b1) && (valid3 == 2'b11)) 199 | valid3 <= 2'b10; 200 | end 201 | 202 | 203 | // Check for cache way validity, if matches generate the cache hit signal 204 | // else generate cache miss signal 205 | always @(posedge reset or posedge clk0) 206 | begin 207 | if(reset == 1'b1) 208 | cache_dataout <= 32'h0; 209 | else 210 | if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag0 == cache_host_addr[23:5])) 211 | begin 212 | cache_hit <= 1'b1; 213 | cache_dataout <= data_cache_dataout_way0[31:0]; 214 | end 215 | else 216 | if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag1 == cache_host_addr[23:5])) 217 | begin 218 | cache_hit <= 1'b1; 219 | cache_dataout <= data_cache_dataout_way1[31:0]; 220 | end 221 | else 222 | if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag2 == cache_host_addr[23:5])) 223 | begin 224 | cache_hit <= 1'b1; 225 | cache_dataout <= data_cache_dataout_way2[31:0]; 226 | end 227 | else 228 | if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag3 == cache_host_addr[23:5])) 229 | begin 230 | cache_hit <= 1'b1; 231 | cache_dataout <= data_cache_dataout_way3[31:0]; 232 | end 233 | else 234 | if((cache_request == 1'b1) && (cache_host_cmd == 001)) 235 | begin 236 | cache_miss <= 1'b1; 237 | cache_hit <= 1'b0; 238 | cache_dataout <= 32'h0; 239 | end 240 | else 241 | begin 242 | cache_miss <= 1'b0; 243 | cache_hit <= 1'b0; 244 | cache_dataout <= 32'h0; 245 | end 246 | end 247 | 248 | 249 | // Access to internal register by CPU address and command signals (write/read) 250 | always @(posedge reset or posedge clk0) 251 | begin 252 | if(reset == 1'b1) 253 | begin 254 | cache_host_dataout <= 32'h0; 255 | cache_register[0] <= 32'h0; 256 | cache_register[1] <= 32'h0; 257 | cache_register[2] <= 32'h0; 258 | cache_register[3] <= 32'h0; 259 | cache_register[4] <= 32'h0; 260 | cache_register[5] <= 32'h0; 261 | cache_register[6] <= 32'h0; 262 | cache_register[7] <= 32'h0; 263 | end 264 | else 265 | begin 266 | if(cache_host_cmd == 3'b010) // Write from Host to Cache internal Registers 267 | begin 268 | case (cache_host_addr) 269 | 270 | 24'h080010: cache_register[0] <= cache_host_datain; // Status Register 271 | 24'h080011: cache_register[1] <= cache_host_datain; // Read Master Start Address 272 | 24'h080012: cache_register[2] <= cache_host_datain; // Write Master Start Address 273 | 24'h080013: cache_register[3] <= cache_host_datain; // Length in Bytes 274 | 24'h080014: cache_register[4] <= cache_host_datain; // Reserved 275 | 24'h080015: cache_register[5] <= cache_host_datain; // Reserved 276 | 24'h080016: cache_register[6] <= cache_host_datain; // Control 277 | 24'h080017: cache_register[7] <= cache_host_datain; // Reserved 278 | endcase 279 | end 280 | else 281 | if(cache_host_cmd == 3'b001) // Read from Cache internal Registers to Host 282 | begin 283 | case (cache_host_addr) 284 | 285 | 24'h080010: cache_host_dataout <= cache_register[0]; 286 | 24'h080011: cache_host_dataout <= cache_register[1]; 287 | 24'h080012: cache_host_dataout <= cache_register[2]; 288 | 24'h080013: cache_host_dataout <= cache_register[3]; 289 | 24'h080014: cache_host_dataout <= cache_register[4]; 290 | 24'h080015: cache_host_dataout <= cache_register[5]; 291 | 24'h080016: cache_host_dataout <= cache_register[6]; 292 | 24'h080017: cache_host_dataout <= cache_register[7]; 293 | endcase 294 | end 295 | end 296 | end 297 | 298 | 299 | always @(posedge reset or posedge clk0) 300 | begin 301 | if(reset == 1'b1) 302 | begin 303 | cache_addr <= 24'h0; 304 | cache_cmd <= 3'h0; 305 | end 306 | else 307 | begin 308 | cache_addr <= cache_bus_grant & cache_host_addr; 309 | cache_cmd <= cache_bus_grant & cache_host_cmd; 310 | end 311 | end 312 | 313 | endmodule 314 | -------------------------------------------------------------------------------- /Verilog/lru_instruction_cache.v: -------------------------------------------------------------------------------- 1 | /********************************************************** 2 | MODULE: Sub Level Least Recently Used Instruction Cache 3 | 4 | FILE NAME: lru_instruction_cache.v 5 | VERSION: 1.0 6 | DATE: May 7th, 2002 7 | AUTHOR: Hossein Amidi 8 | COMPANY: 9 | CODE TYPE: Register Transfer Level 10 | 11 | DESCRIPTION: This module is the top level RTL code of LRU 12 | instruction Cache verilog code. 13 | 14 | It will instantiate the following blocks in the ASIC: 15 | 16 | 1) Instruction Cache Way 0 17 | 2) Instruction Cache Way 1 18 | 3) Instruction Cache Way 2 19 | 4) Instruction Cache Way 3 20 | 21 | 22 | Hossein Amidi 23 | (C) April 2002 24 | 25 | *********************************************************/ 26 | 27 | // DEFINES 28 | `timescale 1ns / 10ps 29 | 30 | // TOP MODULE 31 | module lru_instruction_cache(// Inputs 32 | reset, 33 | clk0, 34 | cache_host_addr, 35 | cache_host_cmd, 36 | cache_request, 37 | cache_host_datain, 38 | cache_bus_grant, 39 | cache_datain, 40 | // Outputs 41 | cache_host_dataout, 42 | cache_hit, 43 | cache_miss, 44 | cache_bus_request, 45 | cache_addr, 46 | cache_cmd, 47 | cache_dataout 48 | ); 49 | 50 | 51 | // Parameter 52 | `include "parameter.v" 53 | 54 | // Inputs 55 | input reset; 56 | input clk0; 57 | input [padd_size - 1 : 0]cache_host_addr; 58 | input [cmd_size - 1 : 0]cache_host_cmd; 59 | input cache_request; 60 | input [data_size - 1 : 0]cache_host_datain; 61 | input cache_bus_grant; 62 | input [data_size - 1 : 0]cache_datain; 63 | 64 | // Outputs 65 | output [data_size - 1 : 0]cache_host_dataout; 66 | output cache_hit; 67 | output cache_miss; 68 | output cache_bus_request; 69 | output [padd_size - 1 : 0]cache_addr; 70 | output [cmd_size - 1 : 0]cache_cmd; 71 | output [data_size - 1 : 0]cache_dataout; 72 | 73 | // Signal Declarations 74 | wire reset; 75 | wire clk0; 76 | wire [padd_size - 1 : 0]cache_host_addr; 77 | wire [cmd_size - 1 : 0]cache_host_cmd; 78 | wire cache_request; 79 | wire [data_size - 1 : 0]cache_host_datain; 80 | wire cache_bus_grant; 81 | wire [data_size - 1 : 0]cache_datain; 82 | 83 | reg [data_size - 1 : 0]cache_host_dataout; 84 | reg cache_hit; 85 | reg cache_miss; 86 | wire cache_bus_request; 87 | reg [padd_size - 1 : 0]cache_addr; 88 | reg [cmd_size - 1 : 0]cache_cmd; 89 | reg [data_size - 1 : 0]cache_dataout; 90 | 91 | wire [cache_line_size - 1 : 0]instruction_cache_datain_way0; 92 | wire [cache_line_size - 1 : 0]instruction_cache_datain_way1; 93 | wire [cache_line_size - 1 : 0]instruction_cache_datain_way2; 94 | wire [cache_line_size - 1 : 0]instruction_cache_datain_way3; 95 | wire [cache_line_size - 1 : 0]instruction_cache_dataout_way0; 96 | wire [cache_line_size - 1 : 0]instruction_cache_dataout_way1; 97 | wire [cache_line_size - 1 : 0]instruction_cache_dataout_way2; 98 | wire [cache_line_size - 1 : 0]instruction_cache_dataout_way3; 99 | 100 | wire cache_wr; 101 | reg [cache_valid - 1 : 0]valid0; 102 | reg [cache_valid - 1 : 0]valid1; 103 | reg [cache_valid - 1 : 0]valid2; 104 | reg [cache_valid - 1 : 0]valid3; 105 | wire [cache_tag - 1 : 0]tag; 106 | wire [cache_tag - 1 : 0]read_tag0; 107 | wire [cache_tag - 1 : 0]read_tag1; 108 | wire [cache_tag - 1 : 0]read_tag2; 109 | wire [cache_tag - 1 : 0]read_tag3; 110 | 111 | wire [cache_valid - 1 : 0]wvalid0; 112 | wire [cache_valid - 1 : 0]wvalid1; 113 | wire [cache_valid - 1 : 0]wvalid2; 114 | wire [cache_valid - 1 : 0]wvalid3; 115 | 116 | 117 | /********* Internal Register of Instruction cache configuration *********/ 118 | reg [cache_reg_width - 1 : 0] cache_register [cache_reg_depth - 1 : 0]; 119 | 120 | 121 | 122 | // Assignment statments 123 | assign cache_bus_request = cache_miss; 124 | assign cache_wr = (cache_host_cmd == 010) ? 1'b1 : 1'b0; 125 | 126 | assign tag = cache_host_addr[23:5]; 127 | assign read_tag0 = instruction_cache_dataout_way0[50:32]; 128 | assign read_tag1 = instruction_cache_dataout_way1[50:32]; 129 | assign read_tag2 = instruction_cache_dataout_way2[50:32]; 130 | assign read_tag3 = instruction_cache_dataout_way3[50:32]; 131 | assign instruction_cache_datain_way0 = ({wvalid0,tag,cache_datain}); 132 | assign instruction_cache_datain_way1 = ({wvalid1,tag,cache_datain}); 133 | assign instruction_cache_datain_way2 = ({wvalid2,tag,cache_datain}); 134 | assign instruction_cache_datain_way3 = ({wvalid3,tag,cache_datain}); 135 | 136 | assign wvalid0 = valid0; 137 | assign wvalid1 = valid1; 138 | assign wvalid2 = valid2; 139 | assign wvalid3 = valid3; 140 | 141 | /********************************** Sub Level Instantiation *********************************/ 142 | 143 | 144 | instruction_cache_way0 instruction_cache_way0_0 (// Input 145 | .A(cache_host_addr[4:0]), 146 | .CLK(clk0), 147 | .D(instruction_cache_datain_way0), 148 | .WE(cache_wr), 149 | .SPO(instruction_cache_dataout_way0)); 150 | 151 | 152 | instruction_cache_way1 instruction_cache_way1_0 (// Input 153 | .A(cache_host_addr[4:0]), 154 | .CLK(clk0), 155 | .D(instruction_cache_datain_way1), 156 | .WE(cache_wr), 157 | .SPO(instruction_cache_dataout_way1)); 158 | 159 | 160 | instruction_cache_way2 instruction_cache_way2_0 (// Input 161 | .A(cache_host_addr[4:0]), 162 | .CLK(clk0), 163 | .D(instruction_cache_datain_way2), 164 | .WE(cache_wr), 165 | .SPO(instruction_cache_dataout_way2)); 166 | 167 | 168 | instruction_cache_way3 instruction_cache_way3_0 (// Input 169 | .A(cache_host_addr[4:0]), 170 | .CLK(clk0), 171 | .D(instruction_cache_datain_way3), 172 | .WE(cache_wr), 173 | .SPO(instruction_cache_dataout_way3)); 174 | 175 | 176 | 177 | // Generate the LRU talbe 178 | always @(posedge reset or posedge clk0) 179 | begin 180 | if(reset == 1'b1) 181 | begin 182 | valid0 <= 2'b00; 183 | valid1 <= 2'b00; 184 | valid2 <= 2'b10; 185 | valid3 <= 2'b10; 186 | end 187 | else 188 | begin 189 | if((cache_wr == 1'b1) && (wvalid0 == 2'b00)) 190 | valid0 <= 2'b01; 191 | else 192 | if((cache_wr == 1'b1) && (wvalid0 == 2'b01)) 193 | valid0 <= 2'b00; 194 | else 195 | if((cache_wr == 1'b1) && (wvalid1 == 2'b00)) 196 | valid1 <= 2'b01; 197 | else 198 | if((cache_wr == 1'b1) && (wvalid1 == 2'b01)) 199 | valid1 <= 2'b00; 200 | else 201 | if((cache_wr == 1'b1) && (wvalid2 == 2'b10)) 202 | valid2 <= 2'b11; 203 | else 204 | if((cache_wr == 1'b1) && (wvalid2 == 2'b11)) 205 | valid2 <= 2'b10; 206 | else 207 | if((cache_wr == 1'b1) && (wvalid3 == 2'b10)) 208 | valid3 <= 2'b11; 209 | else 210 | if((cache_wr == 1'b1) && (wvalid3 == 2'b11)) 211 | valid3 <= 2'b10; 212 | end 213 | end 214 | 215 | 216 | // Check for cache way validity, if matches generate the cache hit signal 217 | // else generate cache miss signal 218 | always @(posedge reset or posedge clk0) 219 | begin 220 | if(reset == 1'b1) 221 | cache_dataout <= 32'h0; 222 | else 223 | if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag0 == cache_host_addr[23:5])) 224 | begin 225 | cache_hit <= 1'b1; 226 | cache_dataout <= instruction_cache_dataout_way0[31:0]; 227 | end 228 | else 229 | if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag1 == cache_host_addr[23:5])) 230 | begin 231 | cache_hit <= 1'b1; 232 | cache_dataout <= instruction_cache_dataout_way1[31:0]; 233 | end 234 | else 235 | if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag2 == cache_host_addr[23:5])) 236 | begin 237 | cache_hit <= 1'b1; 238 | cache_dataout <= instruction_cache_dataout_way2[31:0]; 239 | end 240 | else 241 | if((cache_request == 1'b1) && (cache_host_cmd == 001) && (read_tag3 == cache_host_addr[23:5])) 242 | begin 243 | cache_hit <= 1'b1; 244 | cache_dataout <= instruction_cache_dataout_way3[31:0]; 245 | end 246 | else 247 | if((cache_request == 1'b1) && (cache_host_cmd == 001)) 248 | begin 249 | cache_miss <= 1'b1; 250 | cache_hit <= 1'b0; 251 | cache_dataout <= 32'h0; 252 | end 253 | else 254 | begin 255 | cache_miss <= 1'b0; 256 | cache_hit <= 1'b0; 257 | cache_dataout <= 32'h0; 258 | end 259 | end 260 | 261 | 262 | // Access to internal register by CPU address and command signals (write/read) 263 | always @(posedge reset or posedge clk0) 264 | begin 265 | if(reset == 1'b1) 266 | begin 267 | cache_host_dataout <= 32'h0; 268 | cache_register[0] <= 32'h0; 269 | cache_register[1] <= 32'h0; 270 | cache_register[2] <= 32'h0; 271 | cache_register[3] <= 32'h0; 272 | cache_register[4] <= 32'h0; 273 | cache_register[5] <= 32'h0; 274 | cache_register[6] <= 32'h0; 275 | cache_register[7] <= 32'h0; 276 | end 277 | else 278 | begin 279 | if(cache_host_cmd == 3'b010) // Write from Host to Cache internal Registers 280 | begin 281 | case (cache_host_addr) 282 | 283 | 24'h080018: cache_register[0] <= cache_host_datain; // Status Register 284 | 24'h080019: cache_register[1] <= cache_host_datain; // Read Master Start Address 285 | 24'h08001A: cache_register[2] <= cache_host_datain; // Write Master Start Address 286 | 24'h08001B: cache_register[3] <= cache_host_datain; // Length in Bytes 287 | 24'h08001C: cache_register[4] <= cache_host_datain; // Reserved 288 | 24'h08001D: cache_register[5] <= cache_host_datain; // Reserved 289 | 24'h08001E: cache_register[6] <= cache_host_datain; // Control 290 | 24'h08001F: cache_register[7] <= cache_host_datain; // Reserved 291 | endcase 292 | end 293 | else 294 | if(cache_host_cmd == 3'b001) // Read from Cache internal Registers to Host 295 | begin 296 | case (cache_host_addr) 297 | 298 | 24'h080018: cache_host_dataout <= cache_register[0]; 299 | 24'h080019: cache_host_dataout <= cache_register[1]; 300 | 24'h08001A: cache_host_dataout <= cache_register[2]; 301 | 24'h08001B: cache_host_dataout <= cache_register[3]; 302 | 24'h08001C: cache_host_dataout <= cache_register[4]; 303 | 24'h08001D: cache_host_dataout <= cache_register[5]; 304 | 24'h08001E: cache_host_dataout <= cache_register[6]; 305 | 24'h08001F: cache_host_dataout <= cache_register[7]; 306 | endcase 307 | end 308 | end 309 | end 310 | 311 | 312 | always @(posedge reset or posedge clk0) 313 | begin 314 | if(reset == 1'b1) 315 | begin 316 | cache_addr <= 24'h0; 317 | cache_cmd <= 3'h0; 318 | end 319 | else 320 | begin 321 | cache_addr <= cache_bus_grant & cache_host_addr; 322 | cache_cmd <= cache_bus_grant & cache_host_cmd; 323 | end 324 | end 325 | 326 | endmodule 327 | -------------------------------------------------------------------------------- /Verilog/soc.v: -------------------------------------------------------------------------------- 1 | /********************************************************* 2 | MODULE: Top Level System On A Chip Design 3 | 4 | FILE NAME: soc.v 5 | DATE: May 7th, 2002 6 | AUTHOR: Hossein Amidi 7 | COMPANY: 8 | CODE TYPE: Register Transfer Level 9 | 10 | DESCRIPTION: This module is the top level RTL code of System On a Chip Verilog code. 11 | It will instantiate the following blocks in the ASIC: 12 | 13 | 1) Vertex STARTUP 14 | 2) DLL 15 | 3) RISC uProcessor 16 | 4) DMA Cntrl 17 | 5) LRU Data Cache 18 | 6) LRU Instruction Cache 19 | 7) Bus Arbiter 20 | 8) UART 21 | 9) Timer 22 | 10) Flash Controller 23 | 11) SDRAM Controller 24 | 25 | Hossein Amidi 26 | (C) May 2002 27 | 28 | *********************************************************/ 29 | 30 | // DEFINES 31 | `timescale 1ns / 10ps 32 | 33 | // TOP MODULE 34 | module soc( // Inputs 35 | clk, 36 | reset, 37 | irq, 38 | ser_rxd, 39 | flash_datain, 40 | mem_datain, 41 | // Outputs 42 | pll_lock, 43 | addr, 44 | cs, 45 | ras, 46 | cas, 47 | we, 48 | dqm, 49 | cke, 50 | ba, 51 | pllclk, 52 | halted, 53 | ser_txd, 54 | flash_cle, 55 | flash_ale, 56 | flash_ce, 57 | flash_re, 58 | flash_we, 59 | flash_wp, 60 | flash_rb, 61 | flash_irq, 62 | flash_dataout, 63 | mem_dataout, 64 | mem_addr, 65 | mem_req, 66 | mem_rdwr, 67 | // Inouts 68 | dq 69 | ); 70 | 71 | // Parameter 72 | `include "parameter.v" 73 | 74 | 75 | // Inputs 76 | input clk; 77 | input reset; 78 | input irq; 79 | input ser_rxd; 80 | input [flash_size - 1 : 0]flash_datain; 81 | input [data_size - 1 : 0]mem_datain; 82 | 83 | // Outputs 84 | output pll_lock; 85 | output [add_size - 1 : 0]addr; 86 | output [cs_size - 1 : 0]cs; 87 | output ras; 88 | output cas; 89 | output we; 90 | output [dqm_size - 1 : 0]dqm; 91 | output cke; 92 | output [ba_size - 1 : 0]ba; 93 | output pllclk; 94 | output halted; 95 | output ser_txd; 96 | output flash_cle; 97 | output flash_ale; 98 | output flash_ce; 99 | output flash_re; 100 | output flash_we; 101 | output flash_wp; 102 | output flash_rb; 103 | output flash_irq; 104 | output [flash_size - 1 : 0]flash_dataout; 105 | output [data_size -1 : 0]mem_dataout; 106 | output [padd_size - 1 : 0]mem_addr; 107 | output mem_req; 108 | output mem_rdwr; 109 | 110 | // Inouts 111 | inout [data_size - 1 : 0]dq; 112 | 113 | 114 | // Signal Declarations 115 | wire clk; 116 | wire reset; 117 | wire irq; 118 | wire [add_size - 1 : 0]addr; 119 | wire [cs_size - 1 : 0]cs; 120 | wire ras; 121 | wire cas; 122 | wire we; 123 | wire [dqm_size - 1 : 0]dqm; 124 | wire cke; 125 | wire [ba_size - 1 : 0]ba; 126 | wire pllclk; 127 | wire halted; 128 | wire [data_size - 1 : 0]dq; 129 | 130 | wire system_irq; 131 | 132 | // RISC Signal Declarations 133 | wire [irq_size - 1 : 0]interrupt; 134 | wire cmdack; 135 | wire [arbiter_bus_size - 1 : 0]bus_grant; 136 | wire [data_size - 1 : 0]dcache_host_datain; 137 | wire [data_size - 1 : 0]icache_host_datain; 138 | wire dcache_hit; 139 | wire dcache_miss; 140 | wire icache_hit; 141 | wire icache_miss; 142 | wire [data_size - 1 : 0]dma_host_datain; 143 | wire [padd_size - 1 : 0]host_addr; 144 | wire [cmd_size - 1 : 0]host_cmd; 145 | wire [dqm_size - 1 : 0]host_dm; 146 | wire [arbiter_bus_size - 1 : 0]bus_request; 147 | wire dcache_request; 148 | wire icache_request; 149 | wire [data_size - 1 : 0]dma_host_dataout; 150 | wire [data_size - 1 : 0]dcache_host_dataout; 151 | wire [data_size - 1 : 0]icache_host_dataout; 152 | 153 | // DMA Signal Declarations 154 | wire [fifo_size - 1 : 0]dma_rd_datain; 155 | wire [fifo_size - 1 : 0]dma_wr_datain; 156 | wire dma_irq; 157 | wire [padd_size - 1 : 0]dma_rd_addr; 158 | wire [padd_size - 1 : 0]dma_wr_addr; 159 | wire [cmd_size - 1 : 0]dma_rd_cmd; 160 | wire [fifo_size - 1 : 0]dma_wr_dataout; 161 | wire [fifo_size - 1 : 0]dma_rd_dataout; 162 | wire dma_busy; 163 | 164 | 165 | // LRU Data Cache Signal Declarations 166 | wire [data_size - 1 : 0]dcache_datain; 167 | wire [padd_size - 1 : 0]dcache_addr; 168 | wire [cmd_size - 1 : 0]dcache_cmd; 169 | wire [data_size - 1 : 0]dcache_dataout; 170 | wire [padd_size - 1 : 0]sdram_addr; 171 | wire [cmd_size - 1 : 0]sdram_cmd; 172 | 173 | 174 | // LRU Instruction Cache Signal Declarations 175 | wire [data_size - 1 : 0]icache_datain; 176 | wire [padd_size - 1 : 0]icache_addr; 177 | wire [cmd_size - 1 : 0]icache_cmd; 178 | wire [data_size - 1 : 0]icache_dataout; 179 | 180 | 181 | // Bus Arbiter Signal Declarations 182 | wire [data_size - 1 : 0]sdram_datain; 183 | wire [data_size - 1 : 0]sdram_dataout; 184 | 185 | 186 | // SDRAM Controller Signal Declarations 187 | 188 | 189 | // UART Signal Declarations 190 | wire uart_cs; 191 | wire uart_rd; 192 | wire uart_wr; 193 | wire ser_rxd; 194 | wire ser_txd; 195 | wire [data_size - 1 : 0]uart_host_datain; 196 | wire [data_size - 1 : 0]uart_host_dataout; 197 | 198 | // Timer Signal Declarations 199 | wire [data_size - 1 : 0]timer_host_datain; 200 | wire timer_irq; 201 | wire [data_size - 1 : 0]timer_host_dataout; 202 | 203 | 204 | // Flash Controller Signal Decelaration 205 | wire [data_size - 1 : 0]flash_host_dataout; 206 | wire [flash_size - 1 : 0]flash_datain; 207 | wire [data_size - 1 : 0]flash_host_datain; 208 | wire flash_cle; 209 | wire flash_ale; 210 | wire flash_ce; 211 | wire flash_re; 212 | wire flash_we; 213 | wire flash_wp; 214 | wire flash_rb; 215 | wire flash_irq; 216 | wire [flash_size - 1 : 0]flash_dataout; 217 | 218 | 219 | // Memory 220 | wire [data_size - 1 :0]mem_dataout; 221 | wire [data_size - 1 :0]mem_datain; 222 | wire mem_req; 223 | wire mem_rdwr; 224 | wire [padd_size - 1 : 0]mem_addr; 225 | 226 | assign mem_addr = host_addr; 227 | 228 | 229 | 230 | 231 | // Assignment statments 232 | assign system_irq = irq; 233 | assign interrupt = {timer_irq,dma_irq,system_irq}; 234 | 235 | /*--------------------------- Module Instantiation ----------------------------*/ 236 | 237 | STARTUP_VIRTEX u22 (.GSR(reset)); 238 | 239 | /*--------------------------- DLL Instantiation Block ----------------------------*/ 240 | wire CLKIN_w; 241 | wire clk0; 242 | 243 | wire CLK0_dll, CLK90_dll, CLK180_dll, CLK2X_dll, CLKDV2_dll; 244 | wire clk0_90, clk0_180, clk0_2x, clk0_dv2; 245 | wire pll_lock; 246 | 247 | IBUFG clkpad (.I(clk), .O(CLKIN_w)); 248 | 249 | CLKDLL dll_0 (.CLKIN(CLKIN_w), .CLKFB(clk0), .RST(reset), 250 | .CLK0(CLK0_dll), .CLK90(CLK90_dll), .CLK180(CLK180_dll), .CLK270(), 251 | .CLK2X(CLK2X_dll), .CLKDV(CLKDV2_dll), .LOCKED(pll_lock)); 252 | 253 | BUFG u1 (.I(CLK0_dll), .O(clk0)); 254 | BUFG u2 (.I(CLK180_dll), .O(clk0_180)); 255 | BUFG u3 (.I(CLK2X_dll), .O(clk0_2x)); 256 | 257 | 258 | 259 | //assign pllclk = clk0_180; 260 | 261 | assign pllclk = clk0; 262 | 263 | /****************************** Sub Level Block Instantiation ****************************/ 264 | 265 | risc uProcessor0( // Input 266 | .reset(reset), 267 | .clk0(clk0), 268 | .pll_lock(pll_lock), 269 | .interrupt(interrupt), 270 | .cmdack(cmdack), 271 | .dcache_datain(dcache_host_datain), 272 | .dcache_hit(dcache_hit), 273 | .dcache_miss(dcache_miss), 274 | .icache_datain(icache_host_datain), 275 | .icache_hit(icache_hit), 276 | .icache_miss(icache_miss), 277 | .dma_datain(dma_host_datain), 278 | .dma_busy(dma_busy), 279 | .timer_host_datain(timer_host_datain), 280 | .flash_host_datain(flash_host_datain), 281 | .uart_host_datain(uart_host_datain), 282 | .mem_datain(mem_datain), 283 | // Output 284 | .paddr(host_addr), 285 | .cmd(host_cmd), 286 | .dm(host_dm), 287 | .dcache_request(dcache_request), 288 | .icache_request(icache_request), 289 | .dma_dataout(dma_host_dataout), 290 | .dcache_dataout(dcache_host_dataout), 291 | .icache_dataout(icache_host_dataout), 292 | .timer_host_dataout(timer_host_dataout), 293 | .flash_host_dataout(flash_host_dataout), 294 | .uart_host_dataout(uart_host_dataout), 295 | .mem_dataout(mem_dataout), 296 | .mem_req(mem_req), 297 | .mem_rdwr(mem_rdwr), 298 | .halted(halted) 299 | ); 300 | 301 | 302 | dma_cntrl dma_cntrl0(// Input 303 | .reset(reset), 304 | .clk0(clk0), 305 | .dma_host_addr(host_addr), 306 | .dma_host_cmd(host_cmd), 307 | .dma_host_datain(dma_host_dataout), 308 | .dma_bus_grant(bus_grant[2]), 309 | .dma_rd_datain(dma_rd_datain), 310 | .dma_wr_datain(dma_wr_datain), 311 | // Output 312 | .dma_host_dataout(dma_host_datain), 313 | .dma_irq(dma_irq), 314 | .dma_bus_req(bus_request[2]), 315 | .dma_rd_addr(dma_rd_addr), 316 | .dma_wr_addr(dma_wr_addr), 317 | .dma_wr_dataout(dma_wr_dataout), 318 | .dma_rd_cmd(dma_rd_cmd), 319 | .dma_busy(dma_busy), 320 | .uart_cs(uart_cs), 321 | .uart_rd(uart_rd), 322 | .uart_wr(uart_wr), 323 | .dma_rd_dataout(dma_rd_dataout) 324 | ); 325 | 326 | 327 | 328 | lru_data_cache lru_data_cache0(// Input 329 | .reset(reset), 330 | .clk0(clk0), 331 | .cache_host_addr(host_addr), 332 | .cache_host_cmd(host_cmd), 333 | .cache_request(dcache_request), 334 | .cache_host_datain(dcache_host_dataout), 335 | .cache_bus_grant(bus_grant[0]), 336 | .cache_datain(dcache_datain), 337 | // Output 338 | .cache_host_dataout(dcache_host_datain), 339 | .cache_hit(dcache_hit), 340 | .cache_miss(dcache_miss), 341 | .cache_bus_request(bus_request[0]), 342 | .cache_addr(dcache_addr), 343 | .cache_cmd(dcache_cmd), 344 | .cache_dataout(dcache_dataout) 345 | ); 346 | 347 | 348 | lru_instruction_cache lru_inst_cache0(// Input 349 | .reset(reset), 350 | .clk0(clk0), 351 | .cache_host_addr(host_addr), 352 | .cache_host_cmd(host_cmd), 353 | .cache_request(icache_request), 354 | .cache_host_datain(icache_host_dataout), 355 | .cache_bus_grant(bus_grant[1]), 356 | .cache_datain(icache_datain), 357 | // Output 358 | .cache_host_dataout(icache_host_datain), 359 | .cache_hit(icache_hit), 360 | .cache_miss(icache_miss), 361 | .cache_bus_request(bus_request[1]), 362 | .cache_addr(icache_addr), 363 | .cache_cmd(icache_cmd), 364 | .cache_dataout(icache_dataout) 365 | ); 366 | 367 | 368 | bus_arbiter bus_arbiter0( // Input 369 | .reset(reset), 370 | .clk0(clk0), 371 | .bus_request(bus_request), 372 | .dma_dataout(dma_wr_dataout), 373 | .dma_addr(dma_rd_addr), 374 | .dma_cmd(dma_rd_cmd), 375 | .dcache_dataout(dcache_dataout), 376 | .dcache_addr(dcache_addr), 377 | .dcache_cmd(dcache_cmd), 378 | .icache_dataout(icache_dataout), 379 | .icache_addr(icache_addr), 380 | .icache_cmd(icache_cmd), 381 | .sdram_dataout(sdram_dataout), 382 | // Output 383 | .bus_grant(bus_grant), 384 | .dma_datain(dma_wr_datain), 385 | .dcache_datain(dcache_datain), 386 | .icache_datain(icache_datain), 387 | .sdram_addr(sdram_addr), 388 | .sdram_cmd(sdram_cmd), 389 | .sdram_datain(sdram_datain) 390 | ); 391 | 392 | 393 | uart uart0(// Input 394 | .reset(reset), 395 | .clk0(clk0), 396 | .uart_addr(dma_wr_addr), 397 | .uart_host_addr(host_addr), 398 | .uart_host_cmd(host_cmd), 399 | .uart_cmd(dma_rd_cmd), 400 | .uart_host_datain(uart_host_dataout), 401 | .uart_cs(uart_cs), 402 | .uart_rd(uart_rd), 403 | .uart_wr(uart_wr), 404 | .ser_rxd(ser_rxd), 405 | .uart_datain(dma_rd_dataout), 406 | // Output 407 | .ser_txd(ser_txd), 408 | .uart_host_dataout(uart_host_datain), 409 | .uart_dataout(dma_rd_datain) 410 | ); 411 | 412 | 413 | timer timer0( // Input 414 | .reset(reset), 415 | .clk0(clk0), 416 | .timer_host_datain(timer_host_dataout), 417 | .timer_cmd(host_cmd), 418 | .timer_addr(host_addr), 419 | // Output 420 | .timer_host_dataout(timer_host_datain), 421 | .timer_irq(timer_irq) 422 | ); 423 | 424 | 425 | flash_ctrl flash_ctrl0(// Inputs 426 | .reset(reset), 427 | .clk0(clk0), 428 | .flash_host_addr(host_addr), 429 | .flash_host_cmd(host_cmd), 430 | .flash_host_dataout(flash_host_dataout), 431 | .flash_datain(flash_datain), 432 | // Outputs 433 | .flash_host_datain(flash_host_datain), 434 | .flash_cle(flash_cle), 435 | .flash_ale(flash_ale), 436 | .flash_ce(flash_ce), 437 | .flash_re(flash_re), 438 | .flash_we(flash_we), 439 | .flash_wp(flash_wp), 440 | .flash_rb(flash_rb), 441 | .flash_irq(flash_irq), 442 | .flash_dataout(flash_dataout) 443 | ); 444 | 445 | 446 | 447 | sdram_ctrl sdram_ctrl0(// Inputs 448 | .clk0(clk0), 449 | .clk0_2x(clk0_2x), 450 | .reset(reset), 451 | .paddr(sdram_addr), 452 | .cmd(sdram_cmd), 453 | .dm(host_dm), 454 | .datain(sdram_datain), 455 | // Outputs 456 | .cmdack(cmdack), 457 | .addr(addr), 458 | .cs(cs), 459 | .ras(ras), 460 | .cas(cas), 461 | .we(we), 462 | .dqm(dqm), 463 | .cke(cke), 464 | .ba(ba), 465 | .dataout(sdram_dataout), 466 | // Inouts 467 | .dq(dq) 468 | ); 469 | 470 | endmodule 471 | -------------------------------------------------------------------------------- /Verilog/CONTROL.V: -------------------------------------------------------------------------------- 1 | /**************************************************************************************** 2 | MODULE: Sub Level Controller Block 3 | 4 | FILE NAME: control.v 5 | VERSION: 1.0 6 | DATE: September 28th, 2001 7 | AUTHOR: Hossein Amidi 8 | COMPANY: California Unique Electrical Co. 9 | CODE TYPE: Register Transfer Level 10 | 11 | Instantiations: 12 | 13 | DESCRIPTION: 14 | Sub Level RTL Controller block 15 | 16 | Hossein Amidi 17 | (C) September 2001 18 | California Unique Electric 19 | 20 | ***************************************************************************************/ 21 | 22 | `timescale 1ns / 1ps 23 | 24 | module CNTRL ( // Input 25 | clock, 26 | reset, 27 | OpCode, 28 | ACCNeg, 29 | ACCZero, 30 | Grant, 31 | // Ouptut 32 | NextState, 33 | PCInEn, 34 | IRInEn, 35 | ACCInEn, 36 | ACCOutEn, 37 | MemReq, 38 | RdWrBar, 39 | AddressSel, 40 | ALUSrcBSel 41 | ); 42 | 43 | 44 | // Parameter 45 | parameter OpcodeSize = 8; 46 | parameter StateSize = 2; 47 | parameter Low = 1'b0; 48 | parameter High = 1'b1; 49 | parameter SelInstrAddr = 1'b0; 50 | parameter SelOperandAddr = 1'b1; 51 | parameter SelAddress = 1'b0; 52 | parameter SelData = 1'b1; 53 | 54 | // Instructions options 55 | parameter LDA = 8'h0; 56 | parameter STO = 8'h1; 57 | parameter ADD = 8'h2; 58 | parameter SUB = 8'h3; 59 | parameter JMP = 8'h4; 60 | parameter JGE = 8'h5; 61 | parameter JNE = 8'h6; 62 | parameter STP = 8'h7; 63 | parameter SHR = 8'h8; 64 | parameter SHL = 8'h9; 65 | parameter AND = 8'ha; 66 | parameter OR = 8'hb; 67 | parameter XOR = 8'hc; 68 | parameter COM = 8'hd; 69 | parameter SWP = 8'he; 70 | parameter NOP = 8'hf; 71 | 72 | // Instruction for Memory Map devices 73 | parameter MAP = 8'h64; 74 | 75 | 76 | // Current State options 77 | parameter Init = 2'b00; 78 | parameter InstrFetch = 2'b01; 79 | parameter InstrExec = 2'b10; 80 | parameter InstrStop = 2'b11; 81 | 82 | 83 | // Input 84 | input clock; 85 | input reset; 86 | input [OpcodeSize - 1 : 0] OpCode; 87 | input ACCNeg; 88 | input ACCZero; 89 | input Grant; 90 | 91 | // Output 92 | output [StateSize - 1 : 0] NextState; 93 | output PCInEn; 94 | output IRInEn; 95 | output ACCInEn; 96 | output ACCOutEn; 97 | output MemReq; 98 | output RdWrBar; 99 | output AddressSel; 100 | output ALUSrcBSel; 101 | 102 | // Signal Declerations 103 | reg PCInEn; 104 | reg IRInEn; 105 | reg ACCInEn; 106 | reg ACCOutEn; 107 | reg MemReq; 108 | reg RdWrBar; 109 | reg AddressSel; 110 | reg ALUSrcBSel; 111 | wire [StateSize - 1 : 0] NextState; 112 | 113 | 114 | reg [1:0]state; 115 | // Assignments 116 | assign NextState = state; 117 | 118 | // Finite State Machine's Sequential Section 119 | always @(posedge reset or negedge clock) 120 | begin 121 | if(reset == 1'b1) 122 | begin 123 | state <= Init; 124 | end 125 | else 126 | begin // Grant = 1 -bit, opcode = 8-bit, state = 2-bit 127 | casex ({Grant,OpCode,state}) 128 | 11'b0_xxxxxxxx_00: state <= Init; 129 | 11'b1_00000000_00: state <= InstrFetch; 130 | 11'b1_00000000_01: state <= InstrExec; 131 | 11'b1_00000001_01: state <= InstrExec; 132 | 11'b1_00000010_01: state <= InstrExec; 133 | 11'b1_00000011_01: state <= InstrExec; 134 | 11'b1_00000100_01: state <= InstrExec; 135 | 11'b1_00000101_01: state <= InstrExec; 136 | 11'b1_00000110_01: state <= InstrExec; 137 | 11'b1_00000111_01: state <= InstrExec; 138 | 11'b1_00001000_01: state <= InstrExec; 139 | 11'b1_00001001_01: state <= InstrExec; 140 | 11'b1_00001010_01: state <= InstrExec; 141 | 11'b1_00001011_01: state <= InstrExec; 142 | 11'b1_00001100_01: state <= InstrExec; 143 | 11'b1_00001101_01: state <= InstrExec; 144 | 11'b1_00001110_01: state <= InstrExec; 145 | 11'b1_00001111_01: state <= InstrExec; 146 | 11'b1_00010000_01: state <= InstrExec; 147 | 11'b1_00010001_01: state <= InstrExec; 148 | 11'b1_00010010_01: state <= InstrExec; 149 | 11'b1_00010011_01: state <= InstrExec; 150 | 11'b1_00010100_01: state <= InstrExec; 151 | 11'b1_00010101_01: state <= InstrExec; 152 | 11'b1_00010110_01: state <= InstrExec; 153 | 11'b1_00010111_01: state <= InstrExec; 154 | 11'b1_00011000_01: state <= InstrExec; 155 | 11'b1_00011001_01: state <= InstrExec; 156 | 11'b1_00011010_01: state <= InstrExec; 157 | 11'b1_00011011_01: state <= InstrExec; 158 | 11'b1_00011100_01: state <= InstrExec; 159 | 11'b1_00011101_01: state <= InstrExec; 160 | 11'b1_00011110_01: state <= InstrExec; 161 | 11'b1_00011111_01: state <= InstrExec; 162 | 11'b1_00100000_01: state <= InstrExec; 163 | 11'b1_00100001_01: state <= InstrExec; 164 | 11'b1_00100010_01: state <= InstrExec; 165 | 11'b1_00100011_01: state <= InstrExec; 166 | 11'b1_00100100_01: state <= InstrExec; 167 | 11'b1_00100101_01: state <= InstrExec; 168 | 11'b1_00100110_01: state <= InstrExec; 169 | 11'b1_00100111_01: state <= InstrExec; 170 | 11'b1_00101000_01: state <= InstrExec; 171 | 11'b1_00101001_01: state <= InstrExec; 172 | 11'b1_00101010_01: state <= InstrExec; 173 | 11'b1_00101011_01: state <= InstrExec; 174 | 11'b1_00101100_01: state <= InstrExec; 175 | 11'b1_00101101_01: state <= InstrExec; 176 | 11'b1_00101110_01: state <= InstrExec; 177 | 11'b1_00101111_01: state <= InstrExec; 178 | 11'b1_00110000_01: state <= InstrExec; 179 | 11'b1_00110001_01: state <= InstrExec; 180 | 11'b1_00110010_01: state <= InstrExec; 181 | 11'b1_00110011_01: state <= InstrExec; 182 | 11'b1_00110100_01: state <= InstrExec; 183 | 11'b1_00110101_01: state <= InstrExec; 184 | 11'b1_00110110_01: state <= InstrExec; 185 | 11'b1_00110111_01: state <= InstrExec; 186 | 11'b1_00111000_01: state <= InstrExec; 187 | 11'b1_00111001_01: state <= InstrExec; 188 | 11'b1_00111010_01: state <= InstrExec; 189 | 11'b1_00111011_01: state <= InstrExec; 190 | 11'b1_00111100_01: state <= InstrExec; 191 | 11'b1_00111101_01: state <= InstrExec; 192 | 11'b1_00111110_01: state <= InstrExec; 193 | 11'b1_00111111_01: state <= InstrExec; 194 | 11'b1_01000000_01: state <= InstrExec; 195 | 11'b1_01000001_01: state <= InstrExec; 196 | 11'b1_01000010_01: state <= InstrExec; 197 | 11'b1_01000011_01: state <= InstrExec; 198 | 11'b1_01000100_01: state <= InstrExec; 199 | 11'b1_01000101_01: state <= InstrExec; 200 | 11'b1_01000110_01: state <= InstrExec; 201 | 11'b1_01000111_01: state <= InstrExec; 202 | 11'b1_01001000_01: state <= InstrExec; 203 | 11'b1_01001001_01: state <= InstrExec; 204 | 11'b1_01001010_01: state <= InstrExec; 205 | 11'b1_01001011_01: state <= InstrExec; 206 | 11'b1_01001100_01: state <= InstrExec; 207 | 11'b1_01001101_01: state <= InstrExec; 208 | 11'b1_01001110_01: state <= InstrExec; 209 | 11'b1_01001111_01: state <= InstrExec; 210 | 11'b1_01010000_01: state <= InstrExec; 211 | 11'b1_01010001_01: state <= InstrExec; 212 | 11'b1_01010010_01: state <= InstrExec; 213 | 11'b1_01010011_01: state <= InstrExec; 214 | 11'b1_01010100_01: state <= InstrExec; 215 | 11'b1_01010101_01: state <= InstrExec; 216 | 11'b1_01010110_01: state <= InstrExec; 217 | 11'b1_01010111_01: state <= InstrExec; 218 | 11'b1_01011000_01: state <= InstrExec; 219 | 11'b1_01011001_01: state <= InstrExec; 220 | 11'b1_01011010_01: state <= InstrExec; 221 | 11'b1_01011011_01: state <= InstrExec; 222 | 11'b1_01011100_01: state <= InstrExec; 223 | 11'b1_01011101_01: state <= InstrExec; 224 | 11'b1_01011110_01: state <= InstrExec; 225 | 11'b1_01011111_01: state <= InstrExec; 226 | 11'b1_01100000_01: state <= InstrExec; 227 | 11'b1_01100001_01: state <= InstrExec; 228 | 11'b1_01100010_01: state <= InstrExec; 229 | 11'b1_01100011_01: state <= InstrExec; 230 | 11'b1_01100100_01: state <= InstrExec; 231 | 11'b1_01100101_01: state <= InstrExec; 232 | 11'b1_01100110_01: state <= InstrExec; 233 | 11'b1_01100111_01: state <= InstrExec; 234 | 11'b1_01101000_01: state <= InstrExec; 235 | 11'b1_01101001_01: state <= InstrExec; 236 | 11'b1_01101010_01: state <= InstrExec; 237 | 11'b1_01101011_01: state <= InstrExec; 238 | 11'b1_01101100_01: state <= InstrExec; 239 | 11'b1_01101101_01: state <= InstrExec; 240 | 11'b1_01101110_01: state <= InstrExec; 241 | 11'b1_01101111_01: state <= InstrExec; 242 | 11'b1_01110000_01: state <= InstrExec; 243 | 11'b1_01110001_01: state <= InstrExec; 244 | 11'b1_01110010_01: state <= InstrExec; 245 | 11'b1_01110011_01: state <= InstrExec; 246 | 11'b1_01110100_01: state <= InstrExec; 247 | 11'b1_01110101_01: state <= InstrExec; 248 | 11'b1_01110110_01: state <= InstrExec; 249 | 11'b1_01110111_01: state <= InstrExec; 250 | 11'b1_01111000_01: state <= InstrExec; 251 | 11'b1_01111001_01: state <= InstrExec; 252 | 11'b1_01111010_01: state <= InstrExec; 253 | 11'b1_01111011_01: state <= InstrExec; 254 | 11'b1_01111100_01: state <= InstrExec; 255 | 11'b1_01111101_01: state <= InstrExec; 256 | 11'b1_01111110_01: state <= InstrExec; 257 | 11'b1_01111111_01: state <= InstrExec; 258 | 11'b1_10000000_01: state <= InstrExec; 259 | 11'b1_10000001_01: state <= InstrExec; 260 | 11'b1_10000010_01: state <= InstrExec; 261 | 11'b1_10000011_01: state <= InstrExec; 262 | 11'b1_10000100_01: state <= InstrExec; 263 | 11'b1_10000101_01: state <= InstrExec; 264 | 11'b1_10000110_01: state <= InstrExec; 265 | 11'b1_10000111_01: state <= InstrExec; 266 | 11'b1_10001000_01: state <= InstrExec; 267 | 11'b1_10001001_01: state <= InstrExec; 268 | 11'b1_10001010_01: state <= InstrExec; 269 | 11'b1_10001011_01: state <= InstrExec; 270 | 11'b1_10001100_01: state <= InstrExec; 271 | 11'b1_10001101_01: state <= InstrExec; 272 | 11'b1_10001110_01: state <= InstrExec; 273 | 11'b1_10001111_01: state <= InstrExec; 274 | 11'b1_10010000_01: state <= InstrExec; 275 | 11'b1_10010001_01: state <= InstrExec; 276 | 11'b1_10010010_01: state <= InstrExec; 277 | 11'b1_10010011_01: state <= InstrExec; 278 | 11'b1_10010100_01: state <= InstrExec; 279 | 11'b1_10010101_01: state <= InstrExec; 280 | 11'b1_10010110_01: state <= InstrExec; 281 | 11'b1_10010111_01: state <= InstrExec; 282 | 11'b1_10011000_01: state <= InstrExec; 283 | 11'b1_10011001_01: state <= InstrExec; 284 | 11'b1_10011010_01: state <= InstrExec; 285 | 11'b1_10011011_01: state <= InstrExec; 286 | 11'b1_10011100_01: state <= InstrExec; 287 | 11'b1_10011101_01: state <= InstrExec; 288 | 11'b1_10011110_01: state <= InstrExec; 289 | 11'b1_10011111_01: state <= InstrExec; 290 | 11'b1_10100000_01: state <= InstrExec; 291 | 11'b1_10100001_01: state <= InstrExec; 292 | 11'b1_10100010_01: state <= InstrExec; 293 | 11'b1_10100011_01: state <= InstrExec; 294 | 11'b1_10100100_01: state <= InstrExec; 295 | 11'b1_10100101_01: state <= InstrExec; 296 | 11'b1_10100110_01: state <= InstrExec; 297 | 11'b1_10100111_01: state <= InstrExec; 298 | 11'b1_10101000_01: state <= InstrExec; 299 | 11'b1_10101001_01: state <= InstrExec; 300 | 11'b1_10101010_01: state <= InstrExec; 301 | 11'b1_10101011_01: state <= InstrExec; 302 | 11'b1_10101100_01: state <= InstrExec; 303 | 11'b1_10101101_01: state <= InstrExec; 304 | 11'b1_10101110_01: state <= InstrExec; 305 | 11'b1_10101111_01: state <= InstrExec; 306 | 11'b1_10110000_01: state <= InstrExec; 307 | 11'b1_10110001_01: state <= InstrExec; 308 | 11'b1_10110010_01: state <= InstrExec; 309 | 11'b1_10110011_01: state <= InstrExec; 310 | 11'b1_10110100_01: state <= InstrExec; 311 | 11'b1_10110101_01: state <= InstrExec; 312 | 11'b1_10110110_01: state <= InstrExec; 313 | 11'b1_10110111_01: state <= InstrExec; 314 | 11'b1_10111000_01: state <= InstrExec; 315 | 11'b1_10111001_01: state <= InstrExec; 316 | 11'b1_10111010_01: state <= InstrExec; 317 | 11'b1_10111011_01: state <= InstrExec; 318 | 11'b1_10111100_01: state <= InstrExec; 319 | 11'b1_10111101_01: state <= InstrExec; 320 | 11'b1_10111110_01: state <= InstrExec; 321 | 11'b1_10111111_01: state <= InstrExec; 322 | 11'b1_11000000_01: state <= InstrExec; 323 | 11'b1_11000001_01: state <= InstrExec; 324 | 11'b1_11000010_01: state <= InstrExec; 325 | 11'b1_11000011_01: state <= InstrExec; 326 | 11'b1_11000100_01: state <= InstrExec; 327 | 11'b1_11000101_01: state <= InstrExec; 328 | 11'b1_11000110_01: state <= InstrExec; 329 | 11'b1_11000111_01: state <= InstrExec; 330 | 11'b1_11001000_01: state <= InstrExec; 331 | 11'b1_11001001_01: state <= InstrExec; 332 | 11'b1_11001010_01: state <= InstrExec; 333 | 11'b1_11001011_01: state <= InstrExec; 334 | 11'b1_11001100_01: state <= InstrExec; 335 | 11'b1_11001101_01: state <= InstrExec; 336 | 11'b1_11001110_01: state <= InstrExec; 337 | 11'b1_11001111_01: state <= InstrExec; 338 | 11'b1_11010000_01: state <= InstrExec; 339 | 11'b1_11010001_01: state <= InstrExec; 340 | 11'b1_11010010_01: state <= InstrExec; 341 | 11'b1_11010011_01: state <= InstrExec; 342 | 11'b1_11010100_01: state <= InstrExec; 343 | 11'b1_11010101_01: state <= InstrExec; 344 | 11'b1_11010110_01: state <= InstrExec; 345 | 11'b1_11010111_01: state <= InstrExec; 346 | 11'b1_11011000_01: state <= InstrExec; 347 | 11'b1_11011001_01: state <= InstrExec; 348 | 11'b1_11011010_01: state <= InstrExec; 349 | 11'b1_11011011_01: state <= InstrExec; 350 | 11'b1_11011100_01: state <= InstrExec; 351 | 11'b1_11011101_01: state <= InstrExec; 352 | 11'b1_11011110_01: state <= InstrExec; 353 | 11'b1_11011111_01: state <= InstrExec; 354 | 11'b1_11100000_01: state <= InstrExec; 355 | 11'b1_11100001_01: state <= InstrExec; 356 | 11'b1_11100010_01: state <= InstrExec; 357 | 11'b1_11100011_01: state <= InstrExec; 358 | 11'b1_11100100_01: state <= InstrExec; 359 | 11'b1_11100101_01: state <= InstrExec; 360 | 11'b1_11100110_01: state <= InstrExec; 361 | 11'b1_11100111_01: state <= InstrExec; 362 | 11'b1_11101000_01: state <= InstrExec; 363 | 11'b1_11101001_01: state <= InstrExec; 364 | 11'b1_11101010_01: state <= InstrExec; 365 | 11'b1_11101011_01: state <= InstrExec; 366 | 11'b1_11101100_01: state <= InstrExec; 367 | 11'b1_11101101_01: state <= InstrExec; 368 | 11'b1_11101110_01: state <= InstrExec; 369 | 11'b1_11101111_01: state <= InstrExec; 370 | 11'b1_11110000_01: state <= InstrExec; 371 | 11'b1_11110001_01: state <= InstrExec; 372 | 11'b1_11110010_01: state <= InstrExec; 373 | 11'b1_11110011_01: state <= InstrExec; 374 | 11'b1_11110100_01: state <= InstrExec; 375 | 11'b1_11110101_01: state <= InstrExec; 376 | 11'b1_11110110_01: state <= InstrExec; 377 | 11'b1_11110111_01: state <= InstrExec; 378 | 11'b1_11111000_01: state <= InstrExec; 379 | 11'b1_11111001_01: state <= InstrExec; 380 | 11'b1_11111010_01: state <= InstrExec; 381 | 11'b1_11111011_01: state <= InstrExec; 382 | 11'b1_11111100_01: state <= InstrExec; 383 | 11'b1_11111101_01: state <= InstrExec; 384 | 11'b1_11111110_01: state <= InstrExec; 385 | 11'b1_11111111_01: state <= InstrExec; 386 | 11'b1_00000111_10: state <= InstrStop; 387 | 11'b1_xxxxxxxx_10: state <= InstrFetch; 388 | 11'b1_00000111_11: state <= Init; 389 | default: state <= Init; 390 | endcase 391 | end 392 | end 393 | 394 | 395 | // Finite State Machine's Combinatorial Section 396 | always @(reset or state or ACCNeg or ACCZero or OpCode) 397 | begin 398 | if (reset == 1'b1) 399 | begin 400 | PCInEn <= Low; 401 | IRInEn <= Low; 402 | ACCInEn <= Low; 403 | ACCOutEn <= Low; 404 | MemReq <= Low; 405 | RdWrBar <= Low; 406 | AddressSel <= Low; 407 | ALUSrcBSel <= Low; 408 | end 409 | else 410 | if (state == InstrFetch) 411 | begin 412 | PCInEn <= High; 413 | IRInEn <= High; 414 | ACCInEn <= Low; 415 | ACCOutEn <= Low; 416 | MemReq <= High; 417 | RdWrBar <= High; 418 | AddressSel <= SelInstrAddr; 419 | ALUSrcBSel <= SelAddress; 420 | end 421 | else 422 | if (state == InstrExec) 423 | begin 424 | case (OpCode) 425 | 426 | LDA: 427 | begin 428 | PCInEn <= Low; 429 | IRInEn <= Low; 430 | ACCInEn <= High; 431 | ACCOutEn <= Low; 432 | MemReq <= High; 433 | RdWrBar <= High; 434 | AddressSel <= SelOperandAddr; 435 | ALUSrcBSel <= SelData; 436 | end 437 | STO: 438 | begin 439 | PCInEn <= Low; 440 | IRInEn <= Low; 441 | ACCInEn <= Low; 442 | ACCOutEn <= High; 443 | MemReq <= High; 444 | RdWrBar <= Low; 445 | AddressSel <= SelOperandAddr; 446 | ALUSrcBSel <= SelAddress; 447 | end 448 | ADD: 449 | begin 450 | PCInEn <= Low; 451 | IRInEn <= Low; 452 | ACCInEn <= High; 453 | ACCOutEn <= Low; 454 | MemReq <= High; 455 | RdWrBar <= High; 456 | AddressSel <= SelOperandAddr; 457 | ALUSrcBSel <= SelData; 458 | end 459 | SUB: 460 | begin 461 | PCInEn <= Low; 462 | IRInEn <= Low; 463 | ACCInEn <= High; 464 | ACCOutEn <= Low; 465 | MemReq <= High; 466 | RdWrBar <= High; 467 | AddressSel <= SelOperandAddr; 468 | ALUSrcBSel <= SelData; 469 | end 470 | JMP: 471 | begin 472 | PCInEn <= High; 473 | IRInEn <= Low; 474 | ACCInEn <= Low; 475 | ACCOutEn <= Low; 476 | MemReq <= Low; 477 | RdWrBar <= High; 478 | AddressSel <= SelOperandAddr; 479 | ALUSrcBSel <= SelAddress; 480 | end 481 | JGE: 482 | begin 483 | PCInEn <= ~ACCNeg; 484 | IRInEn <= Low; 485 | ACCInEn <= Low; 486 | ACCOutEn <= Low; 487 | MemReq <= Low; 488 | RdWrBar <= High; 489 | AddressSel <= SelOperandAddr; 490 | ALUSrcBSel <= SelAddress; 491 | end 492 | JNE: 493 | begin 494 | PCInEn <= ~ACCZero; 495 | IRInEn <= Low; 496 | ACCInEn <= Low; 497 | ACCOutEn <= Low; 498 | MemReq <= Low; 499 | RdWrBar <= High; 500 | AddressSel <= SelOperandAddr; 501 | ALUSrcBSel <= SelAddress; 502 | end 503 | STP: 504 | begin 505 | PCInEn <= Low; 506 | IRInEn <= Low; 507 | ACCInEn <= Low; 508 | ACCOutEn <= Low; 509 | MemReq <= Low; 510 | RdWrBar <= High; 511 | AddressSel <= SelAddress; 512 | ALUSrcBSel <= SelAddress; 513 | end 514 | SHR: 515 | begin 516 | PCInEn <= Low; 517 | IRInEn <= Low; 518 | ACCInEn <= High; 519 | ACCOutEn <= Low; 520 | MemReq <= Low; 521 | RdWrBar <= Low; 522 | AddressSel <= SelOperandAddr; 523 | ALUSrcBSel <= SelAddress; 524 | end 525 | SHL: 526 | begin 527 | PCInEn <= Low; 528 | IRInEn <= Low; 529 | ACCInEn <= High; 530 | ACCOutEn <= Low; 531 | MemReq <= Low; 532 | RdWrBar <= Low; 533 | AddressSel <= SelOperandAddr; 534 | ALUSrcBSel <= SelAddress; 535 | end 536 | AND: 537 | begin 538 | PCInEn <= Low; 539 | IRInEn <= Low; 540 | ACCInEn <= High; 541 | ACCOutEn <= Low; 542 | MemReq <= High; 543 | RdWrBar <= High; 544 | AddressSel <= SelOperandAddr; 545 | ALUSrcBSel <= SelData; 546 | end 547 | OR: 548 | begin 549 | PCInEn <= Low; 550 | IRInEn <= Low; 551 | ACCInEn <= High; 552 | ACCOutEn <= Low; 553 | MemReq <= High; 554 | RdWrBar <= High; 555 | AddressSel <= SelOperandAddr; 556 | ALUSrcBSel <= SelData; 557 | end 558 | XOR: 559 | begin 560 | PCInEn <= Low; 561 | IRInEn <= Low; 562 | ACCInEn <= High; 563 | ACCOutEn <= Low; 564 | MemReq <= High; 565 | RdWrBar <= High; 566 | AddressSel <= SelOperandAddr; 567 | ALUSrcBSel <= SelData; 568 | end 569 | COM: 570 | begin 571 | PCInEn <= Low; 572 | IRInEn <= Low; 573 | ACCInEn <= High; 574 | ACCOutEn <= Low; 575 | MemReq <= High; 576 | RdWrBar <= High; 577 | AddressSel <= SelOperandAddr; 578 | ALUSrcBSel <= SelData; 579 | end 580 | SWP: 581 | begin 582 | PCInEn <= Low; 583 | IRInEn <= Low; 584 | ACCInEn <= High; 585 | ACCOutEn <= Low; 586 | MemReq <= High; 587 | RdWrBar <= High; 588 | AddressSel <= SelOperandAddr; 589 | ALUSrcBSel <= SelData; 590 | end 591 | NOP: 592 | begin 593 | PCInEn <= Low; 594 | IRInEn <= Low; 595 | ACCInEn <= Low; 596 | ACCOutEn <= Low; 597 | MemReq <= Low; 598 | RdWrBar <= High; 599 | AddressSel <= SelOperandAddr; 600 | ALUSrcBSel <= SelAddress; 601 | end 602 | default: 603 | begin 604 | PCInEn <= Low; 605 | IRInEn <= Low; 606 | ACCInEn <= Low; 607 | ACCOutEn <= Low; 608 | MemReq <= Low; 609 | RdWrBar <= High; 610 | AddressSel <= SelOperandAddr; 611 | ALUSrcBSel <= SelAddress; 612 | end 613 | endcase 614 | end 615 | else 616 | if (state == InstrStop) 617 | begin 618 | PCInEn <= Low; 619 | IRInEn <= Low; 620 | ACCInEn <= Low; 621 | ACCOutEn <= Low; 622 | MemReq <= Low; 623 | RdWrBar <= High; 624 | AddressSel <= SelAddress; 625 | ALUSrcBSel <= SelAddress; 626 | end 627 | end 628 | endmodule 629 | --------------------------------------------------------------------------------