├── EDK └── edk_user_repository.tar.gz ├── bench └── verilog │ ├── Phy_sim.v │ ├── User_int_sim.v │ ├── altera_mf.v │ ├── host_sim.v │ ├── reg_int_sim.v │ └── tb_top.v ├── doc ├── Tri-mode_Ethernet_MAC_Specifications.pdf └── Tri-mode_Ethernet_MAC_Verification_plan.pdf ├── rtl └── verilog │ ├── Clk_ctrl.v │ ├── MAC_rx.v │ ├── MAC_rx │ ├── Broadcast_filter.v │ ├── CRC_chk.v │ ├── MAC_rx_FF.v │ ├── MAC_rx_add_chk.v │ └── MAC_rx_ctrl.v │ ├── MAC_top.v │ ├── MAC_tx.v │ ├── MAC_tx │ ├── CRC_gen.v │ ├── MAC_tx_Ctrl.v │ ├── MAC_tx_FF.v │ ├── MAC_tx_addr_add.v │ ├── Ramdon_gen.v │ └── flow_ctrl.v │ ├── Phy_int.v │ ├── RMON.v │ ├── RMON │ ├── RMON_addr_gen.v │ ├── RMON_ctrl.v │ └── RMON_dpram.v │ ├── TECH │ ├── CLK_DIV2.v │ ├── CLK_SWITCH.v │ ├── altera │ │ ├── CLK_DIV2.v │ │ ├── CLK_SWITCH.v │ │ └── duram.v │ ├── duram.v │ └── xilinx │ │ ├── CLK_DIV2.v │ │ ├── CLK_SWITCH.v │ │ └── duram.v │ ├── afifo.v │ ├── eth_miim.v │ ├── header.v │ ├── miim │ ├── eth_clockgen.v │ ├── eth_outputcontrol.v │ ├── eth_shiftreg.v │ └── timescale.v │ └── reg_int.v ├── sim └── rtl_sim │ ├── modsim_sim │ ├── bin │ │ ├── com.mod │ │ ├── ip_32W_check.dll │ │ ├── ip_32W_gen.dll │ │ ├── sim.mod │ │ ├── sim_only.mod │ │ └── vlog-rtl.list │ ├── data │ │ ├── 1000Mbps_duplex.vec │ │ ├── 100Mbps_duplex.vec │ │ ├── 10Mbps_duplex.vec │ │ ├── 46-100.ini │ │ ├── 46-46.ini │ │ ├── 46-50.ini │ │ ├── 46-80.ini │ │ ├── 47-47.ini │ │ ├── 48-48.ini │ │ ├── CPU.vec │ │ ├── batch.dat │ │ ├── config.ini │ │ ├── flow_ctrl.vec │ │ ├── source_mac_replace.vec │ │ └── target_mac_check.vec │ ├── log │ │ └── ncsim.log │ └── script │ │ ├── batch_mode.tcl │ │ ├── filesel.tcl │ │ ├── run.tcl │ │ ├── run_proc.tcl │ │ ├── set_reg_data.tcl │ │ ├── set_stimulus.tcl │ │ ├── start_verify.tcl │ │ └── user_lib.tcl │ └── ncsim_sim │ ├── bin │ ├── cds.lib │ ├── com.nc │ ├── config.ini │ ├── hdl.var │ ├── ip_32W_check.dll │ ├── ip_32W_check_vpi.dll │ ├── ip_32W_gen.dll │ ├── ip_32W_gen_vpi.dll │ ├── sim.nc │ ├── sim_only.nc │ └── vlog.list │ ├── data │ ├── 1000Mbps_duplex.vec │ ├── 100Mbps_duplex.vec │ ├── 10Mbps_duplex.vec │ ├── 46-50.ini │ ├── CPU.vec │ ├── batch.dat │ ├── config.ini │ ├── flow_ctrl.vec │ ├── source_mac_replace.vec │ └── target_mac_check.vec │ ├── log │ └── ncsim.log │ └── script │ ├── batch_mode.tcl │ ├── filesel.tcl │ ├── run.tcl │ ├── run_proc.tcl │ ├── set_reg_data.tcl │ ├── set_stimulus.tcl │ ├── start_verify.tcl │ └── user_lib.tcl ├── start.tcl └── syn ├── syn.prj ├── syn_altrea.prj └── syn_xilinx.prj /EDK/edk_user_repository.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/ethernet_tri_mode/HEAD/EDK/edk_user_repository.tar.gz -------------------------------------------------------------------------------- /bench/verilog/Phy_sim.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/ethernet_tri_mode/HEAD/bench/verilog/Phy_sim.v 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