├── tap ├── doc │ ├── jtag.pdf │ └── src │ │ └── jtag.doc └── rtl │ └── verilog │ ├── tap_defines.v │ └── tap_top.v └── cells └── rtl └── verilog ├── BiDirectionalCell.v ├── InputCell.v ├── ControlCell.v └── OutputCell.v /tap/doc/jtag.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/jtag/HEAD/tap/doc/jtag.pdf -------------------------------------------------------------------------------- /tap/doc/src/jtag.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/jtag/HEAD/tap/doc/src/jtag.doc -------------------------------------------------------------------------------- /cells/rtl/verilog/BiDirectionalCell.v: -------------------------------------------------------------------------------- 1 | /********************************************************************************** 2 | * * 3 | * BiDirectional Cell: * 4 | * * 5 | * FromCore: Value that comes from on-chip logic and goes to pin * 6 | * ToCore: Value that is read-in from the pin and goes to core * 7 | * FromPreviousBSCell: Value from previous boundary scan cell * 8 | * ToNextBSCell: Value for next boundary scan cell * 9 | * CaptureDR, ShiftDR, UpdateDR: TAP states * 10 | * extest: Instruction Register Command * 11 | * TCK: Test Clock * 12 | * BiDirPin: Bidirectional pin connected to this BS cell * 13 | * FromOutputEnable: This pin comes from core or ControlCell * 14 | * * 15 | * Signal that is connected to BiDirPin comes from core or BS chain. Tristate * 16 | * control is generated in core or BS chain (ControlCell). * 17 | * * 18 | **********************************************************************************/ 19 | 20 | module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin); 21 | input FromCore; 22 | input FromPreviousBSCell; 23 | input CaptureDR; 24 | input ShiftDR; 25 | input UpdateDR; 26 | input extest; 27 | input TCK; 28 | input FromOutputEnable; 29 | 30 | reg Latch; 31 | 32 | output ToNextBSCell; 33 | reg ToNextBSCell; 34 | 35 | output BiDirPin; 36 | output ToCore; 37 | 38 | reg ShiftedControl; 39 | 40 | wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell; 41 | 42 | always @ (posedge TCK) 43 | begin 44 | if(CaptureDR | ShiftDR) 45 | Latch<=SelectedInput; 46 | end 47 | 48 | always @ (negedge TCK) 49 | begin 50 | ToNextBSCell<=Latch; 51 | end 52 | 53 | always @ (negedge TCK) 54 | begin 55 | if(UpdateDR) 56 | ShiftedControl<=ToNextBSCell; 57 | end 58 | 59 | wire MuxedSignal = extest? ShiftedControl : FromCore; 60 | assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz; 61 | 62 | //BUF Buffer (.I(BiDirPin), .O(ToCore)); 63 | assign ToCore = BiDirPin; 64 | 65 | 66 | endmodule // TristateCell -------------------------------------------------------------------------------- /cells/rtl/verilog/InputCell.v: -------------------------------------------------------------------------------- 1 | /********************************************************************************** 2 | * * 3 | * This verilog file is a part of the Boundary Scan Implementation and comes in * 4 | * a pack with several other files. It is fully IEEE 1149.1 compliant. * 5 | * For details check www.opencores.org (pdf files, bsdl file, etc.) * 6 | * * 7 | * Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG * 8 | * * 9 | * This program is free software; you can redistribute it and/or modify * 10 | * it under the terms of the GNU General Public License as published by * 11 | * the Free Software Foundation; either version 2 of the License, or * 12 | * (at your option) any later version. * 13 | * * 14 | * See the file COPYING for the full details of the license. * 15 | * * 16 | * OPENCORES.ORG is looking for new open source IP cores and developers that * 17 | * would like to help in our mission. * 18 | * * 19 | **********************************************************************************/ 20 | 21 | 22 | 23 | /********************************************************************************** 24 | * * 25 | * Input Cell: * 26 | * * 27 | * InputPin: Value that comes from on-chip logic and goes to pin * 28 | * FromPreviousBSCell: Value from previous boundary scan cell * 29 | * ToNextBSCell: Value for next boundary scan cell * 30 | * CaptureDR, ShiftDR: TAP states * 31 | * TCK: Test Clock * 32 | * * 33 | **********************************************************************************/ 34 | 35 | // This is not a top module 36 | module InputCell( InputPin, FromPreviousBSCell, CaptureDR, ShiftDR, TCK, ToNextBSCell); 37 | input InputPin; 38 | input FromPreviousBSCell; 39 | input CaptureDR; 40 | input ShiftDR; 41 | input TCK; 42 | 43 | reg Latch; 44 | 45 | output ToNextBSCell; 46 | reg ToNextBSCell; 47 | 48 | wire SelectedInput = CaptureDR? InputPin : FromPreviousBSCell; 49 | 50 | always @ (posedge TCK) 51 | begin 52 | if(CaptureDR | ShiftDR) 53 | Latch<=SelectedInput; 54 | end 55 | 56 | always @ (negedge TCK) 57 | begin 58 | ToNextBSCell<=Latch; 59 | end 60 | 61 | 62 | endmodule // InputCell -------------------------------------------------------------------------------- /cells/rtl/verilog/ControlCell.v: -------------------------------------------------------------------------------- 1 | /********************************************************************************** 2 | * * 3 | * This verilog file is a part of the Boundary Scan Implementation and comes in * 4 | * a pack with several other files. It is fully IEEE 1149.1 compliant. * 5 | * For details check www.opencores.org (pdf files, bsdl file, etc.) * 6 | * * 7 | * Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG * 8 | * * 9 | * This program is free software; you can redistribute it and/or modify * 10 | * it under the terms of the GNU General Public License as published by * 11 | * the Free Software Foundation; either version 2 of the License, or * 12 | * (at your option) any later version. * 13 | * * 14 | * See the file COPYING for the full details of the license. * 15 | * * 16 | * OPENCORES.ORG is looking for new open source IP cores and developers that * 17 | * would like to help in our mission. * 18 | * * 19 | **********************************************************************************/ 20 | 21 | 22 | /********************************************************************************** 23 | * * 24 | * I/O Control Cell: * 25 | * * 26 | * OutputControl: Output Control from on-chip logic * 27 | * FromPreviousBSCell: Value from previous boundary scan cell * 28 | * ToNextBSCell: Value for next boundary scan cell * 29 | * CaptureDR, ShiftDR, UpdateDR: TAP states * 30 | * extest: Instruction Register Command * 31 | * TCK: Test Clock * 32 | * * 33 | * Output Enable can be generated by running CaptureDR-UpdateDR sequence or * 34 | * shifting data for the exact number of time * 35 | * * 36 | **********************************************************************************/ 37 | 38 | // This is not a top module 39 | module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable); 40 | input OutputControl; 41 | input FromPreviousBSCell; 42 | input CaptureDR; 43 | input ShiftDR; 44 | input UpdateDR; 45 | input extest; 46 | input TCK; 47 | 48 | reg Latch; 49 | 50 | output ToNextBSCell; 51 | output ToOutputEnable; 52 | 53 | reg ToNextBSCell; 54 | reg ShiftedControl; 55 | 56 | wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell; 57 | 58 | always @ (posedge TCK) 59 | begin 60 | if(CaptureDR | ShiftDR) 61 | Latch<=SelectedInput; 62 | end 63 | 64 | always @ (negedge TCK) 65 | begin 66 | ToNextBSCell<=Latch; 67 | end 68 | 69 | always @ (negedge TCK) 70 | begin 71 | if(UpdateDR) 72 | ShiftedControl<=ToNextBSCell; 73 | end 74 | 75 | assign ToOutputEnable = extest? ShiftedControl : OutputControl; 76 | 77 | endmodule // ControlCell -------------------------------------------------------------------------------- /tap/rtl/verilog/tap_defines.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// tap_defines.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the JTAG Test Access Port (TAP) //// 7 | //// http://www.opencores.org/projects/jtag/ //// 8 | //// //// 9 | //// Author(s): //// 10 | //// Igor Mohor (igorm@opencores.org) //// 11 | //// //// 12 | //// //// 13 | //// All additional information is avaliable in the README.txt //// 14 | //// file. //// 15 | //// //// 16 | ////////////////////////////////////////////////////////////////////// 17 | //// //// 18 | //// Copyright (C) 2000 - 2003 Authors //// 19 | //// //// 20 | //// This source file may be used and distributed without //// 21 | //// restriction provided that this copyright statement is not //// 22 | //// removed from the file and that any derivative work contains //// 23 | //// the original copyright notice and the associated disclaimer. //// 24 | //// //// 25 | //// This source file is free software; you can redistribute it //// 26 | //// and/or modify it under the terms of the GNU Lesser General //// 27 | //// Public License as published by the Free Software Foundation; //// 28 | //// either version 2.1 of the License, or (at your option) any //// 29 | //// later version. //// 30 | //// //// 31 | //// This source is distributed in the hope that it will be //// 32 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 33 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 34 | //// PURPOSE. See the GNU Lesser General Public License for more //// 35 | //// details. //// 36 | //// //// 37 | //// You should have received a copy of the GNU Lesser General //// 38 | //// Public License along with this source; if not, download it //// 39 | //// from http://www.opencores.org/lgpl.shtml //// 40 | //// //// 41 | ////////////////////////////////////////////////////////////////////// 42 | // 43 | // CVS Revision History 44 | // 45 | // $Log: not supported by cvs2svn $ 46 | // Revision 1.2 2004/01/27 10:00:33 mohor 47 | // Unused registers removed. 48 | // 49 | // Revision 1.1 2003/12/23 14:52:14 mohor 50 | // Directory structure changed. New version of TAP. 51 | // 52 | // 53 | // 54 | 55 | 56 | // Define IDCODE Value 57 | `define IDCODE_VALUE 32'h149511c3 58 | // 0001 version 59 | // 0100100101010001 part number (IQ) 60 | // 00011100001 manufacturer id (flextronics) 61 | // 1 required by standard 62 | 63 | // Length of the Instruction register 64 | `define IR_LENGTH 4 65 | 66 | // Supported Instructions 67 | `define EXTEST 4'b0000 68 | `define SAMPLE_PRELOAD 4'b0001 69 | `define IDCODE 4'b0010 70 | `define DEBUG 4'b1000 71 | `define MBIST 4'b1001 72 | `define BYPASS 4'b1111 73 | 74 | -------------------------------------------------------------------------------- /cells/rtl/verilog/OutputCell.v: -------------------------------------------------------------------------------- 1 | /********************************************************************************** 2 | * * 3 | * This verilog file is a part of the Boundary Scan Implementation and comes in * 4 | * a pack with several other files. It is fully IEEE 1149.1 compliant. * 5 | * For details check www.opencores.org (pdf files, bsdl file, etc.) * 6 | * * 7 | * Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG * 8 | * * 9 | * This program is free software; you can redistribute it and/or modify * 10 | * it under the terms of the GNU General Public License as published by * 11 | * the Free Software Foundation; either version 2 of the License, or * 12 | * (at your option) any later version. * 13 | * * 14 | * See the file COPYING for the full details of the license. * 15 | * * 16 | * OPENCORES.ORG is looking for new open source IP cores and developers that * 17 | * would like to help in our mission. * 18 | * * 19 | **********************************************************************************/ 20 | 21 | 22 | 23 | /********************************************************************************** 24 | * * 25 | * Output Cell: * 26 | * * 27 | * FromCore: Value that comes from on-chip logic and goes to pin * 28 | * FromPreviousBSCell: Value from previous boundary scan cell * 29 | * ToNextBSCell: Value for next boundary scan cell * 30 | * CaptureDR, ShiftDR, UpdateDR: TAP states * 31 | * extest: Instruction Register Command * 32 | * TCK: Test Clock * 33 | * TristatedPin: Signal from core is connected to this output pin via BS * 34 | * FromOutputEnable: This pin comes from core or ControlCell * 35 | * * 36 | * Signal that is connected to TristatedPin comes from core or BS chain. * 37 | * Tristate control is generated in core or BS chain (ControlCell). * 38 | * * 39 | **********************************************************************************/ 40 | 41 | // This is not a top module 42 | module OutputCell( FromCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, TristatedPin); 43 | input FromCore; 44 | input FromPreviousBSCell; 45 | input CaptureDR; 46 | input ShiftDR; 47 | input UpdateDR; 48 | input extest; 49 | input TCK; 50 | input FromOutputEnable; 51 | 52 | reg Latch; 53 | 54 | output ToNextBSCell; 55 | reg ToNextBSCell; 56 | 57 | output TristatedPin; 58 | 59 | reg ShiftedControl; 60 | 61 | wire SelectedInput = CaptureDR? FromCore : FromPreviousBSCell; 62 | 63 | always @ (posedge TCK) 64 | begin 65 | if(CaptureDR | ShiftDR) 66 | Latch<=SelectedInput; 67 | end 68 | 69 | always @ (negedge TCK) 70 | begin 71 | ToNextBSCell<=Latch; 72 | end 73 | 74 | always @ (negedge TCK) 75 | begin 76 | if(UpdateDR) 77 | ShiftedControl<=ToNextBSCell; 78 | end 79 | 80 | wire MuxedSignal = extest? ShiftedControl : FromCore; 81 | assign TristatedPin = FromOutputEnable? MuxedSignal : 1'bz; 82 | 83 | endmodule // OutputCell -------------------------------------------------------------------------------- /tap/rtl/verilog/tap_top.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// tap_top.v //// 4 | //// //// 5 | //// //// 6 | //// This file is part of the JTAG Test Access Port (TAP) //// 7 | //// http://www.opencores.org/projects/jtag/ //// 8 | //// //// 9 | //// Author(s): //// 10 | //// Igor Mohor (igorm@opencores.org) //// 11 | //// //// 12 | //// //// 13 | //// All additional information is avaliable in the README.txt //// 14 | //// file. //// 15 | //// //// 16 | ////////////////////////////////////////////////////////////////////// 17 | //// //// 18 | //// Copyright (C) 2000 - 2003 Authors //// 19 | //// //// 20 | //// This source file may be used and distributed without //// 21 | //// restriction provided that this copyright statement is not //// 22 | //// removed from the file and that any derivative work contains //// 23 | //// the original copyright notice and the associated disclaimer. //// 24 | //// //// 25 | //// This source file is free software; you can redistribute it //// 26 | //// and/or modify it under the terms of the GNU Lesser General //// 27 | //// Public License as published by the Free Software Foundation; //// 28 | //// either version 2.1 of the License, or (at your option) any //// 29 | //// later version. //// 30 | //// //// 31 | //// This source is distributed in the hope that it will be //// 32 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 33 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 34 | //// PURPOSE. See the GNU Lesser General Public License for more //// 35 | //// details. //// 36 | //// //// 37 | //// You should have received a copy of the GNU Lesser General //// 38 | //// Public License along with this source; if not, download it //// 39 | //// from http://www.opencores.org/lgpl.shtml //// 40 | //// //// 41 | ////////////////////////////////////////////////////////////////////// 42 | // 43 | // CVS Revision History 44 | // 45 | // $Log: not supported by cvs2svn $ 46 | // Revision 1.5 2004/01/18 09:27:39 simons 47 | // Blocking non blocking assignmenst fixed. 48 | // 49 | // Revision 1.4 2004/01/17 17:37:44 mohor 50 | // capture_dr_o added to ports. 51 | // 52 | // Revision 1.3 2004/01/14 13:50:56 mohor 53 | // 5 consecutive TMS=1 causes reset of TAP. 54 | // 55 | // Revision 1.2 2004/01/08 10:29:44 mohor 56 | // Control signals for tdo_pad_o mux are changed to negedge. 57 | // 58 | // Revision 1.1 2003/12/23 14:52:14 mohor 59 | // Directory structure changed. New version of TAP. 60 | // 61 | // Revision 1.10 2003/10/23 18:08:01 mohor 62 | // MBIST chain connection fixed. 63 | // 64 | // Revision 1.9 2003/10/23 16:17:02 mohor 65 | // CRC logic changed. 66 | // 67 | // Revision 1.8 2003/10/21 09:48:31 simons 68 | // Mbist support added. 69 | // 70 | // Revision 1.7 2002/11/06 14:30:10 mohor 71 | // Trst active high. Inverted on higher layer. 72 | // 73 | // Revision 1.6 2002/04/22 12:55:56 mohor 74 | // tdo_padoen_o changed to tdo_padoe_o. Signal is active high. 75 | // 76 | // Revision 1.5 2002/03/26 14:23:38 mohor 77 | // Signal tdo_padoe_o changed back to tdo_padoen_o. 78 | // 79 | // Revision 1.4 2002/03/25 13:16:15 mohor 80 | // tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just 81 | // not named correctly. 82 | // 83 | // Revision 1.3 2002/03/12 14:30:05 mohor 84 | // Few outputs for boundary scan chain added. 85 | // 86 | // Revision 1.2 2002/03/12 10:31:53 mohor 87 | // tap_top and dbg_top modules are put into two separate modules. tap_top 88 | // contains only tap state machine and related logic. dbg_top contains all 89 | // logic necessery for debugging. 90 | // 91 | // Revision 1.1 2002/03/08 15:28:16 mohor 92 | // Structure changed. Hooks for jtag chain added. 93 | // 94 | // 95 | // 96 | // 97 | 98 | // synopsys translate_off 99 | `include "timescale.v" 100 | // synopsys translate_on 101 | `include "tap_defines.v" 102 | 103 | // Top module 104 | module tap_top( 105 | // JTAG pads 106 | tms_pad_i, 107 | tck_pad_i, 108 | trst_pad_i, 109 | tdi_pad_i, 110 | tdo_pad_o, 111 | tdo_padoe_o, 112 | 113 | // TAP states 114 | shift_dr_o, 115 | pause_dr_o, 116 | update_dr_o, 117 | capture_dr_o, 118 | 119 | // Select signals for boundary scan or mbist 120 | extest_select_o, 121 | sample_preload_select_o, 122 | mbist_select_o, 123 | debug_select_o, 124 | 125 | // TDO signal that is connected to TDI of sub-modules. 126 | tdo_o, 127 | 128 | // TDI signals from sub-modules 129 | debug_tdi_i, // from debug module 130 | bs_chain_tdi_i, // from Boundary Scan Chain 131 | mbist_tdi_i // from Mbist Chain 132 | ); 133 | 134 | 135 | // JTAG pins 136 | input tms_pad_i; // JTAG test mode select pad 137 | input tck_pad_i; // JTAG test clock pad 138 | input trst_pad_i; // JTAG test reset pad 139 | input tdi_pad_i; // JTAG test data input pad 140 | output tdo_pad_o; // JTAG test data output pad 141 | output tdo_padoe_o; // Output enable for JTAG test data output pad 142 | 143 | // TAP states 144 | output shift_dr_o; 145 | output pause_dr_o; 146 | output update_dr_o; 147 | output capture_dr_o; 148 | 149 | // Select signals for boundary scan or mbist 150 | output extest_select_o; 151 | output sample_preload_select_o; 152 | output mbist_select_o; 153 | output debug_select_o; 154 | 155 | // TDO signal that is connected to TDI of sub-modules. 156 | output tdo_o; 157 | 158 | // TDI signals from sub-modules 159 | input debug_tdi_i; // from debug module 160 | input bs_chain_tdi_i; // from Boundary Scan Chain 161 | input mbist_tdi_i; // from Mbist Chain 162 | 163 | // Registers 164 | reg test_logic_reset; 165 | reg run_test_idle; 166 | reg select_dr_scan; 167 | reg capture_dr; 168 | reg shift_dr; 169 | reg exit1_dr; 170 | reg pause_dr; 171 | reg exit2_dr; 172 | reg update_dr; 173 | reg select_ir_scan; 174 | reg capture_ir; 175 | reg shift_ir, shift_ir_neg; 176 | reg exit1_ir; 177 | reg pause_ir; 178 | reg exit2_ir; 179 | reg update_ir; 180 | reg extest_select; 181 | reg sample_preload_select; 182 | reg idcode_select; 183 | reg mbist_select; 184 | reg debug_select; 185 | reg bypass_select; 186 | reg tdo_pad_o; 187 | reg tdo_padoe_o; 188 | reg tms_q1, tms_q2, tms_q3, tms_q4; 189 | wire tms_reset; 190 | 191 | assign tdo_o = tdi_pad_i; 192 | assign shift_dr_o = shift_dr; 193 | assign pause_dr_o = pause_dr; 194 | assign update_dr_o = update_dr; 195 | assign capture_dr_o = capture_dr; 196 | 197 | assign extest_select_o = extest_select; 198 | assign sample_preload_select_o = sample_preload_select; 199 | assign mbist_select_o = mbist_select; 200 | assign debug_select_o = debug_select; 201 | 202 | 203 | always @ (posedge tck_pad_i) 204 | begin 205 | tms_q1 <= #1 tms_pad_i; 206 | tms_q2 <= #1 tms_q1; 207 | tms_q3 <= #1 tms_q2; 208 | tms_q4 <= #1 tms_q3; 209 | end 210 | 211 | 212 | assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset 213 | 214 | 215 | /********************************************************************************** 216 | * * 217 | * TAP State Machine: Fully JTAG compliant * 218 | * * 219 | **********************************************************************************/ 220 | 221 | // test_logic_reset state 222 | always @ (posedge tck_pad_i or posedge trst_pad_i) 223 | begin 224 | if(trst_pad_i) 225 | test_logic_reset<=#1 1'b1; 226 | else if (tms_reset) 227 | test_logic_reset<=#1 1'b1; 228 | else 229 | begin 230 | if(tms_pad_i & (test_logic_reset | select_ir_scan)) 231 | test_logic_reset<=#1 1'b1; 232 | else 233 | test_logic_reset<=#1 1'b0; 234 | end 235 | end 236 | 237 | // run_test_idle state 238 | always @ (posedge tck_pad_i or posedge trst_pad_i) 239 | begin 240 | if(trst_pad_i) 241 | run_test_idle<=#1 1'b0; 242 | else if (tms_reset) 243 | run_test_idle<=#1 1'b0; 244 | else 245 | if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir)) 246 | run_test_idle<=#1 1'b1; 247 | else 248 | run_test_idle<=#1 1'b0; 249 | end 250 | 251 | // select_dr_scan state 252 | always @ (posedge tck_pad_i or posedge trst_pad_i) 253 | begin 254 | if(trst_pad_i) 255 | select_dr_scan<=#1 1'b0; 256 | else if (tms_reset) 257 | select_dr_scan<=#1 1'b0; 258 | else 259 | if(tms_pad_i & (run_test_idle | update_dr | update_ir)) 260 | select_dr_scan<=#1 1'b1; 261 | else 262 | select_dr_scan<=#1 1'b0; 263 | end 264 | 265 | // capture_dr state 266 | always @ (posedge tck_pad_i or posedge trst_pad_i) 267 | begin 268 | if(trst_pad_i) 269 | capture_dr<=#1 1'b0; 270 | else if (tms_reset) 271 | capture_dr<=#1 1'b0; 272 | else 273 | if(~tms_pad_i & select_dr_scan) 274 | capture_dr<=#1 1'b1; 275 | else 276 | capture_dr<=#1 1'b0; 277 | end 278 | 279 | // shift_dr state 280 | always @ (posedge tck_pad_i or posedge trst_pad_i) 281 | begin 282 | if(trst_pad_i) 283 | shift_dr<=#1 1'b0; 284 | else if (tms_reset) 285 | shift_dr<=#1 1'b0; 286 | else 287 | if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr)) 288 | shift_dr<=#1 1'b1; 289 | else 290 | shift_dr<=#1 1'b0; 291 | end 292 | 293 | // exit1_dr state 294 | always @ (posedge tck_pad_i or posedge trst_pad_i) 295 | begin 296 | if(trst_pad_i) 297 | exit1_dr<=#1 1'b0; 298 | else if (tms_reset) 299 | exit1_dr<=#1 1'b0; 300 | else 301 | if(tms_pad_i & (capture_dr | shift_dr)) 302 | exit1_dr<=#1 1'b1; 303 | else 304 | exit1_dr<=#1 1'b0; 305 | end 306 | 307 | // pause_dr state 308 | always @ (posedge tck_pad_i or posedge trst_pad_i) 309 | begin 310 | if(trst_pad_i) 311 | pause_dr<=#1 1'b0; 312 | else if (tms_reset) 313 | pause_dr<=#1 1'b0; 314 | else 315 | if(~tms_pad_i & (exit1_dr | pause_dr)) 316 | pause_dr<=#1 1'b1; 317 | else 318 | pause_dr<=#1 1'b0; 319 | end 320 | 321 | // exit2_dr state 322 | always @ (posedge tck_pad_i or posedge trst_pad_i) 323 | begin 324 | if(trst_pad_i) 325 | exit2_dr<=#1 1'b0; 326 | else if (tms_reset) 327 | exit2_dr<=#1 1'b0; 328 | else 329 | if(tms_pad_i & pause_dr) 330 | exit2_dr<=#1 1'b1; 331 | else 332 | exit2_dr<=#1 1'b0; 333 | end 334 | 335 | // update_dr state 336 | always @ (posedge tck_pad_i or posedge trst_pad_i) 337 | begin 338 | if(trst_pad_i) 339 | update_dr<=#1 1'b0; 340 | else if (tms_reset) 341 | update_dr<=#1 1'b0; 342 | else 343 | if(tms_pad_i & (exit1_dr | exit2_dr)) 344 | update_dr<=#1 1'b1; 345 | else 346 | update_dr<=#1 1'b0; 347 | end 348 | 349 | // select_ir_scan state 350 | always @ (posedge tck_pad_i or posedge trst_pad_i) 351 | begin 352 | if(trst_pad_i) 353 | select_ir_scan<=#1 1'b0; 354 | else if (tms_reset) 355 | select_ir_scan<=#1 1'b0; 356 | else 357 | if(tms_pad_i & select_dr_scan) 358 | select_ir_scan<=#1 1'b1; 359 | else 360 | select_ir_scan<=#1 1'b0; 361 | end 362 | 363 | // capture_ir state 364 | always @ (posedge tck_pad_i or posedge trst_pad_i) 365 | begin 366 | if(trst_pad_i) 367 | capture_ir<=#1 1'b0; 368 | else if (tms_reset) 369 | capture_ir<=#1 1'b0; 370 | else 371 | if(~tms_pad_i & select_ir_scan) 372 | capture_ir<=#1 1'b1; 373 | else 374 | capture_ir<=#1 1'b0; 375 | end 376 | 377 | // shift_ir state 378 | always @ (posedge tck_pad_i or posedge trst_pad_i) 379 | begin 380 | if(trst_pad_i) 381 | shift_ir<=#1 1'b0; 382 | else if (tms_reset) 383 | shift_ir<=#1 1'b0; 384 | else 385 | if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir)) 386 | shift_ir<=#1 1'b1; 387 | else 388 | shift_ir<=#1 1'b0; 389 | end 390 | 391 | // exit1_ir state 392 | always @ (posedge tck_pad_i or posedge trst_pad_i) 393 | begin 394 | if(trst_pad_i) 395 | exit1_ir<=#1 1'b0; 396 | else if (tms_reset) 397 | exit1_ir<=#1 1'b0; 398 | else 399 | if(tms_pad_i & (capture_ir | shift_ir)) 400 | exit1_ir<=#1 1'b1; 401 | else 402 | exit1_ir<=#1 1'b0; 403 | end 404 | 405 | // pause_ir state 406 | always @ (posedge tck_pad_i or posedge trst_pad_i) 407 | begin 408 | if(trst_pad_i) 409 | pause_ir<=#1 1'b0; 410 | else if (tms_reset) 411 | pause_ir<=#1 1'b0; 412 | else 413 | if(~tms_pad_i & (exit1_ir | pause_ir)) 414 | pause_ir<=#1 1'b1; 415 | else 416 | pause_ir<=#1 1'b0; 417 | end 418 | 419 | // exit2_ir state 420 | always @ (posedge tck_pad_i or posedge trst_pad_i) 421 | begin 422 | if(trst_pad_i) 423 | exit2_ir<=#1 1'b0; 424 | else if (tms_reset) 425 | exit2_ir<=#1 1'b0; 426 | else 427 | if(tms_pad_i & pause_ir) 428 | exit2_ir<=#1 1'b1; 429 | else 430 | exit2_ir<=#1 1'b0; 431 | end 432 | 433 | // update_ir state 434 | always @ (posedge tck_pad_i or posedge trst_pad_i) 435 | begin 436 | if(trst_pad_i) 437 | update_ir<=#1 1'b0; 438 | else if (tms_reset) 439 | update_ir<=#1 1'b0; 440 | else 441 | if(tms_pad_i & (exit1_ir | exit2_ir)) 442 | update_ir<=#1 1'b1; 443 | else 444 | update_ir<=#1 1'b0; 445 | end 446 | 447 | /********************************************************************************** 448 | * * 449 | * End: TAP State Machine * 450 | * * 451 | **********************************************************************************/ 452 | 453 | 454 | 455 | /********************************************************************************** 456 | * * 457 | * jtag_ir: JTAG Instruction Register * 458 | * * 459 | **********************************************************************************/ 460 | reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register 461 | reg [`IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg; 462 | reg instruction_tdo; 463 | 464 | always @ (posedge tck_pad_i or posedge trst_pad_i) 465 | begin 466 | if(trst_pad_i) 467 | jtag_ir[`IR_LENGTH-1:0] <= #1 `IR_LENGTH'b0; 468 | else if(capture_ir) 469 | jtag_ir <= #1 4'b0101; // This value is fixed for easier fault detection 470 | else if(shift_ir) 471 | jtag_ir[`IR_LENGTH-1:0] <= #1 {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]}; 472 | end 473 | 474 | always @ (negedge tck_pad_i) 475 | begin 476 | instruction_tdo <= #1 jtag_ir[0]; 477 | end 478 | /********************************************************************************** 479 | * * 480 | * End: jtag_ir * 481 | * * 482 | **********************************************************************************/ 483 | 484 | 485 | 486 | /********************************************************************************** 487 | * * 488 | * idcode logic * 489 | * * 490 | **********************************************************************************/ 491 | reg [31:0] idcode_reg; 492 | reg idcode_tdo; 493 | 494 | always @ (posedge tck_pad_i) 495 | begin 496 | if(idcode_select & shift_dr) 497 | idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]}; 498 | else 499 | idcode_reg <= #1 `IDCODE_VALUE; 500 | end 501 | 502 | always @ (negedge tck_pad_i) 503 | begin 504 | idcode_tdo <= #1 idcode_reg; 505 | end 506 | /********************************************************************************** 507 | * * 508 | * End: idcode logic * 509 | * * 510 | **********************************************************************************/ 511 | 512 | 513 | /********************************************************************************** 514 | * * 515 | * Bypass logic * 516 | * * 517 | **********************************************************************************/ 518 | reg bypassed_tdo; 519 | reg bypass_reg; 520 | 521 | always @ (posedge tck_pad_i or posedge trst_pad_i) 522 | begin 523 | if (trst_pad_i) 524 | bypass_reg<=#1 1'b0; 525 | else if(shift_dr) 526 | bypass_reg<=#1 tdi_pad_i; 527 | end 528 | 529 | always @ (negedge tck_pad_i) 530 | begin 531 | bypassed_tdo <=#1 bypass_reg; 532 | end 533 | /********************************************************************************** 534 | * * 535 | * End: Bypass logic * 536 | * * 537 | **********************************************************************************/ 538 | 539 | 540 | /********************************************************************************** 541 | * * 542 | * Activating Instructions * 543 | * * 544 | **********************************************************************************/ 545 | // Updating jtag_ir (Instruction Register) 546 | always @ (posedge tck_pad_i or posedge trst_pad_i) 547 | begin 548 | if(trst_pad_i) 549 | latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset 550 | else if (tms_reset) 551 | latched_jtag_ir <=#1 `IDCODE; // IDCODE selected after reset 552 | else if(update_ir) 553 | latched_jtag_ir <=#1 jtag_ir; 554 | end 555 | 556 | /********************************************************************************** 557 | * * 558 | * End: Activating Instructions * 559 | * * 560 | **********************************************************************************/ 561 | 562 | 563 | // Updating jtag_ir (Instruction Register) 564 | always @ (latched_jtag_ir) 565 | begin 566 | extest_select = 1'b0; 567 | sample_preload_select = 1'b0; 568 | idcode_select = 1'b0; 569 | mbist_select = 1'b0; 570 | debug_select = 1'b0; 571 | bypass_select = 1'b0; 572 | 573 | case(latched_jtag_ir) /* synthesis parallel_case */ 574 | `EXTEST: extest_select = 1'b1; // External test 575 | `SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload 576 | `IDCODE: idcode_select = 1'b1; // ID Code 577 | `MBIST: mbist_select = 1'b1; // Mbist test 578 | `DEBUG: debug_select = 1'b1; // Debug 579 | `BYPASS: bypass_select = 1'b1; // BYPASS 580 | default: bypass_select = 1'b1; // BYPASS 581 | endcase 582 | end 583 | 584 | 585 | 586 | /********************************************************************************** 587 | * * 588 | * Multiplexing TDO data * 589 | * * 590 | **********************************************************************************/ 591 | always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or 592 | debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or 593 | bypassed_tdo) 594 | begin 595 | if(shift_ir_neg) 596 | tdo_pad_o = instruction_tdo; 597 | else 598 | begin 599 | case(latched_jtag_ir_neg) // synthesis parallel_case 600 | `IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code 601 | `DEBUG: tdo_pad_o = debug_tdi_i; // Debug 602 | `SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading 603 | `EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test 604 | `MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test 605 | default: tdo_pad_o = bypassed_tdo; // BYPASS instruction 606 | endcase 607 | end 608 | end 609 | 610 | 611 | // Tristate control for tdo_pad_o pin 612 | always @ (negedge tck_pad_i) 613 | begin 614 | tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select); 615 | end 616 | /********************************************************************************** 617 | * * 618 | * End: Multiplexing TDO data * 619 | * * 620 | **********************************************************************************/ 621 | 622 | 623 | always @ (negedge tck_pad_i) 624 | begin 625 | shift_ir_neg <= #1 shift_ir; 626 | latched_jtag_ir_neg <= #1 latched_jtag_ir; 627 | end 628 | 629 | 630 | endmodule 631 | --------------------------------------------------------------------------------