├── bench ├── EX_stage │ ├── EX_stage_tb_0.do │ ├── EX_stage_tb_0.v │ ├── alu_tb_0.do │ └── alu_tb_0.v ├── ID_stage │ ├── ID_stage_tb_0.do │ └── ID_stage_tb_0.v ├── IF_stage │ ├── IF_stage_tb_0.do │ ├── IF_stage_tb_0.v │ └── test1.prog ├── MEM_stage │ ├── MEM_stage_tb_0.do │ ├── MEM_stage_tb_0.v │ ├── data_mem_tb_0.do │ └── data_mem_tb_0.v ├── WB_stage │ ├── WB_stage_tb_0.do │ └── WB_stage_tb_0.v ├── hazard_detection_unit │ ├── hazard_detection_unit_tb_0.do │ └── hazard_detection_unit_tb_0.v ├── mips_16_core_top │ ├── mips_16_core_top_tb_0.do │ ├── mips_16_core_top_tb_0.v │ ├── test1.asm │ ├── test1.prog │ ├── test2.asm │ └── test2.prog └── register_file │ ├── register_file_tb_0.do │ └── register_file_tb_0.v ├── doc ├── My MIPS_16 document.docx ├── My MIPS_16 document.pdf ├── Project Description.docx ├── architecture.jpg ├── architecture.pdf ├── architecture.vsd ├── assembler_note.txt ├── instruction_set.txt ├── instruction_set_revise_note.txt ├── project_filesystem_description.txt ├── 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