├── apps ├── README.txt ├── crt │ ├── rtl │ │ └── verilog │ │ │ ├── crtc_iob.v │ │ │ ├── pci_user_constants.v │ │ │ ├── ssvga_crtc.v │ │ │ ├── ssvga_defines.v │ │ │ ├── ssvga_fifo.v │ │ │ ├── ssvga_top.v │ │ │ ├── ssvga_wbm_if.v │ │ │ ├── ssvga_wbs_if.v │ │ │ ├── timescale.v │ │ │ └── top.v │ └── syn │ │ ├── exc │ │ └── pci_crt.exc │ │ ├── out │ │ └── bit │ │ │ ├── fe.log │ │ │ └── pci_crt.bit │ │ ├── synplify │ │ ├── pci_crt.prj │ │ ├── pci_crt.sdc │ │ └── pci_crt.ucf │ │ ├── ucf │ │ └── pci_crt.ucf │ │ └── webpack │ │ ├── ise-openpci.npl │ │ └── pci_crt.ucf ├── sw │ └── driver │ │ ├── Makefile │ │ ├── README.txt │ │ ├── fb │ │ ├── Makefile │ │ ├── XF86Config-fb │ │ ├── spartan_fb.c │ │ ├── spartan_fb.o │ │ ├── spartan_kint.h │ │ └── startx │ │ ├── pci_bridge32_test │ │ ├── pci_bridge32_test.c │ │ ├── pci_bridge32_test.h │ │ ├── sdram_test │ │ ├── sdram_test.c │ │ ├── slide.c │ │ ├── spartan_drv.c │ │ └── spartan_kint.h └── test │ ├── bench │ └── verilog │ │ ├── test_bench.v │ │ └── timescale.v │ ├── rtl │ └── verilog │ │ ├── pci_bridge32.v │ │ ├── pci_test_top_1clk.v │ │ ├── pci_test_top_2clks.v │ │ ├── pci_user_constants.v │ │ └── test.v │ ├── sim │ └── rtl_sim │ │ ├── bin │ │ ├── cds.lib │ │ ├── file_list.txt │ │ └── hdl.var │ │ └── run │ │ ├── clean │ │ ├── debug.do │ │ ├── nc.scr │ │ ├── ncsim.tcl │ │ ├── run_sim.scr │ │ └── vsim.wlf │ └── syn │ └── synplify │ ├── pci_test_top.prj │ ├── pci_test_top.ucf │ ├── pci_test_top_1clk.sdc │ └── pci_test_top_2clks.sdc ├── bench └── verilog │ ├── i2c_slave_model.v │ ├── pci_behavioral_pci2pci_bridge.v │ ├── pci_behaviorial_device.v │ ├── pci_behaviorial_master.v │ ├── pci_behaviorial_target.v │ ├── pci_bench_common_tasks.v │ ├── pci_blue_arbiter.v │ ├── pci_blue_constants.vh │ ├── pci_blue_options.vh │ ├── pci_bus_monitor.v │ ├── pci_regression_constants.v │ ├── pci_testbench_defines.v │ ├── pci_unsupported_commands_master.v │ ├── system.v │ ├── top.v │ ├── wb_bus_mon.v │ ├── wb_master32.v │ ├── wb_master_behavioral.v │ └── wb_slave_behavioral.v ├── doc ├── pci_databook.doc ├── pci_databook.pdf ├── pci_datasheet.doc ├── pci_datasheet.pdf ├── pci_design_document.doc ├── pci_design_document.pdf ├── pci_specification.doc └── pci_specification.pdf ├── lib └── README.txt ├── rtl └── verilog │ ├── bus_commands.v │ ├── pci_async_reset_flop.v │ ├── pci_bridge32.v │ ├── pci_cbe_en_crit.v │ ├── pci_conf_cyc_addr_dec.v │ ├── pci_conf_space.v │ ├── pci_constants.v │ ├── pci_cur_out_reg.v │ ├── pci_delayed_sync.v │ ├── pci_delayed_write_reg.v │ ├── pci_frame_crit.v │ ├── pci_frame_en_crit.v │ ├── pci_frame_load_crit.v │ ├── pci_in_reg.v │ ├── pci_io_mux.v │ ├── pci_io_mux_ad_en_crit.v │ ├── pci_io_mux_ad_load_crit.v │ ├── pci_irdy_out_crit.v │ ├── pci_mas_ad_en_crit.v │ ├── pci_mas_ad_load_crit.v │ ├── pci_mas_ch_state_crit.v │ ├── pci_master32_sm.v │ ├── pci_master32_sm_if.v │ ├── pci_out_reg.v │ ├── pci_par_crit.v │ ├── pci_parity_check.v │ ├── pci_pci_decoder.v │ ├── pci_pci_tpram.v │ ├── pci_pcir_fifo_control.v │ ├── pci_pciw_fifo_control.v │ ├── pci_pciw_pcir_fifos.v │ ├── pci_perr_crit.v │ ├── pci_perr_en_crit.v │ ├── pci_ram_16x40d.v │ ├── pci_rst_int.v │ ├── pci_serr_crit.v │ ├── pci_serr_en_crit.v │ ├── pci_spoci_ctrl.v │ ├── pci_sync_module.v │ ├── pci_synchronizer_flop.v │ ├── pci_target32_clk_en.v │ ├── pci_target32_devs_crit.v │ ├── pci_target32_interface.v │ ├── pci_target32_sm.v │ ├── pci_target32_stop_crit.v │ ├── pci_target32_trdy_crit.v │ ├── pci_target_unit.v │ ├── pci_user_constants.v │ ├── pci_wb_addr_mux.v │ ├── pci_wb_decoder.v │ ├── pci_wb_master.v │ ├── pci_wb_slave.v │ ├── pci_wb_slave_unit.v │ ├── pci_wb_tpram.v │ ├── pci_wbr_fifo_control.v │ ├── pci_wbs_wbb3_2_wbb2.v │ ├── pci_wbw_fifo_control.v │ ├── pci_wbw_wbr_fifos.v │ └── timescale.v ├── sim └── rtl_sim │ ├── bin │ ├── artisan_file_list.lst │ ├── cds.lib │ ├── hdl.var │ ├── nc.scr │ ├── nc_artisan.scr │ ├── nc_xilinx.scr │ ├── nc_xilinx_artisan.scr │ ├── ncelab.args │ ├── ncelab_xilinx.args │ ├── ncsim.args │ ├── ncsim.rc │ ├── ncsim_waves.rc │ ├── ncvlog_artisan.args │ ├── ncvlog_artisan.scr │ ├── ncvlog_rtl.args │ ├── ncvlog_sim.args │ ├── ncvlog_xilinx.args │ ├── ncvlog_xilinx.scr │ ├── rtl_file_list.lst │ ├── sim_file_list.lst │ ├── vs_file_list.lst │ └── xilinx_file_list.lst │ ├── log │ ├── example_pci_tb.log │ ├── get_log_err_war │ ├── ncelab_xilinx.log │ ├── ncsim.log │ ├── ncvlog.log │ ├── parse_monitor_logs.scr │ ├── pci_tb.log │ ├── pciu_mon.log │ └── wbu_mon.log │ └── run │ ├── clean │ ├── ncelab.args │ ├── ncsim.args │ ├── ncsim.key │ ├── ncvlog.args │ ├── regression_example │ ├── run_pci_sim_regr.scr │ └── top_groups.do ├── sw └── configurator │ ├── PCIBridgeConfig.exe │ └── qtintf.dll └── syn └── scr ├── analyze_design.inc ├── cons_art_umc18.inc ├── cons_pci_ports.inc ├── cons_vs_umc18.inc ├── cons_wb_ports.inc ├── elaborate_design.inc ├── read_design.inc ├── reports.inc ├── save_design.inc ├── select_tech.inc ├── set_env.inc ├── tech_vs_umc18.inc └── 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