├── DOC └── fft64_um.pdf ├── BENCH ├── sinerom64_gen.pl ├── sin_tst_rom.v └── USFFT64_2B_TB.v └── RTL ├── fft64_config.inc ├── ram64.v ├── mpu707.v ├── cnorm.v ├── bufram64c1.v ├── rotator64_v.v ├── ram2x64c_1.v ├── usfft64_2b.v ├── WROM64.v └── fft8.v /DOC/fft64_um.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/pipelined_fft_64/HEAD/DOC/fft64_um.pdf -------------------------------------------------------------------------------- /BENCH/sinerom64_gen.pl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/pipelined_fft_64/HEAD/BENCH/sinerom64_gen.pl -------------------------------------------------------------------------------- /RTL/fft64_config.inc: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Parameter file //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : fft64_config.inc 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | 45 | `timescale 10 ps / 1ps 46 | 47 | //input data bit width 48 | `define USFFT64paramnb parameter nb=16; 49 | 50 | //2-nd stage data bit width 51 | `define USFFT64paramnb2 parameter nb2=nb+2; 52 | 53 | //twiddle factor bit width 54 | `define USFFT64paramnw parameter nw=15; 55 | 56 | //when is absent then FFT, when is present then IFFT 57 | //`define USFFT64paramifft ; 58 | 59 | //buffer number 2 or 3 60 | `define USFFT64parambuffers3 61 | 62 | // buffer type: 1 ports in RAMS else -2 ports RAMS 63 | //`define USFFT64bufferports1 64 | 65 | //Coeficient 0.707 bit width is increased 66 | `define USFFT64bitwidth_0707_high -------------------------------------------------------------------------------- /RTL/ram64.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// 1-port synchronous RAM //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : RAM64.v 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: 1-port synchronous RAM 45 | // FILES: RAM64.v -single ported synchronous RAM 46 | // PROPERTIES: 1) Has the volume of 64 data 47 | // 2) RAM is synchronous one, the read datum is outputted 48 | // in 2 cycles after the address setting 49 | // 3) Can be substituted to any 2-port synchronous RAM 50 | ///////////////////////////////////////////////////////////////////// 51 | 52 | `timescale 1 ns / 1 ps 53 | `include "FFT64_CONFIG.inc" 54 | 55 | module RAM64 ( CLK, ED,WE ,ADDR ,DI ,DO ); 56 | `USFFT64paramnb 57 | 58 | output [nb-1:0] DO ; 59 | reg [nb-1:0] DO ; 60 | input CLK ; 61 | wire CLK ; 62 | input ED; 63 | input WE ; 64 | wire WE ; 65 | input [5:0] ADDR ; 66 | wire [5:0] ADDR ; 67 | input [nb-1:0] DI ; 68 | wire [nb-1:0] DI ; 69 | reg [nb-1:0] mem [63:0]; 70 | reg [5:0] addrrd; 71 | 72 | always @(posedge CLK) begin 73 | if (ED) begin 74 | if (WE) mem[ADDR] <= DI; 75 | addrrd <= ADDR; //storing the address 76 | DO <= mem[addrrd]; // registering the read datum 77 | end 78 | end 79 | 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /BENCH/sin_tst_rom.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// ROM with 64 samples of sine waves at the frequencies 0/1 //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | 40 | `timescale 1 ns / 1 ps 41 | module Wave_ROM64 ( ADDR ,DATA ); 42 | output [15:0] DATA ; 43 | input [5:0] ADDR ; 44 | reg [15:0] sine[0:63]; 45 | initial begin 46 | sine[0]=16'h0000; sine[1]=16'h0C8B; sine[2]=16'h18F8; sine[3]=16'h2527; 47 | sine[4]=16'h30FB; sine[5]=16'h3C56; sine[6]=16'h471C; sine[7]=16'h5133; 48 | sine[8]=16'h5A82; sine[9]=16'h62F1; sine[10]=16'h6A6D; sine[11]=16'h70E2; 49 | sine[12]=16'h7641; sine[13]=16'h7A7C; sine[14]=16'h7D8A; sine[15]=16'h7F62; 50 | sine[16]=16'h7FFF; sine[17]=16'h7F62; sine[18]=16'h7D8A; sine[19]=16'h7A7C; 51 | sine[20]=16'h7641; sine[21]=16'h70E2; sine[22]=16'h6A6D; sine[23]=16'h62F1; 52 | sine[24]=16'h5A82; sine[25]=16'h5133; sine[26]=16'h471C; sine[27]=16'h3C56; 53 | sine[28]=16'h30FB; sine[29]=16'h2527; sine[30]=16'h18F8; sine[31]=16'h0C8B; 54 | sine[32]=16'h0000; sine[33]=16'hF375; sine[34]=16'hE708; sine[35]=16'hDAD9; 55 | sine[36]=16'hCF05; sine[37]=16'hC3AA; sine[38]=16'hB8E4; sine[39]=16'hAECD; 56 | sine[40]=16'hA57E; sine[41]=16'h9D0F; sine[42]=16'h9593; sine[43]=16'h8F1E; 57 | sine[44]=16'h89BF; sine[45]=16'h8584; sine[46]=16'h8276; sine[47]=16'h809E; 58 | sine[48]=16'h8001; sine[49]=16'h809E; sine[50]=16'h8276; sine[51]=16'h8584; 59 | sine[52]=16'h89BF; sine[53]=16'h8F1E; sine[54]=16'h9593; sine[55]=16'h9D0F; 60 | sine[56]=16'hA57E; sine[57]=16'hAECD; sine[58]=16'hB8E4; sine[59]=16'hC3AA; 61 | sine[60]=16'hCF05; sine[61]=16'hDAD9; sine[62]=16'hE708; sine[63]=16'hF375; 62 | end 63 | 64 | assign DATA=sine[ADDR]; 65 | endmodule 66 | -------------------------------------------------------------------------------- /RTL/mpu707.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Multiplier by 0.7071 //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : MPU707.v 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: Constant multiplier 45 | // PROPERTIES:1)Is based on shifts right and add 46 | // 2)for short input bit width 0.7071 is approximated as 47 | // 10110101 then rounding is not used 48 | // 3)for long input bit width 0.7071 is approximated as 49 | // 10110101000000101 50 | // 4)hardware is 3 or 4 adders 51 | ///////////////////////////////////////////////////////////////////// 52 | `include "FFT64_CONFIG.inc" 53 | 54 | module MPU707 ( CLK ,DO ,DI ,EI ); 55 | `USFFT64paramnb 56 | 57 | input CLK ; 58 | wire CLK ; 59 | input [nb+1:0] DI ; 60 | wire signed [nb+1:0] DI ; 61 | input EI ; 62 | wire EI ; 63 | 64 | output [nb+1:0] DO ; 65 | reg [nb+1:0] DO ; 66 | 67 | reg signed [nb+5 :0] dx5; 68 | reg signed [nb+2 : 0] dt; 69 | wire signed [nb+6 : 0] dx5p; 70 | wire signed [nb+6 : 0] dot; 71 | 72 | always @(posedge CLK) 73 | begin 74 | if (EI) begin 75 | dx5<=DI+(DI <<2); //multiply by 5 76 | dt<=DI; 77 | DO<=dot >>>4; 78 | end 79 | end 80 | 81 | `ifdef USFFT64bitwidth_0707_high 82 | assign dot= (dx5p+(dt>>>4)+(dx5>>>12)); // multiply by 10110101000000101 83 | `else 84 | assign dot= (dx5p+(dt>>>4) ) ; // multiply by 10110101 85 | `endif 86 | 87 | assign dx5p=(dx5<<1)+(dx5>>>2); // multiply by 101101 88 | 89 | 90 | endmodule 91 | -------------------------------------------------------------------------------- /RTL/cnorm.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Normalization unit //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : CNORM.v 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: shifting left up to 3 bits 45 | // PROPERTIES: 1)shifting left up to 3 bits controlled by 46 | // the 2-bit code SHIFT 47 | // 2)Is registered 48 | // 3)Overflow detector detects the overflow event 49 | // by the given shift condition. The detector is 50 | // zeroed by the START signal 51 | // 4)RDY is the START signal delayed to a single 52 | // clock cycle 53 | ///////////////////////////////////////////////////////////////////// 54 | `timescale 1 ns / 1 ps 55 | `include "FFT64_CONFIG.inc" 56 | 57 | module CNORM ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI ); 58 | `USFFT64paramnb 59 | 60 | output OVF ; 61 | reg OVF ; 62 | output RDY ; 63 | reg RDY ; 64 | output [nb+1:0] DOR ; 65 | wire [nb+1:0] DOR ; 66 | output [nb+1:0] DOI ; 67 | wire [nb+1:0] DOI ; 68 | 69 | input CLK ; 70 | wire CLK ; 71 | input ED ; 72 | wire ED ; 73 | input START ; 74 | wire START ; 75 | input [nb+2:0] DR ; 76 | wire [nb+2:0] DR ; 77 | input [nb+2:0] DI ; 78 | wire [nb+2:0] DI ; 79 | input [1:0] SHIFT ; 80 | wire [1:0] SHIFT ; 81 | 82 | wire[nb+2:0] diri,diii; 83 | assign diri = DR << SHIFT; 84 | assign diii = DI << SHIFT; 85 | 86 | reg [nb+2:0] dir,dii; 87 | always @( posedge CLK ) begin 88 | if (ED) begin 89 | dir<=diri[nb+2:1]; 90 | dii<=diii[nb+2:1]; 91 | end 92 | end 93 | 94 | 95 | always @( posedge CLK ) begin 96 | if (ED) begin 97 | RDY<=START; 98 | if (START) 99 | OVF<=0; 100 | else 101 | case (SHIFT) 102 | 2'b01 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]); 103 | 2'b10 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]) || 104 | (DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]); 105 | 2'b11 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1])|| 106 | (DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]) || 107 | (DR[nb+2] != DR[nb+1]) || (DI[nb-1] != DI[nb-1]); 108 | endcase 109 | end 110 | end 111 | 112 | assign DOR= dir; 113 | assign DOI= dii; 114 | 115 | endmodule 116 | -------------------------------------------------------------------------------- /RTL/bufram64c1.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Storage Buffer //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : BUFRAM64C1.v 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: FIFO - buffer with direct input order and 8-th inverse 45 | // output order 46 | // FILES: BUFRAM64C1.v - 1-st,2-nd,3-d data buffer, contains: 47 | // RAM2x64C_1.v - dual ported synchronous RAM, contains: 48 | // RAM64.v -single ported synchronous RAM 49 | // PROPERTIES: 1)Has the volume of 2x64 complex data 50 | // 2)Contains 2- port RAM and address counter 51 | // 3)Has 64-clock cycle period starting with the START 52 | // impulse and continuing forever 53 | // 4)Signal RDY precedes the 1-st correct datum output 54 | // from the buffer 55 | ///////////////////////////////////////////////////////////////////// 56 | `timescale 1 ns / 1 ps 57 | `include "FFT64_CONFIG.inc" 58 | 59 | module BUFRAM64C1 ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI ); 60 | `USFFT64paramnb 61 | output RDY ; 62 | reg RDY ; 63 | output [nb-1:0] DOR ; 64 | wire [nb-1:0] DOR ; 65 | output [nb-1:0] DOI ; 66 | wire [nb-1:0] DOI ; 67 | 68 | input CLK ; 69 | wire CLK ; 70 | input RST ; 71 | wire RST ; 72 | input ED ; 73 | wire ED ; 74 | input START ; 75 | wire START ; 76 | input [nb-1:0] DR ; 77 | wire [nb-1:0] DR ; 78 | input [nb-1:0] DI ; 79 | wire [nb-1:0] DI ; 80 | 81 | wire odd, we; 82 | wire [5:0] addrw,addrr; 83 | reg [6:0] addr; 84 | reg [7:0] ct2; //counter for the RDY signal 85 | 86 | always @(posedge CLK) // CTADDR 87 | begin 88 | if (RST) begin 89 | addr<=6'b000000; 90 | ct2<= 7'b1000001; 91 | RDY<=1'b0; end 92 | else if (START) begin 93 | addr<=6'b000000; 94 | ct2<= 6'b000000; 95 | RDY<=1'b0;end 96 | else if (ED) begin 97 | RDY<=1'b0; 98 | addr<=addr+1; 99 | if (ct2!=65) 100 | ct2<=ct2+1; 101 | if (ct2==64) 102 | RDY<=1'b1; 103 | end 104 | end 105 | 106 | 107 | assign addrw= addr[5:0]; 108 | assign odd=addr[6]; // signal which switches the 2 parts of the buffer 109 | assign addrr={addr[2 : 0], addr[5 : 3]}; // 8-th inverse output address 110 | assign we = ED; 111 | 112 | RAM2x64C_1 #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd), 113 | .ADDRW(addrw), .ADDRR(addrr), 114 | .DR(DR),.DI(DI), 115 | .DOR(DOR), .DOI(DOI)); 116 | 117 | endmodule 118 | -------------------------------------------------------------------------------- /RTL/rotator64_v.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// rotating unit, stays between 2 stages of FFT pipeline //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: complex multiplication to the twiddle factors proper to the 64 point FFT 45 | // PROPERTIES: 1) Has 64-clock cycle period starting with the START impulse and continuing forever 46 | // 2) rounding is not used 47 | ///////////////////////////////////////////////////////////////////// 48 | 49 | `timescale 1ps / 1ps 50 | `include "FFT64_CONFIG.inc" 51 | 52 | module ROTATOR64 (CLK ,RST,ED,START, DR,DI, DOR, DOI,RDY ); 53 | `USFFT64paramnb 54 | `USFFT64paramnw 55 | 56 | input RST ; 57 | wire RST ; 58 | input CLK ; 59 | wire CLK ; 60 | input ED ; //operation enable 61 | input [nb+1:0] DI; //Imaginary part of data 62 | wire [nb+1:0] DI ; 63 | input [nb+1:0] DR ; //Real part of data 64 | input START ; //1-st Data is entered after this impulse 65 | wire START ; 66 | 67 | output [nb+1:0] DOI ; //Imaginary part of data 68 | wire [nb+1:0] DOI ; 69 | output [nb+1:0] DOR ; //Real part of data 70 | wire [nb+1:0] DOR ; 71 | output RDY ; //repeats START impulse following the output data 72 | reg RDY ; 73 | 74 | 75 | reg [5:0] addrw; 76 | reg sd1,sd2; 77 | always @( posedge CLK) //address counter for twiddle factors 78 | begin 79 | if (RST) begin 80 | addrw<=0; 81 | sd1<=0; 82 | sd2<=0; 83 | end 84 | else if (START && ED) begin 85 | addrw[5:0]<=0; 86 | sd1<=START; 87 | sd2<=0; 88 | end 89 | else if (ED) begin 90 | addrw<=addrw+1; 91 | sd1<=START; 92 | sd2<=sd1; 93 | RDY<=sd2; 94 | end 95 | end 96 | 97 | wire signed [nw-1:0] wr,wi; //twiddle factor coefficients 98 | //twiddle factor ROM 99 | WROM64 UROM( .ADDR(addrw), .WR(wr),.WI(wi) ); 100 | 101 | 102 | reg signed [nb+1 : 0] drd,did; 103 | reg signed [nw-1 : 0] wrd,wid; 104 | wire signed [nw+nb+1 : 0] drri,drii,diri,diii; 105 | reg signed [nb+2:0] drr,dri,dir,dii,dwr,dwi; 106 | 107 | assign drri=drd*wrd; 108 | assign diri=did*wrd; 109 | assign drii=drd*wid; 110 | assign diii=did*wid; 111 | 112 | always @(posedge CLK) //complex multiplier 113 | begin 114 | if (ED) begin 115 | drd<=DR; 116 | did<=DI; 117 | wrd<=wr; 118 | wid<=wi; 119 | drr<=drri[nw+nb+1 :nw-1]; //msbs of multiplications are stored 120 | dri<=drii[nw+nb+1 : nw-1]; 121 | dir<=diri[nw+nb+1 : nw-1]; 122 | dii<=diii[nw+nb+1 : nw-1]; 123 | dwr<=drr - dii; 124 | dwi<=dri + dir; 125 | end 126 | end 127 | assign DOR=dwr[nb+2:1]; 128 | assign DOI=dwi[nb+2 :1]; 129 | 130 | endmodule 131 | -------------------------------------------------------------------------------- /BENCH/USFFT64_2B_TB.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Testbench for the UNFFT64_core - FFT 64 processor //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // FUNCTION:a set of 4 sine waves is inputted to the FFT processor, 40 | // the results are compared with the expected waves, 41 | // the square root mean error is calculated (without a root) 42 | // FILES: USFFT64_2B_TB.v - this file, contains 43 | // USFFT64_2B.v - unit under test 44 | // sin_tst_rom.v - rom with the test waveform, generating by 45 | // sinerom64_gen.pl 46 | // PROPERTIES: 1) the calculated error after ca. 4us modeling 47 | // is outputted to the console as the note: 48 | // rms error is 1 lsb 49 | // 2)if the error is 0,1,2 then the test is OK 50 | // 3) the customer can exchange the test selecting the 51 | // different frequencies and generating the wave ROM by 52 | // the script sinerom64_gen.pl 53 | // 4) the proper operation can be checked by investigation 54 | // of the core output waveforms 55 | ///////////////////////////////////////////////////////////////////// 56 | `include "FFT64_CONFIG.inc" 57 | 58 | `timescale 1ns / 1ps 59 | module USFFT64_2B_tb; 60 | //Parameters declaration: 61 | //defparam UUT.nb = 12; 62 | `USFFT64paramnb 63 | 64 | //Internal signals declarations: 65 | reg CLK; 66 | reg RST; 67 | reg ED; 68 | reg START; 69 | reg [3:0]SHIFT; 70 | wire [nb-1:0]DR; 71 | wire [nb-1:0]DI; 72 | wire RDY; 73 | wire OVF1; 74 | wire OVF2; 75 | wire [5:0]ADDR; 76 | wire signed [nb+2:0]DOR; 77 | wire signed [nb+2:0]DOI; 78 | 79 | initial 80 | begin 81 | CLK = 1'b0; 82 | forever #5 CLK = ~CLK; 83 | end 84 | initial 85 | begin 86 | SHIFT = 4'b0000; 87 | ED = 1'b1; 88 | RST = 1'b0; 89 | START = 1'b0; 90 | #13 RST =1'b1; 91 | #43 RST =1'b0; 92 | #53 START =1'b1; 93 | #12 START =1'b0; 94 | end 95 | 96 | reg [5:0] ct64; 97 | always @(posedge CLK or posedge START) begin 98 | if (START) ct64 = 6'b000000; 99 | else ct64 = ct64 + 'd1; 100 | end 101 | 102 | wire [15:0] DATA_RE,DATA_IM,DATA_0; 103 | Wave_ROM64 UG( .ADDR(ct64) , 104 | .DATA_RE(DATA_RE), .DATA_IM(DATA_IM), .DATA_REF(DATA_0) );// 105 | 106 | assign DR=DATA_RE[15:15-nb+1]; 107 | assign DI=DATA_IM[15:15-nb+1]; 108 | 109 | // Unit Under Test 110 | USFFT64_2B UUT ( 111 | .CLK(CLK), 112 | .RST(RST), 113 | .ED(ED), 114 | .START(START), 115 | .SHIFT(SHIFT), 116 | .DR(DR), 117 | .DI(DI), 118 | .RDY(RDY), 119 | .OVF1(OVF1), 120 | .OVF2(OVF2), 121 | .ADDR(ADDR), 122 | .DOR(DOR), 123 | .DOI(DOI)); 124 | 125 | wire [5:0] addrr; 126 | `ifdef USFFT64paramifft 127 | assign addrr= (64-ADDR); //the result order if IFFT 128 | `else 129 | assign addrr= ADDR; 130 | `endif 131 | 132 | 133 | wire signed [15:0] DATA_R0,DATA_I0,DATA_REF; 134 | Wave_ROM64 UR( .ADDR(addrr) , 135 | .DATA_RE(DATA_R0), .DATA_IM(DATA_I0), .DATA_REF(DATA_REF) );// 136 | 137 | wire signed [18:15-nb+1] DREF=2*DATA_REF[15:15-nb+1]; 138 | 139 | integer sqra; 140 | integer ctres; 141 | reg f; 142 | initial f=0; 143 | always@(posedge CLK) begin 144 | if (f) 145 | ctres=ctres+1; 146 | if (RST || RDY) begin 147 | if (RDY) f=1; 148 | sqra=0; 149 | ctres=0; end 150 | else if (ctres<64) begin 151 | #2 sqra = sqra +(DREF-DOR)*(DREF-DOR); 152 | #2 sqra = sqra +(DOI)*(DOI); end 153 | else if (ctres==64) 154 | $display("rms error is ", (sqra/128), " lsb"); 155 | end 156 | 157 | 158 | endmodule 159 | -------------------------------------------------------------------------------- /RTL/ram2x64c_1.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// 2-port RAM //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : RAM2x64C_1.v 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: 2-port RAM with 1 port to write and 1 port to read 45 | // FILES: RAM2x64C_1.v - dual ported synchronous RAM, contains: 46 | // RAM64.v -single ported synchronous RAM 47 | // PROPERTIES: 1)Has the volume of 2x64 complex data 48 | // 2)Contains 4 single port RAMs for real and 49 | // imaginary parts of data in the 2-fold volume 50 | // Two halves of RAM are switched on and off in the 51 | // write mode by the signal ODD 52 | // 3)RAM is synchronous one, the read datum is 53 | // outputted in 2 cycles after the address setting 54 | // 4)Can be substituted to any 2-port synchronous 55 | // RAM for example, to one RAMB16_S36_S36 in XilinxFPGAs 56 | ///////////////////////////////////////////////////////////////////// 57 | 58 | `timescale 1 ns / 1 ps 59 | `include "FFT64_CONFIG.inc" 60 | 61 | module RAM2x64C_1 ( CLK ,ED ,WE ,ODD ,ADDRW ,ADDRR ,DR ,DI ,DOR ,DOI ); 62 | `USFFT64paramnb 63 | 64 | 65 | output [nb-1:0] DOR ; 66 | wire [nb-1:0] DOR ; 67 | output [nb-1:0] DOI ; 68 | wire [nb-1:0] DOI ; 69 | input CLK ; 70 | wire CLK ; 71 | input ED ; 72 | wire ED ; 73 | input WE ; //write enable 74 | wire WE ; 75 | input ODD ; // RAM part switshing 76 | wire ODD ; 77 | input [5:0] ADDRW ; 78 | wire [5:0] ADDRW ; 79 | input [5:0] ADDRR ; 80 | wire [5:0] ADDRR ; 81 | input [nb-1:0] DR ; 82 | wire [nb-1:0] DR ; 83 | input [nb-1:0] DI ; 84 | wire [nb-1:0] DI ; 85 | 86 | reg oddd,odd2; 87 | always @( posedge CLK) begin //switch which reswiches the RAM parts 88 | if (ED) begin 89 | oddd<=ODD; 90 | odd2<=oddd; 91 | end 92 | end 93 | `ifdef USFFT64bufferports1 94 | //One-port RAMs are used 95 | wire we0,we1; 96 | wire [nb-1:0] dor0,dor1,doi0,doi1; 97 | wire [5:0] addr0,addr1; 98 | 99 | 100 | 101 | assign addr0 =ODD? ADDRW: ADDRR; //MUXA0 102 | assign addr1 = ~ODD? ADDRW:ADDRR; // MUXA1 103 | assign we0 =ODD? WE: 0; // MUXW0: 104 | assign we1 =~ODD? WE: 0; // MUXW1: 105 | 106 | //1-st half - write when odd=1 read when odd=0 107 | RAM64 #(nb) URAM0(.CLK(CLK),.ED(ED),.WE(we0), .ADDR(addr0),.DI(DR),.DO(dor0)); // 108 | RAM64 #(nb) URAM1(.CLK(CLK),.ED(ED),.WE(we0), .ADDR(addr0),.DI(DI),.DO(doi0)); 109 | 110 | //2-d half 111 | RAM64 #(nb) URAM2(.CLK(CLK),.ED(ED),.WE(we1), .ADDR(addr1),.DI(DR),.DO(dor1));// 112 | RAM64 #(nb) URAM3(.CLK(CLK),.ED(ED),.WE(we1), .ADDR(addr1),.DI(DI),.DO(doi1)); 113 | 114 | assign DOR=~odd2? dor0 : dor1; // MUXDR: 115 | assign DOI=~odd2? doi0 : doi1; // MUXDI: 116 | 117 | `else 118 | //Two-port RAM is used 119 | wire [6:0] addrr2 = {ODD,ADDRR}; 120 | wire [6:0] addrw2 = {~ODD,ADDRW}; 121 | wire [2*nb-1:0] di= {DR,DI} ; 122 | wire [2*nb-1:0] doi; 123 | 124 | reg [2*nb-1:0] ram [127:0]; 125 | reg [6:0] read_addra; 126 | always @(posedge CLK) begin 127 | if (ED) 128 | begin 129 | if (WE) 130 | ram[addrw2] <= di; 131 | read_addra <= addrr2; 132 | end 133 | end 134 | assign doi = ram[read_addra]; 135 | 136 | assign DOR=doi[2*nb-1:nb]; // Real read data 137 | assign DOI=doi[nb-1:0]; // Imaginary read data 138 | 139 | 140 | `endif 141 | endmodule 142 | -------------------------------------------------------------------------------- /RTL/usfft64_2b.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Top level of the high speed FFT core //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: Structural model of the high speed 64-complex point FFT 45 | // PROPERTIES: 46 | //1.Fully pipelined, 1 complex data in, 1 complex result out each 47 | //clock cycle 48 | //2. Input data, output data, coefficient widths are adjustable 49 | //in range 8..16 50 | //3. Normalization stages trigger the data overflow and shift 51 | //data right to prevent the overflow 52 | //4. Core can contain 2 or 3 data buffers. In the configuration of 53 | //2 buffers the results are in the shuffled order but provided with 54 | //the proper address. 55 | //5. The core operation can be slowed down by the control 56 | //of the ED input 57 | //6. The reset RST is synchronous 58 | ///////////////////////////////////////////////////////////////////// 59 | 60 | `timescale 1 ns / 1 ps 61 | `include "FFT64_CONFIG.inc" 62 | 63 | module USFFT64_2B ( CLK ,RST ,ED ,START ,SHIFT ,DR ,DI ,RDY ,OVF1 ,OVF2 ,ADDR ,DOR ,DOI ); 64 | `USFFT64paramnb //nb is the data bit width 65 | 66 | output RDY ; // in the next cycle after RDY=1 the 0-th result is present 67 | wire RDY ; 68 | output OVF1 ; // 1 signals that an overflow occured in the 1-st stage 69 | wire OVF1 ; 70 | output OVF2 ; // 1 signals that an overflow occured in the 2-nd stage 71 | wire OVF2 ; 72 | output [5:0] ADDR ; //result data address/number 73 | wire [5:0] ADDR ; 74 | output [nb+2:0] DOR ;//Real part of the output data, 75 | wire [nb+2:0] DOR ; // the bit width is nb+3, can be decreased when instantiating the core 76 | output [nb+2:0] DOI ;//Imaginary part of the output data 77 | wire [nb+2:0] DOI ; 78 | 79 | input CLK ; //Clock signal is less than 320 MHz for the Xilinx Virtex5 FPGA 80 | wire CLK ; 81 | input RST ; //Reset signal, is the synchronous one with respect to CLK 82 | wire RST ; 83 | input ED ; //=1 enables the operation (eneabling CLK) 84 | wire ED ; 85 | input START ; // its falling edge starts the transform or the serie of transforms 86 | wire START ; // and resets the overflow detectors 87 | input [3:0] SHIFT ; // bits 1,0 -shift left code in the 1-st stage 88 | wire [3:0] SHIFT ; // bits 3,2 -shift left code in the 2-nd stage 89 | input [nb-1:0] DR ; // Real part of the input data, 0-th data goes just after 90 | wire [nb-1:0] DR ; // the START signal or after 63-th data of the previous transform 91 | input [nb-1:0] DI ; //Imaginary part of the input data 92 | wire [nb-1:0] DI ; 93 | 94 | wire [nb-1:0] dr1,di1; 95 | wire [nb+1:0] dr3,di3,dr4,di4, dr5,di5 ; 96 | wire [nb+2:0] dr2,di2; 97 | wire [nb+4:0] dr6,di6; 98 | wire [nb+2:0] dr7,di7,dr8,di8; 99 | wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8; 100 | reg [5:0] addri ; 101 | // input buffer =8-bit inversion ordering 102 | BUFRAM64C1 #(nb) U_BUF1(.CLK(CLK), .RST(RST), .ED(ED), .START(START), 103 | .DR(DR), .DI(DI), .RDY(rdy1), .DOR(dr1), .DOI(di1)); 104 | 105 | //1-st stage of FFT 106 | FFT8 #(nb) U_FFT1(.CLK(CLK), .RST(RST), .ED(ED), 107 | .START(rdy1),.DIR(dr1),.DII(di1), 108 | .RDY(rdy2), .DOR(dr2),. DOI(di2)); 109 | 110 | wire [1:0] shiftl= SHIFT[1:0]; 111 | CNORM #(nb) U_NORM1( .CLK(CLK), .ED(ED), //1-st normalization unit 112 | .START(rdy2), // overflow detector reset 113 | .DR(dr2), .DI(di2), 114 | .SHIFT(shiftl), //shift left bit number 115 | .OVF(OVF1), 116 | .RDY(rdy3), 117 | .DOR(dr3),.DOI(di3)); 118 | 119 | // rotator to the angles proportional to PI/32 120 | ROTATOR64 U_MPU (.CLK(CLK),.RST(RST),.ED(ED), 121 | .START(rdy3),. DR(dr3),.DI(di3), 122 | .RDY(rdy4), .DOR(dr4), .DOI(di4)); 123 | 124 | BUFRAM64C1 #(nb+2) U_BUF2(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering 125 | .START(rdy4),. DR(dr4),.DI(di4), 126 | .RDY(rdy5), .DOR(dr5), .DOI(di5)); 127 | 128 | //2-nd stage of FFT 129 | FFT8 #(nb+2) U_FFT2(.CLK(CLK), .RST(RST), .ED(ED), 130 | .START(rdy5),. DIR(dr5),.DII(di5), 131 | .RDY(rdy6), .DOR(dr6), .DOI(di6)); 132 | 133 | wire [1:0] shifth= SHIFT[3:2]; 134 | //2-nd normalization unit 135 | CNORM #(nb+2) U_NORM2 ( .CLK(CLK), .ED(ED), 136 | .START(rdy6), // overflow detector reset 137 | .DR(dr6), .DI(di6), 138 | .SHIFT(shifth), //shift left bit number 139 | .OVF(OVF2), 140 | .RDY(rdy7), 141 | .DOR(dr7), .DOI(di7)); 142 | 143 | 144 | BUFRAM64C1 #(nb+3) Ubuf3(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering 145 | .START(rdy7),. DR(dr7),.DI(di7), 146 | .RDY(rdy8), .DOR(dr8), .DOI(di8)); 147 | 148 | 149 | 150 | 151 | `ifdef USFFT64parambuffers3 // 3-data buffer configuratiion 152 | always @(posedge CLK) begin //POINTER to the result samples 153 | if (RST) 154 | addri<=6'b000000; 155 | else if (rdy8==1 ) 156 | addri<=6'b000000; 157 | else if (ED) 158 | addri<=addri+1; 159 | end 160 | 161 | assign ADDR= addri ; 162 | assign DOR=dr8; 163 | assign DOI=di8; 164 | assign RDY=rdy8; 165 | 166 | `else 167 | always @(posedge CLK) begin //POINTER to the result samples 168 | if (RST) 169 | addri<=6'b000000; 170 | else if (rdy7) 171 | addri<=6'b000000; 172 | else if (ED) 173 | addri<=addri+1; 174 | end 175 | assign ADDR= {addri[2:0] , addri[5:3]} ; 176 | assign DOR= dr7; 177 | assign DOI= di7; 178 | assign RDY= rdy7; 179 | `endif 180 | endmodule 181 | -------------------------------------------------------------------------------- /RTL/WROM64.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// Twiddle factor ROM for 64-point FFT //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : WROM64.v 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: 1-port synchronous RAM 45 | // FILES: RAM64.v -single ported synchronous RAM 46 | // PROPERTIES: 47 | //1) Has 64 complex coefficients which form a table 8x8, 48 | //and stay in the needed order, as they are addressed 49 | //by the simple counter 50 | //2) 16-bit values are stored. When shorter bit width is set 51 | //then rounding is not used 52 | //3) for FFT and IFFT depending on paramifft 53 | ///////////////////////////////////////////////////////////////////// 54 | 55 | `timescale 1ps / 1ps 56 | `include "FFT64_CONFIG.inc" 57 | 58 | module WROM64 ( WI ,WR ,ADDR ); 59 | `USFFT64paramnw 60 | 61 | input [5:0] ADDR ; 62 | wire [5:0] ADDR ; 63 | 64 | output [nw-1:0] WI ; 65 | wire [nw-1:0] WI ; 66 | output [nw-1:0] WR ; 67 | wire [nw-1:0] WR ; 68 | 69 | parameter signed [15:0] c0 = 16'h7fff; 70 | parameter signed [15:0] s0 = 16'h0000; 71 | parameter signed [15:0] c1 = 16'h7f62; 72 | parameter signed [15:0] s1 = 16'h0c8c; 73 | parameter signed [15:0] c2 = 16'h7d8a; 74 | parameter signed [15:0] s2 = 16'h18f9 ; 75 | parameter signed [15:0] c3 = 16'h7a7d; 76 | parameter signed [15:0] s3 = 16'h2528; 77 | parameter signed [15:0] c4 = 16'h7642; 78 | parameter signed [15:0] s4 = 16'h30fc; 79 | parameter signed [15:0] c5 = 16'h70e3; 80 | parameter signed [15:0] s5 = 16'h3c57; 81 | parameter signed [15:0] c6 = 16'h6a6e; 82 | parameter signed [15:0] s6 = 16'h471d ; 83 | parameter signed [15:0] c7 = 16'h62f2; 84 | parameter signed [15:0] s7 = 16'h5134; 85 | parameter signed [15:0] c8 = 16'h5a82; 86 | 87 | parameter[31:0] w0= {c0,-s0}; 88 | parameter[31:0] w1= {c1,-s1}; 89 | parameter[31:0] w2= {c2,-s2}; 90 | parameter[31:0] w3= {c3,-s3}; 91 | parameter[31:0] w4= {c4,-s4}; 92 | parameter[31:0] w5= {c5,-s5}; 93 | parameter[31:0] w6= {c6,-s6}; 94 | parameter[31:0] w7= {c7,-s7}; 95 | parameter[31:0] w8= {c8,-c8}; 96 | parameter[31:0] w9= {s7,-c7}; 97 | parameter[31:0] w10= {s6,-c6}; 98 | parameter[31:0] w12= {s4,-c4}; 99 | parameter[31:0] w14= {s2,-c2}; 100 | parameter[31:0] w15= {s1,-c1}; 101 | parameter[31:0] w16= {s0,-c0}; 102 | parameter[31:0] w18= {-s2, -c2}; 103 | parameter[31:0] w20= {-s4, -c4}; 104 | parameter[31:0] w21= {-s5, -c5}; 105 | parameter[31:0] w24= {-c8, -c8}; 106 | parameter[31:0] w25= {-c7, -s7}; 107 | parameter[31:0] w28= {-c4, -s4}; 108 | parameter[31:0] w30= {-c2, -s2}; 109 | parameter[31:0] w35= {-c3, s3}; 110 | parameter[31:0] w36= {-c4, s4}; 111 | parameter[31:0] w42= {-s6, c6}; 112 | parameter[31:0] w49= {s1, c1}; 113 | 114 | reg [31:0] wf [0:63] ; 115 | integer i; 116 | 117 | always@(ADDR) begin 118 | //(w0, w0, w0, w0, w0, w0, w0, w0, 0..7 // twiddle factors for FFT 119 | // w0, w1, w2, w3, w4, w5, w6, w7, 8..15 120 | // w0, w2, w4, w6, w8, w10,w12,w14, 16..23 121 | // w0, w3, w6, w9, w12,w15,w18,w21, 24..31 122 | // w0, w4, w8, w12,w16,w20,w24,w28, 32..47 123 | // w0, w5, w10,w15,w20,w25,w30,w35, 124 | // w0, w6, w12,w18,w24,w30,w36,w42, 125 | // w0, w7, w14,w21,w28,w35,w42,w49); 126 | for( i =0; i<8; i=i+1) wf[i] =w0; 127 | for( i =8; i<63; i=i+8) wf[i] =w0; 128 | wf[9] =w1 ; wf[10] =w2 ; wf[11] =w3 ;wf[12] =w4 ; 129 | wf[13] =w5 ;wf[14] =w6 ; wf[15] =w7 ; 130 | wf[17] =w2 ;wf[18] =w4 ; wf[19] =w6 ;wf[20] =w8 ; 131 | wf[21] =w10 ;wf[22] =w12 ;wf[23] =w14; 132 | wf[25] =w3 ;wf[26] =w6 ; wf[27] =w9 ;wf[28] =w12 ; 133 | wf[29] =w15 ;wf[30] =w18 ;wf[31] =w21; 134 | wf[33] =w4 ;wf[34] =w8 ; wf[35] =w12 ;wf[36] =w16 ; 135 | wf[37] =w20 ;wf[38] =w24 ;wf[39] =w28; 136 | wf[41] =w5 ;wf[42] =w10 ; wf[43] =w15 ;wf[44] =w20 ; 137 | wf[45] =w25 ;wf[46] =w30 ;wf[47] =w35; 138 | wf[49] =w6 ;wf[50] =w12 ; wf[51] =w18 ;wf[52] =w24 ; 139 | wf[53] =w30 ;wf[54] =w36 ;wf[55] =w42; 140 | wf[57] =w7 ;wf[58] =w14 ; wf[59] =w21 ;wf[60] =w28 ; 141 | wf[61] =w35 ;wf[62] =w42 ;wf[63] =w49; 142 | end 143 | 144 | parameter[31:0] wi0= {c0,s0}; 145 | parameter[31:0] wi1= {c1,s1}; 146 | parameter[31:0] wi2= {c2,s2}; 147 | parameter[31:0] wi3= {c3,s3}; 148 | parameter[31:0] wi4= {c4,s4}; 149 | parameter[31:0] wi5= {c5,s5}; 150 | parameter[31:0] wi6= {c6,s6}; 151 | parameter[31:0] wi7= {c7,s7}; 152 | parameter[31:0] wi8= {c8,c8}; 153 | parameter[31:0] wi9= {s7,c7}; 154 | parameter[31:0] wi10= {s6,c6}; 155 | parameter[31:0] wi12= {s4,c4}; 156 | parameter[31:0] wi14= {s2,c2}; 157 | parameter[31:0] wi15= {s1,c1}; 158 | parameter[31:0] wi16= {s0,c0}; 159 | parameter[31:0] wi18= {-s2, c2}; 160 | parameter[31:0] wi20= {-s4, c4}; 161 | parameter[31:0] wi21= {-s5, c5}; 162 | parameter[31:0] wi24= {-c8, c8}; 163 | parameter[31:0] wi25= {-c7, s7}; 164 | parameter[31:0] wi28= {-c4, s4}; 165 | parameter[31:0] wi30= {-c2, s2}; 166 | parameter[31:0] wi35= {-c3, -s3}; 167 | parameter[31:0] wi36= {-c4, -s4}; 168 | parameter[31:0] wi42= {-s6, -c6}; 169 | parameter[31:0] wi49= {s1, -c1}; 170 | 171 | reg [31:0] wb [0:63] ; 172 | always@(ADDR) begin 173 | //initial begin #10; 174 | //(w0, w0, w0, w0, w0, w0, w0, w0, // twiddle factors for IFFT 175 | for( i =0; i<8; i=i+1) wb[i] =wi0; 176 | for( i =8; i<63; i=i+8) wb[i] =wi0; 177 | wb[9] =wi1 ; wb[10] =wi2 ; wb[11] =wi3 ;wb[12] =wi4 ; 178 | wb[13] =wi5 ;wb[14] =wi6 ; wb[15] =wi7 ; 179 | wb[17] =wi2 ;wb[18] =wi4 ; wb[19] =wi6 ;wb[20] =wi8 ; 180 | wb[21] =wi10 ;wb[22] =wi12 ;wb[23] =wi14; 181 | wb[25] =wi3 ;wb[26] =wi6 ; wb[27] =wi9 ;wb[28] =wi12 ; 182 | wb[29] =wi15 ;wb[30] =wi18 ;wb[31] =wi21; 183 | wb[33] =wi4 ;wb[34] =wi8 ; wb[35] =wi12 ;wb[36] =wi16 ; 184 | wb[37] =wi20 ;wb[38] =wi24 ;wb[39] =wi28; 185 | wb[41] =wi5 ;wb[42] =wi10 ; wb[43] =wi15 ;wb[44] =wi20 ; 186 | wb[45] =wi25 ;wb[46] =wi30 ;wb[47] =wi35; 187 | wb[49] =wi6 ;wb[50] =wi12 ; wb[51] =wi18 ;wb[52] =wi24 ; 188 | wb[53] =wi30 ;wb[54] =wi36 ;wb[55] =wi42; 189 | wb[57] =wi7 ;wb[58] =wi14 ; wb[59] =wi21 ;wb[60] =wi28 ; 190 | wb[61] =wi35 ;wb[62] =wi42 ;wb[63] =wi49; 191 | end 192 | 193 | wire[31:0] reim; 194 | 195 | `ifdef USFFT64paramifft 196 | assign reim = wb[ADDR]; 197 | `else 198 | assign reim = wf[ADDR]; 199 | `endif 200 | 201 | assign WR =reim[31:32-nw]; 202 | assign WI=reim[15 :16-nw]; 203 | 204 | 205 | endmodule 206 | -------------------------------------------------------------------------------- /RTL/fft8.v: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// 8-point FFT, First stage of FFT 64 processor //// 4 | //// //// 5 | //// Authors: Anatoliy Sergienko, Volodya Lepeha //// 6 | //// Company: Unicore Systems http://unicore.co.ua //// 7 | //// //// 8 | //// Downloaded from: http://www.opencores.org //// 9 | //// //// 10 | ///////////////////////////////////////////////////////////////////// 11 | //// //// 12 | //// Copyright (C) 2006-2010 Unicore Systems LTD //// 13 | //// www.unicore.co.ua //// 14 | //// o.uzenkov@unicore.co.ua //// 15 | //// //// 16 | //// This source file may be used and distributed without //// 17 | //// restriction provided that this copyright statement is not //// 18 | //// removed from the file and that any derivative work contains //// 19 | //// the original copyright notice and the associated disclaimer.//// 20 | //// //// 21 | //// THIS SOFTWARE IS PROVIDED "AS IS" //// 22 | //// AND ANY EXPRESSED OR IMPLIED WARRANTIES, //// 23 | //// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED //// 24 | //// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT //// 25 | //// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. //// 26 | //// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS //// 27 | //// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 28 | //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //// 29 | //// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT //// 30 | //// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, //// 31 | //// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) //// 32 | //// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, //// 33 | //// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 34 | //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING //// 35 | //// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, //// 36 | //// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //// 37 | //// //// 38 | ///////////////////////////////////////////////////////////////////// 39 | // Design_Version : 1.0 40 | // File name : FFT8.v 41 | // File Revision : 42 | // Last modification : Sun Sep 30 20:11:56 2007 43 | ///////////////////////////////////////////////////////////////////// 44 | // FUNCTION: 8-point FFT 45 | // FILES: FFT8.v - 1-st stage, contains 46 | // MPU707.v - multiplier to the factor 0.707. 47 | // PROPERTIES:1) Fully pipelined 48 | // 2) Each clock cycle complex datum is entered 49 | // and complex result is outputted 50 | // 3) Has 8-clock cycle period starting with the START 51 | // impulse and continuing forever 52 | // 4) rounding is not used 53 | // 5)Algorithm is from the book "H.J.Nussbaumer FFT and 54 | // convolution algorithms". 55 | // 6)IFFT is performed by substituting the output result 56 | // order to the reversed one 57 | // (by exchanging - to + and + to -) 58 | ///////////////////////////////////////////////////////////////////// 59 | //Algorithm: 60 | // procedure FFT8( 61 | // D: in MEMOC8; -- input array 62 | // DO:out MEMOC8) -- output ARRAY 63 | // is 64 | // variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex; 65 | // variable s1,s2,s3,s4: complex; 66 | // begin 67 | // t1:=D(0) + D(4); 68 | // m3:=D(0) - D(4); 69 | // t2:=D(6) + D(2); 70 | // m6:=CBASE_j*(D(6)-D(2)); 71 | // t3:=D(1) + D(5); 72 | // t4:=D(1) - D(5); 73 | // t5:=D(3) + D(7); 74 | // t6:=D(3) - D(7); 75 | // t8:=t5 + t3; 76 | // m5:=CBASE_j*(t5-t3); 77 | // t7:=t1 + t2; 78 | // m2:=t1 - t2; 79 | // m0:=t7 + t8; 80 | // m1:=t7 - t8; 81 | // m4:=SQRT(0.5)*(t4 - t6); 82 | // m7:=-CBASE_j*SQRT(0.5)*(t4 + t6); 83 | // s1:=m3 + m4; 84 | // s2:=m3 - m4; 85 | // s3:=m6 + m7; 86 | // s4:=m6 - m7; 87 | // DO(0):=m0; 88 | // DO(4):=m1; 89 | // DO(1):=s1 + s3; 90 | // DO(7):=s1 - s3; 91 | // DO(2):=m2 + m5; 92 | // DO(6):=m2 - m5; 93 | // DO(5):=s2 + s4; 94 | // DO(3):=s2 - s4; 95 | // end procedure; 96 | ///////////////////////////////////////////////////////////////////// 97 | `timescale 1ps / 1ps 98 | `include "FFT64_CONFIG.inc" 99 | 100 | module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY ); 101 | `USFFT64paramnb 102 | 103 | input ED ; 104 | wire ED ; 105 | input RST ; 106 | wire RST ; 107 | input CLK ; 108 | wire CLK ; 109 | input [nb-1:0] DII ; 110 | wire [nb-1:0] DII ; 111 | input START ; 112 | wire START ; 113 | input [nb-1:0] DIR ; 114 | wire [nb-1:0] DIR ; 115 | 116 | output [nb+2:0] DOI ; 117 | wire [nb+2:0] DOI ; 118 | output [nb+2:0] DOR ; 119 | wire [nb+2:0] DOR ; 120 | output RDY ; 121 | reg RDY ; 122 | 123 | reg [2:0] ct; //main phase counter 124 | reg [3:0] ctd; //delay counter 125 | 126 | always @( posedge CLK) begin //Control counter 127 | // 128 | if (RST) begin 129 | ct<=0; 130 | ctd<=15; 131 | RDY<=0; end 132 | else if (START) begin 133 | ct<=0; 134 | ctd<=0; 135 | RDY<=0; end 136 | else if (ED) begin 137 | RDY<=0; 138 | ct<=ct+1; 139 | if (ctd !=4'b1111) 140 | ctd<=ctd+1; 141 | if (ctd==12 ) 142 | RDY<=1; 143 | end 144 | 145 | end 146 | 147 | reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i; 148 | always @(posedge CLK) // input register file 149 | begin 150 | if (ED) begin 151 | dr<=DIR; 152 | d1r<=dr; 153 | d2r<=d1r; 154 | d3r<=d2r; 155 | d4r<=d3r; 156 | di<=DII; 157 | d1i<=di; 158 | d2i<=d1i; 159 | d3i<=d2i; 160 | d4i<=d3i; 161 | end 162 | end 163 | 164 | reg signed [nb:0] s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r; 165 | reg signed [nb:0] s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i; 166 | always @(posedge CLK) begin // S1,S2 =t1-t6,m3 and delayed 167 | if (ED && ((ct==5) || (ct==6) || (ct==7) || (ct==0))) begin 168 | s1r<=d4r + dr ; 169 | s1i<=d4i + di ; 170 | s2r<=d4r - dr ; 171 | s2i<= d4i - di; 172 | end 173 | if (ED) begin 174 | s1d1r<=s1r; 175 | s1d2r<=s1d1r; 176 | s1d1i<=s1i; 177 | s1d2i<=s1d1i; 178 | if (ct==0 || ct==1) begin //## note for vhdl 179 | s1d3r<=s1d2r; 180 | s1d3i<=s1d2i; 181 | end 182 | if (ct==6 || ct==7 || ct==0) begin 183 | s2d1r<=s2r; 184 | s2d2r<=s2d1r; 185 | s2d1i<=s2i; 186 | s2d2i<=s2d1i; 187 | end 188 | if (ct==0) begin 189 | s2d3r<=s2d2r; 190 | s2d3i<=s2d2i; 191 | end 192 | end 193 | end 194 | 195 | 196 | reg signed [nb+1:0] s3r,s4r,s3d1r,s3d2r,s3d3r; 197 | reg signed [nb+1:0] s3i,s4i,s3d1i,s3d2i,s3d3i; 198 | always @(posedge CLK) begin //ALU S3: 199 | if (ED) 200 | case (ct) 201 | 0: begin s3r<= s1d2r+s1r; //t7 202 | s3i<= s1d2i+ s1i ;end 203 | 1: begin s3r<= s1d3r - s1d1r; //m2 204 | s3i<= s1d3i - s1d1i; end 205 | 2: begin s3r<= s1d3r +s1r; //t8 206 | s3i<= s1d3i+ s1i ; end 207 | 3: begin s3r<= s1d3r - s1r; // 208 | s3i<= s1d3i - s1i ; end 209 | endcase 210 | 211 | if (ED) begin 212 | if (ct==1 || ct==2 || ct==3) begin 213 | s3d1r<=s3r; //t8 214 | s3d1i<=s3i; 215 | end 216 | if ( ct==2 || ct==3) begin 217 | s3d2r<=s3d1r; //m2 218 | s3d3r<=s3d2r; //t7 219 | s3d2i<=s3d1i; 220 | s3d3i<=s3d2i; 221 | end 222 | end 223 | end 224 | 225 | always @ (posedge CLK) begin // S4 226 | if (ED) begin 227 | if (ct==1) begin 228 | s4r<= s2d2r + s2r; 229 | s4i<= s2d2i + s2i; end 230 | else if (ct==2) begin 231 | s4r<=s2d2r - s2r; 232 | s4i<= s2d2i - s2i; 233 | end 234 | end 235 | end 236 | 237 | assign em = ((ct==2 || ct==3 || ct==4)&& ED); 238 | 239 | wire signed [nb+1:0] m4m7r,m4m7i; 240 | MPU707 #(nb) UMR( .CLK(CLK),.EI(em),.DI(s4r),.DO(m4m7r)); // UMR 241 | MPU707 #(nb) UMI( .CLK(CLK),.EI(em),.DI(s4i), .DO(m4m7i)); // UMR 242 | 243 | reg signed [nb+1:0] sjr,sji, m6r,m6i; 244 | always @ (posedge CLK) begin //multiply by J 245 | if (ED) begin 246 | case (ct) 247 | 3: begin sjr<= s2d1i; //m6 248 | sji<=0 - s2d1r; end 249 | 4: begin sjr<= m4m7i; //m7 250 | sji<=0 - m4m7r;end 251 | 6: begin sjr<= s3i; //m5 252 | sji<=0 - s3r; end 253 | endcase 254 | if (ct==4) begin 255 | m6r<=sjr; //m6 256 | m6i<=sji; 257 | end 258 | end 259 | end 260 | 261 | reg signed [nb+2:0] s5r,s5d1r,s5d2r,q1r; 262 | reg signed [nb+2:0] s5i,s5d1i,s5d2i,q1i; 263 | always @ (posedge CLK) // S5: 264 | if (ED) 265 | case (ct) 266 | 5: begin q1r<=s2d3r +m4m7r ; // S1 267 | q1i<=s2d3i +m4m7i ; 268 | s5r<=m6r + sjr; 269 | s5i<=m6i + sji; end 270 | 6: begin s5r<=m6r - sjr; 271 | s5i<=m6i - sji; 272 | s5d1r<=s5r; 273 | s5d1i<=s5i; end 274 | 7: begin s5r<=s2d3r - m4m7r; 275 | s5i<=s2d3i - m4m7i; 276 | s5d1r<=s5r; 277 | s5d1i<=s5i; 278 | s5d2r<=s5d1r; 279 | s5d2i<=s5d1i; 280 | end 281 | endcase 282 | 283 | reg signed [nb+3:0] s6r,s6i ; 284 | `ifdef paramifft 285 | always @ (posedge CLK) begin // S6-- result adder 286 | if (ED) 287 | case (ct) 288 | 5: begin s6r<=s3d3r +s3d1r ; // -- D0 289 | s6i<=s3d3i +s3d1i ;end //-- D0 290 | 6: begin 291 | s6r<=q1r - s5r ; 292 | s6i<=q1i - s5i ; end 293 | 7: begin 294 | s6r<=s3d2r - sjr ; 295 | s6i<=s3d2i - sji ; end 296 | 0: begin 297 | s6r<=s5r + s5d1r ; 298 | s6i<= s5i +s5d1i ; end 299 | 1:begin s6r<=s3d3r - s3d1r ; //-- D4 300 | s6i<=s3d3i - s3d1i ; end 301 | 2: begin 302 | s6r<= s5r - s5d1r ; // D5 303 | s6i<= s5i - s5d1i ; end 304 | 3: begin // D6 305 | s6r<=s3d3r + sjr ; 306 | s6i<=s3d3i + sji ; 307 | end 308 | 4: begin // D0 309 | s6r<= q1r + s5d2r ; 310 | s6i<= q1i + s5d2i ; 311 | end 312 | endcase 313 | end 314 | 315 | `else 316 | always @ (posedge CLK) begin // S6-- result adder 317 | if (ED) 318 | case (ct) 319 | 5: begin s6r<=s3d3r +s3d1r ; // -- D0 320 | s6i<=s3d3i +s3d1i ;end //-- D0 321 | 6: begin 322 | s6r<=q1r + s5r ; //-- D1 323 | s6i<=q1i + s5i ; end 324 | 7: begin 325 | s6r<=s3d2r +sjr ; //-- D2 326 | s6i<=s3d2i +sji ; end 327 | 0: begin 328 | s6r<=s5r - s5d1r ; // -- D3 329 | s6i<= s5i - s5d1i ;end 330 | 331 | 1:begin s6r<=s3d3r - s3d1r ; //-- D4 332 | s6i<=s3d3i - s3d1i ; end 333 | 2: begin 334 | s6r<=s5r + s5d1r ; //-- D5 335 | s6i<=s5i + s5d1i ; end 336 | 337 | 3: begin 338 | s6r<= s3d3r - sjr ; // D6 339 | s6i<=s3d3i - sji ; end 340 | 341 | 4: begin 342 | s6r<= q1r - s5d2r ; // D0 343 | s6i<= q1i - s5d2i ; end 344 | 345 | endcase 346 | end 347 | `endif 348 | 349 | assign #1 DOR=s6r[nb+2:0]; 350 | assign #1 DOI= s6i[nb+2:0]; 351 | 352 | endmodule 353 | --------------------------------------------------------------------------------