├── bench └── verilog │ ├── spi_slave_model.v │ ├── tst_bench_top.v │ └── wb_master_model.v ├── doc ├── simple_spi.pdf └── src │ └── simple_spi.doc ├── rtl └── verilog │ ├── fifo4.v │ └── simple_spi_top.v └── sim └── rtl_sim ├── bin └── Makefile └── run ├── Makefile ├── ncsim.log ├── ncvlog.log ├── ncwork ├── cds.lib ├── hdl.var └── work │ ├── .cdsvmod │ ├── .inca.db.135.linux │ ├── .inca.db.148.lnx86 │ ├── inca.linux.135.pak │ └── inca.lnx86.148.pak ├── simvision.sv ├── stdout.log └── waves └── waves.do /bench/verilog/spi_slave_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/bench/verilog/spi_slave_model.v -------------------------------------------------------------------------------- /bench/verilog/tst_bench_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/bench/verilog/tst_bench_top.v -------------------------------------------------------------------------------- /bench/verilog/wb_master_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/bench/verilog/wb_master_model.v -------------------------------------------------------------------------------- /doc/simple_spi.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/doc/simple_spi.pdf -------------------------------------------------------------------------------- /doc/src/simple_spi.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/doc/src/simple_spi.doc -------------------------------------------------------------------------------- /rtl/verilog/fifo4.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/rtl/verilog/fifo4.v -------------------------------------------------------------------------------- /rtl/verilog/simple_spi_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/rtl/verilog/simple_spi_top.v -------------------------------------------------------------------------------- /sim/rtl_sim/bin/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/sim/rtl_sim/bin/Makefile -------------------------------------------------------------------------------- /sim/rtl_sim/run/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/sim/rtl_sim/run/Makefile -------------------------------------------------------------------------------- /sim/rtl_sim/run/ncsim.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/simple_spi/HEAD/sim/rtl_sim/run/ncsim.log -------------------------------------------------------------------------------- /sim/rtl_sim/run/ncvlog.log: -------------------------------------------------------------------------------- 1 | ncvlog: v03.40.(b001): (c) Copyright 1995 - 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