├── JAVA_app ├── GigaRxLossy.java └── setup.sh ├── LUT_COE_file └── definition2_ipv4_lut.coe ├── PAPER └── alachiot_berg_stamatak__UDP_IP_core.pdf ├── README.txt └── UDP_IP_CORE ├── UDP_IP_CORE__Spartan3 ├── ALLOW_ZERO_UDP_CHECKSUM.vhd ├── COUNTER_11B_EN_RECEIV.vhd ├── COUNTER_11B_EN_TRANS.vhd ├── COUNTER_6B_LUT_FIFO_MODE.vhd ├── ENABLE_USER_DATA_TRANSMISSION.vhd ├── IPV4_LUT_INDEXER.vhd ├── IPV4_PACKET_TRANSMITTER.vhd ├── IPv4_PACKET_RECEIVER.vhd ├── OVERRIDE_LUT_CONTROL.vhd ├── PACKET_RECEIVER_FSM.vhd ├── REG_16B_WREN.vhd ├── REG_8b_wren.vhd ├── TARGET_EOF.vhd ├── UDP_IP_Core.vhd ├── comp_11b_equal.ngc ├── comp_11b_equal.vhd ├── comp_11b_equal.xco ├── comp_6b_equal.ngc ├── comp_6b_equal.vhd ├── comp_6b_equal.xco ├── dist_mem_64x8.ngc ├── dist_mem_64x8.vhd └── dist_mem_64x8.xco └── UDP_IP_CORE__Virtex5 ├── ALLOW_ZERO_UDP_CHECKSUM.vhd ├── COUNTER_11B_EN_RECEIV.vhd ├── COUNTER_11B_EN_TRANS.vhd ├── COUNTER_6B_LUT_FIFO_MODE.vhd ├── ENABLE_USER_DATA_TRANSMISSION.vhd ├── IPV4_LUT_INDEXER.vhd ├── IPV4_PACKET_TRANSMITTER.vhd ├── IPv4_PACKET_RECEIVER.vhd ├── OVERRIDE_LUT_CONTROL.vhd ├── PACKET_RECEIVER_FSM.vhd ├── REG_16B_WREN.vhd ├── REG_8b_wren.vhd ├── TARGET_EOF.vhd ├── UDP_IP_Core.vhd ├── comp_11b_equal.ngc ├── comp_11b_equal.vhd ├── comp_11b_equal.xco ├── comp_6b_equal.ngc ├── comp_6b_equal.vhd ├── comp_6b_equal.xco ├── dist_mem_64x8.ngc ├── dist_mem_64x8.vhd └── dist_mem_64x8.xco /JAVA_app/GigaRxLossy.java: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2010 Simon A. Berger 3 | * 4 | * This program is free software; you may redistribute it and/or modify its 5 | * under the terms of the GNU General Public License as published by the Free 6 | * Software Foundation; either version 2 of the License, or (at your option) 7 | * any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, but 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 | * for more details. 13 | */ 14 | 15 | 16 | /* 17 | * This is the code used for the evaluation of the FPGA/PC communication using 18 | * UDP/IP. 19 | * This program can operate in two modes, which correspond to the two evaluations 20 | * in the paper: 21 | * - one way test: receive packets for 10 seconds. Calculate actual number of 22 | * sent packets from the serial numbers. 23 | * - two way (duplex) test: send a fixed number of packets and count received 24 | * packets. 25 | * 26 | * The program mode is controlled with the DUPLEX_TEST constant. 27 | * 28 | * To compile this program use "javac GigaRxLossy.java" 29 | * To run the program use "java GigaRxLoss" 30 | */ 31 | 32 | import java.io.IOException; 33 | import java.net.DatagramPacket; 34 | import java.net.DatagramSocket; 35 | import java.net.InetAddress; 36 | import java.net.InetSocketAddress; 37 | import java.net.SocketAddress; 38 | import java.nio.ByteBuffer; 39 | import java.nio.MappedByteBuffer; 40 | import java.nio.IntBuffer; 41 | import java.nio.DoubleBuffer; 42 | 43 | import java.nio.channels.ClosedByInterruptException; 44 | import java.nio.channels.DatagramChannel; 45 | 46 | 47 | public class GigaRxLossy { 48 | public static boolean isValid( ByteBuffer b, int size ) { 49 | int ref = b.get(); 50 | 51 | for( int i = 1; i < size; i++ ) { 52 | if( b.get() != ref ) { 53 | 54 | return false; 55 | } 56 | } 57 | 58 | return true; 59 | } 60 | 61 | public static void main(String[] args) throws IOException, InterruptedException { 62 | final int MTU = 1500; 63 | 64 | final SocketAddress rxaddr = new InetSocketAddress( 21844 ); 65 | 66 | final DatagramChannel rxc = DatagramChannel.open(); 67 | 68 | rxc.socket().bind(rxaddr); 69 | 70 | final SocketAddress txsendtoaddr = new InetSocketAddress( "192.168.1.1", 21845 ); 71 | 72 | 73 | // set this constant to: 74 | // - false for the one-way test 75 | // - true for the duplex test 76 | 77 | boolean DUPLEX_TEST = !true; 78 | 79 | 80 | boolean haveTx; 81 | boolean trigger; 82 | if( DUPLEX_TEST ) { 83 | haveTx = true; 84 | trigger = false; 85 | 86 | } else { 87 | haveTx = false; 88 | trigger = true; 89 | } 90 | 91 | 92 | final DatagramChannel txc; 93 | 94 | if( haveTx || trigger ) 95 | { 96 | txc = DatagramChannel.open(); 97 | txc.socket().bind(null); 98 | } else { 99 | txc = null; 100 | } 101 | 102 | final Thread reader = new Thread() { 103 | // this is the recaiver thread 104 | @Override 105 | public void run() { 106 | 107 | java.nio.ByteBuffer rxb = ByteBuffer.allocateDirect(MTU); 108 | 109 | boolean first = true; 110 | int firstser = -1; 111 | int lastser = -1; 112 | int nrec = 0; 113 | long time = System.currentTimeMillis(); 114 | 115 | long rxbytes = 0; 116 | long txn = 0; 117 | try { 118 | //rxc.connect(rxaddr); 119 | 120 | 121 | while( !isInterrupted() ) { 122 | 123 | rxb.rewind(); 124 | rxc.receive(rxb); 125 | int rxsize = rxb.position(); 126 | 127 | rxb.rewind(); 128 | //int ser = rxb.asIntBuffer().get(0); 129 | IntBuffer ib = rxb.asIntBuffer(); 130 | // DoubleBuffer db = rxb.asDoubleBuffer(); 131 | 132 | int ser = ib.get()>>>24; 133 | 134 | // calculate the number of actually sent packets from the serial 135 | // number. 136 | if( !first ) { 137 | if( ser < lastser ) { 138 | txn += ser - (lastser - 256 ); 139 | } else { 140 | txn += ser - lastser; 141 | } 142 | //System.out.printf( "int %d\n", txn ); 143 | } else { 144 | first = false; 145 | } 146 | lastser = ser; 147 | 148 | if( firstser == -1 ) { 149 | firstser = ser; 150 | } 151 | 152 | 153 | // for maximum speed the validity check may be disabled as the current 154 | // implementation is fairly inefficient. In our tests we never got any 155 | // packet corruption. 156 | boolean CHECK_VALID = true; 157 | if( CHECK_VALID ) { 158 | if( !isValid( rxb, rxsize ) ) { 159 | System.out.println( "invalid" ); 160 | } 161 | } 162 | // lastser = ser; 163 | nrec++; 164 | rxbytes+=rxsize; 165 | 166 | } 167 | } catch( ClosedByInterruptException e ) { 168 | System.out.printf( "reader: interrupted. bye ...\n" ); 169 | 170 | } catch (IOException e) { 171 | 172 | // TODO Auto-generated catch block 173 | e.printStackTrace(); 174 | throw new RuntimeException( "bailing out." ); 175 | } 176 | long dt = System.currentTimeMillis() - time; 177 | System.out.printf( "%d bytes in %d ms: %.2f Mb/s\n", rxbytes, dt, rxbytes / (dt * 1000.0) ); 178 | int serrange = (lastser - firstser) + 1; 179 | System.out.printf( "nrec: %d of %d (%.2f%%)\n", nrec, txn, nrec / (float)txn * 100.0 ); 180 | } 181 | }; 182 | 183 | if( !trigger ) { 184 | reader.start(); 185 | } 186 | 187 | if( haveTx ) { 188 | Thread writer = new Thread() { 189 | // this is the sender thread. 190 | @Override 191 | public void run() { 192 | // TODO Auto-generated method stub 193 | //java.nio.ByteBuffer txb = MappedByteBuffer.allocate(MTU); 194 | java.nio.ByteBuffer txb = java.nio.ByteBuffer.allocateDirect(MTU); 195 | int i = 0; 196 | long time = System.currentTimeMillis(); 197 | 198 | long txbytes = 0; 199 | long nj = 0; 200 | while( i < 1000000 ) { 201 | txb.rewind(); 202 | 203 | txb.asIntBuffer().put(0, i); 204 | txb.rewind(); 205 | try { 206 | txbytes += txc.send(txb, txsendtoaddr); 207 | 208 | 209 | 210 | } catch (IOException e) { 211 | // TODO Auto-generated catch block 212 | e.printStackTrace(); 213 | } 214 | i++; 215 | 216 | if( i % 10000 == 0 ) { 217 | System.out.printf( "tx -> rx %d\n", i ); 218 | } 219 | 220 | // if( ack.i != -1 ) { 221 | // i = ack.i; 222 | // ack.i = -1; 223 | // } 224 | } 225 | long dt = System.currentTimeMillis() - time; 226 | System.out.printf( "%d bytes in %d ms: %.2f Mb/s\n", txbytes, dt, txbytes / (dt * 1000.0) ); 227 | } 228 | }; 229 | 230 | 231 | 232 | writer.start(); 233 | 234 | writer.join(); 235 | reader.interrupt(); 236 | } else { 237 | if( trigger ) { 238 | java.nio.ByteBuffer txb = java.nio.ByteBuffer.allocateDirect(MTU); 239 | txc.send(txb, txsendtoaddr); 240 | Thread.sleep( 1000 ); 241 | } 242 | reader.start(); 243 | Thread.sleep(10000); 244 | reader.interrupt(); 245 | } 246 | } 247 | } 248 | -------------------------------------------------------------------------------- /JAVA_app/setup.sh: -------------------------------------------------------------------------------- 1 | #! /bin/sh 2 | 3 | # This script sets up the basic network configuration and a 'fake' ARP table 4 | # entry for the FPGA. 5 | # We assume that the FPGA is connected to the ethernet port eth0. 6 | # The IP adress of the PC is fixed to 192.168.1.2, the IP of the FPGA 7 | # is fixed to 192.168.1.1. 8 | # The ARP table entry will cause every packet sent to 192.168.1.1 9 | # to be routed to the FPGA. 10 | 11 | sudo ifconfig eth0 down 12 | 13 | sudo ifconfig eth0 -arp 14 | sudo ifconfig eth0 192.168.1.2 15 | sudo arp -i eth0 -s 192.168.1.1 FF:FF:FF:FF:FF:FF 16 | sudo ifconfig eth0 mtu 9000 17 | -------------------------------------------------------------------------------- /LUT_COE_file/definition2_ipv4_lut.coe: -------------------------------------------------------------------------------- 1 | MEMORY_INITIALIZATION_RADIX=2; 2 | MEMORY_INITIALIZATION_VECTOR= 3 | 00000000, 4 | 00100001, 5 | 01110000, 6 | 11101001, 7 | 00110100, 8 | 01011100, 9 | 11111111, 10 | 11111111, 11 | 11111111, 12 | 11111111, 13 | 11111111, 14 | 11111111, 15 | 00001000, 16 | 00000000, 17 | 01000101, 18 | 00000000, 19 | 00100100, 20 | 00000000, 21 | 00000000, 22 | 00000000, 23 | 01000000, 24 | 00000000, 25 | 01000000, 26 | 00010001, 27 | 10110111, 28 | 01111101, 29 | 11000000, 30 | 10101000, 31 | 00000001, 32 | 00000001, 33 | 11000000, 34 | 10101000, 35 | 00000001, 36 | 00000010, 37 | 01010101, 38 | 01010101, 39 | 01010101, 40 | 01010100, 41 | 00000000, 42 | 00000000, 43 | 00000000, 44 | 00000000, 45 | 00000000, 46 | 00000000, 47 | 00000000, 48 | 00000000, 49 | 00000000, 50 | 00000000, 51 | 00000000, 52 | 00000000, 53 | 00000000, 54 | 00000000, 55 | 00000000, 56 | 00000000, 57 | 00000000, 58 | 00000000, 59 | 00000000, 60 | 00000000, 61 | 00000000, 62 | 00000000, 63 | 00000000, 64 | 00000000, 65 | 00000000, 66 | 00000000; 67 | -------------------------------------------------------------------------------- /PAPER/alachiot_berg_stamatak__UDP_IP_core.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/freecores/udp_ip__core/103be62e56dd89d5a06f5e76eba1caced3116aa7/PAPER/alachiot_berg_stamatak__UDP_IP_core.pdf -------------------------------------------------------------------------------- /README.txt: -------------------------------------------------------------------------------- 1 | ====================================================================================================== 2 | UDP/IP Core for FPGAs (in VHDL) 3 | ====================================================================================================== 4 | 5 | Update date: February 9th, 2010 6 | Build date: December 15th, 2009 7 | 8 | 9 | Description 10 | ----------- 11 | 12 | 13 | This is a VHDL implementation of a UDP/IP core that can be connected to the input and output ports of the 14 | Virtex-5 Ethernet MAC Local Link Wrapper and enable communication betweena a PC and a FPGA. 15 | 16 | It has been area-optimized, it is suitable for direct PC-FPGA communication and can operate at Gigabit speed. 17 | 18 | 19 | Example placement on a Virtex 5: 20 | 21 | 22 | -- ----------------------------------------------------------------------- 23 | -- | EXAMPLE DESIGN WRAPPER | 24 | -- | --------------------------------------------------------| 25 | -- | |LOCAL LINK WRAPPER | 26 | -- | | -----------------------------------------| 27 | -- | UDP/IP core | |BLOCK LEVEL WRAPPER | 28 | -- | ----------- | | --------------------- | 29 | -- | |-------- | | ---------- | | ETHERNET MAC | | 30 | -- | || IPv4 | | | | | | | WRAPPER | --------- | 31 | -- |->| pack |-> |->| |--|--->| Tx Tx |--| |--->| 32 | -- | || trans| | | | | | | client PHY | | | | 33 | -- | |-------- | | | LOCAL | | | I/F I/F | | | | 34 | -- | | | | | LINK | | | | | PHY | | 35 | -- | | | | | FIFO | | | | | I/F | | 36 | -- | | | | | | | | | | | | 37 | -- | |-------- | | | | | | Rx Rx | | | | 38 | -- | || IPv4 | | | | | | | client PHY | | | | 39 | -- | || pack |<- |<-| |<-|----| I/F I/F |<-| |<---| 40 | -- | ||receiv| | | | | | | | --------- | 41 | -- | |-------- | | ---------- | --------------------- | 42 | -- | ----------- | -----------------------------------------| 43 | -- | --------------------------------------------------------| 44 | -- ----------------------------------------------------------------------- 45 | 46 | 47 | 48 | Package Structure 49 | ----------------- 50 | 51 | This package contains the following files and folder: 52 | 53 | -README : This file 54 | 55 | -UDP_IP_CORE : This folder contains VHDL, XCO and NGC files both for Virtex 5 as well as Spartan 3 FPGAs. 56 | 57 | -LUT COE file : This folder contains a COE file for the LUT that contains the IP packet header field. 58 | 59 | -JAVA app : This folder contains the JAVA application used on the PC side for transmitting and receiving packets. 60 | 61 | -PAPER : This folder contains a paper that describes in detail the design and implementation of the core. 62 | 63 | 64 | 65 | Usage of the UDP/IP core 66 | ------------------------ 67 | 68 | 69 | Before integrating the core into your design you have to reinitialize the LUT of the transmitter. 70 | This LUT contains the header section of the IP packet.One must change the X fields that appear in the following table. 71 | 72 | The field that should be changed are: 73 | Destination MAC Address : (LUT) 74 | Source MAC Address : (LUT) 75 | Source IP Address : (LUT) 76 | Destination IP Address : (LUT) 77 | Source Port : (LUT) 78 | Destination Port : (LUT) 79 | Header Checksum : VHDL file 80 | 81 | The Addresses are read from the LUT, thats why a reinitialization is required. 82 | The Header Checksum base value is not read from the LUT. It can be found in the VHDL file. 83 | The Header Checksum base value depends on the IP Addresses and it is the Header Checksum value of a packet with no user data. 84 | 85 | If you choose to use the JAVA application provided in this packet only the Destination MAC Address needs to change. 86 | 87 | 88 | ------------------------------------------------------------------------------------------------------------------------------------------ 89 | ------------------------------------------------------------------------------------------------------------------------------------------ 90 | -- IPv4 PACKET STRUCTURE : -- -- 91 | -- size | Description | Transmission Order | Position -- 92 | ------------------------------------------------------------------------------------------------------------------------------------------ 93 | -- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT -- 94 | -- | X-X-X-X-X-X | | -- 95 | -- | | | -- 96 | -- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT -- 97 | -- | 11111111-11111111-11111111-11111111-... | | -- 98 | -- 2 bytes | Ethernet Type | 12 13 | LUT -- 99 | -- | (fixed to 00001000-00000000 :=> | | -- 100 | -- | Internet Protocol, Version 4 (IPv4)) | | -- 101 | -- -- Start of IPv4 Packet - - - - - - - - - - - - - -- -- 102 | -- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length| 14 | LUT -- 103 | -- | 0100 0101 | | -- 104 | -- 1 byte | Differentiated Services | 15 | LUT -- 105 | -- | 00000000 | | -- 106 | -- 2 bytes | Total Length | 16 17 | REG -- 107 | -- | 00000000-00100100 (base: 20 + 8 + datalength)| | -- 108 | -- 2 bytes | Identification | 18 19 | LUT -- 109 | -- | 00000000-00000000 | | -- 110 | -- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset| 20 21 | LUT -- 111 | -- | 010 - 0000000000000 | | -- 112 | -- 1 byte | Time to Live | 22 | LUT -- 113 | -- | 01000000 | | -- 114 | -- 1 byte | Protocol | 23 | LUT -- 115 | -- | 00010001 | | -- 116 | -- 2 bytes | Header Checksum | 24 25 | REG -- 117 | -- | X X (base value) | | -- 118 | -- 4 bytes | Source IP Address | 26 27 28 29 | LUT -- 119 | -- | X-X-X-X - FPGA | | -- 120 | -- 4 bytes | Destin IP Address | 30 31 32 33 | LUT -- 121 | -- | X-X-X-X - PC | | -- 122 | -- -- Start of UDP Packet - - - - - - - - - - - - - - -- -- 123 | -- 2 bytes | Source Port | 34 35 | LUT -- 124 | -- | X-X | | -- 125 | -- 2 bytes | Destination Port | 36 37 | LUT -- 126 | -- | X-X | | -- 127 | -- 2 bytes | Length | 38 39 | REG -- 128 | -- | 00000000 - 00010000 (8 + # data bytes)| | -- 129 | -- 2 bytes | Checksum | 40 41 | LUT -- 130 | -- | 00000000 - 00000000 | | -- 131 | -- X bytes | Data | 42 .. X | from input -- 132 | -- | | | -- -- 133 | ------------------------------------------------------------------------------------------------------------------------------------------ 134 | ------------------------------------------------------------------------------------------------------------------------------------------ 135 | 136 | 137 | 138 | Interface of the UDP/IP core 139 | ---------------------------- 140 | 141 | 142 | The interface of the unit is defined as follows: 143 | 144 | entity UDP_IP_Core is 145 | Port ( rst : in STD_LOGIC; -- active-high 146 | clk_125MHz : in STD_LOGIC; 147 | 148 | -- Transmit signals 149 | transmit_start_enable : in STD_LOGIC; 150 | transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); 151 | usr_data_trans_phase_on : out STD_LOGIC; 152 | transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); 153 | start_of_frame_O : out STD_LOGIC; 154 | end_of_frame_O : out STD_LOGIC; 155 | source_ready : out STD_LOGIC; 156 | transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0); 157 | 158 | --Receive Signals 159 | rx_sof : in STD_LOGIC; 160 | rx_eof : in STD_LOGIC; 161 | input_bus : in STD_LOGIC_VECTOR(7 downto 0); 162 | valid_out_usr_data : out STD_LOGIC; 163 | usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0) 164 | ); 165 | end UDP_IP_Core; 166 | 167 | 168 | The UDP/IP core and the LOCAL LINK WRAPPER must have the same rst and clk signals. 169 | 170 | Signal transmit_start_enable : active high , It must be high for one clock cycle only. 171 | 172 | Signal transmit_data_length : number of user data to be transmitted (number of bytes) 173 | 174 | Signal usr_data_trans_phase_on: is high one clock cycle before the transmittion of user data and remains high while transmitting user data. 175 | 176 | Signal transmit_data_input_bus : input data to be transmitted. Starts transmitting one clock cycle after the usr_data_trans_phase_on is set. 177 | 178 | Signals start_of_frame_O,end_of_frame_O,source_ready,transmit_data_output_bus should be connected to the local link wrapper's input ports. 179 | 180 | Signals rx_sof, rx_eof : active low, inputs from the local link wrapper 181 | 182 | Signal input_bus : input from the local link wrapper 183 | 184 | Signal valid_out_usr_data : output to user, when set it indicates that the usr_data_output_bus contains the user data section of the incoming packet 185 | 186 | Signal usr_data_output_bus : user data output bus output to the user 187 | 188 | 189 | 190 | Implementation Details 191 | ---------------------- 192 | 193 | The VHDL unit have been designed using the Xilinx 10.1 Design Suite. 194 | 195 | ISE 10.1 was used to create the unit. 196 | 197 | 198 | 199 | Verification Details 200 | -------------------- 201 | 202 | Modelsim 6.3f was used for extensive post place and route simulations. 203 | 204 | The development board HTG-V5-PCIE by HiTech Global populated with a V5SX95T-1 FPGA was used to verify the correct behavior of the core. 205 | 206 | The Spartan3 configuration has not been hardware-verified! 207 | 208 | It has been verified on Virtex 6 FPGA by users! 209 | 210 | 211 | Citation 212 | -------- 213 | 214 | By using this component in any architecture design and associated publication, you agree to cite it as: 215 | "Efficient PC-FPGA Communication over Gigabit Ethernet", by Nikolaos Alachiotis, Simon A. Berger and Alexandros Stamatakis, 216 | IEEE ICESS 2010, June/July 2010. 217 | 218 | 219 | Authors and Contact Details 220 | --------------------------- 221 | 222 | Nikos Alachiotis n.alachiotis@gmail.com 223 | Simon A. Berger bergers@in.tum.de 224 | Alexandros Stamatakis stamatak@in.tum.de 225 | 226 | Technichal University of Munich 227 | Department of Computer Science / I 12 228 | The Exelixis Lab 229 | Boltzmannstr. 3 230 | D-85748 Garching b. Muenchen 231 | 232 | 233 | Copyright 234 | --------- 235 | 236 | This component is free. In case you use it for any purpose, particularly 237 | when publishing work relying on this component you must cite it as: 238 | 239 | N. Alachiotis, S.A. Berger, A. Stamatakis: "Efficient PC-FPGA Communication over Gigabit Ethernet". IEEE ICESS 2010, June/July 2010. 240 | 241 | 242 | 243 | You can redistribute it and/or modify 244 | it under the terms of the GNU Lesser General Public License as published by 245 | the Free Software Foundation; either version 2 of the License, or 246 | (at your option) any later version. 247 | 248 | This component is distributed in the hope that it will be useful, 249 | but WITHOUT ANY WARRANTY; without even the implied warranty of 250 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 251 | GNU General Public License for more details. 252 | 253 | 254 | 255 | Release Notes 256 | ------------ 257 | 258 | Update date: February 9th, 2010 259 | 260 | Build date : December 15th, 2009 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/ALLOW_ZERO_UDP_CHECKSUM.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:46:33 12/04/2009 6 | -- Design Name: 7 | -- Module Name: ALLOW_ZERO_UDP_CHECKSUM - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity ALLOW_ZERO_UDP_CHECKSUM is 31 | Port ( clk : in STD_LOGIC; 32 | input : in STD_LOGIC; 33 | output_to_readen : out STD_LOGIC; 34 | output_to_datasel : out STD_LOGIC); 35 | end ALLOW_ZERO_UDP_CHECKSUM; 36 | 37 | architecture Behavioral of ALLOW_ZERO_UDP_CHECKSUM is 38 | 39 | signal input_reg : std_logic; 40 | 41 | begin 42 | 43 | process(clk) 44 | begin 45 | if clk'event and clk='1' then 46 | input_reg<=input; 47 | end if; 48 | end process; 49 | 50 | output_to_readen<=input_reg; 51 | 52 | process(clk) 53 | begin 54 | if clk'event and clk='1' then 55 | output_to_datasel<=input_reg; 56 | end if; 57 | end process; 58 | 59 | end Behavioral; 60 | 61 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_RECEIV.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:16:57 11/30/2009 6 | -- Design Name: 7 | -- Module Name: COUNTER_11B_EN_RECEIV - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity COUNTER_11B_EN_RECEIV is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | count_en : in STD_LOGIC; 34 | value_O : inout STD_LOGIC_VECTOR (10 downto 0)); 35 | end COUNTER_11B_EN_RECEIV; 36 | 37 | architecture Behavioral of COUNTER_11B_EN_RECEIV is 38 | 39 | begin 40 | 41 | process(clk) 42 | begin 43 | if rst='1' then 44 | value_O<="00000000000"; 45 | else 46 | if clk'event and clk='1' then 47 | if count_en='1' then 48 | value_O<=value_O+"00000000001"; 49 | else 50 | value_O<=value_O; 51 | end if; 52 | end if; 53 | end if; 54 | end process; 55 | 56 | 57 | end Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_TRANS.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:16:57 11/30/2009 6 | -- Design Name: 7 | -- Module Name: COUNTER_11B_EN_TRANS - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity COUNTER_11B_EN_TRANS is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | count_en : in STD_LOGIC; 34 | value_O : inout STD_LOGIC_VECTOR (10 downto 0)); 35 | end COUNTER_11B_EN_TRANS; 36 | 37 | architecture Behavioral of COUNTER_11B_EN_TRANS is 38 | 39 | begin 40 | 41 | process(clk) 42 | begin 43 | if rst='1' then 44 | value_O<="11111110110"; 45 | else 46 | if clk'event and clk='1' then 47 | if count_en='1' then 48 | value_O<=value_O+"00000000001"; 49 | else 50 | value_O<=value_O; 51 | end if; 52 | end if; 53 | end if; 54 | end process; 55 | 56 | 57 | end Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_6B_LUT_FIFO_MODE.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 02:30:12 11/30/2009 6 | -- Design Name: 7 | -- Module Name: COUNTER_6B_LUT_FIFO_MODE - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity COUNTER_6B_LUT_FIFO_MODE is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing 34 | count_en : in STD_LOGIC; 35 | value_O : inout STD_LOGIC_VECTOR (5 downto 0)); 36 | end COUNTER_6B_LUT_FIFO_MODE; 37 | 38 | architecture Behavioral of COUNTER_6B_LUT_FIFO_MODE is 39 | 40 | begin 41 | 42 | process(clk) 43 | begin 44 | if rst='1' then 45 | if funct_sel='0' then 46 | value_O<=(others=>'0'); 47 | else 48 | value_O<="100111"; 49 | end if; 50 | else 51 | if clk'event and clk='1' then 52 | if count_en='1' then 53 | value_O<=value_O+"000001"; 54 | else 55 | value_O<=value_O; 56 | end if; 57 | end if; 58 | end if; 59 | end process; 60 | 61 | 62 | end Behavioral; 63 | 64 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/ENABLE_USER_DATA_TRANSMISSION.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12:05:48 12/04/2009 6 | -- Design Name: 7 | -- Module Name: ENABLE_USER_DATA_TRANSMISSION - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity ENABLE_USER_DATA_TRANSMISSION is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | start_usr_data_trans : in STD_LOGIC; 34 | stop_usr_data_trans : in STD_LOGIC; 35 | usr_data_sel : out STD_LOGIC); 36 | end ENABLE_USER_DATA_TRANSMISSION; 37 | 38 | architecture Behavioral of ENABLE_USER_DATA_TRANSMISSION is 39 | 40 | signal usr_data_sel_prev : std_logic :='0'; 41 | 42 | begin 43 | 44 | process(clk) 45 | begin 46 | if rst='1' then 47 | usr_data_sel<='0'; 48 | usr_data_sel_prev<='0'; 49 | else 50 | if clk'event and clk='1' then 51 | if (start_usr_data_trans='1' and usr_data_sel_prev='0') then 52 | usr_data_sel<='1'; 53 | usr_data_sel_prev<='1'; 54 | end if; 55 | if (stop_usr_data_trans='0' and usr_data_sel_prev='1') then -- stop_usr_data_trans is active low 56 | usr_data_sel<='0'; 57 | usr_data_sel_prev<='0'; 58 | end if; 59 | end if; 60 | end if; 61 | end process; 62 | 63 | end Behavioral; 64 | 65 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_LUT_INDEXER.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 22:11:55 11/27/2009 6 | -- Design Name: 7 | -- Module Name: IPV4_LUT_INDEXER - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity IPV4_LUT_INDEXER is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | transmit_enable : in STD_LOGIC; 34 | LUT_index : out STD_LOGIC_VECTOR (5 downto 0)); 35 | end IPV4_LUT_INDEXER; 36 | 37 | architecture Behavioral of IPV4_LUT_INDEXER is 38 | 39 | component dist_mem_64x8 is 40 | port ( 41 | clk : in STD_LOGIC := 'X'; 42 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 43 | qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) 44 | ); 45 | end component; 46 | 47 | component COUNTER_6B_LUT_FIFO_MODE is 48 | Port ( rst : in STD_LOGIC; 49 | clk : in STD_LOGIC; 50 | funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing -- only LUT support is used 51 | count_en : in STD_LOGIC; 52 | value_O : inout STD_LOGIC_VECTOR (5 downto 0)); 53 | end component; 54 | 55 | component comp_6b_equal is 56 | port ( 57 | qa_eq_b : out STD_LOGIC; 58 | clk : in STD_LOGIC := 'X'; 59 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 60 | b : in STD_LOGIC_VECTOR ( 5 downto 0 ) 61 | ); 62 | end component; 63 | 64 | signal count_en_sig , count_end , rst_counter: std_logic :='0'; 65 | signal count_val: std_logic_Vector(5 downto 0):=(others=>'0'); 66 | signal count_en_sig_comb : std_logic; 67 | constant lut_upper_address :std_logic_vector(5 downto 0):="100110"; -- position 38 68 | 69 | begin 70 | 71 | process(clk) 72 | begin 73 | if (rst='1' or count_end='1') then 74 | count_en_sig<='0'; 75 | rst_counter<='1'; 76 | else 77 | rst_counter<='0'; 78 | if clk'event and clk='1' then 79 | if (transmit_enable='1' and count_en_sig='0') then 80 | count_en_sig<='1'; 81 | end if; 82 | end if; 83 | end if; 84 | end process; 85 | 86 | LUT_END_CHECK : comp_6b_equal port map ( 87 | qa_eq_b =>count_end, 88 | clk =>clk, 89 | a =>count_val, 90 | b =>lut_upper_address 91 | 92 | ); 93 | 94 | count_en_sig_comb <=count_en_sig or transmit_enable; 95 | 96 | 97 | 98 | LUT_INDEXER_MODULE : COUNTER_6B_LUT_FIFO_MODE port map ( 99 | rst => rst_counter, 100 | clk => clk, 101 | funct_sel =>'0', -- for now only one function is supported 102 | count_en =>count_en_sig_comb, 103 | value_O =>count_val 104 | ); 105 | 106 | LUT_index<=count_val; 107 | 108 | 109 | end Behavioral; 110 | 111 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_PACKET_TRANSMITTER.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------------------- 2 | -- Copyright (C) 2010 Nikolaos Ch. Alachiotis -- 3 | -- -- 4 | -- Engineer: Nikolaos Ch. Alachiotis -- 5 | -- -- 6 | -- Contact: alachiot@cs.tum.edu -- 7 | -- n.alachiotis@gmail.com -- 8 | -- -- 9 | -- Create Date: 14:45:39 11/27/2009 -- 10 | -- Module Name: IPV4_PACKET_TRANSMITTER -- 11 | -- Target Devices: Virtex 5 FPGAs -- 12 | -- Tool versions: ISE 10.1 -- 13 | -- Description: This component can be used to send IPv4 Ethernet Packets. -- 14 | -- Additional Comments: The look-up table contains the header fields of the IP packet, -- 15 | -- so please keep in mind that you have to reinitialize this LUT. -- 16 | -- -- 17 | ----------------------------------------------------------------------------------------- 18 | library IEEE; 19 | use IEEE.STD_LOGIC_1164.ALL; 20 | use IEEE.STD_LOGIC_ARITH.ALL; 21 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 22 | 23 | ---- Uncomment the following library declaration if instantiating 24 | ---- any Xilinx primitives in this code. 25 | --library UNISIM; 26 | --use UNISIM.VComponents.all; 27 | 28 | entity IPV4_PACKET_TRANSMITTER is 29 | Port ( rst : in STD_LOGIC; 30 | clk_125MHz : in STD_LOGIC; 31 | transmit_start_enable : in STD_LOGIC; 32 | transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); 33 | usr_data_trans_phase_on : out STD_LOGIC; 34 | transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); 35 | start_of_frame_O : out STD_LOGIC; 36 | end_of_frame_O : out STD_LOGIC; 37 | source_ready : out STD_LOGIC; 38 | transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0) 39 | ); 40 | end IPV4_PACKET_TRANSMITTER; 41 | 42 | architecture Behavioral of IPV4_PACKET_TRANSMITTER is 43 | 44 | 45 | ----------------------------------------------------------------------------------------------------------------------------------------- 46 | ----------------------------------------------------------------------------------------------------------------------------------------- 47 | -- IPv4 PACKET STRUCTURE : -- 48 | -- Size | Description | Transmission Order | Position -- 49 | -- ----------------------------------------------------------------------------------------------------------- 50 | -- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT -- 51 | -- | X-X-X-X-X-X | | -- 52 | -- | | | -- 53 | -- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT -- 54 | -- | 11111111-11111111-11111111-11111111-... | | -- 55 | -- 2 bytes | Ethernet Type * | 12 13 | LUT -- 56 | -- | (fixed to 00001000-00000000 :=> | | -- 57 | -- | Internet Protocol, Version 4 (IPv4)) | | -- 58 | -- -- Start of IPv4 Packet ** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | -- 59 | -- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length | 14 | LUT -- 60 | -- | 0100 0101 | | -- 61 | -- 1 byte | Differentiated Services | 15 | LUT -- 62 | -- | 00000000 | | -- 63 | -- 2 bytes | Total Length | 16 17 | REG -- 64 | -- | 00000000-00100100 (base: 20 + 8 + datalength)| | -- 65 | -- 2 bytes | Identification | 18 19 | LUT -- 66 | -- | 00000000-00000000 | | -- 67 | -- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset | 20 21 | LUT -- 68 | -- | 010 - 0000000000000 | | -- 69 | -- 1 byte | Time to Live | 22 | LUT -- 70 | -- | 01000000 | | -- 71 | -- 1 byte | Protocol | 23 | LUT -- 72 | -- | 00010001 | | -- 73 | -- 2 bytes | Header Checksum | 24 25 | REG -- 74 | -- | 10110111 01111101 (base value) | | -- 75 | -- 4 bytes | Source IP Address | 26 27 28 29 | LUT -- 76 | -- | X-X-X-X - FPGA | | -- 77 | -- 4 bytes | Destin IP Address | 30 31 32 33 | LUT -- 78 | -- | X-X-X-X - PC | | -- 79 | -- -- Start of UDP Packet *** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | -- 80 | -- 2 bytes | Source Port | 34 35 | LUT -- 81 | -- | X-X | | -- 82 | -- 2 bytes | Destination Port | 36 37 | LUT -- 83 | -- | X-X | | -- 84 | -- 2 bytes | Length | 38 39 | REG -- 85 | -- | 00000000 - 00010000 (8 + # data bytes) | | -- 86 | -- 2 bytes | Checksum | 40 41 | LUT -- 87 | -- | 00000000 - 00000000 | | -- 88 | -- X bytes | Data | 42 .. X | from input -- 89 | -- | | | -- 90 | ----------------------------------------------------------------------------------------------------------------------------------------- 91 | ----------------------------------------------------------------------------------------------------------------------------------------- 92 | 93 | -- * More details about the Ethernet Type value you can find here: 94 | -- http://en.wikipedia.org/wiki/Ethertype 95 | 96 | -- ** More details about the Internet Protocol, Version 4 (IPv4) you can find here: 97 | -- http://en.wikipedia.org/wiki/IPv4 98 | 99 | -- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here: 100 | -- http://en.wikipedia.org/wiki/User_Datagram_Protocol 101 | 102 | ----------------------------------------------------------------------------------------------------------------------------------------- 103 | ----------------------------------------------------------------------------------------------------------------------------------------- 104 | 105 | 106 | 107 | -------------------------------------------------------------------------------------- 108 | -- COMPONENT DECLARATION 109 | -------------------------------------------------------------------------------------- 110 | 111 | component REG_16B_WREN is 112 | Port ( rst : in STD_LOGIC; 113 | clk : in STD_LOGIC; 114 | wren : in STD_LOGIC; 115 | input : in STD_LOGIC_VECTOR (15 downto 0); 116 | output : out STD_LOGIC_VECTOR (15 downto 0)); 117 | end component; 118 | 119 | component IPV4_LUT_INDEXER is 120 | Port ( rst : in STD_LOGIC; 121 | clk : in STD_LOGIC; 122 | transmit_enable : in STD_LOGIC; 123 | LUT_index : out STD_LOGIC_VECTOR (5 downto 0)); 124 | end component; 125 | 126 | component dist_mem_64x8 is 127 | port ( 128 | clk : in STD_LOGIC := 'X'; 129 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 130 | qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) 131 | ); 132 | end component; 133 | 134 | component OVERRIDE_LUT_CONTROL is 135 | Port ( clk : in STD_LOGIC; 136 | input_addr : in STD_LOGIC_VECTOR (5 downto 0); 137 | sel_total_length_MSBs : out STD_LOGIC; 138 | sel_total_length_LSBs : out STD_LOGIC; 139 | sel_header_checksum_MSBs : out STD_LOGIC; 140 | sel_header_checksum_LSBs : out STD_LOGIC; 141 | sel_length_MSBs : out STD_LOGIC; 142 | sel_length_LSBs : out STD_LOGIC 143 | ); 144 | end component; 145 | 146 | component TARGET_EOF is 147 | Port ( rst : in STD_LOGIC; 148 | clk : in STD_LOGIC; 149 | start : in STD_LOGIC; 150 | total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0); 151 | eof_O : out STD_LOGIC); 152 | end component; 153 | 154 | component ENABLE_USER_DATA_TRANSMISSION is 155 | Port ( rst : in STD_LOGIC; 156 | clk : in STD_LOGIC; 157 | start_usr_data_trans : in STD_LOGIC; 158 | stop_usr_data_trans : in STD_LOGIC; 159 | usr_data_sel : out STD_LOGIC); 160 | end component; 161 | 162 | component ALLOW_ZERO_UDP_CHECKSUM is 163 | Port ( clk : in STD_LOGIC; 164 | input : in STD_LOGIC; 165 | output_to_readen : out STD_LOGIC; 166 | output_to_datasel : out STD_LOGIC); 167 | end component; 168 | 169 | 170 | -------------------------------------------------------------------------------------- 171 | -- SIGNAL DECLARATION 172 | -------------------------------------------------------------------------------------- 173 | 174 | signal transmit_start_enable_tmp, 175 | sel_total_length_MSBs, 176 | sel_total_length_LSBs, 177 | sel_header_checksum_MSBs, 178 | sel_header_checksum_LSBs, 179 | sel_length_MSBs, 180 | sel_length_LSBs, 181 | lut_out_sel, 182 | source_ready_previous_value, 183 | end_of_frame_O_tmp, 184 | transmit_start_enable_reg, 185 | usr_data_sel_sig, 186 | start_usr_data_read, 187 | start_usr_data_trans : STD_LOGIC; 188 | 189 | signal LUT_addr : STD_LOGIC_VECTOR(5 downto 0); 190 | 191 | signal transmit_data_input_bus_tmp, 192 | transmit_data_output_bus_tmp, 193 | sel_total_length_MSBs_vec, 194 | sel_total_length_LSBs_vec, 195 | sel_header_checksum_MSBs_vec, 196 | sel_header_checksum_LSBs_vec, 197 | sel_length_MSBs_vec, 198 | sel_length_LSBs_vec, 199 | lut_out_sel_vec, 200 | transmit_data_output_bus_no_usr_data, 201 | usr_data_not_sel_vec, 202 | usr_data_sel_vec : STD_LOGIC_VECTOR(7 downto 0); 203 | 204 | signal transmit_data_length_tmp, 205 | data_length_regout, 206 | tmp_total_length, 207 | tmp_header_checksum, 208 | tmp_header_checksum_baseval, 209 | tmp_length : STD_LOGIC_VECTOR(15 downto 0); 210 | 211 | 212 | begin 213 | 214 | transmit_start_enable_tmp<=transmit_start_enable; 215 | 216 | transmit_data_length_tmp<=transmit_data_length; 217 | 218 | transmit_data_input_bus_tmp<=transmit_data_input_bus; 219 | 220 | ---------------------------------------------------------------------------------------------------- 221 | -- start_of_frame_O signal 222 | ---------------------------------------------------------------------------------------------------- 223 | -- Description: start_of_frame_O is active low 224 | -- We connect it to the delayed for one clock cycle transmit_start_enable input signal 225 | -- through a NOT gate since transmit_start_enable is active high. 226 | 227 | process(clk_125MHz) 228 | begin 229 | if clk_125MHz'event and clk_125MHz='1' then 230 | transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle. 231 | end if; 232 | end process; 233 | 234 | start_of_frame_O<=not transmit_start_enable_reg; 235 | 236 | ---------------------------------------------------------------------------------------------------- 237 | -- end_of_frame_O signal 238 | ---------------------------------------------------------------------------------------------------- 239 | -- Description: end_of_frame_O is active low 240 | -- The TARGET_EOF module targets the last byte of the packet that is being transmitted 241 | -- based on a counter that counts the number of transmitted bytes and a comparator that 242 | -- detects the last byte which is the th byte. 243 | 244 | TARGET_EOF_port_map: TARGET_EOF port map 245 | ( 246 | rst =>rst, 247 | clk =>clk_125MHz, 248 | start =>transmit_start_enable_reg, 249 | total_length_from_reg =>tmp_total_length, 250 | eof_O =>end_of_frame_O_tmp 251 | ); 252 | 253 | --* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the 254 | -- IPv4 packet. (MAC addresses + Ethernet Type) 255 | 256 | end_of_frame_O<=end_of_frame_O_tmp; 257 | 258 | ---------------------------------------------------------------------------------------------------- 259 | -- source_ready signal 260 | ---------------------------------------------------------------------------------------------------- 261 | -- Description: source_ready is active low 262 | -- This signal is idle(high). (based on rst and end_of_frame_O_tmp). 263 | -- This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp). 264 | 265 | process(clk_125MHz) 266 | begin 267 | if rst='1' then 268 | source_ready<='1'; 269 | source_ready_previous_value<='1'; 270 | else 271 | if clk_125MHz'event and clk_125MHz='1' then 272 | if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then 273 | source_ready<='0'; 274 | source_ready_previous_value<='0'; 275 | else 276 | if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then 277 | source_ready<='1'; 278 | source_ready_previous_value<='1'; 279 | end if; 280 | end if; 281 | end if; 282 | end if; 283 | end process; 284 | 285 | ---------------------------------------------------------------------------------------------------- 286 | -- transmit_data_output_bus 287 | ---------------------------------------------------------------------------------------------------- 288 | ---------------------------------------------------------------------------------------------------- 289 | -- Component Name: REG_16B_WREN 290 | -- Instance Name: NUMBER_OR_DATA_IN_BYTES_REGISTER 291 | -- Description: Register that holds the number of bytes of input data 292 | -- that will be transmitted in the packet. 293 | ---------------------------------------------------------------------------------------------------- 294 | NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map 295 | ( 296 | rst =>rst, 297 | clk =>clk_125MHz, 298 | wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren. 299 | input =>transmit_data_length_tmp, 300 | output =>data_length_regout 301 | ); 302 | ---------------------------------------------------------------------------------------------------- 303 | 304 | tmp_total_length<="0000000000011100" + data_length_regout; 305 | 306 | tmp_header_checksum_baseval<="1011011101111101"; -- CHANGE VALUE! : You have to change this value! 307 | tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout; 308 | 309 | tmp_length<="0000000000001000" + data_length_regout; 310 | 311 | ---------------------------------------------------------------------------------------------------- 312 | 313 | ---------------------------------------------------------------------------------------------------- 314 | -- Component Name: IPV4_LUT_INDEXER 315 | -- Instance Name: IPV4_LUT_INDEXER_port_map 316 | -- Description: When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the 317 | -- addresses to the LUT that contains the header section of the IP packet. 318 | ---------------------------------------------------------------------------------------------------- 319 | IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map 320 | ( 321 | rst =>rst, 322 | clk =>clk_125MHz, 323 | transmit_enable =>transmit_start_enable_tmp, 324 | LUT_index =>LUT_addr 325 | ); 326 | ---------------------------------------------------------------------------------------------------- 327 | 328 | ---------------------------------------------------------------------------------------------------- 329 | -- Component Name: dist_mem_64x8 330 | -- Instance Name: LUT_MEM 331 | -- Description: LUT that contains the header section. 332 | ---------------------------------------------------------------------------------------------------- 333 | LUT_MEM : dist_mem_64x8 port map 334 | ( 335 | clk =>clk_125MHz, 336 | a =>LUT_addr, 337 | qspo =>transmit_data_output_bus_tmp 338 | ); 339 | ---------------------------------------------------------------------------------------------------- 340 | 341 | ---------------------------------------------------------------------------------------------------- 342 | -- Component Name: OVERRIDE_LUT_CONTROL 343 | -- Instance Name: OVERRIDE_LUT_CONTROL_port_map 344 | -- Description: Decides whether the output byte will come from the LUT or not. 345 | ---------------------------------------------------------------------------------------------------- 346 | OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map 347 | ( 348 | clk =>clk_125MHz, 349 | input_addr =>LUT_addr, 350 | sel_total_length_MSBs =>sel_total_length_MSBs, 351 | sel_total_length_LSBs =>sel_total_length_LSBs, 352 | sel_header_checksum_MSBs =>sel_header_checksum_MSBs, 353 | sel_header_checksum_LSBs =>sel_header_checksum_LSBs, 354 | sel_length_MSBs =>sel_length_MSBs, 355 | sel_length_LSBs =>sel_length_LSBs 356 | ); 357 | ---------------------------------------------------------------------------------------------------- 358 | 359 | ---------------------------------------------------------------------------------------------------- 360 | -- MUX 7 to 1 361 | sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs); 362 | sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs); 363 | sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs); 364 | sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs); 365 | sel_length_MSBs_vec<=(others=>sel_length_MSBs); 366 | sel_length_LSBs_vec<=(others=>sel_length_LSBs); 367 | lut_out_sel_vec <= (others=>lut_out_sel); 368 | 369 | lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and 370 | (not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and 371 | (not sel_length_MSBs) and (not sel_length_LSBs); 372 | 373 | -- MUX output 374 | transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or 375 | (tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or 376 | (tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or 377 | (tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or 378 | (tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or 379 | (tmp_length(15 downto 8) and sel_length_MSBs_vec) or 380 | (tmp_length(7 downto 0) and sel_length_LSBs_vec); 381 | ---------------------------------------------------------------------------------------------------- 382 | 383 | ---------------------------------------------------------------------------------------------------- 384 | -- Component Name: ALLOW_ZERO_UDP_CHECKSUM 385 | -- Instance Name: ALLOW_ZERO_UDP_CHECKSUM_port_map 386 | -- Description: Delays the user data transmition phase in order to transmit two bytes with zero 387 | -- first. 388 | ---------------------------------------------------------------------------------------------------- 389 | ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map 390 | ( 391 | clk =>clk_125MHz, 392 | input =>sel_length_LSBs, 393 | output_to_readen =>start_usr_data_read, 394 | output_to_datasel =>start_usr_data_trans 395 | ); 396 | ---------------------------------------------------------------------------------------------------- 397 | 398 | ---------------------------------------------------------------------------------------------------- 399 | -- Component Name: ENABLE_USER_DATA_TRANSMISSION 400 | -- Instance Name: ENABLE_USER_DATA_READ_port_map 401 | -- Description: Sets usr_data_trans_phase_on signal one cycle before the transmittion of the 402 | -- first user byte. 403 | ---------------------------------------------------------------------------------------------------- 404 | ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map 405 | ( rst =>rst, 406 | clk =>clk_125MHz, 407 | start_usr_data_trans =>start_usr_data_read, 408 | stop_usr_data_trans =>end_of_frame_O_tmp, 409 | usr_data_sel =>usr_data_trans_phase_on 410 | ); 411 | ---------------------------------------------------------------------------------------------------- 412 | 413 | ---------------------------------------------------------------------------------------------------- 414 | -- Component Name: ENABLE_USER_DATA_TRANSMISSION 415 | -- Instance Name: ENABLE_USER_DATA_TRANSMISSION_port_map 416 | -- Description: Sets usr_data_sel_sig signal to select user data for transmittion. 417 | ---------------------------------------------------------------------------------------------------- 418 | ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map 419 | ( rst =>rst, 420 | clk =>clk_125MHz, 421 | start_usr_data_trans =>start_usr_data_trans, 422 | stop_usr_data_trans =>end_of_frame_O_tmp, 423 | usr_data_sel =>usr_data_sel_sig 424 | ); 425 | ---------------------------------------------------------------------------------------------------- 426 | 427 | ---------------------------------------------------------------------------------------------------- 428 | -- MUX 2 to 1 429 | usr_data_not_sel_vec<=(others=>not usr_data_sel_sig); 430 | usr_data_sel_vec<=(others=>usr_data_sel_sig); 431 | 432 | -- MUX output 433 | transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or 434 | (transmit_data_input_bus and usr_data_sel_vec); 435 | ---------------------------------------------------------------------------------------------------- 436 | 437 | end Behavioral; 438 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPv4_PACKET_RECEIVER.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------------------- 2 | -- Copyright (C) 2010 Nikolaos Ch. Alachiotis -- 3 | -- -- 4 | -- Engineer: Nikolaos Ch. Alachiotis -- 5 | -- -- 6 | -- Contact: alachiot@cs.tum.edu -- 7 | -- n.alachiotis@gmail.com -- 8 | -- -- 9 | -- Create Date: 14:32:06 02/07/2010 -- 10 | -- Module Name: IPv4_PACKET_RECEIVER -- 11 | -- Target Devices: Virtex 5 FPGAs -- 12 | -- Tool versions: ISE 10.1 -- 13 | -- Description: This component can be used to receive IPv4 Ethernet Packets. -- 14 | -- Additional Comments: -- 15 | -- -- 16 | -- The receiver does not operate properly for data section of 1 or 2 bytes only. -- 17 | -- -- 18 | ----------------------------------------------------------------------------------------- 19 | 20 | 21 | library IEEE; 22 | use IEEE.STD_LOGIC_1164.ALL; 23 | use IEEE.STD_LOGIC_ARITH.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | 26 | ---- Uncomment the following library declaration if instantiating 27 | ---- any Xilinx primitives in this code. 28 | --library UNISIM; 29 | --use UNISIM.VComponents.all; 30 | 31 | entity IPv4_PACKET_RECEIVER is 32 | Port ( rst : in STD_LOGIC; 33 | clk_125Mhz : in STD_LOGIC; 34 | rx_sof : in STD_LOGIC; 35 | rx_eof : in STD_LOGIC; 36 | input_bus : in STD_LOGIC_VECTOR(7 downto 0); 37 | valid_out_usr_data : out STD_LOGIC; 38 | usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)); 39 | end IPv4_PACKET_RECEIVER; 40 | 41 | architecture Behavioral of IPv4_PACKET_RECEIVER is 42 | 43 | component PACKET_RECEIVER_FSM is 44 | Port ( 45 | rst : in STD_LOGIC; 46 | clk : in STD_LOGIC; 47 | 48 | -- Signals from EMAC 49 | rx_sof: in STD_LOGIC; -- active low input 50 | rx_eof: in STD_LOGIC; -- active low input 51 | 52 | -- Signals to Counter and Comparator 53 | sel_comp_Bval: out STD_LOGIC; 54 | comp_Bval: out STD_LOGIC_VECTOR(10 downto 0); 55 | rst_count : out STD_LOGIC; 56 | en_count : out STD_LOGIC; 57 | 58 | -- Signal from Comparator 59 | comp_eq: in STD_LOGIC; 60 | 61 | -- Signals to Length Register 62 | wren_MSbyte: out STD_LOGIC; 63 | wren_LSbyte: out STD_LOGIC; 64 | 65 | -- Signal to user interface 66 | valid_out_usr_data : out STD_LOGIC); 67 | end component; 68 | 69 | component REG_8b_wren is 70 | Port ( rst : in STD_LOGIC; 71 | clk : in STD_LOGIC; 72 | wren : in STD_LOGIC; 73 | input_val : in STD_LOGIC_VECTOR (7 downto 0); 74 | output_val : inout STD_LOGIC_VECTOR(7 downto 0)); 75 | end component; 76 | 77 | component COUNTER_11B_EN_RECEIV is 78 | Port ( rst : in STD_LOGIC; 79 | clk : in STD_LOGIC; 80 | count_en : in STD_LOGIC; 81 | value_O : inout STD_LOGIC_VECTOR (10 downto 0)); 82 | end component; 83 | 84 | component comp_11b_equal is 85 | port ( 86 | qa_eq_b : out STD_LOGIC; 87 | clk : in STD_LOGIC := 'X'; 88 | a : in STD_LOGIC_VECTOR ( 10 downto 0 ); 89 | b : in STD_LOGIC_VECTOR ( 10 downto 0 ) 90 | ); 91 | end component; 92 | 93 | signal sel_comp_Bval, 94 | rst_count, 95 | en_count, 96 | comp_eq, 97 | wren_MSbyte, 98 | wren_LSbyte: STD_LOGIC; 99 | 100 | signal MSbyte_reg_val_out, 101 | LSbyte_reg_val_out : STD_LOGIC_VECTOR(7 downto 0); 102 | 103 | signal counter_val, 104 | match_val, 105 | comp_Bval, 106 | comp_sel_val_vec, 107 | comp_n_sel_val_vec, 108 | length_val: STD_LOGIC_VECTOR(10 downto 0); 109 | 110 | constant length_offest : STD_LOGIC_VECTOR(7 downto 0):="00001010"; 111 | -- This value is formed as 2 (1 clock the latency of comparator and 1 clock fro changing the FSM state) + 8 (number of bytes of UDP header section) 112 | 113 | begin 114 | 115 | usr_data_output_bus<=input_bus; 116 | 117 | PACKET_RECEIVER_FSM_port_map: PACKET_RECEIVER_FSM Port Map 118 | ( 119 | rst => rst, 120 | clk => clk_125MHz, 121 | 122 | rx_sof => rx_sof, 123 | rx_eof => rx_eof, 124 | 125 | sel_comp_Bval => sel_comp_Bval, 126 | comp_Bval => comp_Bval, 127 | rst_count => rst_count, 128 | en_count => en_count, 129 | 130 | comp_eq => comp_eq, 131 | 132 | wren_MSbyte => wren_MSbyte, 133 | wren_LSbyte => wren_LSbyte, 134 | 135 | valid_out_usr_data => valid_out_usr_data 136 | ); 137 | 138 | MSbyte_REG: REG_8b_wren Port Map 139 | ( 140 | rst => rst, 141 | clk => clk_125MHz, 142 | wren => wren_MSbyte, 143 | input_val => input_bus, 144 | output_val =>MSbyte_reg_val_out 145 | ); 146 | 147 | LSbyte_REG: REG_8b_wren Port Map 148 | ( 149 | rst => rst, 150 | clk => clk_125MHz, 151 | wren => wren_LSbyte, 152 | input_val => input_bus, 153 | output_val =>LSbyte_reg_val_out 154 | ); 155 | 156 | COUNTER_11B_EN_port_map: COUNTER_11B_EN_RECEIV Port Map 157 | ( 158 | rst => rst_count, 159 | clk => clk_125MHz, 160 | count_en => en_count, 161 | value_O => counter_val 162 | ); 163 | 164 | Comp_11b_equal_port_map: Comp_11b_equal Port Map 165 | ( 166 | qa_eq_b => comp_eq, 167 | clk => clk_125MHz, 168 | a => counter_val, 169 | b => match_val 170 | ); 171 | 172 | length_val(7 downto 0)<= LSbyte_reg_val_out-length_offest; 173 | length_val(10 downto 8)<= MSbyte_reg_val_out (2 downto 0); 174 | 175 | comp_sel_val_vec<=(others=> sel_comp_Bval); 176 | comp_n_sel_val_vec<= (others=> not sel_comp_Bval); 177 | 178 | match_val<= (comp_sel_val_vec and length_val) or (comp_n_sel_val_vec and comp_Bval); 179 | 180 | 181 | end Behavioral; 182 | 183 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/OVERRIDE_LUT_CONTROL.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:09:25 11/30/2009 6 | -- Design Name: 7 | -- Module Name: OVERRIDE_LUT_CONTROL - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity OVERRIDE_LUT_CONTROL is 31 | Port ( clk : in STD_LOGIC; 32 | input_addr : in STD_LOGIC_VECTOR (5 downto 0); 33 | sel_total_length_MSBs : out STD_LOGIC; 34 | sel_total_length_LSBs : out STD_LOGIC; 35 | sel_header_checksum_MSBs : out STD_LOGIC; 36 | sel_header_checksum_LSBs : out STD_LOGIC; 37 | sel_length_MSBs : out STD_LOGIC; 38 | sel_length_LSBs : out STD_LOGIC 39 | ); 40 | end OVERRIDE_LUT_CONTROL; 41 | 42 | architecture Behavioral of OVERRIDE_LUT_CONTROL is 43 | 44 | component comp_6b_equal is 45 | port ( 46 | qa_eq_b : out STD_LOGIC; 47 | clk : in STD_LOGIC := 'X'; 48 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 49 | b : in STD_LOGIC_VECTOR ( 5 downto 0 ) 50 | ); 51 | end component; 52 | 53 | constant total_length_addr1 : std_logic_vector(5 downto 0):="010000"; 54 | constant total_length_addr2 : std_logic_vector(5 downto 0):="010001"; 55 | 56 | constant header_checksum_addr1 : std_logic_vector(5 downto 0):="011000"; 57 | constant header_checksum_addr2 : std_logic_vector(5 downto 0):="011001"; 58 | 59 | constant length_addr1 : std_logic_vector(5 downto 0):="100110"; 60 | constant length_addr2 : std_logic_vector(5 downto 0):="100111"; 61 | 62 | 63 | signal sel_header_checksum_MSBs_tmp : std_logic; 64 | signal sel_total_length_MSBs_tmp : std_logic; 65 | signal sel_length_MSBs_tmp : std_logic; 66 | 67 | begin 68 | 69 | TARGET_TOTAL_LENGTH_1 : comp_6b_equal port map (sel_total_length_MSBs_tmp,clk,input_addr,total_length_addr1); 70 | 71 | process(clk) 72 | begin 73 | if clk'event and clk='1' then 74 | sel_total_length_LSBs<=sel_total_length_MSBs_tmp; 75 | end if; 76 | end process; 77 | sel_total_length_MSBs<=sel_total_length_MSBs_tmp; 78 | 79 | --TARGET_TOTAL_LENGTH_2 : comp_6b_equal port map (sel_total_length_LSBs,clk,input_addr,total_length_addr2); 80 | 81 | TARGET_HEADER_CHECKSUM_1 : comp_6b_equal port map (sel_header_checksum_MSBs_tmp,clk,input_addr,header_checksum_addr1); 82 | process(clk) 83 | begin 84 | if clk'event and clk='1' then 85 | sel_header_checksum_LSBs<=sel_header_checksum_MSBs_tmp; 86 | end if; 87 | end process; 88 | 89 | sel_header_checksum_MSBs<=sel_header_checksum_MSBs_tmp; 90 | 91 | 92 | 93 | --TARGET_HEADER_CHECKSUM_2 : comp_6b_equal port map (sel_header_checksum_LSBs,clk,input_addr,header_checksum_addr2); 94 | 95 | TARGET_LENGTH_1 : comp_6b_equal port map (sel_length_MSBs_tmp,clk,input_addr,length_addr1); 96 | 97 | process(clk) 98 | begin 99 | if clk'event and clk='1' then 100 | sel_length_LSBs<=sel_length_MSBs_tmp; 101 | end if; 102 | end process; 103 | 104 | sel_length_MSBs<=sel_length_MSBs_tmp; 105 | --TARGET_LENGTH_2 : comp_6b_equal port map (sel_length_LSBs,clk,input_addr,length_addr2); 106 | 107 | end Behavioral; 108 | 109 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/PACKET_RECEIVER_FSM.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 03:48:34 02/07/2010 6 | -- Design Name: 7 | -- Module Name: PACKET_RECEIVER_FSM - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity PACKET_RECEIVER_FSM is 31 | Port ( 32 | rst : in STD_LOGIC; 33 | clk : in STD_LOGIC; 34 | 35 | -- Signals from EMAC 36 | rx_sof: in STD_LOGIC; -- active low input 37 | rx_eof: in STD_LOGIC; -- active low input 38 | 39 | -- Signals to Counter and Comparator 40 | sel_comp_Bval: out STD_LOGIC; 41 | comp_Bval: out STD_LOGIC_VECTOR(10 downto 0); 42 | rst_count : out STD_LOGIC; 43 | en_count : out STD_LOGIC; 44 | 45 | -- Signal from Comparator 46 | comp_eq: in STD_LOGIC; 47 | 48 | -- Signals to Length Register 49 | wren_MSbyte: out STD_LOGIC; 50 | wren_LSbyte: out STD_LOGIC; 51 | 52 | -- Signal to user interface 53 | valid_out_usr_data: out STD_LOGIC); 54 | end PACKET_RECEIVER_FSM; 55 | 56 | architecture Behavioral of PACKET_RECEIVER_FSM is 57 | 58 | TYPE state is (rst_state, 59 | idle_state, 60 | detect_n_store_usr_length_MSbyte_state, 61 | store_usr_length_LSbyte_state, 62 | checksum_gap_state, 63 | receive_usr_data_state); 64 | 65 | signal current_st,next_st: state; 66 | 67 | constant udp_length_match_cycle : std_logic_vector(10 downto 0):="00000100100"; -- UDP length MSbyte - 2 68 | constant udp_checksum_skip : std_logic_vector(10 downto 0):="00000000001"; 69 | constant gnd_vec : std_logic_vector(10 downto 0):="00000000000"; 70 | begin 71 | 72 | process(current_st,rx_sof,rx_eof,comp_eq) 73 | begin 74 | case current_st is 75 | 76 | 77 | when rst_state => 78 | 79 | sel_comp_Bval<='0'; 80 | comp_Bval<=gnd_vec; 81 | rst_count<='1'; 82 | en_count<='0'; 83 | 84 | wren_MSbyte<='0'; 85 | wren_LSbyte<='0'; 86 | 87 | valid_out_usr_data<='0'; 88 | 89 | next_st<=idle_state; 90 | 91 | when idle_state => 92 | 93 | if rx_sof='0' then -- rx_sof is active low 94 | sel_comp_Bval<='0'; 95 | comp_Bval<=udp_length_match_cycle; 96 | rst_count<='1'; 97 | en_count<='0'; 98 | 99 | wren_MSbyte<='0'; 100 | wren_LSbyte<='0'; 101 | 102 | valid_out_usr_data<='0'; 103 | 104 | next_st<=detect_n_store_usr_length_MSbyte_state; 105 | 106 | else 107 | sel_comp_Bval<='0'; 108 | comp_Bval<=gnd_vec; 109 | rst_count<='0'; 110 | en_count<='0'; 111 | 112 | wren_MSbyte<='0'; 113 | wren_LSbyte<='0'; 114 | 115 | valid_out_usr_data<='0'; 116 | 117 | next_st<=idle_state; 118 | end if; 119 | 120 | when detect_n_store_usr_length_MSbyte_state => 121 | 122 | if comp_eq='1' then -- comp_eq is active high 123 | sel_comp_Bval<='0'; 124 | comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field 125 | rst_count<='1'; 126 | en_count<='0'; 127 | 128 | wren_MSbyte<='1'; 129 | wren_LSbyte<='0'; 130 | 131 | valid_out_usr_data<='0'; 132 | 133 | next_st<=store_usr_length_LSbyte_state; 134 | 135 | else 136 | sel_comp_Bval<='0'; 137 | comp_Bval<=udp_length_match_cycle; 138 | rst_count<='0'; 139 | en_count<='1'; 140 | 141 | wren_MSbyte<='0'; 142 | wren_LSbyte<='0'; 143 | 144 | valid_out_usr_data<='0'; 145 | 146 | next_st<=detect_n_store_usr_length_MSbyte_state; 147 | end if; 148 | 149 | when store_usr_length_LSbyte_state => 150 | 151 | sel_comp_Bval<='0'; 152 | comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field 153 | rst_count<='0'; 154 | en_count<='1'; 155 | 156 | wren_MSbyte<='0'; 157 | wren_LSbyte<='1'; 158 | 159 | valid_out_usr_data<='0'; 160 | 161 | next_st<=checksum_gap_state; 162 | 163 | when checksum_gap_state => 164 | 165 | if comp_eq='1' then -- comp_eq is active high 166 | sel_comp_Bval<='1'; 167 | comp_Bval<=gnd_vec; 168 | rst_count<='1'; 169 | en_count<='0'; 170 | 171 | wren_MSbyte<='0'; 172 | wren_LSbyte<='0'; 173 | 174 | valid_out_usr_data<='0'; 175 | 176 | next_st<=receive_usr_data_state; 177 | 178 | else 179 | sel_comp_Bval<='0'; 180 | comp_Bval<=udp_checksum_skip; 181 | rst_count<='0'; 182 | en_count<='1'; 183 | 184 | wren_MSbyte<='0'; 185 | wren_LSbyte<='0'; 186 | 187 | valid_out_usr_data<='0'; 188 | 189 | next_st<=checksum_gap_state; 190 | end if; 191 | 192 | when receive_usr_data_state => 193 | 194 | if (comp_eq='1' or rx_eof='0') then -- comp_eq is active high rx_eof is active-low 195 | sel_comp_Bval<='0'; 196 | comp_Bval<=udp_length_match_cycle; 197 | rst_count<='1'; 198 | en_count<='0'; 199 | 200 | wren_MSbyte<='0'; 201 | wren_LSbyte<='0'; 202 | 203 | valid_out_usr_data<='1'; 204 | 205 | next_st<=idle_state; 206 | 207 | else 208 | sel_comp_Bval<='1'; 209 | comp_Bval<=gnd_vec; 210 | rst_count<='0'; 211 | en_count<='1'; 212 | 213 | wren_MSbyte<='0'; 214 | wren_LSbyte<='0'; 215 | 216 | valid_out_usr_data<='1'; 217 | 218 | next_st<=receive_usr_data_state; 219 | end if; 220 | 221 | 222 | end case; 223 | end process; 224 | 225 | 226 | 227 | 228 | process(clk) 229 | begin 230 | if (rst='1') then 231 | current_st<= rst_state; 232 | elsif (clk'event and clk='1') then 233 | current_st <= next_st; 234 | end if; 235 | end process; 236 | 237 | end Behavioral; 238 | 239 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_16B_WREN.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 21:15:16 11/27/2009 6 | -- Design Name: 7 | -- Module Name: REG_16B_WREN - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 16bit wide Register with write enable option. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity REG_16B_WREN is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | wren : in STD_LOGIC; 34 | input : in STD_LOGIC_VECTOR (15 downto 0); 35 | output : out STD_LOGIC_VECTOR (15 downto 0)); 36 | end REG_16B_WREN; 37 | 38 | architecture Behavioral of REG_16B_WREN is 39 | 40 | begin 41 | 42 | process(clk) 43 | begin 44 | if rst='1' then 45 | output<="0000000000000000"; 46 | else 47 | if clk'event and clk='1' then 48 | if wren='1' then 49 | output<=input; 50 | end if; 51 | end if; 52 | end if; 53 | end process; 54 | 55 | end Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_8b_wren.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:40:03 02/07/2010 6 | -- Design Name: 7 | -- Module Name: REG_8b_wren - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity REG_8b_wren is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | wren : in STD_LOGIC; 34 | input_val : in STD_LOGIC_VECTOR (7 downto 0); 35 | output_val : inout STD_LOGIC_VECTOR(7 downto 0)); 36 | end REG_8b_wren; 37 | 38 | architecture Behavioral of REG_8b_wren is 39 | 40 | begin 41 | 42 | process(clk) 43 | begin 44 | if rst='1' then 45 | output_val<="00000000"; 46 | else 47 | if clk'event and clk='1' then 48 | if wren='1' then 49 | output_val<=input_val; 50 | end if; 51 | end if; 52 | end if; 53 | end process; 54 | 55 | end Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/TARGET_EOF.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:22:56 11/30/2009 6 | -- Design Name: 7 | -- Module Name: TARGET_EOF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity TARGET_EOF is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | start : in STD_LOGIC; 34 | total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0); 35 | eof_O : out STD_LOGIC); 36 | end TARGET_EOF; 37 | 38 | architecture Behavioral of TARGET_EOF is 39 | 40 | signal count_end : std_logic:='0'; 41 | signal count_en_sig : std_logic:='0'; 42 | signal rst_counter : std_logic:='0'; 43 | 44 | component COUNTER_11B_EN_TRANS is 45 | Port ( rst : in STD_LOGIC; 46 | clk : in STD_LOGIC; 47 | count_en : in STD_LOGIC; 48 | value_O : inout STD_LOGIC_VECTOR (10 downto 0)); 49 | end component; 50 | 51 | signal value_O_tmp : std_logic_vector(10 downto 0); 52 | 53 | component comp_11b_equal is 54 | port ( 55 | qa_eq_b : out STD_LOGIC; 56 | clk : in STD_LOGIC := 'X'; 57 | a : in STD_LOGIC_VECTOR ( 10 downto 0 ); 58 | b : in STD_LOGIC_VECTOR ( 10 downto 0 ) 59 | ); 60 | end component; 61 | 62 | signal last_byte,last_byte_reg_in,last_byte_reg_out : std_logic; 63 | 64 | begin 65 | 66 | process(clk) 67 | begin 68 | if (rst='1' or count_end='1') then 69 | count_en_sig<='0'; 70 | rst_counter<='1'; 71 | else 72 | rst_counter<='0'; 73 | if clk'event and clk='1' then 74 | if (start='1' and count_en_sig='0') then 75 | count_en_sig<='1'; 76 | end if; 77 | end if; 78 | end if; 79 | end process; 80 | 81 | 82 | COUNT_TRANFERED_BYTES : COUNTER_11B_EN_TRANS port map 83 | ( rst =>rst_counter, 84 | clk =>clk, 85 | count_en => count_en_sig, 86 | value_O =>value_O_tmp 87 | ); 88 | 89 | COMP_TO_TARGET_LAST_BYTE : comp_11b_equal port map 90 | ( 91 | qa_eq_b =>last_byte_reg_in, 92 | clk =>clk, 93 | a =>value_O_tmp, 94 | b =>total_length_from_reg(10 downto 0) 95 | ); 96 | 97 | process(clk) 98 | begin 99 | if clk'event and clk='1' then 100 | last_byte_reg_out<=last_byte_reg_in; 101 | end if; 102 | end process; 103 | eof_O<=not last_byte_reg_out; 104 | count_end<=last_byte_reg_out; 105 | end Behavioral; 106 | 107 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/UDP_IP_Core.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------------------- 2 | -- Copyright (C) 2010 Nikolaos Ch. Alachiotis -- 3 | -- -- 4 | -- Engineer: Nikolaos Ch. Alachiotis -- 5 | -- -- 6 | -- Contact: alachiot@cs.tum.edu -- 7 | -- n.alachiotis@gmail.com -- 8 | -- -- 9 | -- Create Date: 15:29:59 02/07/2010 -- 10 | -- Module Name: UDP_IP_Core -- 11 | -- Target Devices: Virtex 5 FPGAs -- 12 | -- Tool versions: ISE 10.1 -- 13 | -- Description: This component can be used to transmit and receive UDP/IP -- 14 | -- Ethernet Packets (IPv4). -- 15 | -- Additional Comments: The core has been area-optimized and is suitable for direct -- 16 | -- PC-FPGA communication at Gigabit speed. -- 17 | -- -- 18 | ----------------------------------------------------------------------------------------- 19 | 20 | 21 | library IEEE; 22 | use IEEE.STD_LOGIC_1164.ALL; 23 | use IEEE.STD_LOGIC_ARITH.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | 26 | ---- Uncomment the following library declaration if instantiating 27 | ---- any Xilinx primitives in this code. 28 | --library UNISIM; 29 | --use UNISIM.VComponents.all; 30 | 31 | entity UDP_IP_Core is 32 | Port ( rst : in STD_LOGIC; -- active-high 33 | clk_125MHz : in STD_LOGIC; 34 | 35 | -- Transmit signals 36 | transmit_start_enable : in STD_LOGIC; 37 | transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); 38 | usr_data_trans_phase_on : out STD_LOGIC; 39 | transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); 40 | start_of_frame_O : out STD_LOGIC; 41 | end_of_frame_O : out STD_LOGIC; 42 | source_ready : out STD_LOGIC; 43 | transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0); 44 | 45 | --Receive Signals 46 | rx_sof : in STD_LOGIC; 47 | rx_eof : in STD_LOGIC; 48 | input_bus : in STD_LOGIC_VECTOR(7 downto 0); 49 | valid_out_usr_data : out STD_LOGIC; 50 | usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0) 51 | ); 52 | end UDP_IP_Core; 53 | 54 | architecture Behavioral of UDP_IP_Core is 55 | 56 | component IPV4_PACKET_TRANSMITTER is 57 | Port ( rst : in STD_LOGIC; 58 | clk_125MHz : in STD_LOGIC; 59 | transmit_start_enable : in STD_LOGIC; 60 | transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); 61 | usr_data_trans_phase_on : out STD_LOGIC; 62 | transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); 63 | start_of_frame_O : out STD_LOGIC; 64 | end_of_frame_O : out STD_LOGIC; 65 | source_ready : out STD_LOGIC; 66 | transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0) 67 | ); 68 | end component; 69 | 70 | component IPv4_PACKET_RECEIVER is 71 | Port ( rst : in STD_LOGIC; 72 | clk_125Mhz : in STD_LOGIC; 73 | rx_sof : in STD_LOGIC; 74 | rx_eof : in STD_LOGIC; 75 | input_bus : in STD_LOGIC_VECTOR(7 downto 0); 76 | valid_out_usr_data : out STD_LOGIC; 77 | usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)); 78 | end component; 79 | 80 | begin 81 | 82 | IPV4_PACKET_TRANSMITTER_port_map: IPV4_PACKET_TRANSMITTER 83 | Port Map 84 | ( rst => rst, 85 | clk_125MHz => clk_125MHz, 86 | transmit_start_enable => transmit_start_enable, 87 | transmit_data_length => transmit_data_length, 88 | usr_data_trans_phase_on => usr_data_trans_phase_on, 89 | transmit_data_input_bus => transmit_data_input_bus, 90 | start_of_frame_O => start_of_frame_O, 91 | end_of_frame_O => end_of_frame_O, 92 | source_ready => source_ready, 93 | transmit_data_output_bus => transmit_data_output_bus 94 | ); 95 | 96 | 97 | IPv4_PACKET_RECEIVER_port_map: IPv4_PACKET_RECEIVER 98 | Port Map 99 | ( rst => rst, 100 | clk_125Mhz => clk_125Mhz, 101 | rx_sof => rx_sof, 102 | rx_eof => rx_eof, 103 | input_bus => input_bus, 104 | valid_out_usr_data => valid_out_usr_data, 105 | usr_data_output_bus => usr_data_output_bus 106 | ); 107 | 108 | end Behavioral; 109 | 110 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.ngc: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.4e 3 | $`ax5d=#Zl|bdaa:!3-522):'?%8#?/$0936>6>;2;%<<>4108JJUSS2h6:<7>111925?OIX\^1n1??:1<`?6u589l>88"4595BC0331:;<95601;0?GS502H^_RGAFN38G03BN:2LO=6I<;FLG6>O7:2C:>6G=2:K0=>OIA]Y_MYK9;MMB@@B03EELENOC4:NVP62H6;2D:<>5A1018J4443G;8?6@>429M505>5A2218J7253G987C=92:L76>H2:2D=>6@82:L;6>H>n2DISO[\PHL\TWIW[>1EIYY@RJ38K7=HC81[86^NRUc8TLHXJ\YBHUl4PHL\FPUIIDO:7\?4S79PKPTDM=1_U]K9c:W3+bciWz~yynzzrd]okbod&noeScaaphrfhlhbl'kTi|{nl^llp`wrieUi"dQn_ds\j`Ye'noeSb{{ptv\v`a)g|~{yyQ}ef-e`*ir|ySS7'noeS~z}ubvvv`Ykgnch"jka_ommtlvbd`dnh#oPepwbhZhh|l{~maQm.h]b[`wXflUi#dQzsd]`ewt~Wyf~Rbztr,oqqYffm$bSjo{e^`jp*rnm{UlicU>]/k\plcu'eed|RzfldqX4X(nW}cgi"bzt^m?4;g73\:$kh`PsupvgqsumVfdkdm!gdl\jjhwayogeckk.`]fupgkWgei|{nl^`-mZgXmxUeiRl i^wpaZefz{sT|a{|_mwww+jr|Vkeh#gPg`vf[gos'}cn~RijnZ3^*lYsalx$`ba_ukoav]7U'cTxdbj/mww[j:66hk0Y=!heo]ppwsd||xnSaahib,dakYiggzb|hbfndf-eZcv}hfTbbzjqtco[g(nWhUn}R`j_c-j[pubWjky~tQltq\hprt&eSl`k.h]deqcXj`~$xdk}_fgm_4[)aV~bi!conr\pljb{R:V"dQ{img,hprXgV:Tmcj?012265gf3\:$kh`PsupvgqsumVfdkdm!gdl\jjhwayogeckk.`]fupgkWgei|{nl^`-mZgXmxUeiRl i^wpaZefz{sT|a{|_mwww+jr|Vkeh#gPg`vf[gos'}cn~RijnZ3^*lYsalx$`ba_ukoav]7U'cTxdbj/mww[jY7Whdo<=>?124b=>S7'noeS~z}ubvvv`Ykgnch"jka_ommtlvbd`dnh#oPepwbhZhh|l{~maQm.h]b[`wXflUi#dQzsd]`ewt~Wyf~Rbztr,oqqYffm$bSjo{e^`jp*rnm{UlicU>]/k\plcu'eed|RzfldqX4X(nW}cgi"bzt^m\4Zgil9:;?0``8Q5)`mgUxx{lttpf[ii`aj$licQaoorjt`jnfln%mRk~u`n\jjrby|kgSo f_`]fuZhbWk%bSx}j_bcqv|Ywd|yT`xz|.mww[dhc&`UlmykPbhv,plcuWnoeWl1:W3+bciWz~yynzzrd]okbod&noeScaaphrfhlhbl'kTi|{nl^llp`wrieUi"dQn_ds\j`Ye'`U~hQlaspz[ujr{Vf~x~ cuu]bja(nWnkiRlft.vjawY`mgQ:Q#gPthgq+iihxV~b`h}T0\,j[qokm&e{xRmnrs{\pljb&hdoSb|!c`pq}ZkrpzQ;Q#gPmtz`5>S7'noeS~z}ubvvv`Ykgnch"jka_ommtlvbd`dnh#oPepwbhZhh|l{~maQm.h]b[`wXflUi#dQzsd]`ewt~Wyf~Rbztr,oqqYffm$bSjo{e^`jp*rnm{UlicU>]/k\plcu'eed|RzfldqX4X(nW}cgi"at^abvwX|`fn"l`k_np-gdtuqVg~t~U>]/k\ip~2:2_;#jka_rvqqfrrzlUgcjgl.fgm[kiix`zn`d`jd/c\atsfdVddxhzam]a*lYfWl{TbhQm/ugntZtb{|fm6[\ES]BHLGTk2_XI_QYIRKAH@5<^JI27[GJW^VZT@7c3QCGECV"XE@#4+7'[]_I,= > @Q@ML03:2=f48:1<3;4a=33:1=f484?7l2=>59b86833h6?295n<4<7?d:16=1j0:0;;`>;:1=f404=7lQjq^`5?dY`mVh=7lQht^`5?dYkmVh=7lQct^`5?dYimVh?7lmcr59bw`r33k";%95m(0+6?g.68 >0n%<&4:`+7,2"86l'5(68f-0.<2h#;$:4b):*0>d/1 >0n1>17:`?55<76<1i0<>14:`?5;2d;?7>0n1614:`?=;563jUhc`~nrd]u=Z6+(Qcgecv/CNPF$Bcim{kc.>0/3-46Ynx:80oh=4cmif?fijxV;:nRk~u`n13>eheyU:=oQjqtco(fYdgdzj~hQy9^2/JJHB$GEEI#c^jbwZwfWgoTn0>#c^jbwZwfWe~Tn0>#c^jbwZgtm}7; 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NLW_VCC_P_UNCONNECTED 97 | ); 98 | GND_1 : GND 99 | port map ( 100 | G => NLW_GND_G_UNCONNECTED 101 | ); 102 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000136 : 103 | LUT4 104 | generic map( 105 | INIT => X"8000" 106 | ) 107 | port map ( 108 | I0 => 109 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026_31 110 | , 111 | I1 => 112 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053_32 113 | , 114 | I2 => 115 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093_33 116 | , 117 | I3 => 118 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120_34 119 | , 120 | O => 121 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(0) 122 | 123 | ); 124 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120 : 125 | LUT4 126 | generic map( 127 | INIT => X"9009" 128 | ) 129 | port map ( 130 | I0 => a_2(6), 131 | I1 => b_3(6), 132 | I2 => a_2(7), 133 | I3 => b_3(7), 134 | O => 135 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120_34 136 | 137 | ); 138 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093 : 139 | LUT4 140 | generic map( 141 | INIT => X"9009" 142 | ) 143 | port map ( 144 | I0 => a_2(4), 145 | I1 => b_3(4), 146 | I2 => a_2(5), 147 | I3 => b_3(5), 148 | O => 149 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093_33 150 | 151 | ); 152 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053 : 153 | LUT4 154 | generic map( 155 | INIT => X"9009" 156 | ) 157 | port map ( 158 | I0 => a_2(2), 159 | I1 => b_3(2), 160 | I2 => a_2(3), 161 | I3 => b_3(3), 162 | O => 163 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053_32 164 | 165 | ); 166 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026 : 167 | LUT4 168 | generic map( 169 | INIT => X"9009" 170 | ) 171 | port map ( 172 | I0 => a_2(0), 173 | I1 => b_3(0), 174 | I2 => a_2(1), 175 | I3 => b_3(1), 176 | O => 177 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026_31 178 | 179 | ); 180 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and0000 : 181 | LUT3 182 | generic map( 183 | INIT => X"09" 184 | ) 185 | port map ( 186 | I0 => b_3(9), 187 | I1 => a_2(9), 188 | I2 => BU2_N01, 189 | O => 190 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(1) 191 | 192 | ); 193 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and0000_SW0 : 194 | LUT4 195 | generic map( 196 | INIT => X"6FF6" 197 | ) 198 | port map ( 199 | I0 => a_2(10), 200 | I1 => b_3(10), 201 | I2 => a_2(8), 202 | I3 => b_3(8), 203 | O => BU2_N01 204 | ); 205 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_opt_carry_tile_and_or_carry_muxs_0_i_mux : 206 | MUXCY 207 | port map ( 208 | CI => 209 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o(1) 210 | , 211 | DI => BU2_a_ge_b, 212 | S => 213 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(0) 214 | , 215 | O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result 216 | ); 217 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_opt_carry_tile_and_or_carry_muxs_1_i_mux : 218 | MUXCY 219 | port map ( 220 | CI => BU2_N1, 221 | DI => BU2_a_ge_b, 222 | S => 223 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(1) 224 | , 225 | O => 226 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o(1) 227 | 228 | ); 229 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD 230 | generic map( 231 | INIT => '0' 232 | ) 233 | port map ( 234 | C => clk, 235 | D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result, 236 | Q => qa_eq_b 237 | ); 238 | BU2_XST_VCC : VCC 239 | port map ( 240 | P => BU2_N1 241 | ); 242 | BU2_XST_GND : GND 243 | port map ( 244 | G => BU2_a_ge_b 245 | ); 246 | 247 | end STRUCTURE; 248 | 249 | -- synthesis translate_on 250 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version K.39 4 | # Date: Thu Feb 04 10:01:48 2010 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = False 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = VHDL 21 | SET device = xc3s200 22 | SET devicefamily = spartan3 23 | SET flowvendor = Other 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = ft256 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -4 31 | SET verilogsim = False 32 | SET vhdlsim = True 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT Comparator family Xilinx,_Inc. 9.0 36 | # END Select 37 | # BEGIN Parameters 38 | CSET aclr=false 39 | CSET ainitval=0 40 | CSET aset=false 41 | CSET ce=false 42 | CSET cepriority=Sync_Overrides_CE 43 | CSET component_name=comp_11b_equal 44 | CSET constantbport=false 45 | CSET constantbportvalue=0000000000000000 46 | CSET datatype=Unsigned 47 | CSET nonregisteredoutput=false 48 | CSET operation=eq 49 | CSET pipelinestages=0 50 | CSET radix=2 51 | CSET registeredoutput=true 52 | CSET sclr=false 53 | CSET sset=false 54 | CSET syncctrlpriority=Reset_Overrides_Set 55 | CSET width=11 56 | # END Parameters 57 | GENERATE 58 | # CRC: 40267d7f 59 | 60 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.ngc: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.4e 3 | $6fx5d=#Zl|bdaa:!3-522):'?%8#?/$0937>7)8j18?>?fu062(2b3?0BB][[:`>6>58b3?0BB][[:c>6>58531:?74>?929AQ7>E='YBoS]|`jdaww*RomVLn`~kasugjjZEhX{ehi~}`r.ALV@ABFVNndia/uos+Ze`'jef|R8m_dsvei(iof;97NFJCJ]OMFCI[LU_U]K6;BMNILRSMM;?7NA]E^EFJ@TF\@EESD@IO69@V@GSMM;0H?5ID09D7>AIL;1BJHIMOO;6B@GHABH1=K]]9?7A[[4b9Neoiu^lxxeb`l;LkmkwPbzzcdb>5A1118J4743G;9?6@>329M51453G3m7CLPBTQSMKYWZFZX;6@JTVMQO4=H:2E@=6^;;QCQPd=WAGUIY^GKXc9SMKYE]ZDJAH?4Q79PKPTDM=1_U]K9c:W3+bciWz~yynzzrd]okbod&noeScaaphrfhlhbl'kTi|{nl^llp`wrieUi"dQn_ds\j`Ye'noeSb{{ptv\v`a)g|~{yyQ}ef-e`*ir|yS<7m;T2,c`hX{}x~oy{}e^nlcle)oldTbb`iqgomkcc&hUn}xoc_omwatsfdVh%eRoPep]maZd(aVxiRmnrs{\tistWe#bzt^cm`+oXoh~nSog{/ukfvZabfR;V"dQ{idp,hjiwW}cgi~U?]/k\pljb'f8=5o5Z0.efjZusz|iykPlnejg+abfVddb}gemkmaa(fWl{~maQaougrqdjXj'cTmRk~_og\f*oX}zoTol|}y^roqvYk}}y%`xzPaof-mZaf|lUiey!{idp\c`h\9T$bSygjr.nlkuYsaeoxW=S!i^vjh`)h=:3i7X> gdl\wqtrk}yiRb`gha-c`hXffd{e}kciogg*dYby|kgSca{epwbhZd)aVkTi|Qae^`,mZstmVij~wPpmwp[iss{'f~xRoad/k\cdrbWkc#ygjr^efj^7Z&`Ueh| lnms[qokmzQ;Q#gPthnf+j>71k1^<"ijn^qwvpes}{oT`bifc/efjZhhfyc{iagaee,b[`wrieUecyk~u`n\f+oXiVozSckPb.k\qvcXkhxyuR~cur]oqqu)d|~Tmcj!i^ebp`Yea}%eh|PgdlX5X(nW}cn~"b`oq]wmictS9W%eRzfld-l=0353\:$kh`PsupvgqsumVfdkdm!gdl\jjhwayogeckk.`]fupgkWgei|{nl^`-mZgXmxUeiRl tdos[wct}e~j7X]JR^COMDUd3\YN^RXFSH@OA6=QKJ30ZDKX_U[SA4b0:ZgiZKnffx]i}foo68e-6.<2k#=$:4a)0*0>g/; >0m%:&4:c+1,2g;=3:586o35?48eZcvWk<0mRij_c48eZasWk<0mRbj_c48eZjsWk<0mR`j_c68efju<2kxiy:4b)2*0>d/9 >0n%<&4:`+7,2"86l'5(68f969<2h7=3:4b=0=0>d;;7>0n1:16:`?1?69<2h793=>;b]`khvfzlU}5R># Ykomk~'KFXN,Jkaescwkw&68';%<>Qfp208g`5#c^fbpdYsqyo6=!mPsxl`[utng{cu0?#c^jbwZudd{7; nQgar]reZasWk7; nQxievk93*dWakxS|oPep]a94*dWakxSlQce^`>4)eXi`dbxRxnl<2/gjkwggoexR`nmd?`khvX>kUn}xoc,b]smucX{}kli~3?,b]kevYdm4:'oRfns^c`hw;7$jUxucmPeocah`;7$jUcm~Q|sdv>4)eX`hyT}lQce^`>4)eX`hyTmRij_c?3(fYeWjeeyoat<2/gZnf{VkT`yQm=1.`[mgtWhUeiRl20-a\fZpfd|o6<=>?0123456789:; p<=;bmntZ0eWl{~maQl_bmntdtbW3T1zmRi{_c58udYkmVh<7|oPlu]a3>wfWgoTn95|cmp7?vub|tJK|5j4@Aza>C<328qXj79<:38277d3>j0:4:6>{o6;>4=i<00?7):9:508yVb=?:096<==b54`>4>0081X=4484;29564e22=83;8>o:9c;3;3=725=:3;8>o:9c;3;3=7<~]9=6=4>:0827~Ua2>91>7?<2c65g?7??1;0(9?51`9U02<5s|;o6<5z1d83?x"4:390n;h50;g97?c|@:l0V44={586>x"4?35=7c=<:298m1d=83.887;:;o10>1=7=50;&00?0f3g986954i4d94?"4<35<6290;wE=i;%14>454c=>3;8wE=i;[;90~2==3>197s+36846>"d2>:0(h481:&1`?573`=i6=44o4594?=n=m0;66a86;29?l0c2900c8l50;9l1<<722e>m7>5;h6e>5<#;=0>96`<3;28?l2b290/?94:5:l07?7<3`>o6=4+35861>h4;3807d:l:18'71<2=2d8?7=4;h6a>5<#;=0>96`<3;68?l2f290/?94:5:l07?3<3`h4;3:07d8<:18'71<1i2d8?7?4;h41>5<#;=0=m6`<3;08?l06290/?949a:l07?5<3`<;6=4+3585e>h4;3>07d;i:18'71<1i2d8?7;4;n7;>5<k1<75`7483>>o1m3:17b96:188m2e=831b9h4?::m43?6=3f?h6=44o6:94?=e<=0;6<4?:1y'72<6;2B??6F53;294~"4?3;:7E:<;I1e?!7?281bm7>5;h33>5<951b9K06=O;o1/=548;h37>5<>o6?3:17b6=4?{%14>4e<@=90D>h4$0:93>o6<3:17d?::188m40=831b=:4?::m1b?6=3th8n7>55;294~"4?3;h7E:<;I1e?!7?2>1b=94?::k21?6=3`;=6=44i0594?=h:o0;66sm3b83>1<729q/?:4>b:J77>N4n2.:4784i0694?=n9<0;66g>6;29?j4a2900q~;7:18`[1f3W?i7S;n;_74?[3d3W=<7S99;_5:?[1?3W?27S;7;<67>4475159~w02=838pR9k4=2;953=z{<91<7l5159~w06=838pR9o4=2`953=z{?h1<7o5149~w31=838pR;?4=2c952=z{?<1<7{t;00;6?u23881b>;4k3;?7p}{t==0;6?uQ4d9>5<5sW>o70654e9'7`<5?2wx9?4?:3y]0f=:03>h7)=j:3:8yv362909wS:m;<:90g=#;l0956s|5183>7}Y7g=>=1/?h4=b:p2<<72;qU:>528;40?!5b2;i0q~87:181[053421:?5+3d82b>{t>>0;6?uQ609>4}r45>5<5sW<;7065619'7`<592wx:84?:3y]1c=:03?m7)=j:308yv0b2909wS8j;<:92`=#;l09?6s|7483>7}Y?<16479:;%1f>7352zJ0b>{i>m0;6?uG3g9~j3c=838pD>h4}o4e>5<5sA9m7p`80;296~N4n2we;<4?:3yK7c=zf>81<77}O;o1vb:850;0xL6`vF51zJ0b>{i>h0;6h4}|~DEE|0m08 NLW_VCC_P_UNCONNECTED 81 | ); 82 | GND_1 : GND 83 | port map ( 84 | G => NLW_GND_G_UNCONNECTED 85 | ); 86 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o95 : 87 | LUT3 88 | generic map( 89 | INIT => X"80" 90 | ) 91 | port map ( 92 | I0 => 93 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_16 94 | , 95 | I1 => 96 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53_17 97 | , 98 | I2 => 99 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80_18 100 | , 101 | O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result 102 | ); 103 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80 : 104 | LUT4 105 | generic map( 106 | INIT => X"9009" 107 | ) 108 | port map ( 109 | I0 => a_2(1), 110 | I1 => b_3(1), 111 | I2 => a_2(0), 112 | I3 => b_3(0), 113 | O => 114 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80_18 115 | 116 | ); 117 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53 : 118 | LUT4 119 | generic map( 120 | INIT => X"9009" 121 | ) 122 | port map ( 123 | I0 => a_2(3), 124 | I1 => b_3(3), 125 | I2 => a_2(2), 126 | I3 => b_3(2), 127 | O => 128 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53_17 129 | 130 | ); 131 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26 : 132 | LUT4 133 | generic map( 134 | INIT => X"9009" 135 | ) 136 | port map ( 137 | I0 => a_2(5), 138 | I1 => b_3(5), 139 | I2 => a_2(4), 140 | I3 => b_3(4), 141 | O => 142 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_16 143 | 144 | ); 145 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD 146 | generic map( 147 | INIT => '0' 148 | ) 149 | port map ( 150 | C => clk, 151 | D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result, 152 | Q => qa_eq_b 153 | ); 154 | BU2_XST_GND : GND 155 | port map ( 156 | G => BU2_a_ge_b 157 | ); 158 | 159 | end STRUCTURE; 160 | 161 | -- synthesis translate_on 162 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version K.39 4 | # Date: Thu Feb 04 10:02:26 2010 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = False 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = VHDL 21 | SET device = xc3s200 22 | SET devicefamily = spartan3 23 | SET flowvendor = Other 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = ft256 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -4 31 | SET verilogsim = False 32 | SET vhdlsim = True 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT Comparator family Xilinx,_Inc. 9.0 36 | # END Select 37 | # BEGIN Parameters 38 | CSET aclr=false 39 | CSET ainitval=0 40 | CSET aset=false 41 | CSET ce=false 42 | CSET cepriority=Sync_Overrides_CE 43 | CSET component_name=comp_6b_equal 44 | CSET constantbport=false 45 | CSET constantbportvalue=0000000000000000 46 | CSET datatype=Unsigned 47 | CSET nonregisteredoutput=false 48 | CSET operation=eq 49 | CSET pipelinestages=0 50 | CSET radix=2 51 | CSET registeredoutput=true 52 | CSET sclr=false 53 | CSET sset=false 54 | CSET syncctrlpriority=Reset_Overrides_Set 55 | CSET width=6 56 | # END Parameters 57 | GENERATE 58 | # CRC: dc354663 59 | 60 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.ngc: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.4e 3 | $`2x5d=#Zl|bdaa:!3-522):'?%8#?/$292*5e<;z8;0=AGZ^X7o35;2=54=12@D[YY4kpsc?1?69981=6D@_UU8ptwg;=3:5i665IORVP?b;?3:5=<57:NWWTPR=lye7;7>1139;>JSSX\^1}i~`<683:44<03E^X][[:pqsk91=87;:754@UURVP?uwg5=1<3=4BT0;?GSTW@DMC8:4C;-SLaYWzf`noy} Tig\B`jtmgyid`PCnRqkfct{fx$OB\JGDL\@`unog%a}!Pcf-gmvrXelgT:9v7.oel57=D@LI@SAGLEOQF[Q_WM01HC@CFTUGG51=DG[OTKH@JR@VJKKYNFOE<7N\JAUGG5>A43NDO:6B@AEGG3>JHO@IJ@n5BakmqR`ttafdh7@gaosTfvvohf;1EH5989>7C<>3578J7718<1E><8>5:L153423G8::>;4N33500=I:8<>96@=1746?K46>>l0BOQMURRJJZVUGYY<7CK[WNPH6>IL92Z?7]O]T`9SMKYE]ZCOTo5_IO]AQVHFEL<0_B[]CD68P\VBi2_XI_QNLHCPg>STM[U]E^GMLD18RFE>3_CN[RZVPD3g?]OKAGR&TIL/0/3#WQSE(9$:,L]LIH48\VRKAK=0T^ZPGOFa?]YDG[OTECH@6:ZgfZOcn2RodR^}ilTfvvohf8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`;;`*3-1=f 8#?7l&=)59b,6/33h"?%95n(4+7?d:76=1j0<0;;`>1:1=f4:4?7l2;>79b80<76=1j080<;bnh0>b/8 >0h%?&4:f+6,2b;?3:5h6jfsu]nahY14)eX`hyT{h3?,b]smuckagoTyoher?3(fYoizUzh}aPrrv>4)eXzlmTh}|n_hlsqq;7$jUzylbffx]ta86+kVyrbnQjn``oa87+kVnn|yf265.`[mgtWmzym0>#c^jbwZwtxfUx~~z20-a\lduXymzdS~||t<2/gZwdmV`deckk=1.`[hcjW}s{i0>#c^jbwZoXkl7; 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All rights reserved. 3 | -------------------------------------------------------------------------------- 4 | -- ____ ____ 5 | -- / /\/ / 6 | -- /___/ \ / Vendor: Xilinx 7 | -- \ \ \/ Version: K.39 8 | -- \ \ Application: netgen 9 | -- / / Filename: dist_mem_64x8.vhd 10 | -- /___/ /\ Timestamp: Thu Feb 04 11:02:06 2010 11 | -- \ \ / \ 12 | -- \___\/\___\ 13 | -- 14 | -- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.vhd 15 | -- Device : 3s200ft256-4 16 | -- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.ngc 17 | -- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.vhd 18 | -- # of Entities : 1 19 | -- Design Name : dist_mem_64x8 20 | -- Xilinx : C:\Xilinx\10.1\ISE 21 | -- 22 | -- Purpose: 23 | -- This VHDL netlist is a verification model and uses simulation 24 | -- primitives which may not represent the true implementation of the 25 | -- device, however the netlist is functionally correct and should not 26 | -- be modified. This file cannot be synthesized and should only be used 27 | -- with supported simulation tools. 28 | -- 29 | -- Reference: 30 | -- Development System Reference Guide, Chapter 23 31 | -- Synthesis and Simulation Design Guide, Chapter 6 32 | -- 33 | -------------------------------------------------------------------------------- 34 | 35 | 36 | -- synthesis translate_off 37 | library IEEE; 38 | use IEEE.STD_LOGIC_1164.ALL; 39 | library UNISIM; 40 | use UNISIM.VCOMPONENTS.ALL; 41 | use UNISIM.VPKG.ALL; 42 | 43 | entity dist_mem_64x8 is 44 | port ( 45 | clk : in STD_LOGIC := 'X'; 46 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 47 | qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) 48 | ); 49 | end dist_mem_64x8; 50 | 51 | architecture STRUCTURE of dist_mem_64x8 is 52 | signal N0 : STD_LOGIC; 53 | signal N1 : STD_LOGIC; 54 | signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 ); 55 | signal NlwRenamedSignal_qspo : STD_LOGIC_VECTOR ( 0 downto 0 ); 56 | begin 57 | a_2(5) <= a(5); 58 | a_2(4) <= a(4); 59 | a_2(3) <= a(3); 60 | a_2(2) <= a(2); 61 | a_2(1) <= a(1); 62 | a_2(0) <= a(0); 63 | qspo(7) <= NlwRenamedSignal_qspo(0); 64 | qspo(6) <= NlwRenamedSignal_qspo(0); 65 | qspo(5) <= NlwRenamedSignal_qspo(0); 66 | qspo(4) <= NlwRenamedSignal_qspo(0); 67 | qspo(3) <= NlwRenamedSignal_qspo(0); 68 | qspo(2) <= NlwRenamedSignal_qspo(0); 69 | qspo(1) <= NlwRenamedSignal_qspo(0); 70 | qspo(0) <= NlwRenamedSignal_qspo(0); 71 | VCC_0 : VCC 72 | port map ( 73 | P => N1 74 | ); 75 | GND_1 : GND 76 | port map ( 77 | G => N0 78 | ); 79 | BU2_XST_GND : GND 80 | port map ( 81 | G => NlwRenamedSignal_qspo(0) 82 | ); 83 | 84 | end STRUCTURE; 85 | 86 | -- synthesis translate_on 87 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version K.39 4 | # Date: Thu Feb 04 10:02:06 2010 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = False 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = VHDL 21 | SET device = xc3s200 22 | SET devicefamily = spartan3 23 | SET flowvendor = Other 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = ft256 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -4 31 | SET verilogsim = False 32 | SET vhdlsim = True 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4 36 | # END Select 37 | # BEGIN Parameters 38 | CSET ce_overrides=ce_overrides_sync_controls 39 | CSET coefficient_file="C:/PHd_Projects/The_Felsenstein_CoProcessor/ISE_Design/THE_FELSENSTEIN_COPROCESSOR/Copy of definition1_l1_cache.coe" 40 | CSET common_output_ce=false 41 | CSET common_output_clk=false 42 | CSET component_name=dist_mem_64x8 43 | CSET data_width=8 44 | CSET default_data=0 45 | CSET default_data_radix=16 46 | CSET depth=64 47 | CSET dual_port_address=non_registered 48 | CSET dual_port_output_clock_enable=false 49 | CSET input_clock_enable=false 50 | CSET input_options=non_registered 51 | CSET memory_type=rom 52 | CSET output_options=registered 53 | CSET pipeline_stages=0 54 | CSET qualify_we_with_i_ce=false 55 | CSET reset_qdpo=false 56 | CSET reset_qspo=false 57 | CSET single_port_output_clock_enable=false 58 | CSET sync_reset_qdpo=false 59 | CSET sync_reset_qspo=false 60 | # END Parameters 61 | GENERATE 62 | # CRC: 86e0277a 63 | 64 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:46:33 12/04/2009 6 | -- Design Name: 7 | -- Module Name: ALLOW_ZERO_UDP_CHECKSUM - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity ALLOW_ZERO_UDP_CHECKSUM is 31 | Port ( clk : in STD_LOGIC; 32 | input : in STD_LOGIC; 33 | output_to_readen : out STD_LOGIC; 34 | output_to_datasel : out STD_LOGIC); 35 | end ALLOW_ZERO_UDP_CHECKSUM; 36 | 37 | architecture Behavioral of ALLOW_ZERO_UDP_CHECKSUM is 38 | 39 | signal input_reg : std_logic; 40 | 41 | begin 42 | 43 | process(clk) 44 | begin 45 | if clk'event and clk='1' then 46 | input_reg<=input; 47 | end if; 48 | end process; 49 | 50 | output_to_readen<=input_reg; 51 | 52 | process(clk) 53 | begin 54 | if clk'event and clk='1' then 55 | output_to_datasel<=input_reg; 56 | end if; 57 | end process; 58 | 59 | end Behavioral; 60 | 61 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_RECEIV.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:16:57 11/30/2009 6 | -- Design Name: 7 | -- Module Name: COUNTER_11B_EN_RECEIV - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity COUNTER_11B_EN_RECEIV is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | count_en : in STD_LOGIC; 34 | value_O : inout STD_LOGIC_VECTOR (10 downto 0)); 35 | end COUNTER_11B_EN_RECEIV; 36 | 37 | architecture Behavioral of COUNTER_11B_EN_RECEIV is 38 | 39 | begin 40 | 41 | process(clk) 42 | begin 43 | if rst='1' then 44 | value_O<="00000000000"; 45 | else 46 | if clk'event and clk='1' then 47 | if count_en='1' then 48 | value_O<=value_O+"00000000001"; 49 | else 50 | value_O<=value_O; 51 | end if; 52 | end if; 53 | end if; 54 | end process; 55 | 56 | 57 | end Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_TRANS.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:16:57 11/30/2009 6 | -- Design Name: 7 | -- Module Name: COUNTER_11B_EN_TRANS - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity COUNTER_11B_EN_TRANS is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | count_en : in STD_LOGIC; 34 | value_O : inout STD_LOGIC_VECTOR (10 downto 0)); 35 | end COUNTER_11B_EN_TRANS; 36 | 37 | architecture Behavioral of COUNTER_11B_EN_TRANS is 38 | 39 | begin 40 | 41 | process(clk) 42 | begin 43 | if rst='1' then 44 | value_O<="11111110110"; 45 | else 46 | if clk'event and clk='1' then 47 | if count_en='1' then 48 | value_O<=value_O+"00000000001"; 49 | else 50 | value_O<=value_O; 51 | end if; 52 | end if; 53 | end if; 54 | end process; 55 | 56 | 57 | end Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 02:30:12 11/30/2009 6 | -- Design Name: 7 | -- Module Name: COUNTER_6B_LUT_FIFO_MODE - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity COUNTER_6B_LUT_FIFO_MODE is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing 34 | count_en : in STD_LOGIC; 35 | value_O : inout STD_LOGIC_VECTOR (5 downto 0)); 36 | end COUNTER_6B_LUT_FIFO_MODE; 37 | 38 | architecture Behavioral of COUNTER_6B_LUT_FIFO_MODE is 39 | 40 | begin 41 | 42 | process(clk) 43 | begin 44 | if rst='1' then 45 | if funct_sel='0' then 46 | value_O<=(others=>'0'); 47 | else 48 | value_O<="100111"; 49 | end if; 50 | else 51 | if clk'event and clk='1' then 52 | if count_en='1' then 53 | value_O<=value_O+"000001"; 54 | else 55 | value_O<=value_O; 56 | end if; 57 | end if; 58 | end if; 59 | end process; 60 | 61 | 62 | end Behavioral; 63 | 64 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12:05:48 12/04/2009 6 | -- Design Name: 7 | -- Module Name: ENABLE_USER_DATA_TRANSMISSION - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity ENABLE_USER_DATA_TRANSMISSION is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | start_usr_data_trans : in STD_LOGIC; 34 | stop_usr_data_trans : in STD_LOGIC; 35 | usr_data_sel : out STD_LOGIC); 36 | end ENABLE_USER_DATA_TRANSMISSION; 37 | 38 | architecture Behavioral of ENABLE_USER_DATA_TRANSMISSION is 39 | 40 | signal usr_data_sel_prev : std_logic :='0'; 41 | 42 | begin 43 | 44 | process(clk) 45 | begin 46 | if rst='1' then 47 | usr_data_sel<='0'; 48 | usr_data_sel_prev<='0'; 49 | else 50 | if clk'event and clk='1' then 51 | if (start_usr_data_trans='1' and usr_data_sel_prev='0') then 52 | usr_data_sel<='1'; 53 | usr_data_sel_prev<='1'; 54 | end if; 55 | if (stop_usr_data_trans='0' and usr_data_sel_prev='1') then -- stop_usr_data_trans is active low 56 | usr_data_sel<='0'; 57 | usr_data_sel_prev<='0'; 58 | end if; 59 | end if; 60 | end if; 61 | end process; 62 | 63 | end Behavioral; 64 | 65 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_LUT_INDEXER.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 22:11:55 11/27/2009 6 | -- Design Name: 7 | -- Module Name: IPV4_LUT_INDEXER - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity IPV4_LUT_INDEXER is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | transmit_enable : in STD_LOGIC; 34 | LUT_index : out STD_LOGIC_VECTOR (5 downto 0)); 35 | end IPV4_LUT_INDEXER; 36 | 37 | architecture Behavioral of IPV4_LUT_INDEXER is 38 | 39 | component dist_mem_64x8 is 40 | port ( 41 | clk : in STD_LOGIC := 'X'; 42 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 43 | qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) 44 | ); 45 | end component; 46 | 47 | component COUNTER_6B_LUT_FIFO_MODE is 48 | Port ( rst : in STD_LOGIC; 49 | clk : in STD_LOGIC; 50 | funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing -- only LUT support is used 51 | count_en : in STD_LOGIC; 52 | value_O : inout STD_LOGIC_VECTOR (5 downto 0)); 53 | end component; 54 | 55 | component comp_6b_equal is 56 | port ( 57 | qa_eq_b : out STD_LOGIC; 58 | clk : in STD_LOGIC := 'X'; 59 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 60 | b : in STD_LOGIC_VECTOR ( 5 downto 0 ) 61 | ); 62 | end component; 63 | 64 | signal count_en_sig , count_end , rst_counter: std_logic :='0'; 65 | signal count_val: std_logic_Vector(5 downto 0):=(others=>'0'); 66 | signal count_en_sig_comb : std_logic; 67 | constant lut_upper_address :std_logic_vector(5 downto 0):="100110"; -- position 38 68 | 69 | begin 70 | 71 | process(clk) 72 | begin 73 | if (rst='1' or count_end='1') then 74 | count_en_sig<='0'; 75 | rst_counter<='1'; 76 | else 77 | rst_counter<='0'; 78 | if clk'event and clk='1' then 79 | if (transmit_enable='1' and count_en_sig='0') then 80 | count_en_sig<='1'; 81 | end if; 82 | end if; 83 | end if; 84 | end process; 85 | 86 | LUT_END_CHECK : comp_6b_equal port map ( 87 | qa_eq_b =>count_end, 88 | clk =>clk, 89 | a =>count_val, 90 | b =>lut_upper_address 91 | 92 | ); 93 | 94 | count_en_sig_comb <=count_en_sig or transmit_enable; 95 | 96 | 97 | 98 | LUT_INDEXER_MODULE : COUNTER_6B_LUT_FIFO_MODE port map ( 99 | rst => rst_counter, 100 | clk => clk, 101 | funct_sel =>'0', -- for now only one function is supported 102 | count_en =>count_en_sig_comb, 103 | value_O =>count_val 104 | ); 105 | 106 | LUT_index<=count_val; 107 | 108 | 109 | end Behavioral; 110 | 111 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_PACKET_TRANSMITTER.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------------------- 2 | -- Copyright (C) 2010 Nikolaos Ch. Alachiotis -- 3 | -- -- 4 | -- Engineer: Nikolaos Ch. Alachiotis -- 5 | -- -- 6 | -- Contact: alachiot@cs.tum.edu -- 7 | -- n.alachiotis@gmail.com -- 8 | -- -- 9 | -- Create Date: 14:45:39 11/27/2009 -- 10 | -- Module Name: IPV4_PACKET_TRANSMITTER -- 11 | -- Target Devices: Virtex 5 FPGAs -- 12 | -- Tool versions: ISE 10.1 -- 13 | -- Description: This component can be used to send IPv4 Ethernet Packets. -- 14 | -- Additional Comments: The look-up table contains the header fields of the IP packet, -- 15 | -- so please keep in mind that you have to reinitialize this LUT. -- 16 | -- -- 17 | ----------------------------------------------------------------------------------------- 18 | library IEEE; 19 | use IEEE.STD_LOGIC_1164.ALL; 20 | use IEEE.STD_LOGIC_ARITH.ALL; 21 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 22 | 23 | ---- Uncomment the following library declaration if instantiating 24 | ---- any Xilinx primitives in this code. 25 | --library UNISIM; 26 | --use UNISIM.VComponents.all; 27 | 28 | entity IPV4_PACKET_TRANSMITTER is 29 | Port ( rst : in STD_LOGIC; 30 | clk_125MHz : in STD_LOGIC; 31 | transmit_start_enable : in STD_LOGIC; 32 | transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); 33 | usr_data_trans_phase_on : out STD_LOGIC; 34 | transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); 35 | start_of_frame_O : out STD_LOGIC; 36 | end_of_frame_O : out STD_LOGIC; 37 | source_ready : out STD_LOGIC; 38 | transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0) 39 | ); 40 | end IPV4_PACKET_TRANSMITTER; 41 | 42 | architecture Behavioral of IPV4_PACKET_TRANSMITTER is 43 | 44 | 45 | ----------------------------------------------------------------------------------------------------------------------------------------- 46 | ----------------------------------------------------------------------------------------------------------------------------------------- 47 | -- IPv4 PACKET STRUCTURE : -- 48 | -- Size | Description | Transmission Order | Position -- 49 | -- ----------------------------------------------------------------------------------------------------------- 50 | -- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT -- 51 | -- | X-X-X-X-X-X | | -- 52 | -- | | | -- 53 | -- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT -- 54 | -- | 11111111-11111111-11111111-11111111-... | | -- 55 | -- 2 bytes | Ethernet Type * | 12 13 | LUT -- 56 | -- | (fixed to 00001000-00000000 :=> | | -- 57 | -- | Internet Protocol, Version 4 (IPv4)) | | -- 58 | -- -- Start of IPv4 Packet ** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | -- 59 | -- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length | 14 | LUT -- 60 | -- | 0100 0101 | | -- 61 | -- 1 byte | Differentiated Services | 15 | LUT -- 62 | -- | 00000000 | | -- 63 | -- 2 bytes | Total Length | 16 17 | REG -- 64 | -- | 00000000-00100100 (base: 20 + 8 + datalength)| | -- 65 | -- 2 bytes | Identification | 18 19 | LUT -- 66 | -- | 00000000-00000000 | | -- 67 | -- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset | 20 21 | LUT -- 68 | -- | 010 - 0000000000000 | | -- 69 | -- 1 byte | Time to Live | 22 | LUT -- 70 | -- | 01000000 | | -- 71 | -- 1 byte | Protocol | 23 | LUT -- 72 | -- | 00010001 | | -- 73 | -- 2 bytes | Header Checksum | 24 25 | REG -- 74 | -- | 10110111 01111101 (base value) | | -- 75 | -- 4 bytes | Source IP Address | 26 27 28 29 | LUT -- 76 | -- | X-X-X-X - FPGA | | -- 77 | -- 4 bytes | Destin IP Address | 30 31 32 33 | LUT -- 78 | -- | X-X-X-X - PC | | -- 79 | -- -- Start of UDP Packet *** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | -- 80 | -- 2 bytes | Source Port | 34 35 | LUT -- 81 | -- | X-X | | -- 82 | -- 2 bytes | Destination Port | 36 37 | LUT -- 83 | -- | X-X | | -- 84 | -- 2 bytes | Length | 38 39 | REG -- 85 | -- | 00000000 - 00010000 (8 + # data bytes) | | -- 86 | -- 2 bytes | Checksum | 40 41 | LUT -- 87 | -- | 00000000 - 00000000 | | -- 88 | -- X bytes | Data | 42 .. X | from input -- 89 | -- | | | -- 90 | ----------------------------------------------------------------------------------------------------------------------------------------- 91 | ----------------------------------------------------------------------------------------------------------------------------------------- 92 | 93 | -- * More details about the Ethernet Type value you can find here: 94 | -- http://en.wikipedia.org/wiki/Ethertype 95 | 96 | -- ** More details about the Internet Protocol, Version 4 (IPv4) you can find here: 97 | -- http://en.wikipedia.org/wiki/IPv4 98 | 99 | -- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here: 100 | -- http://en.wikipedia.org/wiki/User_Datagram_Protocol 101 | 102 | ----------------------------------------------------------------------------------------------------------------------------------------- 103 | ----------------------------------------------------------------------------------------------------------------------------------------- 104 | 105 | 106 | 107 | -------------------------------------------------------------------------------------- 108 | -- COMPONENT DECLARATION 109 | -------------------------------------------------------------------------------------- 110 | 111 | component REG_16B_WREN is 112 | Port ( rst : in STD_LOGIC; 113 | clk : in STD_LOGIC; 114 | wren : in STD_LOGIC; 115 | input : in STD_LOGIC_VECTOR (15 downto 0); 116 | output : out STD_LOGIC_VECTOR (15 downto 0)); 117 | end component; 118 | 119 | component IPV4_LUT_INDEXER is 120 | Port ( rst : in STD_LOGIC; 121 | clk : in STD_LOGIC; 122 | transmit_enable : in STD_LOGIC; 123 | LUT_index : out STD_LOGIC_VECTOR (5 downto 0)); 124 | end component; 125 | 126 | component dist_mem_64x8 is 127 | port ( 128 | clk : in STD_LOGIC := 'X'; 129 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 130 | qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) 131 | ); 132 | end component; 133 | 134 | component OVERRIDE_LUT_CONTROL is 135 | Port ( clk : in STD_LOGIC; 136 | input_addr : in STD_LOGIC_VECTOR (5 downto 0); 137 | sel_total_length_MSBs : out STD_LOGIC; 138 | sel_total_length_LSBs : out STD_LOGIC; 139 | sel_header_checksum_MSBs : out STD_LOGIC; 140 | sel_header_checksum_LSBs : out STD_LOGIC; 141 | sel_length_MSBs : out STD_LOGIC; 142 | sel_length_LSBs : out STD_LOGIC 143 | ); 144 | end component; 145 | 146 | component TARGET_EOF is 147 | Port ( rst : in STD_LOGIC; 148 | clk : in STD_LOGIC; 149 | start : in STD_LOGIC; 150 | total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0); 151 | eof_O : out STD_LOGIC); 152 | end component; 153 | 154 | component ENABLE_USER_DATA_TRANSMISSION is 155 | Port ( rst : in STD_LOGIC; 156 | clk : in STD_LOGIC; 157 | start_usr_data_trans : in STD_LOGIC; 158 | stop_usr_data_trans : in STD_LOGIC; 159 | usr_data_sel : out STD_LOGIC); 160 | end component; 161 | 162 | component ALLOW_ZERO_UDP_CHECKSUM is 163 | Port ( clk : in STD_LOGIC; 164 | input : in STD_LOGIC; 165 | output_to_readen : out STD_LOGIC; 166 | output_to_datasel : out STD_LOGIC); 167 | end component; 168 | 169 | 170 | -------------------------------------------------------------------------------------- 171 | -- SIGNAL DECLARATION 172 | -------------------------------------------------------------------------------------- 173 | 174 | signal transmit_start_enable_tmp, 175 | sel_total_length_MSBs, 176 | sel_total_length_LSBs, 177 | sel_header_checksum_MSBs, 178 | sel_header_checksum_LSBs, 179 | sel_length_MSBs, 180 | sel_length_LSBs, 181 | lut_out_sel, 182 | source_ready_previous_value, 183 | end_of_frame_O_tmp, 184 | transmit_start_enable_reg, 185 | usr_data_sel_sig, 186 | start_usr_data_read, 187 | start_usr_data_trans : STD_LOGIC; 188 | 189 | signal LUT_addr : STD_LOGIC_VECTOR(5 downto 0); 190 | 191 | signal transmit_data_input_bus_tmp, 192 | transmit_data_output_bus_tmp, 193 | sel_total_length_MSBs_vec, 194 | sel_total_length_LSBs_vec, 195 | sel_header_checksum_MSBs_vec, 196 | sel_header_checksum_LSBs_vec, 197 | sel_length_MSBs_vec, 198 | sel_length_LSBs_vec, 199 | lut_out_sel_vec, 200 | transmit_data_output_bus_no_usr_data, 201 | usr_data_not_sel_vec, 202 | usr_data_sel_vec : STD_LOGIC_VECTOR(7 downto 0); 203 | 204 | signal transmit_data_length_tmp, 205 | data_length_regout, 206 | tmp_total_length, 207 | tmp_header_checksum, 208 | tmp_header_checksum_baseval, 209 | tmp_length : STD_LOGIC_VECTOR(15 downto 0); 210 | 211 | 212 | begin 213 | 214 | transmit_start_enable_tmp<=transmit_start_enable; 215 | 216 | transmit_data_length_tmp<=transmit_data_length; 217 | 218 | transmit_data_input_bus_tmp<=transmit_data_input_bus; 219 | 220 | ---------------------------------------------------------------------------------------------------- 221 | -- start_of_frame_O signal 222 | ---------------------------------------------------------------------------------------------------- 223 | -- Description: start_of_frame_O is active low 224 | -- We connect it to the delayed for one clock cycle transmit_start_enable input signal 225 | -- through a NOT gate since transmit_start_enable is active high. 226 | 227 | process(clk_125MHz) 228 | begin 229 | if clk_125MHz'event and clk_125MHz='1' then 230 | transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle. 231 | end if; 232 | end process; 233 | 234 | start_of_frame_O<=not transmit_start_enable_reg; 235 | 236 | ---------------------------------------------------------------------------------------------------- 237 | -- end_of_frame_O signal 238 | ---------------------------------------------------------------------------------------------------- 239 | -- Description: end_of_frame_O is active low 240 | -- The TARGET_EOF module targets the last byte of the packet that is being transmitted 241 | -- based on a counter that counts the number of transmitted bytes and a comparator that 242 | -- detects the last byte which is the th byte. 243 | 244 | TARGET_EOF_port_map: TARGET_EOF port map 245 | ( 246 | rst =>rst, 247 | clk =>clk_125MHz, 248 | start =>transmit_start_enable_reg, 249 | total_length_from_reg =>tmp_total_length, 250 | eof_O =>end_of_frame_O_tmp 251 | ); 252 | 253 | --* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the 254 | -- IPv4 packet. (MAC addresses + Ethernet Type) 255 | 256 | end_of_frame_O<=end_of_frame_O_tmp; 257 | 258 | ---------------------------------------------------------------------------------------------------- 259 | -- source_ready signal 260 | ---------------------------------------------------------------------------------------------------- 261 | -- Description: source_ready is active low 262 | -- This signal is idle(high). (based on rst and end_of_frame_O_tmp). 263 | -- This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp). 264 | 265 | process(clk_125MHz) 266 | begin 267 | if rst='1' then 268 | source_ready<='1'; 269 | source_ready_previous_value<='1'; 270 | else 271 | if clk_125MHz'event and clk_125MHz='1' then 272 | if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then 273 | source_ready<='0'; 274 | source_ready_previous_value<='0'; 275 | else 276 | if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then 277 | source_ready<='1'; 278 | source_ready_previous_value<='1'; 279 | end if; 280 | end if; 281 | end if; 282 | end if; 283 | end process; 284 | 285 | ---------------------------------------------------------------------------------------------------- 286 | -- transmit_data_output_bus 287 | ---------------------------------------------------------------------------------------------------- 288 | ---------------------------------------------------------------------------------------------------- 289 | -- Component Name: REG_16B_WREN 290 | -- Instance Name: NUMBER_OR_DATA_IN_BYTES_REGISTER 291 | -- Description: Register that holds the number of bytes of input data 292 | -- that will be transmitted in the packet. 293 | ---------------------------------------------------------------------------------------------------- 294 | NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map 295 | ( 296 | rst =>rst, 297 | clk =>clk_125MHz, 298 | wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren. 299 | input =>transmit_data_length_tmp, 300 | output =>data_length_regout 301 | ); 302 | ---------------------------------------------------------------------------------------------------- 303 | 304 | tmp_total_length<="0000000000011100" + data_length_regout; 305 | 306 | tmp_header_checksum_baseval<="1011011101111101"; -- CHANGE VALUE! : You have to change this value! 307 | tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout; 308 | 309 | tmp_length<="0000000000001000" + data_length_regout; 310 | 311 | ---------------------------------------------------------------------------------------------------- 312 | 313 | ---------------------------------------------------------------------------------------------------- 314 | -- Component Name: IPV4_LUT_INDEXER 315 | -- Instance Name: IPV4_LUT_INDEXER_port_map 316 | -- Description: When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the 317 | -- addresses to the LUT that contains the header section of the IP packet. 318 | ---------------------------------------------------------------------------------------------------- 319 | IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map 320 | ( 321 | rst =>rst, 322 | clk =>clk_125MHz, 323 | transmit_enable =>transmit_start_enable_tmp, 324 | LUT_index =>LUT_addr 325 | ); 326 | ---------------------------------------------------------------------------------------------------- 327 | 328 | ---------------------------------------------------------------------------------------------------- 329 | -- Component Name: dist_mem_64x8 330 | -- Instance Name: LUT_MEM 331 | -- Description: LUT that contains the header section. 332 | ---------------------------------------------------------------------------------------------------- 333 | LUT_MEM : dist_mem_64x8 port map 334 | ( 335 | clk =>clk_125MHz, 336 | a =>LUT_addr, 337 | qspo =>transmit_data_output_bus_tmp 338 | ); 339 | ---------------------------------------------------------------------------------------------------- 340 | 341 | ---------------------------------------------------------------------------------------------------- 342 | -- Component Name: OVERRIDE_LUT_CONTROL 343 | -- Instance Name: OVERRIDE_LUT_CONTROL_port_map 344 | -- Description: Decides whether the output byte will come from the LUT or not. 345 | ---------------------------------------------------------------------------------------------------- 346 | OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map 347 | ( 348 | clk =>clk_125MHz, 349 | input_addr =>LUT_addr, 350 | sel_total_length_MSBs =>sel_total_length_MSBs, 351 | sel_total_length_LSBs =>sel_total_length_LSBs, 352 | sel_header_checksum_MSBs =>sel_header_checksum_MSBs, 353 | sel_header_checksum_LSBs =>sel_header_checksum_LSBs, 354 | sel_length_MSBs =>sel_length_MSBs, 355 | sel_length_LSBs =>sel_length_LSBs 356 | ); 357 | ---------------------------------------------------------------------------------------------------- 358 | 359 | ---------------------------------------------------------------------------------------------------- 360 | -- MUX 7 to 1 361 | sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs); 362 | sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs); 363 | sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs); 364 | sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs); 365 | sel_length_MSBs_vec<=(others=>sel_length_MSBs); 366 | sel_length_LSBs_vec<=(others=>sel_length_LSBs); 367 | lut_out_sel_vec <= (others=>lut_out_sel); 368 | 369 | lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and 370 | (not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and 371 | (not sel_length_MSBs) and (not sel_length_LSBs); 372 | 373 | -- MUX output 374 | transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or 375 | (tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or 376 | (tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or 377 | (tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or 378 | (tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or 379 | (tmp_length(15 downto 8) and sel_length_MSBs_vec) or 380 | (tmp_length(7 downto 0) and sel_length_LSBs_vec); 381 | ---------------------------------------------------------------------------------------------------- 382 | 383 | ---------------------------------------------------------------------------------------------------- 384 | -- Component Name: ALLOW_ZERO_UDP_CHECKSUM 385 | -- Instance Name: ALLOW_ZERO_UDP_CHECKSUM_port_map 386 | -- Description: Delays the user data transmition phase in order to transmit two bytes with zero 387 | -- first. 388 | ---------------------------------------------------------------------------------------------------- 389 | ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map 390 | ( 391 | clk =>clk_125MHz, 392 | input =>sel_length_LSBs, 393 | output_to_readen =>start_usr_data_read, 394 | output_to_datasel =>start_usr_data_trans 395 | ); 396 | ---------------------------------------------------------------------------------------------------- 397 | 398 | ---------------------------------------------------------------------------------------------------- 399 | -- Component Name: ENABLE_USER_DATA_TRANSMISSION 400 | -- Instance Name: ENABLE_USER_DATA_READ_port_map 401 | -- Description: Sets usr_data_trans_phase_on signal one cycle before the transmittion of the 402 | -- first user byte. 403 | ---------------------------------------------------------------------------------------------------- 404 | ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map 405 | ( rst =>rst, 406 | clk =>clk_125MHz, 407 | start_usr_data_trans =>start_usr_data_read, 408 | stop_usr_data_trans =>end_of_frame_O_tmp, 409 | usr_data_sel =>usr_data_trans_phase_on 410 | ); 411 | ---------------------------------------------------------------------------------------------------- 412 | 413 | ---------------------------------------------------------------------------------------------------- 414 | -- Component Name: ENABLE_USER_DATA_TRANSMISSION 415 | -- Instance Name: ENABLE_USER_DATA_TRANSMISSION_port_map 416 | -- Description: Sets usr_data_sel_sig signal to select user data for transmittion. 417 | ---------------------------------------------------------------------------------------------------- 418 | ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map 419 | ( rst =>rst, 420 | clk =>clk_125MHz, 421 | start_usr_data_trans =>start_usr_data_trans, 422 | stop_usr_data_trans =>end_of_frame_O_tmp, 423 | usr_data_sel =>usr_data_sel_sig 424 | ); 425 | ---------------------------------------------------------------------------------------------------- 426 | 427 | ---------------------------------------------------------------------------------------------------- 428 | -- MUX 2 to 1 429 | usr_data_not_sel_vec<=(others=>not usr_data_sel_sig); 430 | usr_data_sel_vec<=(others=>usr_data_sel_sig); 431 | 432 | -- MUX output 433 | transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or 434 | (transmit_data_input_bus and usr_data_sel_vec); 435 | ---------------------------------------------------------------------------------------------------- 436 | 437 | end Behavioral; 438 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPv4_PACKET_RECEIVER.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------------------- 2 | -- Copyright (C) 2010 Nikolaos Ch. Alachiotis -- 3 | -- -- 4 | -- Engineer: Nikolaos Ch. Alachiotis -- 5 | -- -- 6 | -- Contact: alachiot@cs.tum.edu -- 7 | -- n.alachiotis@gmail.com -- 8 | -- -- 9 | -- Create Date: 14:32:06 02/07/2010 -- 10 | -- Module Name: IPv4_PACKET_RECEIVER -- 11 | -- Target Devices: Virtex 5 FPGAs -- 12 | -- Tool versions: ISE 10.1 -- 13 | -- Description: This component can be used to receive IPv4 Ethernet Packets. -- 14 | -- Additional Comments: -- 15 | -- -- 16 | -- The receiver does not operate properly for data section of 1 or 2 bytes only. -- 17 | -- -- 18 | ----------------------------------------------------------------------------------------- 19 | 20 | 21 | library IEEE; 22 | use IEEE.STD_LOGIC_1164.ALL; 23 | use IEEE.STD_LOGIC_ARITH.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | 26 | ---- Uncomment the following library declaration if instantiating 27 | ---- any Xilinx primitives in this code. 28 | --library UNISIM; 29 | --use UNISIM.VComponents.all; 30 | 31 | entity IPv4_PACKET_RECEIVER is 32 | Port ( rst : in STD_LOGIC; 33 | clk_125Mhz : in STD_LOGIC; 34 | rx_sof : in STD_LOGIC; 35 | rx_eof : in STD_LOGIC; 36 | input_bus : in STD_LOGIC_VECTOR(7 downto 0); 37 | valid_out_usr_data : out STD_LOGIC; 38 | usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)); 39 | end IPv4_PACKET_RECEIVER; 40 | 41 | architecture Behavioral of IPv4_PACKET_RECEIVER is 42 | 43 | component PACKET_RECEIVER_FSM is 44 | Port ( 45 | rst : in STD_LOGIC; 46 | clk : in STD_LOGIC; 47 | 48 | -- Signals from EMAC 49 | rx_sof: in STD_LOGIC; -- active low input 50 | rx_eof: in STD_LOGIC; -- active low input 51 | 52 | -- Signals to Counter and Comparator 53 | sel_comp_Bval: out STD_LOGIC; 54 | comp_Bval: out STD_LOGIC_VECTOR(10 downto 0); 55 | rst_count : out STD_LOGIC; 56 | en_count : out STD_LOGIC; 57 | 58 | -- Signal from Comparator 59 | comp_eq: in STD_LOGIC; 60 | 61 | -- Signals to Length Register 62 | wren_MSbyte: out STD_LOGIC; 63 | wren_LSbyte: out STD_LOGIC; 64 | 65 | -- Signal to user interface 66 | valid_out_usr_data : out STD_LOGIC); 67 | end component; 68 | 69 | component REG_8b_wren is 70 | Port ( rst : in STD_LOGIC; 71 | clk : in STD_LOGIC; 72 | wren : in STD_LOGIC; 73 | input_val : in STD_LOGIC_VECTOR (7 downto 0); 74 | output_val : inout STD_LOGIC_VECTOR(7 downto 0)); 75 | end component; 76 | 77 | component COUNTER_11B_EN_RECEIV is 78 | Port ( rst : in STD_LOGIC; 79 | clk : in STD_LOGIC; 80 | count_en : in STD_LOGIC; 81 | value_O : inout STD_LOGIC_VECTOR (10 downto 0)); 82 | end component; 83 | 84 | component comp_11b_equal is 85 | port ( 86 | qa_eq_b : out STD_LOGIC; 87 | clk : in STD_LOGIC := 'X'; 88 | a : in STD_LOGIC_VECTOR ( 10 downto 0 ); 89 | b : in STD_LOGIC_VECTOR ( 10 downto 0 ) 90 | ); 91 | end component; 92 | 93 | signal sel_comp_Bval, 94 | rst_count, 95 | en_count, 96 | comp_eq, 97 | wren_MSbyte, 98 | wren_LSbyte: STD_LOGIC; 99 | 100 | signal MSbyte_reg_val_out, 101 | LSbyte_reg_val_out : STD_LOGIC_VECTOR(7 downto 0); 102 | 103 | signal counter_val, 104 | match_val, 105 | comp_Bval, 106 | comp_sel_val_vec, 107 | comp_n_sel_val_vec, 108 | length_val: STD_LOGIC_VECTOR(10 downto 0); 109 | 110 | constant length_offest : STD_LOGIC_VECTOR(7 downto 0):="00001010"; 111 | -- This value is formed as 2 (1 clock the latency of comparator and 1 clock fro changing the FSM state) + 8 (number of bytes of UDP header section) 112 | 113 | begin 114 | 115 | usr_data_output_bus<=input_bus; 116 | 117 | PACKET_RECEIVER_FSM_port_map: PACKET_RECEIVER_FSM Port Map 118 | ( 119 | rst => rst, 120 | clk => clk_125MHz, 121 | 122 | rx_sof => rx_sof, 123 | rx_eof => rx_eof, 124 | 125 | sel_comp_Bval => sel_comp_Bval, 126 | comp_Bval => comp_Bval, 127 | rst_count => rst_count, 128 | en_count => en_count, 129 | 130 | comp_eq => comp_eq, 131 | 132 | wren_MSbyte => wren_MSbyte, 133 | wren_LSbyte => wren_LSbyte, 134 | 135 | valid_out_usr_data => valid_out_usr_data 136 | ); 137 | 138 | MSbyte_REG: REG_8b_wren Port Map 139 | ( 140 | rst => rst, 141 | clk => clk_125MHz, 142 | wren => wren_MSbyte, 143 | input_val => input_bus, 144 | output_val =>MSbyte_reg_val_out 145 | ); 146 | 147 | LSbyte_REG: REG_8b_wren Port Map 148 | ( 149 | rst => rst, 150 | clk => clk_125MHz, 151 | wren => wren_LSbyte, 152 | input_val => input_bus, 153 | output_val =>LSbyte_reg_val_out 154 | ); 155 | 156 | COUNTER_11B_EN_port_map: COUNTER_11B_EN_RECEIV Port Map 157 | ( 158 | rst => rst_count, 159 | clk => clk_125MHz, 160 | count_en => en_count, 161 | value_O => counter_val 162 | ); 163 | 164 | Comp_11b_equal_port_map: Comp_11b_equal Port Map 165 | ( 166 | qa_eq_b => comp_eq, 167 | clk => clk_125MHz, 168 | a => counter_val, 169 | b => match_val 170 | ); 171 | 172 | length_val(7 downto 0)<= LSbyte_reg_val_out-length_offest; 173 | length_val(10 downto 8)<= MSbyte_reg_val_out (2 downto 0); 174 | 175 | comp_sel_val_vec<=(others=> sel_comp_Bval); 176 | comp_n_sel_val_vec<= (others=> not sel_comp_Bval); 177 | 178 | match_val<= (comp_sel_val_vec and length_val) or (comp_n_sel_val_vec and comp_Bval); 179 | 180 | 181 | end Behavioral; 182 | 183 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/OVERRIDE_LUT_CONTROL.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:09:25 11/30/2009 6 | -- Design Name: 7 | -- Module Name: OVERRIDE_LUT_CONTROL - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity OVERRIDE_LUT_CONTROL is 31 | Port ( clk : in STD_LOGIC; 32 | input_addr : in STD_LOGIC_VECTOR (5 downto 0); 33 | sel_total_length_MSBs : out STD_LOGIC; 34 | sel_total_length_LSBs : out STD_LOGIC; 35 | sel_header_checksum_MSBs : out STD_LOGIC; 36 | sel_header_checksum_LSBs : out STD_LOGIC; 37 | sel_length_MSBs : out STD_LOGIC; 38 | sel_length_LSBs : out STD_LOGIC 39 | ); 40 | end OVERRIDE_LUT_CONTROL; 41 | 42 | architecture Behavioral of OVERRIDE_LUT_CONTROL is 43 | 44 | component comp_6b_equal is 45 | port ( 46 | qa_eq_b : out STD_LOGIC; 47 | clk : in STD_LOGIC := 'X'; 48 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 49 | b : in STD_LOGIC_VECTOR ( 5 downto 0 ) 50 | ); 51 | end component; 52 | 53 | constant total_length_addr1 : std_logic_vector(5 downto 0):="010000"; 54 | constant total_length_addr2 : std_logic_vector(5 downto 0):="010001"; 55 | 56 | constant header_checksum_addr1 : std_logic_vector(5 downto 0):="011000"; 57 | constant header_checksum_addr2 : std_logic_vector(5 downto 0):="011001"; 58 | 59 | constant length_addr1 : std_logic_vector(5 downto 0):="100110"; 60 | constant length_addr2 : std_logic_vector(5 downto 0):="100111"; 61 | 62 | 63 | signal sel_header_checksum_MSBs_tmp : std_logic; 64 | signal sel_total_length_MSBs_tmp : std_logic; 65 | signal sel_length_MSBs_tmp : std_logic; 66 | 67 | begin 68 | 69 | TARGET_TOTAL_LENGTH_1 : comp_6b_equal port map (sel_total_length_MSBs_tmp,clk,input_addr,total_length_addr1); 70 | 71 | process(clk) 72 | begin 73 | if clk'event and clk='1' then 74 | sel_total_length_LSBs<=sel_total_length_MSBs_tmp; 75 | end if; 76 | end process; 77 | sel_total_length_MSBs<=sel_total_length_MSBs_tmp; 78 | 79 | --TARGET_TOTAL_LENGTH_2 : comp_6b_equal port map (sel_total_length_LSBs,clk,input_addr,total_length_addr2); 80 | 81 | TARGET_HEADER_CHECKSUM_1 : comp_6b_equal port map (sel_header_checksum_MSBs_tmp,clk,input_addr,header_checksum_addr1); 82 | process(clk) 83 | begin 84 | if clk'event and clk='1' then 85 | sel_header_checksum_LSBs<=sel_header_checksum_MSBs_tmp; 86 | end if; 87 | end process; 88 | 89 | sel_header_checksum_MSBs<=sel_header_checksum_MSBs_tmp; 90 | 91 | 92 | 93 | --TARGET_HEADER_CHECKSUM_2 : comp_6b_equal port map (sel_header_checksum_LSBs,clk,input_addr,header_checksum_addr2); 94 | 95 | TARGET_LENGTH_1 : comp_6b_equal port map (sel_length_MSBs_tmp,clk,input_addr,length_addr1); 96 | 97 | process(clk) 98 | begin 99 | if clk'event and clk='1' then 100 | sel_length_LSBs<=sel_length_MSBs_tmp; 101 | end if; 102 | end process; 103 | 104 | sel_length_MSBs<=sel_length_MSBs_tmp; 105 | --TARGET_LENGTH_2 : comp_6b_equal port map (sel_length_LSBs,clk,input_addr,length_addr2); 106 | 107 | end Behavioral; 108 | 109 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/PACKET_RECEIVER_FSM.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 03:48:34 02/07/2010 6 | -- Design Name: 7 | -- Module Name: PACKET_RECEIVER_FSM - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity PACKET_RECEIVER_FSM is 31 | Port ( 32 | rst : in STD_LOGIC; 33 | clk : in STD_LOGIC; 34 | 35 | -- Signals from EMAC 36 | rx_sof: in STD_LOGIC; -- active low input 37 | rx_eof: in STD_LOGIC; -- active low input 38 | 39 | -- Signals to Counter and Comparator 40 | sel_comp_Bval: out STD_LOGIC; 41 | comp_Bval: out STD_LOGIC_VECTOR(10 downto 0); 42 | rst_count : out STD_LOGIC; 43 | en_count : out STD_LOGIC; 44 | 45 | -- Signal from Comparator 46 | comp_eq: in STD_LOGIC; 47 | 48 | -- Signals to Length Register 49 | wren_MSbyte: out STD_LOGIC; 50 | wren_LSbyte: out STD_LOGIC; 51 | 52 | -- Signal to user interface 53 | valid_out_usr_data: out STD_LOGIC); 54 | end PACKET_RECEIVER_FSM; 55 | 56 | architecture Behavioral of PACKET_RECEIVER_FSM is 57 | 58 | TYPE state is (rst_state, 59 | idle_state, 60 | detect_n_store_usr_length_MSbyte_state, 61 | store_usr_length_LSbyte_state, 62 | checksum_gap_state, 63 | receive_usr_data_state); 64 | 65 | signal current_st,next_st: state; 66 | 67 | constant udp_length_match_cycle : std_logic_vector(10 downto 0):="00000100100"; -- UDP length MSbyte - 2 68 | constant udp_checksum_skip : std_logic_vector(10 downto 0):="00000000001"; 69 | constant gnd_vec : std_logic_vector(10 downto 0):="00000000000"; 70 | begin 71 | 72 | process(current_st,rx_sof,rx_eof,comp_eq) 73 | begin 74 | case current_st is 75 | 76 | 77 | when rst_state => 78 | 79 | sel_comp_Bval<='0'; 80 | comp_Bval<=gnd_vec; 81 | rst_count<='1'; 82 | en_count<='0'; 83 | 84 | wren_MSbyte<='0'; 85 | wren_LSbyte<='0'; 86 | 87 | valid_out_usr_data<='0'; 88 | 89 | next_st<=idle_state; 90 | 91 | when idle_state => 92 | 93 | if rx_sof='0' then -- rx_sof is active low 94 | sel_comp_Bval<='0'; 95 | comp_Bval<=udp_length_match_cycle; 96 | rst_count<='1'; 97 | en_count<='0'; 98 | 99 | wren_MSbyte<='0'; 100 | wren_LSbyte<='0'; 101 | 102 | valid_out_usr_data<='0'; 103 | 104 | next_st<=detect_n_store_usr_length_MSbyte_state; 105 | 106 | else 107 | sel_comp_Bval<='0'; 108 | comp_Bval<=gnd_vec; 109 | rst_count<='0'; 110 | en_count<='0'; 111 | 112 | wren_MSbyte<='0'; 113 | wren_LSbyte<='0'; 114 | 115 | valid_out_usr_data<='0'; 116 | 117 | next_st<=idle_state; 118 | end if; 119 | 120 | when detect_n_store_usr_length_MSbyte_state => 121 | 122 | if comp_eq='1' then -- comp_eq is active high 123 | sel_comp_Bval<='0'; 124 | comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field 125 | rst_count<='1'; 126 | en_count<='0'; 127 | 128 | wren_MSbyte<='1'; 129 | wren_LSbyte<='0'; 130 | 131 | valid_out_usr_data<='0'; 132 | 133 | next_st<=store_usr_length_LSbyte_state; 134 | 135 | else 136 | sel_comp_Bval<='0'; 137 | comp_Bval<=udp_length_match_cycle; 138 | rst_count<='0'; 139 | en_count<='1'; 140 | 141 | wren_MSbyte<='0'; 142 | wren_LSbyte<='0'; 143 | 144 | valid_out_usr_data<='0'; 145 | 146 | next_st<=detect_n_store_usr_length_MSbyte_state; 147 | end if; 148 | 149 | when store_usr_length_LSbyte_state => 150 | 151 | sel_comp_Bval<='0'; 152 | comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field 153 | rst_count<='0'; 154 | en_count<='1'; 155 | 156 | wren_MSbyte<='0'; 157 | wren_LSbyte<='1'; 158 | 159 | valid_out_usr_data<='0'; 160 | 161 | next_st<=checksum_gap_state; 162 | 163 | when checksum_gap_state => 164 | 165 | if comp_eq='1' then -- comp_eq is active high 166 | sel_comp_Bval<='1'; 167 | comp_Bval<=gnd_vec; 168 | rst_count<='1'; 169 | en_count<='0'; 170 | 171 | wren_MSbyte<='0'; 172 | wren_LSbyte<='0'; 173 | 174 | valid_out_usr_data<='0'; 175 | 176 | next_st<=receive_usr_data_state; 177 | 178 | else 179 | sel_comp_Bval<='0'; 180 | comp_Bval<=udp_checksum_skip; 181 | rst_count<='0'; 182 | en_count<='1'; 183 | 184 | wren_MSbyte<='0'; 185 | wren_LSbyte<='0'; 186 | 187 | valid_out_usr_data<='0'; 188 | 189 | next_st<=checksum_gap_state; 190 | end if; 191 | 192 | when receive_usr_data_state => 193 | 194 | if (comp_eq='1' or rx_eof='0') then -- comp_eq is active high rx_eof is active-low 195 | sel_comp_Bval<='0'; 196 | comp_Bval<=udp_length_match_cycle; 197 | rst_count<='1'; 198 | en_count<='0'; 199 | 200 | wren_MSbyte<='0'; 201 | wren_LSbyte<='0'; 202 | 203 | valid_out_usr_data<='1'; 204 | 205 | next_st<=idle_state; 206 | 207 | else 208 | sel_comp_Bval<='1'; 209 | comp_Bval<=gnd_vec; 210 | rst_count<='0'; 211 | en_count<='1'; 212 | 213 | wren_MSbyte<='0'; 214 | wren_LSbyte<='0'; 215 | 216 | valid_out_usr_data<='1'; 217 | 218 | next_st<=receive_usr_data_state; 219 | end if; 220 | 221 | 222 | end case; 223 | end process; 224 | 225 | 226 | 227 | 228 | process(clk) 229 | begin 230 | if (rst='1') then 231 | current_st<= rst_state; 232 | elsif (clk'event and clk='1') then 233 | current_st <= next_st; 234 | end if; 235 | end process; 236 | 237 | end Behavioral; 238 | 239 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_16B_WREN.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 21:15:16 11/27/2009 6 | -- Design Name: 7 | -- Module Name: REG_16B_WREN - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 16bit wide Register with write enable option. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity REG_16B_WREN is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | wren : in STD_LOGIC; 34 | input : in STD_LOGIC_VECTOR (15 downto 0); 35 | output : out STD_LOGIC_VECTOR (15 downto 0)); 36 | end REG_16B_WREN; 37 | 38 | architecture Behavioral of REG_16B_WREN is 39 | 40 | begin 41 | 42 | process(clk) 43 | begin 44 | if rst='1' then 45 | output<="0000000000000000"; 46 | else 47 | if clk'event and clk='1' then 48 | if wren='1' then 49 | output<=input; 50 | end if; 51 | end if; 52 | end if; 53 | end process; 54 | 55 | end Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_8b_wren.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:40:03 02/07/2010 6 | -- Design Name: 7 | -- Module Name: REG_8b_wren - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity REG_8b_wren is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | wren : in STD_LOGIC; 34 | input_val : in STD_LOGIC_VECTOR (7 downto 0); 35 | output_val : inout STD_LOGIC_VECTOR(7 downto 0)); 36 | end REG_8b_wren; 37 | 38 | architecture Behavioral of REG_8b_wren is 39 | 40 | begin 41 | 42 | process(clk) 43 | begin 44 | if rst='1' then 45 | output_val<="00000000"; 46 | else 47 | if clk'event and clk='1' then 48 | if wren='1' then 49 | output_val<=input_val; 50 | end if; 51 | end if; 52 | end if; 53 | end process; 54 | 55 | end Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/TARGET_EOF.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:22:56 11/30/2009 6 | -- Design Name: 7 | -- Module Name: TARGET_EOF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | ---- Uncomment the following library declaration if instantiating 26 | ---- any Xilinx primitives in this code. 27 | --library UNISIM; 28 | --use UNISIM.VComponents.all; 29 | 30 | entity TARGET_EOF is 31 | Port ( rst : in STD_LOGIC; 32 | clk : in STD_LOGIC; 33 | start : in STD_LOGIC; 34 | total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0); 35 | eof_O : out STD_LOGIC); 36 | end TARGET_EOF; 37 | 38 | architecture Behavioral of TARGET_EOF is 39 | 40 | signal count_end : std_logic:='0'; 41 | signal count_en_sig : std_logic:='0'; 42 | signal rst_counter : std_logic:='0'; 43 | 44 | component COUNTER_11B_EN_TRANS is 45 | Port ( rst : in STD_LOGIC; 46 | clk : in STD_LOGIC; 47 | count_en : in STD_LOGIC; 48 | value_O : inout STD_LOGIC_VECTOR (10 downto 0)); 49 | end component; 50 | 51 | signal value_O_tmp : std_logic_vector(10 downto 0); 52 | 53 | component comp_11b_equal is 54 | port ( 55 | qa_eq_b : out STD_LOGIC; 56 | clk : in STD_LOGIC := 'X'; 57 | a : in STD_LOGIC_VECTOR ( 10 downto 0 ); 58 | b : in STD_LOGIC_VECTOR ( 10 downto 0 ) 59 | ); 60 | end component; 61 | 62 | signal last_byte,last_byte_reg_in,last_byte_reg_out : std_logic; 63 | 64 | begin 65 | 66 | process(clk) 67 | begin 68 | if (rst='1' or count_end='1') then 69 | count_en_sig<='0'; 70 | rst_counter<='1'; 71 | else 72 | rst_counter<='0'; 73 | if clk'event and clk='1' then 74 | if (start='1' and count_en_sig='0') then 75 | count_en_sig<='1'; 76 | end if; 77 | end if; 78 | end if; 79 | end process; 80 | 81 | 82 | COUNT_TRANFERED_BYTES : COUNTER_11B_EN_TRANS port map 83 | ( rst =>rst_counter, 84 | clk =>clk, 85 | count_en => count_en_sig, 86 | value_O =>value_O_tmp 87 | ); 88 | 89 | COMP_TO_TARGET_LAST_BYTE : comp_11b_equal port map 90 | ( 91 | qa_eq_b =>last_byte_reg_in, 92 | clk =>clk, 93 | a =>value_O_tmp, 94 | b =>total_length_from_reg(10 downto 0) 95 | ); 96 | 97 | process(clk) 98 | begin 99 | if clk'event and clk='1' then 100 | last_byte_reg_out<=last_byte_reg_in; 101 | end if; 102 | end process; 103 | eof_O<=not last_byte_reg_out; 104 | count_end<=last_byte_reg_out; 105 | end Behavioral; 106 | 107 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/UDP_IP_Core.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------------------- 2 | -- Copyright (C) 2010 Nikolaos Ch. Alachiotis -- 3 | -- -- 4 | -- Engineer: Nikolaos Ch. Alachiotis -- 5 | -- -- 6 | -- Contact: alachiot@cs.tum.edu -- 7 | -- n.alachiotis@gmail.com -- 8 | -- -- 9 | -- Create Date: 15:29:59 02/07/2010 -- 10 | -- Module Name: UDP_IP_Core -- 11 | -- Target Devices: Virtex 5 FPGAs -- 12 | -- Tool versions: ISE 10.1 -- 13 | -- Description: This component can be used to transmit and receive UDP/IP -- 14 | -- Ethernet Packets (IPv4). -- 15 | -- Additional Comments: The core has been area-optimized and is suitable for direct -- 16 | -- PC-FPGA communication at Gigabit speed. -- 17 | -- -- 18 | ----------------------------------------------------------------------------------------- 19 | 20 | 21 | library IEEE; 22 | use IEEE.STD_LOGIC_1164.ALL; 23 | use IEEE.STD_LOGIC_ARITH.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | 26 | ---- Uncomment the following library declaration if instantiating 27 | ---- any Xilinx primitives in this code. 28 | --library UNISIM; 29 | --use UNISIM.VComponents.all; 30 | 31 | entity UDP_IP_Core is 32 | Port ( rst : in STD_LOGIC; -- active-high 33 | clk_125MHz : in STD_LOGIC; 34 | 35 | -- Transmit signals 36 | transmit_start_enable : in STD_LOGIC; 37 | transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); 38 | usr_data_trans_phase_on : out STD_LOGIC; 39 | transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); 40 | start_of_frame_O : out STD_LOGIC; 41 | end_of_frame_O : out STD_LOGIC; 42 | source_ready : out STD_LOGIC; 43 | transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0); 44 | 45 | --Receive Signals 46 | rx_sof : in STD_LOGIC; 47 | rx_eof : in STD_LOGIC; 48 | input_bus : in STD_LOGIC_VECTOR(7 downto 0); 49 | valid_out_usr_data : out STD_LOGIC; 50 | usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0) 51 | ); 52 | end UDP_IP_Core; 53 | 54 | architecture Behavioral of UDP_IP_Core is 55 | 56 | component IPV4_PACKET_TRANSMITTER is 57 | Port ( rst : in STD_LOGIC; 58 | clk_125MHz : in STD_LOGIC; 59 | transmit_start_enable : in STD_LOGIC; 60 | transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); 61 | usr_data_trans_phase_on : out STD_LOGIC; 62 | transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); 63 | start_of_frame_O : out STD_LOGIC; 64 | end_of_frame_O : out STD_LOGIC; 65 | source_ready : out STD_LOGIC; 66 | transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0) 67 | ); 68 | end component; 69 | 70 | component IPv4_PACKET_RECEIVER is 71 | Port ( rst : in STD_LOGIC; 72 | clk_125Mhz : in STD_LOGIC; 73 | rx_sof : in STD_LOGIC; 74 | rx_eof : in STD_LOGIC; 75 | input_bus : in STD_LOGIC_VECTOR(7 downto 0); 76 | valid_out_usr_data : out STD_LOGIC; 77 | usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)); 78 | end component; 79 | 80 | begin 81 | 82 | IPV4_PACKET_TRANSMITTER_port_map: IPV4_PACKET_TRANSMITTER 83 | Port Map 84 | ( rst => rst, 85 | clk_125MHz => clk_125MHz, 86 | transmit_start_enable => transmit_start_enable, 87 | transmit_data_length => transmit_data_length, 88 | usr_data_trans_phase_on => usr_data_trans_phase_on, 89 | transmit_data_input_bus => transmit_data_input_bus, 90 | start_of_frame_O => start_of_frame_O, 91 | end_of_frame_O => end_of_frame_O, 92 | source_ready => source_ready, 93 | transmit_data_output_bus => transmit_data_output_bus 94 | ); 95 | 96 | 97 | IPv4_PACKET_RECEIVER_port_map: IPv4_PACKET_RECEIVER 98 | Port Map 99 | ( rst => rst, 100 | clk_125Mhz => clk_125Mhz, 101 | rx_sof => rx_sof, 102 | rx_eof => rx_eof, 103 | input_bus => input_bus, 104 | valid_out_usr_data => valid_out_usr_data, 105 | usr_data_output_bus => usr_data_output_bus 106 | ); 107 | 108 | end Behavioral; 109 | 110 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.ngc: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.4e 3 | $8dx5d=#Zl|bdaa:!3-522):'?%8#?/$0937>7)88:0=<4FNQWW>d:683:5==5>1;KMTPR=j5;;6=0i;4tp|<3sno;:?;#>119:456789:;<=>?0127?<6718:05=>60123456719:2?6LZ299AQVYNFOE:7N;:;B8,TMbXX{eainz|/Ujf[Cck{ldxxhga_BmSvjeb{zey#NA]EFGM[Actand$x`~ _be,gjkwW8;iShzam,mcj753JBNOFQCIBGMW@YSQYO27NABMHVWAA733JEYIRIJNDPBPLIIW@DMC:5LRDCWAA72FDMIKK7:NLCLEFD=1GYY:;;MWW2f=JiceyZh||inl`?Hoig{\n~~g`n29M555H6?:1E=5=4N0;1?K443G8;?6@=129M675H4>;1E8?5A539M27=I?;1E4?5A9g9MFZDR[YCES]\@PR58J@RPG[A:7B<4OJ38T1=WI[^j7]GA_CWPMA^e3YCESO[\N@OF5>W13ZE^^NK;;U[SA3e<]9%licQ|tsw`pptbWeelen heo]mkkvnxlfbbhj!a^grqdjXff~n}xoc_c,j[dYbyVdnSo!heo]lqqvr|Vxnk#aztqww[wc`'on$cxzuu]2=f=R8&mnbR}{rtawqwcXdfmbo#ijn^lljuowmeceii n_dsveiYig}ozylbPb/k\eZcvWgoTn"gPurg\gdtuqVzgy~Qcuuq-hprXign%eRintd]amq)salxTkh`T1\,j[qobz&fdc}Q{imgp_5[)aV~b`h!`12;:g>S7'noeS~z}ubvvv`Ykgnch"jka_ommtlvbd`dnh#oPepwbhZhh|l{~maQm.h]b[`wXflUi#dQzsd]`ewt~Wyf~Rbztr,oqqYffm$bSjo{e^`jp*rnm{UlicU>]/k\plcu'eed|RzfldqX4X(nW}cgi"a>88;`?P6(oldTy|zcuwqaZjho`i%kh`Pnnlsmuckagoo"lQjqtco[kismxj`Rl!i^c\atYimVh$eR{|e^abvwXxexSa{{s/nvpZgil'cTklzj_ckw+qobzVmnbV?R.h]wm`t(dfe{SygcerY3Y+oX|`fn#b8<4U1-dakYt|{hxx|j_mmdmf(`mgUecc~fpdnjj`b)iVozylbPnnvfupgkWk$bSlQjq^lf[g)smdzT~h}zluc8QVCUWHFBM^m4URGQ[SOTAKFN?6XLC89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6V\TMKA3>^T\VMEHo5W_BMQAZOINF<0TilPIed8\anXX{cfZh||inl24>^ceVGjfb|Yesqjkk773QnfS@gaosTfvvohf=1j$=';;`*2-0=f 8:"86o'2(68e-5.<2k#8$:4a)7*0>g/> >0m%9&4:c+<,27l2>0?68e979<2k7>3:4a=1=0>g;<7>0m1;14:c?2;22kTi|Qm6:c\c`Ye>2kTkyQm6:c\h`Ye>2kT`yQm6:c\j`Ye<2kh`:4argw0>d/8 >0n%?&5:`+55/33k"9%95m(2+7?g.3!=1i$8';;c*5-1=e >#?7o&7)59a,0;;c>7:1=e4<4?7o29>59a82833k63295m<8<05>eXkfg{mkPv8]3(%^nd`ds,NA]E!Efj`tf|fx+== >.11\mu553jo87nbde:aliuY69kUn}xoc269`khvX98hTi|{nl-a\gjkwi{oTz4Q?,OMMA)HHFL;im6m`mq]25gYby|kg nQlolrbv`Yq1V:'wnQgar]reZabWk7; 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94 | GND_1 : GND 95 | port map ( 96 | G => NLW_GND_G_UNCONNECTED 97 | ); 98 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o206 : 99 | LUT6 100 | generic map( 101 | INIT => X"9000000000000000" 102 | ) 103 | port map ( 104 | I0 => a_2(2), 105 | I1 => b_3(2), 106 | I2 => 107 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_26 108 | , 109 | I3 => 110 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62_27 111 | , 112 | I4 => 113 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139_28 114 | , 115 | I5 => 116 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189_29 117 | , 118 | O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result 119 | ); 120 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189 : 121 | LUT6 122 | generic map( 123 | INIT => X"9009000000009009" 124 | ) 125 | port map ( 126 | I0 => a_2(5), 127 | I1 => b_3(5), 128 | I2 => a_2(6), 129 | I3 => b_3(6), 130 | I4 => a_2(7), 131 | I5 => b_3(7), 132 | O => 133 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189_29 134 | 135 | ); 136 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139 : 137 | LUT6 138 | generic map( 139 | INIT => X"9009000000009009" 140 | ) 141 | port map ( 142 | I0 => a_2(8), 143 | I1 => b_3(8), 144 | I2 => a_2(9), 145 | I3 => b_3(9), 146 | I4 => a_2(10), 147 | I5 => b_3(10), 148 | O => 149 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139_28 150 | 151 | ); 152 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62 : 153 | LUT4 154 | generic map( 155 | INIT => X"9009" 156 | ) 157 | port map ( 158 | I0 => a_2(3), 159 | I1 => b_3(3), 160 | I2 => a_2(4), 161 | I3 => b_3(4), 162 | O => 163 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62_27 164 | 165 | ); 166 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26 : 167 | LUT4 168 | generic map( 169 | INIT => X"9009" 170 | ) 171 | port map ( 172 | I0 => a_2(0), 173 | I1 => b_3(0), 174 | I2 => a_2(1), 175 | I3 => b_3(1), 176 | O => 177 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_26 178 | 179 | ); 180 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD 181 | generic map( 182 | INIT => '0' 183 | ) 184 | port map ( 185 | C => clk, 186 | D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result, 187 | Q => qa_eq_b 188 | ); 189 | BU2_XST_GND : GND 190 | port map ( 191 | G => BU2_a_ge_b 192 | ); 193 | 194 | end STRUCTURE; 195 | 196 | -- synthesis translate_on 197 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version K.39 4 | # Date: Mon Nov 30 15:37:25 2009 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = False 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = VHDL 21 | SET device = xc5vsx95t 22 | SET devicefamily = virtex5 23 | SET flowvendor = Other 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = ff1136 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -1 31 | SET verilogsim = False 32 | SET vhdlsim = True 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT Comparator family Xilinx,_Inc. 9.0 36 | # END Select 37 | # BEGIN Parameters 38 | CSET aclr=false 39 | CSET ainitval=0 40 | CSET aset=false 41 | CSET ce=false 42 | CSET cepriority=Sync_Overrides_CE 43 | CSET component_name=comp_11b_equal 44 | CSET constantbport=false 45 | CSET constantbportvalue=0000000000000000 46 | CSET datatype=Unsigned 47 | CSET nonregisteredoutput=false 48 | CSET operation=eq 49 | CSET pipelinestages=0 50 | CSET radix=2 51 | CSET registeredoutput=true 52 | CSET sclr=false 53 | CSET sset=false 54 | CSET syncctrlpriority=Reset_Overrides_Set 55 | CSET width=11 56 | # END Parameters 57 | GENERATE 58 | # CRC: 6f28c282 59 | 60 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.ngc: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.4e 3 | $92x5d=#Zl|bdaa:!3-522):'?%8#?/$09355=789:;<=>70323<54438$;j6;ysy;6pc`69:<&=h59:HLSQQ86M5/QJg[Uthbli"Zge^Dfhvci{}obbRM`Psm`avuhz&ID^HIJN^Ffwlai'}g{#Rmh/bmntZ0eWl{~ma agn31?FNBKBUGENKASD]W]UC>3JEFADZ[EE37?FIUMVMNBH\NTHMM[LHAG>1H^HO[EE38@7=AL81L?6IAD39J47=N9;1B>?5F339J07=N=01BBDZ\T@VF2>JHIMOO;6B@GHABH1=K]]>?7A[[6b9Neoiu^lxxeb`l;LkmkwPbzzcdb>5A0018J4643G;:?6@>229M56597C<<;O056>H4:2D?>6@:2:L56>H0:2D3>6@6f:LA[GSTX@DT\_A_S69MAQQHZB;0C?5@K09S0>VFZ]k0\D@PBTQJ@]dS7'noeS~z}ubvvv`Ykgnch"jka_ommtlvbd`dnh#oPepwbhZhh|l{~maQm.h]b[`wXflUi#dQzsd]`ewt~Wyf~Rbztr,oqqYffm$bSjo{e^`jp*rnm{UlicU>]/k\plcu'eed|RzfldqX4X(nW}cgi"a>06c3?P6(oldTy|zcuwqaZjho`i%kh`Pnnlsmuckagoo"lQjqtco[kismxj`Rl!i^c\atYimVh$eR{|e^abvwXxexSa{{s/nvpZgil'cTklzj_ckw+qobzVmnbV?R.h]wm`t(dfe{SygcerY3Y+oX|`fn#b??7^QT4S7'noeS~z}ubvvv`Ykgnch"jka_ommtlvbd`dnh#oPepwbhZhh|l{~maQm.h]b[`wXflUi#ykbp^pfwpjsi2_XI_QNLHCPg>STM[U]E^GMLD18RFE>3_CN[RZVPD3g?]OKAGR&TIL/0/3#WQSE(9$:,L]LIH48\VRKAK=0T^ZPGOFa?]YDG[OTECH@6:ZgfZOcn2RodR^}ilTfvvohf8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`;;`*3-1=f 8#?7l&=)59b,6/33h"?%95n(4+7?d:76=1j0<0;;`>1:1=f4:4?7l2;>79b80<76=1j0809;`]fuZd13hUliRl9;`]dpZd13hUgiRl9;`]opZd13hUeiRl;;`aov1=f{l~?7o&?)59a,4/33k"9%95m(2+7?g.3!=1i$8';;c>3:1=e484?7o2=>59a86833k6?2;5m<483:1=e4<48=6mPcnosewcX~0U; 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All rights reserved. 3 | -------------------------------------------------------------------------------- 4 | -- ____ ____ 5 | -- / /\/ / 6 | -- /___/ \ / Vendor: Xilinx 7 | -- \ \ \/ Version: K.39 8 | -- \ \ Application: netgen 9 | -- / / Filename: comp_6b_equal.vhd 10 | -- /___/ /\ Timestamp: Mon Nov 30 14:23:03 2009 11 | -- \ \ / \ 12 | -- \___\/\___\ 13 | -- 14 | -- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.vhd 15 | -- Device : 5vsx95tff1136-1 16 | -- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.ngc 17 | -- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.vhd 18 | -- # of Entities : 1 19 | -- Design Name : comp_6b_equal 20 | -- Xilinx : C:\Xilinx\10.1\ISE 21 | -- 22 | -- Purpose: 23 | -- This VHDL netlist is a verification model and uses simulation 24 | -- primitives which may not represent the true implementation of the 25 | -- device, however the netlist is functionally correct and should not 26 | -- be modified. This file cannot be synthesized and should only be used 27 | -- with supported simulation tools. 28 | -- 29 | -- Reference: 30 | -- Development System Reference Guide, Chapter 23 31 | -- Synthesis and Simulation Design Guide, Chapter 6 32 | -- 33 | -------------------------------------------------------------------------------- 34 | 35 | 36 | -- synthesis translate_off 37 | library IEEE; 38 | use IEEE.STD_LOGIC_1164.ALL; 39 | library UNISIM; 40 | use UNISIM.VCOMPONENTS.ALL; 41 | use UNISIM.VPKG.ALL; 42 | 43 | entity comp_6b_equal is 44 | port ( 45 | qa_eq_b : out STD_LOGIC; 46 | clk : in STD_LOGIC := 'X'; 47 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 48 | b : in STD_LOGIC_VECTOR ( 5 downto 0 ) 49 | ); 50 | end comp_6b_equal; 51 | 52 | architecture STRUCTURE of comp_6b_equal is 53 | signal BU2_N01 : STD_LOGIC; 54 | signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16 : STD_LOGIC; 55 | 56 | signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC; 57 | signal BU2_a_ge_b : STD_LOGIC; 58 | signal NLW_VCC_P_UNCONNECTED : STD_LOGIC; 59 | signal NLW_GND_G_UNCONNECTED : STD_LOGIC; 60 | signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 ); 61 | signal b_3 : STD_LOGIC_VECTOR ( 5 downto 0 ); 62 | begin 63 | a_2(5) <= a(5); 64 | a_2(4) <= a(4); 65 | a_2(3) <= a(3); 66 | a_2(2) <= a(2); 67 | a_2(1) <= a(1); 68 | a_2(0) <= a(0); 69 | b_3(5) <= b(5); 70 | b_3(4) <= b(4); 71 | b_3(3) <= b(3); 72 | b_3(2) <= b(2); 73 | b_3(1) <= b(1); 74 | b_3(0) <= b(0); 75 | VCC_0 : VCC 76 | port map ( 77 | P => NLW_VCC_P_UNCONNECTED 78 | ); 79 | GND_1 : GND 80 | port map ( 81 | G => NLW_GND_G_UNCONNECTED 82 | ); 83 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o107 : 84 | LUT6 85 | generic map( 86 | INIT => X"0000000080200802" 87 | ) 88 | port map ( 89 | I0 => 90 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16 91 | , 92 | I1 => b_3(5), 93 | I2 => b_3(4), 94 | I3 => a_2(5), 95 | I4 => a_2(4), 96 | I5 => BU2_N01, 97 | O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result 98 | ); 99 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o107_SW0 : 100 | LUT4 101 | generic map( 102 | INIT => X"6FF6" 103 | ) 104 | port map ( 105 | I0 => a_2(0), 106 | I1 => b_3(0), 107 | I2 => a_2(3), 108 | I3 => b_3(3), 109 | O => BU2_N01 110 | ); 111 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85 : 112 | LUT4 113 | generic map( 114 | INIT => X"9009" 115 | ) 116 | port map ( 117 | I0 => a_2(1), 118 | I1 => b_3(1), 119 | I2 => a_2(2), 120 | I3 => b_3(2), 121 | O => 122 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16 123 | 124 | ); 125 | BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD 126 | generic map( 127 | INIT => '0' 128 | ) 129 | port map ( 130 | C => clk, 131 | D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result, 132 | Q => qa_eq_b 133 | ); 134 | BU2_XST_GND : GND 135 | port map ( 136 | G => BU2_a_ge_b 137 | ); 138 | 139 | end STRUCTURE; 140 | 141 | -- synthesis translate_on 142 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version K.39 4 | # Date: Mon Nov 30 13:23:03 2009 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = False 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = VHDL 21 | SET device = xc5vsx95t 22 | SET devicefamily = virtex5 23 | SET flowvendor = Other 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = ff1136 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -1 31 | SET verilogsim = False 32 | SET vhdlsim = True 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT Comparator family Xilinx,_Inc. 9.0 36 | # END Select 37 | # BEGIN Parameters 38 | CSET aclr=false 39 | CSET ainitval=0 40 | CSET aset=false 41 | CSET ce=false 42 | CSET cepriority=Sync_Overrides_CE 43 | CSET component_name=comp_6b_equal 44 | CSET constantbport=false 45 | CSET constantbportvalue=0000000000000000 46 | CSET datatype=Unsigned 47 | CSET nonregisteredoutput=false 48 | CSET operation=eq 49 | CSET pipelinestages=0 50 | CSET radix=2 51 | CSET registeredoutput=true 52 | CSET sclr=false 53 | CSET sset=false 54 | CSET syncctrlpriority=Reset_Overrides_Set 55 | CSET width=6 56 | # END Parameters 57 | GENERATE 58 | # CRC: 74b0a9bd 59 | 60 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.ngc: -------------------------------------------------------------------------------- 1 | XILINX-XDB 0.1 STUB 0.1 ASCII 2 | XILINX-XDM V1.4e 3 | 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36=;k1vo?50;0xZd?<58>1m45+6180g>{zfmn1<7?tH738ykbb290:wE8>;|lgb?6=:rB==6sae183>7}O>81vbh?50;0xL37vF91:ma1<72;qC:<5rnd794?4|@?;0qck9:181M063tdn;7>52zJ55>{im10;6?uG609~j`?=838pD;?4}ogb>5<5sA<:7p`jb;296~N192wein4?:3yK24=zfln1<7;|lg1?6=9rB==6sad783>4}O>81vbi950;3xL37{I42?xhc13:1=vF91:m`d<728qC:<5rne`94?7|@?;0qcjl:182M063twvqMNL{02;>c34j9h<8pNOBz2~DEV|uIJ -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. 3 | -------------------------------------------------------------------------------- 4 | -- ____ ____ 5 | -- / /\/ / 6 | -- /___/ \ / Vendor: Xilinx 7 | -- \ \ \/ Version: K.39 8 | -- \ \ Application: netgen 9 | -- / / Filename: dist_mem_64x8.vhd 10 | -- /___/ /\ Timestamp: Tue Dec 01 15:45:04 2009 11 | -- \ \ / \ 12 | -- \___\/\___\ 13 | -- 14 | -- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.vhd 15 | -- Device : 5vsx95tff1136-1 16 | -- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.ngc 17 | -- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.vhd 18 | -- # of Entities : 1 19 | -- Design Name : dist_mem_64x8 20 | -- Xilinx : C:\Xilinx\10.1\ISE 21 | -- 22 | -- Purpose: 23 | -- This VHDL netlist is a verification model and uses simulation 24 | -- primitives which may not represent the true implementation of the 25 | -- device, however the netlist is functionally correct and should not 26 | -- be modified. This file cannot be synthesized and should only be used 27 | -- with supported simulation tools. 28 | -- 29 | -- Reference: 30 | -- Development System Reference Guide, Chapter 23 31 | -- Synthesis and Simulation Design Guide, Chapter 6 32 | -- 33 | -------------------------------------------------------------------------------- 34 | 35 | 36 | -- synthesis translate_off 37 | library IEEE; 38 | use IEEE.STD_LOGIC_1164.ALL; 39 | library UNISIM; 40 | use UNISIM.VCOMPONENTS.ALL; 41 | use UNISIM.VPKG.ALL; 42 | 43 | entity dist_mem_64x8 is 44 | port ( 45 | clk : in STD_LOGIC := 'X'; 46 | a : in STD_LOGIC_VECTOR ( 5 downto 0 ); 47 | qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) 48 | ); 49 | end dist_mem_64x8; 50 | 51 | architecture STRUCTURE of dist_mem_64x8 is 52 | signal N0 : STD_LOGIC; 53 | signal N1 : STD_LOGIC; 54 | signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 ); 55 | signal qspo_3 : STD_LOGIC_VECTOR ( 7 downto 0 ); 56 | signal BU2_U0_gen_rom_rom_inst_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 ); 57 | signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 ); 58 | begin 59 | a_2(5) <= a(5); 60 | a_2(4) <= a(4); 61 | a_2(3) <= a(3); 62 | a_2(2) <= a(2); 63 | a_2(1) <= a(1); 64 | a_2(0) <= a(0); 65 | qspo(7) <= qspo_3(7); 66 | qspo(6) <= qspo_3(6); 67 | qspo(5) <= qspo_3(5); 68 | qspo(4) <= qspo_3(4); 69 | qspo(3) <= qspo_3(3); 70 | qspo(2) <= qspo_3(2); 71 | qspo(1) <= qspo_3(1); 72 | qspo(0) <= qspo_3(0); 73 | VCC_0 : VCC 74 | port map ( 75 | P => N1 76 | ); 77 | GND_1 : GND 78 | port map ( 79 | G => N0 80 | ); 81 | BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000111 : LUT6 82 | generic map( 83 | INIT => X"0000061400040604" 84 | ) 85 | port map ( 86 | I0 => a_2(2), 87 | I1 => a_2(3), 88 | I2 => a_2(5), 89 | I3 => a_2(1), 90 | I4 => a_2(4), 91 | I5 => a_2(0), 92 | O => BU2_U0_gen_rom_rom_inst_spo_int(1) 93 | ); 94 | BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000071 : LUT6 95 | generic map( 96 | INIT => X"2100210023022222" 97 | ) 98 | port map ( 99 | I0 => a_2(3), 100 | I1 => a_2(5), 101 | I2 => a_2(4), 102 | I3 => a_2(1), 103 | I4 => a_2(0), 104 | I5 => a_2(2), 105 | O => BU2_U0_gen_rom_rom_inst_spo_int(7) 106 | ); 107 | BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000041 : LUT6 108 | generic map( 109 | INIT => X"0204162600041726" 110 | ) 111 | port map ( 112 | I0 => a_2(2), 113 | I1 => a_2(3), 114 | I2 => a_2(5), 115 | I3 => a_2(1), 116 | I4 => a_2(4), 117 | I5 => a_2(0), 118 | O => BU2_U0_gen_rom_rom_inst_spo_int(4) 119 | ); 120 | BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000051 : LUT6 121 | generic map( 122 | INIT => X"2301030311110112" 123 | ) 124 | port map ( 125 | I0 => a_2(4), 126 | I1 => a_2(5), 127 | I2 => a_2(2), 128 | I3 => a_2(0), 129 | I4 => a_2(1), 130 | I5 => a_2(3), 131 | O => BU2_U0_gen_rom_rom_inst_spo_int(5) 132 | ); 133 | BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021 : LUT6 134 | generic map( 135 | INIT => X"0100057801014578" 136 | ) 137 | port map ( 138 | I0 => a_2(5), 139 | I1 => a_2(1), 140 | I2 => a_2(2), 141 | I3 => a_2(3), 142 | I4 => a_2(4), 143 | I5 => a_2(0), 144 | O => BU2_U0_gen_rom_rom_inst_spo_int(2) 145 | ); 146 | BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031 : LUT6 147 | generic map( 148 | INIT => X"090101020B0A0202" 149 | ) 150 | port map ( 151 | I0 => a_2(3), 152 | I1 => a_2(4), 153 | I2 => a_2(5), 154 | I3 => a_2(1), 155 | I4 => a_2(0), 156 | I5 => a_2(2), 157 | O => BU2_U0_gen_rom_rom_inst_spo_int(3) 158 | ); 159 | BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000061 : LUT6 160 | generic map( 161 | INIT => X"010701EF02460224" 162 | ) 163 | port map ( 164 | I0 => a_2(2), 165 | I1 => a_2(3), 166 | I2 => a_2(4), 167 | I3 => a_2(5), 168 | I4 => a_2(0), 169 | I5 => a_2(1), 170 | O => BU2_U0_gen_rom_rom_inst_spo_int(6) 171 | ); 172 | BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011 : LUT6 173 | generic map( 174 | INIT => X"1202020210347366" 175 | ) 176 | port map ( 177 | I0 => a_2(3), 178 | I1 => a_2(5), 179 | I2 => a_2(1), 180 | I3 => a_2(0), 181 | I4 => a_2(2), 182 | I5 => a_2(4), 183 | O => BU2_U0_gen_rom_rom_inst_spo_int(0) 184 | ); 185 | BU2_U0_gen_rom_rom_inst_qspo_int_7 : FD 186 | generic map( 187 | INIT => '0' 188 | ) 189 | port map ( 190 | C => clk, 191 | D => BU2_U0_gen_rom_rom_inst_spo_int(7), 192 | Q => qspo_3(7) 193 | ); 194 | BU2_U0_gen_rom_rom_inst_qspo_int_6 : FD 195 | generic map( 196 | INIT => '0' 197 | ) 198 | port map ( 199 | C => clk, 200 | D => BU2_U0_gen_rom_rom_inst_spo_int(6), 201 | Q => qspo_3(6) 202 | ); 203 | BU2_U0_gen_rom_rom_inst_qspo_int_5 : FD 204 | generic map( 205 | INIT => '0' 206 | ) 207 | port map ( 208 | C => clk, 209 | D => BU2_U0_gen_rom_rom_inst_spo_int(5), 210 | Q => qspo_3(5) 211 | ); 212 | BU2_U0_gen_rom_rom_inst_qspo_int_4 : FD 213 | generic map( 214 | INIT => '0' 215 | ) 216 | port map ( 217 | C => clk, 218 | D => BU2_U0_gen_rom_rom_inst_spo_int(4), 219 | Q => qspo_3(4) 220 | ); 221 | BU2_U0_gen_rom_rom_inst_qspo_int_3 : FD 222 | generic map( 223 | INIT => '0' 224 | ) 225 | port map ( 226 | C => clk, 227 | D => BU2_U0_gen_rom_rom_inst_spo_int(3), 228 | Q => qspo_3(3) 229 | ); 230 | BU2_U0_gen_rom_rom_inst_qspo_int_2 : FD 231 | generic map( 232 | INIT => '0' 233 | ) 234 | port map ( 235 | C => clk, 236 | D => BU2_U0_gen_rom_rom_inst_spo_int(2), 237 | Q => qspo_3(2) 238 | ); 239 | BU2_U0_gen_rom_rom_inst_qspo_int_1 : FD 240 | generic map( 241 | INIT => '0' 242 | ) 243 | port map ( 244 | C => clk, 245 | D => BU2_U0_gen_rom_rom_inst_spo_int(1), 246 | Q => qspo_3(1) 247 | ); 248 | BU2_U0_gen_rom_rom_inst_qspo_int_0 : FD 249 | generic map( 250 | INIT => '0' 251 | ) 252 | port map ( 253 | C => clk, 254 | D => BU2_U0_gen_rom_rom_inst_spo_int(0), 255 | Q => qspo_3(0) 256 | ); 257 | BU2_XST_GND : GND 258 | port map ( 259 | G => BU2_qdpo(0) 260 | ); 261 | 262 | end STRUCTURE; 263 | 264 | -- synthesis translate_on 265 | -------------------------------------------------------------------------------- /UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version K.39 4 | # Date: Tue Dec 01 14:45:04 2009 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # BEGIN Project Options 16 | SET addpads = False 17 | SET asysymbol = False 18 | SET busformat = BusFormatAngleBracketNotRipped 19 | SET createndf = False 20 | SET designentry = VHDL 21 | SET device = xc5vsx95t 22 | SET devicefamily = virtex5 23 | SET flowvendor = Other 24 | SET formalverification = False 25 | SET foundationsym = False 26 | SET implementationfiletype = Ngc 27 | SET package = ff1136 28 | SET removerpms = False 29 | SET simulationfiles = Structural 30 | SET speedgrade = -1 31 | SET verilogsim = False 32 | SET vhdlsim = True 33 | # END Project Options 34 | # BEGIN Select 35 | SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4 36 | # END Select 37 | # BEGIN Parameters 38 | CSET ce_overrides=ce_overrides_sync_controls 39 | CSET coefficient_file=C:/PHd_Projects/The_Felsenstein_CoProcessor/definition2_ipv4_lut.coe 40 | CSET common_output_ce=false 41 | CSET common_output_clk=false 42 | CSET component_name=dist_mem_64x8 43 | CSET data_width=8 44 | CSET default_data=0 45 | CSET default_data_radix=16 46 | CSET depth=64 47 | CSET dual_port_address=non_registered 48 | CSET dual_port_output_clock_enable=false 49 | CSET input_clock_enable=false 50 | CSET input_options=non_registered 51 | CSET memory_type=rom 52 | CSET output_options=registered 53 | CSET pipeline_stages=0 54 | CSET qualify_we_with_i_ce=false 55 | CSET reset_qdpo=false 56 | CSET reset_qspo=false 57 | CSET single_port_output_clock_enable=false 58 | CSET sync_reset_qdpo=false 59 | CSET sync_reset_qspo=false 60 | # END Parameters 61 | GENERATE 62 | # CRC: 87a11b99 63 | 64 | --------------------------------------------------------------------------------